2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
57 VkImageLayout dst_layout
,
60 const VkImageSubresourceRange
*range
,
61 VkImageAspectFlags pending_clears
);
63 const struct radv_dynamic_state default_dynamic_state
= {
76 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
81 .stencil_compare_mask
= {
85 .stencil_write_mask
= {
89 .stencil_reference
= {
96 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
97 const struct radv_dynamic_state
*src
)
99 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
100 uint32_t copy_mask
= src
->mask
;
101 uint32_t dest_mask
= 0;
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
106 dest
->viewport
.count
= src
->viewport
.count
;
107 dest
->scissor
.count
= src
->scissor
.count
;
108 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
110 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
111 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
112 src
->viewport
.count
* sizeof(VkViewport
))) {
113 typed_memcpy(dest
->viewport
.viewports
,
114 src
->viewport
.viewports
,
115 src
->viewport
.count
);
116 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
120 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
121 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
122 src
->scissor
.count
* sizeof(VkRect2D
))) {
123 typed_memcpy(dest
->scissor
.scissors
,
124 src
->scissor
.scissors
, src
->scissor
.count
);
125 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
129 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
130 if (dest
->line_width
!= src
->line_width
) {
131 dest
->line_width
= src
->line_width
;
132 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
136 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
137 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
138 sizeof(src
->depth_bias
))) {
139 dest
->depth_bias
= src
->depth_bias
;
140 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
144 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
145 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
146 sizeof(src
->blend_constants
))) {
147 typed_memcpy(dest
->blend_constants
,
148 src
->blend_constants
, 4);
149 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
153 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
154 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
155 sizeof(src
->depth_bounds
))) {
156 dest
->depth_bounds
= src
->depth_bounds
;
157 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
161 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
162 if (memcmp(&dest
->stencil_compare_mask
,
163 &src
->stencil_compare_mask
,
164 sizeof(src
->stencil_compare_mask
))) {
165 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
166 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
170 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
171 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
172 sizeof(src
->stencil_write_mask
))) {
173 dest
->stencil_write_mask
= src
->stencil_write_mask
;
174 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
178 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
179 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
180 sizeof(src
->stencil_reference
))) {
181 dest
->stencil_reference
= src
->stencil_reference
;
182 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
186 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
187 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
188 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
189 typed_memcpy(dest
->discard_rectangle
.rectangles
,
190 src
->discard_rectangle
.rectangles
,
191 src
->discard_rectangle
.count
);
192 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
196 cmd_buffer
->state
.dirty
|= dest_mask
;
200 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
201 struct radv_pipeline
*pipeline
)
203 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
204 struct radv_shader_info
*info
;
206 if (!pipeline
->streamout_shader
)
209 info
= &pipeline
->streamout_shader
->info
.info
;
210 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
211 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
213 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
216 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
218 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
219 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
222 enum ring_type
radv_queue_family_to_ring(int f
) {
224 case RADV_QUEUE_GENERAL
:
226 case RADV_QUEUE_COMPUTE
:
228 case RADV_QUEUE_TRANSFER
:
231 unreachable("Unknown queue family");
235 static VkResult
radv_create_cmd_buffer(
236 struct radv_device
* device
,
237 struct radv_cmd_pool
* pool
,
238 VkCommandBufferLevel level
,
239 VkCommandBuffer
* pCommandBuffer
)
241 struct radv_cmd_buffer
*cmd_buffer
;
243 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
244 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
245 if (cmd_buffer
== NULL
)
246 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
248 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
249 cmd_buffer
->device
= device
;
250 cmd_buffer
->pool
= pool
;
251 cmd_buffer
->level
= level
;
254 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
255 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
258 /* Init the pool_link so we can safely call list_del when we destroy
261 list_inithead(&cmd_buffer
->pool_link
);
262 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
265 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
267 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
268 if (!cmd_buffer
->cs
) {
269 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
270 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
273 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
275 list_inithead(&cmd_buffer
->upload
.list
);
281 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
283 list_del(&cmd_buffer
->pool_link
);
285 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
286 &cmd_buffer
->upload
.list
, list
) {
287 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
292 if (cmd_buffer
->upload
.upload_bo
)
293 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
294 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
296 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
297 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
299 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
303 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
306 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
308 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
309 &cmd_buffer
->upload
.list
, list
) {
310 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
315 cmd_buffer
->push_constant_stages
= 0;
316 cmd_buffer
->scratch_size_needed
= 0;
317 cmd_buffer
->compute_scratch_size_needed
= 0;
318 cmd_buffer
->esgs_ring_size_needed
= 0;
319 cmd_buffer
->gsvs_ring_size_needed
= 0;
320 cmd_buffer
->tess_rings_needed
= false;
321 cmd_buffer
->sample_positions_needed
= false;
323 if (cmd_buffer
->upload
.upload_bo
)
324 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
325 cmd_buffer
->upload
.upload_bo
);
326 cmd_buffer
->upload
.offset
= 0;
328 cmd_buffer
->record_result
= VK_SUCCESS
;
330 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
331 cmd_buffer
->descriptors
[i
].dirty
= 0;
332 cmd_buffer
->descriptors
[i
].valid
= 0;
333 cmd_buffer
->descriptors
[i
].push_dirty
= false;
336 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
337 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
338 unsigned eop_bug_offset
;
341 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 0,
342 &cmd_buffer
->gfx9_fence_offset
,
344 cmd_buffer
->gfx9_fence_bo
= cmd_buffer
->upload
.upload_bo
;
346 /* Allocate a buffer for the EOP bug on GFX9. */
347 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 0,
348 &eop_bug_offset
, &fence_ptr
);
349 cmd_buffer
->gfx9_eop_bug_va
=
350 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
351 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
354 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
356 return cmd_buffer
->record_result
;
360 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
364 struct radeon_winsys_bo
*bo
;
365 struct radv_cmd_buffer_upload
*upload
;
366 struct radv_device
*device
= cmd_buffer
->device
;
368 new_size
= MAX2(min_needed
, 16 * 1024);
369 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
371 bo
= device
->ws
->buffer_create(device
->ws
,
374 RADEON_FLAG_CPU_ACCESS
|
375 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
379 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
383 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
384 if (cmd_buffer
->upload
.upload_bo
) {
385 upload
= malloc(sizeof(*upload
));
388 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
389 device
->ws
->buffer_destroy(bo
);
393 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
394 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
397 cmd_buffer
->upload
.upload_bo
= bo
;
398 cmd_buffer
->upload
.size
= new_size
;
399 cmd_buffer
->upload
.offset
= 0;
400 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
402 if (!cmd_buffer
->upload
.map
) {
403 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
411 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
414 unsigned *out_offset
,
417 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
418 if (offset
+ size
> cmd_buffer
->upload
.size
) {
419 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
424 *out_offset
= offset
;
425 *ptr
= cmd_buffer
->upload
.map
+ offset
;
427 cmd_buffer
->upload
.offset
= offset
+ size
;
432 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
433 unsigned size
, unsigned alignment
,
434 const void *data
, unsigned *out_offset
)
438 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
439 out_offset
, (void **)&ptr
))
443 memcpy(ptr
, data
, size
);
449 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
450 unsigned count
, const uint32_t *data
)
452 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
454 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
456 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
457 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
458 S_370_WR_CONFIRM(1) |
459 S_370_ENGINE_SEL(V_370_ME
));
461 radeon_emit(cs
, va
>> 32);
462 radeon_emit_array(cs
, data
, count
);
465 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
467 struct radv_device
*device
= cmd_buffer
->device
;
468 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
471 va
= radv_buffer_get_va(device
->trace_bo
);
472 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
475 ++cmd_buffer
->state
.trace_id
;
476 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
477 &cmd_buffer
->state
.trace_id
);
479 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
481 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
482 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
486 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
487 enum radv_cmd_flush_bits flags
)
489 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
490 uint32_t *ptr
= NULL
;
493 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
494 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
496 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
497 va
= radv_buffer_get_va(cmd_buffer
->gfx9_fence_bo
) +
498 cmd_buffer
->gfx9_fence_offset
;
499 ptr
= &cmd_buffer
->gfx9_fence_idx
;
502 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
504 /* Force wait for graphics or compute engines to be idle. */
505 si_cs_emit_cache_flush(cmd_buffer
->cs
,
506 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
508 radv_cmd_buffer_uses_mec(cmd_buffer
),
509 flags
, cmd_buffer
->gfx9_eop_bug_va
);
512 if (unlikely(cmd_buffer
->device
->trace_bo
))
513 radv_cmd_buffer_trace_emit(cmd_buffer
);
517 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
518 struct radv_pipeline
*pipeline
, enum ring_type ring
)
520 struct radv_device
*device
= cmd_buffer
->device
;
524 va
= radv_buffer_get_va(device
->trace_bo
);
534 assert(!"invalid ring type");
537 data
[0] = (uintptr_t)pipeline
;
538 data
[1] = (uintptr_t)pipeline
>> 32;
540 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
543 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
544 VkPipelineBindPoint bind_point
,
545 struct radv_descriptor_set
*set
,
548 struct radv_descriptor_state
*descriptors_state
=
549 radv_get_descriptors_state(cmd_buffer
, bind_point
);
551 descriptors_state
->sets
[idx
] = set
;
553 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
554 descriptors_state
->dirty
|= (1u << idx
);
558 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
559 VkPipelineBindPoint bind_point
)
561 struct radv_descriptor_state
*descriptors_state
=
562 radv_get_descriptors_state(cmd_buffer
, bind_point
);
563 struct radv_device
*device
= cmd_buffer
->device
;
564 uint32_t data
[MAX_SETS
* 2] = {};
567 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
569 for_each_bit(i
, descriptors_state
->valid
) {
570 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
571 data
[i
* 2] = (uintptr_t)set
;
572 data
[i
* 2 + 1] = (uintptr_t)set
>> 32;
575 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
578 struct radv_userdata_info
*
579 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
580 gl_shader_stage stage
,
583 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
584 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
588 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
589 struct radv_pipeline
*pipeline
,
590 gl_shader_stage stage
,
591 int idx
, uint64_t va
)
593 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
594 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
595 if (loc
->sgpr_idx
== -1)
598 assert(loc
->num_sgprs
== (HAVE_32BIT_POINTERS
? 1 : 2));
599 assert(!loc
->indirect
);
601 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
602 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
606 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
607 struct radv_pipeline
*pipeline
,
608 struct radv_descriptor_state
*descriptors_state
,
609 gl_shader_stage stage
)
611 struct radv_device
*device
= cmd_buffer
->device
;
612 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
613 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
614 struct radv_userdata_locations
*locs
=
615 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
616 unsigned mask
= locs
->descriptor_sets_enabled
;
618 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
623 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
625 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
626 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
628 radv_emit_shader_pointer_head(cs
, sh_offset
, count
,
629 HAVE_32BIT_POINTERS
);
630 for (int i
= 0; i
< count
; i
++) {
631 struct radv_descriptor_set
*set
=
632 descriptors_state
->sets
[start
+ i
];
634 radv_emit_shader_pointer_body(device
, cs
, set
->va
,
635 HAVE_32BIT_POINTERS
);
641 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
642 struct radv_pipeline
*pipeline
)
644 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
645 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
646 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
648 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
)
649 cmd_buffer
->sample_positions_needed
= true;
651 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
654 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
655 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
656 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
658 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
660 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
662 /* GFX9: Flush DFSM when the AA mode changes. */
663 if (cmd_buffer
->device
->dfsm_allowed
) {
664 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
665 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
670 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
671 struct radv_shader_variant
*shader
)
678 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
680 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
684 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
685 struct radv_pipeline
*pipeline
,
686 bool vertex_stage_only
)
688 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
689 uint32_t mask
= state
->prefetch_L2_mask
;
691 if (vertex_stage_only
) {
692 /* Fast prefetch path for starting draws as soon as possible.
694 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
695 RADV_PREFETCH_VBO_DESCRIPTORS
);
698 if (mask
& RADV_PREFETCH_VS
)
699 radv_emit_shader_prefetch(cmd_buffer
,
700 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
702 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
703 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
705 if (mask
& RADV_PREFETCH_TCS
)
706 radv_emit_shader_prefetch(cmd_buffer
,
707 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
709 if (mask
& RADV_PREFETCH_TES
)
710 radv_emit_shader_prefetch(cmd_buffer
,
711 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
713 if (mask
& RADV_PREFETCH_GS
) {
714 radv_emit_shader_prefetch(cmd_buffer
,
715 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
716 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
719 if (mask
& RADV_PREFETCH_PS
)
720 radv_emit_shader_prefetch(cmd_buffer
,
721 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
723 state
->prefetch_L2_mask
&= ~mask
;
727 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
729 if (!cmd_buffer
->device
->physical_device
->rbplus_allowed
)
732 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
733 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
734 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
736 unsigned sx_ps_downconvert
= 0;
737 unsigned sx_blend_opt_epsilon
= 0;
738 unsigned sx_blend_opt_control
= 0;
740 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
741 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
742 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
743 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
747 int idx
= subpass
->color_attachments
[i
].attachment
;
748 struct radv_color_buffer_info
*cb
= &framebuffer
->attachments
[idx
].cb
;
750 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
751 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
752 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
753 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
755 bool has_alpha
, has_rgb
;
757 /* Set if RGB and A are present. */
758 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
760 if (format
== V_028C70_COLOR_8
||
761 format
== V_028C70_COLOR_16
||
762 format
== V_028C70_COLOR_32
)
763 has_rgb
= !has_alpha
;
767 /* Check the colormask and export format. */
768 if (!(colormask
& 0x7))
770 if (!(colormask
& 0x8))
773 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
778 /* Disable value checking for disabled channels. */
780 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
782 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
784 /* Enable down-conversion for 32bpp and smaller formats. */
786 case V_028C70_COLOR_8
:
787 case V_028C70_COLOR_8_8
:
788 case V_028C70_COLOR_8_8_8_8
:
789 /* For 1 and 2-channel formats, use the superset thereof. */
790 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
791 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
792 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
793 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
794 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
798 case V_028C70_COLOR_5_6_5
:
799 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
800 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
801 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
805 case V_028C70_COLOR_1_5_5_5
:
806 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
807 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
808 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
812 case V_028C70_COLOR_4_4_4_4
:
813 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
814 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
815 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
819 case V_028C70_COLOR_32
:
820 if (swap
== V_028C70_SWAP_STD
&&
821 spi_format
== V_028714_SPI_SHADER_32_R
)
822 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
823 else if (swap
== V_028C70_SWAP_ALT_REV
&&
824 spi_format
== V_028714_SPI_SHADER_32_AR
)
825 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
828 case V_028C70_COLOR_16
:
829 case V_028C70_COLOR_16_16
:
830 /* For 1-channel formats, use the superset thereof. */
831 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
832 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
833 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
834 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
835 if (swap
== V_028C70_SWAP_STD
||
836 swap
== V_028C70_SWAP_STD_REV
)
837 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
839 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
843 case V_028C70_COLOR_10_11_11
:
844 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
845 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
846 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
850 case V_028C70_COLOR_2_10_10_10
:
851 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
852 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
853 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
859 for (unsigned i
= subpass
->color_count
; i
< 8; ++i
) {
860 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
861 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
863 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
864 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
865 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
866 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
870 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
872 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
874 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
877 radv_update_multisample_state(cmd_buffer
, pipeline
);
879 cmd_buffer
->scratch_size_needed
=
880 MAX2(cmd_buffer
->scratch_size_needed
,
881 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
883 if (!cmd_buffer
->state
.emitted_pipeline
||
884 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
885 pipeline
->graphics
.can_use_guardband
)
886 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
888 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
890 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
891 if (!pipeline
->shaders
[i
])
894 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
895 pipeline
->shaders
[i
]->bo
);
898 if (radv_pipeline_has_gs(pipeline
))
899 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
900 pipeline
->gs_copy_shader
->bo
);
902 if (unlikely(cmd_buffer
->device
->trace_bo
))
903 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
905 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
907 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
911 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
913 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
914 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
918 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
920 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
922 si_write_scissors(cmd_buffer
->cs
, 0, count
,
923 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
924 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
925 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
929 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
931 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
934 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
935 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
936 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
937 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
938 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
939 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
940 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
945 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
947 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
949 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
950 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
954 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
956 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
958 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
959 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
963 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
965 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
967 radeon_set_context_reg_seq(cmd_buffer
->cs
,
968 R_028430_DB_STENCILREFMASK
, 2);
969 radeon_emit(cmd_buffer
->cs
,
970 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
971 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
972 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
973 S_028430_STENCILOPVAL(1));
974 radeon_emit(cmd_buffer
->cs
,
975 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
976 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
977 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
978 S_028434_STENCILOPVAL_BF(1));
982 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
984 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
986 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
987 fui(d
->depth_bounds
.min
));
988 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
989 fui(d
->depth_bounds
.max
));
993 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
995 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
996 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
997 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1000 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1001 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1002 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1003 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1004 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1005 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1006 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1010 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1012 struct radv_attachment_info
*att
,
1013 struct radv_image
*image
,
1014 VkImageLayout layout
)
1016 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
1017 struct radv_color_buffer_info
*cb
= &att
->cb
;
1018 uint32_t cb_color_info
= cb
->cb_color_info
;
1020 if (!radv_layout_dcc_compressed(image
, layout
,
1021 radv_image_queue_family_mask(image
,
1022 cmd_buffer
->queue_family_index
,
1023 cmd_buffer
->queue_family_index
))) {
1024 cb_color_info
&= C_028C70_DCC_ENABLE
;
1027 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1028 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1029 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1030 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1031 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1032 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1033 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1034 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1035 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1036 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1037 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1038 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1039 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1041 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1042 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1043 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1045 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1046 S_0287A0_EPITCH(att
->attachment
->image
->surface
.u
.gfx9
.surf
.epitch
));
1048 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1049 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1050 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1051 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1052 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1053 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1054 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1055 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1056 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1057 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1058 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1059 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1061 if (is_vi
) { /* DCC BASE */
1062 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1068 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1069 struct radv_ds_buffer_info
*ds
,
1070 struct radv_image
*image
, VkImageLayout layout
,
1071 bool requires_cond_write
)
1073 uint32_t db_z_info
= ds
->db_z_info
;
1074 uint32_t db_z_info_reg
;
1076 if (!radv_image_is_tc_compat_htile(image
))
1079 if (!radv_layout_has_htile(image
, layout
,
1080 radv_image_queue_family_mask(image
,
1081 cmd_buffer
->queue_family_index
,
1082 cmd_buffer
->queue_family_index
))) {
1083 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1086 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1088 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1089 db_z_info_reg
= R_028038_DB_Z_INFO
;
1091 db_z_info_reg
= R_028040_DB_Z_INFO
;
1094 /* When we don't know the last fast clear value we need to emit a
1095 * conditional packet, otherwise we can update DB_Z_INFO directly.
1097 if (requires_cond_write
) {
1098 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_WRITE
, 7, 0));
1100 const uint32_t write_space
= 0 << 8; /* register */
1101 const uint32_t poll_space
= 1 << 4; /* memory */
1102 const uint32_t function
= 3 << 0; /* equal to the reference */
1103 const uint32_t options
= write_space
| poll_space
| function
;
1104 radeon_emit(cmd_buffer
->cs
, options
);
1106 /* poll address - location of the depth clear value */
1107 uint64_t va
= radv_buffer_get_va(image
->bo
);
1108 va
+= image
->offset
+ image
->clear_value_offset
;
1110 /* In presence of stencil format, we have to adjust the base
1111 * address because the first value is the stencil clear value.
1113 if (vk_format_is_stencil(image
->vk_format
))
1116 radeon_emit(cmd_buffer
->cs
, va
);
1117 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1119 radeon_emit(cmd_buffer
->cs
, fui(0.0f
)); /* reference value */
1120 radeon_emit(cmd_buffer
->cs
, (uint32_t)-1); /* comparison mask */
1121 radeon_emit(cmd_buffer
->cs
, db_z_info_reg
>> 2); /* write address low */
1122 radeon_emit(cmd_buffer
->cs
, 0u); /* write address high */
1123 radeon_emit(cmd_buffer
->cs
, db_z_info
);
1125 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1130 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1131 struct radv_ds_buffer_info
*ds
,
1132 struct radv_image
*image
,
1133 VkImageLayout layout
)
1135 uint32_t db_z_info
= ds
->db_z_info
;
1136 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1138 if (!radv_layout_has_htile(image
, layout
,
1139 radv_image_queue_family_mask(image
,
1140 cmd_buffer
->queue_family_index
,
1141 cmd_buffer
->queue_family_index
))) {
1142 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1143 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1146 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1147 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1150 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1151 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1152 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1153 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1154 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1156 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1157 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1158 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1159 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1160 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1161 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1162 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1163 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1164 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1165 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1166 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1168 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1169 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1170 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1172 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1174 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1175 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1176 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1177 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1178 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1179 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1180 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1181 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1182 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1183 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1187 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1188 radv_update_zrange_precision(cmd_buffer
, ds
, image
, layout
, true);
1190 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1191 ds
->pa_su_poly_offset_db_fmt_cntl
);
1195 * Update the fast clear depth/stencil values if the image is bound as a
1196 * depth/stencil buffer.
1199 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1200 struct radv_image
*image
,
1201 VkClearDepthStencilValue ds_clear_value
,
1202 VkImageAspectFlags aspects
)
1204 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1205 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1206 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1207 struct radv_attachment_info
*att
;
1210 if (!framebuffer
|| !subpass
)
1213 att_idx
= subpass
->depth_stencil_attachment
.attachment
;
1214 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1217 att
= &framebuffer
->attachments
[att_idx
];
1218 if (att
->attachment
->image
!= image
)
1221 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1222 radeon_emit(cs
, ds_clear_value
.stencil
);
1223 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1225 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1226 * only needed when clearing Z to 0.0.
1228 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1229 ds_clear_value
.depth
== 0.0) {
1230 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1232 radv_update_zrange_precision(cmd_buffer
, &att
->ds
, image
,
1238 * Set the clear depth/stencil values to the image's metadata.
1241 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1242 struct radv_image
*image
,
1243 VkClearDepthStencilValue ds_clear_value
,
1244 VkImageAspectFlags aspects
)
1246 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1247 uint64_t va
= radv_buffer_get_va(image
->bo
);
1248 unsigned reg_offset
= 0, reg_count
= 0;
1250 va
+= image
->offset
+ image
->clear_value_offset
;
1252 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1258 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1261 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
1262 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1263 S_370_WR_CONFIRM(1) |
1264 S_370_ENGINE_SEL(V_370_PFP
));
1265 radeon_emit(cs
, va
);
1266 radeon_emit(cs
, va
>> 32);
1267 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1268 radeon_emit(cs
, ds_clear_value
.stencil
);
1269 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1270 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1274 * Update the clear depth/stencil values for this image.
1277 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1278 struct radv_image
*image
,
1279 VkClearDepthStencilValue ds_clear_value
,
1280 VkImageAspectFlags aspects
)
1282 assert(radv_image_has_htile(image
));
1284 radv_set_ds_clear_metadata(cmd_buffer
, image
, ds_clear_value
, aspects
);
1286 radv_update_bound_fast_clear_ds(cmd_buffer
, image
, ds_clear_value
,
1291 * Load the clear depth/stencil values from the image's metadata.
1294 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1295 struct radv_image
*image
)
1297 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1298 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1299 uint64_t va
= radv_buffer_get_va(image
->bo
);
1300 unsigned reg_offset
= 0, reg_count
= 0;
1302 va
+= image
->offset
+ image
->clear_value_offset
;
1304 if (!radv_image_has_htile(image
))
1307 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1313 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1316 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1317 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1318 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1319 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1320 radeon_emit(cs
, va
);
1321 radeon_emit(cs
, va
>> 32);
1322 radeon_emit(cs
, (R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
) >> 2);
1325 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1330 * With DCC some colors don't require CMASK elimination before being
1331 * used as a texture. This sets a predicate value to determine if the
1332 * cmask eliminate is required.
1335 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1336 struct radv_image
*image
,
1339 uint64_t pred_val
= value
;
1340 uint64_t va
= radv_buffer_get_va(image
->bo
);
1341 va
+= image
->offset
+ image
->dcc_pred_offset
;
1343 assert(radv_image_has_dcc(image
));
1345 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1346 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1347 S_370_WR_CONFIRM(1) |
1348 S_370_ENGINE_SEL(V_370_PFP
));
1349 radeon_emit(cmd_buffer
->cs
, va
);
1350 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1351 radeon_emit(cmd_buffer
->cs
, pred_val
);
1352 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1356 * Update the fast clear color values if the image is bound as a color buffer.
1359 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1360 struct radv_image
*image
,
1362 uint32_t color_values
[2])
1364 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1365 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1366 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1367 struct radv_attachment_info
*att
;
1370 if (!framebuffer
|| !subpass
)
1373 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1374 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1377 att
= &framebuffer
->attachments
[att_idx
];
1378 if (att
->attachment
->image
!= image
)
1381 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1382 radeon_emit(cs
, color_values
[0]);
1383 radeon_emit(cs
, color_values
[1]);
1387 * Set the clear color values to the image's metadata.
1390 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1391 struct radv_image
*image
,
1392 uint32_t color_values
[2])
1394 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1395 uint64_t va
= radv_buffer_get_va(image
->bo
);
1397 va
+= image
->offset
+ image
->clear_value_offset
;
1399 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1401 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1402 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1403 S_370_WR_CONFIRM(1) |
1404 S_370_ENGINE_SEL(V_370_PFP
));
1405 radeon_emit(cs
, va
);
1406 radeon_emit(cs
, va
>> 32);
1407 radeon_emit(cs
, color_values
[0]);
1408 radeon_emit(cs
, color_values
[1]);
1412 * Update the clear color values for this image.
1415 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1416 struct radv_image
*image
,
1418 uint32_t color_values
[2])
1420 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1422 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
1424 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1429 * Load the clear color values from the image's metadata.
1432 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1433 struct radv_image
*image
,
1436 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1437 uint64_t va
= radv_buffer_get_va(image
->bo
);
1439 va
+= image
->offset
+ image
->clear_value_offset
;
1441 if (!radv_image_has_cmask(image
) && !radv_image_has_dcc(image
))
1444 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1446 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1447 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1448 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1449 COPY_DATA_COUNT_SEL
);
1450 radeon_emit(cs
, va
);
1451 radeon_emit(cs
, va
>> 32);
1452 radeon_emit(cs
, reg
>> 2);
1455 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1460 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1463 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1464 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1466 /* this may happen for inherited secondary recording */
1470 for (i
= 0; i
< 8; ++i
) {
1471 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1472 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1473 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1477 int idx
= subpass
->color_attachments
[i
].attachment
;
1478 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1479 struct radv_image
*image
= att
->attachment
->image
;
1480 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
1482 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1484 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
1485 radv_emit_fb_color_state(cmd_buffer
, i
, att
, image
, layout
);
1487 radv_load_color_clear_metadata(cmd_buffer
, image
, i
);
1490 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1491 int idx
= subpass
->depth_stencil_attachment
.attachment
;
1492 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1493 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1494 struct radv_image
*image
= att
->attachment
->image
;
1495 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1496 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1497 cmd_buffer
->queue_family_index
,
1498 cmd_buffer
->queue_family_index
);
1499 /* We currently don't support writing decompressed HTILE */
1500 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1501 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1503 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1505 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1506 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1507 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1509 radv_load_ds_clear_metadata(cmd_buffer
, image
);
1511 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1512 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1514 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1516 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1517 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1519 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1520 S_028208_BR_X(framebuffer
->width
) |
1521 S_028208_BR_Y(framebuffer
->height
));
1523 if (cmd_buffer
->device
->dfsm_allowed
) {
1524 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1525 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1528 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
1532 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1534 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1535 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1537 if (state
->index_type
!= state
->last_index_type
) {
1538 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1539 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
1540 2, state
->index_type
);
1542 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1543 radeon_emit(cs
, state
->index_type
);
1546 state
->last_index_type
= state
->index_type
;
1549 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
1550 radeon_emit(cs
, state
->index_va
);
1551 radeon_emit(cs
, state
->index_va
>> 32);
1553 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1554 radeon_emit(cs
, state
->max_index_count
);
1556 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
1559 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1561 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
1562 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1563 uint32_t pa_sc_mode_cntl_1
=
1564 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
1565 uint32_t db_count_control
;
1567 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1568 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1569 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1570 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1571 has_perfect_queries
) {
1572 /* Re-enable out-of-order rasterization if the
1573 * bound pipeline supports it and if it's has
1574 * been disabled before starting any perfect
1575 * occlusion queries.
1577 radeon_set_context_reg(cmd_buffer
->cs
,
1578 R_028A4C_PA_SC_MODE_CNTL_1
,
1582 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1584 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1585 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
1587 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1589 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
1590 S_028004_SAMPLE_RATE(sample_rate
) |
1591 S_028004_ZPASS_ENABLE(1) |
1592 S_028004_SLICE_EVEN_ENABLE(1) |
1593 S_028004_SLICE_ODD_ENABLE(1);
1595 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1596 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1597 has_perfect_queries
) {
1598 /* If the bound pipeline has enabled
1599 * out-of-order rasterization, we should
1600 * disable it before starting any perfect
1601 * occlusion queries.
1603 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
1605 radeon_set_context_reg(cmd_buffer
->cs
,
1606 R_028A4C_PA_SC_MODE_CNTL_1
,
1610 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1611 S_028004_SAMPLE_RATE(sample_rate
);
1615 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1619 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1621 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
1623 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1624 radv_emit_viewport(cmd_buffer
);
1626 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
1627 !cmd_buffer
->device
->physical_device
->has_scissor_bug
)
1628 radv_emit_scissor(cmd_buffer
);
1630 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
1631 radv_emit_line_width(cmd_buffer
);
1633 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1634 radv_emit_blend_constants(cmd_buffer
);
1636 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1637 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1638 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
1639 radv_emit_stencil(cmd_buffer
);
1641 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
1642 radv_emit_depth_bounds(cmd_buffer
);
1644 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
1645 radv_emit_depth_bias(cmd_buffer
);
1647 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
1648 radv_emit_discard_rectangle(cmd_buffer
);
1650 cmd_buffer
->state
.dirty
&= ~states
;
1654 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1655 VkPipelineBindPoint bind_point
)
1657 struct radv_descriptor_state
*descriptors_state
=
1658 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1659 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
1662 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
1667 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1668 set
->va
+= bo_offset
;
1672 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
1673 VkPipelineBindPoint bind_point
)
1675 struct radv_descriptor_state
*descriptors_state
=
1676 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1677 uint8_t ptr_size
= HAVE_32BIT_POINTERS
? 1 : 2;
1678 uint32_t size
= MAX_SETS
* 4 * ptr_size
;
1682 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1683 256, &offset
, &ptr
))
1686 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1687 uint32_t *uptr
= ((uint32_t *)ptr
) + i
* ptr_size
;
1688 uint64_t set_va
= 0;
1689 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
1690 if (descriptors_state
->valid
& (1u << i
))
1692 uptr
[0] = set_va
& 0xffffffff;
1694 uptr
[1] = set_va
>> 32;
1697 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1700 if (cmd_buffer
->state
.pipeline
) {
1701 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1702 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1703 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1705 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1706 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1707 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1709 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1710 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1711 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1713 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1714 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1715 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1717 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1718 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1719 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1722 if (cmd_buffer
->state
.compute_pipeline
)
1723 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1724 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1728 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1729 VkShaderStageFlags stages
)
1731 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
1732 VK_PIPELINE_BIND_POINT_COMPUTE
:
1733 VK_PIPELINE_BIND_POINT_GRAPHICS
;
1734 struct radv_descriptor_state
*descriptors_state
=
1735 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1736 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1737 bool flush_indirect_descriptors
;
1739 if (!descriptors_state
->dirty
)
1742 if (descriptors_state
->push_dirty
)
1743 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
1745 flush_indirect_descriptors
=
1746 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
1747 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
1748 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
1749 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
1751 if (flush_indirect_descriptors
)
1752 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
1754 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1756 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1758 if (cmd_buffer
->state
.pipeline
) {
1759 radv_foreach_stage(stage
, stages
) {
1760 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
1763 radv_emit_descriptor_pointers(cmd_buffer
,
1764 cmd_buffer
->state
.pipeline
,
1765 descriptors_state
, stage
);
1769 if (cmd_buffer
->state
.compute_pipeline
&&
1770 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
1771 radv_emit_descriptor_pointers(cmd_buffer
,
1772 cmd_buffer
->state
.compute_pipeline
,
1774 MESA_SHADER_COMPUTE
);
1777 descriptors_state
->dirty
= 0;
1778 descriptors_state
->push_dirty
= false;
1780 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1782 if (unlikely(cmd_buffer
->device
->trace_bo
))
1783 radv_save_descriptors(cmd_buffer
, bind_point
);
1787 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1788 VkShaderStageFlags stages
)
1790 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
1791 ? cmd_buffer
->state
.compute_pipeline
1792 : cmd_buffer
->state
.pipeline
;
1793 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
1794 VK_PIPELINE_BIND_POINT_COMPUTE
:
1795 VK_PIPELINE_BIND_POINT_GRAPHICS
;
1796 struct radv_descriptor_state
*descriptors_state
=
1797 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1798 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1799 struct radv_shader_variant
*shader
, *prev_shader
;
1804 stages
&= cmd_buffer
->push_constant_stages
;
1806 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1809 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1810 16 * layout
->dynamic_offset_count
,
1811 256, &offset
, &ptr
))
1814 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1815 memcpy((char*)ptr
+ layout
->push_constant_size
,
1816 descriptors_state
->dynamic_buffers
,
1817 16 * layout
->dynamic_offset_count
);
1819 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1822 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1823 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1826 radv_foreach_stage(stage
, stages
) {
1827 shader
= radv_get_shader(pipeline
, stage
);
1829 /* Avoid redundantly emitting the address for merged stages. */
1830 if (shader
&& shader
!= prev_shader
) {
1831 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1832 AC_UD_PUSH_CONSTANTS
, va
);
1834 prev_shader
= shader
;
1838 cmd_buffer
->push_constant_stages
&= ~stages
;
1839 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1843 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1844 bool pipeline_is_dirty
)
1846 if ((pipeline_is_dirty
||
1847 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
1848 cmd_buffer
->state
.pipeline
->vertex_elements
.count
&&
1849 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.has_vertex_buffers
) {
1850 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
1854 uint32_t count
= velems
->count
;
1857 /* allocate some descriptor state for vertex buffers */
1858 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
1859 &vb_offset
, &vb_ptr
))
1862 for (i
= 0; i
< count
; i
++) {
1863 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
1865 int vb
= velems
->binding
[i
];
1866 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[vb
].buffer
;
1867 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
1869 va
= radv_buffer_get_va(buffer
->bo
);
1871 offset
= cmd_buffer
->vertex_bindings
[vb
].offset
+ velems
->offset
[i
];
1872 va
+= offset
+ buffer
->offset
;
1874 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
1875 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= CIK
&& stride
)
1876 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
1878 desc
[2] = buffer
->size
- offset
;
1879 desc
[3] = velems
->rsrc_word3
[i
];
1882 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1885 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1886 AC_UD_VS_VERTEX_BUFFERS
, va
);
1888 cmd_buffer
->state
.vb_va
= va
;
1889 cmd_buffer
->state
.vb_size
= count
* 16;
1890 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
1892 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
1896 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
1898 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1899 struct radv_userdata_info
*loc
;
1902 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
1903 if (!radv_get_shader(pipeline
, stage
))
1906 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
1907 AC_UD_STREAMOUT_BUFFERS
);
1908 if (loc
->sgpr_idx
== -1)
1911 base_reg
= pipeline
->user_data_0
[stage
];
1913 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
1914 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
1917 if (pipeline
->gs_copy_shader
) {
1918 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
1919 if (loc
->sgpr_idx
!= -1) {
1920 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
1922 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
1923 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
1929 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
1931 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
1932 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
1933 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
1938 /* Allocate some descriptor state for streamout buffers. */
1939 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
1940 MAX_SO_BUFFERS
* 16, 256,
1941 &so_offset
, &so_ptr
))
1944 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
1945 struct radv_buffer
*buffer
= sb
[i
].buffer
;
1946 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
1948 if (!(so
->enabled_mask
& (1 << i
)))
1951 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
1955 /* Set the descriptor.
1957 * On VI, the format must be non-INVALID, otherwise
1958 * the buffer will be considered not bound and store
1959 * instructions will be no-ops.
1962 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
1963 desc
[2] = 0xffffffff;
1964 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1965 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1966 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1967 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1968 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1971 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1974 radv_emit_streamout_buffers(cmd_buffer
, va
);
1977 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
1981 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
1983 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
1984 radv_flush_streamout_descriptors(cmd_buffer
);
1985 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
1986 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
1990 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
, bool indexed_draw
,
1991 bool instanced_draw
, bool indirect_draw
,
1992 uint32_t draw_vertex_count
)
1994 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
1995 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1996 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1997 uint32_t ia_multi_vgt_param
;
1998 int32_t primitive_reset_en
;
2001 ia_multi_vgt_param
=
2002 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
2003 indirect_draw
, draw_vertex_count
);
2005 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2006 if (info
->chip_class
>= GFX9
) {
2007 radeon_set_uconfig_reg_idx(cs
,
2008 R_030960_IA_MULTI_VGT_PARAM
,
2009 4, ia_multi_vgt_param
);
2010 } else if (info
->chip_class
>= CIK
) {
2011 radeon_set_context_reg_idx(cs
,
2012 R_028AA8_IA_MULTI_VGT_PARAM
,
2013 1, ia_multi_vgt_param
);
2015 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2016 ia_multi_vgt_param
);
2018 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
2021 /* Primitive restart. */
2022 primitive_reset_en
=
2023 indexed_draw
&& state
->pipeline
->graphics
.prim_restart_enable
;
2025 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
2026 state
->last_primitive_reset_en
= primitive_reset_en
;
2027 if (info
->chip_class
>= GFX9
) {
2028 radeon_set_uconfig_reg(cs
,
2029 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
2030 primitive_reset_en
);
2032 radeon_set_context_reg(cs
,
2033 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
2034 primitive_reset_en
);
2038 if (primitive_reset_en
) {
2039 uint32_t primitive_reset_index
=
2040 state
->index_type
? 0xffffffffu
: 0xffffu
;
2042 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
2043 radeon_set_context_reg(cs
,
2044 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
2045 primitive_reset_index
);
2046 state
->last_primitive_reset_index
= primitive_reset_index
;
2051 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
2052 VkPipelineStageFlags src_stage_mask
)
2054 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
2055 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2056 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2057 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2058 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
2061 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
2062 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
2063 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
2064 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
2065 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2066 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2067 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
2068 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2069 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2070 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
2071 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
2072 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
2073 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
2074 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
2075 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
2076 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
2077 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
2081 static enum radv_cmd_flush_bits
2082 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2083 VkAccessFlags src_flags
,
2084 struct radv_image
*image
)
2086 bool flush_CB_meta
= true, flush_DB_meta
= true;
2087 enum radv_cmd_flush_bits flush_bits
= 0;
2091 if (!radv_image_has_CB_metadata(image
))
2092 flush_CB_meta
= false;
2093 if (!radv_image_has_htile(image
))
2094 flush_DB_meta
= false;
2097 for_each_bit(b
, src_flags
) {
2098 switch ((VkAccessFlagBits
)(1 << b
)) {
2099 case VK_ACCESS_SHADER_WRITE_BIT
:
2100 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
2101 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2102 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2104 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2105 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2107 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2109 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2110 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2112 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2114 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2115 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2116 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2117 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2120 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2122 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2131 static enum radv_cmd_flush_bits
2132 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2133 VkAccessFlags dst_flags
,
2134 struct radv_image
*image
)
2136 bool flush_CB_meta
= true, flush_DB_meta
= true;
2137 enum radv_cmd_flush_bits flush_bits
= 0;
2138 bool flush_CB
= true, flush_DB
= true;
2139 bool image_is_coherent
= false;
2143 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
2148 if (!radv_image_has_CB_metadata(image
))
2149 flush_CB_meta
= false;
2150 if (!radv_image_has_htile(image
))
2151 flush_DB_meta
= false;
2153 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2154 if (image
->info
.samples
== 1 &&
2155 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
2156 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
2157 !vk_format_is_stencil(image
->vk_format
)) {
2158 /* Single-sample color and single-sample depth
2159 * (not stencil) are coherent with shaders on
2162 image_is_coherent
= true;
2167 for_each_bit(b
, dst_flags
) {
2168 switch ((VkAccessFlagBits
)(1 << b
)) {
2169 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2170 case VK_ACCESS_INDEX_READ_BIT
:
2171 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2173 case VK_ACCESS_UNIFORM_READ_BIT
:
2174 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
2176 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2177 case VK_ACCESS_TRANSFER_READ_BIT
:
2178 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2179 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
2180 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2182 case VK_ACCESS_SHADER_READ_BIT
:
2183 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
;
2185 if (!image_is_coherent
)
2186 flush_bits
|= RADV_CMD_FLAG_INV_GLOBAL_L2
;
2188 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2190 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2192 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2194 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2196 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2198 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2207 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2208 const struct radv_subpass_barrier
*barrier
)
2210 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2212 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2213 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2217 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2218 struct radv_subpass_attachment att
)
2220 unsigned idx
= att
.attachment
;
2221 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
2222 VkImageSubresourceRange range
;
2223 range
.aspectMask
= 0;
2224 range
.baseMipLevel
= view
->base_mip
;
2225 range
.levelCount
= 1;
2226 range
.baseArrayLayer
= view
->base_layer
;
2227 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2229 radv_handle_image_transition(cmd_buffer
,
2231 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2232 att
.layout
, 0, 0, &range
,
2233 cmd_buffer
->state
.attachments
[idx
].pending_clear_aspects
);
2235 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2241 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2242 const struct radv_subpass
*subpass
, bool transitions
)
2245 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
2247 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
2248 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
2249 radv_handle_subpass_image_transition(cmd_buffer
,
2250 subpass
->color_attachments
[i
]);
2253 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
2254 radv_handle_subpass_image_transition(cmd_buffer
,
2255 subpass
->input_attachments
[i
]);
2258 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
2259 radv_handle_subpass_image_transition(cmd_buffer
,
2260 subpass
->depth_stencil_attachment
);
2264 cmd_buffer
->state
.subpass
= subpass
;
2266 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2270 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
2271 struct radv_render_pass
*pass
,
2272 const VkRenderPassBeginInfo
*info
)
2274 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2276 if (pass
->attachment_count
== 0) {
2277 state
->attachments
= NULL
;
2281 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2282 pass
->attachment_count
*
2283 sizeof(state
->attachments
[0]),
2284 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2285 if (state
->attachments
== NULL
) {
2286 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2287 return cmd_buffer
->record_result
;
2290 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
2291 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
2292 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
2293 VkImageAspectFlags clear_aspects
= 0;
2295 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2296 /* color attachment */
2297 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2298 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
2301 /* depthstencil attachment */
2302 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2303 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2304 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
2305 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2306 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
2307 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2309 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2310 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2311 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2315 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
2316 state
->attachments
[i
].cleared_views
= 0;
2317 if (clear_aspects
&& info
) {
2318 assert(info
->clearValueCount
> i
);
2319 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
2322 state
->attachments
[i
].current_layout
= att
->initial_layout
;
2328 VkResult
radv_AllocateCommandBuffers(
2330 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
2331 VkCommandBuffer
*pCommandBuffers
)
2333 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2334 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
2336 VkResult result
= VK_SUCCESS
;
2339 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
2341 if (!list_empty(&pool
->free_cmd_buffers
)) {
2342 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
2344 list_del(&cmd_buffer
->pool_link
);
2345 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
2347 result
= radv_reset_cmd_buffer(cmd_buffer
);
2348 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2349 cmd_buffer
->level
= pAllocateInfo
->level
;
2351 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
2353 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
2354 &pCommandBuffers
[i
]);
2356 if (result
!= VK_SUCCESS
)
2360 if (result
!= VK_SUCCESS
) {
2361 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
2362 i
, pCommandBuffers
);
2364 /* From the Vulkan 1.0.66 spec:
2366 * "vkAllocateCommandBuffers can be used to create multiple
2367 * command buffers. If the creation of any of those command
2368 * buffers fails, the implementation must destroy all
2369 * successfully created command buffer objects from this
2370 * command, set all entries of the pCommandBuffers array to
2371 * NULL and return the error."
2373 memset(pCommandBuffers
, 0,
2374 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
2380 void radv_FreeCommandBuffers(
2382 VkCommandPool commandPool
,
2383 uint32_t commandBufferCount
,
2384 const VkCommandBuffer
*pCommandBuffers
)
2386 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2387 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
2390 if (cmd_buffer
->pool
) {
2391 list_del(&cmd_buffer
->pool_link
);
2392 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
2394 radv_cmd_buffer_destroy(cmd_buffer
);
2400 VkResult
radv_ResetCommandBuffer(
2401 VkCommandBuffer commandBuffer
,
2402 VkCommandBufferResetFlags flags
)
2404 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2405 return radv_reset_cmd_buffer(cmd_buffer
);
2408 VkResult
radv_BeginCommandBuffer(
2409 VkCommandBuffer commandBuffer
,
2410 const VkCommandBufferBeginInfo
*pBeginInfo
)
2412 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2413 VkResult result
= VK_SUCCESS
;
2415 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
2416 /* If the command buffer has already been resetted with
2417 * vkResetCommandBuffer, no need to do it again.
2419 result
= radv_reset_cmd_buffer(cmd_buffer
);
2420 if (result
!= VK_SUCCESS
)
2424 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
2425 cmd_buffer
->state
.last_primitive_reset_en
= -1;
2426 cmd_buffer
->state
.last_index_type
= -1;
2427 cmd_buffer
->state
.last_num_instances
= -1;
2428 cmd_buffer
->state
.last_vertex_offset
= -1;
2429 cmd_buffer
->state
.last_first_instance
= -1;
2430 cmd_buffer
->state
.predication_type
= -1;
2431 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
2433 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
2434 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
2435 assert(pBeginInfo
->pInheritanceInfo
);
2436 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
2437 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
2439 struct radv_subpass
*subpass
=
2440 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
2442 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
2443 if (result
!= VK_SUCCESS
)
2446 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
2449 if (unlikely(cmd_buffer
->device
->trace_bo
)) {
2450 struct radv_device
*device
= cmd_buffer
->device
;
2452 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
,
2455 radv_cmd_buffer_trace_emit(cmd_buffer
);
2458 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
2463 void radv_CmdBindVertexBuffers(
2464 VkCommandBuffer commandBuffer
,
2465 uint32_t firstBinding
,
2466 uint32_t bindingCount
,
2467 const VkBuffer
* pBuffers
,
2468 const VkDeviceSize
* pOffsets
)
2470 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2471 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
2472 bool changed
= false;
2474 /* We have to defer setting up vertex buffer since we need the buffer
2475 * stride from the pipeline. */
2477 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
2478 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2479 uint32_t idx
= firstBinding
+ i
;
2482 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
2483 vb
[idx
].offset
!= pOffsets
[i
])) {
2487 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2488 vb
[idx
].offset
= pOffsets
[i
];
2490 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2491 vb
[idx
].buffer
->bo
);
2495 /* No state changes. */
2499 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
2502 void radv_CmdBindIndexBuffer(
2503 VkCommandBuffer commandBuffer
,
2505 VkDeviceSize offset
,
2506 VkIndexType indexType
)
2508 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2509 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2511 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
2512 cmd_buffer
->state
.index_offset
== offset
&&
2513 cmd_buffer
->state
.index_type
== indexType
) {
2514 /* No state changes. */
2518 cmd_buffer
->state
.index_buffer
= index_buffer
;
2519 cmd_buffer
->state
.index_offset
= offset
;
2520 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2521 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
2522 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2524 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2525 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2526 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2527 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
2532 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2533 VkPipelineBindPoint bind_point
,
2534 struct radv_descriptor_set
*set
, unsigned idx
)
2536 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2538 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
2541 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2543 if (!cmd_buffer
->device
->use_global_bo_list
) {
2544 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2545 if (set
->descriptors
[j
])
2546 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
2550 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
2553 void radv_CmdBindDescriptorSets(
2554 VkCommandBuffer commandBuffer
,
2555 VkPipelineBindPoint pipelineBindPoint
,
2556 VkPipelineLayout _layout
,
2558 uint32_t descriptorSetCount
,
2559 const VkDescriptorSet
* pDescriptorSets
,
2560 uint32_t dynamicOffsetCount
,
2561 const uint32_t* pDynamicOffsets
)
2563 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2564 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2565 unsigned dyn_idx
= 0;
2567 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
2568 struct radv_descriptor_state
*descriptors_state
=
2569 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
2571 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2572 unsigned idx
= i
+ firstSet
;
2573 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2574 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
2576 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2577 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2578 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
2579 assert(dyn_idx
< dynamicOffsetCount
);
2581 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2582 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2584 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2585 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
2586 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2587 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2588 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2589 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2590 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2591 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2592 cmd_buffer
->push_constant_stages
|=
2593 set
->layout
->dynamic_shader_stages
;
2598 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2599 struct radv_descriptor_set
*set
,
2600 struct radv_descriptor_set_layout
*layout
,
2601 VkPipelineBindPoint bind_point
)
2603 struct radv_descriptor_state
*descriptors_state
=
2604 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2605 set
->size
= layout
->size
;
2606 set
->layout
= layout
;
2608 if (descriptors_state
->push_set
.capacity
< set
->size
) {
2609 size_t new_size
= MAX2(set
->size
, 1024);
2610 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
2611 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2613 free(set
->mapped_ptr
);
2614 set
->mapped_ptr
= malloc(new_size
);
2616 if (!set
->mapped_ptr
) {
2617 descriptors_state
->push_set
.capacity
= 0;
2618 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2622 descriptors_state
->push_set
.capacity
= new_size
;
2628 void radv_meta_push_descriptor_set(
2629 struct radv_cmd_buffer
* cmd_buffer
,
2630 VkPipelineBindPoint pipelineBindPoint
,
2631 VkPipelineLayout _layout
,
2633 uint32_t descriptorWriteCount
,
2634 const VkWriteDescriptorSet
* pDescriptorWrites
)
2636 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2637 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2641 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2643 push_set
->size
= layout
->set
[set
].layout
->size
;
2644 push_set
->layout
= layout
->set
[set
].layout
;
2646 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2648 (void**) &push_set
->mapped_ptr
))
2651 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2652 push_set
->va
+= bo_offset
;
2654 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2655 radv_descriptor_set_to_handle(push_set
),
2656 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2658 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
2661 void radv_CmdPushDescriptorSetKHR(
2662 VkCommandBuffer commandBuffer
,
2663 VkPipelineBindPoint pipelineBindPoint
,
2664 VkPipelineLayout _layout
,
2666 uint32_t descriptorWriteCount
,
2667 const VkWriteDescriptorSet
* pDescriptorWrites
)
2669 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2670 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2671 struct radv_descriptor_state
*descriptors_state
=
2672 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
2673 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
2675 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2677 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
2678 layout
->set
[set
].layout
,
2682 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2683 radv_descriptor_set_to_handle(push_set
),
2684 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2686 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
2687 descriptors_state
->push_dirty
= true;
2690 void radv_CmdPushDescriptorSetWithTemplateKHR(
2691 VkCommandBuffer commandBuffer
,
2692 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
2693 VkPipelineLayout _layout
,
2697 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2698 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2699 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
2700 struct radv_descriptor_state
*descriptors_state
=
2701 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
2702 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
2704 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2706 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
2707 layout
->set
[set
].layout
,
2711 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2712 descriptorUpdateTemplate
, pData
);
2714 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
2715 descriptors_state
->push_dirty
= true;
2718 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2719 VkPipelineLayout layout
,
2720 VkShaderStageFlags stageFlags
,
2723 const void* pValues
)
2725 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2726 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2727 cmd_buffer
->push_constant_stages
|= stageFlags
;
2730 VkResult
radv_EndCommandBuffer(
2731 VkCommandBuffer commandBuffer
)
2733 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2735 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
2736 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== SI
)
2737 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2738 si_emit_cache_flush(cmd_buffer
);
2741 /* Make sure CP DMA is idle at the end of IBs because the kernel
2742 * doesn't wait for it.
2744 si_cp_dma_wait_for_idle(cmd_buffer
);
2746 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
2748 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
2749 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2751 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
2753 return cmd_buffer
->record_result
;
2757 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2759 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2761 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2764 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2766 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
2767 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
2769 cmd_buffer
->compute_scratch_size_needed
=
2770 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2771 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2773 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2774 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
2776 if (unlikely(cmd_buffer
->device
->trace_bo
))
2777 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
2780 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
2781 VkPipelineBindPoint bind_point
)
2783 struct radv_descriptor_state
*descriptors_state
=
2784 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2786 descriptors_state
->dirty
|= descriptors_state
->valid
;
2789 void radv_CmdBindPipeline(
2790 VkCommandBuffer commandBuffer
,
2791 VkPipelineBindPoint pipelineBindPoint
,
2792 VkPipeline _pipeline
)
2794 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2795 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
2797 switch (pipelineBindPoint
) {
2798 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2799 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
2801 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
2803 cmd_buffer
->state
.compute_pipeline
= pipeline
;
2804 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2806 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2807 if (cmd_buffer
->state
.pipeline
== pipeline
)
2809 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
2811 cmd_buffer
->state
.pipeline
= pipeline
;
2815 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2816 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
2818 /* the new vertex shader might not have the same user regs */
2819 cmd_buffer
->state
.last_first_instance
= -1;
2820 cmd_buffer
->state
.last_vertex_offset
= -1;
2822 /* Prefetch all pipeline shaders at first draw time. */
2823 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
2825 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
2826 radv_bind_streamout_state(cmd_buffer
, pipeline
);
2828 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
2829 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
2830 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
2831 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
2833 if (radv_pipeline_has_tess(pipeline
))
2834 cmd_buffer
->tess_rings_needed
= true;
2837 assert(!"invalid bind point");
2842 void radv_CmdSetViewport(
2843 VkCommandBuffer commandBuffer
,
2844 uint32_t firstViewport
,
2845 uint32_t viewportCount
,
2846 const VkViewport
* pViewports
)
2848 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2849 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2850 MAYBE_UNUSED
const uint32_t total_count
= firstViewport
+ viewportCount
;
2852 assert(firstViewport
< MAX_VIEWPORTS
);
2853 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
2855 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
2856 viewportCount
* sizeof(*pViewports
));
2858 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2861 void radv_CmdSetScissor(
2862 VkCommandBuffer commandBuffer
,
2863 uint32_t firstScissor
,
2864 uint32_t scissorCount
,
2865 const VkRect2D
* pScissors
)
2867 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2868 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2869 MAYBE_UNUSED
const uint32_t total_count
= firstScissor
+ scissorCount
;
2871 assert(firstScissor
< MAX_SCISSORS
);
2872 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
2874 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
2875 scissorCount
* sizeof(*pScissors
));
2877 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2880 void radv_CmdSetLineWidth(
2881 VkCommandBuffer commandBuffer
,
2884 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2885 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
2886 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2889 void radv_CmdSetDepthBias(
2890 VkCommandBuffer commandBuffer
,
2891 float depthBiasConstantFactor
,
2892 float depthBiasClamp
,
2893 float depthBiasSlopeFactor
)
2895 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2897 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
2898 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
2899 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
2901 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2904 void radv_CmdSetBlendConstants(
2905 VkCommandBuffer commandBuffer
,
2906 const float blendConstants
[4])
2908 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2910 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
2911 blendConstants
, sizeof(float) * 4);
2913 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2916 void radv_CmdSetDepthBounds(
2917 VkCommandBuffer commandBuffer
,
2918 float minDepthBounds
,
2919 float maxDepthBounds
)
2921 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2923 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
2924 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
2926 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2929 void radv_CmdSetStencilCompareMask(
2930 VkCommandBuffer commandBuffer
,
2931 VkStencilFaceFlags faceMask
,
2932 uint32_t compareMask
)
2934 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2936 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2937 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2938 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2939 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2941 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2944 void radv_CmdSetStencilWriteMask(
2945 VkCommandBuffer commandBuffer
,
2946 VkStencilFaceFlags faceMask
,
2949 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2951 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2952 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2953 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2954 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2956 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2959 void radv_CmdSetStencilReference(
2960 VkCommandBuffer commandBuffer
,
2961 VkStencilFaceFlags faceMask
,
2964 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2966 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2967 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
2968 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2969 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
2971 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2974 void radv_CmdSetDiscardRectangleEXT(
2975 VkCommandBuffer commandBuffer
,
2976 uint32_t firstDiscardRectangle
,
2977 uint32_t discardRectangleCount
,
2978 const VkRect2D
* pDiscardRectangles
)
2980 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2981 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2982 MAYBE_UNUSED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
2984 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
2985 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
2987 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
2988 pDiscardRectangles
, discardRectangleCount
);
2990 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
2993 void radv_CmdExecuteCommands(
2994 VkCommandBuffer commandBuffer
,
2995 uint32_t commandBufferCount
,
2996 const VkCommandBuffer
* pCmdBuffers
)
2998 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
3000 assert(commandBufferCount
> 0);
3002 /* Emit pending flushes on primary prior to executing secondary */
3003 si_emit_cache_flush(primary
);
3005 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3006 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
3008 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
3009 secondary
->scratch_size_needed
);
3010 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
3011 secondary
->compute_scratch_size_needed
);
3013 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
3014 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
3015 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
3016 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
3017 if (secondary
->tess_rings_needed
)
3018 primary
->tess_rings_needed
= true;
3019 if (secondary
->sample_positions_needed
)
3020 primary
->sample_positions_needed
= true;
3022 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
3025 /* When the secondary command buffer is compute only we don't
3026 * need to re-emit the current graphics pipeline.
3028 if (secondary
->state
.emitted_pipeline
) {
3029 primary
->state
.emitted_pipeline
=
3030 secondary
->state
.emitted_pipeline
;
3033 /* When the secondary command buffer is graphics only we don't
3034 * need to re-emit the current compute pipeline.
3036 if (secondary
->state
.emitted_compute_pipeline
) {
3037 primary
->state
.emitted_compute_pipeline
=
3038 secondary
->state
.emitted_compute_pipeline
;
3041 /* Only re-emit the draw packets when needed. */
3042 if (secondary
->state
.last_primitive_reset_en
!= -1) {
3043 primary
->state
.last_primitive_reset_en
=
3044 secondary
->state
.last_primitive_reset_en
;
3047 if (secondary
->state
.last_primitive_reset_index
) {
3048 primary
->state
.last_primitive_reset_index
=
3049 secondary
->state
.last_primitive_reset_index
;
3052 if (secondary
->state
.last_ia_multi_vgt_param
) {
3053 primary
->state
.last_ia_multi_vgt_param
=
3054 secondary
->state
.last_ia_multi_vgt_param
;
3057 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
3058 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
3059 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
3061 if (secondary
->state
.last_index_type
!= -1) {
3062 primary
->state
.last_index_type
=
3063 secondary
->state
.last_index_type
;
3067 /* After executing commands from secondary buffers we have to dirty
3070 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
3071 RADV_CMD_DIRTY_INDEX_BUFFER
|
3072 RADV_CMD_DIRTY_DYNAMIC_ALL
;
3073 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
3074 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
3077 VkResult
radv_CreateCommandPool(
3079 const VkCommandPoolCreateInfo
* pCreateInfo
,
3080 const VkAllocationCallbacks
* pAllocator
,
3081 VkCommandPool
* pCmdPool
)
3083 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3084 struct radv_cmd_pool
*pool
;
3086 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
3087 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3089 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3092 pool
->alloc
= *pAllocator
;
3094 pool
->alloc
= device
->alloc
;
3096 list_inithead(&pool
->cmd_buffers
);
3097 list_inithead(&pool
->free_cmd_buffers
);
3099 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
3101 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
3107 void radv_DestroyCommandPool(
3109 VkCommandPool commandPool
,
3110 const VkAllocationCallbacks
* pAllocator
)
3112 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3113 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3118 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3119 &pool
->cmd_buffers
, pool_link
) {
3120 radv_cmd_buffer_destroy(cmd_buffer
);
3123 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3124 &pool
->free_cmd_buffers
, pool_link
) {
3125 radv_cmd_buffer_destroy(cmd_buffer
);
3128 vk_free2(&device
->alloc
, pAllocator
, pool
);
3131 VkResult
radv_ResetCommandPool(
3133 VkCommandPool commandPool
,
3134 VkCommandPoolResetFlags flags
)
3136 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3139 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
3140 &pool
->cmd_buffers
, pool_link
) {
3141 result
= radv_reset_cmd_buffer(cmd_buffer
);
3142 if (result
!= VK_SUCCESS
)
3149 void radv_TrimCommandPool(
3151 VkCommandPool commandPool
,
3152 VkCommandPoolTrimFlagsKHR flags
)
3154 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3159 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3160 &pool
->free_cmd_buffers
, pool_link
) {
3161 radv_cmd_buffer_destroy(cmd_buffer
);
3165 void radv_CmdBeginRenderPass(
3166 VkCommandBuffer commandBuffer
,
3167 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3168 VkSubpassContents contents
)
3170 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3171 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3172 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3174 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
3175 cmd_buffer
->cs
, 2048);
3176 MAYBE_UNUSED VkResult result
;
3178 cmd_buffer
->state
.framebuffer
= framebuffer
;
3179 cmd_buffer
->state
.pass
= pass
;
3180 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3182 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
3183 if (result
!= VK_SUCCESS
)
3186 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
3187 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3189 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3192 void radv_CmdBeginRenderPass2KHR(
3193 VkCommandBuffer commandBuffer
,
3194 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
3195 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
3197 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
3198 pSubpassBeginInfo
->contents
);
3201 void radv_CmdNextSubpass(
3202 VkCommandBuffer commandBuffer
,
3203 VkSubpassContents contents
)
3205 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3207 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3209 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3212 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
3213 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3216 void radv_CmdNextSubpass2KHR(
3217 VkCommandBuffer commandBuffer
,
3218 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
3219 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3221 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
3224 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
3226 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
3227 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
3228 if (!radv_get_shader(pipeline
, stage
))
3231 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
3232 if (loc
->sgpr_idx
== -1)
3234 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
3235 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3238 if (pipeline
->gs_copy_shader
) {
3239 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
3240 if (loc
->sgpr_idx
!= -1) {
3241 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3242 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3248 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3249 uint32_t vertex_count
,
3252 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
3253 radeon_emit(cmd_buffer
->cs
, vertex_count
);
3254 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
3255 S_0287F0_USE_OPAQUE(use_opaque
));
3259 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
3261 uint32_t index_count
)
3263 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
3264 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
3265 radeon_emit(cmd_buffer
->cs
, index_va
);
3266 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
3267 radeon_emit(cmd_buffer
->cs
, index_count
);
3268 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
3272 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3274 uint32_t draw_count
,
3278 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3279 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
3280 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
3281 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
;
3282 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
3283 bool predicating
= cmd_buffer
->state
.predicating
;
3286 /* just reset draw state for vertex data */
3287 cmd_buffer
->state
.last_first_instance
= -1;
3288 cmd_buffer
->state
.last_num_instances
= -1;
3289 cmd_buffer
->state
.last_vertex_offset
= -1;
3291 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
3292 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
3293 PKT3_DRAW_INDIRECT
, 3, predicating
));
3295 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3296 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3297 radeon_emit(cs
, di_src_sel
);
3299 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
3300 PKT3_DRAW_INDIRECT_MULTI
,
3303 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3304 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3305 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
3306 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
3307 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
3308 radeon_emit(cs
, draw_count
); /* count */
3309 radeon_emit(cs
, count_va
); /* count_addr */
3310 radeon_emit(cs
, count_va
>> 32);
3311 radeon_emit(cs
, stride
); /* stride */
3312 radeon_emit(cs
, di_src_sel
);
3316 struct radv_draw_info
{
3318 * Number of vertices.
3323 * Index of the first vertex.
3325 int32_t vertex_offset
;
3328 * First instance id.
3330 uint32_t first_instance
;
3333 * Number of instances.
3335 uint32_t instance_count
;
3338 * First index (indexed draws only).
3340 uint32_t first_index
;
3343 * Whether it's an indexed draw.
3348 * Indirect draw parameters resource.
3350 struct radv_buffer
*indirect
;
3351 uint64_t indirect_offset
;
3355 * Draw count parameters resource.
3357 struct radv_buffer
*count_buffer
;
3358 uint64_t count_buffer_offset
;
3361 * Stream output parameters resource.
3363 struct radv_buffer
*strmout_buffer
;
3364 uint64_t strmout_buffer_offset
;
3368 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
3369 const struct radv_draw_info
*info
)
3371 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3372 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3373 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3375 if (info
->strmout_buffer
) {
3376 uint64_t va
= radv_buffer_get_va(info
->strmout_buffer
->bo
);
3378 va
+= info
->strmout_buffer
->offset
+
3379 info
->strmout_buffer_offset
;
3381 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
3384 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3385 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
3386 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
3387 COPY_DATA_WR_CONFIRM
);
3388 radeon_emit(cs
, va
);
3389 radeon_emit(cs
, va
>> 32);
3390 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
3391 radeon_emit(cs
, 0); /* unused */
3393 radv_cs_add_buffer(ws
, cs
, info
->strmout_buffer
->bo
);
3396 if (info
->indirect
) {
3397 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3398 uint64_t count_va
= 0;
3400 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3402 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
3404 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
3406 radeon_emit(cs
, va
);
3407 radeon_emit(cs
, va
>> 32);
3409 if (info
->count_buffer
) {
3410 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
3411 count_va
+= info
->count_buffer
->offset
+
3412 info
->count_buffer_offset
;
3414 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
3417 if (!state
->subpass
->view_mask
) {
3418 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3425 for_each_bit(i
, state
->subpass
->view_mask
) {
3426 radv_emit_view_index(cmd_buffer
, i
);
3428 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3436 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
3438 if (info
->vertex_offset
!= state
->last_vertex_offset
||
3439 info
->first_instance
!= state
->last_first_instance
) {
3440 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
3441 state
->pipeline
->graphics
.vtx_emit_num
);
3443 radeon_emit(cs
, info
->vertex_offset
);
3444 radeon_emit(cs
, info
->first_instance
);
3445 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
3447 state
->last_first_instance
= info
->first_instance
;
3448 state
->last_vertex_offset
= info
->vertex_offset
;
3451 if (state
->last_num_instances
!= info
->instance_count
) {
3452 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
3453 radeon_emit(cs
, info
->instance_count
);
3454 state
->last_num_instances
= info
->instance_count
;
3457 if (info
->indexed
) {
3458 int index_size
= state
->index_type
? 4 : 2;
3461 index_va
= state
->index_va
;
3462 index_va
+= info
->first_index
* index_size
;
3464 if (!state
->subpass
->view_mask
) {
3465 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3470 for_each_bit(i
, state
->subpass
->view_mask
) {
3471 radv_emit_view_index(cmd_buffer
, i
);
3473 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3479 if (!state
->subpass
->view_mask
) {
3480 radv_cs_emit_draw_packet(cmd_buffer
,
3482 !!info
->strmout_buffer
);
3485 for_each_bit(i
, state
->subpass
->view_mask
) {
3486 radv_emit_view_index(cmd_buffer
, i
);
3488 radv_cs_emit_draw_packet(cmd_buffer
,
3490 !!info
->strmout_buffer
);
3498 * Vega and raven have a bug which triggers if there are multiple context
3499 * register contexts active at the same time with different scissor values.
3501 * There are two possible workarounds:
3502 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3503 * there is only ever 1 active set of scissor values at the same time.
3505 * 2) Whenever the hardware switches contexts we have to set the scissor
3506 * registers again even if it is a noop. That way the new context gets
3507 * the correct scissor values.
3509 * This implements option 2. radv_need_late_scissor_emission needs to
3510 * return true on affected HW if radv_emit_all_graphics_states sets
3511 * any context registers.
3513 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
3516 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3518 if (!cmd_buffer
->device
->physical_device
->has_scissor_bug
)
3521 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
3523 /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3524 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
| RADV_CMD_DIRTY_VERTEX_BUFFER
| RADV_CMD_DIRTY_PIPELINE
);
3526 /* Assume all state changes except these two can imply context rolls. */
3527 if (cmd_buffer
->state
.dirty
& used_states
)
3530 if (cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
3533 if (indexed_draw
&& state
->pipeline
->graphics
.prim_restart_enable
&&
3534 (state
->index_type
? 0xffffffffu
: 0xffffu
) != state
->last_primitive_reset_index
)
3541 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
3542 const struct radv_draw_info
*info
)
3544 bool late_scissor_emission
= radv_need_late_scissor_emission(cmd_buffer
, info
->indexed
);
3546 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
3547 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
3548 radv_emit_rbplus_state(cmd_buffer
);
3550 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
3551 radv_emit_graphics_pipeline(cmd_buffer
);
3553 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
3554 radv_emit_framebuffer_state(cmd_buffer
);
3556 if (info
->indexed
) {
3557 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
3558 radv_emit_index_buffer(cmd_buffer
);
3560 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3561 * so the state must be re-emitted before the next indexed
3564 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3565 cmd_buffer
->state
.last_index_type
= -1;
3566 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3570 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
3572 radv_emit_draw_registers(cmd_buffer
, info
->indexed
,
3573 info
->instance_count
> 1, info
->indirect
,
3574 info
->indirect
? 0 : info
->count
);
3576 if (late_scissor_emission
)
3577 radv_emit_scissor(cmd_buffer
);
3581 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
3582 const struct radv_draw_info
*info
)
3584 struct radeon_info
*rad_info
=
3585 &cmd_buffer
->device
->physical_device
->rad_info
;
3587 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
3588 bool pipeline_is_dirty
=
3589 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
3590 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
3592 MAYBE_UNUSED
unsigned cdw_max
=
3593 radeon_check_space(cmd_buffer
->device
->ws
,
3594 cmd_buffer
->cs
, 4096);
3596 /* Use optimal packet order based on whether we need to sync the
3599 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3600 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3601 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
3602 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
3603 /* If we have to wait for idle, set all states first, so that
3604 * all SET packets are processed in parallel with previous draw
3605 * calls. Then upload descriptors, set shader pointers, and
3606 * draw, and prefetch at the end. This ensures that the time
3607 * the CUs are idle is very short. (there are only SET_SH
3608 * packets between the wait and the draw)
3610 radv_emit_all_graphics_states(cmd_buffer
, info
);
3611 si_emit_cache_flush(cmd_buffer
);
3612 /* <-- CUs are idle here --> */
3614 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
3616 radv_emit_draw_packets(cmd_buffer
, info
);
3617 /* <-- CUs are busy here --> */
3619 /* Start prefetches after the draw has been started. Both will
3620 * run in parallel, but starting the draw first is more
3623 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3624 radv_emit_prefetch_L2(cmd_buffer
,
3625 cmd_buffer
->state
.pipeline
, false);
3628 /* If we don't wait for idle, start prefetches first, then set
3629 * states, and draw at the end.
3631 si_emit_cache_flush(cmd_buffer
);
3633 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3634 /* Only prefetch the vertex shader and VBO descriptors
3635 * in order to start the draw as soon as possible.
3637 radv_emit_prefetch_L2(cmd_buffer
,
3638 cmd_buffer
->state
.pipeline
, true);
3641 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
3643 radv_emit_all_graphics_states(cmd_buffer
, info
);
3644 radv_emit_draw_packets(cmd_buffer
, info
);
3646 /* Prefetch the remaining shaders after the draw has been
3649 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3650 radv_emit_prefetch_L2(cmd_buffer
,
3651 cmd_buffer
->state
.pipeline
, false);
3655 /* Workaround for a VGT hang when streamout is enabled.
3656 * It must be done after drawing.
3658 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
3659 (rad_info
->family
== CHIP_HAWAII
||
3660 rad_info
->family
== CHIP_TONGA
||
3661 rad_info
->family
== CHIP_FIJI
)) {
3662 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
3665 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3666 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
3670 VkCommandBuffer commandBuffer
,
3671 uint32_t vertexCount
,
3672 uint32_t instanceCount
,
3673 uint32_t firstVertex
,
3674 uint32_t firstInstance
)
3676 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3677 struct radv_draw_info info
= {};
3679 info
.count
= vertexCount
;
3680 info
.instance_count
= instanceCount
;
3681 info
.first_instance
= firstInstance
;
3682 info
.vertex_offset
= firstVertex
;
3684 radv_draw(cmd_buffer
, &info
);
3687 void radv_CmdDrawIndexed(
3688 VkCommandBuffer commandBuffer
,
3689 uint32_t indexCount
,
3690 uint32_t instanceCount
,
3691 uint32_t firstIndex
,
3692 int32_t vertexOffset
,
3693 uint32_t firstInstance
)
3695 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3696 struct radv_draw_info info
= {};
3698 info
.indexed
= true;
3699 info
.count
= indexCount
;
3700 info
.instance_count
= instanceCount
;
3701 info
.first_index
= firstIndex
;
3702 info
.vertex_offset
= vertexOffset
;
3703 info
.first_instance
= firstInstance
;
3705 radv_draw(cmd_buffer
, &info
);
3708 void radv_CmdDrawIndirect(
3709 VkCommandBuffer commandBuffer
,
3711 VkDeviceSize offset
,
3715 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3716 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3717 struct radv_draw_info info
= {};
3719 info
.count
= drawCount
;
3720 info
.indirect
= buffer
;
3721 info
.indirect_offset
= offset
;
3722 info
.stride
= stride
;
3724 radv_draw(cmd_buffer
, &info
);
3727 void radv_CmdDrawIndexedIndirect(
3728 VkCommandBuffer commandBuffer
,
3730 VkDeviceSize offset
,
3734 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3735 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3736 struct radv_draw_info info
= {};
3738 info
.indexed
= true;
3739 info
.count
= drawCount
;
3740 info
.indirect
= buffer
;
3741 info
.indirect_offset
= offset
;
3742 info
.stride
= stride
;
3744 radv_draw(cmd_buffer
, &info
);
3747 void radv_CmdDrawIndirectCountAMD(
3748 VkCommandBuffer commandBuffer
,
3750 VkDeviceSize offset
,
3751 VkBuffer _countBuffer
,
3752 VkDeviceSize countBufferOffset
,
3753 uint32_t maxDrawCount
,
3756 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3757 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3758 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3759 struct radv_draw_info info
= {};
3761 info
.count
= maxDrawCount
;
3762 info
.indirect
= buffer
;
3763 info
.indirect_offset
= offset
;
3764 info
.count_buffer
= count_buffer
;
3765 info
.count_buffer_offset
= countBufferOffset
;
3766 info
.stride
= stride
;
3768 radv_draw(cmd_buffer
, &info
);
3771 void radv_CmdDrawIndexedIndirectCountAMD(
3772 VkCommandBuffer commandBuffer
,
3774 VkDeviceSize offset
,
3775 VkBuffer _countBuffer
,
3776 VkDeviceSize countBufferOffset
,
3777 uint32_t maxDrawCount
,
3780 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3781 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3782 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3783 struct radv_draw_info info
= {};
3785 info
.indexed
= true;
3786 info
.count
= maxDrawCount
;
3787 info
.indirect
= buffer
;
3788 info
.indirect_offset
= offset
;
3789 info
.count_buffer
= count_buffer
;
3790 info
.count_buffer_offset
= countBufferOffset
;
3791 info
.stride
= stride
;
3793 radv_draw(cmd_buffer
, &info
);
3796 void radv_CmdDrawIndirectCountKHR(
3797 VkCommandBuffer commandBuffer
,
3799 VkDeviceSize offset
,
3800 VkBuffer _countBuffer
,
3801 VkDeviceSize countBufferOffset
,
3802 uint32_t maxDrawCount
,
3805 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3806 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3807 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3808 struct radv_draw_info info
= {};
3810 info
.count
= maxDrawCount
;
3811 info
.indirect
= buffer
;
3812 info
.indirect_offset
= offset
;
3813 info
.count_buffer
= count_buffer
;
3814 info
.count_buffer_offset
= countBufferOffset
;
3815 info
.stride
= stride
;
3817 radv_draw(cmd_buffer
, &info
);
3820 void radv_CmdDrawIndexedIndirectCountKHR(
3821 VkCommandBuffer commandBuffer
,
3823 VkDeviceSize offset
,
3824 VkBuffer _countBuffer
,
3825 VkDeviceSize countBufferOffset
,
3826 uint32_t maxDrawCount
,
3829 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3830 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3831 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3832 struct radv_draw_info info
= {};
3834 info
.indexed
= true;
3835 info
.count
= maxDrawCount
;
3836 info
.indirect
= buffer
;
3837 info
.indirect_offset
= offset
;
3838 info
.count_buffer
= count_buffer
;
3839 info
.count_buffer_offset
= countBufferOffset
;
3840 info
.stride
= stride
;
3842 radv_draw(cmd_buffer
, &info
);
3845 struct radv_dispatch_info
{
3847 * Determine the layout of the grid (in block units) to be used.
3852 * A starting offset for the grid. If unaligned is set, the offset
3853 * must still be aligned.
3855 uint32_t offsets
[3];
3857 * Whether it's an unaligned compute dispatch.
3862 * Indirect compute parameters resource.
3864 struct radv_buffer
*indirect
;
3865 uint64_t indirect_offset
;
3869 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
3870 const struct radv_dispatch_info
*info
)
3872 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3873 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3874 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
3875 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3876 bool predicating
= cmd_buffer
->state
.predicating
;
3877 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3878 struct radv_userdata_info
*loc
;
3880 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
3881 AC_UD_CS_GRID_SIZE
);
3883 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
3885 if (info
->indirect
) {
3886 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3888 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3890 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
3892 if (loc
->sgpr_idx
!= -1) {
3893 for (unsigned i
= 0; i
< 3; ++i
) {
3894 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3895 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
3896 COPY_DATA_DST_SEL(COPY_DATA_REG
));
3897 radeon_emit(cs
, (va
+ 4 * i
));
3898 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
3899 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
3900 + loc
->sgpr_idx
* 4) >> 2) + i
);
3905 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
3906 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
3907 PKT3_SHADER_TYPE_S(1));
3908 radeon_emit(cs
, va
);
3909 radeon_emit(cs
, va
>> 32);
3910 radeon_emit(cs
, dispatch_initiator
);
3912 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
3913 PKT3_SHADER_TYPE_S(1));
3915 radeon_emit(cs
, va
);
3916 radeon_emit(cs
, va
>> 32);
3918 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
3919 PKT3_SHADER_TYPE_S(1));
3921 radeon_emit(cs
, dispatch_initiator
);
3924 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
3925 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
3927 if (info
->unaligned
) {
3928 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
3929 unsigned remainder
[3];
3931 /* If aligned, these should be an entire block size,
3934 remainder
[0] = blocks
[0] + cs_block_size
[0] -
3935 align_u32_npot(blocks
[0], cs_block_size
[0]);
3936 remainder
[1] = blocks
[1] + cs_block_size
[1] -
3937 align_u32_npot(blocks
[1], cs_block_size
[1]);
3938 remainder
[2] = blocks
[2] + cs_block_size
[2] -
3939 align_u32_npot(blocks
[2], cs_block_size
[2]);
3941 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
3942 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
3943 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
3945 for(unsigned i
= 0; i
< 3; ++i
) {
3946 assert(offsets
[i
] % cs_block_size
[i
] == 0);
3947 offsets
[i
] /= cs_block_size
[i
];
3950 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3952 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
3953 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
3955 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
3956 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
3958 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
3959 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
3961 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
3964 if (loc
->sgpr_idx
!= -1) {
3965 assert(!loc
->indirect
);
3966 assert(loc
->num_sgprs
== 3);
3968 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
3969 loc
->sgpr_idx
* 4, 3);
3970 radeon_emit(cs
, blocks
[0]);
3971 radeon_emit(cs
, blocks
[1]);
3972 radeon_emit(cs
, blocks
[2]);
3975 if (offsets
[0] || offsets
[1] || offsets
[2]) {
3976 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
3977 radeon_emit(cs
, offsets
[0]);
3978 radeon_emit(cs
, offsets
[1]);
3979 radeon_emit(cs
, offsets
[2]);
3981 /* The blocks in the packet are not counts but end values. */
3982 for (unsigned i
= 0; i
< 3; ++i
)
3983 blocks
[i
] += offsets
[i
];
3985 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
3988 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
3989 PKT3_SHADER_TYPE_S(1));
3990 radeon_emit(cs
, blocks
[0]);
3991 radeon_emit(cs
, blocks
[1]);
3992 radeon_emit(cs
, blocks
[2]);
3993 radeon_emit(cs
, dispatch_initiator
);
3996 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4000 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
4002 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4003 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4007 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
4008 const struct radv_dispatch_info
*info
)
4010 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4012 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
4013 bool pipeline_is_dirty
= pipeline
&&
4014 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
4016 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4017 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4018 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4019 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4020 /* If we have to wait for idle, set all states first, so that
4021 * all SET packets are processed in parallel with previous draw
4022 * calls. Then upload descriptors, set shader pointers, and
4023 * dispatch, and prefetch at the end. This ensures that the
4024 * time the CUs are idle is very short. (there are only SET_SH
4025 * packets between the wait and the draw)
4027 radv_emit_compute_pipeline(cmd_buffer
);
4028 si_emit_cache_flush(cmd_buffer
);
4029 /* <-- CUs are idle here --> */
4031 radv_upload_compute_shader_descriptors(cmd_buffer
);
4033 radv_emit_dispatch_packets(cmd_buffer
, info
);
4034 /* <-- CUs are busy here --> */
4036 /* Start prefetches after the dispatch has been started. Both
4037 * will run in parallel, but starting the dispatch first is
4040 if (has_prefetch
&& pipeline_is_dirty
) {
4041 radv_emit_shader_prefetch(cmd_buffer
,
4042 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4045 /* If we don't wait for idle, start prefetches first, then set
4046 * states, and dispatch at the end.
4048 si_emit_cache_flush(cmd_buffer
);
4050 if (has_prefetch
&& pipeline_is_dirty
) {
4051 radv_emit_shader_prefetch(cmd_buffer
,
4052 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4055 radv_upload_compute_shader_descriptors(cmd_buffer
);
4057 radv_emit_compute_pipeline(cmd_buffer
);
4058 radv_emit_dispatch_packets(cmd_buffer
, info
);
4061 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
4064 void radv_CmdDispatchBase(
4065 VkCommandBuffer commandBuffer
,
4073 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4074 struct radv_dispatch_info info
= {};
4080 info
.offsets
[0] = base_x
;
4081 info
.offsets
[1] = base_y
;
4082 info
.offsets
[2] = base_z
;
4083 radv_dispatch(cmd_buffer
, &info
);
4086 void radv_CmdDispatch(
4087 VkCommandBuffer commandBuffer
,
4092 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
4095 void radv_CmdDispatchIndirect(
4096 VkCommandBuffer commandBuffer
,
4098 VkDeviceSize offset
)
4100 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4101 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4102 struct radv_dispatch_info info
= {};
4104 info
.indirect
= buffer
;
4105 info
.indirect_offset
= offset
;
4107 radv_dispatch(cmd_buffer
, &info
);
4110 void radv_unaligned_dispatch(
4111 struct radv_cmd_buffer
*cmd_buffer
,
4116 struct radv_dispatch_info info
= {};
4123 radv_dispatch(cmd_buffer
, &info
);
4126 void radv_CmdEndRenderPass(
4127 VkCommandBuffer commandBuffer
)
4129 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4131 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
4133 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
4135 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
4136 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
4137 radv_handle_subpass_image_transition(cmd_buffer
,
4138 (struct radv_subpass_attachment
){i
, layout
});
4141 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
4143 cmd_buffer
->state
.pass
= NULL
;
4144 cmd_buffer
->state
.subpass
= NULL
;
4145 cmd_buffer
->state
.attachments
= NULL
;
4146 cmd_buffer
->state
.framebuffer
= NULL
;
4149 void radv_CmdEndRenderPass2KHR(
4150 VkCommandBuffer commandBuffer
,
4151 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4153 radv_CmdEndRenderPass(commandBuffer
);
4157 * For HTILE we have the following interesting clear words:
4158 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4159 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4160 * 0xfffffff0: Clear depth to 1.0
4161 * 0x00000000: Clear depth to 0.0
4163 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
4164 struct radv_image
*image
,
4165 const VkImageSubresourceRange
*range
,
4166 uint32_t clear_word
)
4168 assert(range
->baseMipLevel
== 0);
4169 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
4170 unsigned layer_count
= radv_get_layerCount(image
, range
);
4171 uint64_t size
= image
->surface
.htile_slice_size
* layer_count
;
4172 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4173 uint64_t offset
= image
->offset
+ image
->htile_offset
+
4174 image
->surface
.htile_slice_size
* range
->baseArrayLayer
;
4175 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4176 VkClearDepthStencilValue value
= {};
4178 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4179 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4181 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
, offset
,
4184 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4186 if (vk_format_is_stencil(image
->vk_format
))
4187 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
4189 radv_set_ds_clear_metadata(cmd_buffer
, image
, value
, aspects
);
4192 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4193 struct radv_image
*image
,
4194 VkImageLayout src_layout
,
4195 VkImageLayout dst_layout
,
4196 unsigned src_queue_mask
,
4197 unsigned dst_queue_mask
,
4198 const VkImageSubresourceRange
*range
,
4199 VkImageAspectFlags pending_clears
)
4201 if (!radv_image_has_htile(image
))
4204 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
4205 radv_layout_has_htile(image
, dst_layout
, dst_queue_mask
)) {
4206 /* TODO: merge with the clear if applicable */
4207 radv_initialize_htile(cmd_buffer
, image
, range
, 0);
4208 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4209 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4210 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
4211 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
4212 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4213 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4214 VkImageSubresourceRange local_range
= *range
;
4215 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4216 local_range
.baseMipLevel
= 0;
4217 local_range
.levelCount
= 1;
4219 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4220 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4222 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
4224 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4225 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4229 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
4230 struct radv_image
*image
, uint32_t value
)
4232 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4234 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4235 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4237 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, value
);
4239 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4242 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
4243 struct radv_image
*image
, uint32_t value
)
4245 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4247 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4248 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4250 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, value
);
4252 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4253 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4257 * Initialize DCC/FMASK/CMASK metadata for a color image.
4259 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
4260 struct radv_image
*image
,
4261 VkImageLayout src_layout
,
4262 VkImageLayout dst_layout
,
4263 unsigned src_queue_mask
,
4264 unsigned dst_queue_mask
)
4266 if (radv_image_has_cmask(image
)) {
4267 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4269 /* TODO: clarify this. */
4270 if (radv_image_has_fmask(image
)) {
4271 value
= 0xccccccccu
;
4274 radv_initialise_cmask(cmd_buffer
, image
, value
);
4277 if (radv_image_has_dcc(image
)) {
4278 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4279 bool need_decompress_pass
= false;
4281 if (radv_layout_dcc_compressed(image
, dst_layout
,
4283 value
= 0x20202020u
;
4284 need_decompress_pass
= true;
4287 radv_initialize_dcc(cmd_buffer
, image
, value
);
4289 radv_set_dcc_need_cmask_elim_pred(cmd_buffer
, image
,
4290 need_decompress_pass
);
4293 if (radv_image_has_cmask(image
) || radv_image_has_dcc(image
)) {
4294 uint32_t color_values
[2] = {};
4295 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
4300 * Handle color image transitions for DCC/FMASK/CMASK.
4302 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4303 struct radv_image
*image
,
4304 VkImageLayout src_layout
,
4305 VkImageLayout dst_layout
,
4306 unsigned src_queue_mask
,
4307 unsigned dst_queue_mask
,
4308 const VkImageSubresourceRange
*range
)
4310 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
4311 radv_init_color_image_metadata(cmd_buffer
, image
,
4312 src_layout
, dst_layout
,
4313 src_queue_mask
, dst_queue_mask
);
4317 if (radv_image_has_dcc(image
)) {
4318 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
4319 radv_initialize_dcc(cmd_buffer
, image
, 0xffffffffu
);
4320 } else if (radv_layout_dcc_compressed(image
, src_layout
, src_queue_mask
) &&
4321 !radv_layout_dcc_compressed(image
, dst_layout
, dst_queue_mask
)) {
4322 radv_decompress_dcc(cmd_buffer
, image
, range
);
4323 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4324 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4325 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4327 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
4328 if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4329 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4330 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4335 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4336 struct radv_image
*image
,
4337 VkImageLayout src_layout
,
4338 VkImageLayout dst_layout
,
4339 uint32_t src_family
,
4340 uint32_t dst_family
,
4341 const VkImageSubresourceRange
*range
,
4342 VkImageAspectFlags pending_clears
)
4344 if (image
->exclusive
&& src_family
!= dst_family
) {
4345 /* This is an acquire or a release operation and there will be
4346 * a corresponding release/acquire. Do the transition in the
4347 * most flexible queue. */
4349 assert(src_family
== cmd_buffer
->queue_family_index
||
4350 dst_family
== cmd_buffer
->queue_family_index
);
4352 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
4355 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
4356 (src_family
== RADV_QUEUE_GENERAL
||
4357 dst_family
== RADV_QUEUE_GENERAL
))
4361 unsigned src_queue_mask
=
4362 radv_image_queue_family_mask(image
, src_family
,
4363 cmd_buffer
->queue_family_index
);
4364 unsigned dst_queue_mask
=
4365 radv_image_queue_family_mask(image
, dst_family
,
4366 cmd_buffer
->queue_family_index
);
4368 if (vk_format_is_depth(image
->vk_format
)) {
4369 radv_handle_depth_image_transition(cmd_buffer
, image
,
4370 src_layout
, dst_layout
,
4371 src_queue_mask
, dst_queue_mask
,
4372 range
, pending_clears
);
4374 radv_handle_color_image_transition(cmd_buffer
, image
,
4375 src_layout
, dst_layout
,
4376 src_queue_mask
, dst_queue_mask
,
4381 struct radv_barrier_info
{
4382 uint32_t eventCount
;
4383 const VkEvent
*pEvents
;
4384 VkPipelineStageFlags srcStageMask
;
4388 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
4389 uint32_t memoryBarrierCount
,
4390 const VkMemoryBarrier
*pMemoryBarriers
,
4391 uint32_t bufferMemoryBarrierCount
,
4392 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
4393 uint32_t imageMemoryBarrierCount
,
4394 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
4395 const struct radv_barrier_info
*info
)
4397 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4398 enum radv_cmd_flush_bits src_flush_bits
= 0;
4399 enum radv_cmd_flush_bits dst_flush_bits
= 0;
4401 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
4402 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
4403 uint64_t va
= radv_buffer_get_va(event
->bo
);
4405 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
4407 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
4409 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
4410 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4413 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
4414 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
4416 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
4420 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
4421 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
4423 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
4427 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4428 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4430 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
4432 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
4436 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
4437 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
4439 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4440 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4441 radv_handle_image_transition(cmd_buffer
, image
,
4442 pImageMemoryBarriers
[i
].oldLayout
,
4443 pImageMemoryBarriers
[i
].newLayout
,
4444 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
4445 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
4446 &pImageMemoryBarriers
[i
].subresourceRange
,
4450 /* Make sure CP DMA is idle because the driver might have performed a
4451 * DMA operation for copying or filling buffers/images.
4453 si_cp_dma_wait_for_idle(cmd_buffer
);
4455 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
4458 void radv_CmdPipelineBarrier(
4459 VkCommandBuffer commandBuffer
,
4460 VkPipelineStageFlags srcStageMask
,
4461 VkPipelineStageFlags destStageMask
,
4463 uint32_t memoryBarrierCount
,
4464 const VkMemoryBarrier
* pMemoryBarriers
,
4465 uint32_t bufferMemoryBarrierCount
,
4466 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4467 uint32_t imageMemoryBarrierCount
,
4468 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4470 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4471 struct radv_barrier_info info
;
4473 info
.eventCount
= 0;
4474 info
.pEvents
= NULL
;
4475 info
.srcStageMask
= srcStageMask
;
4477 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
4478 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4479 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
4483 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
4484 struct radv_event
*event
,
4485 VkPipelineStageFlags stageMask
,
4488 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4489 uint64_t va
= radv_buffer_get_va(event
->bo
);
4491 si_emit_cache_flush(cmd_buffer
);
4493 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
4495 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 18);
4497 /* Flags that only require a top-of-pipe event. */
4498 VkPipelineStageFlags top_of_pipe_flags
=
4499 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
4501 /* Flags that only require a post-index-fetch event. */
4502 VkPipelineStageFlags post_index_fetch_flags
=
4504 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
4505 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
4507 /* Make sure CP DMA is idle because the driver might have performed a
4508 * DMA operation for copying or filling buffers/images.
4510 si_cp_dma_wait_for_idle(cmd_buffer
);
4512 /* TODO: Emit EOS events for syncing PS/CS stages. */
4514 if (!(stageMask
& ~top_of_pipe_flags
)) {
4515 /* Just need to sync the PFP engine. */
4516 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
4517 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
4518 S_370_WR_CONFIRM(1) |
4519 S_370_ENGINE_SEL(V_370_PFP
));
4520 radeon_emit(cs
, va
);
4521 radeon_emit(cs
, va
>> 32);
4522 radeon_emit(cs
, value
);
4523 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
4524 /* Sync ME because PFP reads index and indirect buffers. */
4525 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
4526 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
4527 S_370_WR_CONFIRM(1) |
4528 S_370_ENGINE_SEL(V_370_ME
));
4529 radeon_emit(cs
, va
);
4530 radeon_emit(cs
, va
>> 32);
4531 radeon_emit(cs
, value
);
4533 /* Otherwise, sync all prior GPU work using an EOP event. */
4534 si_cs_emit_write_event_eop(cs
,
4535 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
4536 radv_cmd_buffer_uses_mec(cmd_buffer
),
4537 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
4538 EOP_DATA_SEL_VALUE_32BIT
, va
, 2, value
,
4539 cmd_buffer
->gfx9_eop_bug_va
);
4542 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4545 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
4547 VkPipelineStageFlags stageMask
)
4549 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4550 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4552 write_event(cmd_buffer
, event
, stageMask
, 1);
4555 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
4557 VkPipelineStageFlags stageMask
)
4559 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4560 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4562 write_event(cmd_buffer
, event
, stageMask
, 0);
4565 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
4566 uint32_t eventCount
,
4567 const VkEvent
* pEvents
,
4568 VkPipelineStageFlags srcStageMask
,
4569 VkPipelineStageFlags dstStageMask
,
4570 uint32_t memoryBarrierCount
,
4571 const VkMemoryBarrier
* pMemoryBarriers
,
4572 uint32_t bufferMemoryBarrierCount
,
4573 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4574 uint32_t imageMemoryBarrierCount
,
4575 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4577 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4578 struct radv_barrier_info info
;
4580 info
.eventCount
= eventCount
;
4581 info
.pEvents
= pEvents
;
4582 info
.srcStageMask
= 0;
4584 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
4585 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4586 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
4590 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
4591 uint32_t deviceMask
)
4596 /* VK_EXT_conditional_rendering */
4597 void radv_CmdBeginConditionalRenderingEXT(
4598 VkCommandBuffer commandBuffer
,
4599 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
4601 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4602 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
4603 bool draw_visible
= true;
4606 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
4608 /* By default, if the 32-bit value at offset in buffer memory is zero,
4609 * then the rendering commands are discarded, otherwise they are
4610 * executed as normal. If the inverted flag is set, all commands are
4611 * discarded if the value is non zero.
4613 if (pConditionalRenderingBegin
->flags
&
4614 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
4615 draw_visible
= false;
4618 /* Enable predication for this command buffer. */
4619 si_emit_set_predication_state(cmd_buffer
, draw_visible
, va
);
4620 cmd_buffer
->state
.predicating
= true;
4622 /* Store conditional rendering user info. */
4623 cmd_buffer
->state
.predication_type
= draw_visible
;
4624 cmd_buffer
->state
.predication_va
= va
;
4627 void radv_CmdEndConditionalRenderingEXT(
4628 VkCommandBuffer commandBuffer
)
4630 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4632 /* Disable predication for this command buffer. */
4633 si_emit_set_predication_state(cmd_buffer
, false, 0);
4634 cmd_buffer
->state
.predicating
= false;
4636 /* Reset conditional rendering user info. */
4637 cmd_buffer
->state
.predication_type
= -1;
4638 cmd_buffer
->state
.predication_va
= 0;
4641 /* VK_EXT_transform_feedback */
4642 void radv_CmdBindTransformFeedbackBuffersEXT(
4643 VkCommandBuffer commandBuffer
,
4644 uint32_t firstBinding
,
4645 uint32_t bindingCount
,
4646 const VkBuffer
* pBuffers
,
4647 const VkDeviceSize
* pOffsets
,
4648 const VkDeviceSize
* pSizes
)
4650 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4651 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
4652 uint8_t enabled_mask
= 0;
4654 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
4655 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
4656 uint32_t idx
= firstBinding
+ i
;
4658 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
4659 sb
[idx
].offset
= pOffsets
[i
];
4660 sb
[idx
].size
= pSizes
[i
];
4662 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
4663 sb
[idx
].buffer
->bo
);
4665 enabled_mask
|= 1 << idx
;
4668 cmd_buffer
->state
.streamout
.enabled_mask
= enabled_mask
;
4670 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
4674 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
4676 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
4677 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4679 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
4681 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
4682 S_028B94_RAST_STREAM(0) |
4683 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
4684 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
4685 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
4686 radeon_emit(cs
, so
->hw_enabled_mask
&
4687 so
->enabled_stream_buffers_mask
);
4691 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
4693 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
4694 bool old_streamout_enabled
= so
->streamout_enabled
;
4695 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
4697 so
->streamout_enabled
= enable
;
4699 so
->hw_enabled_mask
= so
->enabled_mask
|
4700 (so
->enabled_mask
<< 4) |
4701 (so
->enabled_mask
<< 8) |
4702 (so
->enabled_mask
<< 12);
4704 if ((old_streamout_enabled
!= so
->streamout_enabled
) ||
4705 (old_hw_enabled_mask
!= so
->hw_enabled_mask
))
4706 radv_emit_streamout_enable(cmd_buffer
);
4709 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
4711 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4712 unsigned reg_strmout_cntl
;
4714 /* The register is at different places on different ASICs. */
4715 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
4716 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
4717 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
4719 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
4720 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
4723 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4724 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
4726 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
4727 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
4728 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
4730 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4731 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4732 radeon_emit(cs
, 4); /* poll interval */
4735 void radv_CmdBeginTransformFeedbackEXT(
4736 VkCommandBuffer commandBuffer
,
4737 uint32_t firstCounterBuffer
,
4738 uint32_t counterBufferCount
,
4739 const VkBuffer
* pCounterBuffers
,
4740 const VkDeviceSize
* pCounterBufferOffsets
)
4742 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4743 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
4744 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
4745 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4748 radv_flush_vgt_streamout(cmd_buffer
);
4750 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
4751 for_each_bit(i
, so
->enabled_mask
) {
4752 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
4753 if (counter_buffer_idx
>= 0 && counter_buffer_idx
> counterBufferCount
)
4754 counter_buffer_idx
= -1;
4756 /* SI binds streamout buffers as shader resources.
4757 * VGT only counts primitives and tells the shader through
4760 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
4761 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
4762 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
4764 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
4765 /* The array of counter buffers is optional. */
4766 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
4767 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
4769 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
4772 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
4773 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
4774 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4775 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
4776 radeon_emit(cs
, 0); /* unused */
4777 radeon_emit(cs
, 0); /* unused */
4778 radeon_emit(cs
, va
); /* src address lo */
4779 radeon_emit(cs
, va
>> 32); /* src address hi */
4781 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
4783 /* Start from the beginning. */
4784 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
4785 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
4786 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4787 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
4788 radeon_emit(cs
, 0); /* unused */
4789 radeon_emit(cs
, 0); /* unused */
4790 radeon_emit(cs
, 0); /* unused */
4791 radeon_emit(cs
, 0); /* unused */
4795 radv_set_streamout_enable(cmd_buffer
, true);
4798 void radv_CmdEndTransformFeedbackEXT(
4799 VkCommandBuffer commandBuffer
,
4800 uint32_t firstCounterBuffer
,
4801 uint32_t counterBufferCount
,
4802 const VkBuffer
* pCounterBuffers
,
4803 const VkDeviceSize
* pCounterBufferOffsets
)
4805 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4806 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
4807 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4810 radv_flush_vgt_streamout(cmd_buffer
);
4812 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
4813 for_each_bit(i
, so
->enabled_mask
) {
4814 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
4815 if (counter_buffer_idx
>= 0 && counter_buffer_idx
> counterBufferCount
)
4816 counter_buffer_idx
= -1;
4818 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
4819 /* The array of counters buffer is optional. */
4820 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
4821 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
4823 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
4825 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
4826 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
4827 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4828 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
4829 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
4830 radeon_emit(cs
, va
); /* dst address lo */
4831 radeon_emit(cs
, va
>> 32); /* dst address hi */
4832 radeon_emit(cs
, 0); /* unused */
4833 radeon_emit(cs
, 0); /* unused */
4835 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
4838 /* Deactivate transform feedback by zeroing the buffer size.
4839 * The counters (primitives generated, primitives emitted) may
4840 * be enabled even if there is not buffer bound. This ensures
4841 * that the primitives-emitted query won't increment.
4843 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
4846 radv_set_streamout_enable(cmd_buffer
, false);
4849 void radv_CmdDrawIndirectByteCountEXT(
4850 VkCommandBuffer commandBuffer
,
4851 uint32_t instanceCount
,
4852 uint32_t firstInstance
,
4853 VkBuffer _counterBuffer
,
4854 VkDeviceSize counterBufferOffset
,
4855 uint32_t counterOffset
,
4856 uint32_t vertexStride
)
4858 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4859 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
4860 struct radv_draw_info info
= {};
4862 info
.instance_count
= instanceCount
;
4863 info
.first_instance
= firstInstance
;
4864 info
.strmout_buffer
= counterBuffer
;
4865 info
.strmout_buffer_offset
= counterBufferOffset
;
4866 info
.stride
= vertexStride
;
4868 radv_draw(cmd_buffer
, &info
);