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e020153c2940d35e653f541fb1a41385aca2da06
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safely call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo, 8);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 cmd_buffer->ring_offsets_idx = -1;
314
315 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
316 cmd_buffer->descriptors[i].dirty = 0;
317 cmd_buffer->descriptors[i].valid = 0;
318 cmd_buffer->descriptors[i].push_dirty = false;
319 }
320
321 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
322 void *fence_ptr;
323 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
324 &cmd_buffer->gfx9_fence_offset,
325 &fence_ptr);
326 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
327 }
328
329 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
330
331 return cmd_buffer->record_result;
332 }
333
334 static bool
335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
336 uint64_t min_needed)
337 {
338 uint64_t new_size;
339 struct radeon_winsys_bo *bo;
340 struct radv_cmd_buffer_upload *upload;
341 struct radv_device *device = cmd_buffer->device;
342
343 new_size = MAX2(min_needed, 16 * 1024);
344 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
345
346 bo = device->ws->buffer_create(device->ws,
347 new_size, 4096,
348 RADEON_DOMAIN_GTT,
349 RADEON_FLAG_CPU_ACCESS|
350 RADEON_FLAG_NO_INTERPROCESS_SHARING |
351 RADEON_FLAG_32BIT);
352
353 if (!bo) {
354 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
355 return false;
356 }
357
358 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
359 if (cmd_buffer->upload.upload_bo) {
360 upload = malloc(sizeof(*upload));
361
362 if (!upload) {
363 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
364 device->ws->buffer_destroy(bo);
365 return false;
366 }
367
368 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
369 list_add(&upload->list, &cmd_buffer->upload.list);
370 }
371
372 cmd_buffer->upload.upload_bo = bo;
373 cmd_buffer->upload.size = new_size;
374 cmd_buffer->upload.offset = 0;
375 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
376
377 if (!cmd_buffer->upload.map) {
378 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
379 return false;
380 }
381
382 return true;
383 }
384
385 bool
386 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
387 unsigned size,
388 unsigned alignment,
389 unsigned *out_offset,
390 void **ptr)
391 {
392 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
393 if (offset + size > cmd_buffer->upload.size) {
394 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
395 return false;
396 offset = 0;
397 }
398
399 *out_offset = offset;
400 *ptr = cmd_buffer->upload.map + offset;
401
402 cmd_buffer->upload.offset = offset + size;
403 return true;
404 }
405
406 bool
407 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
408 unsigned size, unsigned alignment,
409 const void *data, unsigned *out_offset)
410 {
411 uint8_t *ptr;
412
413 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
414 out_offset, (void **)&ptr))
415 return false;
416
417 if (ptr)
418 memcpy(ptr, data, size);
419
420 return true;
421 }
422
423 static void
424 radv_emit_write_data_packet(struct radeon_cmdbuf *cs, uint64_t va,
425 unsigned count, const uint32_t *data)
426 {
427 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
428 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
429 S_370_WR_CONFIRM(1) |
430 S_370_ENGINE_SEL(V_370_ME));
431 radeon_emit(cs, va);
432 radeon_emit(cs, va >> 32);
433 radeon_emit_array(cs, data, count);
434 }
435
436 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
437 {
438 struct radv_device *device = cmd_buffer->device;
439 struct radeon_cmdbuf *cs = cmd_buffer->cs;
440 uint64_t va;
441
442 va = radv_buffer_get_va(device->trace_bo);
443 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
444 va += 4;
445
446 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
447
448 ++cmd_buffer->state.trace_id;
449 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
450 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
451 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
452 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
453 }
454
455 static void
456 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
457 enum radv_cmd_flush_bits flags)
458 {
459 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
460 uint32_t *ptr = NULL;
461 uint64_t va = 0;
462
463 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
464 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
465
466 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
467 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
468 cmd_buffer->gfx9_fence_offset;
469 ptr = &cmd_buffer->gfx9_fence_idx;
470 }
471
472 /* Force wait for graphics or compute engines to be idle. */
473 si_cs_emit_cache_flush(cmd_buffer->cs,
474 cmd_buffer->device->physical_device->rad_info.chip_class,
475 ptr, va,
476 radv_cmd_buffer_uses_mec(cmd_buffer),
477 flags);
478 }
479
480 if (unlikely(cmd_buffer->device->trace_bo))
481 radv_cmd_buffer_trace_emit(cmd_buffer);
482 }
483
484 static void
485 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
486 struct radv_pipeline *pipeline, enum ring_type ring)
487 {
488 struct radv_device *device = cmd_buffer->device;
489 struct radeon_cmdbuf *cs = cmd_buffer->cs;
490 uint32_t data[2];
491 uint64_t va;
492
493 va = radv_buffer_get_va(device->trace_bo);
494
495 switch (ring) {
496 case RING_GFX:
497 va += 8;
498 break;
499 case RING_COMPUTE:
500 va += 16;
501 break;
502 default:
503 assert(!"invalid ring type");
504 }
505
506 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
507 cmd_buffer->cs, 6);
508
509 data[0] = (uintptr_t)pipeline;
510 data[1] = (uintptr_t)pipeline >> 32;
511
512 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
513 radv_emit_write_data_packet(cs, va, 2, data);
514 }
515
516 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
517 VkPipelineBindPoint bind_point,
518 struct radv_descriptor_set *set,
519 unsigned idx)
520 {
521 struct radv_descriptor_state *descriptors_state =
522 radv_get_descriptors_state(cmd_buffer, bind_point);
523
524 descriptors_state->sets[idx] = set;
525 if (set)
526 descriptors_state->valid |= (1u << idx);
527 else
528 descriptors_state->valid &= ~(1u << idx);
529 descriptors_state->dirty |= (1u << idx);
530 }
531
532 static void
533 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
534 VkPipelineBindPoint bind_point)
535 {
536 struct radv_descriptor_state *descriptors_state =
537 radv_get_descriptors_state(cmd_buffer, bind_point);
538 struct radv_device *device = cmd_buffer->device;
539 struct radeon_cmdbuf *cs = cmd_buffer->cs;
540 uint32_t data[MAX_SETS * 2] = {};
541 uint64_t va;
542 unsigned i;
543 va = radv_buffer_get_va(device->trace_bo) + 24;
544
545 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
546 cmd_buffer->cs, 4 + MAX_SETS * 2);
547
548 for_each_bit(i, descriptors_state->valid) {
549 struct radv_descriptor_set *set = descriptors_state->sets[i];
550 data[i * 2] = (uintptr_t)set;
551 data[i * 2 + 1] = (uintptr_t)set >> 32;
552 }
553
554 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
555 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
556 }
557
558 struct radv_userdata_info *
559 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
560 gl_shader_stage stage,
561 int idx)
562 {
563 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
564 return &shader->info.user_sgprs_locs.shader_data[idx];
565 }
566
567 static void
568 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
569 struct radv_pipeline *pipeline,
570 gl_shader_stage stage,
571 int idx, uint64_t va)
572 {
573 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
574 uint32_t base_reg = pipeline->user_data_0[stage];
575 if (loc->sgpr_idx == -1)
576 return;
577
578 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
579 assert(!loc->indirect);
580
581 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
582 base_reg + loc->sgpr_idx * 4, va, false);
583 }
584
585 static void
586 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
587 struct radv_pipeline *pipeline,
588 struct radv_descriptor_state *descriptors_state,
589 gl_shader_stage stage)
590 {
591 struct radv_device *device = cmd_buffer->device;
592 struct radeon_cmdbuf *cs = cmd_buffer->cs;
593 uint32_t sh_base = pipeline->user_data_0[stage];
594 struct radv_userdata_locations *locs =
595 &pipeline->shaders[stage]->info.user_sgprs_locs;
596 unsigned mask;
597
598 mask = descriptors_state->dirty & descriptors_state->valid;
599
600 for (int i = 0; i < MAX_SETS; i++) {
601 struct radv_userdata_info *loc = &locs->descriptor_sets[i];
602 if (loc->sgpr_idx != -1 && !loc->indirect)
603 continue;
604 mask &= ~(1 << i);
605 }
606
607 while (mask) {
608 int start, count;
609
610 u_bit_scan_consecutive_range(&mask, &start, &count);
611
612 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
613 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
614
615 radv_emit_shader_pointer_head(cs, sh_offset, count,
616 HAVE_32BIT_POINTERS);
617 for (int i = 0; i < count; i++) {
618 struct radv_descriptor_set *set =
619 descriptors_state->sets[start + i];
620
621 radv_emit_shader_pointer_body(device, cs, set->va,
622 HAVE_32BIT_POINTERS);
623 }
624 }
625 }
626
627 static void
628 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
629 struct radv_pipeline *pipeline)
630 {
631 int num_samples = pipeline->graphics.ms.num_samples;
632 struct radv_multisample_state *ms = &pipeline->graphics.ms;
633 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
634
635 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
636 cmd_buffer->sample_positions_needed = true;
637
638 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
639 return;
640
641 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
642 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
643 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
644
645 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
646
647 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
648
649 /* GFX9: Flush DFSM when the AA mode changes. */
650 if (cmd_buffer->device->dfsm_allowed) {
651 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
652 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
653 }
654 }
655
656 static void
657 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
658 struct radv_shader_variant *shader)
659 {
660 uint64_t va;
661
662 if (!shader)
663 return;
664
665 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
666
667 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
668 }
669
670 static void
671 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
672 struct radv_pipeline *pipeline,
673 bool vertex_stage_only)
674 {
675 struct radv_cmd_state *state = &cmd_buffer->state;
676 uint32_t mask = state->prefetch_L2_mask;
677
678 if (vertex_stage_only) {
679 /* Fast prefetch path for starting draws as soon as possible.
680 */
681 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
682 RADV_PREFETCH_VBO_DESCRIPTORS);
683 }
684
685 if (mask & RADV_PREFETCH_VS)
686 radv_emit_shader_prefetch(cmd_buffer,
687 pipeline->shaders[MESA_SHADER_VERTEX]);
688
689 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
690 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
691
692 if (mask & RADV_PREFETCH_TCS)
693 radv_emit_shader_prefetch(cmd_buffer,
694 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
695
696 if (mask & RADV_PREFETCH_TES)
697 radv_emit_shader_prefetch(cmd_buffer,
698 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
699
700 if (mask & RADV_PREFETCH_GS) {
701 radv_emit_shader_prefetch(cmd_buffer,
702 pipeline->shaders[MESA_SHADER_GEOMETRY]);
703 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
704 }
705
706 if (mask & RADV_PREFETCH_PS)
707 radv_emit_shader_prefetch(cmd_buffer,
708 pipeline->shaders[MESA_SHADER_FRAGMENT]);
709
710 state->prefetch_L2_mask &= ~mask;
711 }
712
713 static void
714 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
715 {
716 if (!cmd_buffer->device->physical_device->rbplus_allowed)
717 return;
718
719 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
720 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
721 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
722
723 unsigned sx_ps_downconvert = 0;
724 unsigned sx_blend_opt_epsilon = 0;
725 unsigned sx_blend_opt_control = 0;
726
727 for (unsigned i = 0; i < subpass->color_count; ++i) {
728 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
729 continue;
730
731 int idx = subpass->color_attachments[i].attachment;
732 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
733
734 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
735 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
736 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
737 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
738
739 bool has_alpha, has_rgb;
740
741 /* Set if RGB and A are present. */
742 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
743
744 if (format == V_028C70_COLOR_8 ||
745 format == V_028C70_COLOR_16 ||
746 format == V_028C70_COLOR_32)
747 has_rgb = !has_alpha;
748 else
749 has_rgb = true;
750
751 /* Check the colormask and export format. */
752 if (!(colormask & 0x7))
753 has_rgb = false;
754 if (!(colormask & 0x8))
755 has_alpha = false;
756
757 if (spi_format == V_028714_SPI_SHADER_ZERO) {
758 has_rgb = false;
759 has_alpha = false;
760 }
761
762 /* Disable value checking for disabled channels. */
763 if (!has_rgb)
764 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
765 if (!has_alpha)
766 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
767
768 /* Enable down-conversion for 32bpp and smaller formats. */
769 switch (format) {
770 case V_028C70_COLOR_8:
771 case V_028C70_COLOR_8_8:
772 case V_028C70_COLOR_8_8_8_8:
773 /* For 1 and 2-channel formats, use the superset thereof. */
774 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
775 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
776 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
777 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
778 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
779 }
780 break;
781
782 case V_028C70_COLOR_5_6_5:
783 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
784 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
785 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
786 }
787 break;
788
789 case V_028C70_COLOR_1_5_5_5:
790 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
791 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
792 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
793 }
794 break;
795
796 case V_028C70_COLOR_4_4_4_4:
797 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
798 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
799 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
800 }
801 break;
802
803 case V_028C70_COLOR_32:
804 if (swap == V_028C70_SWAP_STD &&
805 spi_format == V_028714_SPI_SHADER_32_R)
806 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
807 else if (swap == V_028C70_SWAP_ALT_REV &&
808 spi_format == V_028714_SPI_SHADER_32_AR)
809 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
810 break;
811
812 case V_028C70_COLOR_16:
813 case V_028C70_COLOR_16_16:
814 /* For 1-channel formats, use the superset thereof. */
815 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
816 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
817 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
818 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
819 if (swap == V_028C70_SWAP_STD ||
820 swap == V_028C70_SWAP_STD_REV)
821 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
822 else
823 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
824 }
825 break;
826
827 case V_028C70_COLOR_10_11_11:
828 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
829 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
830 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
831 }
832 break;
833
834 case V_028C70_COLOR_2_10_10_10:
835 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
836 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
837 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
838 }
839 break;
840 }
841 }
842
843 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
844 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
845 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
846 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
847 }
848
849 static void
850 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
851 {
852 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
853
854 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
855 return;
856
857 radv_update_multisample_state(cmd_buffer, pipeline);
858
859 cmd_buffer->scratch_size_needed =
860 MAX2(cmd_buffer->scratch_size_needed,
861 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
862
863 if (!cmd_buffer->state.emitted_pipeline ||
864 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
865 pipeline->graphics.can_use_guardband)
866 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
867
868 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
869
870 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
871 if (!pipeline->shaders[i])
872 continue;
873
874 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
875 pipeline->shaders[i]->bo, 8);
876 }
877
878 if (radv_pipeline_has_gs(pipeline))
879 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
880 pipeline->gs_copy_shader->bo, 8);
881
882 if (unlikely(cmd_buffer->device->trace_bo))
883 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
884
885 cmd_buffer->state.emitted_pipeline = pipeline;
886
887 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
888 }
889
890 static void
891 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
892 {
893 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
894 cmd_buffer->state.dynamic.viewport.viewports);
895 }
896
897 static void
898 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
899 {
900 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
901
902 si_write_scissors(cmd_buffer->cs, 0, count,
903 cmd_buffer->state.dynamic.scissor.scissors,
904 cmd_buffer->state.dynamic.viewport.viewports,
905 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
906 }
907
908 static void
909 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
910 {
911 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
912 return;
913
914 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
915 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
916 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
917 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
918 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
919 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
920 S_028214_BR_Y(rect.offset.y + rect.extent.height));
921 }
922 }
923
924 static void
925 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
926 {
927 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
928
929 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
930 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
931 }
932
933 static void
934 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
935 {
936 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
937
938 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
939 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
940 }
941
942 static void
943 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
944 {
945 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
946
947 radeon_set_context_reg_seq(cmd_buffer->cs,
948 R_028430_DB_STENCILREFMASK, 2);
949 radeon_emit(cmd_buffer->cs,
950 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
951 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
952 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
953 S_028430_STENCILOPVAL(1));
954 radeon_emit(cmd_buffer->cs,
955 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
956 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
957 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
958 S_028434_STENCILOPVAL_BF(1));
959 }
960
961 static void
962 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
963 {
964 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
965
966 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
967 fui(d->depth_bounds.min));
968 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
969 fui(d->depth_bounds.max));
970 }
971
972 static void
973 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
974 {
975 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
976 unsigned slope = fui(d->depth_bias.slope * 16.0f);
977 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
978
979
980 radeon_set_context_reg_seq(cmd_buffer->cs,
981 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
982 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
983 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
984 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
985 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
986 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
987 }
988
989 static void
990 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
991 int index,
992 struct radv_attachment_info *att,
993 struct radv_image *image,
994 VkImageLayout layout)
995 {
996 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
997 struct radv_color_buffer_info *cb = &att->cb;
998 uint32_t cb_color_info = cb->cb_color_info;
999
1000 if (!radv_layout_dcc_compressed(image, layout,
1001 radv_image_queue_family_mask(image,
1002 cmd_buffer->queue_family_index,
1003 cmd_buffer->queue_family_index))) {
1004 cb_color_info &= C_028C70_DCC_ENABLE;
1005 }
1006
1007 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1008 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1009 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1010 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1011 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1012 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1013 radeon_emit(cmd_buffer->cs, cb_color_info);
1014 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1015 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1016 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1017 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1018 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1019 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1020
1021 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1022 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1023 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1024
1025 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1026 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1027 } else {
1028 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1029 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1030 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1031 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1032 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1033 radeon_emit(cmd_buffer->cs, cb_color_info);
1034 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1035 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1036 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1037 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1038 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1039 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1040
1041 if (is_vi) { /* DCC BASE */
1042 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1043 }
1044 }
1045 }
1046
1047 static void
1048 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1049 struct radv_ds_buffer_info *ds,
1050 struct radv_image *image, VkImageLayout layout,
1051 bool requires_cond_write)
1052 {
1053 uint32_t db_z_info = ds->db_z_info;
1054 uint32_t db_z_info_reg;
1055
1056 if (!radv_image_is_tc_compat_htile(image))
1057 return;
1058
1059 if (!radv_layout_has_htile(image, layout,
1060 radv_image_queue_family_mask(image,
1061 cmd_buffer->queue_family_index,
1062 cmd_buffer->queue_family_index))) {
1063 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1064 }
1065
1066 db_z_info &= C_028040_ZRANGE_PRECISION;
1067
1068 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1069 db_z_info_reg = R_028038_DB_Z_INFO;
1070 } else {
1071 db_z_info_reg = R_028040_DB_Z_INFO;
1072 }
1073
1074 /* When we don't know the last fast clear value we need to emit a
1075 * conditional packet, otherwise we can update DB_Z_INFO directly.
1076 */
1077 if (requires_cond_write) {
1078 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1079
1080 const uint32_t write_space = 0 << 8; /* register */
1081 const uint32_t poll_space = 1 << 4; /* memory */
1082 const uint32_t function = 3 << 0; /* equal to the reference */
1083 const uint32_t options = write_space | poll_space | function;
1084 radeon_emit(cmd_buffer->cs, options);
1085
1086 /* poll address - location of the depth clear value */
1087 uint64_t va = radv_buffer_get_va(image->bo);
1088 va += image->offset + image->clear_value_offset;
1089
1090 /* In presence of stencil format, we have to adjust the base
1091 * address because the first value is the stencil clear value.
1092 */
1093 if (vk_format_is_stencil(image->vk_format))
1094 va += 4;
1095
1096 radeon_emit(cmd_buffer->cs, va);
1097 radeon_emit(cmd_buffer->cs, va >> 32);
1098
1099 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1100 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1101 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1102 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1103 radeon_emit(cmd_buffer->cs, db_z_info);
1104 } else {
1105 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1106 }
1107 }
1108
1109 static void
1110 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1111 struct radv_ds_buffer_info *ds,
1112 struct radv_image *image,
1113 VkImageLayout layout)
1114 {
1115 uint32_t db_z_info = ds->db_z_info;
1116 uint32_t db_stencil_info = ds->db_stencil_info;
1117
1118 if (!radv_layout_has_htile(image, layout,
1119 radv_image_queue_family_mask(image,
1120 cmd_buffer->queue_family_index,
1121 cmd_buffer->queue_family_index))) {
1122 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1123 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1124 }
1125
1126 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1127 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1128
1129
1130 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1131 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1132 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1133 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1134 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1135
1136 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1137 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1138 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1139 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1140 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1141 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1142 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1143 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1144 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1145 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1146 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1147
1148 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1149 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1150 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1151 } else {
1152 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1153
1154 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1155 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1156 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1157 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1158 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1159 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1160 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1161 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1162 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1163 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1164
1165 }
1166
1167 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1168 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1169
1170 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1171 ds->pa_su_poly_offset_db_fmt_cntl);
1172 }
1173
1174 /**
1175 * Update the fast clear depth/stencil values if the image is bound as a
1176 * depth/stencil buffer.
1177 */
1178 static void
1179 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1180 struct radv_image *image,
1181 VkClearDepthStencilValue ds_clear_value,
1182 VkImageAspectFlags aspects)
1183 {
1184 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1185 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1186 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1187 struct radv_attachment_info *att;
1188 uint32_t att_idx;
1189
1190 if (!framebuffer || !subpass)
1191 return;
1192
1193 att_idx = subpass->depth_stencil_attachment.attachment;
1194 if (att_idx == VK_ATTACHMENT_UNUSED)
1195 return;
1196
1197 att = &framebuffer->attachments[att_idx];
1198 if (att->attachment->image != image)
1199 return;
1200
1201 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1202 radeon_emit(cs, ds_clear_value.stencil);
1203 radeon_emit(cs, fui(ds_clear_value.depth));
1204
1205 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1206 * only needed when clearing Z to 0.0.
1207 */
1208 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1209 ds_clear_value.depth == 0.0) {
1210 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1211
1212 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1213 layout, false);
1214 }
1215 }
1216
1217 /**
1218 * Set the clear depth/stencil values to the image's metadata.
1219 */
1220 static void
1221 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1222 struct radv_image *image,
1223 VkClearDepthStencilValue ds_clear_value,
1224 VkImageAspectFlags aspects)
1225 {
1226 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1227 uint64_t va = radv_buffer_get_va(image->bo);
1228 unsigned reg_offset = 0, reg_count = 0;
1229
1230 va += image->offset + image->clear_value_offset;
1231
1232 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1233 ++reg_count;
1234 } else {
1235 ++reg_offset;
1236 va += 4;
1237 }
1238 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1239 ++reg_count;
1240
1241 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1242 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1243 S_370_WR_CONFIRM(1) |
1244 S_370_ENGINE_SEL(V_370_PFP));
1245 radeon_emit(cs, va);
1246 radeon_emit(cs, va >> 32);
1247 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1248 radeon_emit(cs, ds_clear_value.stencil);
1249 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1250 radeon_emit(cs, fui(ds_clear_value.depth));
1251 }
1252
1253 /**
1254 * Update the clear depth/stencil values for this image.
1255 */
1256 void
1257 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1258 struct radv_image *image,
1259 VkClearDepthStencilValue ds_clear_value,
1260 VkImageAspectFlags aspects)
1261 {
1262 assert(radv_image_has_htile(image));
1263
1264 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1265
1266 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1267 aspects);
1268 }
1269
1270 /**
1271 * Load the clear depth/stencil values from the image's metadata.
1272 */
1273 static void
1274 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1275 struct radv_image *image)
1276 {
1277 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1278 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1279 uint64_t va = radv_buffer_get_va(image->bo);
1280 unsigned reg_offset = 0, reg_count = 0;
1281
1282 va += image->offset + image->clear_value_offset;
1283
1284 if (!radv_image_has_htile(image))
1285 return;
1286
1287 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1288 ++reg_count;
1289 } else {
1290 ++reg_offset;
1291 va += 4;
1292 }
1293 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1294 ++reg_count;
1295
1296 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1297 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1298 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1299 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1300 radeon_emit(cs, va);
1301 radeon_emit(cs, va >> 32);
1302 radeon_emit(cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1303 radeon_emit(cs, 0);
1304
1305 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1306 radeon_emit(cs, 0);
1307 }
1308
1309 /*
1310 * With DCC some colors don't require CMASK elimination before being
1311 * used as a texture. This sets a predicate value to determine if the
1312 * cmask eliminate is required.
1313 */
1314 void
1315 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1316 struct radv_image *image,
1317 bool value)
1318 {
1319 uint64_t pred_val = value;
1320 uint64_t va = radv_buffer_get_va(image->bo);
1321 va += image->offset + image->dcc_pred_offset;
1322
1323 assert(radv_image_has_dcc(image));
1324
1325 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1326 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1327 S_370_WR_CONFIRM(1) |
1328 S_370_ENGINE_SEL(V_370_PFP));
1329 radeon_emit(cmd_buffer->cs, va);
1330 radeon_emit(cmd_buffer->cs, va >> 32);
1331 radeon_emit(cmd_buffer->cs, pred_val);
1332 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1333 }
1334
1335 /**
1336 * Update the fast clear color values if the image is bound as a color buffer.
1337 */
1338 static void
1339 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1340 struct radv_image *image,
1341 int cb_idx,
1342 uint32_t color_values[2])
1343 {
1344 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1345 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1346 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1347 struct radv_attachment_info *att;
1348 uint32_t att_idx;
1349
1350 if (!framebuffer || !subpass)
1351 return;
1352
1353 att_idx = subpass->color_attachments[cb_idx].attachment;
1354 if (att_idx == VK_ATTACHMENT_UNUSED)
1355 return;
1356
1357 att = &framebuffer->attachments[att_idx];
1358 if (att->attachment->image != image)
1359 return;
1360
1361 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1362 radeon_emit(cs, color_values[0]);
1363 radeon_emit(cs, color_values[1]);
1364 }
1365
1366 /**
1367 * Set the clear color values to the image's metadata.
1368 */
1369 static void
1370 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1371 struct radv_image *image,
1372 uint32_t color_values[2])
1373 {
1374 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1375 uint64_t va = radv_buffer_get_va(image->bo);
1376
1377 va += image->offset + image->clear_value_offset;
1378
1379 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1380
1381 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1382 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1383 S_370_WR_CONFIRM(1) |
1384 S_370_ENGINE_SEL(V_370_PFP));
1385 radeon_emit(cs, va);
1386 radeon_emit(cs, va >> 32);
1387 radeon_emit(cs, color_values[0]);
1388 radeon_emit(cs, color_values[1]);
1389 }
1390
1391 /**
1392 * Update the clear color values for this image.
1393 */
1394 void
1395 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1396 struct radv_image *image,
1397 int cb_idx,
1398 uint32_t color_values[2])
1399 {
1400 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1401
1402 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1403
1404 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1405 color_values);
1406 }
1407
1408 /**
1409 * Load the clear color values from the image's metadata.
1410 */
1411 static void
1412 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1413 struct radv_image *image,
1414 int cb_idx)
1415 {
1416 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1417 uint64_t va = radv_buffer_get_va(image->bo);
1418
1419 va += image->offset + image->clear_value_offset;
1420
1421 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1422 return;
1423
1424 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1425
1426 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1427 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1428 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1429 COPY_DATA_COUNT_SEL);
1430 radeon_emit(cs, va);
1431 radeon_emit(cs, va >> 32);
1432 radeon_emit(cs, reg >> 2);
1433 radeon_emit(cs, 0);
1434
1435 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1436 radeon_emit(cs, 0);
1437 }
1438
1439 static void
1440 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1441 {
1442 int i;
1443 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1444 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1445
1446 /* this may happen for inherited secondary recording */
1447 if (!framebuffer)
1448 return;
1449
1450 for (i = 0; i < 8; ++i) {
1451 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1452 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1453 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1454 continue;
1455 }
1456
1457 int idx = subpass->color_attachments[i].attachment;
1458 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1459 struct radv_image *image = att->attachment->image;
1460 VkImageLayout layout = subpass->color_attachments[i].layout;
1461
1462 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1463
1464 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1465 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1466
1467 radv_load_color_clear_metadata(cmd_buffer, image, i);
1468 }
1469
1470 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1471 int idx = subpass->depth_stencil_attachment.attachment;
1472 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1473 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1474 struct radv_image *image = att->attachment->image;
1475 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1476 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1477 cmd_buffer->queue_family_index,
1478 cmd_buffer->queue_family_index);
1479 /* We currently don't support writing decompressed HTILE */
1480 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1481 radv_layout_is_htile_compressed(image, layout, queue_mask));
1482
1483 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1484
1485 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1486 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1487 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1488 }
1489 radv_load_ds_clear_metadata(cmd_buffer, image);
1490 } else {
1491 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1492 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1493 else
1494 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1495
1496 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1497 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1498 }
1499 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1500 S_028208_BR_X(framebuffer->width) |
1501 S_028208_BR_Y(framebuffer->height));
1502
1503 if (cmd_buffer->device->dfsm_allowed) {
1504 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1505 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1506 }
1507
1508 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1509 }
1510
1511 static void
1512 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1513 {
1514 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1515 struct radv_cmd_state *state = &cmd_buffer->state;
1516
1517 if (state->index_type != state->last_index_type) {
1518 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1519 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1520 2, state->index_type);
1521 } else {
1522 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1523 radeon_emit(cs, state->index_type);
1524 }
1525
1526 state->last_index_type = state->index_type;
1527 }
1528
1529 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1530 radeon_emit(cs, state->index_va);
1531 radeon_emit(cs, state->index_va >> 32);
1532
1533 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1534 radeon_emit(cs, state->max_index_count);
1535
1536 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1537 }
1538
1539 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1540 {
1541 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1542 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1543 uint32_t pa_sc_mode_cntl_1 =
1544 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1545 uint32_t db_count_control;
1546
1547 if(!cmd_buffer->state.active_occlusion_queries) {
1548 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1549 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1550 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1551 has_perfect_queries) {
1552 /* Re-enable out-of-order rasterization if the
1553 * bound pipeline supports it and if it's has
1554 * been disabled before starting any perfect
1555 * occlusion queries.
1556 */
1557 radeon_set_context_reg(cmd_buffer->cs,
1558 R_028A4C_PA_SC_MODE_CNTL_1,
1559 pa_sc_mode_cntl_1);
1560 }
1561 db_count_control = 0;
1562 } else {
1563 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1564 }
1565 } else {
1566 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1567 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1568
1569 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1570 db_count_control =
1571 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1572 S_028004_SAMPLE_RATE(sample_rate) |
1573 S_028004_ZPASS_ENABLE(1) |
1574 S_028004_SLICE_EVEN_ENABLE(1) |
1575 S_028004_SLICE_ODD_ENABLE(1);
1576
1577 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1578 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1579 has_perfect_queries) {
1580 /* If the bound pipeline has enabled
1581 * out-of-order rasterization, we should
1582 * disable it before starting any perfect
1583 * occlusion queries.
1584 */
1585 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1586
1587 radeon_set_context_reg(cmd_buffer->cs,
1588 R_028A4C_PA_SC_MODE_CNTL_1,
1589 pa_sc_mode_cntl_1);
1590 }
1591 } else {
1592 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1593 S_028004_SAMPLE_RATE(sample_rate);
1594 }
1595 }
1596
1597 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1598 }
1599
1600 static void
1601 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1602 {
1603 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1604
1605 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1606 radv_emit_viewport(cmd_buffer);
1607
1608 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1609 !cmd_buffer->device->physical_device->has_scissor_bug)
1610 radv_emit_scissor(cmd_buffer);
1611
1612 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1613 radv_emit_line_width(cmd_buffer);
1614
1615 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1616 radv_emit_blend_constants(cmd_buffer);
1617
1618 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1619 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1620 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1621 radv_emit_stencil(cmd_buffer);
1622
1623 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1624 radv_emit_depth_bounds(cmd_buffer);
1625
1626 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1627 radv_emit_depth_bias(cmd_buffer);
1628
1629 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1630 radv_emit_discard_rectangle(cmd_buffer);
1631
1632 cmd_buffer->state.dirty &= ~states;
1633 }
1634
1635 static void
1636 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1637 VkPipelineBindPoint bind_point)
1638 {
1639 struct radv_descriptor_state *descriptors_state =
1640 radv_get_descriptors_state(cmd_buffer, bind_point);
1641 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1642 unsigned bo_offset;
1643
1644 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1645 set->mapped_ptr,
1646 &bo_offset))
1647 return;
1648
1649 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1650 set->va += bo_offset;
1651 }
1652
1653 static void
1654 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1655 VkPipelineBindPoint bind_point)
1656 {
1657 struct radv_descriptor_state *descriptors_state =
1658 radv_get_descriptors_state(cmd_buffer, bind_point);
1659 uint32_t size = MAX_SETS * 2 * 4;
1660 uint32_t offset;
1661 void *ptr;
1662
1663 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1664 256, &offset, &ptr))
1665 return;
1666
1667 for (unsigned i = 0; i < MAX_SETS; i++) {
1668 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1669 uint64_t set_va = 0;
1670 struct radv_descriptor_set *set = descriptors_state->sets[i];
1671 if (descriptors_state->valid & (1u << i))
1672 set_va = set->va;
1673 uptr[0] = set_va & 0xffffffff;
1674 uptr[1] = set_va >> 32;
1675 }
1676
1677 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1678 va += offset;
1679
1680 if (cmd_buffer->state.pipeline) {
1681 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1682 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1683 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1684
1685 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1686 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1687 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1688
1689 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1690 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1691 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1692
1693 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1694 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1695 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1696
1697 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1698 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1699 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1700 }
1701
1702 if (cmd_buffer->state.compute_pipeline)
1703 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1704 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1705 }
1706
1707 static void
1708 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1709 VkShaderStageFlags stages)
1710 {
1711 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1712 VK_PIPELINE_BIND_POINT_COMPUTE :
1713 VK_PIPELINE_BIND_POINT_GRAPHICS;
1714 struct radv_descriptor_state *descriptors_state =
1715 radv_get_descriptors_state(cmd_buffer, bind_point);
1716
1717 if (!descriptors_state->dirty)
1718 return;
1719
1720 if (descriptors_state->push_dirty)
1721 radv_flush_push_descriptors(cmd_buffer, bind_point);
1722
1723 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1724 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1725 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1726 }
1727
1728 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1729 cmd_buffer->cs,
1730 MAX_SETS * MESA_SHADER_STAGES * 4);
1731
1732 if (cmd_buffer->state.pipeline) {
1733 radv_foreach_stage(stage, stages) {
1734 if (!cmd_buffer->state.pipeline->shaders[stage])
1735 continue;
1736
1737 radv_emit_descriptor_pointers(cmd_buffer,
1738 cmd_buffer->state.pipeline,
1739 descriptors_state, stage);
1740 }
1741 }
1742
1743 if (cmd_buffer->state.compute_pipeline &&
1744 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1745 radv_emit_descriptor_pointers(cmd_buffer,
1746 cmd_buffer->state.compute_pipeline,
1747 descriptors_state,
1748 MESA_SHADER_COMPUTE);
1749 }
1750
1751 descriptors_state->dirty = 0;
1752 descriptors_state->push_dirty = false;
1753
1754 if (unlikely(cmd_buffer->device->trace_bo))
1755 radv_save_descriptors(cmd_buffer, bind_point);
1756
1757 assert(cmd_buffer->cs->cdw <= cdw_max);
1758 }
1759
1760 static void
1761 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1762 VkShaderStageFlags stages)
1763 {
1764 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1765 ? cmd_buffer->state.compute_pipeline
1766 : cmd_buffer->state.pipeline;
1767 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1768 VK_PIPELINE_BIND_POINT_COMPUTE :
1769 VK_PIPELINE_BIND_POINT_GRAPHICS;
1770 struct radv_descriptor_state *descriptors_state =
1771 radv_get_descriptors_state(cmd_buffer, bind_point);
1772 struct radv_pipeline_layout *layout = pipeline->layout;
1773 struct radv_shader_variant *shader, *prev_shader;
1774 unsigned offset;
1775 void *ptr;
1776 uint64_t va;
1777
1778 stages &= cmd_buffer->push_constant_stages;
1779 if (!stages ||
1780 (!layout->push_constant_size && !layout->dynamic_offset_count))
1781 return;
1782
1783 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1784 16 * layout->dynamic_offset_count,
1785 256, &offset, &ptr))
1786 return;
1787
1788 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1789 memcpy((char*)ptr + layout->push_constant_size,
1790 descriptors_state->dynamic_buffers,
1791 16 * layout->dynamic_offset_count);
1792
1793 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1794 va += offset;
1795
1796 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1797 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1798
1799 prev_shader = NULL;
1800 radv_foreach_stage(stage, stages) {
1801 shader = radv_get_shader(pipeline, stage);
1802
1803 /* Avoid redundantly emitting the address for merged stages. */
1804 if (shader && shader != prev_shader) {
1805 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1806 AC_UD_PUSH_CONSTANTS, va);
1807
1808 prev_shader = shader;
1809 }
1810 }
1811
1812 cmd_buffer->push_constant_stages &= ~stages;
1813 assert(cmd_buffer->cs->cdw <= cdw_max);
1814 }
1815
1816 static void
1817 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1818 bool pipeline_is_dirty)
1819 {
1820 if ((pipeline_is_dirty ||
1821 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1822 cmd_buffer->state.pipeline->vertex_elements.count &&
1823 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1824 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1825 unsigned vb_offset;
1826 void *vb_ptr;
1827 uint32_t i = 0;
1828 uint32_t count = velems->count;
1829 uint64_t va;
1830
1831 /* allocate some descriptor state for vertex buffers */
1832 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1833 &vb_offset, &vb_ptr))
1834 return;
1835
1836 for (i = 0; i < count; i++) {
1837 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1838 uint32_t offset;
1839 int vb = velems->binding[i];
1840 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1841 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1842
1843 va = radv_buffer_get_va(buffer->bo);
1844
1845 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1846 va += offset + buffer->offset;
1847 desc[0] = va;
1848 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1849 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1850 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1851 else
1852 desc[2] = buffer->size - offset;
1853 desc[3] = velems->rsrc_word3[i];
1854 }
1855
1856 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1857 va += vb_offset;
1858
1859 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1860 AC_UD_VS_VERTEX_BUFFERS, va);
1861
1862 cmd_buffer->state.vb_va = va;
1863 cmd_buffer->state.vb_size = count * 16;
1864 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1865 }
1866 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1867 }
1868
1869 static void
1870 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1871 {
1872 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1873 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1874 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1875 }
1876
1877 static void
1878 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1879 bool instanced_draw, bool indirect_draw,
1880 uint32_t draw_vertex_count)
1881 {
1882 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1883 struct radv_cmd_state *state = &cmd_buffer->state;
1884 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1885 uint32_t ia_multi_vgt_param;
1886 int32_t primitive_reset_en;
1887
1888 /* Draw state. */
1889 ia_multi_vgt_param =
1890 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1891 indirect_draw, draw_vertex_count);
1892
1893 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1894 if (info->chip_class >= GFX9) {
1895 radeon_set_uconfig_reg_idx(cs,
1896 R_030960_IA_MULTI_VGT_PARAM,
1897 4, ia_multi_vgt_param);
1898 } else if (info->chip_class >= CIK) {
1899 radeon_set_context_reg_idx(cs,
1900 R_028AA8_IA_MULTI_VGT_PARAM,
1901 1, ia_multi_vgt_param);
1902 } else {
1903 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1904 ia_multi_vgt_param);
1905 }
1906 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1907 }
1908
1909 /* Primitive restart. */
1910 primitive_reset_en =
1911 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1912
1913 if (primitive_reset_en != state->last_primitive_reset_en) {
1914 state->last_primitive_reset_en = primitive_reset_en;
1915 if (info->chip_class >= GFX9) {
1916 radeon_set_uconfig_reg(cs,
1917 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1918 primitive_reset_en);
1919 } else {
1920 radeon_set_context_reg(cs,
1921 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1922 primitive_reset_en);
1923 }
1924 }
1925
1926 if (primitive_reset_en) {
1927 uint32_t primitive_reset_index =
1928 state->index_type ? 0xffffffffu : 0xffffu;
1929
1930 if (primitive_reset_index != state->last_primitive_reset_index) {
1931 radeon_set_context_reg(cs,
1932 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1933 primitive_reset_index);
1934 state->last_primitive_reset_index = primitive_reset_index;
1935 }
1936 }
1937 }
1938
1939 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1940 VkPipelineStageFlags src_stage_mask)
1941 {
1942 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1943 VK_PIPELINE_STAGE_TRANSFER_BIT |
1944 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1945 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1946 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1947 }
1948
1949 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1950 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1951 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1952 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1953 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1954 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1955 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1956 VK_PIPELINE_STAGE_TRANSFER_BIT |
1957 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1958 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1959 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1960 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1961 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1962 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1963 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1964 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1965 }
1966 }
1967
1968 static enum radv_cmd_flush_bits
1969 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1970 VkAccessFlags src_flags)
1971 {
1972 enum radv_cmd_flush_bits flush_bits = 0;
1973 uint32_t b;
1974 for_each_bit(b, src_flags) {
1975 switch ((VkAccessFlagBits)(1 << b)) {
1976 case VK_ACCESS_SHADER_WRITE_BIT:
1977 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1978 break;
1979 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1980 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1981 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1982 break;
1983 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1984 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1985 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1986 break;
1987 case VK_ACCESS_TRANSFER_WRITE_BIT:
1988 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1989 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1990 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1991 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1992 RADV_CMD_FLAG_INV_GLOBAL_L2;
1993 break;
1994 default:
1995 break;
1996 }
1997 }
1998 return flush_bits;
1999 }
2000
2001 static enum radv_cmd_flush_bits
2002 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2003 VkAccessFlags dst_flags,
2004 struct radv_image *image)
2005 {
2006 enum radv_cmd_flush_bits flush_bits = 0;
2007 uint32_t b;
2008 for_each_bit(b, dst_flags) {
2009 switch ((VkAccessFlagBits)(1 << b)) {
2010 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2011 case VK_ACCESS_INDEX_READ_BIT:
2012 break;
2013 case VK_ACCESS_UNIFORM_READ_BIT:
2014 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2015 break;
2016 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2017 case VK_ACCESS_SHADER_READ_BIT:
2018 case VK_ACCESS_TRANSFER_READ_BIT:
2019 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2020 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2021 RADV_CMD_FLAG_INV_GLOBAL_L2;
2022 break;
2023 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2024 /* TODO: change to image && when the image gets passed
2025 * through from the subpass. */
2026 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2027 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2028 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2029 break;
2030 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2031 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2032 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2033 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2034 break;
2035 default:
2036 break;
2037 }
2038 }
2039 return flush_bits;
2040 }
2041
2042 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2043 {
2044 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2045 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2046 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2047 NULL);
2048 }
2049
2050 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2051 VkAttachmentReference att)
2052 {
2053 unsigned idx = att.attachment;
2054 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2055 VkImageSubresourceRange range;
2056 range.aspectMask = 0;
2057 range.baseMipLevel = view->base_mip;
2058 range.levelCount = 1;
2059 range.baseArrayLayer = view->base_layer;
2060 range.layerCount = cmd_buffer->state.framebuffer->layers;
2061
2062 radv_handle_image_transition(cmd_buffer,
2063 view->image,
2064 cmd_buffer->state.attachments[idx].current_layout,
2065 att.layout, 0, 0, &range,
2066 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2067
2068 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2069
2070
2071 }
2072
2073 void
2074 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2075 const struct radv_subpass *subpass, bool transitions)
2076 {
2077 if (transitions) {
2078 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2079
2080 for (unsigned i = 0; i < subpass->color_count; ++i) {
2081 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2082 radv_handle_subpass_image_transition(cmd_buffer,
2083 subpass->color_attachments[i]);
2084 }
2085
2086 for (unsigned i = 0; i < subpass->input_count; ++i) {
2087 radv_handle_subpass_image_transition(cmd_buffer,
2088 subpass->input_attachments[i]);
2089 }
2090
2091 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2092 radv_handle_subpass_image_transition(cmd_buffer,
2093 subpass->depth_stencil_attachment);
2094 }
2095 }
2096
2097 cmd_buffer->state.subpass = subpass;
2098
2099 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2100 }
2101
2102 static VkResult
2103 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2104 struct radv_render_pass *pass,
2105 const VkRenderPassBeginInfo *info)
2106 {
2107 struct radv_cmd_state *state = &cmd_buffer->state;
2108
2109 if (pass->attachment_count == 0) {
2110 state->attachments = NULL;
2111 return VK_SUCCESS;
2112 }
2113
2114 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2115 pass->attachment_count *
2116 sizeof(state->attachments[0]),
2117 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2118 if (state->attachments == NULL) {
2119 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2120 return cmd_buffer->record_result;
2121 }
2122
2123 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2124 struct radv_render_pass_attachment *att = &pass->attachments[i];
2125 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2126 VkImageAspectFlags clear_aspects = 0;
2127
2128 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2129 /* color attachment */
2130 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2131 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2132 }
2133 } else {
2134 /* depthstencil attachment */
2135 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2136 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2137 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2138 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2139 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2140 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2141 }
2142 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2143 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2144 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2145 }
2146 }
2147
2148 state->attachments[i].pending_clear_aspects = clear_aspects;
2149 state->attachments[i].cleared_views = 0;
2150 if (clear_aspects && info) {
2151 assert(info->clearValueCount > i);
2152 state->attachments[i].clear_value = info->pClearValues[i];
2153 }
2154
2155 state->attachments[i].current_layout = att->initial_layout;
2156 }
2157
2158 return VK_SUCCESS;
2159 }
2160
2161 VkResult radv_AllocateCommandBuffers(
2162 VkDevice _device,
2163 const VkCommandBufferAllocateInfo *pAllocateInfo,
2164 VkCommandBuffer *pCommandBuffers)
2165 {
2166 RADV_FROM_HANDLE(radv_device, device, _device);
2167 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2168
2169 VkResult result = VK_SUCCESS;
2170 uint32_t i;
2171
2172 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2173
2174 if (!list_empty(&pool->free_cmd_buffers)) {
2175 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2176
2177 list_del(&cmd_buffer->pool_link);
2178 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2179
2180 result = radv_reset_cmd_buffer(cmd_buffer);
2181 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2182 cmd_buffer->level = pAllocateInfo->level;
2183
2184 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2185 } else {
2186 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2187 &pCommandBuffers[i]);
2188 }
2189 if (result != VK_SUCCESS)
2190 break;
2191 }
2192
2193 if (result != VK_SUCCESS) {
2194 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2195 i, pCommandBuffers);
2196
2197 /* From the Vulkan 1.0.66 spec:
2198 *
2199 * "vkAllocateCommandBuffers can be used to create multiple
2200 * command buffers. If the creation of any of those command
2201 * buffers fails, the implementation must destroy all
2202 * successfully created command buffer objects from this
2203 * command, set all entries of the pCommandBuffers array to
2204 * NULL and return the error."
2205 */
2206 memset(pCommandBuffers, 0,
2207 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2208 }
2209
2210 return result;
2211 }
2212
2213 void radv_FreeCommandBuffers(
2214 VkDevice device,
2215 VkCommandPool commandPool,
2216 uint32_t commandBufferCount,
2217 const VkCommandBuffer *pCommandBuffers)
2218 {
2219 for (uint32_t i = 0; i < commandBufferCount; i++) {
2220 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2221
2222 if (cmd_buffer) {
2223 if (cmd_buffer->pool) {
2224 list_del(&cmd_buffer->pool_link);
2225 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2226 } else
2227 radv_cmd_buffer_destroy(cmd_buffer);
2228
2229 }
2230 }
2231 }
2232
2233 VkResult radv_ResetCommandBuffer(
2234 VkCommandBuffer commandBuffer,
2235 VkCommandBufferResetFlags flags)
2236 {
2237 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2238 return radv_reset_cmd_buffer(cmd_buffer);
2239 }
2240
2241 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2242 {
2243 struct radv_device *device = cmd_buffer->device;
2244 if (device->gfx_init) {
2245 uint64_t va = radv_buffer_get_va(device->gfx_init);
2246 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2247 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2248 radeon_emit(cmd_buffer->cs, va);
2249 radeon_emit(cmd_buffer->cs, va >> 32);
2250 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2251 } else
2252 si_init_config(cmd_buffer);
2253 }
2254
2255 VkResult radv_BeginCommandBuffer(
2256 VkCommandBuffer commandBuffer,
2257 const VkCommandBufferBeginInfo *pBeginInfo)
2258 {
2259 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2260 VkResult result = VK_SUCCESS;
2261
2262 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2263 /* If the command buffer has already been resetted with
2264 * vkResetCommandBuffer, no need to do it again.
2265 */
2266 result = radv_reset_cmd_buffer(cmd_buffer);
2267 if (result != VK_SUCCESS)
2268 return result;
2269 }
2270
2271 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2272 cmd_buffer->state.last_primitive_reset_en = -1;
2273 cmd_buffer->state.last_index_type = -1;
2274 cmd_buffer->state.last_num_instances = -1;
2275 cmd_buffer->state.last_vertex_offset = -1;
2276 cmd_buffer->state.last_first_instance = -1;
2277 cmd_buffer->usage_flags = pBeginInfo->flags;
2278
2279 /* setup initial configuration into command buffer */
2280 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2281 switch (cmd_buffer->queue_family_index) {
2282 case RADV_QUEUE_GENERAL:
2283 emit_gfx_buffer_state(cmd_buffer);
2284 break;
2285 case RADV_QUEUE_COMPUTE:
2286 si_init_compute(cmd_buffer);
2287 break;
2288 case RADV_QUEUE_TRANSFER:
2289 default:
2290 break;
2291 }
2292 }
2293
2294 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2295 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2296 assert(pBeginInfo->pInheritanceInfo);
2297 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2298 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2299
2300 struct radv_subpass *subpass =
2301 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2302
2303 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2304 if (result != VK_SUCCESS)
2305 return result;
2306
2307 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2308 }
2309
2310 if (unlikely(cmd_buffer->device->trace_bo))
2311 radv_cmd_buffer_trace_emit(cmd_buffer);
2312
2313 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2314
2315 return result;
2316 }
2317
2318 void radv_CmdBindVertexBuffers(
2319 VkCommandBuffer commandBuffer,
2320 uint32_t firstBinding,
2321 uint32_t bindingCount,
2322 const VkBuffer* pBuffers,
2323 const VkDeviceSize* pOffsets)
2324 {
2325 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2326 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2327 bool changed = false;
2328
2329 /* We have to defer setting up vertex buffer since we need the buffer
2330 * stride from the pipeline. */
2331
2332 assert(firstBinding + bindingCount <= MAX_VBS);
2333 for (uint32_t i = 0; i < bindingCount; i++) {
2334 uint32_t idx = firstBinding + i;
2335
2336 if (!changed &&
2337 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2338 vb[idx].offset != pOffsets[i])) {
2339 changed = true;
2340 }
2341
2342 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2343 vb[idx].offset = pOffsets[i];
2344
2345 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2346 vb[idx].buffer->bo, 8);
2347 }
2348
2349 if (!changed) {
2350 /* No state changes. */
2351 return;
2352 }
2353
2354 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2355 }
2356
2357 void radv_CmdBindIndexBuffer(
2358 VkCommandBuffer commandBuffer,
2359 VkBuffer buffer,
2360 VkDeviceSize offset,
2361 VkIndexType indexType)
2362 {
2363 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2364 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2365
2366 if (cmd_buffer->state.index_buffer == index_buffer &&
2367 cmd_buffer->state.index_offset == offset &&
2368 cmd_buffer->state.index_type == indexType) {
2369 /* No state changes. */
2370 return;
2371 }
2372
2373 cmd_buffer->state.index_buffer = index_buffer;
2374 cmd_buffer->state.index_offset = offset;
2375 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2376 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2377 cmd_buffer->state.index_va += index_buffer->offset + offset;
2378
2379 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2380 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2381 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2382 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2383 }
2384
2385
2386 static void
2387 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2388 VkPipelineBindPoint bind_point,
2389 struct radv_descriptor_set *set, unsigned idx)
2390 {
2391 struct radeon_winsys *ws = cmd_buffer->device->ws;
2392
2393 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2394 if (!set)
2395 return;
2396
2397 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2398
2399 if (!cmd_buffer->device->use_global_bo_list) {
2400 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2401 if (set->descriptors[j])
2402 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2403 }
2404
2405 if(set->bo)
2406 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2407 }
2408
2409 void radv_CmdBindDescriptorSets(
2410 VkCommandBuffer commandBuffer,
2411 VkPipelineBindPoint pipelineBindPoint,
2412 VkPipelineLayout _layout,
2413 uint32_t firstSet,
2414 uint32_t descriptorSetCount,
2415 const VkDescriptorSet* pDescriptorSets,
2416 uint32_t dynamicOffsetCount,
2417 const uint32_t* pDynamicOffsets)
2418 {
2419 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2420 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2421 unsigned dyn_idx = 0;
2422
2423 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2424 struct radv_descriptor_state *descriptors_state =
2425 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2426
2427 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2428 unsigned idx = i + firstSet;
2429 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2430 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2431
2432 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2433 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2434 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2435 assert(dyn_idx < dynamicOffsetCount);
2436
2437 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2438 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2439 dst[0] = va;
2440 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2441 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2442 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2443 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2444 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2445 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2446 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2447 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2448 cmd_buffer->push_constant_stages |=
2449 set->layout->dynamic_shader_stages;
2450 }
2451 }
2452 }
2453
2454 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2455 struct radv_descriptor_set *set,
2456 struct radv_descriptor_set_layout *layout,
2457 VkPipelineBindPoint bind_point)
2458 {
2459 struct radv_descriptor_state *descriptors_state =
2460 radv_get_descriptors_state(cmd_buffer, bind_point);
2461 set->size = layout->size;
2462 set->layout = layout;
2463
2464 if (descriptors_state->push_set.capacity < set->size) {
2465 size_t new_size = MAX2(set->size, 1024);
2466 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2467 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2468
2469 free(set->mapped_ptr);
2470 set->mapped_ptr = malloc(new_size);
2471
2472 if (!set->mapped_ptr) {
2473 descriptors_state->push_set.capacity = 0;
2474 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2475 return false;
2476 }
2477
2478 descriptors_state->push_set.capacity = new_size;
2479 }
2480
2481 return true;
2482 }
2483
2484 void radv_meta_push_descriptor_set(
2485 struct radv_cmd_buffer* cmd_buffer,
2486 VkPipelineBindPoint pipelineBindPoint,
2487 VkPipelineLayout _layout,
2488 uint32_t set,
2489 uint32_t descriptorWriteCount,
2490 const VkWriteDescriptorSet* pDescriptorWrites)
2491 {
2492 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2493 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2494 unsigned bo_offset;
2495
2496 assert(set == 0);
2497 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2498
2499 push_set->size = layout->set[set].layout->size;
2500 push_set->layout = layout->set[set].layout;
2501
2502 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2503 &bo_offset,
2504 (void**) &push_set->mapped_ptr))
2505 return;
2506
2507 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2508 push_set->va += bo_offset;
2509
2510 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2511 radv_descriptor_set_to_handle(push_set),
2512 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2513
2514 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2515 }
2516
2517 void radv_CmdPushDescriptorSetKHR(
2518 VkCommandBuffer commandBuffer,
2519 VkPipelineBindPoint pipelineBindPoint,
2520 VkPipelineLayout _layout,
2521 uint32_t set,
2522 uint32_t descriptorWriteCount,
2523 const VkWriteDescriptorSet* pDescriptorWrites)
2524 {
2525 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2526 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2527 struct radv_descriptor_state *descriptors_state =
2528 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2529 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2530
2531 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2532
2533 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2534 layout->set[set].layout,
2535 pipelineBindPoint))
2536 return;
2537
2538 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2539 radv_descriptor_set_to_handle(push_set),
2540 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2541
2542 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2543 descriptors_state->push_dirty = true;
2544 }
2545
2546 void radv_CmdPushDescriptorSetWithTemplateKHR(
2547 VkCommandBuffer commandBuffer,
2548 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2549 VkPipelineLayout _layout,
2550 uint32_t set,
2551 const void* pData)
2552 {
2553 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2554 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2555 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2556 struct radv_descriptor_state *descriptors_state =
2557 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2558 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2559
2560 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2561
2562 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2563 layout->set[set].layout,
2564 templ->bind_point))
2565 return;
2566
2567 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2568 descriptorUpdateTemplate, pData);
2569
2570 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2571 descriptors_state->push_dirty = true;
2572 }
2573
2574 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2575 VkPipelineLayout layout,
2576 VkShaderStageFlags stageFlags,
2577 uint32_t offset,
2578 uint32_t size,
2579 const void* pValues)
2580 {
2581 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2582 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2583 cmd_buffer->push_constant_stages |= stageFlags;
2584 }
2585
2586 VkResult radv_EndCommandBuffer(
2587 VkCommandBuffer commandBuffer)
2588 {
2589 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2590
2591 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2592 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2593 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2594 si_emit_cache_flush(cmd_buffer);
2595 }
2596
2597 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2598
2599 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2600 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2601
2602 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2603
2604 return cmd_buffer->record_result;
2605 }
2606
2607 static void
2608 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2609 {
2610 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2611
2612 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2613 return;
2614
2615 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2616
2617 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2618 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2619
2620 cmd_buffer->compute_scratch_size_needed =
2621 MAX2(cmd_buffer->compute_scratch_size_needed,
2622 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2623
2624 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2625 pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
2626
2627 if (unlikely(cmd_buffer->device->trace_bo))
2628 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2629 }
2630
2631 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2632 VkPipelineBindPoint bind_point)
2633 {
2634 struct radv_descriptor_state *descriptors_state =
2635 radv_get_descriptors_state(cmd_buffer, bind_point);
2636
2637 descriptors_state->dirty |= descriptors_state->valid;
2638 }
2639
2640 void radv_CmdBindPipeline(
2641 VkCommandBuffer commandBuffer,
2642 VkPipelineBindPoint pipelineBindPoint,
2643 VkPipeline _pipeline)
2644 {
2645 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2646 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2647
2648 switch (pipelineBindPoint) {
2649 case VK_PIPELINE_BIND_POINT_COMPUTE:
2650 if (cmd_buffer->state.compute_pipeline == pipeline)
2651 return;
2652 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2653
2654 cmd_buffer->state.compute_pipeline = pipeline;
2655 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2656 break;
2657 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2658 if (cmd_buffer->state.pipeline == pipeline)
2659 return;
2660 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2661
2662 cmd_buffer->state.pipeline = pipeline;
2663 if (!pipeline)
2664 break;
2665
2666 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2667 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2668
2669 /* the new vertex shader might not have the same user regs */
2670 cmd_buffer->state.last_first_instance = -1;
2671 cmd_buffer->state.last_vertex_offset = -1;
2672
2673 /* Prefetch all pipeline shaders at first draw time. */
2674 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2675
2676 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2677
2678 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2679 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2680 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2681 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2682
2683 if (radv_pipeline_has_tess(pipeline))
2684 cmd_buffer->tess_rings_needed = true;
2685
2686 if (radv_pipeline_has_gs(pipeline)) {
2687 struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2688 AC_UD_SCRATCH_RING_OFFSETS);
2689 if (cmd_buffer->ring_offsets_idx == -1)
2690 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2691 else if (loc->sgpr_idx != -1)
2692 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2693 }
2694 break;
2695 default:
2696 assert(!"invalid bind point");
2697 break;
2698 }
2699 }
2700
2701 void radv_CmdSetViewport(
2702 VkCommandBuffer commandBuffer,
2703 uint32_t firstViewport,
2704 uint32_t viewportCount,
2705 const VkViewport* pViewports)
2706 {
2707 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2708 struct radv_cmd_state *state = &cmd_buffer->state;
2709 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2710
2711 assert(firstViewport < MAX_VIEWPORTS);
2712 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2713
2714 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2715 viewportCount * sizeof(*pViewports));
2716
2717 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2718 }
2719
2720 void radv_CmdSetScissor(
2721 VkCommandBuffer commandBuffer,
2722 uint32_t firstScissor,
2723 uint32_t scissorCount,
2724 const VkRect2D* pScissors)
2725 {
2726 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2727 struct radv_cmd_state *state = &cmd_buffer->state;
2728 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2729
2730 assert(firstScissor < MAX_SCISSORS);
2731 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2732
2733 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2734 scissorCount * sizeof(*pScissors));
2735
2736 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2737 }
2738
2739 void radv_CmdSetLineWidth(
2740 VkCommandBuffer commandBuffer,
2741 float lineWidth)
2742 {
2743 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2744 cmd_buffer->state.dynamic.line_width = lineWidth;
2745 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2746 }
2747
2748 void radv_CmdSetDepthBias(
2749 VkCommandBuffer commandBuffer,
2750 float depthBiasConstantFactor,
2751 float depthBiasClamp,
2752 float depthBiasSlopeFactor)
2753 {
2754 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2755
2756 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2757 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2758 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2759
2760 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2761 }
2762
2763 void radv_CmdSetBlendConstants(
2764 VkCommandBuffer commandBuffer,
2765 const float blendConstants[4])
2766 {
2767 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2768
2769 memcpy(cmd_buffer->state.dynamic.blend_constants,
2770 blendConstants, sizeof(float) * 4);
2771
2772 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2773 }
2774
2775 void radv_CmdSetDepthBounds(
2776 VkCommandBuffer commandBuffer,
2777 float minDepthBounds,
2778 float maxDepthBounds)
2779 {
2780 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2781
2782 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2783 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2784
2785 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2786 }
2787
2788 void radv_CmdSetStencilCompareMask(
2789 VkCommandBuffer commandBuffer,
2790 VkStencilFaceFlags faceMask,
2791 uint32_t compareMask)
2792 {
2793 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2794
2795 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2796 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2797 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2798 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2799
2800 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2801 }
2802
2803 void radv_CmdSetStencilWriteMask(
2804 VkCommandBuffer commandBuffer,
2805 VkStencilFaceFlags faceMask,
2806 uint32_t writeMask)
2807 {
2808 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2809
2810 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2811 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2812 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2813 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2814
2815 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2816 }
2817
2818 void radv_CmdSetStencilReference(
2819 VkCommandBuffer commandBuffer,
2820 VkStencilFaceFlags faceMask,
2821 uint32_t reference)
2822 {
2823 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2824
2825 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2826 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2827 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2828 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2829
2830 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2831 }
2832
2833 void radv_CmdSetDiscardRectangleEXT(
2834 VkCommandBuffer commandBuffer,
2835 uint32_t firstDiscardRectangle,
2836 uint32_t discardRectangleCount,
2837 const VkRect2D* pDiscardRectangles)
2838 {
2839 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2840 struct radv_cmd_state *state = &cmd_buffer->state;
2841 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2842
2843 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2844 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2845
2846 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2847 pDiscardRectangles, discardRectangleCount);
2848
2849 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2850 }
2851
2852 void radv_CmdExecuteCommands(
2853 VkCommandBuffer commandBuffer,
2854 uint32_t commandBufferCount,
2855 const VkCommandBuffer* pCmdBuffers)
2856 {
2857 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2858
2859 assert(commandBufferCount > 0);
2860
2861 /* Emit pending flushes on primary prior to executing secondary */
2862 si_emit_cache_flush(primary);
2863
2864 for (uint32_t i = 0; i < commandBufferCount; i++) {
2865 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2866
2867 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2868 secondary->scratch_size_needed);
2869 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2870 secondary->compute_scratch_size_needed);
2871
2872 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2873 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2874 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2875 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2876 if (secondary->tess_rings_needed)
2877 primary->tess_rings_needed = true;
2878 if (secondary->sample_positions_needed)
2879 primary->sample_positions_needed = true;
2880
2881 if (secondary->ring_offsets_idx != -1) {
2882 if (primary->ring_offsets_idx == -1)
2883 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2884 else
2885 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2886 }
2887 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2888
2889
2890 /* When the secondary command buffer is compute only we don't
2891 * need to re-emit the current graphics pipeline.
2892 */
2893 if (secondary->state.emitted_pipeline) {
2894 primary->state.emitted_pipeline =
2895 secondary->state.emitted_pipeline;
2896 }
2897
2898 /* When the secondary command buffer is graphics only we don't
2899 * need to re-emit the current compute pipeline.
2900 */
2901 if (secondary->state.emitted_compute_pipeline) {
2902 primary->state.emitted_compute_pipeline =
2903 secondary->state.emitted_compute_pipeline;
2904 }
2905
2906 /* Only re-emit the draw packets when needed. */
2907 if (secondary->state.last_primitive_reset_en != -1) {
2908 primary->state.last_primitive_reset_en =
2909 secondary->state.last_primitive_reset_en;
2910 }
2911
2912 if (secondary->state.last_primitive_reset_index) {
2913 primary->state.last_primitive_reset_index =
2914 secondary->state.last_primitive_reset_index;
2915 }
2916
2917 if (secondary->state.last_ia_multi_vgt_param) {
2918 primary->state.last_ia_multi_vgt_param =
2919 secondary->state.last_ia_multi_vgt_param;
2920 }
2921
2922 primary->state.last_first_instance = secondary->state.last_first_instance;
2923 primary->state.last_num_instances = secondary->state.last_num_instances;
2924 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2925
2926 if (secondary->state.last_index_type != -1) {
2927 primary->state.last_index_type =
2928 secondary->state.last_index_type;
2929 }
2930 }
2931
2932 /* After executing commands from secondary buffers we have to dirty
2933 * some states.
2934 */
2935 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2936 RADV_CMD_DIRTY_INDEX_BUFFER |
2937 RADV_CMD_DIRTY_DYNAMIC_ALL;
2938 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2939 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2940 }
2941
2942 VkResult radv_CreateCommandPool(
2943 VkDevice _device,
2944 const VkCommandPoolCreateInfo* pCreateInfo,
2945 const VkAllocationCallbacks* pAllocator,
2946 VkCommandPool* pCmdPool)
2947 {
2948 RADV_FROM_HANDLE(radv_device, device, _device);
2949 struct radv_cmd_pool *pool;
2950
2951 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2952 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2953 if (pool == NULL)
2954 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2955
2956 if (pAllocator)
2957 pool->alloc = *pAllocator;
2958 else
2959 pool->alloc = device->alloc;
2960
2961 list_inithead(&pool->cmd_buffers);
2962 list_inithead(&pool->free_cmd_buffers);
2963
2964 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2965
2966 *pCmdPool = radv_cmd_pool_to_handle(pool);
2967
2968 return VK_SUCCESS;
2969
2970 }
2971
2972 void radv_DestroyCommandPool(
2973 VkDevice _device,
2974 VkCommandPool commandPool,
2975 const VkAllocationCallbacks* pAllocator)
2976 {
2977 RADV_FROM_HANDLE(radv_device, device, _device);
2978 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2979
2980 if (!pool)
2981 return;
2982
2983 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2984 &pool->cmd_buffers, pool_link) {
2985 radv_cmd_buffer_destroy(cmd_buffer);
2986 }
2987
2988 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2989 &pool->free_cmd_buffers, pool_link) {
2990 radv_cmd_buffer_destroy(cmd_buffer);
2991 }
2992
2993 vk_free2(&device->alloc, pAllocator, pool);
2994 }
2995
2996 VkResult radv_ResetCommandPool(
2997 VkDevice device,
2998 VkCommandPool commandPool,
2999 VkCommandPoolResetFlags flags)
3000 {
3001 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3002 VkResult result;
3003
3004 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3005 &pool->cmd_buffers, pool_link) {
3006 result = radv_reset_cmd_buffer(cmd_buffer);
3007 if (result != VK_SUCCESS)
3008 return result;
3009 }
3010
3011 return VK_SUCCESS;
3012 }
3013
3014 void radv_TrimCommandPool(
3015 VkDevice device,
3016 VkCommandPool commandPool,
3017 VkCommandPoolTrimFlagsKHR flags)
3018 {
3019 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3020
3021 if (!pool)
3022 return;
3023
3024 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3025 &pool->free_cmd_buffers, pool_link) {
3026 radv_cmd_buffer_destroy(cmd_buffer);
3027 }
3028 }
3029
3030 void radv_CmdBeginRenderPass(
3031 VkCommandBuffer commandBuffer,
3032 const VkRenderPassBeginInfo* pRenderPassBegin,
3033 VkSubpassContents contents)
3034 {
3035 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3036 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3037 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3038
3039 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3040 cmd_buffer->cs, 2048);
3041 MAYBE_UNUSED VkResult result;
3042
3043 cmd_buffer->state.framebuffer = framebuffer;
3044 cmd_buffer->state.pass = pass;
3045 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3046
3047 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3048 if (result != VK_SUCCESS)
3049 return;
3050
3051 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3052 assert(cmd_buffer->cs->cdw <= cdw_max);
3053
3054 radv_cmd_buffer_clear_subpass(cmd_buffer);
3055 }
3056
3057 void radv_CmdNextSubpass(
3058 VkCommandBuffer commandBuffer,
3059 VkSubpassContents contents)
3060 {
3061 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3062
3063 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3064
3065 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3066 2048);
3067
3068 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3069 radv_cmd_buffer_clear_subpass(cmd_buffer);
3070 }
3071
3072 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3073 {
3074 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3075 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3076 if (!pipeline->shaders[stage])
3077 continue;
3078 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3079 if (loc->sgpr_idx == -1)
3080 continue;
3081 uint32_t base_reg = pipeline->user_data_0[stage];
3082 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3083
3084 }
3085 if (pipeline->gs_copy_shader) {
3086 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3087 if (loc->sgpr_idx != -1) {
3088 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3089 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3090 }
3091 }
3092 }
3093
3094 static void
3095 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3096 uint32_t vertex_count)
3097 {
3098 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3099 radeon_emit(cmd_buffer->cs, vertex_count);
3100 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3101 S_0287F0_USE_OPAQUE(0));
3102 }
3103
3104 static void
3105 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3106 uint64_t index_va,
3107 uint32_t index_count)
3108 {
3109 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3110 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3111 radeon_emit(cmd_buffer->cs, index_va);
3112 radeon_emit(cmd_buffer->cs, index_va >> 32);
3113 radeon_emit(cmd_buffer->cs, index_count);
3114 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3115 }
3116
3117 static void
3118 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3119 bool indexed,
3120 uint32_t draw_count,
3121 uint64_t count_va,
3122 uint32_t stride)
3123 {
3124 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3125 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3126 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3127 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3128 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3129 assert(base_reg);
3130
3131 /* just reset draw state for vertex data */
3132 cmd_buffer->state.last_first_instance = -1;
3133 cmd_buffer->state.last_num_instances = -1;
3134 cmd_buffer->state.last_vertex_offset = -1;
3135
3136 if (draw_count == 1 && !count_va && !draw_id_enable) {
3137 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3138 PKT3_DRAW_INDIRECT, 3, false));
3139 radeon_emit(cs, 0);
3140 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3141 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3142 radeon_emit(cs, di_src_sel);
3143 } else {
3144 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3145 PKT3_DRAW_INDIRECT_MULTI,
3146 8, false));
3147 radeon_emit(cs, 0);
3148 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3149 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3150 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3151 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3152 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3153 radeon_emit(cs, draw_count); /* count */
3154 radeon_emit(cs, count_va); /* count_addr */
3155 radeon_emit(cs, count_va >> 32);
3156 radeon_emit(cs, stride); /* stride */
3157 radeon_emit(cs, di_src_sel);
3158 }
3159 }
3160
3161 struct radv_draw_info {
3162 /**
3163 * Number of vertices.
3164 */
3165 uint32_t count;
3166
3167 /**
3168 * Index of the first vertex.
3169 */
3170 int32_t vertex_offset;
3171
3172 /**
3173 * First instance id.
3174 */
3175 uint32_t first_instance;
3176
3177 /**
3178 * Number of instances.
3179 */
3180 uint32_t instance_count;
3181
3182 /**
3183 * First index (indexed draws only).
3184 */
3185 uint32_t first_index;
3186
3187 /**
3188 * Whether it's an indexed draw.
3189 */
3190 bool indexed;
3191
3192 /**
3193 * Indirect draw parameters resource.
3194 */
3195 struct radv_buffer *indirect;
3196 uint64_t indirect_offset;
3197 uint32_t stride;
3198
3199 /**
3200 * Draw count parameters resource.
3201 */
3202 struct radv_buffer *count_buffer;
3203 uint64_t count_buffer_offset;
3204 };
3205
3206 static void
3207 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3208 const struct radv_draw_info *info)
3209 {
3210 struct radv_cmd_state *state = &cmd_buffer->state;
3211 struct radeon_winsys *ws = cmd_buffer->device->ws;
3212 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3213
3214 if (info->indirect) {
3215 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3216 uint64_t count_va = 0;
3217
3218 va += info->indirect->offset + info->indirect_offset;
3219
3220 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3221
3222 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3223 radeon_emit(cs, 1);
3224 radeon_emit(cs, va);
3225 radeon_emit(cs, va >> 32);
3226
3227 if (info->count_buffer) {
3228 count_va = radv_buffer_get_va(info->count_buffer->bo);
3229 count_va += info->count_buffer->offset +
3230 info->count_buffer_offset;
3231
3232 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3233 }
3234
3235 if (!state->subpass->view_mask) {
3236 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3237 info->indexed,
3238 info->count,
3239 count_va,
3240 info->stride);
3241 } else {
3242 unsigned i;
3243 for_each_bit(i, state->subpass->view_mask) {
3244 radv_emit_view_index(cmd_buffer, i);
3245
3246 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3247 info->indexed,
3248 info->count,
3249 count_va,
3250 info->stride);
3251 }
3252 }
3253 } else {
3254 assert(state->pipeline->graphics.vtx_base_sgpr);
3255
3256 if (info->vertex_offset != state->last_vertex_offset ||
3257 info->first_instance != state->last_first_instance) {
3258 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3259 state->pipeline->graphics.vtx_emit_num);
3260
3261 radeon_emit(cs, info->vertex_offset);
3262 radeon_emit(cs, info->first_instance);
3263 if (state->pipeline->graphics.vtx_emit_num == 3)
3264 radeon_emit(cs, 0);
3265 state->last_first_instance = info->first_instance;
3266 state->last_vertex_offset = info->vertex_offset;
3267 }
3268
3269 if (state->last_num_instances != info->instance_count) {
3270 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3271 radeon_emit(cs, info->instance_count);
3272 state->last_num_instances = info->instance_count;
3273 }
3274
3275 if (info->indexed) {
3276 int index_size = state->index_type ? 4 : 2;
3277 uint64_t index_va;
3278
3279 index_va = state->index_va;
3280 index_va += info->first_index * index_size;
3281
3282 if (!state->subpass->view_mask) {
3283 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3284 index_va,
3285 info->count);
3286 } else {
3287 unsigned i;
3288 for_each_bit(i, state->subpass->view_mask) {
3289 radv_emit_view_index(cmd_buffer, i);
3290
3291 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3292 index_va,
3293 info->count);
3294 }
3295 }
3296 } else {
3297 if (!state->subpass->view_mask) {
3298 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3299 } else {
3300 unsigned i;
3301 for_each_bit(i, state->subpass->view_mask) {
3302 radv_emit_view_index(cmd_buffer, i);
3303
3304 radv_cs_emit_draw_packet(cmd_buffer,
3305 info->count);
3306 }
3307 }
3308 }
3309 }
3310 }
3311
3312 /*
3313 * Vega and raven have a bug which triggers if there are multiple context
3314 * register contexts active at the same time with different scissor values.
3315 *
3316 * There are two possible workarounds:
3317 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3318 * there is only ever 1 active set of scissor values at the same time.
3319 *
3320 * 2) Whenever the hardware switches contexts we have to set the scissor
3321 * registers again even if it is a noop. That way the new context gets
3322 * the correct scissor values.
3323 *
3324 * This implements option 2. radv_need_late_scissor_emission needs to
3325 * return true on affected HW if radv_emit_all_graphics_states sets
3326 * any context registers.
3327 */
3328 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3329 bool indexed_draw)
3330 {
3331 struct radv_cmd_state *state = &cmd_buffer->state;
3332
3333 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3334 return false;
3335
3336 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3337
3338 /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3339 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_VERTEX_BUFFER | RADV_CMD_DIRTY_PIPELINE);
3340
3341 /* Assume all state changes except these two can imply context rolls. */
3342 if (cmd_buffer->state.dirty & used_states)
3343 return true;
3344
3345 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3346 return true;
3347
3348 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3349 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3350 return true;
3351
3352 return false;
3353 }
3354
3355 static void
3356 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3357 const struct radv_draw_info *info)
3358 {
3359 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3360
3361 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3362 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3363 radv_emit_rbplus_state(cmd_buffer);
3364
3365 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3366 radv_emit_graphics_pipeline(cmd_buffer);
3367
3368 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3369 radv_emit_framebuffer_state(cmd_buffer);
3370
3371 if (info->indexed) {
3372 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3373 radv_emit_index_buffer(cmd_buffer);
3374 } else {
3375 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3376 * so the state must be re-emitted before the next indexed
3377 * draw.
3378 */
3379 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3380 cmd_buffer->state.last_index_type = -1;
3381 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3382 }
3383 }
3384
3385 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3386
3387 radv_emit_draw_registers(cmd_buffer, info->indexed,
3388 info->instance_count > 1, info->indirect,
3389 info->indirect ? 0 : info->count);
3390
3391 if (late_scissor_emission)
3392 radv_emit_scissor(cmd_buffer);
3393 }
3394
3395 static void
3396 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3397 const struct radv_draw_info *info)
3398 {
3399 bool has_prefetch =
3400 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3401 bool pipeline_is_dirty =
3402 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3403 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3404
3405 MAYBE_UNUSED unsigned cdw_max =
3406 radeon_check_space(cmd_buffer->device->ws,
3407 cmd_buffer->cs, 4096);
3408
3409 /* Use optimal packet order based on whether we need to sync the
3410 * pipeline.
3411 */
3412 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3413 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3414 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3415 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3416 /* If we have to wait for idle, set all states first, so that
3417 * all SET packets are processed in parallel with previous draw
3418 * calls. Then upload descriptors, set shader pointers, and
3419 * draw, and prefetch at the end. This ensures that the time
3420 * the CUs are idle is very short. (there are only SET_SH
3421 * packets between the wait and the draw)
3422 */
3423 radv_emit_all_graphics_states(cmd_buffer, info);
3424 si_emit_cache_flush(cmd_buffer);
3425 /* <-- CUs are idle here --> */
3426
3427 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3428
3429 radv_emit_draw_packets(cmd_buffer, info);
3430 /* <-- CUs are busy here --> */
3431
3432 /* Start prefetches after the draw has been started. Both will
3433 * run in parallel, but starting the draw first is more
3434 * important.
3435 */
3436 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3437 radv_emit_prefetch_L2(cmd_buffer,
3438 cmd_buffer->state.pipeline, false);
3439 }
3440 } else {
3441 /* If we don't wait for idle, start prefetches first, then set
3442 * states, and draw at the end.
3443 */
3444 si_emit_cache_flush(cmd_buffer);
3445
3446 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3447 /* Only prefetch the vertex shader and VBO descriptors
3448 * in order to start the draw as soon as possible.
3449 */
3450 radv_emit_prefetch_L2(cmd_buffer,
3451 cmd_buffer->state.pipeline, true);
3452 }
3453
3454 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3455
3456 radv_emit_all_graphics_states(cmd_buffer, info);
3457 radv_emit_draw_packets(cmd_buffer, info);
3458
3459 /* Prefetch the remaining shaders after the draw has been
3460 * started.
3461 */
3462 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3463 radv_emit_prefetch_L2(cmd_buffer,
3464 cmd_buffer->state.pipeline, false);
3465 }
3466 }
3467
3468 assert(cmd_buffer->cs->cdw <= cdw_max);
3469 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3470 }
3471
3472 void radv_CmdDraw(
3473 VkCommandBuffer commandBuffer,
3474 uint32_t vertexCount,
3475 uint32_t instanceCount,
3476 uint32_t firstVertex,
3477 uint32_t firstInstance)
3478 {
3479 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3480 struct radv_draw_info info = {};
3481
3482 info.count = vertexCount;
3483 info.instance_count = instanceCount;
3484 info.first_instance = firstInstance;
3485 info.vertex_offset = firstVertex;
3486
3487 radv_draw(cmd_buffer, &info);
3488 }
3489
3490 void radv_CmdDrawIndexed(
3491 VkCommandBuffer commandBuffer,
3492 uint32_t indexCount,
3493 uint32_t instanceCount,
3494 uint32_t firstIndex,
3495 int32_t vertexOffset,
3496 uint32_t firstInstance)
3497 {
3498 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3499 struct radv_draw_info info = {};
3500
3501 info.indexed = true;
3502 info.count = indexCount;
3503 info.instance_count = instanceCount;
3504 info.first_index = firstIndex;
3505 info.vertex_offset = vertexOffset;
3506 info.first_instance = firstInstance;
3507
3508 radv_draw(cmd_buffer, &info);
3509 }
3510
3511 void radv_CmdDrawIndirect(
3512 VkCommandBuffer commandBuffer,
3513 VkBuffer _buffer,
3514 VkDeviceSize offset,
3515 uint32_t drawCount,
3516 uint32_t stride)
3517 {
3518 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3519 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3520 struct radv_draw_info info = {};
3521
3522 info.count = drawCount;
3523 info.indirect = buffer;
3524 info.indirect_offset = offset;
3525 info.stride = stride;
3526
3527 radv_draw(cmd_buffer, &info);
3528 }
3529
3530 void radv_CmdDrawIndexedIndirect(
3531 VkCommandBuffer commandBuffer,
3532 VkBuffer _buffer,
3533 VkDeviceSize offset,
3534 uint32_t drawCount,
3535 uint32_t stride)
3536 {
3537 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3538 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3539 struct radv_draw_info info = {};
3540
3541 info.indexed = true;
3542 info.count = drawCount;
3543 info.indirect = buffer;
3544 info.indirect_offset = offset;
3545 info.stride = stride;
3546
3547 radv_draw(cmd_buffer, &info);
3548 }
3549
3550 void radv_CmdDrawIndirectCountAMD(
3551 VkCommandBuffer commandBuffer,
3552 VkBuffer _buffer,
3553 VkDeviceSize offset,
3554 VkBuffer _countBuffer,
3555 VkDeviceSize countBufferOffset,
3556 uint32_t maxDrawCount,
3557 uint32_t stride)
3558 {
3559 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3560 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3561 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3562 struct radv_draw_info info = {};
3563
3564 info.count = maxDrawCount;
3565 info.indirect = buffer;
3566 info.indirect_offset = offset;
3567 info.count_buffer = count_buffer;
3568 info.count_buffer_offset = countBufferOffset;
3569 info.stride = stride;
3570
3571 radv_draw(cmd_buffer, &info);
3572 }
3573
3574 void radv_CmdDrawIndexedIndirectCountAMD(
3575 VkCommandBuffer commandBuffer,
3576 VkBuffer _buffer,
3577 VkDeviceSize offset,
3578 VkBuffer _countBuffer,
3579 VkDeviceSize countBufferOffset,
3580 uint32_t maxDrawCount,
3581 uint32_t stride)
3582 {
3583 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3584 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3585 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3586 struct radv_draw_info info = {};
3587
3588 info.indexed = true;
3589 info.count = maxDrawCount;
3590 info.indirect = buffer;
3591 info.indirect_offset = offset;
3592 info.count_buffer = count_buffer;
3593 info.count_buffer_offset = countBufferOffset;
3594 info.stride = stride;
3595
3596 radv_draw(cmd_buffer, &info);
3597 }
3598
3599 void radv_CmdDrawIndirectCountKHR(
3600 VkCommandBuffer commandBuffer,
3601 VkBuffer _buffer,
3602 VkDeviceSize offset,
3603 VkBuffer _countBuffer,
3604 VkDeviceSize countBufferOffset,
3605 uint32_t maxDrawCount,
3606 uint32_t stride)
3607 {
3608 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3609 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3610 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3611 struct radv_draw_info info = {};
3612
3613 info.count = maxDrawCount;
3614 info.indirect = buffer;
3615 info.indirect_offset = offset;
3616 info.count_buffer = count_buffer;
3617 info.count_buffer_offset = countBufferOffset;
3618 info.stride = stride;
3619
3620 radv_draw(cmd_buffer, &info);
3621 }
3622
3623 void radv_CmdDrawIndexedIndirectCountKHR(
3624 VkCommandBuffer commandBuffer,
3625 VkBuffer _buffer,
3626 VkDeviceSize offset,
3627 VkBuffer _countBuffer,
3628 VkDeviceSize countBufferOffset,
3629 uint32_t maxDrawCount,
3630 uint32_t stride)
3631 {
3632 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3633 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3634 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3635 struct radv_draw_info info = {};
3636
3637 info.indexed = true;
3638 info.count = maxDrawCount;
3639 info.indirect = buffer;
3640 info.indirect_offset = offset;
3641 info.count_buffer = count_buffer;
3642 info.count_buffer_offset = countBufferOffset;
3643 info.stride = stride;
3644
3645 radv_draw(cmd_buffer, &info);
3646 }
3647
3648 struct radv_dispatch_info {
3649 /**
3650 * Determine the layout of the grid (in block units) to be used.
3651 */
3652 uint32_t blocks[3];
3653
3654 /**
3655 * A starting offset for the grid. If unaligned is set, the offset
3656 * must still be aligned.
3657 */
3658 uint32_t offsets[3];
3659 /**
3660 * Whether it's an unaligned compute dispatch.
3661 */
3662 bool unaligned;
3663
3664 /**
3665 * Indirect compute parameters resource.
3666 */
3667 struct radv_buffer *indirect;
3668 uint64_t indirect_offset;
3669 };
3670
3671 static void
3672 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3673 const struct radv_dispatch_info *info)
3674 {
3675 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3676 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3677 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3678 struct radeon_winsys *ws = cmd_buffer->device->ws;
3679 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3680 struct radv_userdata_info *loc;
3681
3682 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3683 AC_UD_CS_GRID_SIZE);
3684
3685 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3686
3687 if (info->indirect) {
3688 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3689
3690 va += info->indirect->offset + info->indirect_offset;
3691
3692 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3693
3694 if (loc->sgpr_idx != -1) {
3695 for (unsigned i = 0; i < 3; ++i) {
3696 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3697 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3698 COPY_DATA_DST_SEL(COPY_DATA_REG));
3699 radeon_emit(cs, (va + 4 * i));
3700 radeon_emit(cs, (va + 4 * i) >> 32);
3701 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3702 + loc->sgpr_idx * 4) >> 2) + i);
3703 radeon_emit(cs, 0);
3704 }
3705 }
3706
3707 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3708 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3709 PKT3_SHADER_TYPE_S(1));
3710 radeon_emit(cs, va);
3711 radeon_emit(cs, va >> 32);
3712 radeon_emit(cs, dispatch_initiator);
3713 } else {
3714 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3715 PKT3_SHADER_TYPE_S(1));
3716 radeon_emit(cs, 1);
3717 radeon_emit(cs, va);
3718 radeon_emit(cs, va >> 32);
3719
3720 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3721 PKT3_SHADER_TYPE_S(1));
3722 radeon_emit(cs, 0);
3723 radeon_emit(cs, dispatch_initiator);
3724 }
3725 } else {
3726 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3727 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3728
3729 if (info->unaligned) {
3730 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3731 unsigned remainder[3];
3732
3733 /* If aligned, these should be an entire block size,
3734 * not 0.
3735 */
3736 remainder[0] = blocks[0] + cs_block_size[0] -
3737 align_u32_npot(blocks[0], cs_block_size[0]);
3738 remainder[1] = blocks[1] + cs_block_size[1] -
3739 align_u32_npot(blocks[1], cs_block_size[1]);
3740 remainder[2] = blocks[2] + cs_block_size[2] -
3741 align_u32_npot(blocks[2], cs_block_size[2]);
3742
3743 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3744 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3745 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3746
3747 for(unsigned i = 0; i < 3; ++i) {
3748 assert(offsets[i] % cs_block_size[i] == 0);
3749 offsets[i] /= cs_block_size[i];
3750 }
3751
3752 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3753 radeon_emit(cs,
3754 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3755 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3756 radeon_emit(cs,
3757 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3758 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3759 radeon_emit(cs,
3760 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3761 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3762
3763 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3764 }
3765
3766 if (loc->sgpr_idx != -1) {
3767 assert(!loc->indirect);
3768 assert(loc->num_sgprs == 3);
3769
3770 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3771 loc->sgpr_idx * 4, 3);
3772 radeon_emit(cs, blocks[0]);
3773 radeon_emit(cs, blocks[1]);
3774 radeon_emit(cs, blocks[2]);
3775 }
3776
3777 if (offsets[0] || offsets[1] || offsets[2]) {
3778 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3779 radeon_emit(cs, offsets[0]);
3780 radeon_emit(cs, offsets[1]);
3781 radeon_emit(cs, offsets[2]);
3782
3783 /* The blocks in the packet are not counts but end values. */
3784 for (unsigned i = 0; i < 3; ++i)
3785 blocks[i] += offsets[i];
3786 } else {
3787 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3788 }
3789
3790 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3791 PKT3_SHADER_TYPE_S(1));
3792 radeon_emit(cs, blocks[0]);
3793 radeon_emit(cs, blocks[1]);
3794 radeon_emit(cs, blocks[2]);
3795 radeon_emit(cs, dispatch_initiator);
3796 }
3797
3798 assert(cmd_buffer->cs->cdw <= cdw_max);
3799 }
3800
3801 static void
3802 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3803 {
3804 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3805 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3806 }
3807
3808 static void
3809 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3810 const struct radv_dispatch_info *info)
3811 {
3812 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3813 bool has_prefetch =
3814 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3815 bool pipeline_is_dirty = pipeline &&
3816 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3817
3818 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3819 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3820 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3821 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3822 /* If we have to wait for idle, set all states first, so that
3823 * all SET packets are processed in parallel with previous draw
3824 * calls. Then upload descriptors, set shader pointers, and
3825 * dispatch, and prefetch at the end. This ensures that the
3826 * time the CUs are idle is very short. (there are only SET_SH
3827 * packets between the wait and the draw)
3828 */
3829 radv_emit_compute_pipeline(cmd_buffer);
3830 si_emit_cache_flush(cmd_buffer);
3831 /* <-- CUs are idle here --> */
3832
3833 radv_upload_compute_shader_descriptors(cmd_buffer);
3834
3835 radv_emit_dispatch_packets(cmd_buffer, info);
3836 /* <-- CUs are busy here --> */
3837
3838 /* Start prefetches after the dispatch has been started. Both
3839 * will run in parallel, but starting the dispatch first is
3840 * more important.
3841 */
3842 if (has_prefetch && pipeline_is_dirty) {
3843 radv_emit_shader_prefetch(cmd_buffer,
3844 pipeline->shaders[MESA_SHADER_COMPUTE]);
3845 }
3846 } else {
3847 /* If we don't wait for idle, start prefetches first, then set
3848 * states, and dispatch at the end.
3849 */
3850 si_emit_cache_flush(cmd_buffer);
3851
3852 if (has_prefetch && pipeline_is_dirty) {
3853 radv_emit_shader_prefetch(cmd_buffer,
3854 pipeline->shaders[MESA_SHADER_COMPUTE]);
3855 }
3856
3857 radv_upload_compute_shader_descriptors(cmd_buffer);
3858
3859 radv_emit_compute_pipeline(cmd_buffer);
3860 radv_emit_dispatch_packets(cmd_buffer, info);
3861 }
3862
3863 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3864 }
3865
3866 void radv_CmdDispatchBase(
3867 VkCommandBuffer commandBuffer,
3868 uint32_t base_x,
3869 uint32_t base_y,
3870 uint32_t base_z,
3871 uint32_t x,
3872 uint32_t y,
3873 uint32_t z)
3874 {
3875 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3876 struct radv_dispatch_info info = {};
3877
3878 info.blocks[0] = x;
3879 info.blocks[1] = y;
3880 info.blocks[2] = z;
3881
3882 info.offsets[0] = base_x;
3883 info.offsets[1] = base_y;
3884 info.offsets[2] = base_z;
3885 radv_dispatch(cmd_buffer, &info);
3886 }
3887
3888 void radv_CmdDispatch(
3889 VkCommandBuffer commandBuffer,
3890 uint32_t x,
3891 uint32_t y,
3892 uint32_t z)
3893 {
3894 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3895 }
3896
3897 void radv_CmdDispatchIndirect(
3898 VkCommandBuffer commandBuffer,
3899 VkBuffer _buffer,
3900 VkDeviceSize offset)
3901 {
3902 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3903 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3904 struct radv_dispatch_info info = {};
3905
3906 info.indirect = buffer;
3907 info.indirect_offset = offset;
3908
3909 radv_dispatch(cmd_buffer, &info);
3910 }
3911
3912 void radv_unaligned_dispatch(
3913 struct radv_cmd_buffer *cmd_buffer,
3914 uint32_t x,
3915 uint32_t y,
3916 uint32_t z)
3917 {
3918 struct radv_dispatch_info info = {};
3919
3920 info.blocks[0] = x;
3921 info.blocks[1] = y;
3922 info.blocks[2] = z;
3923 info.unaligned = 1;
3924
3925 radv_dispatch(cmd_buffer, &info);
3926 }
3927
3928 void radv_CmdEndRenderPass(
3929 VkCommandBuffer commandBuffer)
3930 {
3931 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3932
3933 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3934
3935 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3936
3937 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3938 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3939 radv_handle_subpass_image_transition(cmd_buffer,
3940 (VkAttachmentReference){i, layout});
3941 }
3942
3943 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3944
3945 cmd_buffer->state.pass = NULL;
3946 cmd_buffer->state.subpass = NULL;
3947 cmd_buffer->state.attachments = NULL;
3948 cmd_buffer->state.framebuffer = NULL;
3949 }
3950
3951 /*
3952 * For HTILE we have the following interesting clear words:
3953 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3954 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3955 * 0xfffffff0: Clear depth to 1.0
3956 * 0x00000000: Clear depth to 0.0
3957 */
3958 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3959 struct radv_image *image,
3960 const VkImageSubresourceRange *range,
3961 uint32_t clear_word)
3962 {
3963 assert(range->baseMipLevel == 0);
3964 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3965 unsigned layer_count = radv_get_layerCount(image, range);
3966 uint64_t size = image->surface.htile_slice_size * layer_count;
3967 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
3968 uint64_t offset = image->offset + image->htile_offset +
3969 image->surface.htile_slice_size * range->baseArrayLayer;
3970 struct radv_cmd_state *state = &cmd_buffer->state;
3971 VkClearDepthStencilValue value = {};
3972
3973 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3974 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3975
3976 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3977 size, clear_word);
3978
3979 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3980
3981 if (vk_format_is_stencil(image->vk_format))
3982 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3983
3984 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
3985 }
3986
3987 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3988 struct radv_image *image,
3989 VkImageLayout src_layout,
3990 VkImageLayout dst_layout,
3991 unsigned src_queue_mask,
3992 unsigned dst_queue_mask,
3993 const VkImageSubresourceRange *range,
3994 VkImageAspectFlags pending_clears)
3995 {
3996 if (!radv_image_has_htile(image))
3997 return;
3998
3999 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4000 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4001 /* TODO: merge with the clear if applicable */
4002 radv_initialize_htile(cmd_buffer, image, range, 0);
4003 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4004 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4005 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4006 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4007 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4008 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4009 VkImageSubresourceRange local_range = *range;
4010 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4011 local_range.baseMipLevel = 0;
4012 local_range.levelCount = 1;
4013
4014 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4015 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4016
4017 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4018
4019 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4020 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4021 }
4022 }
4023
4024 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4025 struct radv_image *image, uint32_t value)
4026 {
4027 struct radv_cmd_state *state = &cmd_buffer->state;
4028
4029 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4030 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4031
4032 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4033
4034 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4035 }
4036
4037 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4038 struct radv_image *image, uint32_t value)
4039 {
4040 struct radv_cmd_state *state = &cmd_buffer->state;
4041
4042 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4043 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4044
4045 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4046
4047 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4048 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4049 }
4050
4051 /**
4052 * Initialize DCC/FMASK/CMASK metadata for a color image.
4053 */
4054 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4055 struct radv_image *image,
4056 VkImageLayout src_layout,
4057 VkImageLayout dst_layout,
4058 unsigned src_queue_mask,
4059 unsigned dst_queue_mask)
4060 {
4061 if (radv_image_has_cmask(image)) {
4062 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4063
4064 /* TODO: clarify this. */
4065 if (radv_image_has_fmask(image)) {
4066 value = 0xccccccccu;
4067 }
4068
4069 radv_initialise_cmask(cmd_buffer, image, value);
4070 }
4071
4072 if (radv_image_has_dcc(image)) {
4073 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4074
4075 if (radv_layout_dcc_compressed(image, dst_layout,
4076 dst_queue_mask)) {
4077 value = 0x20202020u;
4078 }
4079
4080 radv_initialize_dcc(cmd_buffer, image, value);
4081
4082 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image, false);
4083 }
4084
4085 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4086 uint32_t color_values[2] = {};
4087 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4088 }
4089 }
4090
4091 /**
4092 * Handle color image transitions for DCC/FMASK/CMASK.
4093 */
4094 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4095 struct radv_image *image,
4096 VkImageLayout src_layout,
4097 VkImageLayout dst_layout,
4098 unsigned src_queue_mask,
4099 unsigned dst_queue_mask,
4100 const VkImageSubresourceRange *range)
4101 {
4102 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4103 radv_init_color_image_metadata(cmd_buffer, image,
4104 src_layout, dst_layout,
4105 src_queue_mask, dst_queue_mask);
4106 return;
4107 }
4108
4109 if (radv_image_has_dcc(image)) {
4110 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4111 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4112 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4113 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4114 radv_decompress_dcc(cmd_buffer, image, range);
4115 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4116 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4117 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4118 }
4119 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4120 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4121 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4122 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4123 }
4124 }
4125 }
4126
4127 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4128 struct radv_image *image,
4129 VkImageLayout src_layout,
4130 VkImageLayout dst_layout,
4131 uint32_t src_family,
4132 uint32_t dst_family,
4133 const VkImageSubresourceRange *range,
4134 VkImageAspectFlags pending_clears)
4135 {
4136 if (image->exclusive && src_family != dst_family) {
4137 /* This is an acquire or a release operation and there will be
4138 * a corresponding release/acquire. Do the transition in the
4139 * most flexible queue. */
4140
4141 assert(src_family == cmd_buffer->queue_family_index ||
4142 dst_family == cmd_buffer->queue_family_index);
4143
4144 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4145 return;
4146
4147 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4148 (src_family == RADV_QUEUE_GENERAL ||
4149 dst_family == RADV_QUEUE_GENERAL))
4150 return;
4151 }
4152
4153 unsigned src_queue_mask =
4154 radv_image_queue_family_mask(image, src_family,
4155 cmd_buffer->queue_family_index);
4156 unsigned dst_queue_mask =
4157 radv_image_queue_family_mask(image, dst_family,
4158 cmd_buffer->queue_family_index);
4159
4160 if (vk_format_is_depth(image->vk_format)) {
4161 radv_handle_depth_image_transition(cmd_buffer, image,
4162 src_layout, dst_layout,
4163 src_queue_mask, dst_queue_mask,
4164 range, pending_clears);
4165 } else {
4166 radv_handle_color_image_transition(cmd_buffer, image,
4167 src_layout, dst_layout,
4168 src_queue_mask, dst_queue_mask,
4169 range);
4170 }
4171 }
4172
4173 void radv_CmdPipelineBarrier(
4174 VkCommandBuffer commandBuffer,
4175 VkPipelineStageFlags srcStageMask,
4176 VkPipelineStageFlags destStageMask,
4177 VkBool32 byRegion,
4178 uint32_t memoryBarrierCount,
4179 const VkMemoryBarrier* pMemoryBarriers,
4180 uint32_t bufferMemoryBarrierCount,
4181 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4182 uint32_t imageMemoryBarrierCount,
4183 const VkImageMemoryBarrier* pImageMemoryBarriers)
4184 {
4185 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4186 enum radv_cmd_flush_bits src_flush_bits = 0;
4187 enum radv_cmd_flush_bits dst_flush_bits = 0;
4188
4189 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4190 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
4191 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4192 NULL);
4193 }
4194
4195 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4196 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
4197 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4198 NULL);
4199 }
4200
4201 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4202 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4203 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
4204 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4205 image);
4206 }
4207
4208 radv_stage_flush(cmd_buffer, srcStageMask);
4209 cmd_buffer->state.flush_bits |= src_flush_bits;
4210
4211 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4212 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4213 radv_handle_image_transition(cmd_buffer, image,
4214 pImageMemoryBarriers[i].oldLayout,
4215 pImageMemoryBarriers[i].newLayout,
4216 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4217 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4218 &pImageMemoryBarriers[i].subresourceRange,
4219 0);
4220 }
4221
4222 cmd_buffer->state.flush_bits |= dst_flush_bits;
4223 }
4224
4225
4226 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4227 struct radv_event *event,
4228 VkPipelineStageFlags stageMask,
4229 unsigned value)
4230 {
4231 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4232 uint64_t va = radv_buffer_get_va(event->bo);
4233
4234 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4235
4236 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4237
4238 /* TODO: this is overkill. Probably should figure something out from
4239 * the stage mask. */
4240
4241 si_cs_emit_write_event_eop(cs,
4242 cmd_buffer->device->physical_device->rad_info.chip_class,
4243 radv_cmd_buffer_uses_mec(cmd_buffer),
4244 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4245 EOP_DATA_SEL_VALUE_32BIT, va, 2, value);
4246
4247 assert(cmd_buffer->cs->cdw <= cdw_max);
4248 }
4249
4250 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4251 VkEvent _event,
4252 VkPipelineStageFlags stageMask)
4253 {
4254 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4255 RADV_FROM_HANDLE(radv_event, event, _event);
4256
4257 write_event(cmd_buffer, event, stageMask, 1);
4258 }
4259
4260 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4261 VkEvent _event,
4262 VkPipelineStageFlags stageMask)
4263 {
4264 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4265 RADV_FROM_HANDLE(radv_event, event, _event);
4266
4267 write_event(cmd_buffer, event, stageMask, 0);
4268 }
4269
4270 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4271 uint32_t eventCount,
4272 const VkEvent* pEvents,
4273 VkPipelineStageFlags srcStageMask,
4274 VkPipelineStageFlags dstStageMask,
4275 uint32_t memoryBarrierCount,
4276 const VkMemoryBarrier* pMemoryBarriers,
4277 uint32_t bufferMemoryBarrierCount,
4278 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4279 uint32_t imageMemoryBarrierCount,
4280 const VkImageMemoryBarrier* pImageMemoryBarriers)
4281 {
4282 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4283 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4284
4285 for (unsigned i = 0; i < eventCount; ++i) {
4286 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4287 uint64_t va = radv_buffer_get_va(event->bo);
4288
4289 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4290
4291 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4292
4293 si_emit_wait_fence(cs, va, 1, 0xffffffff);
4294 assert(cmd_buffer->cs->cdw <= cdw_max);
4295 }
4296
4297
4298 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4299 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4300
4301 radv_handle_image_transition(cmd_buffer, image,
4302 pImageMemoryBarriers[i].oldLayout,
4303 pImageMemoryBarriers[i].newLayout,
4304 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4305 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4306 &pImageMemoryBarriers[i].subresourceRange,
4307 0);
4308 }
4309
4310 /* TODO: figure out how to do memory barriers without waiting */
4311 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4312 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4313 RADV_CMD_FLAG_INV_VMEM_L1 |
4314 RADV_CMD_FLAG_INV_SMEM_L1;
4315 }
4316
4317
4318 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4319 uint32_t deviceMask)
4320 {
4321 /* No-op */
4322 }