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radv: add tess shader stage user data support.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 uint32_t src_family,
42 uint32_t dst_family,
43 const VkImageSubresourceRange *range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static void
191 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
192 {
193 list_del(&cmd_buffer->pool_link);
194
195 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
196 &cmd_buffer->upload.list, list) {
197 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
198 list_del(&up->list);
199 free(up);
200 }
201
202 if (cmd_buffer->upload.upload_bo)
203 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
204 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
205 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
206 }
207
208 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
209 {
210
211 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
212
213 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
214 &cmd_buffer->upload.list, list) {
215 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
216 list_del(&up->list);
217 free(up);
218 }
219
220 cmd_buffer->scratch_size_needed = 0;
221 cmd_buffer->compute_scratch_size_needed = 0;
222 cmd_buffer->esgs_ring_size_needed = 0;
223 cmd_buffer->gsvs_ring_size_needed = 0;
224
225 if (cmd_buffer->upload.upload_bo)
226 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
227 cmd_buffer->upload.upload_bo, 8);
228 cmd_buffer->upload.offset = 0;
229
230 cmd_buffer->record_fail = false;
231
232 cmd_buffer->ring_offsets_idx = -1;
233 }
234
235 static bool
236 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
237 uint64_t min_needed)
238 {
239 uint64_t new_size;
240 struct radeon_winsys_bo *bo;
241 struct radv_cmd_buffer_upload *upload;
242 struct radv_device *device = cmd_buffer->device;
243
244 new_size = MAX2(min_needed, 16 * 1024);
245 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
246
247 bo = device->ws->buffer_create(device->ws,
248 new_size, 4096,
249 RADEON_DOMAIN_GTT,
250 RADEON_FLAG_CPU_ACCESS);
251
252 if (!bo) {
253 cmd_buffer->record_fail = true;
254 return false;
255 }
256
257 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
258 if (cmd_buffer->upload.upload_bo) {
259 upload = malloc(sizeof(*upload));
260
261 if (!upload) {
262 cmd_buffer->record_fail = true;
263 device->ws->buffer_destroy(bo);
264 return false;
265 }
266
267 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
268 list_add(&upload->list, &cmd_buffer->upload.list);
269 }
270
271 cmd_buffer->upload.upload_bo = bo;
272 cmd_buffer->upload.size = new_size;
273 cmd_buffer->upload.offset = 0;
274 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
275
276 if (!cmd_buffer->upload.map) {
277 cmd_buffer->record_fail = true;
278 return false;
279 }
280
281 return true;
282 }
283
284 bool
285 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
286 unsigned size,
287 unsigned alignment,
288 unsigned *out_offset,
289 void **ptr)
290 {
291 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
292 if (offset + size > cmd_buffer->upload.size) {
293 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
294 return false;
295 offset = 0;
296 }
297
298 *out_offset = offset;
299 *ptr = cmd_buffer->upload.map + offset;
300
301 cmd_buffer->upload.offset = offset + size;
302 return true;
303 }
304
305 bool
306 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
307 unsigned size, unsigned alignment,
308 const void *data, unsigned *out_offset)
309 {
310 uint8_t *ptr;
311
312 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
313 out_offset, (void **)&ptr))
314 return false;
315
316 if (ptr)
317 memcpy(ptr, data, size);
318
319 return true;
320 }
321
322 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
323 {
324 struct radv_device *device = cmd_buffer->device;
325 struct radeon_winsys_cs *cs = cmd_buffer->cs;
326 uint64_t va;
327
328 if (!device->trace_bo)
329 return;
330
331 va = device->ws->buffer_get_va(device->trace_bo);
332
333 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
334
335 ++cmd_buffer->state.trace_id;
336 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
337 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
338 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
339 S_370_WR_CONFIRM(1) |
340 S_370_ENGINE_SEL(V_370_ME));
341 radeon_emit(cs, va);
342 radeon_emit(cs, va >> 32);
343 radeon_emit(cs, cmd_buffer->state.trace_id);
344 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
345 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
346 }
347
348 static void
349 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
350 struct radv_pipeline *pipeline)
351 {
352 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
353 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
354 8);
355 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
356 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
357 }
358
359 static void
360 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
361 struct radv_pipeline *pipeline)
362 {
363 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
364 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
365 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
366
367 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
369 }
370
371 /* 12.4 fixed-point */
372 static unsigned radv_pack_float_12p4(float x)
373 {
374 return x <= 0 ? 0 :
375 x >= 4096 ? 0xffff : x * 16;
376 }
377
378 static uint32_t
379 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
380 {
381 switch (stage) {
382 case MESA_SHADER_FRAGMENT:
383 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
384 case MESA_SHADER_VERTEX:
385 if (has_tess)
386 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
387 else
388 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
389 case MESA_SHADER_GEOMETRY:
390 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
391 case MESA_SHADER_COMPUTE:
392 return R_00B900_COMPUTE_USER_DATA_0;
393 case MESA_SHADER_TESS_CTRL:
394 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
395 case MESA_SHADER_TESS_EVAL:
396 if (has_gs)
397 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
398 else
399 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
400 default:
401 unreachable("unknown shader");
402 }
403 }
404
405 static struct ac_userdata_info *
406 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
407 gl_shader_stage stage,
408 int idx)
409 {
410 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
411 }
412
413 static void
414 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
415 struct radv_pipeline *pipeline,
416 gl_shader_stage stage,
417 int idx, uint64_t va)
418 {
419 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
420 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
421 if (loc->sgpr_idx == -1)
422 return;
423 assert(loc->num_sgprs == 2);
424 assert(!loc->indirect);
425 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
426 radeon_emit(cmd_buffer->cs, va);
427 radeon_emit(cmd_buffer->cs, va >> 32);
428 }
429
430 static void
431 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
432 struct radv_pipeline *pipeline)
433 {
434 int num_samples = pipeline->graphics.ms.num_samples;
435 struct radv_multisample_state *ms = &pipeline->graphics.ms;
436 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
437
438 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
439 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
440 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
441
442 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
443 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
444
445 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
446 return;
447
448 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
449 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
450 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
451
452 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
453
454 uint32_t samples_offset;
455 void *samples_ptr;
456 void *src;
457 radv_cmd_buffer_upload_alloc(cmd_buffer, num_samples * 4 * 2, 256, &samples_offset,
458 &samples_ptr);
459 switch (num_samples) {
460 case 1:
461 src = cmd_buffer->device->sample_locations_1x;
462 break;
463 case 2:
464 src = cmd_buffer->device->sample_locations_2x;
465 break;
466 case 4:
467 src = cmd_buffer->device->sample_locations_4x;
468 break;
469 case 8:
470 src = cmd_buffer->device->sample_locations_8x;
471 break;
472 case 16:
473 src = cmd_buffer->device->sample_locations_16x;
474 break;
475 default:
476 unreachable("unknown number of samples");
477 }
478 memcpy(samples_ptr, src, num_samples * 4 * 2);
479
480 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
481 va += samples_offset;
482
483 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
484 AC_UD_PS_SAMPLE_POS, va);
485 }
486
487 static void
488 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
489 struct radv_pipeline *pipeline)
490 {
491 struct radv_raster_state *raster = &pipeline->graphics.raster;
492
493 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
494 raster->pa_cl_clip_cntl);
495
496 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
497 raster->spi_interp_control);
498
499 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
500 unsigned tmp = (unsigned)(1.0 * 8.0);
501 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
502 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
503 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
504
505 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
506 raster->pa_su_vtx_cntl);
507
508 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
509 raster->pa_su_sc_mode_cntl);
510 }
511
512 static void
513 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
514 struct radv_pipeline *pipeline,
515 struct radv_shader_variant *shader,
516 struct ac_vs_output_info *outinfo)
517 {
518 struct radeon_winsys *ws = cmd_buffer->device->ws;
519 uint64_t va = ws->buffer_get_va(shader->bo);
520 unsigned export_count;
521
522 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
523
524 export_count = MAX2(1, outinfo->param_exports);
525 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
526 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
527
528 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
529 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
530 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
531 V_02870C_SPI_SHADER_4COMP :
532 V_02870C_SPI_SHADER_NONE) |
533 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
534 V_02870C_SPI_SHADER_4COMP :
535 V_02870C_SPI_SHADER_NONE) |
536 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
537 V_02870C_SPI_SHADER_4COMP :
538 V_02870C_SPI_SHADER_NONE));
539
540
541 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
542 radeon_emit(cmd_buffer->cs, va >> 8);
543 radeon_emit(cmd_buffer->cs, va >> 40);
544 radeon_emit(cmd_buffer->cs, shader->rsrc1);
545 radeon_emit(cmd_buffer->cs, shader->rsrc2);
546
547 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
548 S_028818_VTX_W0_FMT(1) |
549 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
550 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
551 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
552
553
554 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
555 pipeline->graphics.pa_cl_vs_out_cntl);
556
557 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
558 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
559 }
560
561 static void
562 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
563 struct radv_shader_variant *shader,
564 struct ac_es_output_info *outinfo)
565 {
566 struct radeon_winsys *ws = cmd_buffer->device->ws;
567 uint64_t va = ws->buffer_get_va(shader->bo);
568
569 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
570
571 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
572 outinfo->esgs_itemsize / 4);
573 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
574 radeon_emit(cmd_buffer->cs, va >> 8);
575 radeon_emit(cmd_buffer->cs, va >> 40);
576 radeon_emit(cmd_buffer->cs, shader->rsrc1);
577 radeon_emit(cmd_buffer->cs, shader->rsrc2);
578 }
579
580 static void
581 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
582 struct radv_pipeline *pipeline)
583 {
584 struct radv_shader_variant *vs;
585
586 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
587
588 vs = pipeline->shaders[MESA_SHADER_VERTEX];
589
590 if (vs->info.vs.as_es)
591 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
592 else
593 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
594
595 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
596 }
597
598
599 static void
600 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
601 struct radv_pipeline *pipeline)
602 {
603 struct radeon_winsys *ws = cmd_buffer->device->ws;
604 struct radv_shader_variant *gs;
605 uint64_t va;
606
607 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
608
609 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
610 if (!gs)
611 return;
612
613 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
614
615 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
616 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
617 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
618 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
619
620 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
621
622 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
623
624 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
625 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
626 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
627 radeon_emit(cmd_buffer->cs, 0);
628 radeon_emit(cmd_buffer->cs, 0);
629 radeon_emit(cmd_buffer->cs, 0);
630
631 uint32_t gs_num_invocations = gs->info.gs.invocations;
632 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
633 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
634 S_028B90_ENABLE(gs_num_invocations > 0));
635
636 va = ws->buffer_get_va(gs->bo);
637 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
638 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
639 radeon_emit(cmd_buffer->cs, va >> 8);
640 radeon_emit(cmd_buffer->cs, va >> 40);
641 radeon_emit(cmd_buffer->cs, gs->rsrc1);
642 radeon_emit(cmd_buffer->cs, gs->rsrc2);
643
644 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
645
646 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
647 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
648 if (loc->sgpr_idx != -1) {
649 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
650 uint32_t num_entries = 64;
651 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
652
653 if (is_vi)
654 num_entries *= stride;
655
656 stride = S_008F04_STRIDE(stride);
657 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
658 radeon_emit(cmd_buffer->cs, stride);
659 radeon_emit(cmd_buffer->cs, num_entries);
660 }
661 }
662
663 static void
664 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
665 struct radv_pipeline *pipeline)
666 {
667 struct radeon_winsys *ws = cmd_buffer->device->ws;
668 struct radv_shader_variant *ps;
669 uint64_t va;
670 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
671 struct radv_blend_state *blend = &pipeline->graphics.blend;
672 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
673
674 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
675
676 va = ws->buffer_get_va(ps->bo);
677 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
678
679 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
680 radeon_emit(cmd_buffer->cs, va >> 8);
681 radeon_emit(cmd_buffer->cs, va >> 40);
682 radeon_emit(cmd_buffer->cs, ps->rsrc1);
683 radeon_emit(cmd_buffer->cs, ps->rsrc2);
684
685 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
686 pipeline->graphics.db_shader_control);
687
688 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
689 ps->config.spi_ps_input_ena);
690
691 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
692 ps->config.spi_ps_input_addr);
693
694 if (ps->info.fs.force_persample)
695 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
696
697 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
698 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
699
700 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
701
702 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
703 pipeline->graphics.shader_z_format);
704
705 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
706
707 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
708 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
709
710 if (pipeline->graphics.ps_input_cntl_num) {
711 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
712 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
713 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
714 }
715 }
716 }
717
718 static void
719 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
720 struct radv_pipeline *pipeline)
721 {
722 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
723 return;
724
725 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
726 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
727 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
728 radv_update_multisample_state(cmd_buffer, pipeline);
729 radv_emit_vertex_shader(cmd_buffer, pipeline);
730 radv_emit_geometry_shader(cmd_buffer, pipeline);
731 radv_emit_fragment_shader(cmd_buffer, pipeline);
732
733 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
734 pipeline->graphics.prim_restart_enable);
735
736 cmd_buffer->scratch_size_needed =
737 MAX2(cmd_buffer->scratch_size_needed,
738 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
739
740 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
741 S_0286E8_WAVES(pipeline->max_waves) |
742 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
743
744 if (!cmd_buffer->state.emitted_pipeline ||
745 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
746 pipeline->graphics.can_use_guardband)
747 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
748 cmd_buffer->state.emitted_pipeline = pipeline;
749 }
750
751 static void
752 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
753 {
754 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
755 cmd_buffer->state.dynamic.viewport.viewports);
756 }
757
758 static void
759 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
760 {
761 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
762 si_write_scissors(cmd_buffer->cs, 0, count,
763 cmd_buffer->state.dynamic.scissor.scissors,
764 cmd_buffer->state.dynamic.viewport.viewports,
765 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
766 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
767 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
768 }
769
770 static void
771 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
772 int index,
773 struct radv_color_buffer_info *cb)
774 {
775 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
776 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
777 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
778 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
779 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
780 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
781 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
782 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
783 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
784 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
785 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
786 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
787 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
788
789 if (is_vi) { /* DCC BASE */
790 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
791 }
792 }
793
794 static void
795 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
796 struct radv_ds_buffer_info *ds,
797 struct radv_image *image,
798 VkImageLayout layout)
799 {
800 uint32_t db_z_info = ds->db_z_info;
801
802 if (!radv_layout_has_htile(image, layout))
803 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
804
805 if (!radv_layout_can_expclear(image, layout))
806 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
807
808 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
809 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
810
811 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
812 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
813 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
814 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
815 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
816 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
817 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
818 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
819 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
820 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
821
822 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
823 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
824 ds->pa_su_poly_offset_db_fmt_cntl);
825 }
826
827 /*
828 * To hw resolve multisample images both src and dst need to have the same
829 * micro tiling mode. However we don't always know in advance when creating
830 * the images. This function gets called if we have a resolve attachment,
831 * and tests if the attachment image has the same tiling mode, then it
832 * checks if the generated framebuffer data has the same tiling mode, and
833 * updates it if not.
834 */
835 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
836 struct radv_attachment_info *att,
837 uint32_t micro_tile_mode)
838 {
839 struct radv_image *image = att->attachment->image;
840 uint32_t tile_mode_index;
841 if (image->surface.nsamples <= 1)
842 return;
843
844 if (image->surface.micro_tile_mode != micro_tile_mode) {
845 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
846 }
847
848 if (att->cb.micro_tile_mode != micro_tile_mode) {
849 tile_mode_index = image->surface.tiling_index[0];
850
851 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
852 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
853 att->cb.micro_tile_mode = micro_tile_mode;
854 }
855 }
856
857 void
858 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
859 struct radv_image *image,
860 VkClearDepthStencilValue ds_clear_value,
861 VkImageAspectFlags aspects)
862 {
863 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
864 va += image->offset + image->clear_value_offset;
865 unsigned reg_offset = 0, reg_count = 0;
866
867 if (!image->surface.htile_size || !aspects)
868 return;
869
870 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
871 ++reg_count;
872 } else {
873 ++reg_offset;
874 va += 4;
875 }
876 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
877 ++reg_count;
878
879 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
880
881 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
882 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
883 S_370_WR_CONFIRM(1) |
884 S_370_ENGINE_SEL(V_370_PFP));
885 radeon_emit(cmd_buffer->cs, va);
886 radeon_emit(cmd_buffer->cs, va >> 32);
887 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
888 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
889 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
890 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
891
892 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
893 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
894 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
895 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
896 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
897 }
898
899 static void
900 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
901 struct radv_image *image)
902 {
903 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
904 va += image->offset + image->clear_value_offset;
905
906 if (!image->surface.htile_size)
907 return;
908
909 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
910
911 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
912 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
913 COPY_DATA_DST_SEL(COPY_DATA_REG) |
914 COPY_DATA_COUNT_SEL);
915 radeon_emit(cmd_buffer->cs, va);
916 radeon_emit(cmd_buffer->cs, va >> 32);
917 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
918 radeon_emit(cmd_buffer->cs, 0);
919
920 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
921 radeon_emit(cmd_buffer->cs, 0);
922 }
923
924 void
925 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
926 struct radv_image *image,
927 int idx,
928 uint32_t color_values[2])
929 {
930 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
931 va += image->offset + image->clear_value_offset;
932
933 if (!image->cmask.size && !image->surface.dcc_size)
934 return;
935
936 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
937
938 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
939 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
940 S_370_WR_CONFIRM(1) |
941 S_370_ENGINE_SEL(V_370_PFP));
942 radeon_emit(cmd_buffer->cs, va);
943 radeon_emit(cmd_buffer->cs, va >> 32);
944 radeon_emit(cmd_buffer->cs, color_values[0]);
945 radeon_emit(cmd_buffer->cs, color_values[1]);
946
947 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
948 radeon_emit(cmd_buffer->cs, color_values[0]);
949 radeon_emit(cmd_buffer->cs, color_values[1]);
950 }
951
952 static void
953 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
954 struct radv_image *image,
955 int idx)
956 {
957 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
958 va += image->offset + image->clear_value_offset;
959
960 if (!image->cmask.size && !image->surface.dcc_size)
961 return;
962
963 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
964 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
965
966 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
967 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
968 COPY_DATA_DST_SEL(COPY_DATA_REG) |
969 COPY_DATA_COUNT_SEL);
970 radeon_emit(cmd_buffer->cs, va);
971 radeon_emit(cmd_buffer->cs, va >> 32);
972 radeon_emit(cmd_buffer->cs, reg >> 2);
973 radeon_emit(cmd_buffer->cs, 0);
974
975 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
976 radeon_emit(cmd_buffer->cs, 0);
977 }
978
979 void
980 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
981 {
982 int i;
983 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
984 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
985 int dst_resolve_micro_tile_mode = -1;
986
987 if (subpass->has_resolve) {
988 uint32_t a = subpass->resolve_attachments[0].attachment;
989 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
990 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
991 }
992 for (i = 0; i < subpass->color_count; ++i) {
993 int idx = subpass->color_attachments[i].attachment;
994 struct radv_attachment_info *att = &framebuffer->attachments[idx];
995
996 if (dst_resolve_micro_tile_mode != -1) {
997 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
998 att, dst_resolve_micro_tile_mode);
999 }
1000 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1001
1002 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1003 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1004
1005 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1006 }
1007
1008 for (i = subpass->color_count; i < 8; i++)
1009 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1010 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1011
1012 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1013 int idx = subpass->depth_stencil_attachment.attachment;
1014 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1015 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1016 struct radv_image *image = att->attachment->image;
1017 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1018
1019 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1020
1021 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1022 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1023 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1024 }
1025 radv_load_depth_clear_regs(cmd_buffer, image);
1026 } else {
1027 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1028 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1029 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1030 }
1031 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1032 S_028208_BR_X(framebuffer->width) |
1033 S_028208_BR_Y(framebuffer->height));
1034 }
1035
1036 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1037 {
1038 uint32_t db_count_control;
1039
1040 if(!cmd_buffer->state.active_occlusion_queries) {
1041 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1042 db_count_control = 0;
1043 } else {
1044 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1045 }
1046 } else {
1047 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1048 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1049 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1050 S_028004_ZPASS_ENABLE(1) |
1051 S_028004_SLICE_EVEN_ENABLE(1) |
1052 S_028004_SLICE_ODD_ENABLE(1);
1053 } else {
1054 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1055 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1056 }
1057 }
1058
1059 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1060 }
1061
1062 static void
1063 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1064 {
1065 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1066
1067 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1068 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1069 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1070 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1071 }
1072
1073 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1074 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1075 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1076 }
1077
1078 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1079 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1080 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1081 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1082 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1083 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1084 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1085 S_028430_STENCILOPVAL(1));
1086 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1087 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1088 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1089 S_028434_STENCILOPVAL_BF(1));
1090 }
1091
1092 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1093 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1094 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1095 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1096 }
1097
1098 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1099 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1100 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1101 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1102 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1103
1104 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1105 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1106 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1107 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1108 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1109 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1110 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1111 }
1112 }
1113
1114 cmd_buffer->state.dirty = 0;
1115 }
1116
1117 static void
1118 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1119 struct radv_pipeline *pipeline,
1120 int idx,
1121 uint64_t va,
1122 gl_shader_stage stage)
1123 {
1124 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1125 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1126
1127 if (desc_set_loc->sgpr_idx == -1)
1128 return;
1129
1130 assert(!desc_set_loc->indirect);
1131 assert(desc_set_loc->num_sgprs == 2);
1132 radeon_set_sh_reg_seq(cmd_buffer->cs,
1133 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1134 radeon_emit(cmd_buffer->cs, va);
1135 radeon_emit(cmd_buffer->cs, va >> 32);
1136 }
1137
1138 static void
1139 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1140 struct radv_pipeline *pipeline,
1141 VkShaderStageFlags stages,
1142 struct radv_descriptor_set *set,
1143 unsigned idx)
1144 {
1145 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1146 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1147 idx, set->va,
1148 MESA_SHADER_FRAGMENT);
1149
1150 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1151 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1152 idx, set->va,
1153 MESA_SHADER_VERTEX);
1154
1155 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1156 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1157 idx, set->va,
1158 MESA_SHADER_GEOMETRY);
1159
1160 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1161 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1162 idx, set->va,
1163 MESA_SHADER_TESS_CTRL);
1164
1165 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1166 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1167 idx, set->va,
1168 MESA_SHADER_TESS_EVAL);
1169
1170 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1171 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1172 idx, set->va,
1173 MESA_SHADER_COMPUTE);
1174 }
1175
1176 static void
1177 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1178 struct radv_pipeline *pipeline,
1179 VkShaderStageFlags stages)
1180 {
1181 unsigned i;
1182 if (!cmd_buffer->state.descriptors_dirty)
1183 return;
1184
1185 for (i = 0; i < MAX_SETS; i++) {
1186 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1187 continue;
1188 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1189 if (!set)
1190 continue;
1191
1192 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1193 }
1194 cmd_buffer->state.descriptors_dirty = 0;
1195 }
1196
1197 static void
1198 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1199 struct radv_pipeline *pipeline,
1200 VkShaderStageFlags stages)
1201 {
1202 struct radv_pipeline_layout *layout = pipeline->layout;
1203 unsigned offset;
1204 void *ptr;
1205 uint64_t va;
1206
1207 stages &= cmd_buffer->push_constant_stages;
1208 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1209 return;
1210
1211 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1212 16 * layout->dynamic_offset_count,
1213 256, &offset, &ptr))
1214 return;
1215
1216 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1217 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1218 16 * layout->dynamic_offset_count);
1219
1220 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1221 va += offset;
1222
1223 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1224 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1225 AC_UD_PUSH_CONSTANTS, va);
1226
1227 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1228 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1229 AC_UD_PUSH_CONSTANTS, va);
1230
1231 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1232 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1233 AC_UD_PUSH_CONSTANTS, va);
1234
1235 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1236 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL,
1237 AC_UD_PUSH_CONSTANTS, va);
1238
1239 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1240 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL,
1241 AC_UD_PUSH_CONSTANTS, va);
1242
1243 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1244 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1245 AC_UD_PUSH_CONSTANTS, va);
1246
1247 cmd_buffer->push_constant_stages &= ~stages;
1248 }
1249
1250 static void
1251 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1252 bool instanced_draw, bool indirect_draw,
1253 uint32_t draw_vertex_count)
1254 {
1255 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1256 struct radv_device *device = cmd_buffer->device;
1257 uint32_t ia_multi_vgt_param;
1258 uint32_t ls_hs_config = 0;
1259
1260 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1261 cmd_buffer->cs, 4096);
1262
1263 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1264 cmd_buffer->state.pipeline->num_vertex_attribs) {
1265 unsigned vb_offset;
1266 void *vb_ptr;
1267 uint32_t i = 0;
1268 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1269 uint64_t va;
1270
1271 /* allocate some descriptor state for vertex buffers */
1272 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1273 &vb_offset, &vb_ptr);
1274
1275 for (i = 0; i < num_attribs; i++) {
1276 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1277 uint32_t offset;
1278 int vb = cmd_buffer->state.pipeline->va_binding[i];
1279 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1280 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1281
1282 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1283 va = device->ws->buffer_get_va(buffer->bo);
1284
1285 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1286 va += offset + buffer->offset;
1287 desc[0] = va;
1288 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1289 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1290 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1291 else
1292 desc[2] = buffer->size - offset;
1293 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1294 }
1295
1296 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1297 va += vb_offset;
1298
1299 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1300 AC_UD_VS_VERTEX_BUFFERS, va);
1301 }
1302
1303 cmd_buffer->state.vertex_descriptors_dirty = false;
1304 cmd_buffer->state.vb_dirty = 0;
1305 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1306 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1307
1308 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1309 radv_emit_framebuffer_state(cmd_buffer);
1310
1311 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1312 radv_emit_viewport(cmd_buffer);
1313
1314 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1315 radv_emit_scissor(cmd_buffer);
1316
1317 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1318 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1319 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1320 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1321 else
1322 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1323 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1324 }
1325
1326 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1327 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1328
1329 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1330 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
1331 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1332 } else {
1333 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1334 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
1335 }
1336 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1337 }
1338
1339 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1340
1341 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1342 VK_SHADER_STAGE_ALL_GRAPHICS);
1343 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1344 VK_SHADER_STAGE_ALL_GRAPHICS);
1345
1346 assert(cmd_buffer->cs->cdw <= cdw_max);
1347
1348 si_emit_cache_flush(cmd_buffer);
1349 }
1350
1351 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1352 VkPipelineStageFlags src_stage_mask)
1353 {
1354 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1355 VK_PIPELINE_STAGE_TRANSFER_BIT |
1356 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1357 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1358 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1359 }
1360
1361 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1362 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1363 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1364 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1365 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1366 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1367 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1368 VK_PIPELINE_STAGE_TRANSFER_BIT |
1369 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1370 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1371 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1372 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1373 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1374 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1375 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1376 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1377 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1378 }
1379 }
1380
1381 static enum radv_cmd_flush_bits
1382 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1383 VkAccessFlags src_flags)
1384 {
1385 enum radv_cmd_flush_bits flush_bits = 0;
1386 uint32_t b;
1387 for_each_bit(b, src_flags) {
1388 switch ((VkAccessFlagBits)(1 << b)) {
1389 case VK_ACCESS_SHADER_WRITE_BIT:
1390 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1391 break;
1392 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1393 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1394 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1395 break;
1396 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1397 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1398 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1399 break;
1400 case VK_ACCESS_TRANSFER_WRITE_BIT:
1401 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1402 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1403 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1404 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1405 RADV_CMD_FLAG_INV_GLOBAL_L2;
1406 break;
1407 default:
1408 break;
1409 }
1410 }
1411 return flush_bits;
1412 }
1413
1414 static enum radv_cmd_flush_bits
1415 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1416 VkAccessFlags dst_flags,
1417 struct radv_image *image)
1418 {
1419 enum radv_cmd_flush_bits flush_bits = 0;
1420 uint32_t b;
1421 for_each_bit(b, dst_flags) {
1422 switch ((VkAccessFlagBits)(1 << b)) {
1423 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1424 case VK_ACCESS_INDEX_READ_BIT:
1425 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1426 break;
1427 case VK_ACCESS_UNIFORM_READ_BIT:
1428 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1429 break;
1430 case VK_ACCESS_SHADER_READ_BIT:
1431 case VK_ACCESS_TRANSFER_READ_BIT:
1432 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1433 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1434 RADV_CMD_FLAG_INV_GLOBAL_L2;
1435 break;
1436 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1437 /* TODO: change to image && when the image gets passed
1438 * through from the subpass. */
1439 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1440 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1441 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1442 break;
1443 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1444 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1445 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1446 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1447 break;
1448 default:
1449 break;
1450 }
1451 }
1452 return flush_bits;
1453 }
1454
1455 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1456 {
1457 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1458 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1459 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1460 NULL);
1461 }
1462
1463 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1464 VkAttachmentReference att)
1465 {
1466 unsigned idx = att.attachment;
1467 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1468 VkImageSubresourceRange range;
1469 range.aspectMask = 0;
1470 range.baseMipLevel = view->base_mip;
1471 range.levelCount = 1;
1472 range.baseArrayLayer = view->base_layer;
1473 range.layerCount = cmd_buffer->state.framebuffer->layers;
1474
1475 radv_handle_image_transition(cmd_buffer,
1476 view->image,
1477 cmd_buffer->state.attachments[idx].current_layout,
1478 att.layout, 0, 0, &range,
1479 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1480
1481 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1482
1483
1484 }
1485
1486 void
1487 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1488 const struct radv_subpass *subpass, bool transitions)
1489 {
1490 if (transitions) {
1491 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1492
1493 for (unsigned i = 0; i < subpass->color_count; ++i) {
1494 radv_handle_subpass_image_transition(cmd_buffer,
1495 subpass->color_attachments[i]);
1496 }
1497
1498 for (unsigned i = 0; i < subpass->input_count; ++i) {
1499 radv_handle_subpass_image_transition(cmd_buffer,
1500 subpass->input_attachments[i]);
1501 }
1502
1503 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1504 radv_handle_subpass_image_transition(cmd_buffer,
1505 subpass->depth_stencil_attachment);
1506 }
1507 }
1508
1509 cmd_buffer->state.subpass = subpass;
1510
1511 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1512 }
1513
1514 static void
1515 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1516 struct radv_render_pass *pass,
1517 const VkRenderPassBeginInfo *info)
1518 {
1519 struct radv_cmd_state *state = &cmd_buffer->state;
1520
1521 if (pass->attachment_count == 0) {
1522 state->attachments = NULL;
1523 return;
1524 }
1525
1526 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1527 pass->attachment_count *
1528 sizeof(state->attachments[0]),
1529 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1530 if (state->attachments == NULL) {
1531 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1532 abort();
1533 }
1534
1535 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1536 struct radv_render_pass_attachment *att = &pass->attachments[i];
1537 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1538 VkImageAspectFlags clear_aspects = 0;
1539
1540 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1541 /* color attachment */
1542 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1543 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1544 }
1545 } else {
1546 /* depthstencil attachment */
1547 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1548 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1549 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1550 }
1551 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1552 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1553 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1554 }
1555 }
1556
1557 state->attachments[i].pending_clear_aspects = clear_aspects;
1558 if (clear_aspects && info) {
1559 assert(info->clearValueCount > i);
1560 state->attachments[i].clear_value = info->pClearValues[i];
1561 }
1562
1563 state->attachments[i].current_layout = att->initial_layout;
1564 }
1565 }
1566
1567 VkResult radv_AllocateCommandBuffers(
1568 VkDevice _device,
1569 const VkCommandBufferAllocateInfo *pAllocateInfo,
1570 VkCommandBuffer *pCommandBuffers)
1571 {
1572 RADV_FROM_HANDLE(radv_device, device, _device);
1573 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1574
1575 VkResult result = VK_SUCCESS;
1576 uint32_t i;
1577
1578 memset(pCommandBuffers, 0,
1579 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1580
1581 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1582
1583 if (!list_empty(&pool->free_cmd_buffers)) {
1584 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1585
1586 list_del(&cmd_buffer->pool_link);
1587 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1588
1589 radv_reset_cmd_buffer(cmd_buffer);
1590 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1591 cmd_buffer->level = pAllocateInfo->level;
1592
1593 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1594 result = VK_SUCCESS;
1595 } else {
1596 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1597 &pCommandBuffers[i]);
1598 }
1599 if (result != VK_SUCCESS)
1600 break;
1601 }
1602
1603 if (result != VK_SUCCESS)
1604 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1605 i, pCommandBuffers);
1606
1607 return result;
1608 }
1609
1610 void radv_FreeCommandBuffers(
1611 VkDevice device,
1612 VkCommandPool commandPool,
1613 uint32_t commandBufferCount,
1614 const VkCommandBuffer *pCommandBuffers)
1615 {
1616 for (uint32_t i = 0; i < commandBufferCount; i++) {
1617 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1618
1619 if (cmd_buffer) {
1620 if (cmd_buffer->pool) {
1621 list_del(&cmd_buffer->pool_link);
1622 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1623 } else
1624 radv_cmd_buffer_destroy(cmd_buffer);
1625
1626 }
1627 }
1628 }
1629
1630 VkResult radv_ResetCommandBuffer(
1631 VkCommandBuffer commandBuffer,
1632 VkCommandBufferResetFlags flags)
1633 {
1634 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1635 radv_reset_cmd_buffer(cmd_buffer);
1636 return VK_SUCCESS;
1637 }
1638
1639 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1640 {
1641 struct radv_device *device = cmd_buffer->device;
1642 if (device->gfx_init) {
1643 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1644 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1645 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1646 radeon_emit(cmd_buffer->cs, va);
1647 radeon_emit(cmd_buffer->cs, (va >> 32) & 0xffff);
1648 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1649 } else
1650 si_init_config(cmd_buffer);
1651 }
1652
1653 VkResult radv_BeginCommandBuffer(
1654 VkCommandBuffer commandBuffer,
1655 const VkCommandBufferBeginInfo *pBeginInfo)
1656 {
1657 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1658 radv_reset_cmd_buffer(cmd_buffer);
1659
1660 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1661
1662 /* setup initial configuration into command buffer */
1663 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1664 switch (cmd_buffer->queue_family_index) {
1665 case RADV_QUEUE_GENERAL:
1666 emit_gfx_buffer_state(cmd_buffer);
1667 radv_set_db_count_control(cmd_buffer);
1668 break;
1669 case RADV_QUEUE_COMPUTE:
1670 si_init_compute(cmd_buffer);
1671 break;
1672 case RADV_QUEUE_TRANSFER:
1673 default:
1674 break;
1675 }
1676 }
1677
1678 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1679 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1680 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1681
1682 struct radv_subpass *subpass =
1683 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1684
1685 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1686 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1687 }
1688
1689 return VK_SUCCESS;
1690 }
1691
1692 void radv_CmdBindVertexBuffers(
1693 VkCommandBuffer commandBuffer,
1694 uint32_t firstBinding,
1695 uint32_t bindingCount,
1696 const VkBuffer* pBuffers,
1697 const VkDeviceSize* pOffsets)
1698 {
1699 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1700 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1701
1702 /* We have to defer setting up vertex buffer since we need the buffer
1703 * stride from the pipeline. */
1704
1705 assert(firstBinding + bindingCount < MAX_VBS);
1706 for (uint32_t i = 0; i < bindingCount; i++) {
1707 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1708 vb[firstBinding + i].offset = pOffsets[i];
1709 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1710 }
1711 }
1712
1713 void radv_CmdBindIndexBuffer(
1714 VkCommandBuffer commandBuffer,
1715 VkBuffer buffer,
1716 VkDeviceSize offset,
1717 VkIndexType indexType)
1718 {
1719 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1720
1721 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1722 cmd_buffer->state.index_offset = offset;
1723 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1724 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1725 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1726 }
1727
1728
1729 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1730 struct radv_descriptor_set *set,
1731 unsigned idx)
1732 {
1733 struct radeon_winsys *ws = cmd_buffer->device->ws;
1734
1735 cmd_buffer->state.descriptors[idx] = set;
1736 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1737 if (!set)
1738 return;
1739
1740 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1741 if (set->descriptors[j])
1742 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1743
1744 if(set->bo)
1745 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1746 }
1747
1748 void radv_CmdBindDescriptorSets(
1749 VkCommandBuffer commandBuffer,
1750 VkPipelineBindPoint pipelineBindPoint,
1751 VkPipelineLayout _layout,
1752 uint32_t firstSet,
1753 uint32_t descriptorSetCount,
1754 const VkDescriptorSet* pDescriptorSets,
1755 uint32_t dynamicOffsetCount,
1756 const uint32_t* pDynamicOffsets)
1757 {
1758 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1759 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1760 unsigned dyn_idx = 0;
1761
1762 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1763 cmd_buffer->cs, MAX_SETS * 4 * 6);
1764
1765 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1766 unsigned idx = i + firstSet;
1767 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1768 radv_bind_descriptor_set(cmd_buffer, set, idx);
1769
1770 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1771 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1772 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1773 assert(dyn_idx < dynamicOffsetCount);
1774
1775 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1776 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1777 dst[0] = va;
1778 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1779 dst[2] = range->size;
1780 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1781 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1782 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1783 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1784 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1785 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1786 cmd_buffer->push_constant_stages |=
1787 set->layout->dynamic_shader_stages;
1788 }
1789 }
1790
1791 assert(cmd_buffer->cs->cdw <= cdw_max);
1792 }
1793
1794 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1795 VkPipelineLayout layout,
1796 VkShaderStageFlags stageFlags,
1797 uint32_t offset,
1798 uint32_t size,
1799 const void* pValues)
1800 {
1801 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1802 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1803 cmd_buffer->push_constant_stages |= stageFlags;
1804 }
1805
1806 VkResult radv_EndCommandBuffer(
1807 VkCommandBuffer commandBuffer)
1808 {
1809 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1810
1811 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
1812 si_emit_cache_flush(cmd_buffer);
1813
1814 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1815 cmd_buffer->record_fail)
1816 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1817 return VK_SUCCESS;
1818 }
1819
1820 static void
1821 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1822 {
1823 struct radeon_winsys *ws = cmd_buffer->device->ws;
1824 struct radv_shader_variant *compute_shader;
1825 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1826 uint64_t va;
1827
1828 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1829 return;
1830
1831 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1832
1833 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1834 va = ws->buffer_get_va(compute_shader->bo);
1835
1836 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1837
1838 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1839 cmd_buffer->cs, 16);
1840
1841 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1842 radeon_emit(cmd_buffer->cs, va >> 8);
1843 radeon_emit(cmd_buffer->cs, va >> 40);
1844
1845 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1846 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1847 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1848
1849
1850 cmd_buffer->compute_scratch_size_needed =
1851 MAX2(cmd_buffer->compute_scratch_size_needed,
1852 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1853
1854 /* change these once we have scratch support */
1855 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1856 S_00B860_WAVES(pipeline->max_waves) |
1857 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1858
1859 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1860 radeon_emit(cmd_buffer->cs,
1861 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1862 radeon_emit(cmd_buffer->cs,
1863 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1864 radeon_emit(cmd_buffer->cs,
1865 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1866
1867 assert(cmd_buffer->cs->cdw <= cdw_max);
1868 }
1869
1870
1871 void radv_CmdBindPipeline(
1872 VkCommandBuffer commandBuffer,
1873 VkPipelineBindPoint pipelineBindPoint,
1874 VkPipeline _pipeline)
1875 {
1876 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1877 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1878
1879 for (unsigned i = 0; i < MAX_SETS; i++) {
1880 if (cmd_buffer->state.descriptors[i])
1881 cmd_buffer->state.descriptors_dirty |= (1 << i);
1882 }
1883
1884 switch (pipelineBindPoint) {
1885 case VK_PIPELINE_BIND_POINT_COMPUTE:
1886 cmd_buffer->state.compute_pipeline = pipeline;
1887 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
1888 break;
1889 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1890 cmd_buffer->state.pipeline = pipeline;
1891 cmd_buffer->state.vertex_descriptors_dirty = true;
1892 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1893 cmd_buffer->push_constant_stages |= pipeline->active_stages;
1894
1895 /* Apply the dynamic state from the pipeline */
1896 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
1897 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
1898 &pipeline->dynamic_state,
1899 pipeline->dynamic_state_mask);
1900
1901 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
1902 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
1903 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
1904 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
1905
1906 if (radv_pipeline_has_gs(pipeline)) {
1907 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1908 AC_UD_SCRATCH_RING_OFFSETS);
1909 if (cmd_buffer->ring_offsets_idx == -1)
1910 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
1911 else if (loc->sgpr_idx != -1)
1912 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
1913 }
1914 break;
1915 default:
1916 assert(!"invalid bind point");
1917 break;
1918 }
1919 }
1920
1921 void radv_CmdSetViewport(
1922 VkCommandBuffer commandBuffer,
1923 uint32_t firstViewport,
1924 uint32_t viewportCount,
1925 const VkViewport* pViewports)
1926 {
1927 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1928
1929 const uint32_t total_count = firstViewport + viewportCount;
1930 if (cmd_buffer->state.dynamic.viewport.count < total_count)
1931 cmd_buffer->state.dynamic.viewport.count = total_count;
1932
1933 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
1934 pViewports, viewportCount * sizeof(*pViewports));
1935
1936 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
1937 }
1938
1939 void radv_CmdSetScissor(
1940 VkCommandBuffer commandBuffer,
1941 uint32_t firstScissor,
1942 uint32_t scissorCount,
1943 const VkRect2D* pScissors)
1944 {
1945 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1946
1947 const uint32_t total_count = firstScissor + scissorCount;
1948 if (cmd_buffer->state.dynamic.scissor.count < total_count)
1949 cmd_buffer->state.dynamic.scissor.count = total_count;
1950
1951 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
1952 pScissors, scissorCount * sizeof(*pScissors));
1953 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1954 }
1955
1956 void radv_CmdSetLineWidth(
1957 VkCommandBuffer commandBuffer,
1958 float lineWidth)
1959 {
1960 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1961 cmd_buffer->state.dynamic.line_width = lineWidth;
1962 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1963 }
1964
1965 void radv_CmdSetDepthBias(
1966 VkCommandBuffer commandBuffer,
1967 float depthBiasConstantFactor,
1968 float depthBiasClamp,
1969 float depthBiasSlopeFactor)
1970 {
1971 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1972
1973 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
1974 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
1975 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
1976
1977 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1978 }
1979
1980 void radv_CmdSetBlendConstants(
1981 VkCommandBuffer commandBuffer,
1982 const float blendConstants[4])
1983 {
1984 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1985
1986 memcpy(cmd_buffer->state.dynamic.blend_constants,
1987 blendConstants, sizeof(float) * 4);
1988
1989 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
1990 }
1991
1992 void radv_CmdSetDepthBounds(
1993 VkCommandBuffer commandBuffer,
1994 float minDepthBounds,
1995 float maxDepthBounds)
1996 {
1997 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1998
1999 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2000 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2001
2002 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2003 }
2004
2005 void radv_CmdSetStencilCompareMask(
2006 VkCommandBuffer commandBuffer,
2007 VkStencilFaceFlags faceMask,
2008 uint32_t compareMask)
2009 {
2010 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2011
2012 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2013 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2014 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2015 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2016
2017 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2018 }
2019
2020 void radv_CmdSetStencilWriteMask(
2021 VkCommandBuffer commandBuffer,
2022 VkStencilFaceFlags faceMask,
2023 uint32_t writeMask)
2024 {
2025 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2026
2027 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2028 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2029 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2030 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2031
2032 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2033 }
2034
2035 void radv_CmdSetStencilReference(
2036 VkCommandBuffer commandBuffer,
2037 VkStencilFaceFlags faceMask,
2038 uint32_t reference)
2039 {
2040 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2041
2042 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2043 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2044 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2045 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2046
2047 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2048 }
2049
2050
2051 void radv_CmdExecuteCommands(
2052 VkCommandBuffer commandBuffer,
2053 uint32_t commandBufferCount,
2054 const VkCommandBuffer* pCmdBuffers)
2055 {
2056 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2057
2058 /* Emit pending flushes on primary prior to executing secondary */
2059 si_emit_cache_flush(primary);
2060
2061 for (uint32_t i = 0; i < commandBufferCount; i++) {
2062 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2063
2064 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2065 secondary->scratch_size_needed);
2066 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2067 secondary->compute_scratch_size_needed);
2068
2069 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2070 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2071 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2072 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2073
2074 if (secondary->ring_offsets_idx != -1) {
2075 if (primary->ring_offsets_idx == -1)
2076 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2077 else
2078 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2079 }
2080 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2081 }
2082
2083 /* if we execute secondary we need to re-emit out pipelines */
2084 if (commandBufferCount) {
2085 primary->state.emitted_pipeline = NULL;
2086 primary->state.emitted_compute_pipeline = NULL;
2087 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2088 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2089 }
2090 }
2091
2092 VkResult radv_CreateCommandPool(
2093 VkDevice _device,
2094 const VkCommandPoolCreateInfo* pCreateInfo,
2095 const VkAllocationCallbacks* pAllocator,
2096 VkCommandPool* pCmdPool)
2097 {
2098 RADV_FROM_HANDLE(radv_device, device, _device);
2099 struct radv_cmd_pool *pool;
2100
2101 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2102 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2103 if (pool == NULL)
2104 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2105
2106 if (pAllocator)
2107 pool->alloc = *pAllocator;
2108 else
2109 pool->alloc = device->alloc;
2110
2111 list_inithead(&pool->cmd_buffers);
2112 list_inithead(&pool->free_cmd_buffers);
2113
2114 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2115
2116 *pCmdPool = radv_cmd_pool_to_handle(pool);
2117
2118 return VK_SUCCESS;
2119
2120 }
2121
2122 void radv_DestroyCommandPool(
2123 VkDevice _device,
2124 VkCommandPool commandPool,
2125 const VkAllocationCallbacks* pAllocator)
2126 {
2127 RADV_FROM_HANDLE(radv_device, device, _device);
2128 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2129
2130 if (!pool)
2131 return;
2132
2133 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2134 &pool->cmd_buffers, pool_link) {
2135 radv_cmd_buffer_destroy(cmd_buffer);
2136 }
2137
2138 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2139 &pool->free_cmd_buffers, pool_link) {
2140 radv_cmd_buffer_destroy(cmd_buffer);
2141 }
2142
2143 vk_free2(&device->alloc, pAllocator, pool);
2144 }
2145
2146 VkResult radv_ResetCommandPool(
2147 VkDevice device,
2148 VkCommandPool commandPool,
2149 VkCommandPoolResetFlags flags)
2150 {
2151 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2152
2153 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2154 &pool->cmd_buffers, pool_link) {
2155 radv_reset_cmd_buffer(cmd_buffer);
2156 }
2157
2158 return VK_SUCCESS;
2159 }
2160
2161 void radv_TrimCommandPoolKHR(
2162 VkDevice device,
2163 VkCommandPool commandPool,
2164 VkCommandPoolTrimFlagsKHR flags)
2165 {
2166 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2167
2168 if (!pool)
2169 return;
2170
2171 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2172 &pool->free_cmd_buffers, pool_link) {
2173 radv_cmd_buffer_destroy(cmd_buffer);
2174 }
2175 }
2176
2177 void radv_CmdBeginRenderPass(
2178 VkCommandBuffer commandBuffer,
2179 const VkRenderPassBeginInfo* pRenderPassBegin,
2180 VkSubpassContents contents)
2181 {
2182 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2183 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2184 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2185
2186 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2187 cmd_buffer->cs, 2048);
2188
2189 cmd_buffer->state.framebuffer = framebuffer;
2190 cmd_buffer->state.pass = pass;
2191 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2192 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2193
2194 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2195 assert(cmd_buffer->cs->cdw <= cdw_max);
2196
2197 radv_cmd_buffer_clear_subpass(cmd_buffer);
2198 }
2199
2200 void radv_CmdNextSubpass(
2201 VkCommandBuffer commandBuffer,
2202 VkSubpassContents contents)
2203 {
2204 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2205
2206 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2207
2208 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2209 2048);
2210
2211 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2212 radv_cmd_buffer_clear_subpass(cmd_buffer);
2213 }
2214
2215 void radv_CmdDraw(
2216 VkCommandBuffer commandBuffer,
2217 uint32_t vertexCount,
2218 uint32_t instanceCount,
2219 uint32_t firstVertex,
2220 uint32_t firstInstance)
2221 {
2222 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2223
2224 radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, vertexCount);
2225
2226 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2227
2228 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2229 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2230 if (loc->sgpr_idx != -1) {
2231 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2232 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2233 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2234 radeon_emit(cmd_buffer->cs, firstVertex);
2235 radeon_emit(cmd_buffer->cs, firstInstance);
2236 radeon_emit(cmd_buffer->cs, 0);
2237 }
2238 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2239 radeon_emit(cmd_buffer->cs, instanceCount);
2240
2241 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2242 radeon_emit(cmd_buffer->cs, vertexCount);
2243 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2244 S_0287F0_USE_OPAQUE(0));
2245
2246 assert(cmd_buffer->cs->cdw <= cdw_max);
2247
2248 radv_cmd_buffer_trace_emit(cmd_buffer);
2249 }
2250
2251 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2252 {
2253 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
2254
2255 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
2256 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
2257 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
2258 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2259 primitive_reset_index);
2260 }
2261 }
2262
2263 void radv_CmdDrawIndexed(
2264 VkCommandBuffer commandBuffer,
2265 uint32_t indexCount,
2266 uint32_t instanceCount,
2267 uint32_t firstIndex,
2268 int32_t vertexOffset,
2269 uint32_t firstInstance)
2270 {
2271 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2272 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2273 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2274 uint64_t index_va;
2275
2276 radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, indexCount);
2277 radv_emit_primitive_reset_index(cmd_buffer);
2278
2279 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2280
2281 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2282 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2283
2284 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2285 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2286 if (loc->sgpr_idx != -1) {
2287 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2288 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2289 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2290 radeon_emit(cmd_buffer->cs, vertexOffset);
2291 radeon_emit(cmd_buffer->cs, firstInstance);
2292 radeon_emit(cmd_buffer->cs, 0);
2293 }
2294 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2295 radeon_emit(cmd_buffer->cs, instanceCount);
2296
2297 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2298 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2299 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2300 radeon_emit(cmd_buffer->cs, index_max_size);
2301 radeon_emit(cmd_buffer->cs, index_va);
2302 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2303 radeon_emit(cmd_buffer->cs, indexCount);
2304 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2305
2306 assert(cmd_buffer->cs->cdw <= cdw_max);
2307 radv_cmd_buffer_trace_emit(cmd_buffer);
2308 }
2309
2310 static void
2311 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2312 VkBuffer _buffer,
2313 VkDeviceSize offset,
2314 VkBuffer _count_buffer,
2315 VkDeviceSize count_offset,
2316 uint32_t draw_count,
2317 uint32_t stride,
2318 bool indexed)
2319 {
2320 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2321 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2322 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2323 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2324 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2325 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2326 indirect_va += offset + buffer->offset;
2327 uint64_t count_va = 0;
2328
2329 if (count_buffer) {
2330 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2331 count_va += count_offset + count_buffer->offset;
2332 }
2333
2334 if (!draw_count)
2335 return;
2336
2337 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2338
2339 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2340 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2341 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2342 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2343 assert(loc->sgpr_idx != -1);
2344 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2345 radeon_emit(cs, 1);
2346 radeon_emit(cs, indirect_va);
2347 radeon_emit(cs, indirect_va >> 32);
2348
2349 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2350 PKT3_DRAW_INDIRECT_MULTI,
2351 8, false));
2352 radeon_emit(cs, 0);
2353 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2354 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2355 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2356 S_2C3_DRAW_INDEX_ENABLE(1) |
2357 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2358 radeon_emit(cs, draw_count); /* count */
2359 radeon_emit(cs, count_va); /* count_addr */
2360 radeon_emit(cs, count_va >> 32);
2361 radeon_emit(cs, stride); /* stride */
2362 radeon_emit(cs, di_src_sel);
2363 radv_cmd_buffer_trace_emit(cmd_buffer);
2364 }
2365
2366 static void
2367 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2368 VkBuffer buffer,
2369 VkDeviceSize offset,
2370 VkBuffer countBuffer,
2371 VkDeviceSize countBufferOffset,
2372 uint32_t maxDrawCount,
2373 uint32_t stride)
2374 {
2375 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2376 radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0);
2377
2378 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2379 cmd_buffer->cs, 14);
2380
2381 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2382 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2383
2384 assert(cmd_buffer->cs->cdw <= cdw_max);
2385 }
2386
2387 static void
2388 radv_cmd_draw_indexed_indirect_count(
2389 VkCommandBuffer commandBuffer,
2390 VkBuffer buffer,
2391 VkDeviceSize offset,
2392 VkBuffer countBuffer,
2393 VkDeviceSize countBufferOffset,
2394 uint32_t maxDrawCount,
2395 uint32_t stride)
2396 {
2397 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2398 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2399 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2400 uint64_t index_va;
2401 radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0);
2402 radv_emit_primitive_reset_index(cmd_buffer);
2403
2404 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2405 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2406
2407 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2408
2409 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2410 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2411
2412 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2413 radeon_emit(cmd_buffer->cs, index_va);
2414 radeon_emit(cmd_buffer->cs, index_va >> 32);
2415
2416 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2417 radeon_emit(cmd_buffer->cs, index_max_size);
2418
2419 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2420 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2421
2422 assert(cmd_buffer->cs->cdw <= cdw_max);
2423 }
2424
2425 void radv_CmdDrawIndirect(
2426 VkCommandBuffer commandBuffer,
2427 VkBuffer buffer,
2428 VkDeviceSize offset,
2429 uint32_t drawCount,
2430 uint32_t stride)
2431 {
2432 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2433 VK_NULL_HANDLE, 0, drawCount, stride);
2434 }
2435
2436 void radv_CmdDrawIndexedIndirect(
2437 VkCommandBuffer commandBuffer,
2438 VkBuffer buffer,
2439 VkDeviceSize offset,
2440 uint32_t drawCount,
2441 uint32_t stride)
2442 {
2443 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2444 VK_NULL_HANDLE, 0, drawCount, stride);
2445 }
2446
2447 void radv_CmdDrawIndirectCountAMD(
2448 VkCommandBuffer commandBuffer,
2449 VkBuffer buffer,
2450 VkDeviceSize offset,
2451 VkBuffer countBuffer,
2452 VkDeviceSize countBufferOffset,
2453 uint32_t maxDrawCount,
2454 uint32_t stride)
2455 {
2456 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2457 countBuffer, countBufferOffset,
2458 maxDrawCount, stride);
2459 }
2460
2461 void radv_CmdDrawIndexedIndirectCountAMD(
2462 VkCommandBuffer commandBuffer,
2463 VkBuffer buffer,
2464 VkDeviceSize offset,
2465 VkBuffer countBuffer,
2466 VkDeviceSize countBufferOffset,
2467 uint32_t maxDrawCount,
2468 uint32_t stride)
2469 {
2470 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2471 countBuffer, countBufferOffset,
2472 maxDrawCount, stride);
2473 }
2474
2475 static void
2476 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2477 {
2478 radv_emit_compute_pipeline(cmd_buffer);
2479 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2480 VK_SHADER_STAGE_COMPUTE_BIT);
2481 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2482 VK_SHADER_STAGE_COMPUTE_BIT);
2483 si_emit_cache_flush(cmd_buffer);
2484 }
2485
2486 void radv_CmdDispatch(
2487 VkCommandBuffer commandBuffer,
2488 uint32_t x,
2489 uint32_t y,
2490 uint32_t z)
2491 {
2492 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2493
2494 radv_flush_compute_state(cmd_buffer);
2495
2496 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2497
2498 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2499 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2500 if (loc->sgpr_idx != -1) {
2501 assert(!loc->indirect);
2502 assert(loc->num_sgprs == 3);
2503 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2504 radeon_emit(cmd_buffer->cs, x);
2505 radeon_emit(cmd_buffer->cs, y);
2506 radeon_emit(cmd_buffer->cs, z);
2507 }
2508
2509 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2510 PKT3_SHADER_TYPE_S(1));
2511 radeon_emit(cmd_buffer->cs, x);
2512 radeon_emit(cmd_buffer->cs, y);
2513 radeon_emit(cmd_buffer->cs, z);
2514 radeon_emit(cmd_buffer->cs, 1);
2515
2516 assert(cmd_buffer->cs->cdw <= cdw_max);
2517 radv_cmd_buffer_trace_emit(cmd_buffer);
2518 }
2519
2520 void radv_CmdDispatchIndirect(
2521 VkCommandBuffer commandBuffer,
2522 VkBuffer _buffer,
2523 VkDeviceSize offset)
2524 {
2525 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2526 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2527 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2528 va += buffer->offset + offset;
2529
2530 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2531
2532 radv_flush_compute_state(cmd_buffer);
2533
2534 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2535 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2536 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2537 if (loc->sgpr_idx != -1) {
2538 for (unsigned i = 0; i < 3; ++i) {
2539 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2540 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2541 COPY_DATA_DST_SEL(COPY_DATA_REG));
2542 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2543 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2544 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2545 radeon_emit(cmd_buffer->cs, 0);
2546 }
2547 }
2548
2549 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2550 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2551 PKT3_SHADER_TYPE_S(1));
2552 radeon_emit(cmd_buffer->cs, va);
2553 radeon_emit(cmd_buffer->cs, va >> 32);
2554 radeon_emit(cmd_buffer->cs, 1);
2555 } else {
2556 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2557 PKT3_SHADER_TYPE_S(1));
2558 radeon_emit(cmd_buffer->cs, 1);
2559 radeon_emit(cmd_buffer->cs, va);
2560 radeon_emit(cmd_buffer->cs, va >> 32);
2561
2562 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2563 PKT3_SHADER_TYPE_S(1));
2564 radeon_emit(cmd_buffer->cs, 0);
2565 radeon_emit(cmd_buffer->cs, 1);
2566 }
2567
2568 assert(cmd_buffer->cs->cdw <= cdw_max);
2569 radv_cmd_buffer_trace_emit(cmd_buffer);
2570 }
2571
2572 void radv_unaligned_dispatch(
2573 struct radv_cmd_buffer *cmd_buffer,
2574 uint32_t x,
2575 uint32_t y,
2576 uint32_t z)
2577 {
2578 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2579 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2580 uint32_t blocks[3], remainder[3];
2581
2582 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2583 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2584 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2585
2586 /* If aligned, these should be an entire block size, not 0 */
2587 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2588 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2589 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2590
2591 radv_flush_compute_state(cmd_buffer);
2592
2593 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2594
2595 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2596 radeon_emit(cmd_buffer->cs,
2597 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2598 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2599 radeon_emit(cmd_buffer->cs,
2600 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2601 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2602 radeon_emit(cmd_buffer->cs,
2603 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2604 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2605
2606 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2607 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2608 if (loc->sgpr_idx != -1) {
2609 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2610 radeon_emit(cmd_buffer->cs, blocks[0]);
2611 radeon_emit(cmd_buffer->cs, blocks[1]);
2612 radeon_emit(cmd_buffer->cs, blocks[2]);
2613 }
2614 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2615 PKT3_SHADER_TYPE_S(1));
2616 radeon_emit(cmd_buffer->cs, blocks[0]);
2617 radeon_emit(cmd_buffer->cs, blocks[1]);
2618 radeon_emit(cmd_buffer->cs, blocks[2]);
2619 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2620 S_00B800_PARTIAL_TG_EN(1));
2621
2622 assert(cmd_buffer->cs->cdw <= cdw_max);
2623 radv_cmd_buffer_trace_emit(cmd_buffer);
2624 }
2625
2626 void radv_CmdEndRenderPass(
2627 VkCommandBuffer commandBuffer)
2628 {
2629 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2630
2631 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2632
2633 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2634
2635 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2636 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2637 radv_handle_subpass_image_transition(cmd_buffer,
2638 (VkAttachmentReference){i, layout});
2639 }
2640
2641 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2642
2643 cmd_buffer->state.pass = NULL;
2644 cmd_buffer->state.subpass = NULL;
2645 cmd_buffer->state.attachments = NULL;
2646 cmd_buffer->state.framebuffer = NULL;
2647 }
2648
2649
2650 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2651 struct radv_image *image,
2652 const VkImageSubresourceRange *range)
2653 {
2654 assert(range->baseMipLevel == 0);
2655 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
2656 unsigned layer_count = radv_get_layerCount(image, range);
2657 uint64_t size = image->surface.htile_slice_size * layer_count;
2658 uint64_t offset = image->offset + image->htile_offset +
2659 image->surface.htile_slice_size * range->baseArrayLayer;
2660
2661 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2662 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2663
2664 radv_fill_buffer(cmd_buffer, image->bo, offset, size, 0xffffffff);
2665
2666 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2667 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2668 RADV_CMD_FLAG_INV_VMEM_L1 |
2669 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2670 }
2671
2672 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2673 struct radv_image *image,
2674 VkImageLayout src_layout,
2675 VkImageLayout dst_layout,
2676 const VkImageSubresourceRange *range,
2677 VkImageAspectFlags pending_clears)
2678 {
2679 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2680 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2681 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2682 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2683 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2684 /* The clear will initialize htile. */
2685 return;
2686 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2687 radv_layout_has_htile(image, dst_layout)) {
2688 /* TODO: merge with the clear if applicable */
2689 radv_initialize_htile(cmd_buffer, image, range);
2690 } else if (!radv_layout_has_htile(image, src_layout) &&
2691 radv_layout_has_htile(image, dst_layout)) {
2692 radv_initialize_htile(cmd_buffer, image, range);
2693 } else if ((radv_layout_has_htile(image, src_layout) &&
2694 !radv_layout_has_htile(image, dst_layout)) ||
2695 (radv_layout_is_htile_compressed(image, src_layout) &&
2696 !radv_layout_is_htile_compressed(image, dst_layout))) {
2697 VkImageSubresourceRange local_range = *range;
2698 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2699 local_range.baseMipLevel = 0;
2700 local_range.levelCount = 1;
2701
2702 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2703 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2704
2705 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
2706
2707 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2708 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2709 }
2710 }
2711
2712 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2713 struct radv_image *image, uint32_t value)
2714 {
2715 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2716 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2717
2718 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2719 image->cmask.size, value);
2720
2721 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2722 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2723 RADV_CMD_FLAG_INV_VMEM_L1 |
2724 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2725 }
2726
2727 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2728 struct radv_image *image,
2729 VkImageLayout src_layout,
2730 VkImageLayout dst_layout,
2731 unsigned src_queue_mask,
2732 unsigned dst_queue_mask,
2733 const VkImageSubresourceRange *range,
2734 VkImageAspectFlags pending_clears)
2735 {
2736 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2737 if (image->fmask.size)
2738 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2739 else
2740 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2741 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2742 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2743 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
2744 }
2745 }
2746
2747 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2748 struct radv_image *image, uint32_t value)
2749 {
2750
2751 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2752 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2753
2754 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2755 image->surface.dcc_size, value);
2756
2757 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2758 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2759 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2760 RADV_CMD_FLAG_INV_VMEM_L1 |
2761 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2762 }
2763
2764 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2765 struct radv_image *image,
2766 VkImageLayout src_layout,
2767 VkImageLayout dst_layout,
2768 unsigned src_queue_mask,
2769 unsigned dst_queue_mask,
2770 const VkImageSubresourceRange *range,
2771 VkImageAspectFlags pending_clears)
2772 {
2773 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2774 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2775 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2776 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2777 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
2778 }
2779 }
2780
2781 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2782 struct radv_image *image,
2783 VkImageLayout src_layout,
2784 VkImageLayout dst_layout,
2785 uint32_t src_family,
2786 uint32_t dst_family,
2787 const VkImageSubresourceRange *range,
2788 VkImageAspectFlags pending_clears)
2789 {
2790 if (image->exclusive && src_family != dst_family) {
2791 /* This is an acquire or a release operation and there will be
2792 * a corresponding release/acquire. Do the transition in the
2793 * most flexible queue. */
2794
2795 assert(src_family == cmd_buffer->queue_family_index ||
2796 dst_family == cmd_buffer->queue_family_index);
2797
2798 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
2799 return;
2800
2801 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
2802 (src_family == RADV_QUEUE_GENERAL ||
2803 dst_family == RADV_QUEUE_GENERAL))
2804 return;
2805 }
2806
2807 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
2808 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
2809
2810 if (image->surface.htile_size)
2811 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2812 dst_layout, range, pending_clears);
2813
2814 if (image->cmask.size)
2815 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2816 dst_layout, src_queue_mask,
2817 dst_queue_mask, range,
2818 pending_clears);
2819
2820 if (image->surface.dcc_size)
2821 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2822 dst_layout, src_queue_mask,
2823 dst_queue_mask, range,
2824 pending_clears);
2825 }
2826
2827 void radv_CmdPipelineBarrier(
2828 VkCommandBuffer commandBuffer,
2829 VkPipelineStageFlags srcStageMask,
2830 VkPipelineStageFlags destStageMask,
2831 VkBool32 byRegion,
2832 uint32_t memoryBarrierCount,
2833 const VkMemoryBarrier* pMemoryBarriers,
2834 uint32_t bufferMemoryBarrierCount,
2835 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2836 uint32_t imageMemoryBarrierCount,
2837 const VkImageMemoryBarrier* pImageMemoryBarriers)
2838 {
2839 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2840 enum radv_cmd_flush_bits src_flush_bits = 0;
2841 enum radv_cmd_flush_bits dst_flush_bits = 0;
2842
2843 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2844 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
2845 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
2846 NULL);
2847 }
2848
2849 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2850 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
2851 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
2852 NULL);
2853 }
2854
2855 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2856 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2857 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
2858 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
2859 image);
2860 }
2861
2862 radv_stage_flush(cmd_buffer, srcStageMask);
2863 cmd_buffer->state.flush_bits |= src_flush_bits;
2864
2865 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2866 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2867 radv_handle_image_transition(cmd_buffer, image,
2868 pImageMemoryBarriers[i].oldLayout,
2869 pImageMemoryBarriers[i].newLayout,
2870 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2871 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2872 &pImageMemoryBarriers[i].subresourceRange,
2873 0);
2874 }
2875
2876 cmd_buffer->state.flush_bits |= dst_flush_bits;
2877 }
2878
2879
2880 static void write_event(struct radv_cmd_buffer *cmd_buffer,
2881 struct radv_event *event,
2882 VkPipelineStageFlags stageMask,
2883 unsigned value)
2884 {
2885 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2886 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2887
2888 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2889
2890 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
2891
2892 /* TODO: this is overkill. Probably should figure something out from
2893 * the stage mask. */
2894
2895 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
2896 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2897 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2898 EVENT_INDEX(5));
2899 radeon_emit(cs, va);
2900 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2901 radeon_emit(cs, 2);
2902 radeon_emit(cs, 0);
2903 }
2904
2905 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2906 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2907 EVENT_INDEX(5));
2908 radeon_emit(cs, va);
2909 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2910 radeon_emit(cs, value);
2911 radeon_emit(cs, 0);
2912
2913 assert(cmd_buffer->cs->cdw <= cdw_max);
2914 }
2915
2916 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
2917 VkEvent _event,
2918 VkPipelineStageFlags stageMask)
2919 {
2920 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2921 RADV_FROM_HANDLE(radv_event, event, _event);
2922
2923 write_event(cmd_buffer, event, stageMask, 1);
2924 }
2925
2926 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
2927 VkEvent _event,
2928 VkPipelineStageFlags stageMask)
2929 {
2930 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2931 RADV_FROM_HANDLE(radv_event, event, _event);
2932
2933 write_event(cmd_buffer, event, stageMask, 0);
2934 }
2935
2936 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
2937 uint32_t eventCount,
2938 const VkEvent* pEvents,
2939 VkPipelineStageFlags srcStageMask,
2940 VkPipelineStageFlags dstStageMask,
2941 uint32_t memoryBarrierCount,
2942 const VkMemoryBarrier* pMemoryBarriers,
2943 uint32_t bufferMemoryBarrierCount,
2944 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2945 uint32_t imageMemoryBarrierCount,
2946 const VkImageMemoryBarrier* pImageMemoryBarriers)
2947 {
2948 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2949 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2950
2951 for (unsigned i = 0; i < eventCount; ++i) {
2952 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
2953 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2954
2955 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2956
2957 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
2958
2959 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
2960 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
2961 radeon_emit(cs, va);
2962 radeon_emit(cs, va >> 32);
2963 radeon_emit(cs, 1); /* reference value */
2964 radeon_emit(cs, 0xffffffff); /* mask */
2965 radeon_emit(cs, 4); /* poll interval */
2966
2967 assert(cmd_buffer->cs->cdw <= cdw_max);
2968 }
2969
2970
2971 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2972 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2973
2974 radv_handle_image_transition(cmd_buffer, image,
2975 pImageMemoryBarriers[i].oldLayout,
2976 pImageMemoryBarriers[i].newLayout,
2977 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2978 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2979 &pImageMemoryBarriers[i].subresourceRange,
2980 0);
2981 }
2982
2983 /* TODO: figure out how to do memory barriers without waiting */
2984 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
2985 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2986 RADV_CMD_FLAG_INV_VMEM_L1 |
2987 RADV_CMD_FLAG_INV_SMEM_L1;
2988 }