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radv: simplify the logic in radv_set_descriptor_set()
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safely call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
314 cmd_buffer->descriptors[i].dirty = 0;
315 cmd_buffer->descriptors[i].valid = 0;
316 cmd_buffer->descriptors[i].push_dirty = false;
317 }
318
319 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
320 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
321 unsigned eop_bug_offset;
322 void *fence_ptr;
323
324 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
325 &cmd_buffer->gfx9_fence_offset,
326 &fence_ptr);
327 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
328
329 /* Allocate a buffer for the EOP bug on GFX9. */
330 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
331 &eop_bug_offset, &fence_ptr);
332 cmd_buffer->gfx9_eop_bug_va =
333 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
334 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
335 }
336
337 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
338
339 return cmd_buffer->record_result;
340 }
341
342 static bool
343 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
344 uint64_t min_needed)
345 {
346 uint64_t new_size;
347 struct radeon_winsys_bo *bo;
348 struct radv_cmd_buffer_upload *upload;
349 struct radv_device *device = cmd_buffer->device;
350
351 new_size = MAX2(min_needed, 16 * 1024);
352 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
353
354 bo = device->ws->buffer_create(device->ws,
355 new_size, 4096,
356 RADEON_DOMAIN_GTT,
357 RADEON_FLAG_CPU_ACCESS|
358 RADEON_FLAG_NO_INTERPROCESS_SHARING |
359 RADEON_FLAG_32BIT);
360
361 if (!bo) {
362 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
363 return false;
364 }
365
366 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
367 if (cmd_buffer->upload.upload_bo) {
368 upload = malloc(sizeof(*upload));
369
370 if (!upload) {
371 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
372 device->ws->buffer_destroy(bo);
373 return false;
374 }
375
376 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
377 list_add(&upload->list, &cmd_buffer->upload.list);
378 }
379
380 cmd_buffer->upload.upload_bo = bo;
381 cmd_buffer->upload.size = new_size;
382 cmd_buffer->upload.offset = 0;
383 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
384
385 if (!cmd_buffer->upload.map) {
386 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
387 return false;
388 }
389
390 return true;
391 }
392
393 bool
394 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
395 unsigned size,
396 unsigned alignment,
397 unsigned *out_offset,
398 void **ptr)
399 {
400 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
401 if (offset + size > cmd_buffer->upload.size) {
402 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
403 return false;
404 offset = 0;
405 }
406
407 *out_offset = offset;
408 *ptr = cmd_buffer->upload.map + offset;
409
410 cmd_buffer->upload.offset = offset + size;
411 return true;
412 }
413
414 bool
415 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
416 unsigned size, unsigned alignment,
417 const void *data, unsigned *out_offset)
418 {
419 uint8_t *ptr;
420
421 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
422 out_offset, (void **)&ptr))
423 return false;
424
425 if (ptr)
426 memcpy(ptr, data, size);
427
428 return true;
429 }
430
431 static void
432 radv_emit_write_data_packet(struct radeon_cmdbuf *cs, uint64_t va,
433 unsigned count, const uint32_t *data)
434 {
435 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
436 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
437 S_370_WR_CONFIRM(1) |
438 S_370_ENGINE_SEL(V_370_ME));
439 radeon_emit(cs, va);
440 radeon_emit(cs, va >> 32);
441 radeon_emit_array(cs, data, count);
442 }
443
444 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
445 {
446 struct radv_device *device = cmd_buffer->device;
447 struct radeon_cmdbuf *cs = cmd_buffer->cs;
448 uint64_t va;
449
450 va = radv_buffer_get_va(device->trace_bo);
451 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
452 va += 4;
453
454 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
455
456 ++cmd_buffer->state.trace_id;
457 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
458 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
459 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
460 }
461
462 static void
463 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
464 enum radv_cmd_flush_bits flags)
465 {
466 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
467 uint32_t *ptr = NULL;
468 uint64_t va = 0;
469
470 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
471 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
472
473 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
474 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
475 cmd_buffer->gfx9_fence_offset;
476 ptr = &cmd_buffer->gfx9_fence_idx;
477 }
478
479 /* Force wait for graphics or compute engines to be idle. */
480 si_cs_emit_cache_flush(cmd_buffer->cs,
481 cmd_buffer->device->physical_device->rad_info.chip_class,
482 ptr, va,
483 radv_cmd_buffer_uses_mec(cmd_buffer),
484 flags, cmd_buffer->gfx9_eop_bug_va);
485 }
486
487 if (unlikely(cmd_buffer->device->trace_bo))
488 radv_cmd_buffer_trace_emit(cmd_buffer);
489 }
490
491 static void
492 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
493 struct radv_pipeline *pipeline, enum ring_type ring)
494 {
495 struct radv_device *device = cmd_buffer->device;
496 struct radeon_cmdbuf *cs = cmd_buffer->cs;
497 uint32_t data[2];
498 uint64_t va;
499
500 va = radv_buffer_get_va(device->trace_bo);
501
502 switch (ring) {
503 case RING_GFX:
504 va += 8;
505 break;
506 case RING_COMPUTE:
507 va += 16;
508 break;
509 default:
510 assert(!"invalid ring type");
511 }
512
513 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
514 cmd_buffer->cs, 6);
515
516 data[0] = (uintptr_t)pipeline;
517 data[1] = (uintptr_t)pipeline >> 32;
518
519 radv_emit_write_data_packet(cs, va, 2, data);
520 }
521
522 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
523 VkPipelineBindPoint bind_point,
524 struct radv_descriptor_set *set,
525 unsigned idx)
526 {
527 struct radv_descriptor_state *descriptors_state =
528 radv_get_descriptors_state(cmd_buffer, bind_point);
529
530 descriptors_state->sets[idx] = set;
531
532 descriptors_state->valid |= (1u << idx); /* active descriptors */
533 descriptors_state->dirty |= (1u << idx);
534 }
535
536 static void
537 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
538 VkPipelineBindPoint bind_point)
539 {
540 struct radv_descriptor_state *descriptors_state =
541 radv_get_descriptors_state(cmd_buffer, bind_point);
542 struct radv_device *device = cmd_buffer->device;
543 struct radeon_cmdbuf *cs = cmd_buffer->cs;
544 uint32_t data[MAX_SETS * 2] = {};
545 uint64_t va;
546 unsigned i;
547 va = radv_buffer_get_va(device->trace_bo) + 24;
548
549 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
550 cmd_buffer->cs, 4 + MAX_SETS * 2);
551
552 for_each_bit(i, descriptors_state->valid) {
553 struct radv_descriptor_set *set = descriptors_state->sets[i];
554 data[i * 2] = (uintptr_t)set;
555 data[i * 2 + 1] = (uintptr_t)set >> 32;
556 }
557
558 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
559 }
560
561 struct radv_userdata_info *
562 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
563 gl_shader_stage stage,
564 int idx)
565 {
566 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
567 return &shader->info.user_sgprs_locs.shader_data[idx];
568 }
569
570 static void
571 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
572 struct radv_pipeline *pipeline,
573 gl_shader_stage stage,
574 int idx, uint64_t va)
575 {
576 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
577 uint32_t base_reg = pipeline->user_data_0[stage];
578 if (loc->sgpr_idx == -1)
579 return;
580
581 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
582 assert(!loc->indirect);
583
584 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
585 base_reg + loc->sgpr_idx * 4, va, false);
586 }
587
588 static void
589 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
590 struct radv_pipeline *pipeline,
591 struct radv_descriptor_state *descriptors_state,
592 gl_shader_stage stage)
593 {
594 struct radv_device *device = cmd_buffer->device;
595 struct radeon_cmdbuf *cs = cmd_buffer->cs;
596 uint32_t sh_base = pipeline->user_data_0[stage];
597 struct radv_userdata_locations *locs =
598 &pipeline->shaders[stage]->info.user_sgprs_locs;
599 unsigned mask = locs->descriptor_sets_enabled;
600
601 mask &= descriptors_state->dirty & descriptors_state->valid;
602
603 while (mask) {
604 int start, count;
605
606 u_bit_scan_consecutive_range(&mask, &start, &count);
607
608 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
609 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
610
611 radv_emit_shader_pointer_head(cs, sh_offset, count,
612 HAVE_32BIT_POINTERS);
613 for (int i = 0; i < count; i++) {
614 struct radv_descriptor_set *set =
615 descriptors_state->sets[start + i];
616
617 radv_emit_shader_pointer_body(device, cs, set->va,
618 HAVE_32BIT_POINTERS);
619 }
620 }
621 }
622
623 static void
624 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
625 struct radv_pipeline *pipeline)
626 {
627 int num_samples = pipeline->graphics.ms.num_samples;
628 struct radv_multisample_state *ms = &pipeline->graphics.ms;
629 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
630
631 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
632 cmd_buffer->sample_positions_needed = true;
633
634 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
635 return;
636
637 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
638 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
639 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
640
641 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
642
643 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
644
645 /* GFX9: Flush DFSM when the AA mode changes. */
646 if (cmd_buffer->device->dfsm_allowed) {
647 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
648 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
649 }
650 }
651
652 static void
653 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
654 struct radv_shader_variant *shader)
655 {
656 uint64_t va;
657
658 if (!shader)
659 return;
660
661 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
662
663 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
664 }
665
666 static void
667 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
668 struct radv_pipeline *pipeline,
669 bool vertex_stage_only)
670 {
671 struct radv_cmd_state *state = &cmd_buffer->state;
672 uint32_t mask = state->prefetch_L2_mask;
673
674 if (vertex_stage_only) {
675 /* Fast prefetch path for starting draws as soon as possible.
676 */
677 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
678 RADV_PREFETCH_VBO_DESCRIPTORS);
679 }
680
681 if (mask & RADV_PREFETCH_VS)
682 radv_emit_shader_prefetch(cmd_buffer,
683 pipeline->shaders[MESA_SHADER_VERTEX]);
684
685 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
686 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
687
688 if (mask & RADV_PREFETCH_TCS)
689 radv_emit_shader_prefetch(cmd_buffer,
690 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
691
692 if (mask & RADV_PREFETCH_TES)
693 radv_emit_shader_prefetch(cmd_buffer,
694 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
695
696 if (mask & RADV_PREFETCH_GS) {
697 radv_emit_shader_prefetch(cmd_buffer,
698 pipeline->shaders[MESA_SHADER_GEOMETRY]);
699 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
700 }
701
702 if (mask & RADV_PREFETCH_PS)
703 radv_emit_shader_prefetch(cmd_buffer,
704 pipeline->shaders[MESA_SHADER_FRAGMENT]);
705
706 state->prefetch_L2_mask &= ~mask;
707 }
708
709 static void
710 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
711 {
712 if (!cmd_buffer->device->physical_device->rbplus_allowed)
713 return;
714
715 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
716 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
717 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
718
719 unsigned sx_ps_downconvert = 0;
720 unsigned sx_blend_opt_epsilon = 0;
721 unsigned sx_blend_opt_control = 0;
722
723 for (unsigned i = 0; i < subpass->color_count; ++i) {
724 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
725 continue;
726
727 int idx = subpass->color_attachments[i].attachment;
728 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
729
730 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
731 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
732 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
733 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
734
735 bool has_alpha, has_rgb;
736
737 /* Set if RGB and A are present. */
738 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
739
740 if (format == V_028C70_COLOR_8 ||
741 format == V_028C70_COLOR_16 ||
742 format == V_028C70_COLOR_32)
743 has_rgb = !has_alpha;
744 else
745 has_rgb = true;
746
747 /* Check the colormask and export format. */
748 if (!(colormask & 0x7))
749 has_rgb = false;
750 if (!(colormask & 0x8))
751 has_alpha = false;
752
753 if (spi_format == V_028714_SPI_SHADER_ZERO) {
754 has_rgb = false;
755 has_alpha = false;
756 }
757
758 /* Disable value checking for disabled channels. */
759 if (!has_rgb)
760 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
761 if (!has_alpha)
762 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
763
764 /* Enable down-conversion for 32bpp and smaller formats. */
765 switch (format) {
766 case V_028C70_COLOR_8:
767 case V_028C70_COLOR_8_8:
768 case V_028C70_COLOR_8_8_8_8:
769 /* For 1 and 2-channel formats, use the superset thereof. */
770 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
771 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
772 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
773 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
774 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
775 }
776 break;
777
778 case V_028C70_COLOR_5_6_5:
779 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
780 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
781 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
782 }
783 break;
784
785 case V_028C70_COLOR_1_5_5_5:
786 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
787 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
788 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
789 }
790 break;
791
792 case V_028C70_COLOR_4_4_4_4:
793 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
794 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
795 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
796 }
797 break;
798
799 case V_028C70_COLOR_32:
800 if (swap == V_028C70_SWAP_STD &&
801 spi_format == V_028714_SPI_SHADER_32_R)
802 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
803 else if (swap == V_028C70_SWAP_ALT_REV &&
804 spi_format == V_028714_SPI_SHADER_32_AR)
805 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
806 break;
807
808 case V_028C70_COLOR_16:
809 case V_028C70_COLOR_16_16:
810 /* For 1-channel formats, use the superset thereof. */
811 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
812 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
813 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
814 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
815 if (swap == V_028C70_SWAP_STD ||
816 swap == V_028C70_SWAP_STD_REV)
817 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
818 else
819 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
820 }
821 break;
822
823 case V_028C70_COLOR_10_11_11:
824 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
825 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
826 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
827 }
828 break;
829
830 case V_028C70_COLOR_2_10_10_10:
831 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
832 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
833 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
834 }
835 break;
836 }
837 }
838
839 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
840 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
841 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
842 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
843 }
844
845 static void
846 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
847 {
848 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
849
850 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
851 return;
852
853 radv_update_multisample_state(cmd_buffer, pipeline);
854
855 cmd_buffer->scratch_size_needed =
856 MAX2(cmd_buffer->scratch_size_needed,
857 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
858
859 if (!cmd_buffer->state.emitted_pipeline ||
860 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
861 pipeline->graphics.can_use_guardband)
862 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
863
864 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
865
866 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
867 if (!pipeline->shaders[i])
868 continue;
869
870 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
871 pipeline->shaders[i]->bo);
872 }
873
874 if (radv_pipeline_has_gs(pipeline))
875 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
876 pipeline->gs_copy_shader->bo);
877
878 if (unlikely(cmd_buffer->device->trace_bo))
879 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
880
881 cmd_buffer->state.emitted_pipeline = pipeline;
882
883 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
884 }
885
886 static void
887 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
888 {
889 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
890 cmd_buffer->state.dynamic.viewport.viewports);
891 }
892
893 static void
894 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
895 {
896 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
897
898 si_write_scissors(cmd_buffer->cs, 0, count,
899 cmd_buffer->state.dynamic.scissor.scissors,
900 cmd_buffer->state.dynamic.viewport.viewports,
901 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
902 }
903
904 static void
905 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
906 {
907 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
908 return;
909
910 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
911 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
912 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
913 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
914 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
915 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
916 S_028214_BR_Y(rect.offset.y + rect.extent.height));
917 }
918 }
919
920 static void
921 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
922 {
923 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
924
925 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
926 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
927 }
928
929 static void
930 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
931 {
932 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
933
934 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
935 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
936 }
937
938 static void
939 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
940 {
941 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
942
943 radeon_set_context_reg_seq(cmd_buffer->cs,
944 R_028430_DB_STENCILREFMASK, 2);
945 radeon_emit(cmd_buffer->cs,
946 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
947 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
948 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
949 S_028430_STENCILOPVAL(1));
950 radeon_emit(cmd_buffer->cs,
951 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
952 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
953 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
954 S_028434_STENCILOPVAL_BF(1));
955 }
956
957 static void
958 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
959 {
960 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
961
962 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
963 fui(d->depth_bounds.min));
964 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
965 fui(d->depth_bounds.max));
966 }
967
968 static void
969 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
970 {
971 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
972 unsigned slope = fui(d->depth_bias.slope * 16.0f);
973 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
974
975
976 radeon_set_context_reg_seq(cmd_buffer->cs,
977 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
978 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
979 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
980 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
981 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
982 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
983 }
984
985 static void
986 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
987 int index,
988 struct radv_attachment_info *att,
989 struct radv_image *image,
990 VkImageLayout layout)
991 {
992 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
993 struct radv_color_buffer_info *cb = &att->cb;
994 uint32_t cb_color_info = cb->cb_color_info;
995
996 if (!radv_layout_dcc_compressed(image, layout,
997 radv_image_queue_family_mask(image,
998 cmd_buffer->queue_family_index,
999 cmd_buffer->queue_family_index))) {
1000 cb_color_info &= C_028C70_DCC_ENABLE;
1001 }
1002
1003 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1004 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1005 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1006 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1007 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1008 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1009 radeon_emit(cmd_buffer->cs, cb_color_info);
1010 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1011 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1012 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1013 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1014 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1015 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1016
1017 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1018 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1019 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1020
1021 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1022 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1023 } else {
1024 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1025 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1026 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1027 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1028 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1029 radeon_emit(cmd_buffer->cs, cb_color_info);
1030 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1031 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1032 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1033 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1034 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1035 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1036
1037 if (is_vi) { /* DCC BASE */
1038 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1039 }
1040 }
1041 }
1042
1043 static void
1044 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1045 struct radv_ds_buffer_info *ds,
1046 struct radv_image *image, VkImageLayout layout,
1047 bool requires_cond_write)
1048 {
1049 uint32_t db_z_info = ds->db_z_info;
1050 uint32_t db_z_info_reg;
1051
1052 if (!radv_image_is_tc_compat_htile(image))
1053 return;
1054
1055 if (!radv_layout_has_htile(image, layout,
1056 radv_image_queue_family_mask(image,
1057 cmd_buffer->queue_family_index,
1058 cmd_buffer->queue_family_index))) {
1059 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1060 }
1061
1062 db_z_info &= C_028040_ZRANGE_PRECISION;
1063
1064 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1065 db_z_info_reg = R_028038_DB_Z_INFO;
1066 } else {
1067 db_z_info_reg = R_028040_DB_Z_INFO;
1068 }
1069
1070 /* When we don't know the last fast clear value we need to emit a
1071 * conditional packet, otherwise we can update DB_Z_INFO directly.
1072 */
1073 if (requires_cond_write) {
1074 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1075
1076 const uint32_t write_space = 0 << 8; /* register */
1077 const uint32_t poll_space = 1 << 4; /* memory */
1078 const uint32_t function = 3 << 0; /* equal to the reference */
1079 const uint32_t options = write_space | poll_space | function;
1080 radeon_emit(cmd_buffer->cs, options);
1081
1082 /* poll address - location of the depth clear value */
1083 uint64_t va = radv_buffer_get_va(image->bo);
1084 va += image->offset + image->clear_value_offset;
1085
1086 /* In presence of stencil format, we have to adjust the base
1087 * address because the first value is the stencil clear value.
1088 */
1089 if (vk_format_is_stencil(image->vk_format))
1090 va += 4;
1091
1092 radeon_emit(cmd_buffer->cs, va);
1093 radeon_emit(cmd_buffer->cs, va >> 32);
1094
1095 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1096 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1097 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1098 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1099 radeon_emit(cmd_buffer->cs, db_z_info);
1100 } else {
1101 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1102 }
1103 }
1104
1105 static void
1106 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1107 struct radv_ds_buffer_info *ds,
1108 struct radv_image *image,
1109 VkImageLayout layout)
1110 {
1111 uint32_t db_z_info = ds->db_z_info;
1112 uint32_t db_stencil_info = ds->db_stencil_info;
1113
1114 if (!radv_layout_has_htile(image, layout,
1115 radv_image_queue_family_mask(image,
1116 cmd_buffer->queue_family_index,
1117 cmd_buffer->queue_family_index))) {
1118 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1119 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1120 }
1121
1122 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1123 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1124
1125
1126 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1127 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1128 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1129 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1130 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1131
1132 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1133 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1134 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1135 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1136 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1137 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1138 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1139 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1140 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1141 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1142 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1143
1144 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1145 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1146 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1147 } else {
1148 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1149
1150 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1151 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1152 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1153 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1154 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1155 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1156 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1157 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1158 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1159 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1160
1161 }
1162
1163 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1164 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1165
1166 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1167 ds->pa_su_poly_offset_db_fmt_cntl);
1168 }
1169
1170 /**
1171 * Update the fast clear depth/stencil values if the image is bound as a
1172 * depth/stencil buffer.
1173 */
1174 static void
1175 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1176 struct radv_image *image,
1177 VkClearDepthStencilValue ds_clear_value,
1178 VkImageAspectFlags aspects)
1179 {
1180 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1181 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1182 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1183 struct radv_attachment_info *att;
1184 uint32_t att_idx;
1185
1186 if (!framebuffer || !subpass)
1187 return;
1188
1189 att_idx = subpass->depth_stencil_attachment.attachment;
1190 if (att_idx == VK_ATTACHMENT_UNUSED)
1191 return;
1192
1193 att = &framebuffer->attachments[att_idx];
1194 if (att->attachment->image != image)
1195 return;
1196
1197 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1198 radeon_emit(cs, ds_clear_value.stencil);
1199 radeon_emit(cs, fui(ds_clear_value.depth));
1200
1201 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1202 * only needed when clearing Z to 0.0.
1203 */
1204 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1205 ds_clear_value.depth == 0.0) {
1206 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1207
1208 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1209 layout, false);
1210 }
1211 }
1212
1213 /**
1214 * Set the clear depth/stencil values to the image's metadata.
1215 */
1216 static void
1217 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1218 struct radv_image *image,
1219 VkClearDepthStencilValue ds_clear_value,
1220 VkImageAspectFlags aspects)
1221 {
1222 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1223 uint64_t va = radv_buffer_get_va(image->bo);
1224 unsigned reg_offset = 0, reg_count = 0;
1225
1226 va += image->offset + image->clear_value_offset;
1227
1228 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1229 ++reg_count;
1230 } else {
1231 ++reg_offset;
1232 va += 4;
1233 }
1234 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1235 ++reg_count;
1236
1237 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1238 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1239 S_370_WR_CONFIRM(1) |
1240 S_370_ENGINE_SEL(V_370_PFP));
1241 radeon_emit(cs, va);
1242 radeon_emit(cs, va >> 32);
1243 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1244 radeon_emit(cs, ds_clear_value.stencil);
1245 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1246 radeon_emit(cs, fui(ds_clear_value.depth));
1247 }
1248
1249 /**
1250 * Update the clear depth/stencil values for this image.
1251 */
1252 void
1253 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1254 struct radv_image *image,
1255 VkClearDepthStencilValue ds_clear_value,
1256 VkImageAspectFlags aspects)
1257 {
1258 assert(radv_image_has_htile(image));
1259
1260 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1261
1262 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1263 aspects);
1264 }
1265
1266 /**
1267 * Load the clear depth/stencil values from the image's metadata.
1268 */
1269 static void
1270 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1271 struct radv_image *image)
1272 {
1273 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1274 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1275 uint64_t va = radv_buffer_get_va(image->bo);
1276 unsigned reg_offset = 0, reg_count = 0;
1277
1278 va += image->offset + image->clear_value_offset;
1279
1280 if (!radv_image_has_htile(image))
1281 return;
1282
1283 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1284 ++reg_count;
1285 } else {
1286 ++reg_offset;
1287 va += 4;
1288 }
1289 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1290 ++reg_count;
1291
1292 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1293 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1294 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1295 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1296 radeon_emit(cs, va);
1297 radeon_emit(cs, va >> 32);
1298 radeon_emit(cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1299 radeon_emit(cs, 0);
1300
1301 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1302 radeon_emit(cs, 0);
1303 }
1304
1305 /*
1306 * With DCC some colors don't require CMASK elimination before being
1307 * used as a texture. This sets a predicate value to determine if the
1308 * cmask eliminate is required.
1309 */
1310 void
1311 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1312 struct radv_image *image,
1313 bool value)
1314 {
1315 uint64_t pred_val = value;
1316 uint64_t va = radv_buffer_get_va(image->bo);
1317 va += image->offset + image->dcc_pred_offset;
1318
1319 assert(radv_image_has_dcc(image));
1320
1321 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1322 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1323 S_370_WR_CONFIRM(1) |
1324 S_370_ENGINE_SEL(V_370_PFP));
1325 radeon_emit(cmd_buffer->cs, va);
1326 radeon_emit(cmd_buffer->cs, va >> 32);
1327 radeon_emit(cmd_buffer->cs, pred_val);
1328 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1329 }
1330
1331 /**
1332 * Update the fast clear color values if the image is bound as a color buffer.
1333 */
1334 static void
1335 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1336 struct radv_image *image,
1337 int cb_idx,
1338 uint32_t color_values[2])
1339 {
1340 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1341 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1342 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1343 struct radv_attachment_info *att;
1344 uint32_t att_idx;
1345
1346 if (!framebuffer || !subpass)
1347 return;
1348
1349 att_idx = subpass->color_attachments[cb_idx].attachment;
1350 if (att_idx == VK_ATTACHMENT_UNUSED)
1351 return;
1352
1353 att = &framebuffer->attachments[att_idx];
1354 if (att->attachment->image != image)
1355 return;
1356
1357 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1358 radeon_emit(cs, color_values[0]);
1359 radeon_emit(cs, color_values[1]);
1360 }
1361
1362 /**
1363 * Set the clear color values to the image's metadata.
1364 */
1365 static void
1366 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1367 struct radv_image *image,
1368 uint32_t color_values[2])
1369 {
1370 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1371 uint64_t va = radv_buffer_get_va(image->bo);
1372
1373 va += image->offset + image->clear_value_offset;
1374
1375 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1376
1377 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1378 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1379 S_370_WR_CONFIRM(1) |
1380 S_370_ENGINE_SEL(V_370_PFP));
1381 radeon_emit(cs, va);
1382 radeon_emit(cs, va >> 32);
1383 radeon_emit(cs, color_values[0]);
1384 radeon_emit(cs, color_values[1]);
1385 }
1386
1387 /**
1388 * Update the clear color values for this image.
1389 */
1390 void
1391 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1392 struct radv_image *image,
1393 int cb_idx,
1394 uint32_t color_values[2])
1395 {
1396 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1397
1398 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1399
1400 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1401 color_values);
1402 }
1403
1404 /**
1405 * Load the clear color values from the image's metadata.
1406 */
1407 static void
1408 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1409 struct radv_image *image,
1410 int cb_idx)
1411 {
1412 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1413 uint64_t va = radv_buffer_get_va(image->bo);
1414
1415 va += image->offset + image->clear_value_offset;
1416
1417 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1418 return;
1419
1420 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1421
1422 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1423 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1424 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1425 COPY_DATA_COUNT_SEL);
1426 radeon_emit(cs, va);
1427 radeon_emit(cs, va >> 32);
1428 radeon_emit(cs, reg >> 2);
1429 radeon_emit(cs, 0);
1430
1431 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1432 radeon_emit(cs, 0);
1433 }
1434
1435 static void
1436 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1437 {
1438 int i;
1439 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1440 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1441
1442 /* this may happen for inherited secondary recording */
1443 if (!framebuffer)
1444 return;
1445
1446 for (i = 0; i < 8; ++i) {
1447 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1448 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1449 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1450 continue;
1451 }
1452
1453 int idx = subpass->color_attachments[i].attachment;
1454 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1455 struct radv_image *image = att->attachment->image;
1456 VkImageLayout layout = subpass->color_attachments[i].layout;
1457
1458 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1459
1460 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1461 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1462
1463 radv_load_color_clear_metadata(cmd_buffer, image, i);
1464 }
1465
1466 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1467 int idx = subpass->depth_stencil_attachment.attachment;
1468 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1469 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1470 struct radv_image *image = att->attachment->image;
1471 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1472 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1473 cmd_buffer->queue_family_index,
1474 cmd_buffer->queue_family_index);
1475 /* We currently don't support writing decompressed HTILE */
1476 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1477 radv_layout_is_htile_compressed(image, layout, queue_mask));
1478
1479 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1480
1481 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1482 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1483 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1484 }
1485 radv_load_ds_clear_metadata(cmd_buffer, image);
1486 } else {
1487 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1488 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1489 else
1490 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1491
1492 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1493 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1494 }
1495 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1496 S_028208_BR_X(framebuffer->width) |
1497 S_028208_BR_Y(framebuffer->height));
1498
1499 if (cmd_buffer->device->dfsm_allowed) {
1500 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1501 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1502 }
1503
1504 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1505 }
1506
1507 static void
1508 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1509 {
1510 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1511 struct radv_cmd_state *state = &cmd_buffer->state;
1512
1513 if (state->index_type != state->last_index_type) {
1514 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1515 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1516 2, state->index_type);
1517 } else {
1518 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1519 radeon_emit(cs, state->index_type);
1520 }
1521
1522 state->last_index_type = state->index_type;
1523 }
1524
1525 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1526 radeon_emit(cs, state->index_va);
1527 radeon_emit(cs, state->index_va >> 32);
1528
1529 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1530 radeon_emit(cs, state->max_index_count);
1531
1532 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1533 }
1534
1535 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1536 {
1537 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1538 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1539 uint32_t pa_sc_mode_cntl_1 =
1540 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1541 uint32_t db_count_control;
1542
1543 if(!cmd_buffer->state.active_occlusion_queries) {
1544 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1545 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1546 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1547 has_perfect_queries) {
1548 /* Re-enable out-of-order rasterization if the
1549 * bound pipeline supports it and if it's has
1550 * been disabled before starting any perfect
1551 * occlusion queries.
1552 */
1553 radeon_set_context_reg(cmd_buffer->cs,
1554 R_028A4C_PA_SC_MODE_CNTL_1,
1555 pa_sc_mode_cntl_1);
1556 }
1557 db_count_control = 0;
1558 } else {
1559 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1560 }
1561 } else {
1562 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1563 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1564
1565 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1566 db_count_control =
1567 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1568 S_028004_SAMPLE_RATE(sample_rate) |
1569 S_028004_ZPASS_ENABLE(1) |
1570 S_028004_SLICE_EVEN_ENABLE(1) |
1571 S_028004_SLICE_ODD_ENABLE(1);
1572
1573 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1574 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1575 has_perfect_queries) {
1576 /* If the bound pipeline has enabled
1577 * out-of-order rasterization, we should
1578 * disable it before starting any perfect
1579 * occlusion queries.
1580 */
1581 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1582
1583 radeon_set_context_reg(cmd_buffer->cs,
1584 R_028A4C_PA_SC_MODE_CNTL_1,
1585 pa_sc_mode_cntl_1);
1586 }
1587 } else {
1588 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1589 S_028004_SAMPLE_RATE(sample_rate);
1590 }
1591 }
1592
1593 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1594 }
1595
1596 static void
1597 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1598 {
1599 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1600
1601 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1602 radv_emit_viewport(cmd_buffer);
1603
1604 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1605 !cmd_buffer->device->physical_device->has_scissor_bug)
1606 radv_emit_scissor(cmd_buffer);
1607
1608 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1609 radv_emit_line_width(cmd_buffer);
1610
1611 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1612 radv_emit_blend_constants(cmd_buffer);
1613
1614 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1615 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1616 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1617 radv_emit_stencil(cmd_buffer);
1618
1619 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1620 radv_emit_depth_bounds(cmd_buffer);
1621
1622 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1623 radv_emit_depth_bias(cmd_buffer);
1624
1625 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1626 radv_emit_discard_rectangle(cmd_buffer);
1627
1628 cmd_buffer->state.dirty &= ~states;
1629 }
1630
1631 static void
1632 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1633 VkPipelineBindPoint bind_point)
1634 {
1635 struct radv_descriptor_state *descriptors_state =
1636 radv_get_descriptors_state(cmd_buffer, bind_point);
1637 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1638 unsigned bo_offset;
1639
1640 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1641 set->mapped_ptr,
1642 &bo_offset))
1643 return;
1644
1645 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1646 set->va += bo_offset;
1647 }
1648
1649 static void
1650 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1651 VkPipelineBindPoint bind_point)
1652 {
1653 struct radv_descriptor_state *descriptors_state =
1654 radv_get_descriptors_state(cmd_buffer, bind_point);
1655 uint32_t size = MAX_SETS * 2 * 4;
1656 uint32_t offset;
1657 void *ptr;
1658
1659 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1660 256, &offset, &ptr))
1661 return;
1662
1663 for (unsigned i = 0; i < MAX_SETS; i++) {
1664 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1665 uint64_t set_va = 0;
1666 struct radv_descriptor_set *set = descriptors_state->sets[i];
1667 if (descriptors_state->valid & (1u << i))
1668 set_va = set->va;
1669 uptr[0] = set_va & 0xffffffff;
1670 uptr[1] = set_va >> 32;
1671 }
1672
1673 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1674 va += offset;
1675
1676 if (cmd_buffer->state.pipeline) {
1677 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1678 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1679 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1680
1681 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1682 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1683 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1684
1685 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1686 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1687 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1688
1689 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1690 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1691 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1692
1693 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1694 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1695 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1696 }
1697
1698 if (cmd_buffer->state.compute_pipeline)
1699 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1700 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1701 }
1702
1703 static void
1704 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1705 VkShaderStageFlags stages)
1706 {
1707 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1708 VK_PIPELINE_BIND_POINT_COMPUTE :
1709 VK_PIPELINE_BIND_POINT_GRAPHICS;
1710 struct radv_descriptor_state *descriptors_state =
1711 radv_get_descriptors_state(cmd_buffer, bind_point);
1712
1713 if (!descriptors_state->dirty)
1714 return;
1715
1716 if (descriptors_state->push_dirty)
1717 radv_flush_push_descriptors(cmd_buffer, bind_point);
1718
1719 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1720 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1721 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1722 }
1723
1724 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1725 cmd_buffer->cs,
1726 MAX_SETS * MESA_SHADER_STAGES * 4);
1727
1728 if (cmd_buffer->state.pipeline) {
1729 radv_foreach_stage(stage, stages) {
1730 if (!cmd_buffer->state.pipeline->shaders[stage])
1731 continue;
1732
1733 radv_emit_descriptor_pointers(cmd_buffer,
1734 cmd_buffer->state.pipeline,
1735 descriptors_state, stage);
1736 }
1737 }
1738
1739 if (cmd_buffer->state.compute_pipeline &&
1740 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1741 radv_emit_descriptor_pointers(cmd_buffer,
1742 cmd_buffer->state.compute_pipeline,
1743 descriptors_state,
1744 MESA_SHADER_COMPUTE);
1745 }
1746
1747 descriptors_state->dirty = 0;
1748 descriptors_state->push_dirty = false;
1749
1750 if (unlikely(cmd_buffer->device->trace_bo))
1751 radv_save_descriptors(cmd_buffer, bind_point);
1752
1753 assert(cmd_buffer->cs->cdw <= cdw_max);
1754 }
1755
1756 static void
1757 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1758 VkShaderStageFlags stages)
1759 {
1760 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1761 ? cmd_buffer->state.compute_pipeline
1762 : cmd_buffer->state.pipeline;
1763 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1764 VK_PIPELINE_BIND_POINT_COMPUTE :
1765 VK_PIPELINE_BIND_POINT_GRAPHICS;
1766 struct radv_descriptor_state *descriptors_state =
1767 radv_get_descriptors_state(cmd_buffer, bind_point);
1768 struct radv_pipeline_layout *layout = pipeline->layout;
1769 struct radv_shader_variant *shader, *prev_shader;
1770 unsigned offset;
1771 void *ptr;
1772 uint64_t va;
1773
1774 stages &= cmd_buffer->push_constant_stages;
1775 if (!stages ||
1776 (!layout->push_constant_size && !layout->dynamic_offset_count))
1777 return;
1778
1779 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1780 16 * layout->dynamic_offset_count,
1781 256, &offset, &ptr))
1782 return;
1783
1784 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1785 memcpy((char*)ptr + layout->push_constant_size,
1786 descriptors_state->dynamic_buffers,
1787 16 * layout->dynamic_offset_count);
1788
1789 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1790 va += offset;
1791
1792 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1793 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1794
1795 prev_shader = NULL;
1796 radv_foreach_stage(stage, stages) {
1797 shader = radv_get_shader(pipeline, stage);
1798
1799 /* Avoid redundantly emitting the address for merged stages. */
1800 if (shader && shader != prev_shader) {
1801 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1802 AC_UD_PUSH_CONSTANTS, va);
1803
1804 prev_shader = shader;
1805 }
1806 }
1807
1808 cmd_buffer->push_constant_stages &= ~stages;
1809 assert(cmd_buffer->cs->cdw <= cdw_max);
1810 }
1811
1812 static void
1813 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1814 bool pipeline_is_dirty)
1815 {
1816 if ((pipeline_is_dirty ||
1817 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1818 cmd_buffer->state.pipeline->vertex_elements.count &&
1819 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1820 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1821 unsigned vb_offset;
1822 void *vb_ptr;
1823 uint32_t i = 0;
1824 uint32_t count = velems->count;
1825 uint64_t va;
1826
1827 /* allocate some descriptor state for vertex buffers */
1828 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1829 &vb_offset, &vb_ptr))
1830 return;
1831
1832 for (i = 0; i < count; i++) {
1833 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1834 uint32_t offset;
1835 int vb = velems->binding[i];
1836 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1837 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1838
1839 va = radv_buffer_get_va(buffer->bo);
1840
1841 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1842 va += offset + buffer->offset;
1843 desc[0] = va;
1844 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1845 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1846 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1847 else
1848 desc[2] = buffer->size - offset;
1849 desc[3] = velems->rsrc_word3[i];
1850 }
1851
1852 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1853 va += vb_offset;
1854
1855 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1856 AC_UD_VS_VERTEX_BUFFERS, va);
1857
1858 cmd_buffer->state.vb_va = va;
1859 cmd_buffer->state.vb_size = count * 16;
1860 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1861 }
1862 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1863 }
1864
1865 static void
1866 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1867 {
1868 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1869 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1870 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1871 }
1872
1873 static void
1874 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1875 bool instanced_draw, bool indirect_draw,
1876 uint32_t draw_vertex_count)
1877 {
1878 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1879 struct radv_cmd_state *state = &cmd_buffer->state;
1880 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1881 uint32_t ia_multi_vgt_param;
1882 int32_t primitive_reset_en;
1883
1884 /* Draw state. */
1885 ia_multi_vgt_param =
1886 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1887 indirect_draw, draw_vertex_count);
1888
1889 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1890 if (info->chip_class >= GFX9) {
1891 radeon_set_uconfig_reg_idx(cs,
1892 R_030960_IA_MULTI_VGT_PARAM,
1893 4, ia_multi_vgt_param);
1894 } else if (info->chip_class >= CIK) {
1895 radeon_set_context_reg_idx(cs,
1896 R_028AA8_IA_MULTI_VGT_PARAM,
1897 1, ia_multi_vgt_param);
1898 } else {
1899 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1900 ia_multi_vgt_param);
1901 }
1902 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1903 }
1904
1905 /* Primitive restart. */
1906 primitive_reset_en =
1907 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1908
1909 if (primitive_reset_en != state->last_primitive_reset_en) {
1910 state->last_primitive_reset_en = primitive_reset_en;
1911 if (info->chip_class >= GFX9) {
1912 radeon_set_uconfig_reg(cs,
1913 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1914 primitive_reset_en);
1915 } else {
1916 radeon_set_context_reg(cs,
1917 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1918 primitive_reset_en);
1919 }
1920 }
1921
1922 if (primitive_reset_en) {
1923 uint32_t primitive_reset_index =
1924 state->index_type ? 0xffffffffu : 0xffffu;
1925
1926 if (primitive_reset_index != state->last_primitive_reset_index) {
1927 radeon_set_context_reg(cs,
1928 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1929 primitive_reset_index);
1930 state->last_primitive_reset_index = primitive_reset_index;
1931 }
1932 }
1933 }
1934
1935 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1936 VkPipelineStageFlags src_stage_mask)
1937 {
1938 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1939 VK_PIPELINE_STAGE_TRANSFER_BIT |
1940 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1941 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1942 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1943 }
1944
1945 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1946 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1947 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1948 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1949 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1950 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1951 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1952 VK_PIPELINE_STAGE_TRANSFER_BIT |
1953 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1954 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1955 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1956 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1957 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1958 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1959 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1960 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1961 }
1962 }
1963
1964 static enum radv_cmd_flush_bits
1965 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1966 VkAccessFlags src_flags,
1967 struct radv_image *image)
1968 {
1969 enum radv_cmd_flush_bits flush_bits = 0;
1970 uint32_t b;
1971 for_each_bit(b, src_flags) {
1972 switch ((VkAccessFlagBits)(1 << b)) {
1973 case VK_ACCESS_SHADER_WRITE_BIT:
1974 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1975 break;
1976 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1977 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
1978 if (!image || (image && radv_image_has_CB_metadata(image))) {
1979 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1980 }
1981 break;
1982 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1983 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
1984 if (!image || (image && radv_image_has_htile(image))) {
1985 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1986 }
1987 break;
1988 case VK_ACCESS_TRANSFER_WRITE_BIT:
1989 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1990 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1991 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1992 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1993 RADV_CMD_FLAG_INV_GLOBAL_L2;
1994 break;
1995 default:
1996 break;
1997 }
1998 }
1999 return flush_bits;
2000 }
2001
2002 static enum radv_cmd_flush_bits
2003 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2004 VkAccessFlags dst_flags,
2005 struct radv_image *image)
2006 {
2007 enum radv_cmd_flush_bits flush_bits = 0;
2008 uint32_t b;
2009 for_each_bit(b, dst_flags) {
2010 switch ((VkAccessFlagBits)(1 << b)) {
2011 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2012 case VK_ACCESS_INDEX_READ_BIT:
2013 break;
2014 case VK_ACCESS_UNIFORM_READ_BIT:
2015 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2016 break;
2017 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2018 case VK_ACCESS_SHADER_READ_BIT:
2019 case VK_ACCESS_TRANSFER_READ_BIT:
2020 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2021 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2022 RADV_CMD_FLAG_INV_GLOBAL_L2;
2023 break;
2024 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2025 /* TODO: change to image && when the image gets passed
2026 * through from the subpass. */
2027 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2028 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2029 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2030 break;
2031 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2032 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2033 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2034 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2035 break;
2036 default:
2037 break;
2038 }
2039 }
2040 return flush_bits;
2041 }
2042
2043 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2044 {
2045 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2046 NULL);
2047 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2048 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2049 NULL);
2050 }
2051
2052 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2053 struct radv_subpass_attachment att)
2054 {
2055 unsigned idx = att.attachment;
2056 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2057 VkImageSubresourceRange range;
2058 range.aspectMask = 0;
2059 range.baseMipLevel = view->base_mip;
2060 range.levelCount = 1;
2061 range.baseArrayLayer = view->base_layer;
2062 range.layerCount = cmd_buffer->state.framebuffer->layers;
2063
2064 radv_handle_image_transition(cmd_buffer,
2065 view->image,
2066 cmd_buffer->state.attachments[idx].current_layout,
2067 att.layout, 0, 0, &range,
2068 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2069
2070 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2071
2072
2073 }
2074
2075 void
2076 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2077 const struct radv_subpass *subpass, bool transitions)
2078 {
2079 if (transitions) {
2080 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2081
2082 for (unsigned i = 0; i < subpass->color_count; ++i) {
2083 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2084 radv_handle_subpass_image_transition(cmd_buffer,
2085 subpass->color_attachments[i]);
2086 }
2087
2088 for (unsigned i = 0; i < subpass->input_count; ++i) {
2089 radv_handle_subpass_image_transition(cmd_buffer,
2090 subpass->input_attachments[i]);
2091 }
2092
2093 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2094 radv_handle_subpass_image_transition(cmd_buffer,
2095 subpass->depth_stencil_attachment);
2096 }
2097 }
2098
2099 cmd_buffer->state.subpass = subpass;
2100
2101 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2102 }
2103
2104 static VkResult
2105 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2106 struct radv_render_pass *pass,
2107 const VkRenderPassBeginInfo *info)
2108 {
2109 struct radv_cmd_state *state = &cmd_buffer->state;
2110
2111 if (pass->attachment_count == 0) {
2112 state->attachments = NULL;
2113 return VK_SUCCESS;
2114 }
2115
2116 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2117 pass->attachment_count *
2118 sizeof(state->attachments[0]),
2119 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2120 if (state->attachments == NULL) {
2121 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2122 return cmd_buffer->record_result;
2123 }
2124
2125 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2126 struct radv_render_pass_attachment *att = &pass->attachments[i];
2127 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2128 VkImageAspectFlags clear_aspects = 0;
2129
2130 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2131 /* color attachment */
2132 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2133 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2134 }
2135 } else {
2136 /* depthstencil attachment */
2137 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2138 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2139 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2140 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2141 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2142 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2143 }
2144 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2145 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2146 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2147 }
2148 }
2149
2150 state->attachments[i].pending_clear_aspects = clear_aspects;
2151 state->attachments[i].cleared_views = 0;
2152 if (clear_aspects && info) {
2153 assert(info->clearValueCount > i);
2154 state->attachments[i].clear_value = info->pClearValues[i];
2155 }
2156
2157 state->attachments[i].current_layout = att->initial_layout;
2158 }
2159
2160 return VK_SUCCESS;
2161 }
2162
2163 VkResult radv_AllocateCommandBuffers(
2164 VkDevice _device,
2165 const VkCommandBufferAllocateInfo *pAllocateInfo,
2166 VkCommandBuffer *pCommandBuffers)
2167 {
2168 RADV_FROM_HANDLE(radv_device, device, _device);
2169 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2170
2171 VkResult result = VK_SUCCESS;
2172 uint32_t i;
2173
2174 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2175
2176 if (!list_empty(&pool->free_cmd_buffers)) {
2177 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2178
2179 list_del(&cmd_buffer->pool_link);
2180 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2181
2182 result = radv_reset_cmd_buffer(cmd_buffer);
2183 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2184 cmd_buffer->level = pAllocateInfo->level;
2185
2186 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2187 } else {
2188 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2189 &pCommandBuffers[i]);
2190 }
2191 if (result != VK_SUCCESS)
2192 break;
2193 }
2194
2195 if (result != VK_SUCCESS) {
2196 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2197 i, pCommandBuffers);
2198
2199 /* From the Vulkan 1.0.66 spec:
2200 *
2201 * "vkAllocateCommandBuffers can be used to create multiple
2202 * command buffers. If the creation of any of those command
2203 * buffers fails, the implementation must destroy all
2204 * successfully created command buffer objects from this
2205 * command, set all entries of the pCommandBuffers array to
2206 * NULL and return the error."
2207 */
2208 memset(pCommandBuffers, 0,
2209 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2210 }
2211
2212 return result;
2213 }
2214
2215 void radv_FreeCommandBuffers(
2216 VkDevice device,
2217 VkCommandPool commandPool,
2218 uint32_t commandBufferCount,
2219 const VkCommandBuffer *pCommandBuffers)
2220 {
2221 for (uint32_t i = 0; i < commandBufferCount; i++) {
2222 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2223
2224 if (cmd_buffer) {
2225 if (cmd_buffer->pool) {
2226 list_del(&cmd_buffer->pool_link);
2227 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2228 } else
2229 radv_cmd_buffer_destroy(cmd_buffer);
2230
2231 }
2232 }
2233 }
2234
2235 VkResult radv_ResetCommandBuffer(
2236 VkCommandBuffer commandBuffer,
2237 VkCommandBufferResetFlags flags)
2238 {
2239 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2240 return radv_reset_cmd_buffer(cmd_buffer);
2241 }
2242
2243 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2244 {
2245 struct radv_device *device = cmd_buffer->device;
2246 if (device->gfx_init) {
2247 uint64_t va = radv_buffer_get_va(device->gfx_init);
2248 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init);
2249 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2250 radeon_emit(cmd_buffer->cs, va);
2251 radeon_emit(cmd_buffer->cs, va >> 32);
2252 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2253 } else
2254 si_init_config(cmd_buffer);
2255 }
2256
2257 VkResult radv_BeginCommandBuffer(
2258 VkCommandBuffer commandBuffer,
2259 const VkCommandBufferBeginInfo *pBeginInfo)
2260 {
2261 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2262 VkResult result = VK_SUCCESS;
2263
2264 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2265 /* If the command buffer has already been resetted with
2266 * vkResetCommandBuffer, no need to do it again.
2267 */
2268 result = radv_reset_cmd_buffer(cmd_buffer);
2269 if (result != VK_SUCCESS)
2270 return result;
2271 }
2272
2273 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2274 cmd_buffer->state.last_primitive_reset_en = -1;
2275 cmd_buffer->state.last_index_type = -1;
2276 cmd_buffer->state.last_num_instances = -1;
2277 cmd_buffer->state.last_vertex_offset = -1;
2278 cmd_buffer->state.last_first_instance = -1;
2279 cmd_buffer->usage_flags = pBeginInfo->flags;
2280
2281 /* setup initial configuration into command buffer */
2282 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2283 switch (cmd_buffer->queue_family_index) {
2284 case RADV_QUEUE_GENERAL:
2285 emit_gfx_buffer_state(cmd_buffer);
2286 break;
2287 case RADV_QUEUE_COMPUTE:
2288 si_init_compute(cmd_buffer);
2289 break;
2290 case RADV_QUEUE_TRANSFER:
2291 default:
2292 break;
2293 }
2294 }
2295
2296 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2297 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2298 assert(pBeginInfo->pInheritanceInfo);
2299 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2300 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2301
2302 struct radv_subpass *subpass =
2303 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2304
2305 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2306 if (result != VK_SUCCESS)
2307 return result;
2308
2309 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2310 }
2311
2312 if (unlikely(cmd_buffer->device->trace_bo)) {
2313 struct radv_device *device = cmd_buffer->device;
2314
2315 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2316 device->trace_bo);
2317
2318 radv_cmd_buffer_trace_emit(cmd_buffer);
2319 }
2320
2321 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2322
2323 return result;
2324 }
2325
2326 void radv_CmdBindVertexBuffers(
2327 VkCommandBuffer commandBuffer,
2328 uint32_t firstBinding,
2329 uint32_t bindingCount,
2330 const VkBuffer* pBuffers,
2331 const VkDeviceSize* pOffsets)
2332 {
2333 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2334 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2335 bool changed = false;
2336
2337 /* We have to defer setting up vertex buffer since we need the buffer
2338 * stride from the pipeline. */
2339
2340 assert(firstBinding + bindingCount <= MAX_VBS);
2341 for (uint32_t i = 0; i < bindingCount; i++) {
2342 uint32_t idx = firstBinding + i;
2343
2344 if (!changed &&
2345 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2346 vb[idx].offset != pOffsets[i])) {
2347 changed = true;
2348 }
2349
2350 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2351 vb[idx].offset = pOffsets[i];
2352
2353 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2354 vb[idx].buffer->bo);
2355 }
2356
2357 if (!changed) {
2358 /* No state changes. */
2359 return;
2360 }
2361
2362 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2363 }
2364
2365 void radv_CmdBindIndexBuffer(
2366 VkCommandBuffer commandBuffer,
2367 VkBuffer buffer,
2368 VkDeviceSize offset,
2369 VkIndexType indexType)
2370 {
2371 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2372 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2373
2374 if (cmd_buffer->state.index_buffer == index_buffer &&
2375 cmd_buffer->state.index_offset == offset &&
2376 cmd_buffer->state.index_type == indexType) {
2377 /* No state changes. */
2378 return;
2379 }
2380
2381 cmd_buffer->state.index_buffer = index_buffer;
2382 cmd_buffer->state.index_offset = offset;
2383 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2384 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2385 cmd_buffer->state.index_va += index_buffer->offset + offset;
2386
2387 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2388 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2389 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2390 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2391 }
2392
2393
2394 static void
2395 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2396 VkPipelineBindPoint bind_point,
2397 struct radv_descriptor_set *set, unsigned idx)
2398 {
2399 struct radeon_winsys *ws = cmd_buffer->device->ws;
2400
2401 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2402
2403 assert(set);
2404 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2405
2406 if (!cmd_buffer->device->use_global_bo_list) {
2407 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2408 if (set->descriptors[j])
2409 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2410 }
2411
2412 if(set->bo)
2413 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2414 }
2415
2416 void radv_CmdBindDescriptorSets(
2417 VkCommandBuffer commandBuffer,
2418 VkPipelineBindPoint pipelineBindPoint,
2419 VkPipelineLayout _layout,
2420 uint32_t firstSet,
2421 uint32_t descriptorSetCount,
2422 const VkDescriptorSet* pDescriptorSets,
2423 uint32_t dynamicOffsetCount,
2424 const uint32_t* pDynamicOffsets)
2425 {
2426 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2427 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2428 unsigned dyn_idx = 0;
2429
2430 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2431 struct radv_descriptor_state *descriptors_state =
2432 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2433
2434 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2435 unsigned idx = i + firstSet;
2436 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2437 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2438
2439 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2440 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2441 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2442 assert(dyn_idx < dynamicOffsetCount);
2443
2444 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2445 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2446 dst[0] = va;
2447 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2448 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2449 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2450 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2451 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2452 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2453 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2454 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2455 cmd_buffer->push_constant_stages |=
2456 set->layout->dynamic_shader_stages;
2457 }
2458 }
2459 }
2460
2461 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2462 struct radv_descriptor_set *set,
2463 struct radv_descriptor_set_layout *layout,
2464 VkPipelineBindPoint bind_point)
2465 {
2466 struct radv_descriptor_state *descriptors_state =
2467 radv_get_descriptors_state(cmd_buffer, bind_point);
2468 set->size = layout->size;
2469 set->layout = layout;
2470
2471 if (descriptors_state->push_set.capacity < set->size) {
2472 size_t new_size = MAX2(set->size, 1024);
2473 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2474 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2475
2476 free(set->mapped_ptr);
2477 set->mapped_ptr = malloc(new_size);
2478
2479 if (!set->mapped_ptr) {
2480 descriptors_state->push_set.capacity = 0;
2481 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2482 return false;
2483 }
2484
2485 descriptors_state->push_set.capacity = new_size;
2486 }
2487
2488 return true;
2489 }
2490
2491 void radv_meta_push_descriptor_set(
2492 struct radv_cmd_buffer* cmd_buffer,
2493 VkPipelineBindPoint pipelineBindPoint,
2494 VkPipelineLayout _layout,
2495 uint32_t set,
2496 uint32_t descriptorWriteCount,
2497 const VkWriteDescriptorSet* pDescriptorWrites)
2498 {
2499 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2500 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2501 unsigned bo_offset;
2502
2503 assert(set == 0);
2504 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2505
2506 push_set->size = layout->set[set].layout->size;
2507 push_set->layout = layout->set[set].layout;
2508
2509 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2510 &bo_offset,
2511 (void**) &push_set->mapped_ptr))
2512 return;
2513
2514 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2515 push_set->va += bo_offset;
2516
2517 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2518 radv_descriptor_set_to_handle(push_set),
2519 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2520
2521 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2522 }
2523
2524 void radv_CmdPushDescriptorSetKHR(
2525 VkCommandBuffer commandBuffer,
2526 VkPipelineBindPoint pipelineBindPoint,
2527 VkPipelineLayout _layout,
2528 uint32_t set,
2529 uint32_t descriptorWriteCount,
2530 const VkWriteDescriptorSet* pDescriptorWrites)
2531 {
2532 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2533 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2534 struct radv_descriptor_state *descriptors_state =
2535 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2536 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2537
2538 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2539
2540 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2541 layout->set[set].layout,
2542 pipelineBindPoint))
2543 return;
2544
2545 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2546 radv_descriptor_set_to_handle(push_set),
2547 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2548
2549 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2550 descriptors_state->push_dirty = true;
2551 }
2552
2553 void radv_CmdPushDescriptorSetWithTemplateKHR(
2554 VkCommandBuffer commandBuffer,
2555 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2556 VkPipelineLayout _layout,
2557 uint32_t set,
2558 const void* pData)
2559 {
2560 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2561 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2562 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2563 struct radv_descriptor_state *descriptors_state =
2564 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2565 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2566
2567 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2568
2569 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2570 layout->set[set].layout,
2571 templ->bind_point))
2572 return;
2573
2574 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2575 descriptorUpdateTemplate, pData);
2576
2577 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2578 descriptors_state->push_dirty = true;
2579 }
2580
2581 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2582 VkPipelineLayout layout,
2583 VkShaderStageFlags stageFlags,
2584 uint32_t offset,
2585 uint32_t size,
2586 const void* pValues)
2587 {
2588 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2589 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2590 cmd_buffer->push_constant_stages |= stageFlags;
2591 }
2592
2593 VkResult radv_EndCommandBuffer(
2594 VkCommandBuffer commandBuffer)
2595 {
2596 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2597
2598 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2599 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2600 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2601 si_emit_cache_flush(cmd_buffer);
2602 }
2603
2604 /* Make sure CP DMA is idle at the end of IBs because the kernel
2605 * doesn't wait for it.
2606 */
2607 si_cp_dma_wait_for_idle(cmd_buffer);
2608
2609 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2610
2611 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2612 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2613
2614 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2615
2616 return cmd_buffer->record_result;
2617 }
2618
2619 static void
2620 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2621 {
2622 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2623
2624 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2625 return;
2626
2627 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2628
2629 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2630 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2631
2632 cmd_buffer->compute_scratch_size_needed =
2633 MAX2(cmd_buffer->compute_scratch_size_needed,
2634 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2635
2636 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2637 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2638
2639 if (unlikely(cmd_buffer->device->trace_bo))
2640 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2641 }
2642
2643 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2644 VkPipelineBindPoint bind_point)
2645 {
2646 struct radv_descriptor_state *descriptors_state =
2647 radv_get_descriptors_state(cmd_buffer, bind_point);
2648
2649 descriptors_state->dirty |= descriptors_state->valid;
2650 }
2651
2652 void radv_CmdBindPipeline(
2653 VkCommandBuffer commandBuffer,
2654 VkPipelineBindPoint pipelineBindPoint,
2655 VkPipeline _pipeline)
2656 {
2657 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2658 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2659
2660 switch (pipelineBindPoint) {
2661 case VK_PIPELINE_BIND_POINT_COMPUTE:
2662 if (cmd_buffer->state.compute_pipeline == pipeline)
2663 return;
2664 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2665
2666 cmd_buffer->state.compute_pipeline = pipeline;
2667 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2668 break;
2669 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2670 if (cmd_buffer->state.pipeline == pipeline)
2671 return;
2672 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2673
2674 cmd_buffer->state.pipeline = pipeline;
2675 if (!pipeline)
2676 break;
2677
2678 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2679 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2680
2681 /* the new vertex shader might not have the same user regs */
2682 cmd_buffer->state.last_first_instance = -1;
2683 cmd_buffer->state.last_vertex_offset = -1;
2684
2685 /* Prefetch all pipeline shaders at first draw time. */
2686 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2687
2688 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2689
2690 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2691 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2692 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2693 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2694
2695 if (radv_pipeline_has_tess(pipeline))
2696 cmd_buffer->tess_rings_needed = true;
2697 break;
2698 default:
2699 assert(!"invalid bind point");
2700 break;
2701 }
2702 }
2703
2704 void radv_CmdSetViewport(
2705 VkCommandBuffer commandBuffer,
2706 uint32_t firstViewport,
2707 uint32_t viewportCount,
2708 const VkViewport* pViewports)
2709 {
2710 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2711 struct radv_cmd_state *state = &cmd_buffer->state;
2712 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2713
2714 assert(firstViewport < MAX_VIEWPORTS);
2715 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2716
2717 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2718 viewportCount * sizeof(*pViewports));
2719
2720 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2721 }
2722
2723 void radv_CmdSetScissor(
2724 VkCommandBuffer commandBuffer,
2725 uint32_t firstScissor,
2726 uint32_t scissorCount,
2727 const VkRect2D* pScissors)
2728 {
2729 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2730 struct radv_cmd_state *state = &cmd_buffer->state;
2731 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2732
2733 assert(firstScissor < MAX_SCISSORS);
2734 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2735
2736 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2737 scissorCount * sizeof(*pScissors));
2738
2739 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2740 }
2741
2742 void radv_CmdSetLineWidth(
2743 VkCommandBuffer commandBuffer,
2744 float lineWidth)
2745 {
2746 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2747 cmd_buffer->state.dynamic.line_width = lineWidth;
2748 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2749 }
2750
2751 void radv_CmdSetDepthBias(
2752 VkCommandBuffer commandBuffer,
2753 float depthBiasConstantFactor,
2754 float depthBiasClamp,
2755 float depthBiasSlopeFactor)
2756 {
2757 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2758
2759 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2760 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2761 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2762
2763 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2764 }
2765
2766 void radv_CmdSetBlendConstants(
2767 VkCommandBuffer commandBuffer,
2768 const float blendConstants[4])
2769 {
2770 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2771
2772 memcpy(cmd_buffer->state.dynamic.blend_constants,
2773 blendConstants, sizeof(float) * 4);
2774
2775 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2776 }
2777
2778 void radv_CmdSetDepthBounds(
2779 VkCommandBuffer commandBuffer,
2780 float minDepthBounds,
2781 float maxDepthBounds)
2782 {
2783 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2784
2785 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2786 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2787
2788 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2789 }
2790
2791 void radv_CmdSetStencilCompareMask(
2792 VkCommandBuffer commandBuffer,
2793 VkStencilFaceFlags faceMask,
2794 uint32_t compareMask)
2795 {
2796 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2797
2798 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2799 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2800 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2801 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2802
2803 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2804 }
2805
2806 void radv_CmdSetStencilWriteMask(
2807 VkCommandBuffer commandBuffer,
2808 VkStencilFaceFlags faceMask,
2809 uint32_t writeMask)
2810 {
2811 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2812
2813 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2814 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2815 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2816 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2817
2818 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2819 }
2820
2821 void radv_CmdSetStencilReference(
2822 VkCommandBuffer commandBuffer,
2823 VkStencilFaceFlags faceMask,
2824 uint32_t reference)
2825 {
2826 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2827
2828 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2829 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2830 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2831 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2832
2833 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2834 }
2835
2836 void radv_CmdSetDiscardRectangleEXT(
2837 VkCommandBuffer commandBuffer,
2838 uint32_t firstDiscardRectangle,
2839 uint32_t discardRectangleCount,
2840 const VkRect2D* pDiscardRectangles)
2841 {
2842 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2843 struct radv_cmd_state *state = &cmd_buffer->state;
2844 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2845
2846 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2847 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2848
2849 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2850 pDiscardRectangles, discardRectangleCount);
2851
2852 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2853 }
2854
2855 void radv_CmdExecuteCommands(
2856 VkCommandBuffer commandBuffer,
2857 uint32_t commandBufferCount,
2858 const VkCommandBuffer* pCmdBuffers)
2859 {
2860 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2861
2862 assert(commandBufferCount > 0);
2863
2864 /* Emit pending flushes on primary prior to executing secondary */
2865 si_emit_cache_flush(primary);
2866
2867 for (uint32_t i = 0; i < commandBufferCount; i++) {
2868 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2869
2870 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2871 secondary->scratch_size_needed);
2872 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2873 secondary->compute_scratch_size_needed);
2874
2875 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2876 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2877 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2878 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2879 if (secondary->tess_rings_needed)
2880 primary->tess_rings_needed = true;
2881 if (secondary->sample_positions_needed)
2882 primary->sample_positions_needed = true;
2883
2884 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2885
2886
2887 /* When the secondary command buffer is compute only we don't
2888 * need to re-emit the current graphics pipeline.
2889 */
2890 if (secondary->state.emitted_pipeline) {
2891 primary->state.emitted_pipeline =
2892 secondary->state.emitted_pipeline;
2893 }
2894
2895 /* When the secondary command buffer is graphics only we don't
2896 * need to re-emit the current compute pipeline.
2897 */
2898 if (secondary->state.emitted_compute_pipeline) {
2899 primary->state.emitted_compute_pipeline =
2900 secondary->state.emitted_compute_pipeline;
2901 }
2902
2903 /* Only re-emit the draw packets when needed. */
2904 if (secondary->state.last_primitive_reset_en != -1) {
2905 primary->state.last_primitive_reset_en =
2906 secondary->state.last_primitive_reset_en;
2907 }
2908
2909 if (secondary->state.last_primitive_reset_index) {
2910 primary->state.last_primitive_reset_index =
2911 secondary->state.last_primitive_reset_index;
2912 }
2913
2914 if (secondary->state.last_ia_multi_vgt_param) {
2915 primary->state.last_ia_multi_vgt_param =
2916 secondary->state.last_ia_multi_vgt_param;
2917 }
2918
2919 primary->state.last_first_instance = secondary->state.last_first_instance;
2920 primary->state.last_num_instances = secondary->state.last_num_instances;
2921 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2922
2923 if (secondary->state.last_index_type != -1) {
2924 primary->state.last_index_type =
2925 secondary->state.last_index_type;
2926 }
2927 }
2928
2929 /* After executing commands from secondary buffers we have to dirty
2930 * some states.
2931 */
2932 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2933 RADV_CMD_DIRTY_INDEX_BUFFER |
2934 RADV_CMD_DIRTY_DYNAMIC_ALL;
2935 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2936 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2937 }
2938
2939 VkResult radv_CreateCommandPool(
2940 VkDevice _device,
2941 const VkCommandPoolCreateInfo* pCreateInfo,
2942 const VkAllocationCallbacks* pAllocator,
2943 VkCommandPool* pCmdPool)
2944 {
2945 RADV_FROM_HANDLE(radv_device, device, _device);
2946 struct radv_cmd_pool *pool;
2947
2948 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2949 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2950 if (pool == NULL)
2951 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2952
2953 if (pAllocator)
2954 pool->alloc = *pAllocator;
2955 else
2956 pool->alloc = device->alloc;
2957
2958 list_inithead(&pool->cmd_buffers);
2959 list_inithead(&pool->free_cmd_buffers);
2960
2961 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2962
2963 *pCmdPool = radv_cmd_pool_to_handle(pool);
2964
2965 return VK_SUCCESS;
2966
2967 }
2968
2969 void radv_DestroyCommandPool(
2970 VkDevice _device,
2971 VkCommandPool commandPool,
2972 const VkAllocationCallbacks* pAllocator)
2973 {
2974 RADV_FROM_HANDLE(radv_device, device, _device);
2975 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2976
2977 if (!pool)
2978 return;
2979
2980 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2981 &pool->cmd_buffers, pool_link) {
2982 radv_cmd_buffer_destroy(cmd_buffer);
2983 }
2984
2985 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2986 &pool->free_cmd_buffers, pool_link) {
2987 radv_cmd_buffer_destroy(cmd_buffer);
2988 }
2989
2990 vk_free2(&device->alloc, pAllocator, pool);
2991 }
2992
2993 VkResult radv_ResetCommandPool(
2994 VkDevice device,
2995 VkCommandPool commandPool,
2996 VkCommandPoolResetFlags flags)
2997 {
2998 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2999 VkResult result;
3000
3001 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3002 &pool->cmd_buffers, pool_link) {
3003 result = radv_reset_cmd_buffer(cmd_buffer);
3004 if (result != VK_SUCCESS)
3005 return result;
3006 }
3007
3008 return VK_SUCCESS;
3009 }
3010
3011 void radv_TrimCommandPool(
3012 VkDevice device,
3013 VkCommandPool commandPool,
3014 VkCommandPoolTrimFlagsKHR flags)
3015 {
3016 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3017
3018 if (!pool)
3019 return;
3020
3021 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3022 &pool->free_cmd_buffers, pool_link) {
3023 radv_cmd_buffer_destroy(cmd_buffer);
3024 }
3025 }
3026
3027 void radv_CmdBeginRenderPass(
3028 VkCommandBuffer commandBuffer,
3029 const VkRenderPassBeginInfo* pRenderPassBegin,
3030 VkSubpassContents contents)
3031 {
3032 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3033 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3034 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3035
3036 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3037 cmd_buffer->cs, 2048);
3038 MAYBE_UNUSED VkResult result;
3039
3040 cmd_buffer->state.framebuffer = framebuffer;
3041 cmd_buffer->state.pass = pass;
3042 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3043
3044 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3045 if (result != VK_SUCCESS)
3046 return;
3047
3048 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3049 assert(cmd_buffer->cs->cdw <= cdw_max);
3050
3051 radv_cmd_buffer_clear_subpass(cmd_buffer);
3052 }
3053
3054 void radv_CmdBeginRenderPass2KHR(
3055 VkCommandBuffer commandBuffer,
3056 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3057 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3058 {
3059 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3060 pSubpassBeginInfo->contents);
3061 }
3062
3063 void radv_CmdNextSubpass(
3064 VkCommandBuffer commandBuffer,
3065 VkSubpassContents contents)
3066 {
3067 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3068
3069 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3070
3071 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3072 2048);
3073
3074 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3075 radv_cmd_buffer_clear_subpass(cmd_buffer);
3076 }
3077
3078 void radv_CmdNextSubpass2KHR(
3079 VkCommandBuffer commandBuffer,
3080 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3081 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3082 {
3083 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3084 }
3085
3086 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3087 {
3088 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3089 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3090 if (!radv_get_shader(pipeline, stage))
3091 continue;
3092
3093 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3094 if (loc->sgpr_idx == -1)
3095 continue;
3096 uint32_t base_reg = pipeline->user_data_0[stage];
3097 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3098
3099 }
3100 if (pipeline->gs_copy_shader) {
3101 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3102 if (loc->sgpr_idx != -1) {
3103 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3104 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3105 }
3106 }
3107 }
3108
3109 static void
3110 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3111 uint32_t vertex_count)
3112 {
3113 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3114 radeon_emit(cmd_buffer->cs, vertex_count);
3115 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3116 S_0287F0_USE_OPAQUE(0));
3117 }
3118
3119 static void
3120 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3121 uint64_t index_va,
3122 uint32_t index_count)
3123 {
3124 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3125 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3126 radeon_emit(cmd_buffer->cs, index_va);
3127 radeon_emit(cmd_buffer->cs, index_va >> 32);
3128 radeon_emit(cmd_buffer->cs, index_count);
3129 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3130 }
3131
3132 static void
3133 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3134 bool indexed,
3135 uint32_t draw_count,
3136 uint64_t count_va,
3137 uint32_t stride)
3138 {
3139 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3140 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3141 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3142 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3143 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3144 assert(base_reg);
3145
3146 /* just reset draw state for vertex data */
3147 cmd_buffer->state.last_first_instance = -1;
3148 cmd_buffer->state.last_num_instances = -1;
3149 cmd_buffer->state.last_vertex_offset = -1;
3150
3151 if (draw_count == 1 && !count_va && !draw_id_enable) {
3152 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3153 PKT3_DRAW_INDIRECT, 3, false));
3154 radeon_emit(cs, 0);
3155 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3156 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3157 radeon_emit(cs, di_src_sel);
3158 } else {
3159 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3160 PKT3_DRAW_INDIRECT_MULTI,
3161 8, false));
3162 radeon_emit(cs, 0);
3163 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3164 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3165 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3166 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3167 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3168 radeon_emit(cs, draw_count); /* count */
3169 radeon_emit(cs, count_va); /* count_addr */
3170 radeon_emit(cs, count_va >> 32);
3171 radeon_emit(cs, stride); /* stride */
3172 radeon_emit(cs, di_src_sel);
3173 }
3174 }
3175
3176 struct radv_draw_info {
3177 /**
3178 * Number of vertices.
3179 */
3180 uint32_t count;
3181
3182 /**
3183 * Index of the first vertex.
3184 */
3185 int32_t vertex_offset;
3186
3187 /**
3188 * First instance id.
3189 */
3190 uint32_t first_instance;
3191
3192 /**
3193 * Number of instances.
3194 */
3195 uint32_t instance_count;
3196
3197 /**
3198 * First index (indexed draws only).
3199 */
3200 uint32_t first_index;
3201
3202 /**
3203 * Whether it's an indexed draw.
3204 */
3205 bool indexed;
3206
3207 /**
3208 * Indirect draw parameters resource.
3209 */
3210 struct radv_buffer *indirect;
3211 uint64_t indirect_offset;
3212 uint32_t stride;
3213
3214 /**
3215 * Draw count parameters resource.
3216 */
3217 struct radv_buffer *count_buffer;
3218 uint64_t count_buffer_offset;
3219 };
3220
3221 static void
3222 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3223 const struct radv_draw_info *info)
3224 {
3225 struct radv_cmd_state *state = &cmd_buffer->state;
3226 struct radeon_winsys *ws = cmd_buffer->device->ws;
3227 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3228
3229 if (info->indirect) {
3230 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3231 uint64_t count_va = 0;
3232
3233 va += info->indirect->offset + info->indirect_offset;
3234
3235 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3236
3237 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3238 radeon_emit(cs, 1);
3239 radeon_emit(cs, va);
3240 radeon_emit(cs, va >> 32);
3241
3242 if (info->count_buffer) {
3243 count_va = radv_buffer_get_va(info->count_buffer->bo);
3244 count_va += info->count_buffer->offset +
3245 info->count_buffer_offset;
3246
3247 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3248 }
3249
3250 if (!state->subpass->view_mask) {
3251 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3252 info->indexed,
3253 info->count,
3254 count_va,
3255 info->stride);
3256 } else {
3257 unsigned i;
3258 for_each_bit(i, state->subpass->view_mask) {
3259 radv_emit_view_index(cmd_buffer, i);
3260
3261 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3262 info->indexed,
3263 info->count,
3264 count_va,
3265 info->stride);
3266 }
3267 }
3268 } else {
3269 assert(state->pipeline->graphics.vtx_base_sgpr);
3270
3271 if (info->vertex_offset != state->last_vertex_offset ||
3272 info->first_instance != state->last_first_instance) {
3273 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3274 state->pipeline->graphics.vtx_emit_num);
3275
3276 radeon_emit(cs, info->vertex_offset);
3277 radeon_emit(cs, info->first_instance);
3278 if (state->pipeline->graphics.vtx_emit_num == 3)
3279 radeon_emit(cs, 0);
3280 state->last_first_instance = info->first_instance;
3281 state->last_vertex_offset = info->vertex_offset;
3282 }
3283
3284 if (state->last_num_instances != info->instance_count) {
3285 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3286 radeon_emit(cs, info->instance_count);
3287 state->last_num_instances = info->instance_count;
3288 }
3289
3290 if (info->indexed) {
3291 int index_size = state->index_type ? 4 : 2;
3292 uint64_t index_va;
3293
3294 index_va = state->index_va;
3295 index_va += info->first_index * index_size;
3296
3297 if (!state->subpass->view_mask) {
3298 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3299 index_va,
3300 info->count);
3301 } else {
3302 unsigned i;
3303 for_each_bit(i, state->subpass->view_mask) {
3304 radv_emit_view_index(cmd_buffer, i);
3305
3306 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3307 index_va,
3308 info->count);
3309 }
3310 }
3311 } else {
3312 if (!state->subpass->view_mask) {
3313 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3314 } else {
3315 unsigned i;
3316 for_each_bit(i, state->subpass->view_mask) {
3317 radv_emit_view_index(cmd_buffer, i);
3318
3319 radv_cs_emit_draw_packet(cmd_buffer,
3320 info->count);
3321 }
3322 }
3323 }
3324 }
3325 }
3326
3327 /*
3328 * Vega and raven have a bug which triggers if there are multiple context
3329 * register contexts active at the same time with different scissor values.
3330 *
3331 * There are two possible workarounds:
3332 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3333 * there is only ever 1 active set of scissor values at the same time.
3334 *
3335 * 2) Whenever the hardware switches contexts we have to set the scissor
3336 * registers again even if it is a noop. That way the new context gets
3337 * the correct scissor values.
3338 *
3339 * This implements option 2. radv_need_late_scissor_emission needs to
3340 * return true on affected HW if radv_emit_all_graphics_states sets
3341 * any context registers.
3342 */
3343 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3344 bool indexed_draw)
3345 {
3346 struct radv_cmd_state *state = &cmd_buffer->state;
3347
3348 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3349 return false;
3350
3351 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3352
3353 /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3354 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_VERTEX_BUFFER | RADV_CMD_DIRTY_PIPELINE);
3355
3356 /* Assume all state changes except these two can imply context rolls. */
3357 if (cmd_buffer->state.dirty & used_states)
3358 return true;
3359
3360 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3361 return true;
3362
3363 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3364 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3365 return true;
3366
3367 return false;
3368 }
3369
3370 static void
3371 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3372 const struct radv_draw_info *info)
3373 {
3374 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3375
3376 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3377 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3378 radv_emit_rbplus_state(cmd_buffer);
3379
3380 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3381 radv_emit_graphics_pipeline(cmd_buffer);
3382
3383 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3384 radv_emit_framebuffer_state(cmd_buffer);
3385
3386 if (info->indexed) {
3387 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3388 radv_emit_index_buffer(cmd_buffer);
3389 } else {
3390 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3391 * so the state must be re-emitted before the next indexed
3392 * draw.
3393 */
3394 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3395 cmd_buffer->state.last_index_type = -1;
3396 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3397 }
3398 }
3399
3400 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3401
3402 radv_emit_draw_registers(cmd_buffer, info->indexed,
3403 info->instance_count > 1, info->indirect,
3404 info->indirect ? 0 : info->count);
3405
3406 if (late_scissor_emission)
3407 radv_emit_scissor(cmd_buffer);
3408 }
3409
3410 static void
3411 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3412 const struct radv_draw_info *info)
3413 {
3414 bool has_prefetch =
3415 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3416 bool pipeline_is_dirty =
3417 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3418 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3419
3420 MAYBE_UNUSED unsigned cdw_max =
3421 radeon_check_space(cmd_buffer->device->ws,
3422 cmd_buffer->cs, 4096);
3423
3424 /* Use optimal packet order based on whether we need to sync the
3425 * pipeline.
3426 */
3427 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3428 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3429 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3430 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3431 /* If we have to wait for idle, set all states first, so that
3432 * all SET packets are processed in parallel with previous draw
3433 * calls. Then upload descriptors, set shader pointers, and
3434 * draw, and prefetch at the end. This ensures that the time
3435 * the CUs are idle is very short. (there are only SET_SH
3436 * packets between the wait and the draw)
3437 */
3438 radv_emit_all_graphics_states(cmd_buffer, info);
3439 si_emit_cache_flush(cmd_buffer);
3440 /* <-- CUs are idle here --> */
3441
3442 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3443
3444 radv_emit_draw_packets(cmd_buffer, info);
3445 /* <-- CUs are busy here --> */
3446
3447 /* Start prefetches after the draw has been started. Both will
3448 * run in parallel, but starting the draw first is more
3449 * important.
3450 */
3451 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3452 radv_emit_prefetch_L2(cmd_buffer,
3453 cmd_buffer->state.pipeline, false);
3454 }
3455 } else {
3456 /* If we don't wait for idle, start prefetches first, then set
3457 * states, and draw at the end.
3458 */
3459 si_emit_cache_flush(cmd_buffer);
3460
3461 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3462 /* Only prefetch the vertex shader and VBO descriptors
3463 * in order to start the draw as soon as possible.
3464 */
3465 radv_emit_prefetch_L2(cmd_buffer,
3466 cmd_buffer->state.pipeline, true);
3467 }
3468
3469 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3470
3471 radv_emit_all_graphics_states(cmd_buffer, info);
3472 radv_emit_draw_packets(cmd_buffer, info);
3473
3474 /* Prefetch the remaining shaders after the draw has been
3475 * started.
3476 */
3477 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3478 radv_emit_prefetch_L2(cmd_buffer,
3479 cmd_buffer->state.pipeline, false);
3480 }
3481 }
3482
3483 assert(cmd_buffer->cs->cdw <= cdw_max);
3484 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3485 }
3486
3487 void radv_CmdDraw(
3488 VkCommandBuffer commandBuffer,
3489 uint32_t vertexCount,
3490 uint32_t instanceCount,
3491 uint32_t firstVertex,
3492 uint32_t firstInstance)
3493 {
3494 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3495 struct radv_draw_info info = {};
3496
3497 info.count = vertexCount;
3498 info.instance_count = instanceCount;
3499 info.first_instance = firstInstance;
3500 info.vertex_offset = firstVertex;
3501
3502 radv_draw(cmd_buffer, &info);
3503 }
3504
3505 void radv_CmdDrawIndexed(
3506 VkCommandBuffer commandBuffer,
3507 uint32_t indexCount,
3508 uint32_t instanceCount,
3509 uint32_t firstIndex,
3510 int32_t vertexOffset,
3511 uint32_t firstInstance)
3512 {
3513 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3514 struct radv_draw_info info = {};
3515
3516 info.indexed = true;
3517 info.count = indexCount;
3518 info.instance_count = instanceCount;
3519 info.first_index = firstIndex;
3520 info.vertex_offset = vertexOffset;
3521 info.first_instance = firstInstance;
3522
3523 radv_draw(cmd_buffer, &info);
3524 }
3525
3526 void radv_CmdDrawIndirect(
3527 VkCommandBuffer commandBuffer,
3528 VkBuffer _buffer,
3529 VkDeviceSize offset,
3530 uint32_t drawCount,
3531 uint32_t stride)
3532 {
3533 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3534 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3535 struct radv_draw_info info = {};
3536
3537 info.count = drawCount;
3538 info.indirect = buffer;
3539 info.indirect_offset = offset;
3540 info.stride = stride;
3541
3542 radv_draw(cmd_buffer, &info);
3543 }
3544
3545 void radv_CmdDrawIndexedIndirect(
3546 VkCommandBuffer commandBuffer,
3547 VkBuffer _buffer,
3548 VkDeviceSize offset,
3549 uint32_t drawCount,
3550 uint32_t stride)
3551 {
3552 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3553 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3554 struct radv_draw_info info = {};
3555
3556 info.indexed = true;
3557 info.count = drawCount;
3558 info.indirect = buffer;
3559 info.indirect_offset = offset;
3560 info.stride = stride;
3561
3562 radv_draw(cmd_buffer, &info);
3563 }
3564
3565 void radv_CmdDrawIndirectCountAMD(
3566 VkCommandBuffer commandBuffer,
3567 VkBuffer _buffer,
3568 VkDeviceSize offset,
3569 VkBuffer _countBuffer,
3570 VkDeviceSize countBufferOffset,
3571 uint32_t maxDrawCount,
3572 uint32_t stride)
3573 {
3574 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3575 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3576 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3577 struct radv_draw_info info = {};
3578
3579 info.count = maxDrawCount;
3580 info.indirect = buffer;
3581 info.indirect_offset = offset;
3582 info.count_buffer = count_buffer;
3583 info.count_buffer_offset = countBufferOffset;
3584 info.stride = stride;
3585
3586 radv_draw(cmd_buffer, &info);
3587 }
3588
3589 void radv_CmdDrawIndexedIndirectCountAMD(
3590 VkCommandBuffer commandBuffer,
3591 VkBuffer _buffer,
3592 VkDeviceSize offset,
3593 VkBuffer _countBuffer,
3594 VkDeviceSize countBufferOffset,
3595 uint32_t maxDrawCount,
3596 uint32_t stride)
3597 {
3598 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3599 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3600 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3601 struct radv_draw_info info = {};
3602
3603 info.indexed = true;
3604 info.count = maxDrawCount;
3605 info.indirect = buffer;
3606 info.indirect_offset = offset;
3607 info.count_buffer = count_buffer;
3608 info.count_buffer_offset = countBufferOffset;
3609 info.stride = stride;
3610
3611 radv_draw(cmd_buffer, &info);
3612 }
3613
3614 void radv_CmdDrawIndirectCountKHR(
3615 VkCommandBuffer commandBuffer,
3616 VkBuffer _buffer,
3617 VkDeviceSize offset,
3618 VkBuffer _countBuffer,
3619 VkDeviceSize countBufferOffset,
3620 uint32_t maxDrawCount,
3621 uint32_t stride)
3622 {
3623 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3624 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3625 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3626 struct radv_draw_info info = {};
3627
3628 info.count = maxDrawCount;
3629 info.indirect = buffer;
3630 info.indirect_offset = offset;
3631 info.count_buffer = count_buffer;
3632 info.count_buffer_offset = countBufferOffset;
3633 info.stride = stride;
3634
3635 radv_draw(cmd_buffer, &info);
3636 }
3637
3638 void radv_CmdDrawIndexedIndirectCountKHR(
3639 VkCommandBuffer commandBuffer,
3640 VkBuffer _buffer,
3641 VkDeviceSize offset,
3642 VkBuffer _countBuffer,
3643 VkDeviceSize countBufferOffset,
3644 uint32_t maxDrawCount,
3645 uint32_t stride)
3646 {
3647 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3648 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3649 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3650 struct radv_draw_info info = {};
3651
3652 info.indexed = true;
3653 info.count = maxDrawCount;
3654 info.indirect = buffer;
3655 info.indirect_offset = offset;
3656 info.count_buffer = count_buffer;
3657 info.count_buffer_offset = countBufferOffset;
3658 info.stride = stride;
3659
3660 radv_draw(cmd_buffer, &info);
3661 }
3662
3663 struct radv_dispatch_info {
3664 /**
3665 * Determine the layout of the grid (in block units) to be used.
3666 */
3667 uint32_t blocks[3];
3668
3669 /**
3670 * A starting offset for the grid. If unaligned is set, the offset
3671 * must still be aligned.
3672 */
3673 uint32_t offsets[3];
3674 /**
3675 * Whether it's an unaligned compute dispatch.
3676 */
3677 bool unaligned;
3678
3679 /**
3680 * Indirect compute parameters resource.
3681 */
3682 struct radv_buffer *indirect;
3683 uint64_t indirect_offset;
3684 };
3685
3686 static void
3687 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3688 const struct radv_dispatch_info *info)
3689 {
3690 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3691 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3692 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3693 struct radeon_winsys *ws = cmd_buffer->device->ws;
3694 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3695 struct radv_userdata_info *loc;
3696
3697 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3698 AC_UD_CS_GRID_SIZE);
3699
3700 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3701
3702 if (info->indirect) {
3703 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3704
3705 va += info->indirect->offset + info->indirect_offset;
3706
3707 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3708
3709 if (loc->sgpr_idx != -1) {
3710 for (unsigned i = 0; i < 3; ++i) {
3711 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3712 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3713 COPY_DATA_DST_SEL(COPY_DATA_REG));
3714 radeon_emit(cs, (va + 4 * i));
3715 radeon_emit(cs, (va + 4 * i) >> 32);
3716 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3717 + loc->sgpr_idx * 4) >> 2) + i);
3718 radeon_emit(cs, 0);
3719 }
3720 }
3721
3722 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3723 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3724 PKT3_SHADER_TYPE_S(1));
3725 radeon_emit(cs, va);
3726 radeon_emit(cs, va >> 32);
3727 radeon_emit(cs, dispatch_initiator);
3728 } else {
3729 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3730 PKT3_SHADER_TYPE_S(1));
3731 radeon_emit(cs, 1);
3732 radeon_emit(cs, va);
3733 radeon_emit(cs, va >> 32);
3734
3735 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3736 PKT3_SHADER_TYPE_S(1));
3737 radeon_emit(cs, 0);
3738 radeon_emit(cs, dispatch_initiator);
3739 }
3740 } else {
3741 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3742 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3743
3744 if (info->unaligned) {
3745 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3746 unsigned remainder[3];
3747
3748 /* If aligned, these should be an entire block size,
3749 * not 0.
3750 */
3751 remainder[0] = blocks[0] + cs_block_size[0] -
3752 align_u32_npot(blocks[0], cs_block_size[0]);
3753 remainder[1] = blocks[1] + cs_block_size[1] -
3754 align_u32_npot(blocks[1], cs_block_size[1]);
3755 remainder[2] = blocks[2] + cs_block_size[2] -
3756 align_u32_npot(blocks[2], cs_block_size[2]);
3757
3758 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3759 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3760 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3761
3762 for(unsigned i = 0; i < 3; ++i) {
3763 assert(offsets[i] % cs_block_size[i] == 0);
3764 offsets[i] /= cs_block_size[i];
3765 }
3766
3767 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3768 radeon_emit(cs,
3769 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3770 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3771 radeon_emit(cs,
3772 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3773 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3774 radeon_emit(cs,
3775 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3776 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3777
3778 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3779 }
3780
3781 if (loc->sgpr_idx != -1) {
3782 assert(!loc->indirect);
3783 assert(loc->num_sgprs == 3);
3784
3785 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3786 loc->sgpr_idx * 4, 3);
3787 radeon_emit(cs, blocks[0]);
3788 radeon_emit(cs, blocks[1]);
3789 radeon_emit(cs, blocks[2]);
3790 }
3791
3792 if (offsets[0] || offsets[1] || offsets[2]) {
3793 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3794 radeon_emit(cs, offsets[0]);
3795 radeon_emit(cs, offsets[1]);
3796 radeon_emit(cs, offsets[2]);
3797
3798 /* The blocks in the packet are not counts but end values. */
3799 for (unsigned i = 0; i < 3; ++i)
3800 blocks[i] += offsets[i];
3801 } else {
3802 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3803 }
3804
3805 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3806 PKT3_SHADER_TYPE_S(1));
3807 radeon_emit(cs, blocks[0]);
3808 radeon_emit(cs, blocks[1]);
3809 radeon_emit(cs, blocks[2]);
3810 radeon_emit(cs, dispatch_initiator);
3811 }
3812
3813 assert(cmd_buffer->cs->cdw <= cdw_max);
3814 }
3815
3816 static void
3817 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3818 {
3819 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3820 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3821 }
3822
3823 static void
3824 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3825 const struct radv_dispatch_info *info)
3826 {
3827 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3828 bool has_prefetch =
3829 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3830 bool pipeline_is_dirty = pipeline &&
3831 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3832
3833 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3834 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3835 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3836 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3837 /* If we have to wait for idle, set all states first, so that
3838 * all SET packets are processed in parallel with previous draw
3839 * calls. Then upload descriptors, set shader pointers, and
3840 * dispatch, and prefetch at the end. This ensures that the
3841 * time the CUs are idle is very short. (there are only SET_SH
3842 * packets between the wait and the draw)
3843 */
3844 radv_emit_compute_pipeline(cmd_buffer);
3845 si_emit_cache_flush(cmd_buffer);
3846 /* <-- CUs are idle here --> */
3847
3848 radv_upload_compute_shader_descriptors(cmd_buffer);
3849
3850 radv_emit_dispatch_packets(cmd_buffer, info);
3851 /* <-- CUs are busy here --> */
3852
3853 /* Start prefetches after the dispatch has been started. Both
3854 * will run in parallel, but starting the dispatch first is
3855 * more important.
3856 */
3857 if (has_prefetch && pipeline_is_dirty) {
3858 radv_emit_shader_prefetch(cmd_buffer,
3859 pipeline->shaders[MESA_SHADER_COMPUTE]);
3860 }
3861 } else {
3862 /* If we don't wait for idle, start prefetches first, then set
3863 * states, and dispatch at the end.
3864 */
3865 si_emit_cache_flush(cmd_buffer);
3866
3867 if (has_prefetch && pipeline_is_dirty) {
3868 radv_emit_shader_prefetch(cmd_buffer,
3869 pipeline->shaders[MESA_SHADER_COMPUTE]);
3870 }
3871
3872 radv_upload_compute_shader_descriptors(cmd_buffer);
3873
3874 radv_emit_compute_pipeline(cmd_buffer);
3875 radv_emit_dispatch_packets(cmd_buffer, info);
3876 }
3877
3878 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3879 }
3880
3881 void radv_CmdDispatchBase(
3882 VkCommandBuffer commandBuffer,
3883 uint32_t base_x,
3884 uint32_t base_y,
3885 uint32_t base_z,
3886 uint32_t x,
3887 uint32_t y,
3888 uint32_t z)
3889 {
3890 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3891 struct radv_dispatch_info info = {};
3892
3893 info.blocks[0] = x;
3894 info.blocks[1] = y;
3895 info.blocks[2] = z;
3896
3897 info.offsets[0] = base_x;
3898 info.offsets[1] = base_y;
3899 info.offsets[2] = base_z;
3900 radv_dispatch(cmd_buffer, &info);
3901 }
3902
3903 void radv_CmdDispatch(
3904 VkCommandBuffer commandBuffer,
3905 uint32_t x,
3906 uint32_t y,
3907 uint32_t z)
3908 {
3909 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3910 }
3911
3912 void radv_CmdDispatchIndirect(
3913 VkCommandBuffer commandBuffer,
3914 VkBuffer _buffer,
3915 VkDeviceSize offset)
3916 {
3917 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3918 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3919 struct radv_dispatch_info info = {};
3920
3921 info.indirect = buffer;
3922 info.indirect_offset = offset;
3923
3924 radv_dispatch(cmd_buffer, &info);
3925 }
3926
3927 void radv_unaligned_dispatch(
3928 struct radv_cmd_buffer *cmd_buffer,
3929 uint32_t x,
3930 uint32_t y,
3931 uint32_t z)
3932 {
3933 struct radv_dispatch_info info = {};
3934
3935 info.blocks[0] = x;
3936 info.blocks[1] = y;
3937 info.blocks[2] = z;
3938 info.unaligned = 1;
3939
3940 radv_dispatch(cmd_buffer, &info);
3941 }
3942
3943 void radv_CmdEndRenderPass(
3944 VkCommandBuffer commandBuffer)
3945 {
3946 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3947
3948 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3949
3950 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3951
3952 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3953 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3954 radv_handle_subpass_image_transition(cmd_buffer,
3955 (struct radv_subpass_attachment){i, layout});
3956 }
3957
3958 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3959
3960 cmd_buffer->state.pass = NULL;
3961 cmd_buffer->state.subpass = NULL;
3962 cmd_buffer->state.attachments = NULL;
3963 cmd_buffer->state.framebuffer = NULL;
3964 }
3965
3966 void radv_CmdEndRenderPass2KHR(
3967 VkCommandBuffer commandBuffer,
3968 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3969 {
3970 radv_CmdEndRenderPass(commandBuffer);
3971 }
3972
3973 /*
3974 * For HTILE we have the following interesting clear words:
3975 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3976 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3977 * 0xfffffff0: Clear depth to 1.0
3978 * 0x00000000: Clear depth to 0.0
3979 */
3980 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3981 struct radv_image *image,
3982 const VkImageSubresourceRange *range,
3983 uint32_t clear_word)
3984 {
3985 assert(range->baseMipLevel == 0);
3986 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3987 unsigned layer_count = radv_get_layerCount(image, range);
3988 uint64_t size = image->surface.htile_slice_size * layer_count;
3989 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
3990 uint64_t offset = image->offset + image->htile_offset +
3991 image->surface.htile_slice_size * range->baseArrayLayer;
3992 struct radv_cmd_state *state = &cmd_buffer->state;
3993 VkClearDepthStencilValue value = {};
3994
3995 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3996 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3997
3998 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3999 size, clear_word);
4000
4001 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4002
4003 if (vk_format_is_stencil(image->vk_format))
4004 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4005
4006 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4007 }
4008
4009 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4010 struct radv_image *image,
4011 VkImageLayout src_layout,
4012 VkImageLayout dst_layout,
4013 unsigned src_queue_mask,
4014 unsigned dst_queue_mask,
4015 const VkImageSubresourceRange *range,
4016 VkImageAspectFlags pending_clears)
4017 {
4018 if (!radv_image_has_htile(image))
4019 return;
4020
4021 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4022 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4023 /* TODO: merge with the clear if applicable */
4024 radv_initialize_htile(cmd_buffer, image, range, 0);
4025 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4026 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4027 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4028 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4029 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4030 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4031 VkImageSubresourceRange local_range = *range;
4032 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4033 local_range.baseMipLevel = 0;
4034 local_range.levelCount = 1;
4035
4036 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4037 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4038
4039 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4040
4041 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4042 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4043 }
4044 }
4045
4046 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4047 struct radv_image *image, uint32_t value)
4048 {
4049 struct radv_cmd_state *state = &cmd_buffer->state;
4050
4051 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4052 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4053
4054 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4055
4056 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4057 }
4058
4059 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4060 struct radv_image *image, uint32_t value)
4061 {
4062 struct radv_cmd_state *state = &cmd_buffer->state;
4063
4064 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4065 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4066
4067 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4068
4069 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4070 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4071 }
4072
4073 /**
4074 * Initialize DCC/FMASK/CMASK metadata for a color image.
4075 */
4076 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4077 struct radv_image *image,
4078 VkImageLayout src_layout,
4079 VkImageLayout dst_layout,
4080 unsigned src_queue_mask,
4081 unsigned dst_queue_mask)
4082 {
4083 if (radv_image_has_cmask(image)) {
4084 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4085
4086 /* TODO: clarify this. */
4087 if (radv_image_has_fmask(image)) {
4088 value = 0xccccccccu;
4089 }
4090
4091 radv_initialise_cmask(cmd_buffer, image, value);
4092 }
4093
4094 if (radv_image_has_dcc(image)) {
4095 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4096
4097 if (radv_layout_dcc_compressed(image, dst_layout,
4098 dst_queue_mask)) {
4099 value = 0x20202020u;
4100 }
4101
4102 radv_initialize_dcc(cmd_buffer, image, value);
4103
4104 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image, false);
4105 }
4106
4107 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4108 uint32_t color_values[2] = {};
4109 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4110 }
4111 }
4112
4113 /**
4114 * Handle color image transitions for DCC/FMASK/CMASK.
4115 */
4116 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4117 struct radv_image *image,
4118 VkImageLayout src_layout,
4119 VkImageLayout dst_layout,
4120 unsigned src_queue_mask,
4121 unsigned dst_queue_mask,
4122 const VkImageSubresourceRange *range)
4123 {
4124 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4125 radv_init_color_image_metadata(cmd_buffer, image,
4126 src_layout, dst_layout,
4127 src_queue_mask, dst_queue_mask);
4128 return;
4129 }
4130
4131 if (radv_image_has_dcc(image)) {
4132 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4133 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4134 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4135 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4136 radv_decompress_dcc(cmd_buffer, image, range);
4137 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4138 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4139 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4140 }
4141 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4142 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4143 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4144 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4145 }
4146 }
4147 }
4148
4149 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4150 struct radv_image *image,
4151 VkImageLayout src_layout,
4152 VkImageLayout dst_layout,
4153 uint32_t src_family,
4154 uint32_t dst_family,
4155 const VkImageSubresourceRange *range,
4156 VkImageAspectFlags pending_clears)
4157 {
4158 if (image->exclusive && src_family != dst_family) {
4159 /* This is an acquire or a release operation and there will be
4160 * a corresponding release/acquire. Do the transition in the
4161 * most flexible queue. */
4162
4163 assert(src_family == cmd_buffer->queue_family_index ||
4164 dst_family == cmd_buffer->queue_family_index);
4165
4166 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4167 return;
4168
4169 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4170 (src_family == RADV_QUEUE_GENERAL ||
4171 dst_family == RADV_QUEUE_GENERAL))
4172 return;
4173 }
4174
4175 unsigned src_queue_mask =
4176 radv_image_queue_family_mask(image, src_family,
4177 cmd_buffer->queue_family_index);
4178 unsigned dst_queue_mask =
4179 radv_image_queue_family_mask(image, dst_family,
4180 cmd_buffer->queue_family_index);
4181
4182 if (vk_format_is_depth(image->vk_format)) {
4183 radv_handle_depth_image_transition(cmd_buffer, image,
4184 src_layout, dst_layout,
4185 src_queue_mask, dst_queue_mask,
4186 range, pending_clears);
4187 } else {
4188 radv_handle_color_image_transition(cmd_buffer, image,
4189 src_layout, dst_layout,
4190 src_queue_mask, dst_queue_mask,
4191 range);
4192 }
4193 }
4194
4195 struct radv_barrier_info {
4196 uint32_t eventCount;
4197 const VkEvent *pEvents;
4198 VkPipelineStageFlags srcStageMask;
4199 };
4200
4201 static void
4202 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4203 uint32_t memoryBarrierCount,
4204 const VkMemoryBarrier *pMemoryBarriers,
4205 uint32_t bufferMemoryBarrierCount,
4206 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4207 uint32_t imageMemoryBarrierCount,
4208 const VkImageMemoryBarrier *pImageMemoryBarriers,
4209 const struct radv_barrier_info *info)
4210 {
4211 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4212 enum radv_cmd_flush_bits src_flush_bits = 0;
4213 enum radv_cmd_flush_bits dst_flush_bits = 0;
4214
4215 for (unsigned i = 0; i < info->eventCount; ++i) {
4216 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4217 uint64_t va = radv_buffer_get_va(event->bo);
4218
4219 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4220
4221 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4222
4223 si_emit_wait_fence(cs, va, 1, 0xffffffff);
4224 assert(cmd_buffer->cs->cdw <= cdw_max);
4225 }
4226
4227 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4228 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4229 NULL);
4230 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4231 NULL);
4232 }
4233
4234 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4235 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4236 NULL);
4237 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4238 NULL);
4239 }
4240
4241 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4242 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4243
4244 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4245 image);
4246 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4247 image);
4248 }
4249
4250 radv_stage_flush(cmd_buffer, info->srcStageMask);
4251 cmd_buffer->state.flush_bits |= src_flush_bits;
4252
4253 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4254 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4255 radv_handle_image_transition(cmd_buffer, image,
4256 pImageMemoryBarriers[i].oldLayout,
4257 pImageMemoryBarriers[i].newLayout,
4258 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4259 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4260 &pImageMemoryBarriers[i].subresourceRange,
4261 0);
4262 }
4263
4264 /* Make sure CP DMA is idle because the driver might have performed a
4265 * DMA operation for copying or filling buffers/images.
4266 */
4267 si_cp_dma_wait_for_idle(cmd_buffer);
4268
4269 cmd_buffer->state.flush_bits |= dst_flush_bits;
4270 }
4271
4272 void radv_CmdPipelineBarrier(
4273 VkCommandBuffer commandBuffer,
4274 VkPipelineStageFlags srcStageMask,
4275 VkPipelineStageFlags destStageMask,
4276 VkBool32 byRegion,
4277 uint32_t memoryBarrierCount,
4278 const VkMemoryBarrier* pMemoryBarriers,
4279 uint32_t bufferMemoryBarrierCount,
4280 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4281 uint32_t imageMemoryBarrierCount,
4282 const VkImageMemoryBarrier* pImageMemoryBarriers)
4283 {
4284 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4285 struct radv_barrier_info info;
4286
4287 info.eventCount = 0;
4288 info.pEvents = NULL;
4289 info.srcStageMask = srcStageMask;
4290
4291 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4292 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4293 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4294 }
4295
4296
4297 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4298 struct radv_event *event,
4299 VkPipelineStageFlags stageMask,
4300 unsigned value)
4301 {
4302 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4303 uint64_t va = radv_buffer_get_va(event->bo);
4304
4305 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4306
4307 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4308
4309 /* Flags that only require a top-of-pipe event. */
4310 VkPipelineStageFlags top_of_pipe_flags =
4311 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4312
4313 /* Flags that only require a post-index-fetch event. */
4314 VkPipelineStageFlags post_index_fetch_flags =
4315 top_of_pipe_flags |
4316 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4317 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4318
4319 /* Make sure CP DMA is idle because the driver might have performed a
4320 * DMA operation for copying or filling buffers/images.
4321 */
4322 si_cp_dma_wait_for_idle(cmd_buffer);
4323
4324 /* TODO: Emit EOS events for syncing PS/CS stages. */
4325
4326 if (!(stageMask & ~top_of_pipe_flags)) {
4327 /* Just need to sync the PFP engine. */
4328 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4329 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4330 S_370_WR_CONFIRM(1) |
4331 S_370_ENGINE_SEL(V_370_PFP));
4332 radeon_emit(cs, va);
4333 radeon_emit(cs, va >> 32);
4334 radeon_emit(cs, value);
4335 } else if (!(stageMask & ~post_index_fetch_flags)) {
4336 /* Sync ME because PFP reads index and indirect buffers. */
4337 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4338 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4339 S_370_WR_CONFIRM(1) |
4340 S_370_ENGINE_SEL(V_370_ME));
4341 radeon_emit(cs, va);
4342 radeon_emit(cs, va >> 32);
4343 radeon_emit(cs, value);
4344 } else {
4345 /* Otherwise, sync all prior GPU work using an EOP event. */
4346 si_cs_emit_write_event_eop(cs,
4347 cmd_buffer->device->physical_device->rad_info.chip_class,
4348 radv_cmd_buffer_uses_mec(cmd_buffer),
4349 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4350 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4351 cmd_buffer->gfx9_eop_bug_va);
4352 }
4353
4354 assert(cmd_buffer->cs->cdw <= cdw_max);
4355 }
4356
4357 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4358 VkEvent _event,
4359 VkPipelineStageFlags stageMask)
4360 {
4361 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4362 RADV_FROM_HANDLE(radv_event, event, _event);
4363
4364 write_event(cmd_buffer, event, stageMask, 1);
4365 }
4366
4367 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4368 VkEvent _event,
4369 VkPipelineStageFlags stageMask)
4370 {
4371 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4372 RADV_FROM_HANDLE(radv_event, event, _event);
4373
4374 write_event(cmd_buffer, event, stageMask, 0);
4375 }
4376
4377 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4378 uint32_t eventCount,
4379 const VkEvent* pEvents,
4380 VkPipelineStageFlags srcStageMask,
4381 VkPipelineStageFlags dstStageMask,
4382 uint32_t memoryBarrierCount,
4383 const VkMemoryBarrier* pMemoryBarriers,
4384 uint32_t bufferMemoryBarrierCount,
4385 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4386 uint32_t imageMemoryBarrierCount,
4387 const VkImageMemoryBarrier* pImageMemoryBarriers)
4388 {
4389 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4390 struct radv_barrier_info info;
4391
4392 info.eventCount = eventCount;
4393 info.pEvents = pEvents;
4394 info.srcStageMask = 0;
4395
4396 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4397 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4398 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4399 }
4400
4401
4402 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4403 uint32_t deviceMask)
4404 {
4405 /* No-op */
4406 }