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e45f61298726bf7dca7c00b080bb7c5ed61fa181
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "gfx9d.h"
33 #include "vk_format.h"
34 #include "radv_meta.h"
35
36 #include "ac_debug.h"
37
38 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
39 struct radv_image *image,
40 VkImageLayout src_layout,
41 VkImageLayout dst_layout,
42 uint32_t src_family,
43 uint32_t dst_family,
44 const VkImageSubresourceRange *range,
45 VkImageAspectFlags pending_clears);
46
47 const struct radv_dynamic_state default_dynamic_state = {
48 .viewport = {
49 .count = 0,
50 },
51 .scissor = {
52 .count = 0,
53 },
54 .line_width = 1.0f,
55 .depth_bias = {
56 .bias = 0.0f,
57 .clamp = 0.0f,
58 .slope = 0.0f,
59 },
60 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
61 .depth_bounds = {
62 .min = 0.0f,
63 .max = 1.0f,
64 },
65 .stencil_compare_mask = {
66 .front = ~0u,
67 .back = ~0u,
68 },
69 .stencil_write_mask = {
70 .front = ~0u,
71 .back = ~0u,
72 },
73 .stencil_reference = {
74 .front = 0u,
75 .back = 0u,
76 },
77 };
78
79 void
80 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
81 const struct radv_dynamic_state *src,
82 uint32_t copy_mask)
83 {
84 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
85 dest->viewport.count = src->viewport.count;
86 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
87 src->viewport.count);
88 }
89
90 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
91 dest->scissor.count = src->scissor.count;
92 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
93 src->scissor.count);
94 }
95
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
97 dest->line_width = src->line_width;
98
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
100 dest->depth_bias = src->depth_bias;
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
103 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
106 dest->depth_bounds = src->depth_bounds;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
109 dest->stencil_compare_mask = src->stencil_compare_mask;
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
112 dest->stencil_write_mask = src->stencil_write_mask;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
115 dest->stencil_reference = src->stencil_reference;
116 }
117
118 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
119 {
120 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
121 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
122 }
123
124 enum ring_type radv_queue_family_to_ring(int f) {
125 switch (f) {
126 case RADV_QUEUE_GENERAL:
127 return RING_GFX;
128 case RADV_QUEUE_COMPUTE:
129 return RING_COMPUTE;
130 case RADV_QUEUE_TRANSFER:
131 return RING_DMA;
132 default:
133 unreachable("Unknown queue family");
134 }
135 }
136
137 static VkResult radv_create_cmd_buffer(
138 struct radv_device * device,
139 struct radv_cmd_pool * pool,
140 VkCommandBufferLevel level,
141 VkCommandBuffer* pCommandBuffer)
142 {
143 struct radv_cmd_buffer *cmd_buffer;
144 VkResult result;
145 unsigned ring;
146 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
147 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
148 if (cmd_buffer == NULL)
149 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
150
151 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
152 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
153 cmd_buffer->device = device;
154 cmd_buffer->pool = pool;
155 cmd_buffer->level = level;
156
157 if (pool) {
158 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
159 cmd_buffer->queue_family_index = pool->queue_family_index;
160
161 } else {
162 /* Init the pool_link so we can safefly call list_del when we destroy
163 * the command buffer
164 */
165 list_inithead(&cmd_buffer->pool_link);
166 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
167 }
168
169 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
170
171 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
172 if (!cmd_buffer->cs) {
173 result = VK_ERROR_OUT_OF_HOST_MEMORY;
174 goto fail;
175 }
176
177 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
178
179 cmd_buffer->upload.offset = 0;
180 cmd_buffer->upload.size = 0;
181 list_inithead(&cmd_buffer->upload.list);
182
183 return VK_SUCCESS;
184
185 fail:
186 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
187
188 return result;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
211 {
212
213 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
214
215 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
216 &cmd_buffer->upload.list, list) {
217 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
218 list_del(&up->list);
219 free(up);
220 }
221
222 cmd_buffer->scratch_size_needed = 0;
223 cmd_buffer->compute_scratch_size_needed = 0;
224 cmd_buffer->esgs_ring_size_needed = 0;
225 cmd_buffer->gsvs_ring_size_needed = 0;
226 cmd_buffer->tess_rings_needed = false;
227 cmd_buffer->sample_positions_needed = false;
228
229 if (cmd_buffer->upload.upload_bo)
230 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
231 cmd_buffer->upload.upload_bo, 8);
232 cmd_buffer->upload.offset = 0;
233
234 cmd_buffer->record_fail = false;
235
236 cmd_buffer->ring_offsets_idx = -1;
237
238 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
239 void *fence_ptr;
240 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
241 &cmd_buffer->gfx9_fence_offset,
242 &fence_ptr);
243 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
244 }
245 }
246
247 static bool
248 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
249 uint64_t min_needed)
250 {
251 uint64_t new_size;
252 struct radeon_winsys_bo *bo;
253 struct radv_cmd_buffer_upload *upload;
254 struct radv_device *device = cmd_buffer->device;
255
256 new_size = MAX2(min_needed, 16 * 1024);
257 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
258
259 bo = device->ws->buffer_create(device->ws,
260 new_size, 4096,
261 RADEON_DOMAIN_GTT,
262 RADEON_FLAG_CPU_ACCESS);
263
264 if (!bo) {
265 cmd_buffer->record_fail = true;
266 return false;
267 }
268
269 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
270 if (cmd_buffer->upload.upload_bo) {
271 upload = malloc(sizeof(*upload));
272
273 if (!upload) {
274 cmd_buffer->record_fail = true;
275 device->ws->buffer_destroy(bo);
276 return false;
277 }
278
279 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
280 list_add(&upload->list, &cmd_buffer->upload.list);
281 }
282
283 cmd_buffer->upload.upload_bo = bo;
284 cmd_buffer->upload.size = new_size;
285 cmd_buffer->upload.offset = 0;
286 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
287
288 if (!cmd_buffer->upload.map) {
289 cmd_buffer->record_fail = true;
290 return false;
291 }
292
293 return true;
294 }
295
296 bool
297 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
298 unsigned size,
299 unsigned alignment,
300 unsigned *out_offset,
301 void **ptr)
302 {
303 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
304 if (offset + size > cmd_buffer->upload.size) {
305 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
306 return false;
307 offset = 0;
308 }
309
310 *out_offset = offset;
311 *ptr = cmd_buffer->upload.map + offset;
312
313 cmd_buffer->upload.offset = offset + size;
314 return true;
315 }
316
317 bool
318 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
319 unsigned size, unsigned alignment,
320 const void *data, unsigned *out_offset)
321 {
322 uint8_t *ptr;
323
324 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
325 out_offset, (void **)&ptr))
326 return false;
327
328 if (ptr)
329 memcpy(ptr, data, size);
330
331 return true;
332 }
333
334 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
335 {
336 struct radv_device *device = cmd_buffer->device;
337 struct radeon_winsys_cs *cs = cmd_buffer->cs;
338 uint64_t va;
339
340 if (!device->trace_bo)
341 return;
342
343 va = device->ws->buffer_get_va(device->trace_bo);
344
345 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
346
347 ++cmd_buffer->state.trace_id;
348 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
349 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
350 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
351 S_370_WR_CONFIRM(1) |
352 S_370_ENGINE_SEL(V_370_ME));
353 radeon_emit(cs, va);
354 radeon_emit(cs, va >> 32);
355 radeon_emit(cs, cmd_buffer->state.trace_id);
356 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
357 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
358 }
359
360 static void
361 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
362 struct radv_pipeline *pipeline)
363 {
364 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
365 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
366 8);
367 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
369
370 if (cmd_buffer->device->physical_device->has_rbplus) {
371 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
372 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
373 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
374 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
375 }
376 }
377
378 static void
379 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
380 struct radv_pipeline *pipeline)
381 {
382 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
383 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
384 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
385
386 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
387 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
388 }
389
390 /* 12.4 fixed-point */
391 static unsigned radv_pack_float_12p4(float x)
392 {
393 return x <= 0 ? 0 :
394 x >= 4096 ? 0xffff : x * 16;
395 }
396
397 uint32_t
398 radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
399 {
400 switch (stage) {
401 case MESA_SHADER_FRAGMENT:
402 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
403 case MESA_SHADER_VERTEX:
404 if (has_tess)
405 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
406 else
407 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
408 case MESA_SHADER_GEOMETRY:
409 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
410 case MESA_SHADER_COMPUTE:
411 return R_00B900_COMPUTE_USER_DATA_0;
412 case MESA_SHADER_TESS_CTRL:
413 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
414 case MESA_SHADER_TESS_EVAL:
415 if (has_gs)
416 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
417 else
418 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
419 default:
420 unreachable("unknown shader");
421 }
422 }
423
424 struct ac_userdata_info *
425 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
426 gl_shader_stage stage,
427 int idx)
428 {
429 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
430 }
431
432 static void
433 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
434 struct radv_pipeline *pipeline,
435 gl_shader_stage stage,
436 int idx, uint64_t va)
437 {
438 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
439 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
440 if (loc->sgpr_idx == -1)
441 return;
442 assert(loc->num_sgprs == 2);
443 assert(!loc->indirect);
444 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
445 radeon_emit(cmd_buffer->cs, va);
446 radeon_emit(cmd_buffer->cs, va >> 32);
447 }
448
449 static void
450 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
451 struct radv_pipeline *pipeline)
452 {
453 int num_samples = pipeline->graphics.ms.num_samples;
454 struct radv_multisample_state *ms = &pipeline->graphics.ms;
455 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
456
457 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
458 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
459 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
460
461 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
462 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
463
464 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
465 return;
466
467 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
468 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
469 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
470
471 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
472
473 /* GFX9: Flush DFSM when the AA mode changes. */
474 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
475 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
476 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
477 }
478 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
479 uint32_t offset;
480 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
481 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
482 if (loc->sgpr_idx == -1)
483 return;
484 assert(loc->num_sgprs == 1);
485 assert(!loc->indirect);
486 switch (num_samples) {
487 default:
488 offset = 0;
489 break;
490 case 2:
491 offset = 1;
492 break;
493 case 4:
494 offset = 3;
495 break;
496 case 8:
497 offset = 7;
498 break;
499 case 16:
500 offset = 15;
501 break;
502 }
503
504 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
505 cmd_buffer->sample_positions_needed = true;
506 }
507 }
508
509 static void
510 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
511 struct radv_pipeline *pipeline)
512 {
513 struct radv_raster_state *raster = &pipeline->graphics.raster;
514
515 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
516 raster->pa_cl_clip_cntl);
517
518 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
519 raster->spi_interp_control);
520
521 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
522 unsigned tmp = (unsigned)(1.0 * 8.0);
523 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
524 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
525 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
526
527 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
528 raster->pa_su_vtx_cntl);
529
530 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
531 raster->pa_su_sc_mode_cntl);
532 }
533
534 static inline void
535 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
536 unsigned size)
537 {
538 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
539 si_cp_dma_prefetch(cmd_buffer, va, size);
540 }
541
542 static void
543 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
544 struct radv_pipeline *pipeline,
545 struct radv_shader_variant *shader,
546 struct ac_vs_output_info *outinfo)
547 {
548 struct radeon_winsys *ws = cmd_buffer->device->ws;
549 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
550 unsigned export_count;
551
552 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
553 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
554
555 export_count = MAX2(1, outinfo->param_exports);
556 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
557 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
558
559 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
560 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
561 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
562 V_02870C_SPI_SHADER_4COMP :
563 V_02870C_SPI_SHADER_NONE) |
564 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
565 V_02870C_SPI_SHADER_4COMP :
566 V_02870C_SPI_SHADER_NONE) |
567 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
568 V_02870C_SPI_SHADER_4COMP :
569 V_02870C_SPI_SHADER_NONE));
570
571
572 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
573 radeon_emit(cmd_buffer->cs, va >> 8);
574 radeon_emit(cmd_buffer->cs, va >> 40);
575 radeon_emit(cmd_buffer->cs, shader->rsrc1);
576 radeon_emit(cmd_buffer->cs, shader->rsrc2);
577
578 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
579 S_028818_VTX_W0_FMT(1) |
580 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
581 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
582 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
583
584
585 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
586 pipeline->graphics.pa_cl_vs_out_cntl);
587
588 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
589 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
590 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
591 }
592
593 static void
594 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
595 struct radv_shader_variant *shader,
596 struct ac_es_output_info *outinfo)
597 {
598 struct radeon_winsys *ws = cmd_buffer->device->ws;
599 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
600
601 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
602 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
603
604 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
605 outinfo->esgs_itemsize / 4);
606 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
607 radeon_emit(cmd_buffer->cs, va >> 8);
608 radeon_emit(cmd_buffer->cs, va >> 40);
609 radeon_emit(cmd_buffer->cs, shader->rsrc1);
610 radeon_emit(cmd_buffer->cs, shader->rsrc2);
611 }
612
613 static void
614 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
615 struct radv_shader_variant *shader)
616 {
617 struct radeon_winsys *ws = cmd_buffer->device->ws;
618 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
619 uint32_t rsrc2 = shader->rsrc2;
620
621 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
622 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
623
624 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
625 radeon_emit(cmd_buffer->cs, va >> 8);
626 radeon_emit(cmd_buffer->cs, va >> 40);
627
628 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
629 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
630 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
631 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
632
633 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
634 radeon_emit(cmd_buffer->cs, shader->rsrc1);
635 radeon_emit(cmd_buffer->cs, rsrc2);
636 }
637
638 static void
639 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
640 struct radv_shader_variant *shader)
641 {
642 struct radeon_winsys *ws = cmd_buffer->device->ws;
643 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
644
645 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
646 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
647
648 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
649 radeon_emit(cmd_buffer->cs, va >> 8);
650 radeon_emit(cmd_buffer->cs, va >> 40);
651 radeon_emit(cmd_buffer->cs, shader->rsrc1);
652 radeon_emit(cmd_buffer->cs, shader->rsrc2);
653 }
654
655 static void
656 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
657 struct radv_pipeline *pipeline)
658 {
659 struct radv_shader_variant *vs;
660
661 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
662
663 vs = pipeline->shaders[MESA_SHADER_VERTEX];
664
665 if (vs->info.vs.as_ls)
666 radv_emit_hw_ls(cmd_buffer, vs);
667 else if (vs->info.vs.as_es)
668 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
669 else
670 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
671
672 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
673 }
674
675
676 static void
677 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
678 struct radv_pipeline *pipeline)
679 {
680 if (!radv_pipeline_has_tess(pipeline))
681 return;
682
683 struct radv_shader_variant *tes, *tcs;
684
685 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
686 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
687
688 if (tes->info.tes.as_es)
689 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
690 else
691 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
692
693 radv_emit_hw_hs(cmd_buffer, tcs);
694
695 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
696 pipeline->graphics.tess.tf_param);
697
698 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
699 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
700 pipeline->graphics.tess.ls_hs_config);
701 else
702 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
703 pipeline->graphics.tess.ls_hs_config);
704
705 struct ac_userdata_info *loc;
706
707 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
708 if (loc->sgpr_idx != -1) {
709 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
710 assert(loc->num_sgprs == 4);
711 assert(!loc->indirect);
712 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
713 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
714 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
715 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
716 pipeline->graphics.tess.num_tcs_input_cp << 26);
717 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
718 }
719
720 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
721 if (loc->sgpr_idx != -1) {
722 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
723 assert(loc->num_sgprs == 1);
724 assert(!loc->indirect);
725
726 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
727 pipeline->graphics.tess.offchip_layout);
728 }
729
730 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
731 if (loc->sgpr_idx != -1) {
732 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
733 assert(loc->num_sgprs == 1);
734 assert(!loc->indirect);
735
736 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
737 pipeline->graphics.tess.tcs_in_layout);
738 }
739 }
740
741 static void
742 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
743 struct radv_pipeline *pipeline)
744 {
745 struct radeon_winsys *ws = cmd_buffer->device->ws;
746 struct radv_shader_variant *gs;
747 uint64_t va;
748
749 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
750
751 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
752 if (!gs)
753 return;
754
755 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
756
757 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
758 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
759 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
760 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
761
762 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
763
764 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
765
766 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
767 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
768 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
769 radeon_emit(cmd_buffer->cs, 0);
770 radeon_emit(cmd_buffer->cs, 0);
771 radeon_emit(cmd_buffer->cs, 0);
772
773 uint32_t gs_num_invocations = gs->info.gs.invocations;
774 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
775 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
776 S_028B90_ENABLE(gs_num_invocations > 0));
777
778 va = ws->buffer_get_va(gs->bo) + gs->bo_offset;
779 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
780 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
781
782 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
783 radeon_emit(cmd_buffer->cs, va >> 8);
784 radeon_emit(cmd_buffer->cs, va >> 40);
785 radeon_emit(cmd_buffer->cs, gs->rsrc1);
786 radeon_emit(cmd_buffer->cs, gs->rsrc2);
787
788 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
789
790 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
791 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
792 if (loc->sgpr_idx != -1) {
793 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
794 uint32_t num_entries = 64;
795 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
796
797 if (is_vi)
798 num_entries *= stride;
799
800 stride = S_008F04_STRIDE(stride);
801 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
802 radeon_emit(cmd_buffer->cs, stride);
803 radeon_emit(cmd_buffer->cs, num_entries);
804 }
805 }
806
807 static void
808 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
809 struct radv_pipeline *pipeline)
810 {
811 struct radeon_winsys *ws = cmd_buffer->device->ws;
812 struct radv_shader_variant *ps;
813 uint64_t va;
814 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
815 struct radv_blend_state *blend = &pipeline->graphics.blend;
816 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
817
818 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
819 va = ws->buffer_get_va(ps->bo) + ps->bo_offset;
820 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
821 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
822
823 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
824 radeon_emit(cmd_buffer->cs, va >> 8);
825 radeon_emit(cmd_buffer->cs, va >> 40);
826 radeon_emit(cmd_buffer->cs, ps->rsrc1);
827 radeon_emit(cmd_buffer->cs, ps->rsrc2);
828
829 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
830 pipeline->graphics.db_shader_control);
831
832 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
833 ps->config.spi_ps_input_ena);
834
835 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
836 ps->config.spi_ps_input_addr);
837
838 if (ps->info.info.ps.force_persample)
839 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
840
841 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
842 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
843
844 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
845
846 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
847 pipeline->graphics.shader_z_format);
848
849 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
850
851 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
852 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
853
854 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
855 /* optimise this? */
856 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
857 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
858 }
859
860 if (pipeline->graphics.ps_input_cntl_num) {
861 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
862 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
863 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
864 }
865 }
866 }
867
868 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
869 struct radv_pipeline *pipeline)
870 {
871 uint32_t vtx_reuse_depth = 30;
872 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
873 return;
874
875 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
876 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
877 vtx_reuse_depth = 14;
878 }
879 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
880 vtx_reuse_depth);
881 }
882
883 static void
884 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
885 struct radv_pipeline *pipeline)
886 {
887 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
888 return;
889
890 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
891 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
892 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
893 radv_update_multisample_state(cmd_buffer, pipeline);
894 radv_emit_vertex_shader(cmd_buffer, pipeline);
895 radv_emit_tess_shaders(cmd_buffer, pipeline);
896 radv_emit_geometry_shader(cmd_buffer, pipeline);
897 radv_emit_fragment_shader(cmd_buffer, pipeline);
898 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
899
900 cmd_buffer->scratch_size_needed =
901 MAX2(cmd_buffer->scratch_size_needed,
902 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
903
904 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
905 S_0286E8_WAVES(pipeline->max_waves) |
906 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
907
908 if (!cmd_buffer->state.emitted_pipeline ||
909 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
910 pipeline->graphics.can_use_guardband)
911 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
912
913 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
914
915 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
916 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
917 } else {
918 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
919 }
920 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
921
922 cmd_buffer->state.emitted_pipeline = pipeline;
923 }
924
925 static void
926 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
927 {
928 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
929 cmd_buffer->state.dynamic.viewport.viewports);
930 }
931
932 static void
933 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
934 {
935 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
936 si_write_scissors(cmd_buffer->cs, 0, count,
937 cmd_buffer->state.dynamic.scissor.scissors,
938 cmd_buffer->state.dynamic.viewport.viewports,
939 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
940 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
941 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
942 }
943
944 static void
945 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
946 int index,
947 struct radv_color_buffer_info *cb)
948 {
949 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
950
951 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
952 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
953 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
954 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
955 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
956 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
957 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
958 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
959 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
960 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
961 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
962 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
963 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
964
965 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
966 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
967 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
968
969 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
970 cb->gfx9_epitch);
971 } else {
972 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
973 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
974 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
975 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
976 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
977 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
978 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
979 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
980 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
981 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
982 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
983 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
984
985 if (is_vi) { /* DCC BASE */
986 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
987 }
988 }
989 }
990
991 static void
992 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
993 struct radv_ds_buffer_info *ds,
994 struct radv_image *image,
995 VkImageLayout layout)
996 {
997 uint32_t db_z_info = ds->db_z_info;
998 uint32_t db_stencil_info = ds->db_stencil_info;
999
1000 if (!radv_layout_has_htile(image, layout,
1001 radv_image_queue_family_mask(image,
1002 cmd_buffer->queue_family_index,
1003 cmd_buffer->queue_family_index))) {
1004 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1005 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1006 }
1007
1008 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1009 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1010
1011
1012 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1013 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1014 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1015 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1016 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1017
1018 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1019 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1020 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1021 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1022 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1023 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1024 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1025 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1026 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1027 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1028 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1029
1030 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1031 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1032 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1033 } else {
1034 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1035
1036 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1037 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1038 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1039 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1040 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1041 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1042 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1043 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1044 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1045 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1046
1047 }
1048
1049 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1050 ds->pa_su_poly_offset_db_fmt_cntl);
1051 }
1052
1053 void
1054 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1055 struct radv_image *image,
1056 VkClearDepthStencilValue ds_clear_value,
1057 VkImageAspectFlags aspects)
1058 {
1059 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1060 va += image->offset + image->clear_value_offset;
1061 unsigned reg_offset = 0, reg_count = 0;
1062
1063 if (!image->surface.htile_size || !aspects)
1064 return;
1065
1066 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1067 ++reg_count;
1068 } else {
1069 ++reg_offset;
1070 va += 4;
1071 }
1072 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1073 ++reg_count;
1074
1075 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1076
1077 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1078 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1079 S_370_WR_CONFIRM(1) |
1080 S_370_ENGINE_SEL(V_370_PFP));
1081 radeon_emit(cmd_buffer->cs, va);
1082 radeon_emit(cmd_buffer->cs, va >> 32);
1083 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1084 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1085 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1086 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1087
1088 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1089 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1090 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1091 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1092 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1093 }
1094
1095 static void
1096 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1097 struct radv_image *image)
1098 {
1099 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1100 va += image->offset + image->clear_value_offset;
1101
1102 if (!image->surface.htile_size)
1103 return;
1104
1105 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1106
1107 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1108 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1109 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1110 COPY_DATA_COUNT_SEL);
1111 radeon_emit(cmd_buffer->cs, va);
1112 radeon_emit(cmd_buffer->cs, va >> 32);
1113 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1114 radeon_emit(cmd_buffer->cs, 0);
1115
1116 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1117 radeon_emit(cmd_buffer->cs, 0);
1118 }
1119
1120 /*
1121 *with DCC some colors don't require CMASK elimiation before being
1122 * used as a texture. This sets a predicate value to determine if the
1123 * cmask eliminate is required.
1124 */
1125 void
1126 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1127 struct radv_image *image,
1128 bool value)
1129 {
1130 uint64_t pred_val = value;
1131 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1132 va += image->offset + image->dcc_pred_offset;
1133
1134 if (!image->surface.dcc_size)
1135 return;
1136
1137 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1138
1139 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1140 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1141 S_370_WR_CONFIRM(1) |
1142 S_370_ENGINE_SEL(V_370_PFP));
1143 radeon_emit(cmd_buffer->cs, va);
1144 radeon_emit(cmd_buffer->cs, va >> 32);
1145 radeon_emit(cmd_buffer->cs, pred_val);
1146 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1147 }
1148
1149 void
1150 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1151 struct radv_image *image,
1152 int idx,
1153 uint32_t color_values[2])
1154 {
1155 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1156 va += image->offset + image->clear_value_offset;
1157
1158 if (!image->cmask.size && !image->surface.dcc_size)
1159 return;
1160
1161 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1162
1163 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1164 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1165 S_370_WR_CONFIRM(1) |
1166 S_370_ENGINE_SEL(V_370_PFP));
1167 radeon_emit(cmd_buffer->cs, va);
1168 radeon_emit(cmd_buffer->cs, va >> 32);
1169 radeon_emit(cmd_buffer->cs, color_values[0]);
1170 radeon_emit(cmd_buffer->cs, color_values[1]);
1171
1172 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1173 radeon_emit(cmd_buffer->cs, color_values[0]);
1174 radeon_emit(cmd_buffer->cs, color_values[1]);
1175 }
1176
1177 static void
1178 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1179 struct radv_image *image,
1180 int idx)
1181 {
1182 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1183 va += image->offset + image->clear_value_offset;
1184
1185 if (!image->cmask.size && !image->surface.dcc_size)
1186 return;
1187
1188 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1189 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1190
1191 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1192 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1193 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1194 COPY_DATA_COUNT_SEL);
1195 radeon_emit(cmd_buffer->cs, va);
1196 radeon_emit(cmd_buffer->cs, va >> 32);
1197 radeon_emit(cmd_buffer->cs, reg >> 2);
1198 radeon_emit(cmd_buffer->cs, 0);
1199
1200 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1201 radeon_emit(cmd_buffer->cs, 0);
1202 }
1203
1204 void
1205 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1206 {
1207 int i;
1208 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1209 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1210
1211 for (i = 0; i < 8; ++i) {
1212 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1213 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1214 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1215 continue;
1216 }
1217
1218 int idx = subpass->color_attachments[i].attachment;
1219 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1220
1221 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1222
1223 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1224 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1225
1226 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1227 }
1228
1229 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1230 int idx = subpass->depth_stencil_attachment.attachment;
1231 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1232 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1233 struct radv_image *image = att->attachment->image;
1234 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1235 uint32_t queue_mask = radv_image_queue_family_mask(image,
1236 cmd_buffer->queue_family_index,
1237 cmd_buffer->queue_family_index);
1238 /* We currently don't support writing decompressed HTILE */
1239 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1240 radv_layout_is_htile_compressed(image, layout, queue_mask));
1241
1242 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1243
1244 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1245 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1246 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1247 }
1248 radv_load_depth_clear_regs(cmd_buffer, image);
1249 } else {
1250 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1251 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1252 else
1253 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1254
1255 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1256 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1257 }
1258 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1259 S_028208_BR_X(framebuffer->width) |
1260 S_028208_BR_Y(framebuffer->height));
1261
1262 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1263 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1264 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1265 }
1266 }
1267
1268 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1269 {
1270 uint32_t db_count_control;
1271
1272 if(!cmd_buffer->state.active_occlusion_queries) {
1273 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1274 db_count_control = 0;
1275 } else {
1276 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1277 }
1278 } else {
1279 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1280 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1281 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1282 S_028004_ZPASS_ENABLE(1) |
1283 S_028004_SLICE_EVEN_ENABLE(1) |
1284 S_028004_SLICE_ODD_ENABLE(1);
1285 } else {
1286 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1287 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1288 }
1289 }
1290
1291 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1292 }
1293
1294 static void
1295 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1296 {
1297 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1298
1299 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1300 return;
1301
1302 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1303 radv_emit_viewport(cmd_buffer);
1304
1305 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1306 radv_emit_scissor(cmd_buffer);
1307
1308 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1309 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1310 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1311 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1312 }
1313
1314 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1315 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1316 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1317 }
1318
1319 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1320 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1321 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1322 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1323 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1324 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1325 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1326 S_028430_STENCILOPVAL(1));
1327 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1328 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1329 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1330 S_028434_STENCILOPVAL_BF(1));
1331 }
1332
1333 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1334 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1335 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1336 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1337 }
1338
1339 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1340 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1341 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1342 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1343 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1344
1345 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1346 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1347 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1348 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1349 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1350 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1351 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1352 }
1353 }
1354
1355 cmd_buffer->state.dirty = 0;
1356 }
1357
1358 static void
1359 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1360 struct radv_pipeline *pipeline,
1361 int idx,
1362 uint64_t va,
1363 gl_shader_stage stage)
1364 {
1365 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1366 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1367
1368 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1369 return;
1370
1371 assert(!desc_set_loc->indirect);
1372 assert(desc_set_loc->num_sgprs == 2);
1373 radeon_set_sh_reg_seq(cmd_buffer->cs,
1374 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1375 radeon_emit(cmd_buffer->cs, va);
1376 radeon_emit(cmd_buffer->cs, va >> 32);
1377 }
1378
1379 static void
1380 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1381 VkShaderStageFlags stages,
1382 struct radv_descriptor_set *set,
1383 unsigned idx)
1384 {
1385 if (cmd_buffer->state.pipeline) {
1386 radv_foreach_stage(stage, stages) {
1387 if (cmd_buffer->state.pipeline->shaders[stage])
1388 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1389 idx, set->va,
1390 stage);
1391 }
1392 }
1393
1394 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1395 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1396 idx, set->va,
1397 MESA_SHADER_COMPUTE);
1398 }
1399
1400 static void
1401 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1402 {
1403 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1404 uint32_t *ptr = NULL;
1405 unsigned bo_offset;
1406
1407 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1408 &bo_offset,
1409 (void**) &ptr))
1410 return;
1411
1412 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1413 set->va += bo_offset;
1414
1415 memcpy(ptr, set->mapped_ptr, set->size);
1416 }
1417
1418 static void
1419 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1420 {
1421 uint32_t size = MAX_SETS * 2 * 4;
1422 uint32_t offset;
1423 void *ptr;
1424
1425 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1426 256, &offset, &ptr))
1427 return;
1428
1429 for (unsigned i = 0; i < MAX_SETS; i++) {
1430 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1431 uint64_t set_va = 0;
1432 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1433 if (set)
1434 set_va = set->va;
1435 uptr[0] = set_va & 0xffffffff;
1436 uptr[1] = set_va >> 32;
1437 }
1438
1439 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1440 va += offset;
1441
1442 if (cmd_buffer->state.pipeline) {
1443 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1444 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1445 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1446
1447 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1448 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1449 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1450
1451 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1452 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1453 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1454
1455 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1456 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1457 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1458
1459 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1460 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1461 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1462 }
1463
1464 if (cmd_buffer->state.compute_pipeline)
1465 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1466 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1467 }
1468
1469 static void
1470 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1471 VkShaderStageFlags stages)
1472 {
1473 unsigned i;
1474
1475 if (!cmd_buffer->state.descriptors_dirty)
1476 return;
1477
1478 if (cmd_buffer->state.push_descriptors_dirty)
1479 radv_flush_push_descriptors(cmd_buffer);
1480
1481 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1482 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1483 radv_flush_indirect_descriptor_sets(cmd_buffer);
1484 }
1485
1486 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1487 cmd_buffer->cs,
1488 MAX_SETS * MESA_SHADER_STAGES * 4);
1489
1490 for (i = 0; i < MAX_SETS; i++) {
1491 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1492 continue;
1493 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1494 if (!set)
1495 continue;
1496
1497 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1498 }
1499 cmd_buffer->state.descriptors_dirty = 0;
1500 cmd_buffer->state.push_descriptors_dirty = false;
1501 assert(cmd_buffer->cs->cdw <= cdw_max);
1502 }
1503
1504 static void
1505 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1506 struct radv_pipeline *pipeline,
1507 VkShaderStageFlags stages)
1508 {
1509 struct radv_pipeline_layout *layout = pipeline->layout;
1510 unsigned offset;
1511 void *ptr;
1512 uint64_t va;
1513
1514 stages &= cmd_buffer->push_constant_stages;
1515 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1516 return;
1517
1518 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1519 16 * layout->dynamic_offset_count,
1520 256, &offset, &ptr))
1521 return;
1522
1523 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1524 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1525 16 * layout->dynamic_offset_count);
1526
1527 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1528 va += offset;
1529
1530 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1531 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1532
1533 radv_foreach_stage(stage, stages) {
1534 if (pipeline->shaders[stage]) {
1535 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1536 AC_UD_PUSH_CONSTANTS, va);
1537 }
1538 }
1539
1540 cmd_buffer->push_constant_stages &= ~stages;
1541 assert(cmd_buffer->cs->cdw <= cdw_max);
1542 }
1543
1544 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1545 bool indexed_draw)
1546 {
1547 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1548
1549 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1550 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1551 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1552 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1553 primitive_reset_en);
1554 } else {
1555 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1556 primitive_reset_en);
1557 }
1558 }
1559
1560 if (primitive_reset_en) {
1561 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1562
1563 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1564 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1565 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1566 primitive_reset_index);
1567 }
1568 }
1569 }
1570
1571 static void
1572 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1573 {
1574 struct radv_device *device = cmd_buffer->device;
1575
1576 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1577 cmd_buffer->state.pipeline->num_vertex_attribs &&
1578 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1579 unsigned vb_offset;
1580 void *vb_ptr;
1581 uint32_t i = 0;
1582 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1583 uint64_t va;
1584
1585 /* allocate some descriptor state for vertex buffers */
1586 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1587 &vb_offset, &vb_ptr);
1588
1589 for (i = 0; i < num_attribs; i++) {
1590 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1591 uint32_t offset;
1592 int vb = cmd_buffer->state.pipeline->va_binding[i];
1593 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1594 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1595
1596 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1597 va = device->ws->buffer_get_va(buffer->bo);
1598
1599 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1600 va += offset + buffer->offset;
1601 desc[0] = va;
1602 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1603 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1604 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1605 else
1606 desc[2] = buffer->size - offset;
1607 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1608 }
1609
1610 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1611 va += vb_offset;
1612
1613 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1614 AC_UD_VS_VERTEX_BUFFERS, va);
1615 }
1616 cmd_buffer->state.vb_dirty = 0;
1617 }
1618
1619 static void
1620 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1621 bool indexed_draw, bool instanced_draw,
1622 bool indirect_draw,
1623 uint32_t draw_vertex_count)
1624 {
1625 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1626 uint32_t ia_multi_vgt_param;
1627
1628 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1629 cmd_buffer->cs, 4096);
1630
1631 radv_cmd_buffer_update_vertex_descriptors(cmd_buffer);
1632
1633 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1634 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1635
1636 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1637 radv_emit_framebuffer_state(cmd_buffer);
1638
1639 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1640 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1641 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1642 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1643 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1644 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1645 else
1646 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1647 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1648 }
1649
1650 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1651
1652 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1653
1654 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1655 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1656 VK_SHADER_STAGE_ALL_GRAPHICS);
1657
1658 assert(cmd_buffer->cs->cdw <= cdw_max);
1659
1660 si_emit_cache_flush(cmd_buffer);
1661 }
1662
1663 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1664 VkPipelineStageFlags src_stage_mask)
1665 {
1666 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1667 VK_PIPELINE_STAGE_TRANSFER_BIT |
1668 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1669 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1670 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1671 }
1672
1673 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1674 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1675 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1676 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1677 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1678 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1679 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1680 VK_PIPELINE_STAGE_TRANSFER_BIT |
1681 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1682 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1683 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1684 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1685 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1686 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1687 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1688 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1689 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1690 }
1691 }
1692
1693 static enum radv_cmd_flush_bits
1694 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1695 VkAccessFlags src_flags)
1696 {
1697 enum radv_cmd_flush_bits flush_bits = 0;
1698 uint32_t b;
1699 for_each_bit(b, src_flags) {
1700 switch ((VkAccessFlagBits)(1 << b)) {
1701 case VK_ACCESS_SHADER_WRITE_BIT:
1702 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1703 break;
1704 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1705 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1706 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1707 break;
1708 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1709 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1710 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1711 break;
1712 case VK_ACCESS_TRANSFER_WRITE_BIT:
1713 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1714 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1715 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1716 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1717 RADV_CMD_FLAG_INV_GLOBAL_L2;
1718 break;
1719 default:
1720 break;
1721 }
1722 }
1723 return flush_bits;
1724 }
1725
1726 static enum radv_cmd_flush_bits
1727 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1728 VkAccessFlags dst_flags,
1729 struct radv_image *image)
1730 {
1731 enum radv_cmd_flush_bits flush_bits = 0;
1732 uint32_t b;
1733 for_each_bit(b, dst_flags) {
1734 switch ((VkAccessFlagBits)(1 << b)) {
1735 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1736 case VK_ACCESS_INDEX_READ_BIT:
1737 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1738 break;
1739 case VK_ACCESS_UNIFORM_READ_BIT:
1740 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1741 break;
1742 case VK_ACCESS_SHADER_READ_BIT:
1743 case VK_ACCESS_TRANSFER_READ_BIT:
1744 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1745 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1746 RADV_CMD_FLAG_INV_GLOBAL_L2;
1747 break;
1748 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1749 /* TODO: change to image && when the image gets passed
1750 * through from the subpass. */
1751 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1752 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1753 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1754 break;
1755 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1756 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1757 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1758 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1759 break;
1760 default:
1761 break;
1762 }
1763 }
1764 return flush_bits;
1765 }
1766
1767 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1768 {
1769 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1770 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1771 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1772 NULL);
1773 }
1774
1775 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1776 VkAttachmentReference att)
1777 {
1778 unsigned idx = att.attachment;
1779 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1780 VkImageSubresourceRange range;
1781 range.aspectMask = 0;
1782 range.baseMipLevel = view->base_mip;
1783 range.levelCount = 1;
1784 range.baseArrayLayer = view->base_layer;
1785 range.layerCount = cmd_buffer->state.framebuffer->layers;
1786
1787 radv_handle_image_transition(cmd_buffer,
1788 view->image,
1789 cmd_buffer->state.attachments[idx].current_layout,
1790 att.layout, 0, 0, &range,
1791 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1792
1793 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1794
1795
1796 }
1797
1798 void
1799 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1800 const struct radv_subpass *subpass, bool transitions)
1801 {
1802 if (transitions) {
1803 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1804
1805 for (unsigned i = 0; i < subpass->color_count; ++i) {
1806 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1807 radv_handle_subpass_image_transition(cmd_buffer,
1808 subpass->color_attachments[i]);
1809 }
1810
1811 for (unsigned i = 0; i < subpass->input_count; ++i) {
1812 radv_handle_subpass_image_transition(cmd_buffer,
1813 subpass->input_attachments[i]);
1814 }
1815
1816 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1817 radv_handle_subpass_image_transition(cmd_buffer,
1818 subpass->depth_stencil_attachment);
1819 }
1820 }
1821
1822 cmd_buffer->state.subpass = subpass;
1823
1824 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1825 }
1826
1827 static void
1828 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1829 struct radv_render_pass *pass,
1830 const VkRenderPassBeginInfo *info)
1831 {
1832 struct radv_cmd_state *state = &cmd_buffer->state;
1833
1834 if (pass->attachment_count == 0) {
1835 state->attachments = NULL;
1836 return;
1837 }
1838
1839 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1840 pass->attachment_count *
1841 sizeof(state->attachments[0]),
1842 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1843 if (state->attachments == NULL) {
1844 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1845 abort();
1846 }
1847
1848 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1849 struct radv_render_pass_attachment *att = &pass->attachments[i];
1850 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1851 VkImageAspectFlags clear_aspects = 0;
1852
1853 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1854 /* color attachment */
1855 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1856 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1857 }
1858 } else {
1859 /* depthstencil attachment */
1860 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1861 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1862 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1863 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1864 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1865 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1866 }
1867 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1868 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1869 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1870 }
1871 }
1872
1873 state->attachments[i].pending_clear_aspects = clear_aspects;
1874 if (clear_aspects && info) {
1875 assert(info->clearValueCount > i);
1876 state->attachments[i].clear_value = info->pClearValues[i];
1877 }
1878
1879 state->attachments[i].current_layout = att->initial_layout;
1880 }
1881 }
1882
1883 VkResult radv_AllocateCommandBuffers(
1884 VkDevice _device,
1885 const VkCommandBufferAllocateInfo *pAllocateInfo,
1886 VkCommandBuffer *pCommandBuffers)
1887 {
1888 RADV_FROM_HANDLE(radv_device, device, _device);
1889 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1890
1891 VkResult result = VK_SUCCESS;
1892 uint32_t i;
1893
1894 memset(pCommandBuffers, 0,
1895 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1896
1897 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1898
1899 if (!list_empty(&pool->free_cmd_buffers)) {
1900 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1901
1902 list_del(&cmd_buffer->pool_link);
1903 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1904
1905 radv_reset_cmd_buffer(cmd_buffer);
1906 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1907 cmd_buffer->level = pAllocateInfo->level;
1908
1909 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1910 result = VK_SUCCESS;
1911 } else {
1912 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1913 &pCommandBuffers[i]);
1914 }
1915 if (result != VK_SUCCESS)
1916 break;
1917 }
1918
1919 if (result != VK_SUCCESS)
1920 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1921 i, pCommandBuffers);
1922
1923 return result;
1924 }
1925
1926 void radv_FreeCommandBuffers(
1927 VkDevice device,
1928 VkCommandPool commandPool,
1929 uint32_t commandBufferCount,
1930 const VkCommandBuffer *pCommandBuffers)
1931 {
1932 for (uint32_t i = 0; i < commandBufferCount; i++) {
1933 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1934
1935 if (cmd_buffer) {
1936 if (cmd_buffer->pool) {
1937 list_del(&cmd_buffer->pool_link);
1938 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1939 } else
1940 radv_cmd_buffer_destroy(cmd_buffer);
1941
1942 }
1943 }
1944 }
1945
1946 VkResult radv_ResetCommandBuffer(
1947 VkCommandBuffer commandBuffer,
1948 VkCommandBufferResetFlags flags)
1949 {
1950 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1951 radv_reset_cmd_buffer(cmd_buffer);
1952 return VK_SUCCESS;
1953 }
1954
1955 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1956 {
1957 struct radv_device *device = cmd_buffer->device;
1958 if (device->gfx_init) {
1959 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1960 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1961 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1962 radeon_emit(cmd_buffer->cs, va);
1963 radeon_emit(cmd_buffer->cs, va >> 32);
1964 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1965 } else
1966 si_init_config(cmd_buffer);
1967 }
1968
1969 VkResult radv_BeginCommandBuffer(
1970 VkCommandBuffer commandBuffer,
1971 const VkCommandBufferBeginInfo *pBeginInfo)
1972 {
1973 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1974 radv_reset_cmd_buffer(cmd_buffer);
1975
1976 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1977 cmd_buffer->state.last_primitive_reset_en = -1;
1978
1979 /* setup initial configuration into command buffer */
1980 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1981 switch (cmd_buffer->queue_family_index) {
1982 case RADV_QUEUE_GENERAL:
1983 emit_gfx_buffer_state(cmd_buffer);
1984 radv_set_db_count_control(cmd_buffer);
1985 break;
1986 case RADV_QUEUE_COMPUTE:
1987 si_init_compute(cmd_buffer);
1988 break;
1989 case RADV_QUEUE_TRANSFER:
1990 default:
1991 break;
1992 }
1993 }
1994
1995 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1996 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1997 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1998
1999 struct radv_subpass *subpass =
2000 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2001
2002 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2003 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2004 }
2005
2006 radv_cmd_buffer_trace_emit(cmd_buffer);
2007 return VK_SUCCESS;
2008 }
2009
2010 void radv_CmdBindVertexBuffers(
2011 VkCommandBuffer commandBuffer,
2012 uint32_t firstBinding,
2013 uint32_t bindingCount,
2014 const VkBuffer* pBuffers,
2015 const VkDeviceSize* pOffsets)
2016 {
2017 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2018 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2019
2020 /* We have to defer setting up vertex buffer since we need the buffer
2021 * stride from the pipeline. */
2022
2023 assert(firstBinding + bindingCount < MAX_VBS);
2024 for (uint32_t i = 0; i < bindingCount; i++) {
2025 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2026 vb[firstBinding + i].offset = pOffsets[i];
2027 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
2028 }
2029 }
2030
2031 void radv_CmdBindIndexBuffer(
2032 VkCommandBuffer commandBuffer,
2033 VkBuffer buffer,
2034 VkDeviceSize offset,
2035 VkIndexType indexType)
2036 {
2037 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2038 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2039
2040 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2041 cmd_buffer->state.index_va = cmd_buffer->device->ws->buffer_get_va(index_buffer->bo);
2042 cmd_buffer->state.index_va += index_buffer->offset + offset;
2043
2044 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2045 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2046 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2047 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2048 }
2049
2050
2051 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2052 struct radv_descriptor_set *set,
2053 unsigned idx)
2054 {
2055 struct radeon_winsys *ws = cmd_buffer->device->ws;
2056
2057 cmd_buffer->state.descriptors[idx] = set;
2058 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2059 if (!set)
2060 return;
2061
2062 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2063
2064 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2065 if (set->descriptors[j])
2066 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2067
2068 if(set->bo)
2069 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2070 }
2071
2072 void radv_CmdBindDescriptorSets(
2073 VkCommandBuffer commandBuffer,
2074 VkPipelineBindPoint pipelineBindPoint,
2075 VkPipelineLayout _layout,
2076 uint32_t firstSet,
2077 uint32_t descriptorSetCount,
2078 const VkDescriptorSet* pDescriptorSets,
2079 uint32_t dynamicOffsetCount,
2080 const uint32_t* pDynamicOffsets)
2081 {
2082 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2083 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2084 unsigned dyn_idx = 0;
2085
2086 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2087 unsigned idx = i + firstSet;
2088 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2089 radv_bind_descriptor_set(cmd_buffer, set, idx);
2090
2091 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2092 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2093 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2094 assert(dyn_idx < dynamicOffsetCount);
2095
2096 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2097 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2098 dst[0] = va;
2099 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2100 dst[2] = range->size;
2101 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2102 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2103 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2104 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2105 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2106 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2107 cmd_buffer->push_constant_stages |=
2108 set->layout->dynamic_shader_stages;
2109 }
2110 }
2111 }
2112
2113 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2114 struct radv_descriptor_set *set,
2115 struct radv_descriptor_set_layout *layout)
2116 {
2117 set->size = layout->size;
2118 set->layout = layout;
2119
2120 if (cmd_buffer->push_descriptors.capacity < set->size) {
2121 size_t new_size = MAX2(set->size, 1024);
2122 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2123 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2124
2125 free(set->mapped_ptr);
2126 set->mapped_ptr = malloc(new_size);
2127
2128 if (!set->mapped_ptr) {
2129 cmd_buffer->push_descriptors.capacity = 0;
2130 cmd_buffer->record_fail = true;
2131 return false;
2132 }
2133
2134 cmd_buffer->push_descriptors.capacity = new_size;
2135 }
2136
2137 return true;
2138 }
2139
2140 void radv_meta_push_descriptor_set(
2141 struct radv_cmd_buffer* cmd_buffer,
2142 VkPipelineBindPoint pipelineBindPoint,
2143 VkPipelineLayout _layout,
2144 uint32_t set,
2145 uint32_t descriptorWriteCount,
2146 const VkWriteDescriptorSet* pDescriptorWrites)
2147 {
2148 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2149 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2150 unsigned bo_offset;
2151
2152 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2153
2154 push_set->size = layout->set[set].layout->size;
2155 push_set->layout = layout->set[set].layout;
2156
2157 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2158 &bo_offset,
2159 (void**) &push_set->mapped_ptr))
2160 return;
2161
2162 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2163 push_set->va += bo_offset;
2164
2165 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2166 radv_descriptor_set_to_handle(push_set),
2167 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2168
2169 cmd_buffer->state.descriptors[set] = push_set;
2170 cmd_buffer->state.descriptors_dirty |= (1u << set);
2171 }
2172
2173 void radv_CmdPushDescriptorSetKHR(
2174 VkCommandBuffer commandBuffer,
2175 VkPipelineBindPoint pipelineBindPoint,
2176 VkPipelineLayout _layout,
2177 uint32_t set,
2178 uint32_t descriptorWriteCount,
2179 const VkWriteDescriptorSet* pDescriptorWrites)
2180 {
2181 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2182 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2183 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2184
2185 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2186
2187 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2188 return;
2189
2190 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2191 radv_descriptor_set_to_handle(push_set),
2192 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2193
2194 cmd_buffer->state.descriptors[set] = push_set;
2195 cmd_buffer->state.descriptors_dirty |= (1u << set);
2196 cmd_buffer->state.push_descriptors_dirty = true;
2197 }
2198
2199 void radv_CmdPushDescriptorSetWithTemplateKHR(
2200 VkCommandBuffer commandBuffer,
2201 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2202 VkPipelineLayout _layout,
2203 uint32_t set,
2204 const void* pData)
2205 {
2206 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2207 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2208 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2209
2210 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2211
2212 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2213 return;
2214
2215 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2216 descriptorUpdateTemplate, pData);
2217
2218 cmd_buffer->state.descriptors[set] = push_set;
2219 cmd_buffer->state.descriptors_dirty |= (1u << set);
2220 cmd_buffer->state.push_descriptors_dirty = true;
2221 }
2222
2223 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2224 VkPipelineLayout layout,
2225 VkShaderStageFlags stageFlags,
2226 uint32_t offset,
2227 uint32_t size,
2228 const void* pValues)
2229 {
2230 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2231 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2232 cmd_buffer->push_constant_stages |= stageFlags;
2233 }
2234
2235 VkResult radv_EndCommandBuffer(
2236 VkCommandBuffer commandBuffer)
2237 {
2238 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2239
2240 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2241 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2242 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2243 si_emit_cache_flush(cmd_buffer);
2244 }
2245
2246 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
2247 cmd_buffer->record_fail)
2248 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2249 return VK_SUCCESS;
2250 }
2251
2252 static void
2253 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2254 {
2255 struct radeon_winsys *ws = cmd_buffer->device->ws;
2256 struct radv_shader_variant *compute_shader;
2257 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2258 uint64_t va;
2259
2260 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2261 return;
2262
2263 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2264
2265 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2266 va = ws->buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2267
2268 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2269 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2270
2271 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2272 cmd_buffer->cs, 16);
2273
2274 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2275 radeon_emit(cmd_buffer->cs, va >> 8);
2276 radeon_emit(cmd_buffer->cs, va >> 40);
2277
2278 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2279 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2280 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2281
2282
2283 cmd_buffer->compute_scratch_size_needed =
2284 MAX2(cmd_buffer->compute_scratch_size_needed,
2285 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2286
2287 /* change these once we have scratch support */
2288 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2289 S_00B860_WAVES(pipeline->max_waves) |
2290 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2291
2292 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2293 radeon_emit(cmd_buffer->cs,
2294 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2295 radeon_emit(cmd_buffer->cs,
2296 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2297 radeon_emit(cmd_buffer->cs,
2298 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2299
2300 assert(cmd_buffer->cs->cdw <= cdw_max);
2301 }
2302
2303 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2304 {
2305 for (unsigned i = 0; i < MAX_SETS; i++) {
2306 if (cmd_buffer->state.descriptors[i])
2307 cmd_buffer->state.descriptors_dirty |= (1u << i);
2308 }
2309 }
2310
2311 void radv_CmdBindPipeline(
2312 VkCommandBuffer commandBuffer,
2313 VkPipelineBindPoint pipelineBindPoint,
2314 VkPipeline _pipeline)
2315 {
2316 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2317 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2318
2319 radv_mark_descriptor_sets_dirty(cmd_buffer);
2320
2321 switch (pipelineBindPoint) {
2322 case VK_PIPELINE_BIND_POINT_COMPUTE:
2323 cmd_buffer->state.compute_pipeline = pipeline;
2324 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2325 break;
2326 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2327 cmd_buffer->state.pipeline = pipeline;
2328 if (!pipeline)
2329 break;
2330
2331 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2332 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2333
2334 /* Apply the dynamic state from the pipeline */
2335 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2336 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2337 &pipeline->dynamic_state,
2338 pipeline->dynamic_state_mask);
2339
2340 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2341 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2342 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2343 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2344
2345 if (radv_pipeline_has_tess(pipeline))
2346 cmd_buffer->tess_rings_needed = true;
2347
2348 if (radv_pipeline_has_gs(pipeline)) {
2349 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2350 AC_UD_SCRATCH_RING_OFFSETS);
2351 if (cmd_buffer->ring_offsets_idx == -1)
2352 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2353 else if (loc->sgpr_idx != -1)
2354 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2355 }
2356 break;
2357 default:
2358 assert(!"invalid bind point");
2359 break;
2360 }
2361 }
2362
2363 void radv_CmdSetViewport(
2364 VkCommandBuffer commandBuffer,
2365 uint32_t firstViewport,
2366 uint32_t viewportCount,
2367 const VkViewport* pViewports)
2368 {
2369 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2370
2371 const uint32_t total_count = firstViewport + viewportCount;
2372 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2373 cmd_buffer->state.dynamic.viewport.count = total_count;
2374
2375 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2376 pViewports, viewportCount * sizeof(*pViewports));
2377
2378 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2379 }
2380
2381 void radv_CmdSetScissor(
2382 VkCommandBuffer commandBuffer,
2383 uint32_t firstScissor,
2384 uint32_t scissorCount,
2385 const VkRect2D* pScissors)
2386 {
2387 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2388
2389 const uint32_t total_count = firstScissor + scissorCount;
2390 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2391 cmd_buffer->state.dynamic.scissor.count = total_count;
2392
2393 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2394 pScissors, scissorCount * sizeof(*pScissors));
2395 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2396 }
2397
2398 void radv_CmdSetLineWidth(
2399 VkCommandBuffer commandBuffer,
2400 float lineWidth)
2401 {
2402 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2403 cmd_buffer->state.dynamic.line_width = lineWidth;
2404 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2405 }
2406
2407 void radv_CmdSetDepthBias(
2408 VkCommandBuffer commandBuffer,
2409 float depthBiasConstantFactor,
2410 float depthBiasClamp,
2411 float depthBiasSlopeFactor)
2412 {
2413 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2414
2415 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2416 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2417 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2418
2419 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2420 }
2421
2422 void radv_CmdSetBlendConstants(
2423 VkCommandBuffer commandBuffer,
2424 const float blendConstants[4])
2425 {
2426 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2427
2428 memcpy(cmd_buffer->state.dynamic.blend_constants,
2429 blendConstants, sizeof(float) * 4);
2430
2431 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2432 }
2433
2434 void radv_CmdSetDepthBounds(
2435 VkCommandBuffer commandBuffer,
2436 float minDepthBounds,
2437 float maxDepthBounds)
2438 {
2439 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2440
2441 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2442 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2443
2444 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2445 }
2446
2447 void radv_CmdSetStencilCompareMask(
2448 VkCommandBuffer commandBuffer,
2449 VkStencilFaceFlags faceMask,
2450 uint32_t compareMask)
2451 {
2452 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2453
2454 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2455 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2456 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2457 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2458
2459 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2460 }
2461
2462 void radv_CmdSetStencilWriteMask(
2463 VkCommandBuffer commandBuffer,
2464 VkStencilFaceFlags faceMask,
2465 uint32_t writeMask)
2466 {
2467 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2468
2469 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2470 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2471 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2472 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2473
2474 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2475 }
2476
2477 void radv_CmdSetStencilReference(
2478 VkCommandBuffer commandBuffer,
2479 VkStencilFaceFlags faceMask,
2480 uint32_t reference)
2481 {
2482 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2483
2484 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2485 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2486 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2487 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2488
2489 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2490 }
2491
2492 void radv_CmdExecuteCommands(
2493 VkCommandBuffer commandBuffer,
2494 uint32_t commandBufferCount,
2495 const VkCommandBuffer* pCmdBuffers)
2496 {
2497 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2498
2499 /* Emit pending flushes on primary prior to executing secondary */
2500 si_emit_cache_flush(primary);
2501
2502 for (uint32_t i = 0; i < commandBufferCount; i++) {
2503 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2504
2505 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2506 secondary->scratch_size_needed);
2507 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2508 secondary->compute_scratch_size_needed);
2509
2510 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2511 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2512 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2513 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2514 if (secondary->tess_rings_needed)
2515 primary->tess_rings_needed = true;
2516 if (secondary->sample_positions_needed)
2517 primary->sample_positions_needed = true;
2518
2519 if (secondary->ring_offsets_idx != -1) {
2520 if (primary->ring_offsets_idx == -1)
2521 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2522 else
2523 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2524 }
2525 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2526 }
2527
2528 /* if we execute secondary we need to re-emit out pipelines */
2529 if (commandBufferCount) {
2530 primary->state.emitted_pipeline = NULL;
2531 primary->state.emitted_compute_pipeline = NULL;
2532 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2533 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2534 primary->state.last_primitive_reset_en = -1;
2535 primary->state.last_primitive_reset_index = 0;
2536 radv_mark_descriptor_sets_dirty(primary);
2537 }
2538 }
2539
2540 VkResult radv_CreateCommandPool(
2541 VkDevice _device,
2542 const VkCommandPoolCreateInfo* pCreateInfo,
2543 const VkAllocationCallbacks* pAllocator,
2544 VkCommandPool* pCmdPool)
2545 {
2546 RADV_FROM_HANDLE(radv_device, device, _device);
2547 struct radv_cmd_pool *pool;
2548
2549 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2550 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2551 if (pool == NULL)
2552 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2553
2554 if (pAllocator)
2555 pool->alloc = *pAllocator;
2556 else
2557 pool->alloc = device->alloc;
2558
2559 list_inithead(&pool->cmd_buffers);
2560 list_inithead(&pool->free_cmd_buffers);
2561
2562 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2563
2564 *pCmdPool = radv_cmd_pool_to_handle(pool);
2565
2566 return VK_SUCCESS;
2567
2568 }
2569
2570 void radv_DestroyCommandPool(
2571 VkDevice _device,
2572 VkCommandPool commandPool,
2573 const VkAllocationCallbacks* pAllocator)
2574 {
2575 RADV_FROM_HANDLE(radv_device, device, _device);
2576 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2577
2578 if (!pool)
2579 return;
2580
2581 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2582 &pool->cmd_buffers, pool_link) {
2583 radv_cmd_buffer_destroy(cmd_buffer);
2584 }
2585
2586 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2587 &pool->free_cmd_buffers, pool_link) {
2588 radv_cmd_buffer_destroy(cmd_buffer);
2589 }
2590
2591 vk_free2(&device->alloc, pAllocator, pool);
2592 }
2593
2594 VkResult radv_ResetCommandPool(
2595 VkDevice device,
2596 VkCommandPool commandPool,
2597 VkCommandPoolResetFlags flags)
2598 {
2599 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2600
2601 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2602 &pool->cmd_buffers, pool_link) {
2603 radv_reset_cmd_buffer(cmd_buffer);
2604 }
2605
2606 return VK_SUCCESS;
2607 }
2608
2609 void radv_TrimCommandPoolKHR(
2610 VkDevice device,
2611 VkCommandPool commandPool,
2612 VkCommandPoolTrimFlagsKHR flags)
2613 {
2614 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2615
2616 if (!pool)
2617 return;
2618
2619 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2620 &pool->free_cmd_buffers, pool_link) {
2621 radv_cmd_buffer_destroy(cmd_buffer);
2622 }
2623 }
2624
2625 void radv_CmdBeginRenderPass(
2626 VkCommandBuffer commandBuffer,
2627 const VkRenderPassBeginInfo* pRenderPassBegin,
2628 VkSubpassContents contents)
2629 {
2630 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2631 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2632 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2633
2634 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2635 cmd_buffer->cs, 2048);
2636
2637 cmd_buffer->state.framebuffer = framebuffer;
2638 cmd_buffer->state.pass = pass;
2639 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2640 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2641
2642 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2643 assert(cmd_buffer->cs->cdw <= cdw_max);
2644
2645 radv_cmd_buffer_clear_subpass(cmd_buffer);
2646 }
2647
2648 void radv_CmdNextSubpass(
2649 VkCommandBuffer commandBuffer,
2650 VkSubpassContents contents)
2651 {
2652 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2653
2654 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2655
2656 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2657 2048);
2658
2659 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2660 radv_cmd_buffer_clear_subpass(cmd_buffer);
2661 }
2662
2663 void radv_CmdDraw(
2664 VkCommandBuffer commandBuffer,
2665 uint32_t vertexCount,
2666 uint32_t instanceCount,
2667 uint32_t firstVertex,
2668 uint32_t firstInstance)
2669 {
2670 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2671
2672 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2673
2674 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2675
2676 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2677 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2678 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2679 radeon_emit(cmd_buffer->cs, firstVertex);
2680 radeon_emit(cmd_buffer->cs, firstInstance);
2681 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2682 radeon_emit(cmd_buffer->cs, 0);
2683
2684 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
2685 radeon_emit(cmd_buffer->cs, instanceCount);
2686
2687 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2688 radeon_emit(cmd_buffer->cs, vertexCount);
2689 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2690 S_0287F0_USE_OPAQUE(0));
2691
2692 assert(cmd_buffer->cs->cdw <= cdw_max);
2693
2694 radv_cmd_buffer_trace_emit(cmd_buffer);
2695 }
2696
2697 void radv_CmdDrawIndexed(
2698 VkCommandBuffer commandBuffer,
2699 uint32_t indexCount,
2700 uint32_t instanceCount,
2701 uint32_t firstIndex,
2702 int32_t vertexOffset,
2703 uint32_t firstInstance)
2704 {
2705 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2706 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2707 uint64_t index_va;
2708
2709 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2710
2711 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 16);
2712
2713 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2714 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
2715 2, cmd_buffer->state.index_type);
2716 } else {
2717 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2718 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2719 }
2720
2721 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2722 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2723 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2724 radeon_emit(cmd_buffer->cs, vertexOffset);
2725 radeon_emit(cmd_buffer->cs, firstInstance);
2726 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2727 radeon_emit(cmd_buffer->cs, 0);
2728
2729 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2730 radeon_emit(cmd_buffer->cs, instanceCount);
2731
2732 index_va = cmd_buffer->state.index_va;
2733 index_va += firstIndex * index_size;
2734 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2735 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2736 radeon_emit(cmd_buffer->cs, index_va);
2737 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2738 radeon_emit(cmd_buffer->cs, indexCount);
2739 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2740
2741 assert(cmd_buffer->cs->cdw <= cdw_max);
2742 radv_cmd_buffer_trace_emit(cmd_buffer);
2743 }
2744
2745 static void
2746 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2747 VkBuffer _buffer,
2748 VkDeviceSize offset,
2749 VkBuffer _count_buffer,
2750 VkDeviceSize count_offset,
2751 uint32_t draw_count,
2752 uint32_t stride,
2753 bool indexed)
2754 {
2755 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2756 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2757 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2758 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2759 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2760 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2761 indirect_va += offset + buffer->offset;
2762 uint64_t count_va = 0;
2763
2764 if (count_buffer) {
2765 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2766 count_va += count_offset + count_buffer->offset;
2767 }
2768
2769 if (!draw_count)
2770 return;
2771
2772 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2773 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2774 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2775 assert(base_reg);
2776
2777 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2778 radeon_emit(cs, 1);
2779 radeon_emit(cs, indirect_va);
2780 radeon_emit(cs, indirect_va >> 32);
2781
2782 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2783 PKT3_DRAW_INDIRECT_MULTI,
2784 8, false));
2785 radeon_emit(cs, 0);
2786 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2787 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2788 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2789 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2790 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2791 radeon_emit(cs, draw_count); /* count */
2792 radeon_emit(cs, count_va); /* count_addr */
2793 radeon_emit(cs, count_va >> 32);
2794 radeon_emit(cs, stride); /* stride */
2795 radeon_emit(cs, di_src_sel);
2796 radv_cmd_buffer_trace_emit(cmd_buffer);
2797 }
2798
2799 static void
2800 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2801 VkBuffer buffer,
2802 VkDeviceSize offset,
2803 VkBuffer countBuffer,
2804 VkDeviceSize countBufferOffset,
2805 uint32_t maxDrawCount,
2806 uint32_t stride)
2807 {
2808 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2809 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2810
2811 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2812 cmd_buffer->cs, 14);
2813
2814 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2815 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2816
2817 assert(cmd_buffer->cs->cdw <= cdw_max);
2818 }
2819
2820 static void
2821 radv_cmd_draw_indexed_indirect_count(
2822 VkCommandBuffer commandBuffer,
2823 VkBuffer buffer,
2824 VkDeviceSize offset,
2825 VkBuffer countBuffer,
2826 VkDeviceSize countBufferOffset,
2827 uint32_t maxDrawCount,
2828 uint32_t stride)
2829 {
2830 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2831 uint64_t index_va;
2832 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2833
2834 index_va = cmd_buffer->state.index_va;
2835
2836 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2837
2838 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2839 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2840
2841 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2842 radeon_emit(cmd_buffer->cs, index_va);
2843 radeon_emit(cmd_buffer->cs, index_va >> 32);
2844
2845 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2846 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2847
2848 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2849 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2850
2851 assert(cmd_buffer->cs->cdw <= cdw_max);
2852 }
2853
2854 void radv_CmdDrawIndirect(
2855 VkCommandBuffer commandBuffer,
2856 VkBuffer buffer,
2857 VkDeviceSize offset,
2858 uint32_t drawCount,
2859 uint32_t stride)
2860 {
2861 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2862 VK_NULL_HANDLE, 0, drawCount, stride);
2863 }
2864
2865 void radv_CmdDrawIndexedIndirect(
2866 VkCommandBuffer commandBuffer,
2867 VkBuffer buffer,
2868 VkDeviceSize offset,
2869 uint32_t drawCount,
2870 uint32_t stride)
2871 {
2872 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2873 VK_NULL_HANDLE, 0, drawCount, stride);
2874 }
2875
2876 void radv_CmdDrawIndirectCountAMD(
2877 VkCommandBuffer commandBuffer,
2878 VkBuffer buffer,
2879 VkDeviceSize offset,
2880 VkBuffer countBuffer,
2881 VkDeviceSize countBufferOffset,
2882 uint32_t maxDrawCount,
2883 uint32_t stride)
2884 {
2885 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2886 countBuffer, countBufferOffset,
2887 maxDrawCount, stride);
2888 }
2889
2890 void radv_CmdDrawIndexedIndirectCountAMD(
2891 VkCommandBuffer commandBuffer,
2892 VkBuffer buffer,
2893 VkDeviceSize offset,
2894 VkBuffer countBuffer,
2895 VkDeviceSize countBufferOffset,
2896 uint32_t maxDrawCount,
2897 uint32_t stride)
2898 {
2899 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2900 countBuffer, countBufferOffset,
2901 maxDrawCount, stride);
2902 }
2903
2904 static void
2905 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2906 {
2907 radv_emit_compute_pipeline(cmd_buffer);
2908 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
2909 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2910 VK_SHADER_STAGE_COMPUTE_BIT);
2911 si_emit_cache_flush(cmd_buffer);
2912 }
2913
2914 void radv_CmdDispatch(
2915 VkCommandBuffer commandBuffer,
2916 uint32_t x,
2917 uint32_t y,
2918 uint32_t z)
2919 {
2920 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2921
2922 radv_flush_compute_state(cmd_buffer);
2923
2924 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2925
2926 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2927 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2928 if (loc->sgpr_idx != -1) {
2929 assert(!loc->indirect);
2930 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2931 assert(loc->num_sgprs == grid_used);
2932 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2933 radeon_emit(cmd_buffer->cs, x);
2934 if (grid_used > 1)
2935 radeon_emit(cmd_buffer->cs, y);
2936 if (grid_used > 2)
2937 radeon_emit(cmd_buffer->cs, z);
2938 }
2939
2940 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2941 PKT3_SHADER_TYPE_S(1));
2942 radeon_emit(cmd_buffer->cs, x);
2943 radeon_emit(cmd_buffer->cs, y);
2944 radeon_emit(cmd_buffer->cs, z);
2945 radeon_emit(cmd_buffer->cs, 1);
2946
2947 assert(cmd_buffer->cs->cdw <= cdw_max);
2948 radv_cmd_buffer_trace_emit(cmd_buffer);
2949 }
2950
2951 void radv_CmdDispatchIndirect(
2952 VkCommandBuffer commandBuffer,
2953 VkBuffer _buffer,
2954 VkDeviceSize offset)
2955 {
2956 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2957 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2958 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2959 va += buffer->offset + offset;
2960
2961 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2962
2963 radv_flush_compute_state(cmd_buffer);
2964
2965 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2966 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2967 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2968 if (loc->sgpr_idx != -1) {
2969 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2970 for (unsigned i = 0; i < grid_used; ++i) {
2971 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2972 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2973 COPY_DATA_DST_SEL(COPY_DATA_REG));
2974 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2975 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2976 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2977 radeon_emit(cmd_buffer->cs, 0);
2978 }
2979 }
2980
2981 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2982 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2983 PKT3_SHADER_TYPE_S(1));
2984 radeon_emit(cmd_buffer->cs, va);
2985 radeon_emit(cmd_buffer->cs, va >> 32);
2986 radeon_emit(cmd_buffer->cs, 1);
2987 } else {
2988 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2989 PKT3_SHADER_TYPE_S(1));
2990 radeon_emit(cmd_buffer->cs, 1);
2991 radeon_emit(cmd_buffer->cs, va);
2992 radeon_emit(cmd_buffer->cs, va >> 32);
2993
2994 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2995 PKT3_SHADER_TYPE_S(1));
2996 radeon_emit(cmd_buffer->cs, 0);
2997 radeon_emit(cmd_buffer->cs, 1);
2998 }
2999
3000 assert(cmd_buffer->cs->cdw <= cdw_max);
3001 radv_cmd_buffer_trace_emit(cmd_buffer);
3002 }
3003
3004 void radv_unaligned_dispatch(
3005 struct radv_cmd_buffer *cmd_buffer,
3006 uint32_t x,
3007 uint32_t y,
3008 uint32_t z)
3009 {
3010 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3011 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3012 uint32_t blocks[3], remainder[3];
3013
3014 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
3015 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
3016 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
3017
3018 /* If aligned, these should be an entire block size, not 0 */
3019 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
3020 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
3021 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
3022
3023 radv_flush_compute_state(cmd_buffer);
3024
3025 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
3026
3027 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3028 radeon_emit(cmd_buffer->cs,
3029 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
3030 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3031 radeon_emit(cmd_buffer->cs,
3032 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
3033 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3034 radeon_emit(cmd_buffer->cs,
3035 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
3036 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3037
3038 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3039 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3040 if (loc->sgpr_idx != -1) {
3041 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3042 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
3043 radeon_emit(cmd_buffer->cs, blocks[0]);
3044 if (grid_used > 1)
3045 radeon_emit(cmd_buffer->cs, blocks[1]);
3046 if (grid_used > 2)
3047 radeon_emit(cmd_buffer->cs, blocks[2]);
3048 }
3049 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3050 PKT3_SHADER_TYPE_S(1));
3051 radeon_emit(cmd_buffer->cs, blocks[0]);
3052 radeon_emit(cmd_buffer->cs, blocks[1]);
3053 radeon_emit(cmd_buffer->cs, blocks[2]);
3054 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
3055 S_00B800_PARTIAL_TG_EN(1));
3056
3057 assert(cmd_buffer->cs->cdw <= cdw_max);
3058 radv_cmd_buffer_trace_emit(cmd_buffer);
3059 }
3060
3061 void radv_CmdEndRenderPass(
3062 VkCommandBuffer commandBuffer)
3063 {
3064 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3065
3066 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3067
3068 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3069
3070 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3071 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3072 radv_handle_subpass_image_transition(cmd_buffer,
3073 (VkAttachmentReference){i, layout});
3074 }
3075
3076 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3077
3078 cmd_buffer->state.pass = NULL;
3079 cmd_buffer->state.subpass = NULL;
3080 cmd_buffer->state.attachments = NULL;
3081 cmd_buffer->state.framebuffer = NULL;
3082 }
3083
3084 /*
3085 * For HTILE we have the following interesting clear words:
3086 * 0x0000030f: Uncompressed.
3087 * 0xfffffff0: Clear depth to 1.0
3088 * 0x00000000: Clear depth to 0.0
3089 */
3090 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3091 struct radv_image *image,
3092 const VkImageSubresourceRange *range,
3093 uint32_t clear_word)
3094 {
3095 assert(range->baseMipLevel == 0);
3096 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3097 unsigned layer_count = radv_get_layerCount(image, range);
3098 uint64_t size = image->surface.htile_slice_size * layer_count;
3099 uint64_t offset = image->offset + image->htile_offset +
3100 image->surface.htile_slice_size * range->baseArrayLayer;
3101
3102 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3103 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3104
3105 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3106
3107 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3108 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3109 RADV_CMD_FLAG_INV_VMEM_L1 |
3110 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3111 }
3112
3113 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3114 struct radv_image *image,
3115 VkImageLayout src_layout,
3116 VkImageLayout dst_layout,
3117 unsigned src_queue_mask,
3118 unsigned dst_queue_mask,
3119 const VkImageSubresourceRange *range,
3120 VkImageAspectFlags pending_clears)
3121 {
3122 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3123 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3124 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3125 cmd_buffer->state.render_area.extent.width == image->info.width &&
3126 cmd_buffer->state.render_area.extent.height == image->info.height) {
3127 /* The clear will initialize htile. */
3128 return;
3129 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3130 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3131 /* TODO: merge with the clear if applicable */
3132 radv_initialize_htile(cmd_buffer, image, range, 0);
3133 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3134 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3135 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3136 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3137 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3138 VkImageSubresourceRange local_range = *range;
3139 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3140 local_range.baseMipLevel = 0;
3141 local_range.levelCount = 1;
3142
3143 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3144 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3145
3146 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3147
3148 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3149 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3150 }
3151 }
3152
3153 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3154 struct radv_image *image, uint32_t value)
3155 {
3156 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3157 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3158
3159 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3160 image->cmask.size, value);
3161
3162 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3163 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3164 RADV_CMD_FLAG_INV_VMEM_L1 |
3165 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3166 }
3167
3168 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3169 struct radv_image *image,
3170 VkImageLayout src_layout,
3171 VkImageLayout dst_layout,
3172 unsigned src_queue_mask,
3173 unsigned dst_queue_mask,
3174 const VkImageSubresourceRange *range,
3175 VkImageAspectFlags pending_clears)
3176 {
3177 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3178 if (image->fmask.size)
3179 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3180 else
3181 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3182 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3183 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3184 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3185 }
3186 }
3187
3188 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3189 struct radv_image *image, uint32_t value)
3190 {
3191
3192 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3193 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3194
3195 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3196 image->surface.dcc_size, value);
3197
3198 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3199 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3200 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3201 RADV_CMD_FLAG_INV_VMEM_L1 |
3202 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3203 }
3204
3205 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3206 struct radv_image *image,
3207 VkImageLayout src_layout,
3208 VkImageLayout dst_layout,
3209 unsigned src_queue_mask,
3210 unsigned dst_queue_mask,
3211 const VkImageSubresourceRange *range,
3212 VkImageAspectFlags pending_clears)
3213 {
3214 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3215 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3216 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3217 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3218 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3219 }
3220 }
3221
3222 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3223 struct radv_image *image,
3224 VkImageLayout src_layout,
3225 VkImageLayout dst_layout,
3226 uint32_t src_family,
3227 uint32_t dst_family,
3228 const VkImageSubresourceRange *range,
3229 VkImageAspectFlags pending_clears)
3230 {
3231 if (image->exclusive && src_family != dst_family) {
3232 /* This is an acquire or a release operation and there will be
3233 * a corresponding release/acquire. Do the transition in the
3234 * most flexible queue. */
3235
3236 assert(src_family == cmd_buffer->queue_family_index ||
3237 dst_family == cmd_buffer->queue_family_index);
3238
3239 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3240 return;
3241
3242 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3243 (src_family == RADV_QUEUE_GENERAL ||
3244 dst_family == RADV_QUEUE_GENERAL))
3245 return;
3246 }
3247
3248 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3249 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3250
3251 if (image->surface.htile_size)
3252 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3253 dst_layout, src_queue_mask,
3254 dst_queue_mask, range,
3255 pending_clears);
3256
3257 if (image->cmask.size)
3258 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3259 dst_layout, src_queue_mask,
3260 dst_queue_mask, range,
3261 pending_clears);
3262
3263 if (image->surface.dcc_size)
3264 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3265 dst_layout, src_queue_mask,
3266 dst_queue_mask, range,
3267 pending_clears);
3268 }
3269
3270 void radv_CmdPipelineBarrier(
3271 VkCommandBuffer commandBuffer,
3272 VkPipelineStageFlags srcStageMask,
3273 VkPipelineStageFlags destStageMask,
3274 VkBool32 byRegion,
3275 uint32_t memoryBarrierCount,
3276 const VkMemoryBarrier* pMemoryBarriers,
3277 uint32_t bufferMemoryBarrierCount,
3278 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3279 uint32_t imageMemoryBarrierCount,
3280 const VkImageMemoryBarrier* pImageMemoryBarriers)
3281 {
3282 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3283 enum radv_cmd_flush_bits src_flush_bits = 0;
3284 enum radv_cmd_flush_bits dst_flush_bits = 0;
3285
3286 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3287 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3288 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3289 NULL);
3290 }
3291
3292 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3293 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3294 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3295 NULL);
3296 }
3297
3298 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3299 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3300 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3301 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3302 image);
3303 }
3304
3305 radv_stage_flush(cmd_buffer, srcStageMask);
3306 cmd_buffer->state.flush_bits |= src_flush_bits;
3307
3308 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3309 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3310 radv_handle_image_transition(cmd_buffer, image,
3311 pImageMemoryBarriers[i].oldLayout,
3312 pImageMemoryBarriers[i].newLayout,
3313 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3314 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3315 &pImageMemoryBarriers[i].subresourceRange,
3316 0);
3317 }
3318
3319 cmd_buffer->state.flush_bits |= dst_flush_bits;
3320 }
3321
3322
3323 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3324 struct radv_event *event,
3325 VkPipelineStageFlags stageMask,
3326 unsigned value)
3327 {
3328 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3329 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3330
3331 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3332
3333 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3334
3335 /* TODO: this is overkill. Probably should figure something out from
3336 * the stage mask. */
3337
3338 si_cs_emit_write_event_eop(cs,
3339 cmd_buffer->state.predicating,
3340 cmd_buffer->device->physical_device->rad_info.chip_class,
3341 false,
3342 EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
3343 1, va, 2, value);
3344
3345 assert(cmd_buffer->cs->cdw <= cdw_max);
3346 }
3347
3348 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3349 VkEvent _event,
3350 VkPipelineStageFlags stageMask)
3351 {
3352 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3353 RADV_FROM_HANDLE(radv_event, event, _event);
3354
3355 write_event(cmd_buffer, event, stageMask, 1);
3356 }
3357
3358 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3359 VkEvent _event,
3360 VkPipelineStageFlags stageMask)
3361 {
3362 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3363 RADV_FROM_HANDLE(radv_event, event, _event);
3364
3365 write_event(cmd_buffer, event, stageMask, 0);
3366 }
3367
3368 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3369 uint32_t eventCount,
3370 const VkEvent* pEvents,
3371 VkPipelineStageFlags srcStageMask,
3372 VkPipelineStageFlags dstStageMask,
3373 uint32_t memoryBarrierCount,
3374 const VkMemoryBarrier* pMemoryBarriers,
3375 uint32_t bufferMemoryBarrierCount,
3376 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3377 uint32_t imageMemoryBarrierCount,
3378 const VkImageMemoryBarrier* pImageMemoryBarriers)
3379 {
3380 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3381 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3382
3383 for (unsigned i = 0; i < eventCount; ++i) {
3384 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3385 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3386
3387 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3388
3389 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3390
3391 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3392 assert(cmd_buffer->cs->cdw <= cdw_max);
3393 }
3394
3395
3396 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3397 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3398
3399 radv_handle_image_transition(cmd_buffer, image,
3400 pImageMemoryBarriers[i].oldLayout,
3401 pImageMemoryBarriers[i].newLayout,
3402 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3403 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3404 &pImageMemoryBarriers[i].subresourceRange,
3405 0);
3406 }
3407
3408 /* TODO: figure out how to do memory barriers without waiting */
3409 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3410 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3411 RADV_CMD_FLAG_INV_VMEM_L1 |
3412 RADV_CMD_FLAG_INV_SMEM_L1;
3413 }