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[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 uint32_t src_family,
42 uint32_t dst_family,
43 const VkImageSubresourceRange *range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static void
191 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
192 {
193 list_del(&cmd_buffer->pool_link);
194
195 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
196 &cmd_buffer->upload.list, list) {
197 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
198 list_del(&up->list);
199 free(up);
200 }
201
202 if (cmd_buffer->upload.upload_bo)
203 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
204 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
205 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
206 }
207
208 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
209 {
210
211 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
212
213 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
214 &cmd_buffer->upload.list, list) {
215 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
216 list_del(&up->list);
217 free(up);
218 }
219
220 cmd_buffer->scratch_size_needed = 0;
221 cmd_buffer->compute_scratch_size_needed = 0;
222 cmd_buffer->esgs_ring_size_needed = 0;
223 cmd_buffer->gsvs_ring_size_needed = 0;
224
225 if (cmd_buffer->upload.upload_bo)
226 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
227 cmd_buffer->upload.upload_bo, 8);
228 cmd_buffer->upload.offset = 0;
229
230 cmd_buffer->record_fail = false;
231
232 cmd_buffer->ring_offsets_idx = -1;
233 }
234
235 static bool
236 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
237 uint64_t min_needed)
238 {
239 uint64_t new_size;
240 struct radeon_winsys_bo *bo;
241 struct radv_cmd_buffer_upload *upload;
242 struct radv_device *device = cmd_buffer->device;
243
244 new_size = MAX2(min_needed, 16 * 1024);
245 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
246
247 bo = device->ws->buffer_create(device->ws,
248 new_size, 4096,
249 RADEON_DOMAIN_GTT,
250 RADEON_FLAG_CPU_ACCESS);
251
252 if (!bo) {
253 cmd_buffer->record_fail = true;
254 return false;
255 }
256
257 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
258 if (cmd_buffer->upload.upload_bo) {
259 upload = malloc(sizeof(*upload));
260
261 if (!upload) {
262 cmd_buffer->record_fail = true;
263 device->ws->buffer_destroy(bo);
264 return false;
265 }
266
267 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
268 list_add(&upload->list, &cmd_buffer->upload.list);
269 }
270
271 cmd_buffer->upload.upload_bo = bo;
272 cmd_buffer->upload.size = new_size;
273 cmd_buffer->upload.offset = 0;
274 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
275
276 if (!cmd_buffer->upload.map) {
277 cmd_buffer->record_fail = true;
278 return false;
279 }
280
281 return true;
282 }
283
284 bool
285 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
286 unsigned size,
287 unsigned alignment,
288 unsigned *out_offset,
289 void **ptr)
290 {
291 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
292 if (offset + size > cmd_buffer->upload.size) {
293 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
294 return false;
295 offset = 0;
296 }
297
298 *out_offset = offset;
299 *ptr = cmd_buffer->upload.map + offset;
300
301 cmd_buffer->upload.offset = offset + size;
302 return true;
303 }
304
305 bool
306 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
307 unsigned size, unsigned alignment,
308 const void *data, unsigned *out_offset)
309 {
310 uint8_t *ptr;
311
312 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
313 out_offset, (void **)&ptr))
314 return false;
315
316 if (ptr)
317 memcpy(ptr, data, size);
318
319 return true;
320 }
321
322 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
323 {
324 struct radv_device *device = cmd_buffer->device;
325 struct radeon_winsys_cs *cs = cmd_buffer->cs;
326 uint64_t va;
327
328 if (!device->trace_bo)
329 return;
330
331 va = device->ws->buffer_get_va(device->trace_bo);
332
333 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
334
335 ++cmd_buffer->state.trace_id;
336 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
337 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
338 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
339 S_370_WR_CONFIRM(1) |
340 S_370_ENGINE_SEL(V_370_ME));
341 radeon_emit(cs, va);
342 radeon_emit(cs, va >> 32);
343 radeon_emit(cs, cmd_buffer->state.trace_id);
344 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
345 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
346 }
347
348 static void
349 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
350 struct radv_pipeline *pipeline)
351 {
352 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
353 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
354 8);
355 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
356 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
357 }
358
359 static void
360 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
361 struct radv_pipeline *pipeline)
362 {
363 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
364 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
365 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
366
367 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
369 }
370
371 /* 12.4 fixed-point */
372 static unsigned radv_pack_float_12p4(float x)
373 {
374 return x <= 0 ? 0 :
375 x >= 4096 ? 0xffff : x * 16;
376 }
377
378 static uint32_t
379 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs)
380 {
381 switch (stage) {
382 case MESA_SHADER_FRAGMENT:
383 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
384 case MESA_SHADER_VERTEX:
385 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
386 case MESA_SHADER_GEOMETRY:
387 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
388 case MESA_SHADER_COMPUTE:
389 return R_00B900_COMPUTE_USER_DATA_0;
390 default:
391 unreachable("unknown shader");
392 }
393 }
394
395 static struct ac_userdata_info *
396 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
397 gl_shader_stage stage,
398 int idx)
399 {
400 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
401 }
402
403 static void
404 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
405 struct radv_pipeline *pipeline,
406 gl_shader_stage stage,
407 int idx, uint64_t va)
408 {
409 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
410 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline));
411 if (loc->sgpr_idx == -1)
412 return;
413 assert(loc->num_sgprs == 2);
414 assert(!loc->indirect);
415 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
416 radeon_emit(cmd_buffer->cs, va);
417 radeon_emit(cmd_buffer->cs, va >> 32);
418 }
419
420 static void
421 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
422 struct radv_pipeline *pipeline)
423 {
424 int num_samples = pipeline->graphics.ms.num_samples;
425 struct radv_multisample_state *ms = &pipeline->graphics.ms;
426 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
427
428 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
429 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
430 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
431
432 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
433 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
434
435 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
436 return;
437
438 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
439 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
440 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
441
442 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
443
444 uint32_t samples_offset;
445 void *samples_ptr;
446 void *src;
447 radv_cmd_buffer_upload_alloc(cmd_buffer, num_samples * 4 * 2, 256, &samples_offset,
448 &samples_ptr);
449 switch (num_samples) {
450 case 1:
451 src = cmd_buffer->device->sample_locations_1x;
452 break;
453 case 2:
454 src = cmd_buffer->device->sample_locations_2x;
455 break;
456 case 4:
457 src = cmd_buffer->device->sample_locations_4x;
458 break;
459 case 8:
460 src = cmd_buffer->device->sample_locations_8x;
461 break;
462 case 16:
463 src = cmd_buffer->device->sample_locations_16x;
464 break;
465 default:
466 unreachable("unknown number of samples");
467 }
468 memcpy(samples_ptr, src, num_samples * 4 * 2);
469
470 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
471 va += samples_offset;
472
473 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
474 AC_UD_PS_SAMPLE_POS, va);
475 }
476
477 static void
478 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
479 struct radv_pipeline *pipeline)
480 {
481 struct radv_raster_state *raster = &pipeline->graphics.raster;
482
483 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
484 raster->pa_cl_clip_cntl);
485
486 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
487 raster->spi_interp_control);
488
489 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
490 unsigned tmp = (unsigned)(1.0 * 8.0);
491 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
492 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
493 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
494
495 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
496 raster->pa_su_vtx_cntl);
497
498 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
499 raster->pa_su_sc_mode_cntl);
500 }
501
502 static void
503 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
504 struct radv_pipeline *pipeline,
505 struct radv_shader_variant *shader,
506 struct ac_vs_output_info *outinfo)
507 {
508 struct radeon_winsys *ws = cmd_buffer->device->ws;
509 uint64_t va = ws->buffer_get_va(shader->bo);
510 unsigned export_count;
511
512 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
513
514 export_count = MAX2(1, outinfo->param_exports);
515 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
516 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
517
518 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
519 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
520 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
521 V_02870C_SPI_SHADER_4COMP :
522 V_02870C_SPI_SHADER_NONE) |
523 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
524 V_02870C_SPI_SHADER_4COMP :
525 V_02870C_SPI_SHADER_NONE) |
526 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
527 V_02870C_SPI_SHADER_4COMP :
528 V_02870C_SPI_SHADER_NONE));
529
530
531 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
532 radeon_emit(cmd_buffer->cs, va >> 8);
533 radeon_emit(cmd_buffer->cs, va >> 40);
534 radeon_emit(cmd_buffer->cs, shader->rsrc1);
535 radeon_emit(cmd_buffer->cs, shader->rsrc2);
536
537 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
538 S_028818_VTX_W0_FMT(1) |
539 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
540 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
541 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
542
543
544 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
545 pipeline->graphics.pa_cl_vs_out_cntl);
546
547 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
548 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
549 }
550
551 static void
552 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
553 struct radv_shader_variant *shader,
554 struct ac_es_output_info *outinfo)
555 {
556 struct radeon_winsys *ws = cmd_buffer->device->ws;
557 uint64_t va = ws->buffer_get_va(shader->bo);
558
559 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
560
561 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
562 outinfo->esgs_itemsize / 4);
563 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
564 radeon_emit(cmd_buffer->cs, va >> 8);
565 radeon_emit(cmd_buffer->cs, va >> 40);
566 radeon_emit(cmd_buffer->cs, shader->rsrc1);
567 radeon_emit(cmd_buffer->cs, shader->rsrc2);
568 }
569
570 static void
571 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
572 struct radv_pipeline *pipeline)
573 {
574 struct radv_shader_variant *vs;
575
576 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
577
578 vs = pipeline->shaders[MESA_SHADER_VERTEX];
579
580 if (vs->info.vs.as_es)
581 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
582 else
583 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
584
585 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
586 }
587
588
589 static void
590 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
591 struct radv_pipeline *pipeline)
592 {
593 struct radeon_winsys *ws = cmd_buffer->device->ws;
594 struct radv_shader_variant *gs;
595 uint64_t va;
596
597 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
598
599 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
600 if (!gs)
601 return;
602
603 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
604
605 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
606 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
607 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
608 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
609
610 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
611
612 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
613
614 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
615 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
616 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
617 radeon_emit(cmd_buffer->cs, 0);
618 radeon_emit(cmd_buffer->cs, 0);
619 radeon_emit(cmd_buffer->cs, 0);
620
621 uint32_t gs_num_invocations = gs->info.gs.invocations;
622 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
623 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
624 S_028B90_ENABLE(gs_num_invocations > 0));
625
626 va = ws->buffer_get_va(gs->bo);
627 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
628 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
629 radeon_emit(cmd_buffer->cs, va >> 8);
630 radeon_emit(cmd_buffer->cs, va >> 40);
631 radeon_emit(cmd_buffer->cs, gs->rsrc1);
632 radeon_emit(cmd_buffer->cs, gs->rsrc2);
633
634 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
635
636 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
637 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
638 if (loc->sgpr_idx != -1) {
639 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
640 uint32_t num_entries = 64;
641 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
642
643 if (is_vi)
644 num_entries *= stride;
645
646 stride = S_008F04_STRIDE(stride);
647 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
648 radeon_emit(cmd_buffer->cs, stride);
649 radeon_emit(cmd_buffer->cs, num_entries);
650 }
651 }
652
653 static void
654 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
655 struct radv_pipeline *pipeline)
656 {
657 struct radeon_winsys *ws = cmd_buffer->device->ws;
658 struct radv_shader_variant *ps;
659 uint64_t va;
660 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
661 struct radv_blend_state *blend = &pipeline->graphics.blend;
662 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
663
664 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
665
666 va = ws->buffer_get_va(ps->bo);
667 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
668
669 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
670 radeon_emit(cmd_buffer->cs, va >> 8);
671 radeon_emit(cmd_buffer->cs, va >> 40);
672 radeon_emit(cmd_buffer->cs, ps->rsrc1);
673 radeon_emit(cmd_buffer->cs, ps->rsrc2);
674
675 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
676 pipeline->graphics.db_shader_control);
677
678 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
679 ps->config.spi_ps_input_ena);
680
681 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
682 ps->config.spi_ps_input_addr);
683
684 if (ps->info.fs.force_persample)
685 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
686
687 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
688 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
689
690 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
691
692 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
693 pipeline->graphics.shader_z_format);
694
695 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
696
697 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
698 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
699
700 if (pipeline->graphics.ps_input_cntl_num) {
701 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
702 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
703 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
704 }
705 }
706 }
707
708 static void
709 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
710 struct radv_pipeline *pipeline)
711 {
712 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
713 return;
714
715 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
716 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
717 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
718 radv_update_multisample_state(cmd_buffer, pipeline);
719 radv_emit_vertex_shader(cmd_buffer, pipeline);
720 radv_emit_geometry_shader(cmd_buffer, pipeline);
721 radv_emit_fragment_shader(cmd_buffer, pipeline);
722
723 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
724 pipeline->graphics.prim_restart_enable);
725
726 cmd_buffer->scratch_size_needed =
727 MAX2(cmd_buffer->scratch_size_needed,
728 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
729
730 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
731 S_0286E8_WAVES(pipeline->max_waves) |
732 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
733
734 if (!cmd_buffer->state.emitted_pipeline ||
735 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
736 pipeline->graphics.can_use_guardband)
737 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
738 cmd_buffer->state.emitted_pipeline = pipeline;
739 }
740
741 static void
742 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
743 {
744 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
745 cmd_buffer->state.dynamic.viewport.viewports);
746 }
747
748 static void
749 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
750 {
751 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
752 si_write_scissors(cmd_buffer->cs, 0, count,
753 cmd_buffer->state.dynamic.scissor.scissors,
754 cmd_buffer->state.dynamic.viewport.viewports,
755 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
756 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
757 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
758 }
759
760 static void
761 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
762 int index,
763 struct radv_color_buffer_info *cb)
764 {
765 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
766 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
767 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
768 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
769 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
770 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
771 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
772 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
773 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
774 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
775 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
776 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
777 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
778
779 if (is_vi) { /* DCC BASE */
780 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
781 }
782 }
783
784 static void
785 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
786 struct radv_ds_buffer_info *ds,
787 struct radv_image *image,
788 VkImageLayout layout)
789 {
790 uint32_t db_z_info = ds->db_z_info;
791
792 if (!radv_layout_has_htile(image, layout))
793 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
794
795 if (!radv_layout_can_expclear(image, layout))
796 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
797
798 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
799 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
800
801 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
802 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
803 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
804 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
805 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
806 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
807 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
808 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
809 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
810 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
811
812 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
813 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
814 ds->pa_su_poly_offset_db_fmt_cntl);
815 }
816
817 /*
818 * To hw resolve multisample images both src and dst need to have the same
819 * micro tiling mode. However we don't always know in advance when creating
820 * the images. This function gets called if we have a resolve attachment,
821 * and tests if the attachment image has the same tiling mode, then it
822 * checks if the generated framebuffer data has the same tiling mode, and
823 * updates it if not.
824 */
825 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
826 struct radv_attachment_info *att,
827 uint32_t micro_tile_mode)
828 {
829 struct radv_image *image = att->attachment->image;
830 uint32_t tile_mode_index;
831 if (image->surface.nsamples <= 1)
832 return;
833
834 if (image->surface.micro_tile_mode != micro_tile_mode) {
835 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
836 }
837
838 if (att->cb.micro_tile_mode != micro_tile_mode) {
839 tile_mode_index = image->surface.tiling_index[0];
840
841 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
842 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
843 att->cb.micro_tile_mode = micro_tile_mode;
844 }
845 }
846
847 void
848 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
849 struct radv_image *image,
850 VkClearDepthStencilValue ds_clear_value,
851 VkImageAspectFlags aspects)
852 {
853 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
854 va += image->offset + image->clear_value_offset;
855 unsigned reg_offset = 0, reg_count = 0;
856
857 if (!image->surface.htile_size || !aspects)
858 return;
859
860 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
861 ++reg_count;
862 } else {
863 ++reg_offset;
864 va += 4;
865 }
866 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
867 ++reg_count;
868
869 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
870
871 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
872 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
873 S_370_WR_CONFIRM(1) |
874 S_370_ENGINE_SEL(V_370_PFP));
875 radeon_emit(cmd_buffer->cs, va);
876 radeon_emit(cmd_buffer->cs, va >> 32);
877 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
878 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
879 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
880 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
881
882 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
883 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
884 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
885 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
886 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
887 }
888
889 static void
890 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
891 struct radv_image *image)
892 {
893 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
894 va += image->offset + image->clear_value_offset;
895
896 if (!image->surface.htile_size)
897 return;
898
899 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
900
901 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
902 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
903 COPY_DATA_DST_SEL(COPY_DATA_REG) |
904 COPY_DATA_COUNT_SEL);
905 radeon_emit(cmd_buffer->cs, va);
906 radeon_emit(cmd_buffer->cs, va >> 32);
907 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
908 radeon_emit(cmd_buffer->cs, 0);
909
910 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
911 radeon_emit(cmd_buffer->cs, 0);
912 }
913
914 void
915 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
916 struct radv_image *image,
917 int idx,
918 uint32_t color_values[2])
919 {
920 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
921 va += image->offset + image->clear_value_offset;
922
923 if (!image->cmask.size && !image->surface.dcc_size)
924 return;
925
926 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
927
928 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
929 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
930 S_370_WR_CONFIRM(1) |
931 S_370_ENGINE_SEL(V_370_PFP));
932 radeon_emit(cmd_buffer->cs, va);
933 radeon_emit(cmd_buffer->cs, va >> 32);
934 radeon_emit(cmd_buffer->cs, color_values[0]);
935 radeon_emit(cmd_buffer->cs, color_values[1]);
936
937 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
938 radeon_emit(cmd_buffer->cs, color_values[0]);
939 radeon_emit(cmd_buffer->cs, color_values[1]);
940 }
941
942 static void
943 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
944 struct radv_image *image,
945 int idx)
946 {
947 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
948 va += image->offset + image->clear_value_offset;
949
950 if (!image->cmask.size && !image->surface.dcc_size)
951 return;
952
953 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
954 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
955
956 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
957 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
958 COPY_DATA_DST_SEL(COPY_DATA_REG) |
959 COPY_DATA_COUNT_SEL);
960 radeon_emit(cmd_buffer->cs, va);
961 radeon_emit(cmd_buffer->cs, va >> 32);
962 radeon_emit(cmd_buffer->cs, reg >> 2);
963 radeon_emit(cmd_buffer->cs, 0);
964
965 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
966 radeon_emit(cmd_buffer->cs, 0);
967 }
968
969 void
970 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
971 {
972 int i;
973 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
974 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
975 int dst_resolve_micro_tile_mode = -1;
976
977 if (subpass->has_resolve) {
978 uint32_t a = subpass->resolve_attachments[0].attachment;
979 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
980 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
981 }
982 for (i = 0; i < subpass->color_count; ++i) {
983 int idx = subpass->color_attachments[i].attachment;
984 struct radv_attachment_info *att = &framebuffer->attachments[idx];
985
986 if (dst_resolve_micro_tile_mode != -1) {
987 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
988 att, dst_resolve_micro_tile_mode);
989 }
990 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
991
992 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
993 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
994
995 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
996 }
997
998 for (i = subpass->color_count; i < 8; i++)
999 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1000 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1001
1002 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1003 int idx = subpass->depth_stencil_attachment.attachment;
1004 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1005 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1006 struct radv_image *image = att->attachment->image;
1007 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1008
1009 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1010
1011 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1012 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1013 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1014 }
1015 radv_load_depth_clear_regs(cmd_buffer, image);
1016 } else {
1017 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1018 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1019 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1020 }
1021 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1022 S_028208_BR_X(framebuffer->width) |
1023 S_028208_BR_Y(framebuffer->height));
1024 }
1025
1026 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1027 {
1028 uint32_t db_count_control;
1029
1030 if(!cmd_buffer->state.active_occlusion_queries) {
1031 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1032 db_count_control = 0;
1033 } else {
1034 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1035 }
1036 } else {
1037 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1038 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1039 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1040 S_028004_ZPASS_ENABLE(1) |
1041 S_028004_SLICE_EVEN_ENABLE(1) |
1042 S_028004_SLICE_ODD_ENABLE(1);
1043 } else {
1044 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1045 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1046 }
1047 }
1048
1049 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1050 }
1051
1052 static void
1053 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1054 {
1055 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1056
1057 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1058 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1059 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1060 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1061 }
1062
1063 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1064 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1065 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1066 }
1067
1068 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1069 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1070 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1071 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1072 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1073 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1074 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1075 S_028430_STENCILOPVAL(1));
1076 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1077 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1078 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1079 S_028434_STENCILOPVAL_BF(1));
1080 }
1081
1082 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1083 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1084 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1085 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1086 }
1087
1088 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1089 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1090 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1091 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1092 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1093
1094 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1095 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1096 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1097 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1098 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1099 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1100 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1101 }
1102 }
1103
1104 cmd_buffer->state.dirty = 0;
1105 }
1106
1107 static void
1108 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1109 struct radv_pipeline *pipeline,
1110 int idx,
1111 uint64_t va,
1112 gl_shader_stage stage)
1113 {
1114 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1115 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline));
1116
1117 if (desc_set_loc->sgpr_idx == -1)
1118 return;
1119
1120 assert(!desc_set_loc->indirect);
1121 assert(desc_set_loc->num_sgprs == 2);
1122 radeon_set_sh_reg_seq(cmd_buffer->cs,
1123 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1124 radeon_emit(cmd_buffer->cs, va);
1125 radeon_emit(cmd_buffer->cs, va >> 32);
1126 }
1127
1128 static void
1129 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1130 struct radv_pipeline *pipeline,
1131 VkShaderStageFlags stages,
1132 struct radv_descriptor_set *set,
1133 unsigned idx)
1134 {
1135 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1136 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1137 idx, set->va,
1138 MESA_SHADER_FRAGMENT);
1139
1140 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1141 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1142 idx, set->va,
1143 MESA_SHADER_VERTEX);
1144
1145 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1146 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1147 idx, set->va,
1148 MESA_SHADER_GEOMETRY);
1149
1150 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1151 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1152 idx, set->va,
1153 MESA_SHADER_COMPUTE);
1154 }
1155
1156 static void
1157 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1158 struct radv_pipeline *pipeline,
1159 VkShaderStageFlags stages)
1160 {
1161 unsigned i;
1162 if (!cmd_buffer->state.descriptors_dirty)
1163 return;
1164
1165 for (i = 0; i < MAX_SETS; i++) {
1166 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1167 continue;
1168 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1169 if (!set)
1170 continue;
1171
1172 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1173 }
1174 cmd_buffer->state.descriptors_dirty = 0;
1175 }
1176
1177 static void
1178 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1179 struct radv_pipeline *pipeline,
1180 VkShaderStageFlags stages)
1181 {
1182 struct radv_pipeline_layout *layout = pipeline->layout;
1183 unsigned offset;
1184 void *ptr;
1185 uint64_t va;
1186
1187 stages &= cmd_buffer->push_constant_stages;
1188 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1189 return;
1190
1191 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1192 16 * layout->dynamic_offset_count,
1193 256, &offset, &ptr))
1194 return;
1195
1196 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1197 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1198 16 * layout->dynamic_offset_count);
1199
1200 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1201 va += offset;
1202
1203 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1204 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1205 AC_UD_PUSH_CONSTANTS, va);
1206
1207 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1208 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1209 AC_UD_PUSH_CONSTANTS, va);
1210
1211 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1212 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1213 AC_UD_PUSH_CONSTANTS, va);
1214
1215 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1216 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1217 AC_UD_PUSH_CONSTANTS, va);
1218
1219 cmd_buffer->push_constant_stages &= ~stages;
1220 }
1221
1222 static void
1223 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1224 bool instanced_draw, bool indirect_draw,
1225 uint32_t draw_vertex_count)
1226 {
1227 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1228 struct radv_device *device = cmd_buffer->device;
1229 uint32_t ia_multi_vgt_param;
1230 uint32_t ls_hs_config = 0;
1231
1232 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1233 cmd_buffer->cs, 4096);
1234
1235 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1236 cmd_buffer->state.pipeline->num_vertex_attribs) {
1237 unsigned vb_offset;
1238 void *vb_ptr;
1239 uint32_t i = 0;
1240 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1241 uint64_t va;
1242
1243 /* allocate some descriptor state for vertex buffers */
1244 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1245 &vb_offset, &vb_ptr);
1246
1247 for (i = 0; i < num_attribs; i++) {
1248 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1249 uint32_t offset;
1250 int vb = cmd_buffer->state.pipeline->va_binding[i];
1251 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1252 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1253
1254 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1255 va = device->ws->buffer_get_va(buffer->bo);
1256
1257 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1258 va += offset + buffer->offset;
1259 desc[0] = va;
1260 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1261 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1262 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1263 else
1264 desc[2] = buffer->size - offset;
1265 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1266 }
1267
1268 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1269 va += vb_offset;
1270
1271 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1272 AC_UD_VS_VERTEX_BUFFERS, va);
1273 }
1274
1275 cmd_buffer->state.vertex_descriptors_dirty = false;
1276 cmd_buffer->state.vb_dirty = 0;
1277 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1278 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1279
1280 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1281 radv_emit_framebuffer_state(cmd_buffer);
1282
1283 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1284 radv_emit_viewport(cmd_buffer);
1285
1286 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1287 radv_emit_scissor(cmd_buffer);
1288
1289 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1290 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1291 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1292 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1293 else
1294 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1295 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1296 }
1297
1298 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1299 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1300
1301 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1302 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
1303 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1304 } else {
1305 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1306 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
1307 }
1308 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1309 }
1310
1311 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1312
1313 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1314 VK_SHADER_STAGE_ALL_GRAPHICS);
1315 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1316 VK_SHADER_STAGE_ALL_GRAPHICS);
1317
1318 assert(cmd_buffer->cs->cdw <= cdw_max);
1319
1320 si_emit_cache_flush(cmd_buffer);
1321 }
1322
1323 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1324 VkPipelineStageFlags src_stage_mask)
1325 {
1326 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1327 VK_PIPELINE_STAGE_TRANSFER_BIT |
1328 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1329 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1330 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1331 }
1332
1333 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1334 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1335 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1336 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1337 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1338 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1339 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1340 VK_PIPELINE_STAGE_TRANSFER_BIT |
1341 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1342 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1343 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1344 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1345 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1346 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1347 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1348 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1349 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1350 }
1351 }
1352
1353 static enum radv_cmd_flush_bits
1354 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1355 VkAccessFlags src_flags)
1356 {
1357 enum radv_cmd_flush_bits flush_bits = 0;
1358 uint32_t b;
1359 for_each_bit(b, src_flags) {
1360 switch ((VkAccessFlagBits)(1 << b)) {
1361 case VK_ACCESS_SHADER_WRITE_BIT:
1362 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1363 break;
1364 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1365 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1366 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1367 break;
1368 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1369 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1370 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1371 break;
1372 case VK_ACCESS_TRANSFER_WRITE_BIT:
1373 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1374 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1375 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1376 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1377 RADV_CMD_FLAG_INV_GLOBAL_L2;
1378 break;
1379 default:
1380 break;
1381 }
1382 }
1383 return flush_bits;
1384 }
1385
1386 static enum radv_cmd_flush_bits
1387 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1388 VkAccessFlags dst_flags,
1389 struct radv_image *image)
1390 {
1391 enum radv_cmd_flush_bits flush_bits = 0;
1392 uint32_t b;
1393 for_each_bit(b, dst_flags) {
1394 switch ((VkAccessFlagBits)(1 << b)) {
1395 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1396 case VK_ACCESS_INDEX_READ_BIT:
1397 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1398 break;
1399 case VK_ACCESS_UNIFORM_READ_BIT:
1400 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1401 break;
1402 case VK_ACCESS_SHADER_READ_BIT:
1403 case VK_ACCESS_TRANSFER_READ_BIT:
1404 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1405 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1406 RADV_CMD_FLAG_INV_GLOBAL_L2;
1407 break;
1408 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1409 /* TODO: change to image && when the image gets passed
1410 * through from the subpass. */
1411 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1412 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1413 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1414 break;
1415 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1416 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1417 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1418 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1419 break;
1420 default:
1421 break;
1422 }
1423 }
1424 return flush_bits;
1425 }
1426
1427 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1428 {
1429 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1430 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1431 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1432 NULL);
1433 }
1434
1435 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1436 VkAttachmentReference att)
1437 {
1438 unsigned idx = att.attachment;
1439 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1440 VkImageSubresourceRange range;
1441 range.aspectMask = 0;
1442 range.baseMipLevel = view->base_mip;
1443 range.levelCount = 1;
1444 range.baseArrayLayer = view->base_layer;
1445 range.layerCount = cmd_buffer->state.framebuffer->layers;
1446
1447 radv_handle_image_transition(cmd_buffer,
1448 view->image,
1449 cmd_buffer->state.attachments[idx].current_layout,
1450 att.layout, 0, 0, &range,
1451 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1452
1453 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1454
1455
1456 }
1457
1458 void
1459 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1460 const struct radv_subpass *subpass, bool transitions)
1461 {
1462 if (transitions) {
1463 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1464
1465 for (unsigned i = 0; i < subpass->color_count; ++i) {
1466 radv_handle_subpass_image_transition(cmd_buffer,
1467 subpass->color_attachments[i]);
1468 }
1469
1470 for (unsigned i = 0; i < subpass->input_count; ++i) {
1471 radv_handle_subpass_image_transition(cmd_buffer,
1472 subpass->input_attachments[i]);
1473 }
1474
1475 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1476 radv_handle_subpass_image_transition(cmd_buffer,
1477 subpass->depth_stencil_attachment);
1478 }
1479 }
1480
1481 cmd_buffer->state.subpass = subpass;
1482
1483 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1484 }
1485
1486 static void
1487 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1488 struct radv_render_pass *pass,
1489 const VkRenderPassBeginInfo *info)
1490 {
1491 struct radv_cmd_state *state = &cmd_buffer->state;
1492
1493 if (pass->attachment_count == 0) {
1494 state->attachments = NULL;
1495 return;
1496 }
1497
1498 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1499 pass->attachment_count *
1500 sizeof(state->attachments[0]),
1501 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1502 if (state->attachments == NULL) {
1503 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1504 abort();
1505 }
1506
1507 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1508 struct radv_render_pass_attachment *att = &pass->attachments[i];
1509 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1510 VkImageAspectFlags clear_aspects = 0;
1511
1512 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1513 /* color attachment */
1514 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1515 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1516 }
1517 } else {
1518 /* depthstencil attachment */
1519 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1520 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1521 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1522 }
1523 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1524 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1525 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1526 }
1527 }
1528
1529 state->attachments[i].pending_clear_aspects = clear_aspects;
1530 if (clear_aspects && info) {
1531 assert(info->clearValueCount > i);
1532 state->attachments[i].clear_value = info->pClearValues[i];
1533 }
1534
1535 state->attachments[i].current_layout = att->initial_layout;
1536 }
1537 }
1538
1539 VkResult radv_AllocateCommandBuffers(
1540 VkDevice _device,
1541 const VkCommandBufferAllocateInfo *pAllocateInfo,
1542 VkCommandBuffer *pCommandBuffers)
1543 {
1544 RADV_FROM_HANDLE(radv_device, device, _device);
1545 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1546
1547 VkResult result = VK_SUCCESS;
1548 uint32_t i;
1549
1550 memset(pCommandBuffers, 0,
1551 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1552
1553 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1554
1555 if (!list_empty(&pool->free_cmd_buffers)) {
1556 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1557
1558 list_del(&cmd_buffer->pool_link);
1559 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1560
1561 radv_reset_cmd_buffer(cmd_buffer);
1562 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1563 cmd_buffer->level = pAllocateInfo->level;
1564
1565 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1566 result = VK_SUCCESS;
1567 } else {
1568 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1569 &pCommandBuffers[i]);
1570 }
1571 if (result != VK_SUCCESS)
1572 break;
1573 }
1574
1575 if (result != VK_SUCCESS)
1576 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1577 i, pCommandBuffers);
1578
1579 return result;
1580 }
1581
1582 void radv_FreeCommandBuffers(
1583 VkDevice device,
1584 VkCommandPool commandPool,
1585 uint32_t commandBufferCount,
1586 const VkCommandBuffer *pCommandBuffers)
1587 {
1588 for (uint32_t i = 0; i < commandBufferCount; i++) {
1589 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1590
1591 if (cmd_buffer) {
1592 if (cmd_buffer->pool) {
1593 list_del(&cmd_buffer->pool_link);
1594 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1595 } else
1596 radv_cmd_buffer_destroy(cmd_buffer);
1597
1598 }
1599 }
1600 }
1601
1602 VkResult radv_ResetCommandBuffer(
1603 VkCommandBuffer commandBuffer,
1604 VkCommandBufferResetFlags flags)
1605 {
1606 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1607 radv_reset_cmd_buffer(cmd_buffer);
1608 return VK_SUCCESS;
1609 }
1610
1611 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1612 {
1613 struct radv_device *device = cmd_buffer->device;
1614 if (device->gfx_init) {
1615 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1616 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1617 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1618 radeon_emit(cmd_buffer->cs, va);
1619 radeon_emit(cmd_buffer->cs, (va >> 32) & 0xffff);
1620 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1621 } else
1622 si_init_config(cmd_buffer);
1623 }
1624
1625 VkResult radv_BeginCommandBuffer(
1626 VkCommandBuffer commandBuffer,
1627 const VkCommandBufferBeginInfo *pBeginInfo)
1628 {
1629 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1630 radv_reset_cmd_buffer(cmd_buffer);
1631
1632 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1633
1634 /* setup initial configuration into command buffer */
1635 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1636 switch (cmd_buffer->queue_family_index) {
1637 case RADV_QUEUE_GENERAL:
1638 emit_gfx_buffer_state(cmd_buffer);
1639 radv_set_db_count_control(cmd_buffer);
1640 break;
1641 case RADV_QUEUE_COMPUTE:
1642 si_init_compute(cmd_buffer);
1643 break;
1644 case RADV_QUEUE_TRANSFER:
1645 default:
1646 break;
1647 }
1648 }
1649
1650 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1651 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1652 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1653
1654 struct radv_subpass *subpass =
1655 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1656
1657 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1658 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1659 }
1660
1661 return VK_SUCCESS;
1662 }
1663
1664 void radv_CmdBindVertexBuffers(
1665 VkCommandBuffer commandBuffer,
1666 uint32_t firstBinding,
1667 uint32_t bindingCount,
1668 const VkBuffer* pBuffers,
1669 const VkDeviceSize* pOffsets)
1670 {
1671 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1672 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1673
1674 /* We have to defer setting up vertex buffer since we need the buffer
1675 * stride from the pipeline. */
1676
1677 assert(firstBinding + bindingCount < MAX_VBS);
1678 for (uint32_t i = 0; i < bindingCount; i++) {
1679 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1680 vb[firstBinding + i].offset = pOffsets[i];
1681 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1682 }
1683 }
1684
1685 void radv_CmdBindIndexBuffer(
1686 VkCommandBuffer commandBuffer,
1687 VkBuffer buffer,
1688 VkDeviceSize offset,
1689 VkIndexType indexType)
1690 {
1691 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1692
1693 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1694 cmd_buffer->state.index_offset = offset;
1695 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1696 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1697 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1698 }
1699
1700
1701 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1702 struct radv_descriptor_set *set,
1703 unsigned idx)
1704 {
1705 struct radeon_winsys *ws = cmd_buffer->device->ws;
1706
1707 cmd_buffer->state.descriptors[idx] = set;
1708 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1709 if (!set)
1710 return;
1711
1712 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1713 if (set->descriptors[j])
1714 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1715
1716 if(set->bo)
1717 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1718 }
1719
1720 void radv_CmdBindDescriptorSets(
1721 VkCommandBuffer commandBuffer,
1722 VkPipelineBindPoint pipelineBindPoint,
1723 VkPipelineLayout _layout,
1724 uint32_t firstSet,
1725 uint32_t descriptorSetCount,
1726 const VkDescriptorSet* pDescriptorSets,
1727 uint32_t dynamicOffsetCount,
1728 const uint32_t* pDynamicOffsets)
1729 {
1730 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1731 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1732 unsigned dyn_idx = 0;
1733
1734 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1735 cmd_buffer->cs, MAX_SETS * 4 * 6);
1736
1737 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1738 unsigned idx = i + firstSet;
1739 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1740 radv_bind_descriptor_set(cmd_buffer, set, idx);
1741
1742 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1743 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1744 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1745 assert(dyn_idx < dynamicOffsetCount);
1746
1747 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1748 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1749 dst[0] = va;
1750 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1751 dst[2] = range->size;
1752 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1753 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1754 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1755 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1756 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1757 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1758 cmd_buffer->push_constant_stages |=
1759 set->layout->dynamic_shader_stages;
1760 }
1761 }
1762
1763 assert(cmd_buffer->cs->cdw <= cdw_max);
1764 }
1765
1766 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1767 VkPipelineLayout layout,
1768 VkShaderStageFlags stageFlags,
1769 uint32_t offset,
1770 uint32_t size,
1771 const void* pValues)
1772 {
1773 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1774 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1775 cmd_buffer->push_constant_stages |= stageFlags;
1776 }
1777
1778 VkResult radv_EndCommandBuffer(
1779 VkCommandBuffer commandBuffer)
1780 {
1781 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1782
1783 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
1784 si_emit_cache_flush(cmd_buffer);
1785
1786 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1787 cmd_buffer->record_fail)
1788 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1789 return VK_SUCCESS;
1790 }
1791
1792 static void
1793 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1794 {
1795 struct radeon_winsys *ws = cmd_buffer->device->ws;
1796 struct radv_shader_variant *compute_shader;
1797 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1798 uint64_t va;
1799
1800 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1801 return;
1802
1803 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1804
1805 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1806 va = ws->buffer_get_va(compute_shader->bo);
1807
1808 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1809
1810 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1811 cmd_buffer->cs, 16);
1812
1813 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1814 radeon_emit(cmd_buffer->cs, va >> 8);
1815 radeon_emit(cmd_buffer->cs, va >> 40);
1816
1817 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1818 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1819 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1820
1821
1822 cmd_buffer->compute_scratch_size_needed =
1823 MAX2(cmd_buffer->compute_scratch_size_needed,
1824 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1825
1826 /* change these once we have scratch support */
1827 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1828 S_00B860_WAVES(pipeline->max_waves) |
1829 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1830
1831 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1832 radeon_emit(cmd_buffer->cs,
1833 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1834 radeon_emit(cmd_buffer->cs,
1835 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1836 radeon_emit(cmd_buffer->cs,
1837 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1838
1839 assert(cmd_buffer->cs->cdw <= cdw_max);
1840 }
1841
1842
1843 void radv_CmdBindPipeline(
1844 VkCommandBuffer commandBuffer,
1845 VkPipelineBindPoint pipelineBindPoint,
1846 VkPipeline _pipeline)
1847 {
1848 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1849 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1850
1851 for (unsigned i = 0; i < MAX_SETS; i++) {
1852 if (cmd_buffer->state.descriptors[i])
1853 cmd_buffer->state.descriptors_dirty |= (1 << i);
1854 }
1855
1856 switch (pipelineBindPoint) {
1857 case VK_PIPELINE_BIND_POINT_COMPUTE:
1858 cmd_buffer->state.compute_pipeline = pipeline;
1859 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
1860 break;
1861 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1862 cmd_buffer->state.pipeline = pipeline;
1863 cmd_buffer->state.vertex_descriptors_dirty = true;
1864 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1865 cmd_buffer->push_constant_stages |= pipeline->active_stages;
1866
1867 /* Apply the dynamic state from the pipeline */
1868 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
1869 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
1870 &pipeline->dynamic_state,
1871 pipeline->dynamic_state_mask);
1872
1873 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
1874 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
1875 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
1876 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
1877
1878 if (radv_pipeline_has_gs(pipeline)) {
1879 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1880 AC_UD_SCRATCH_RING_OFFSETS);
1881 if (cmd_buffer->ring_offsets_idx == -1)
1882 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
1883 else if (loc->sgpr_idx != -1)
1884 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
1885 }
1886 break;
1887 default:
1888 assert(!"invalid bind point");
1889 break;
1890 }
1891 }
1892
1893 void radv_CmdSetViewport(
1894 VkCommandBuffer commandBuffer,
1895 uint32_t firstViewport,
1896 uint32_t viewportCount,
1897 const VkViewport* pViewports)
1898 {
1899 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1900
1901 const uint32_t total_count = firstViewport + viewportCount;
1902 if (cmd_buffer->state.dynamic.viewport.count < total_count)
1903 cmd_buffer->state.dynamic.viewport.count = total_count;
1904
1905 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
1906 pViewports, viewportCount * sizeof(*pViewports));
1907
1908 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
1909 }
1910
1911 void radv_CmdSetScissor(
1912 VkCommandBuffer commandBuffer,
1913 uint32_t firstScissor,
1914 uint32_t scissorCount,
1915 const VkRect2D* pScissors)
1916 {
1917 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1918
1919 const uint32_t total_count = firstScissor + scissorCount;
1920 if (cmd_buffer->state.dynamic.scissor.count < total_count)
1921 cmd_buffer->state.dynamic.scissor.count = total_count;
1922
1923 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
1924 pScissors, scissorCount * sizeof(*pScissors));
1925 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1926 }
1927
1928 void radv_CmdSetLineWidth(
1929 VkCommandBuffer commandBuffer,
1930 float lineWidth)
1931 {
1932 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1933 cmd_buffer->state.dynamic.line_width = lineWidth;
1934 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1935 }
1936
1937 void radv_CmdSetDepthBias(
1938 VkCommandBuffer commandBuffer,
1939 float depthBiasConstantFactor,
1940 float depthBiasClamp,
1941 float depthBiasSlopeFactor)
1942 {
1943 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1944
1945 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
1946 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
1947 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
1948
1949 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1950 }
1951
1952 void radv_CmdSetBlendConstants(
1953 VkCommandBuffer commandBuffer,
1954 const float blendConstants[4])
1955 {
1956 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1957
1958 memcpy(cmd_buffer->state.dynamic.blend_constants,
1959 blendConstants, sizeof(float) * 4);
1960
1961 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
1962 }
1963
1964 void radv_CmdSetDepthBounds(
1965 VkCommandBuffer commandBuffer,
1966 float minDepthBounds,
1967 float maxDepthBounds)
1968 {
1969 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1970
1971 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
1972 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
1973
1974 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
1975 }
1976
1977 void radv_CmdSetStencilCompareMask(
1978 VkCommandBuffer commandBuffer,
1979 VkStencilFaceFlags faceMask,
1980 uint32_t compareMask)
1981 {
1982 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1983
1984 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1985 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
1986 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1987 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
1988
1989 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1990 }
1991
1992 void radv_CmdSetStencilWriteMask(
1993 VkCommandBuffer commandBuffer,
1994 VkStencilFaceFlags faceMask,
1995 uint32_t writeMask)
1996 {
1997 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1998
1999 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2000 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2001 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2002 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2003
2004 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2005 }
2006
2007 void radv_CmdSetStencilReference(
2008 VkCommandBuffer commandBuffer,
2009 VkStencilFaceFlags faceMask,
2010 uint32_t reference)
2011 {
2012 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2013
2014 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2015 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2016 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2017 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2018
2019 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2020 }
2021
2022
2023 void radv_CmdExecuteCommands(
2024 VkCommandBuffer commandBuffer,
2025 uint32_t commandBufferCount,
2026 const VkCommandBuffer* pCmdBuffers)
2027 {
2028 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2029
2030 /* Emit pending flushes on primary prior to executing secondary */
2031 si_emit_cache_flush(primary);
2032
2033 for (uint32_t i = 0; i < commandBufferCount; i++) {
2034 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2035
2036 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2037 secondary->scratch_size_needed);
2038 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2039 secondary->compute_scratch_size_needed);
2040
2041 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2042 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2043 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2044 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2045
2046 if (secondary->ring_offsets_idx != -1) {
2047 if (primary->ring_offsets_idx == -1)
2048 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2049 else
2050 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2051 }
2052 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2053 }
2054
2055 /* if we execute secondary we need to re-emit out pipelines */
2056 if (commandBufferCount) {
2057 primary->state.emitted_pipeline = NULL;
2058 primary->state.emitted_compute_pipeline = NULL;
2059 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2060 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2061 }
2062 }
2063
2064 VkResult radv_CreateCommandPool(
2065 VkDevice _device,
2066 const VkCommandPoolCreateInfo* pCreateInfo,
2067 const VkAllocationCallbacks* pAllocator,
2068 VkCommandPool* pCmdPool)
2069 {
2070 RADV_FROM_HANDLE(radv_device, device, _device);
2071 struct radv_cmd_pool *pool;
2072
2073 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2074 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2075 if (pool == NULL)
2076 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2077
2078 if (pAllocator)
2079 pool->alloc = *pAllocator;
2080 else
2081 pool->alloc = device->alloc;
2082
2083 list_inithead(&pool->cmd_buffers);
2084 list_inithead(&pool->free_cmd_buffers);
2085
2086 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2087
2088 *pCmdPool = radv_cmd_pool_to_handle(pool);
2089
2090 return VK_SUCCESS;
2091
2092 }
2093
2094 void radv_DestroyCommandPool(
2095 VkDevice _device,
2096 VkCommandPool commandPool,
2097 const VkAllocationCallbacks* pAllocator)
2098 {
2099 RADV_FROM_HANDLE(radv_device, device, _device);
2100 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2101
2102 if (!pool)
2103 return;
2104
2105 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2106 &pool->cmd_buffers, pool_link) {
2107 radv_cmd_buffer_destroy(cmd_buffer);
2108 }
2109
2110 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2111 &pool->free_cmd_buffers, pool_link) {
2112 radv_cmd_buffer_destroy(cmd_buffer);
2113 }
2114
2115 vk_free2(&device->alloc, pAllocator, pool);
2116 }
2117
2118 VkResult radv_ResetCommandPool(
2119 VkDevice device,
2120 VkCommandPool commandPool,
2121 VkCommandPoolResetFlags flags)
2122 {
2123 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2124
2125 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2126 &pool->cmd_buffers, pool_link) {
2127 radv_reset_cmd_buffer(cmd_buffer);
2128 }
2129
2130 return VK_SUCCESS;
2131 }
2132
2133 void radv_TrimCommandPoolKHR(
2134 VkDevice device,
2135 VkCommandPool commandPool,
2136 VkCommandPoolTrimFlagsKHR flags)
2137 {
2138 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2139
2140 if (!pool)
2141 return;
2142
2143 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2144 &pool->free_cmd_buffers, pool_link) {
2145 radv_cmd_buffer_destroy(cmd_buffer);
2146 }
2147 }
2148
2149 void radv_CmdBeginRenderPass(
2150 VkCommandBuffer commandBuffer,
2151 const VkRenderPassBeginInfo* pRenderPassBegin,
2152 VkSubpassContents contents)
2153 {
2154 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2155 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2156 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2157
2158 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2159 cmd_buffer->cs, 2048);
2160
2161 cmd_buffer->state.framebuffer = framebuffer;
2162 cmd_buffer->state.pass = pass;
2163 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2164 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2165
2166 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2167 assert(cmd_buffer->cs->cdw <= cdw_max);
2168
2169 radv_cmd_buffer_clear_subpass(cmd_buffer);
2170 }
2171
2172 void radv_CmdNextSubpass(
2173 VkCommandBuffer commandBuffer,
2174 VkSubpassContents contents)
2175 {
2176 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2177
2178 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2179
2180 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2181 2048);
2182
2183 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2184 radv_cmd_buffer_clear_subpass(cmd_buffer);
2185 }
2186
2187 void radv_CmdDraw(
2188 VkCommandBuffer commandBuffer,
2189 uint32_t vertexCount,
2190 uint32_t instanceCount,
2191 uint32_t firstVertex,
2192 uint32_t firstInstance)
2193 {
2194 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2195
2196 radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, vertexCount);
2197
2198 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2199
2200 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2201 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2202 if (loc->sgpr_idx != -1) {
2203 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2204 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2205 radeon_emit(cmd_buffer->cs, firstVertex);
2206 radeon_emit(cmd_buffer->cs, firstInstance);
2207 radeon_emit(cmd_buffer->cs, 0);
2208 }
2209 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2210 radeon_emit(cmd_buffer->cs, instanceCount);
2211
2212 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2213 radeon_emit(cmd_buffer->cs, vertexCount);
2214 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2215 S_0287F0_USE_OPAQUE(0));
2216
2217 assert(cmd_buffer->cs->cdw <= cdw_max);
2218
2219 radv_cmd_buffer_trace_emit(cmd_buffer);
2220 }
2221
2222 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2223 {
2224 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
2225
2226 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
2227 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
2228 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
2229 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2230 primitive_reset_index);
2231 }
2232 }
2233
2234 void radv_CmdDrawIndexed(
2235 VkCommandBuffer commandBuffer,
2236 uint32_t indexCount,
2237 uint32_t instanceCount,
2238 uint32_t firstIndex,
2239 int32_t vertexOffset,
2240 uint32_t firstInstance)
2241 {
2242 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2243 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2244 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2245 uint64_t index_va;
2246
2247 radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, indexCount);
2248 radv_emit_primitive_reset_index(cmd_buffer);
2249
2250 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2251
2252 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2253 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2254
2255 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2256 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2257 if (loc->sgpr_idx != -1) {
2258 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2259 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2260 radeon_emit(cmd_buffer->cs, vertexOffset);
2261 radeon_emit(cmd_buffer->cs, firstInstance);
2262 radeon_emit(cmd_buffer->cs, 0);
2263 }
2264 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2265 radeon_emit(cmd_buffer->cs, instanceCount);
2266
2267 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2268 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2269 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2270 radeon_emit(cmd_buffer->cs, index_max_size);
2271 radeon_emit(cmd_buffer->cs, index_va);
2272 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2273 radeon_emit(cmd_buffer->cs, indexCount);
2274 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2275
2276 assert(cmd_buffer->cs->cdw <= cdw_max);
2277 radv_cmd_buffer_trace_emit(cmd_buffer);
2278 }
2279
2280 static void
2281 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2282 VkBuffer _buffer,
2283 VkDeviceSize offset,
2284 VkBuffer _count_buffer,
2285 VkDeviceSize count_offset,
2286 uint32_t draw_count,
2287 uint32_t stride,
2288 bool indexed)
2289 {
2290 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2291 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2292 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2293 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2294 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2295 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2296 indirect_va += offset + buffer->offset;
2297 uint64_t count_va = 0;
2298
2299 if (count_buffer) {
2300 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2301 count_va += count_offset + count_buffer->offset;
2302 }
2303
2304 if (!draw_count)
2305 return;
2306
2307 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2308
2309 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2310 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2311 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2312 assert(loc->sgpr_idx != -1);
2313 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2314 radeon_emit(cs, 1);
2315 radeon_emit(cs, indirect_va);
2316 radeon_emit(cs, indirect_va >> 32);
2317
2318 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2319 PKT3_DRAW_INDIRECT_MULTI,
2320 8, false));
2321 radeon_emit(cs, 0);
2322 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2323 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2324 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2325 S_2C3_DRAW_INDEX_ENABLE(1) |
2326 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2327 radeon_emit(cs, draw_count); /* count */
2328 radeon_emit(cs, count_va); /* count_addr */
2329 radeon_emit(cs, count_va >> 32);
2330 radeon_emit(cs, stride); /* stride */
2331 radeon_emit(cs, di_src_sel);
2332 radv_cmd_buffer_trace_emit(cmd_buffer);
2333 }
2334
2335 static void
2336 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2337 VkBuffer buffer,
2338 VkDeviceSize offset,
2339 VkBuffer countBuffer,
2340 VkDeviceSize countBufferOffset,
2341 uint32_t maxDrawCount,
2342 uint32_t stride)
2343 {
2344 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2345 radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0);
2346
2347 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2348 cmd_buffer->cs, 14);
2349
2350 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2351 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2352
2353 assert(cmd_buffer->cs->cdw <= cdw_max);
2354 }
2355
2356 static void
2357 radv_cmd_draw_indexed_indirect_count(
2358 VkCommandBuffer commandBuffer,
2359 VkBuffer buffer,
2360 VkDeviceSize offset,
2361 VkBuffer countBuffer,
2362 VkDeviceSize countBufferOffset,
2363 uint32_t maxDrawCount,
2364 uint32_t stride)
2365 {
2366 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2367 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2368 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2369 uint64_t index_va;
2370 radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0);
2371 radv_emit_primitive_reset_index(cmd_buffer);
2372
2373 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2374 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2375
2376 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2377
2378 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2379 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2380
2381 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2382 radeon_emit(cmd_buffer->cs, index_va);
2383 radeon_emit(cmd_buffer->cs, index_va >> 32);
2384
2385 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2386 radeon_emit(cmd_buffer->cs, index_max_size);
2387
2388 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2389 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2390
2391 assert(cmd_buffer->cs->cdw <= cdw_max);
2392 }
2393
2394 void radv_CmdDrawIndirect(
2395 VkCommandBuffer commandBuffer,
2396 VkBuffer buffer,
2397 VkDeviceSize offset,
2398 uint32_t drawCount,
2399 uint32_t stride)
2400 {
2401 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2402 VK_NULL_HANDLE, 0, drawCount, stride);
2403 }
2404
2405 void radv_CmdDrawIndexedIndirect(
2406 VkCommandBuffer commandBuffer,
2407 VkBuffer buffer,
2408 VkDeviceSize offset,
2409 uint32_t drawCount,
2410 uint32_t stride)
2411 {
2412 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2413 VK_NULL_HANDLE, 0, drawCount, stride);
2414 }
2415
2416 void radv_CmdDrawIndirectCountAMD(
2417 VkCommandBuffer commandBuffer,
2418 VkBuffer buffer,
2419 VkDeviceSize offset,
2420 VkBuffer countBuffer,
2421 VkDeviceSize countBufferOffset,
2422 uint32_t maxDrawCount,
2423 uint32_t stride)
2424 {
2425 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2426 countBuffer, countBufferOffset,
2427 maxDrawCount, stride);
2428 }
2429
2430 void radv_CmdDrawIndexedIndirectCountAMD(
2431 VkCommandBuffer commandBuffer,
2432 VkBuffer buffer,
2433 VkDeviceSize offset,
2434 VkBuffer countBuffer,
2435 VkDeviceSize countBufferOffset,
2436 uint32_t maxDrawCount,
2437 uint32_t stride)
2438 {
2439 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2440 countBuffer, countBufferOffset,
2441 maxDrawCount, stride);
2442 }
2443
2444 static void
2445 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2446 {
2447 radv_emit_compute_pipeline(cmd_buffer);
2448 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2449 VK_SHADER_STAGE_COMPUTE_BIT);
2450 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2451 VK_SHADER_STAGE_COMPUTE_BIT);
2452 si_emit_cache_flush(cmd_buffer);
2453 }
2454
2455 void radv_CmdDispatch(
2456 VkCommandBuffer commandBuffer,
2457 uint32_t x,
2458 uint32_t y,
2459 uint32_t z)
2460 {
2461 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2462
2463 radv_flush_compute_state(cmd_buffer);
2464
2465 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2466
2467 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2468 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2469 if (loc->sgpr_idx != -1) {
2470 assert(!loc->indirect);
2471 assert(loc->num_sgprs == 3);
2472 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2473 radeon_emit(cmd_buffer->cs, x);
2474 radeon_emit(cmd_buffer->cs, y);
2475 radeon_emit(cmd_buffer->cs, z);
2476 }
2477
2478 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2479 PKT3_SHADER_TYPE_S(1));
2480 radeon_emit(cmd_buffer->cs, x);
2481 radeon_emit(cmd_buffer->cs, y);
2482 radeon_emit(cmd_buffer->cs, z);
2483 radeon_emit(cmd_buffer->cs, 1);
2484
2485 assert(cmd_buffer->cs->cdw <= cdw_max);
2486 radv_cmd_buffer_trace_emit(cmd_buffer);
2487 }
2488
2489 void radv_CmdDispatchIndirect(
2490 VkCommandBuffer commandBuffer,
2491 VkBuffer _buffer,
2492 VkDeviceSize offset)
2493 {
2494 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2495 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2496 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2497 va += buffer->offset + offset;
2498
2499 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2500
2501 radv_flush_compute_state(cmd_buffer);
2502
2503 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2504 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2505 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2506 if (loc->sgpr_idx != -1) {
2507 for (unsigned i = 0; i < 3; ++i) {
2508 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2509 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2510 COPY_DATA_DST_SEL(COPY_DATA_REG));
2511 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2512 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2513 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2514 radeon_emit(cmd_buffer->cs, 0);
2515 }
2516 }
2517
2518 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2519 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2520 PKT3_SHADER_TYPE_S(1));
2521 radeon_emit(cmd_buffer->cs, va);
2522 radeon_emit(cmd_buffer->cs, va >> 32);
2523 radeon_emit(cmd_buffer->cs, 1);
2524 } else {
2525 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2526 PKT3_SHADER_TYPE_S(1));
2527 radeon_emit(cmd_buffer->cs, 1);
2528 radeon_emit(cmd_buffer->cs, va);
2529 radeon_emit(cmd_buffer->cs, va >> 32);
2530
2531 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2532 PKT3_SHADER_TYPE_S(1));
2533 radeon_emit(cmd_buffer->cs, 0);
2534 radeon_emit(cmd_buffer->cs, 1);
2535 }
2536
2537 assert(cmd_buffer->cs->cdw <= cdw_max);
2538 radv_cmd_buffer_trace_emit(cmd_buffer);
2539 }
2540
2541 void radv_unaligned_dispatch(
2542 struct radv_cmd_buffer *cmd_buffer,
2543 uint32_t x,
2544 uint32_t y,
2545 uint32_t z)
2546 {
2547 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2548 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2549 uint32_t blocks[3], remainder[3];
2550
2551 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2552 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2553 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2554
2555 /* If aligned, these should be an entire block size, not 0 */
2556 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2557 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2558 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2559
2560 radv_flush_compute_state(cmd_buffer);
2561
2562 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2563
2564 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2565 radeon_emit(cmd_buffer->cs,
2566 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2567 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2568 radeon_emit(cmd_buffer->cs,
2569 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2570 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2571 radeon_emit(cmd_buffer->cs,
2572 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2573 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2574
2575 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2576 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2577 if (loc->sgpr_idx != -1) {
2578 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2579 radeon_emit(cmd_buffer->cs, blocks[0]);
2580 radeon_emit(cmd_buffer->cs, blocks[1]);
2581 radeon_emit(cmd_buffer->cs, blocks[2]);
2582 }
2583 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2584 PKT3_SHADER_TYPE_S(1));
2585 radeon_emit(cmd_buffer->cs, blocks[0]);
2586 radeon_emit(cmd_buffer->cs, blocks[1]);
2587 radeon_emit(cmd_buffer->cs, blocks[2]);
2588 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2589 S_00B800_PARTIAL_TG_EN(1));
2590
2591 assert(cmd_buffer->cs->cdw <= cdw_max);
2592 radv_cmd_buffer_trace_emit(cmd_buffer);
2593 }
2594
2595 void radv_CmdEndRenderPass(
2596 VkCommandBuffer commandBuffer)
2597 {
2598 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2599
2600 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2601
2602 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2603
2604 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2605 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2606 radv_handle_subpass_image_transition(cmd_buffer,
2607 (VkAttachmentReference){i, layout});
2608 }
2609
2610 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2611
2612 cmd_buffer->state.pass = NULL;
2613 cmd_buffer->state.subpass = NULL;
2614 cmd_buffer->state.attachments = NULL;
2615 cmd_buffer->state.framebuffer = NULL;
2616 }
2617
2618
2619 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2620 struct radv_image *image,
2621 const VkImageSubresourceRange *range)
2622 {
2623 assert(range->baseMipLevel == 0);
2624 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
2625 unsigned layer_count = radv_get_layerCount(image, range);
2626 uint64_t size = image->surface.htile_slice_size * layer_count;
2627 uint64_t offset = image->offset + image->htile_offset +
2628 image->surface.htile_slice_size * range->baseArrayLayer;
2629
2630 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2631 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2632
2633 radv_fill_buffer(cmd_buffer, image->bo, offset, size, 0xffffffff);
2634
2635 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2636 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2637 RADV_CMD_FLAG_INV_VMEM_L1 |
2638 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2639 }
2640
2641 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2642 struct radv_image *image,
2643 VkImageLayout src_layout,
2644 VkImageLayout dst_layout,
2645 const VkImageSubresourceRange *range,
2646 VkImageAspectFlags pending_clears)
2647 {
2648 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2649 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2650 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2651 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2652 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2653 /* The clear will initialize htile. */
2654 return;
2655 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2656 radv_layout_has_htile(image, dst_layout)) {
2657 /* TODO: merge with the clear if applicable */
2658 radv_initialize_htile(cmd_buffer, image, range);
2659 } else if (!radv_layout_has_htile(image, src_layout) &&
2660 radv_layout_has_htile(image, dst_layout)) {
2661 radv_initialize_htile(cmd_buffer, image, range);
2662 } else if ((radv_layout_has_htile(image, src_layout) &&
2663 !radv_layout_has_htile(image, dst_layout)) ||
2664 (radv_layout_is_htile_compressed(image, src_layout) &&
2665 !radv_layout_is_htile_compressed(image, dst_layout))) {
2666 VkImageSubresourceRange local_range = *range;
2667 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2668 local_range.baseMipLevel = 0;
2669 local_range.levelCount = 1;
2670
2671 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2672 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2673
2674 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
2675
2676 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2677 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2678 }
2679 }
2680
2681 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2682 struct radv_image *image, uint32_t value)
2683 {
2684 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2685 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2686
2687 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2688 image->cmask.size, value);
2689
2690 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2691 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2692 RADV_CMD_FLAG_INV_VMEM_L1 |
2693 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2694 }
2695
2696 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2697 struct radv_image *image,
2698 VkImageLayout src_layout,
2699 VkImageLayout dst_layout,
2700 unsigned src_queue_mask,
2701 unsigned dst_queue_mask,
2702 const VkImageSubresourceRange *range,
2703 VkImageAspectFlags pending_clears)
2704 {
2705 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2706 if (image->fmask.size)
2707 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2708 else
2709 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2710 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2711 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2712 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
2713 }
2714 }
2715
2716 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2717 struct radv_image *image, uint32_t value)
2718 {
2719
2720 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2721 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2722
2723 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2724 image->surface.dcc_size, value);
2725
2726 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2727 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2728 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2729 RADV_CMD_FLAG_INV_VMEM_L1 |
2730 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2731 }
2732
2733 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2734 struct radv_image *image,
2735 VkImageLayout src_layout,
2736 VkImageLayout dst_layout,
2737 unsigned src_queue_mask,
2738 unsigned dst_queue_mask,
2739 const VkImageSubresourceRange *range,
2740 VkImageAspectFlags pending_clears)
2741 {
2742 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2743 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2744 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2745 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2746 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
2747 }
2748 }
2749
2750 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2751 struct radv_image *image,
2752 VkImageLayout src_layout,
2753 VkImageLayout dst_layout,
2754 uint32_t src_family,
2755 uint32_t dst_family,
2756 const VkImageSubresourceRange *range,
2757 VkImageAspectFlags pending_clears)
2758 {
2759 if (image->exclusive && src_family != dst_family) {
2760 /* This is an acquire or a release operation and there will be
2761 * a corresponding release/acquire. Do the transition in the
2762 * most flexible queue. */
2763
2764 assert(src_family == cmd_buffer->queue_family_index ||
2765 dst_family == cmd_buffer->queue_family_index);
2766
2767 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
2768 return;
2769
2770 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
2771 (src_family == RADV_QUEUE_GENERAL ||
2772 dst_family == RADV_QUEUE_GENERAL))
2773 return;
2774 }
2775
2776 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
2777 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
2778
2779 if (image->surface.htile_size)
2780 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2781 dst_layout, range, pending_clears);
2782
2783 if (image->cmask.size)
2784 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2785 dst_layout, src_queue_mask,
2786 dst_queue_mask, range,
2787 pending_clears);
2788
2789 if (image->surface.dcc_size)
2790 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2791 dst_layout, src_queue_mask,
2792 dst_queue_mask, range,
2793 pending_clears);
2794 }
2795
2796 void radv_CmdPipelineBarrier(
2797 VkCommandBuffer commandBuffer,
2798 VkPipelineStageFlags srcStageMask,
2799 VkPipelineStageFlags destStageMask,
2800 VkBool32 byRegion,
2801 uint32_t memoryBarrierCount,
2802 const VkMemoryBarrier* pMemoryBarriers,
2803 uint32_t bufferMemoryBarrierCount,
2804 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2805 uint32_t imageMemoryBarrierCount,
2806 const VkImageMemoryBarrier* pImageMemoryBarriers)
2807 {
2808 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2809 enum radv_cmd_flush_bits src_flush_bits = 0;
2810 enum radv_cmd_flush_bits dst_flush_bits = 0;
2811
2812 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2813 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
2814 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
2815 NULL);
2816 }
2817
2818 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2819 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
2820 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
2821 NULL);
2822 }
2823
2824 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2825 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2826 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
2827 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
2828 image);
2829 }
2830
2831 radv_stage_flush(cmd_buffer, srcStageMask);
2832 cmd_buffer->state.flush_bits |= src_flush_bits;
2833
2834 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2835 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2836 radv_handle_image_transition(cmd_buffer, image,
2837 pImageMemoryBarriers[i].oldLayout,
2838 pImageMemoryBarriers[i].newLayout,
2839 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2840 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2841 &pImageMemoryBarriers[i].subresourceRange,
2842 0);
2843 }
2844
2845 cmd_buffer->state.flush_bits |= dst_flush_bits;
2846 }
2847
2848
2849 static void write_event(struct radv_cmd_buffer *cmd_buffer,
2850 struct radv_event *event,
2851 VkPipelineStageFlags stageMask,
2852 unsigned value)
2853 {
2854 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2855 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2856
2857 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2858
2859 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
2860
2861 /* TODO: this is overkill. Probably should figure something out from
2862 * the stage mask. */
2863
2864 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
2865 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2866 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2867 EVENT_INDEX(5));
2868 radeon_emit(cs, va);
2869 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2870 radeon_emit(cs, 2);
2871 radeon_emit(cs, 0);
2872 }
2873
2874 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2875 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2876 EVENT_INDEX(5));
2877 radeon_emit(cs, va);
2878 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2879 radeon_emit(cs, value);
2880 radeon_emit(cs, 0);
2881
2882 assert(cmd_buffer->cs->cdw <= cdw_max);
2883 }
2884
2885 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
2886 VkEvent _event,
2887 VkPipelineStageFlags stageMask)
2888 {
2889 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2890 RADV_FROM_HANDLE(radv_event, event, _event);
2891
2892 write_event(cmd_buffer, event, stageMask, 1);
2893 }
2894
2895 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
2896 VkEvent _event,
2897 VkPipelineStageFlags stageMask)
2898 {
2899 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2900 RADV_FROM_HANDLE(radv_event, event, _event);
2901
2902 write_event(cmd_buffer, event, stageMask, 0);
2903 }
2904
2905 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
2906 uint32_t eventCount,
2907 const VkEvent* pEvents,
2908 VkPipelineStageFlags srcStageMask,
2909 VkPipelineStageFlags dstStageMask,
2910 uint32_t memoryBarrierCount,
2911 const VkMemoryBarrier* pMemoryBarriers,
2912 uint32_t bufferMemoryBarrierCount,
2913 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2914 uint32_t imageMemoryBarrierCount,
2915 const VkImageMemoryBarrier* pImageMemoryBarriers)
2916 {
2917 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2918 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2919
2920 for (unsigned i = 0; i < eventCount; ++i) {
2921 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
2922 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2923
2924 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2925
2926 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
2927
2928 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
2929 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
2930 radeon_emit(cs, va);
2931 radeon_emit(cs, va >> 32);
2932 radeon_emit(cs, 1); /* reference value */
2933 radeon_emit(cs, 0xffffffff); /* mask */
2934 radeon_emit(cs, 4); /* poll interval */
2935
2936 assert(cmd_buffer->cs->cdw <= cdw_max);
2937 }
2938
2939
2940 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2941 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2942
2943 radv_handle_image_transition(cmd_buffer, image,
2944 pImageMemoryBarriers[i].oldLayout,
2945 pImageMemoryBarriers[i].newLayout,
2946 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2947 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2948 &pImageMemoryBarriers[i].subresourceRange,
2949 0);
2950 }
2951
2952 /* TODO: figure out how to do memory barriers without waiting */
2953 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
2954 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2955 RADV_CMD_FLAG_INV_VMEM_L1 |
2956 RADV_CMD_FLAG_INV_SMEM_L1;
2957 }