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ac/surface: remove RADEON_SURF_HAS_TILE_MODE_INDEX
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "gfx9d.h"
33 #include "vk_format.h"
34 #include "radv_meta.h"
35
36 #include "ac_debug.h"
37
38 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
39 struct radv_image *image,
40 VkImageLayout src_layout,
41 VkImageLayout dst_layout,
42 uint32_t src_family,
43 uint32_t dst_family,
44 const VkImageSubresourceRange *range,
45 VkImageAspectFlags pending_clears);
46
47 const struct radv_dynamic_state default_dynamic_state = {
48 .viewport = {
49 .count = 0,
50 },
51 .scissor = {
52 .count = 0,
53 },
54 .line_width = 1.0f,
55 .depth_bias = {
56 .bias = 0.0f,
57 .clamp = 0.0f,
58 .slope = 0.0f,
59 },
60 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
61 .depth_bounds = {
62 .min = 0.0f,
63 .max = 1.0f,
64 },
65 .stencil_compare_mask = {
66 .front = ~0u,
67 .back = ~0u,
68 },
69 .stencil_write_mask = {
70 .front = ~0u,
71 .back = ~0u,
72 },
73 .stencil_reference = {
74 .front = 0u,
75 .back = 0u,
76 },
77 };
78
79 void
80 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
81 const struct radv_dynamic_state *src,
82 uint32_t copy_mask)
83 {
84 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
85 dest->viewport.count = src->viewport.count;
86 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
87 src->viewport.count);
88 }
89
90 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
91 dest->scissor.count = src->scissor.count;
92 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
93 src->scissor.count);
94 }
95
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
97 dest->line_width = src->line_width;
98
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
100 dest->depth_bias = src->depth_bias;
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
103 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
106 dest->depth_bounds = src->depth_bounds;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
109 dest->stencil_compare_mask = src->stencil_compare_mask;
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
112 dest->stencil_write_mask = src->stencil_write_mask;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
115 dest->stencil_reference = src->stencil_reference;
116 }
117
118 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
119 {
120 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
121 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
122 }
123
124 enum ring_type radv_queue_family_to_ring(int f) {
125 switch (f) {
126 case RADV_QUEUE_GENERAL:
127 return RING_GFX;
128 case RADV_QUEUE_COMPUTE:
129 return RING_COMPUTE;
130 case RADV_QUEUE_TRANSFER:
131 return RING_DMA;
132 default:
133 unreachable("Unknown queue family");
134 }
135 }
136
137 static VkResult radv_create_cmd_buffer(
138 struct radv_device * device,
139 struct radv_cmd_pool * pool,
140 VkCommandBufferLevel level,
141 VkCommandBuffer* pCommandBuffer)
142 {
143 struct radv_cmd_buffer *cmd_buffer;
144 VkResult result;
145 unsigned ring;
146 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
147 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
148 if (cmd_buffer == NULL)
149 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
150
151 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
152 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
153 cmd_buffer->device = device;
154 cmd_buffer->pool = pool;
155 cmd_buffer->level = level;
156
157 if (pool) {
158 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
159 cmd_buffer->queue_family_index = pool->queue_family_index;
160
161 } else {
162 /* Init the pool_link so we can safefly call list_del when we destroy
163 * the command buffer
164 */
165 list_inithead(&cmd_buffer->pool_link);
166 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
167 }
168
169 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
170
171 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
172 if (!cmd_buffer->cs) {
173 result = VK_ERROR_OUT_OF_HOST_MEMORY;
174 goto fail;
175 }
176
177 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
178
179 cmd_buffer->upload.offset = 0;
180 cmd_buffer->upload.size = 0;
181 list_inithead(&cmd_buffer->upload.list);
182
183 return VK_SUCCESS;
184
185 fail:
186 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
187
188 return result;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
211 {
212
213 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
214
215 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
216 &cmd_buffer->upload.list, list) {
217 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
218 list_del(&up->list);
219 free(up);
220 }
221
222 cmd_buffer->scratch_size_needed = 0;
223 cmd_buffer->compute_scratch_size_needed = 0;
224 cmd_buffer->esgs_ring_size_needed = 0;
225 cmd_buffer->gsvs_ring_size_needed = 0;
226 cmd_buffer->tess_rings_needed = false;
227 cmd_buffer->sample_positions_needed = false;
228
229 if (cmd_buffer->upload.upload_bo)
230 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
231 cmd_buffer->upload.upload_bo, 8);
232 cmd_buffer->upload.offset = 0;
233
234 cmd_buffer->record_fail = false;
235
236 cmd_buffer->ring_offsets_idx = -1;
237
238 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
239 void *fence_ptr;
240 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
241 &cmd_buffer->gfx9_fence_offset,
242 &fence_ptr);
243 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
244 }
245 }
246
247 static bool
248 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
249 uint64_t min_needed)
250 {
251 uint64_t new_size;
252 struct radeon_winsys_bo *bo;
253 struct radv_cmd_buffer_upload *upload;
254 struct radv_device *device = cmd_buffer->device;
255
256 new_size = MAX2(min_needed, 16 * 1024);
257 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
258
259 bo = device->ws->buffer_create(device->ws,
260 new_size, 4096,
261 RADEON_DOMAIN_GTT,
262 RADEON_FLAG_CPU_ACCESS);
263
264 if (!bo) {
265 cmd_buffer->record_fail = true;
266 return false;
267 }
268
269 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
270 if (cmd_buffer->upload.upload_bo) {
271 upload = malloc(sizeof(*upload));
272
273 if (!upload) {
274 cmd_buffer->record_fail = true;
275 device->ws->buffer_destroy(bo);
276 return false;
277 }
278
279 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
280 list_add(&upload->list, &cmd_buffer->upload.list);
281 }
282
283 cmd_buffer->upload.upload_bo = bo;
284 cmd_buffer->upload.size = new_size;
285 cmd_buffer->upload.offset = 0;
286 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
287
288 if (!cmd_buffer->upload.map) {
289 cmd_buffer->record_fail = true;
290 return false;
291 }
292
293 return true;
294 }
295
296 bool
297 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
298 unsigned size,
299 unsigned alignment,
300 unsigned *out_offset,
301 void **ptr)
302 {
303 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
304 if (offset + size > cmd_buffer->upload.size) {
305 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
306 return false;
307 offset = 0;
308 }
309
310 *out_offset = offset;
311 *ptr = cmd_buffer->upload.map + offset;
312
313 cmd_buffer->upload.offset = offset + size;
314 return true;
315 }
316
317 bool
318 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
319 unsigned size, unsigned alignment,
320 const void *data, unsigned *out_offset)
321 {
322 uint8_t *ptr;
323
324 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
325 out_offset, (void **)&ptr))
326 return false;
327
328 if (ptr)
329 memcpy(ptr, data, size);
330
331 return true;
332 }
333
334 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
335 {
336 struct radv_device *device = cmd_buffer->device;
337 struct radeon_winsys_cs *cs = cmd_buffer->cs;
338 uint64_t va;
339
340 if (!device->trace_bo)
341 return;
342
343 va = device->ws->buffer_get_va(device->trace_bo);
344
345 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
346
347 ++cmd_buffer->state.trace_id;
348 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
349 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
350 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
351 S_370_WR_CONFIRM(1) |
352 S_370_ENGINE_SEL(V_370_ME));
353 radeon_emit(cs, va);
354 radeon_emit(cs, va >> 32);
355 radeon_emit(cs, cmd_buffer->state.trace_id);
356 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
357 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
358 }
359
360 static void
361 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
362 struct radv_pipeline *pipeline)
363 {
364 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
365 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
366 8);
367 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
369
370 if (cmd_buffer->device->physical_device->has_rbplus) {
371 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
372 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
373 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
374 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
375 }
376 }
377
378 static void
379 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
380 struct radv_pipeline *pipeline)
381 {
382 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
383 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
384 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
385
386 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
387 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
388 }
389
390 /* 12.4 fixed-point */
391 static unsigned radv_pack_float_12p4(float x)
392 {
393 return x <= 0 ? 0 :
394 x >= 4096 ? 0xffff : x * 16;
395 }
396
397 uint32_t
398 radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
399 {
400 switch (stage) {
401 case MESA_SHADER_FRAGMENT:
402 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
403 case MESA_SHADER_VERTEX:
404 if (has_tess)
405 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
406 else
407 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
408 case MESA_SHADER_GEOMETRY:
409 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
410 case MESA_SHADER_COMPUTE:
411 return R_00B900_COMPUTE_USER_DATA_0;
412 case MESA_SHADER_TESS_CTRL:
413 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
414 case MESA_SHADER_TESS_EVAL:
415 if (has_gs)
416 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
417 else
418 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
419 default:
420 unreachable("unknown shader");
421 }
422 }
423
424 struct ac_userdata_info *
425 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
426 gl_shader_stage stage,
427 int idx)
428 {
429 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
430 }
431
432 static void
433 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
434 struct radv_pipeline *pipeline,
435 gl_shader_stage stage,
436 int idx, uint64_t va)
437 {
438 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
439 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
440 if (loc->sgpr_idx == -1)
441 return;
442 assert(loc->num_sgprs == 2);
443 assert(!loc->indirect);
444 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
445 radeon_emit(cmd_buffer->cs, va);
446 radeon_emit(cmd_buffer->cs, va >> 32);
447 }
448
449 static void
450 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
451 struct radv_pipeline *pipeline)
452 {
453 int num_samples = pipeline->graphics.ms.num_samples;
454 struct radv_multisample_state *ms = &pipeline->graphics.ms;
455 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
456
457 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
458 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
459 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
460
461 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
462 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
463
464 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
465 return;
466
467 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
468 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
469 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
470
471 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
472
473 /* GFX9: Flush DFSM when the AA mode changes. */
474 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
475 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
476 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
477 }
478 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
479 uint32_t offset;
480 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
481 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
482 if (loc->sgpr_idx == -1)
483 return;
484 assert(loc->num_sgprs == 1);
485 assert(!loc->indirect);
486 switch (num_samples) {
487 default:
488 offset = 0;
489 break;
490 case 2:
491 offset = 1;
492 break;
493 case 4:
494 offset = 3;
495 break;
496 case 8:
497 offset = 7;
498 break;
499 case 16:
500 offset = 15;
501 break;
502 }
503
504 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
505 cmd_buffer->sample_positions_needed = true;
506 }
507 }
508
509 static void
510 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
511 struct radv_pipeline *pipeline)
512 {
513 struct radv_raster_state *raster = &pipeline->graphics.raster;
514
515 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
516 raster->pa_cl_clip_cntl);
517
518 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
519 raster->spi_interp_control);
520
521 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
522 unsigned tmp = (unsigned)(1.0 * 8.0);
523 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
524 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
525 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
526
527 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
528 raster->pa_su_vtx_cntl);
529
530 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
531 raster->pa_su_sc_mode_cntl);
532 }
533
534 static inline void
535 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
536 unsigned size)
537 {
538 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
539 si_cp_dma_prefetch(cmd_buffer, va, size);
540 }
541
542 static void
543 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
544 struct radv_pipeline *pipeline,
545 struct radv_shader_variant *shader,
546 struct ac_vs_output_info *outinfo)
547 {
548 struct radeon_winsys *ws = cmd_buffer->device->ws;
549 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
550 unsigned export_count;
551
552 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
553 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
554
555 export_count = MAX2(1, outinfo->param_exports);
556 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
557 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
558
559 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
560 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
561 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
562 V_02870C_SPI_SHADER_4COMP :
563 V_02870C_SPI_SHADER_NONE) |
564 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
565 V_02870C_SPI_SHADER_4COMP :
566 V_02870C_SPI_SHADER_NONE) |
567 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
568 V_02870C_SPI_SHADER_4COMP :
569 V_02870C_SPI_SHADER_NONE));
570
571
572 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
573 radeon_emit(cmd_buffer->cs, va >> 8);
574 radeon_emit(cmd_buffer->cs, va >> 40);
575 radeon_emit(cmd_buffer->cs, shader->rsrc1);
576 radeon_emit(cmd_buffer->cs, shader->rsrc2);
577
578 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
579 S_028818_VTX_W0_FMT(1) |
580 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
581 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
582 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
583
584
585 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
586 pipeline->graphics.pa_cl_vs_out_cntl);
587
588 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
589 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
590 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
591 }
592
593 static void
594 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
595 struct radv_shader_variant *shader,
596 struct ac_es_output_info *outinfo)
597 {
598 struct radeon_winsys *ws = cmd_buffer->device->ws;
599 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
600
601 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
602 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
603
604 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
605 outinfo->esgs_itemsize / 4);
606 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
607 radeon_emit(cmd_buffer->cs, va >> 8);
608 radeon_emit(cmd_buffer->cs, va >> 40);
609 radeon_emit(cmd_buffer->cs, shader->rsrc1);
610 radeon_emit(cmd_buffer->cs, shader->rsrc2);
611 }
612
613 static void
614 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
615 struct radv_shader_variant *shader)
616 {
617 struct radeon_winsys *ws = cmd_buffer->device->ws;
618 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
619 uint32_t rsrc2 = shader->rsrc2;
620
621 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
622 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
623
624 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
625 radeon_emit(cmd_buffer->cs, va >> 8);
626 radeon_emit(cmd_buffer->cs, va >> 40);
627
628 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
629 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
630 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
631 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
632
633 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
634 radeon_emit(cmd_buffer->cs, shader->rsrc1);
635 radeon_emit(cmd_buffer->cs, rsrc2);
636 }
637
638 static void
639 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
640 struct radv_shader_variant *shader)
641 {
642 struct radeon_winsys *ws = cmd_buffer->device->ws;
643 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
644
645 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
646 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
647
648 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
649 radeon_emit(cmd_buffer->cs, va >> 8);
650 radeon_emit(cmd_buffer->cs, va >> 40);
651 radeon_emit(cmd_buffer->cs, shader->rsrc1);
652 radeon_emit(cmd_buffer->cs, shader->rsrc2);
653 }
654
655 static void
656 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
657 struct radv_pipeline *pipeline)
658 {
659 struct radv_shader_variant *vs;
660
661 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
662
663 vs = pipeline->shaders[MESA_SHADER_VERTEX];
664
665 if (vs->info.vs.as_ls)
666 radv_emit_hw_ls(cmd_buffer, vs);
667 else if (vs->info.vs.as_es)
668 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
669 else
670 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
671
672 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
673 }
674
675
676 static void
677 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
678 struct radv_pipeline *pipeline)
679 {
680 if (!radv_pipeline_has_tess(pipeline))
681 return;
682
683 struct radv_shader_variant *tes, *tcs;
684
685 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
686 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
687
688 if (tes->info.tes.as_es)
689 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
690 else
691 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
692
693 radv_emit_hw_hs(cmd_buffer, tcs);
694
695 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
696 pipeline->graphics.tess.tf_param);
697
698 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
699 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
700 pipeline->graphics.tess.ls_hs_config);
701 else
702 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
703 pipeline->graphics.tess.ls_hs_config);
704
705 struct ac_userdata_info *loc;
706
707 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
708 if (loc->sgpr_idx != -1) {
709 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
710 assert(loc->num_sgprs == 4);
711 assert(!loc->indirect);
712 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
713 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
714 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
715 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
716 pipeline->graphics.tess.num_tcs_input_cp << 26);
717 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
718 }
719
720 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
721 if (loc->sgpr_idx != -1) {
722 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
723 assert(loc->num_sgprs == 1);
724 assert(!loc->indirect);
725
726 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
727 pipeline->graphics.tess.offchip_layout);
728 }
729
730 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
731 if (loc->sgpr_idx != -1) {
732 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
733 assert(loc->num_sgprs == 1);
734 assert(!loc->indirect);
735
736 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
737 pipeline->graphics.tess.tcs_in_layout);
738 }
739 }
740
741 static void
742 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
743 struct radv_pipeline *pipeline)
744 {
745 struct radeon_winsys *ws = cmd_buffer->device->ws;
746 struct radv_shader_variant *gs;
747 uint64_t va;
748
749 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
750
751 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
752 if (!gs)
753 return;
754
755 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
756
757 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
758 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
759 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
760 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
761
762 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
763
764 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
765
766 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
767 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
768 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
769 radeon_emit(cmd_buffer->cs, 0);
770 radeon_emit(cmd_buffer->cs, 0);
771 radeon_emit(cmd_buffer->cs, 0);
772
773 uint32_t gs_num_invocations = gs->info.gs.invocations;
774 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
775 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
776 S_028B90_ENABLE(gs_num_invocations > 0));
777
778 va = ws->buffer_get_va(gs->bo) + gs->bo_offset;
779 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
780 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
781
782 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
783 radeon_emit(cmd_buffer->cs, va >> 8);
784 radeon_emit(cmd_buffer->cs, va >> 40);
785 radeon_emit(cmd_buffer->cs, gs->rsrc1);
786 radeon_emit(cmd_buffer->cs, gs->rsrc2);
787
788 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
789
790 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
791 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
792 if (loc->sgpr_idx != -1) {
793 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
794 uint32_t num_entries = 64;
795 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
796
797 if (is_vi)
798 num_entries *= stride;
799
800 stride = S_008F04_STRIDE(stride);
801 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
802 radeon_emit(cmd_buffer->cs, stride);
803 radeon_emit(cmd_buffer->cs, num_entries);
804 }
805 }
806
807 static void
808 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
809 struct radv_pipeline *pipeline)
810 {
811 struct radeon_winsys *ws = cmd_buffer->device->ws;
812 struct radv_shader_variant *ps;
813 uint64_t va;
814 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
815 struct radv_blend_state *blend = &pipeline->graphics.blend;
816 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
817
818 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
819 va = ws->buffer_get_va(ps->bo) + ps->bo_offset;
820 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
821 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
822
823 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
824 radeon_emit(cmd_buffer->cs, va >> 8);
825 radeon_emit(cmd_buffer->cs, va >> 40);
826 radeon_emit(cmd_buffer->cs, ps->rsrc1);
827 radeon_emit(cmd_buffer->cs, ps->rsrc2);
828
829 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
830 pipeline->graphics.db_shader_control);
831
832 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
833 ps->config.spi_ps_input_ena);
834
835 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
836 ps->config.spi_ps_input_addr);
837
838 if (ps->info.info.ps.force_persample)
839 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
840
841 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
842 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
843
844 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
845
846 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
847 pipeline->graphics.shader_z_format);
848
849 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
850
851 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
852 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
853
854 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
855 /* optimise this? */
856 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
857 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
858 }
859
860 if (pipeline->graphics.ps_input_cntl_num) {
861 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
862 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
863 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
864 }
865 }
866 }
867
868 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
869 struct radv_pipeline *pipeline)
870 {
871 uint32_t vtx_reuse_depth = 30;
872 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
873 return;
874
875 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
876 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
877 vtx_reuse_depth = 14;
878 }
879 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
880 vtx_reuse_depth);
881 }
882
883 static void
884 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
885 struct radv_pipeline *pipeline)
886 {
887 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
888 return;
889
890 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
891 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
892 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
893 radv_update_multisample_state(cmd_buffer, pipeline);
894 radv_emit_vertex_shader(cmd_buffer, pipeline);
895 radv_emit_tess_shaders(cmd_buffer, pipeline);
896 radv_emit_geometry_shader(cmd_buffer, pipeline);
897 radv_emit_fragment_shader(cmd_buffer, pipeline);
898 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
899
900 cmd_buffer->scratch_size_needed =
901 MAX2(cmd_buffer->scratch_size_needed,
902 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
903
904 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
905 S_0286E8_WAVES(pipeline->max_waves) |
906 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
907
908 if (!cmd_buffer->state.emitted_pipeline ||
909 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
910 pipeline->graphics.can_use_guardband)
911 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
912
913 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
914
915 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
916 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
917 } else {
918 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
919 }
920 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
921
922 cmd_buffer->state.emitted_pipeline = pipeline;
923 }
924
925 static void
926 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
927 {
928 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
929 cmd_buffer->state.dynamic.viewport.viewports);
930 }
931
932 static void
933 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
934 {
935 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
936 si_write_scissors(cmd_buffer->cs, 0, count,
937 cmd_buffer->state.dynamic.scissor.scissors,
938 cmd_buffer->state.dynamic.viewport.viewports,
939 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
940 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
941 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
942 }
943
944 static void
945 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
946 int index,
947 struct radv_color_buffer_info *cb)
948 {
949 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
950
951 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
952 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
953 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
954 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
955 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
956 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
957 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
958 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
959 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
960 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
961 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
962 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
963 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
964
965 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
966 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
967 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
968
969 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
970 cb->gfx9_epitch);
971 } else {
972 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
973 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
974 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
975 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
976 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
977 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
978 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
979 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
980 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
981 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
982 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
983 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
984
985 if (is_vi) { /* DCC BASE */
986 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
987 }
988 }
989 }
990
991 static void
992 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
993 struct radv_ds_buffer_info *ds,
994 struct radv_image *image,
995 VkImageLayout layout)
996 {
997 uint32_t db_z_info = ds->db_z_info;
998 uint32_t db_stencil_info = ds->db_stencil_info;
999
1000 if (!radv_layout_has_htile(image, layout,
1001 radv_image_queue_family_mask(image,
1002 cmd_buffer->queue_family_index,
1003 cmd_buffer->queue_family_index))) {
1004 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1005 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1006 }
1007
1008 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1009
1010 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1011 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1012 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1013 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1014 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1015
1016 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1017 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1018 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1019 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1020 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1021 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1022 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1023 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1024 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1025 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1026 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1027
1028 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1029 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1030 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1031 } else {
1032 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1033
1034 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1035 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1036 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1037 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1038 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1039 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1040 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1041 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1042 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1043 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1044
1045 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1046 }
1047
1048 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1049 ds->pa_su_poly_offset_db_fmt_cntl);
1050 }
1051
1052 void
1053 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1054 struct radv_image *image,
1055 VkClearDepthStencilValue ds_clear_value,
1056 VkImageAspectFlags aspects)
1057 {
1058 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1059 va += image->offset + image->clear_value_offset;
1060 unsigned reg_offset = 0, reg_count = 0;
1061
1062 if (!image->surface.htile_size || !aspects)
1063 return;
1064
1065 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1066 ++reg_count;
1067 } else {
1068 ++reg_offset;
1069 va += 4;
1070 }
1071 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1072 ++reg_count;
1073
1074 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1075
1076 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1077 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1078 S_370_WR_CONFIRM(1) |
1079 S_370_ENGINE_SEL(V_370_PFP));
1080 radeon_emit(cmd_buffer->cs, va);
1081 radeon_emit(cmd_buffer->cs, va >> 32);
1082 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1083 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1084 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1085 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1086
1087 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1088 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1089 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1090 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1091 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1092 }
1093
1094 static void
1095 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1096 struct radv_image *image)
1097 {
1098 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1099 va += image->offset + image->clear_value_offset;
1100
1101 if (!image->surface.htile_size)
1102 return;
1103
1104 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1105
1106 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1107 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1108 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1109 COPY_DATA_COUNT_SEL);
1110 radeon_emit(cmd_buffer->cs, va);
1111 radeon_emit(cmd_buffer->cs, va >> 32);
1112 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1113 radeon_emit(cmd_buffer->cs, 0);
1114
1115 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1116 radeon_emit(cmd_buffer->cs, 0);
1117 }
1118
1119 /*
1120 *with DCC some colors don't require CMASK elimiation before being
1121 * used as a texture. This sets a predicate value to determine if the
1122 * cmask eliminate is required.
1123 */
1124 void
1125 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1126 struct radv_image *image,
1127 bool value)
1128 {
1129 uint64_t pred_val = value;
1130 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1131 va += image->offset + image->dcc_pred_offset;
1132
1133 if (!image->surface.dcc_size)
1134 return;
1135
1136 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1137
1138 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1139 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1140 S_370_WR_CONFIRM(1) |
1141 S_370_ENGINE_SEL(V_370_PFP));
1142 radeon_emit(cmd_buffer->cs, va);
1143 radeon_emit(cmd_buffer->cs, va >> 32);
1144 radeon_emit(cmd_buffer->cs, pred_val);
1145 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1146 }
1147
1148 void
1149 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1150 struct radv_image *image,
1151 int idx,
1152 uint32_t color_values[2])
1153 {
1154 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1155 va += image->offset + image->clear_value_offset;
1156
1157 if (!image->cmask.size && !image->surface.dcc_size)
1158 return;
1159
1160 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1161
1162 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1163 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1164 S_370_WR_CONFIRM(1) |
1165 S_370_ENGINE_SEL(V_370_PFP));
1166 radeon_emit(cmd_buffer->cs, va);
1167 radeon_emit(cmd_buffer->cs, va >> 32);
1168 radeon_emit(cmd_buffer->cs, color_values[0]);
1169 radeon_emit(cmd_buffer->cs, color_values[1]);
1170
1171 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1172 radeon_emit(cmd_buffer->cs, color_values[0]);
1173 radeon_emit(cmd_buffer->cs, color_values[1]);
1174 }
1175
1176 static void
1177 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1178 struct radv_image *image,
1179 int idx)
1180 {
1181 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1182 va += image->offset + image->clear_value_offset;
1183
1184 if (!image->cmask.size && !image->surface.dcc_size)
1185 return;
1186
1187 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1188 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1189
1190 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1191 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1192 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1193 COPY_DATA_COUNT_SEL);
1194 radeon_emit(cmd_buffer->cs, va);
1195 radeon_emit(cmd_buffer->cs, va >> 32);
1196 radeon_emit(cmd_buffer->cs, reg >> 2);
1197 radeon_emit(cmd_buffer->cs, 0);
1198
1199 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1200 radeon_emit(cmd_buffer->cs, 0);
1201 }
1202
1203 void
1204 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1205 {
1206 int i;
1207 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1208 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1209
1210 for (i = 0; i < 8; ++i) {
1211 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1212 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1213 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1214 continue;
1215 }
1216
1217 int idx = subpass->color_attachments[i].attachment;
1218 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1219
1220 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1221
1222 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1223 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1224
1225 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1226 }
1227
1228 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1229 int idx = subpass->depth_stencil_attachment.attachment;
1230 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1231 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1232 struct radv_image *image = att->attachment->image;
1233 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1234 uint32_t queue_mask = radv_image_queue_family_mask(image,
1235 cmd_buffer->queue_family_index,
1236 cmd_buffer->queue_family_index);
1237 /* We currently don't support writing decompressed HTILE */
1238 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1239 radv_layout_is_htile_compressed(image, layout, queue_mask));
1240
1241 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1242
1243 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1244 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1245 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1246 }
1247 radv_load_depth_clear_regs(cmd_buffer, image);
1248 } else {
1249 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1250 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1251 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1252 }
1253 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1254 S_028208_BR_X(framebuffer->width) |
1255 S_028208_BR_Y(framebuffer->height));
1256
1257 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1258 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1259 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1260 }
1261 }
1262
1263 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1264 {
1265 uint32_t db_count_control;
1266
1267 if(!cmd_buffer->state.active_occlusion_queries) {
1268 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1269 db_count_control = 0;
1270 } else {
1271 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1272 }
1273 } else {
1274 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1275 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1276 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1277 S_028004_ZPASS_ENABLE(1) |
1278 S_028004_SLICE_EVEN_ENABLE(1) |
1279 S_028004_SLICE_ODD_ENABLE(1);
1280 } else {
1281 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1282 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1283 }
1284 }
1285
1286 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1287 }
1288
1289 static void
1290 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1291 {
1292 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1293
1294 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1295 return;
1296
1297 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1298 radv_emit_viewport(cmd_buffer);
1299
1300 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1301 radv_emit_scissor(cmd_buffer);
1302
1303 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1304 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1305 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1306 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1307 }
1308
1309 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1310 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1311 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1312 }
1313
1314 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1315 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1316 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1317 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1318 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1319 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1320 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1321 S_028430_STENCILOPVAL(1));
1322 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1323 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1324 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1325 S_028434_STENCILOPVAL_BF(1));
1326 }
1327
1328 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1329 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1330 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1331 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1332 }
1333
1334 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1335 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1336 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1337 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1338 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1339
1340 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1341 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1342 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1343 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1344 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1345 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1346 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1347 }
1348 }
1349
1350 cmd_buffer->state.dirty = 0;
1351 }
1352
1353 static void
1354 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1355 struct radv_pipeline *pipeline,
1356 int idx,
1357 uint64_t va,
1358 gl_shader_stage stage)
1359 {
1360 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1361 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1362
1363 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1364 return;
1365
1366 assert(!desc_set_loc->indirect);
1367 assert(desc_set_loc->num_sgprs == 2);
1368 radeon_set_sh_reg_seq(cmd_buffer->cs,
1369 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1370 radeon_emit(cmd_buffer->cs, va);
1371 radeon_emit(cmd_buffer->cs, va >> 32);
1372 }
1373
1374 static void
1375 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1376 VkShaderStageFlags stages,
1377 struct radv_descriptor_set *set,
1378 unsigned idx)
1379 {
1380 if (cmd_buffer->state.pipeline) {
1381 radv_foreach_stage(stage, stages) {
1382 if (cmd_buffer->state.pipeline->shaders[stage])
1383 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1384 idx, set->va,
1385 stage);
1386 }
1387 }
1388
1389 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1390 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1391 idx, set->va,
1392 MESA_SHADER_COMPUTE);
1393 }
1394
1395 static void
1396 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1397 {
1398 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1399 uint32_t *ptr = NULL;
1400 unsigned bo_offset;
1401
1402 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1403 &bo_offset,
1404 (void**) &ptr))
1405 return;
1406
1407 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1408 set->va += bo_offset;
1409
1410 memcpy(ptr, set->mapped_ptr, set->size);
1411 }
1412
1413 static void
1414 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1415 {
1416 uint32_t size = MAX_SETS * 2 * 4;
1417 uint32_t offset;
1418 void *ptr;
1419
1420 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1421 256, &offset, &ptr))
1422 return;
1423
1424 for (unsigned i = 0; i < MAX_SETS; i++) {
1425 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1426 uint64_t set_va = 0;
1427 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1428 if (set)
1429 set_va = set->va;
1430 uptr[0] = set_va & 0xffffffff;
1431 uptr[1] = set_va >> 32;
1432 }
1433
1434 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1435 va += offset;
1436
1437 if (cmd_buffer->state.pipeline) {
1438 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1439 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1440 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1441
1442 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1443 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1444 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1445
1446 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1447 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1448 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1449
1450 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1451 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1452 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1453
1454 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1455 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1456 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1457 }
1458
1459 if (cmd_buffer->state.compute_pipeline)
1460 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1461 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1462 }
1463
1464 static void
1465 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1466 VkShaderStageFlags stages)
1467 {
1468 unsigned i;
1469
1470 if (!cmd_buffer->state.descriptors_dirty)
1471 return;
1472
1473 if (cmd_buffer->state.push_descriptors_dirty)
1474 radv_flush_push_descriptors(cmd_buffer);
1475
1476 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1477 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1478 radv_flush_indirect_descriptor_sets(cmd_buffer);
1479 }
1480
1481 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1482 cmd_buffer->cs,
1483 MAX_SETS * MESA_SHADER_STAGES * 4);
1484
1485 for (i = 0; i < MAX_SETS; i++) {
1486 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1487 continue;
1488 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1489 if (!set)
1490 continue;
1491
1492 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1493 }
1494 cmd_buffer->state.descriptors_dirty = 0;
1495 cmd_buffer->state.push_descriptors_dirty = false;
1496 assert(cmd_buffer->cs->cdw <= cdw_max);
1497 }
1498
1499 static void
1500 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1501 struct radv_pipeline *pipeline,
1502 VkShaderStageFlags stages)
1503 {
1504 struct radv_pipeline_layout *layout = pipeline->layout;
1505 unsigned offset;
1506 void *ptr;
1507 uint64_t va;
1508
1509 stages &= cmd_buffer->push_constant_stages;
1510 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1511 return;
1512
1513 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1514 16 * layout->dynamic_offset_count,
1515 256, &offset, &ptr))
1516 return;
1517
1518 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1519 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1520 16 * layout->dynamic_offset_count);
1521
1522 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1523 va += offset;
1524
1525 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1526 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1527
1528 radv_foreach_stage(stage, stages) {
1529 if (pipeline->shaders[stage]) {
1530 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1531 AC_UD_PUSH_CONSTANTS, va);
1532 }
1533 }
1534
1535 cmd_buffer->push_constant_stages &= ~stages;
1536 assert(cmd_buffer->cs->cdw <= cdw_max);
1537 }
1538
1539 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1540 bool indexed_draw)
1541 {
1542 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1543
1544 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1545 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1546 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1547 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1548 primitive_reset_en);
1549 } else {
1550 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1551 primitive_reset_en);
1552 }
1553 }
1554
1555 if (primitive_reset_en) {
1556 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1557
1558 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1559 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1560 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1561 primitive_reset_index);
1562 }
1563 }
1564 }
1565
1566 static void
1567 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1568 {
1569 struct radv_device *device = cmd_buffer->device;
1570
1571 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1572 cmd_buffer->state.pipeline->num_vertex_attribs &&
1573 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1574 unsigned vb_offset;
1575 void *vb_ptr;
1576 uint32_t i = 0;
1577 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1578 uint64_t va;
1579
1580 /* allocate some descriptor state for vertex buffers */
1581 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1582 &vb_offset, &vb_ptr);
1583
1584 for (i = 0; i < num_attribs; i++) {
1585 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1586 uint32_t offset;
1587 int vb = cmd_buffer->state.pipeline->va_binding[i];
1588 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1589 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1590
1591 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1592 va = device->ws->buffer_get_va(buffer->bo);
1593
1594 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1595 va += offset + buffer->offset;
1596 desc[0] = va;
1597 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1598 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1599 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1600 else
1601 desc[2] = buffer->size - offset;
1602 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1603 }
1604
1605 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1606 va += vb_offset;
1607
1608 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1609 AC_UD_VS_VERTEX_BUFFERS, va);
1610 }
1611 cmd_buffer->state.vb_dirty = 0;
1612 }
1613
1614 static void
1615 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1616 bool indexed_draw, bool instanced_draw,
1617 bool indirect_draw,
1618 uint32_t draw_vertex_count)
1619 {
1620 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1621 uint32_t ia_multi_vgt_param;
1622
1623 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1624 cmd_buffer->cs, 4096);
1625
1626 radv_cmd_buffer_update_vertex_descriptors(cmd_buffer);
1627
1628 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1629 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1630
1631 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1632 radv_emit_framebuffer_state(cmd_buffer);
1633
1634 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1635 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1636 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1637 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1638 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1639 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1640 else
1641 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1642 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1643 }
1644
1645 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1646
1647 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1648
1649 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1650 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1651 VK_SHADER_STAGE_ALL_GRAPHICS);
1652
1653 assert(cmd_buffer->cs->cdw <= cdw_max);
1654
1655 si_emit_cache_flush(cmd_buffer);
1656 }
1657
1658 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1659 VkPipelineStageFlags src_stage_mask)
1660 {
1661 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1662 VK_PIPELINE_STAGE_TRANSFER_BIT |
1663 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1664 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1665 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1666 }
1667
1668 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1669 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1670 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1671 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1672 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1673 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1674 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1675 VK_PIPELINE_STAGE_TRANSFER_BIT |
1676 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1677 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1678 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1679 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1680 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1681 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1682 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1683 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1684 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1685 }
1686 }
1687
1688 static enum radv_cmd_flush_bits
1689 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1690 VkAccessFlags src_flags)
1691 {
1692 enum radv_cmd_flush_bits flush_bits = 0;
1693 uint32_t b;
1694 for_each_bit(b, src_flags) {
1695 switch ((VkAccessFlagBits)(1 << b)) {
1696 case VK_ACCESS_SHADER_WRITE_BIT:
1697 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1698 break;
1699 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1700 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1701 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1702 break;
1703 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1704 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1705 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1706 break;
1707 case VK_ACCESS_TRANSFER_WRITE_BIT:
1708 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1709 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1710 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1711 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1712 RADV_CMD_FLAG_INV_GLOBAL_L2;
1713 break;
1714 default:
1715 break;
1716 }
1717 }
1718 return flush_bits;
1719 }
1720
1721 static enum radv_cmd_flush_bits
1722 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1723 VkAccessFlags dst_flags,
1724 struct radv_image *image)
1725 {
1726 enum radv_cmd_flush_bits flush_bits = 0;
1727 uint32_t b;
1728 for_each_bit(b, dst_flags) {
1729 switch ((VkAccessFlagBits)(1 << b)) {
1730 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1731 case VK_ACCESS_INDEX_READ_BIT:
1732 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1733 break;
1734 case VK_ACCESS_UNIFORM_READ_BIT:
1735 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1736 break;
1737 case VK_ACCESS_SHADER_READ_BIT:
1738 case VK_ACCESS_TRANSFER_READ_BIT:
1739 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1740 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1741 RADV_CMD_FLAG_INV_GLOBAL_L2;
1742 break;
1743 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1744 /* TODO: change to image && when the image gets passed
1745 * through from the subpass. */
1746 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1747 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1748 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1749 break;
1750 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1751 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1752 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1753 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1754 break;
1755 default:
1756 break;
1757 }
1758 }
1759 return flush_bits;
1760 }
1761
1762 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1763 {
1764 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1765 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1766 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1767 NULL);
1768 }
1769
1770 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1771 VkAttachmentReference att)
1772 {
1773 unsigned idx = att.attachment;
1774 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1775 VkImageSubresourceRange range;
1776 range.aspectMask = 0;
1777 range.baseMipLevel = view->base_mip;
1778 range.levelCount = 1;
1779 range.baseArrayLayer = view->base_layer;
1780 range.layerCount = cmd_buffer->state.framebuffer->layers;
1781
1782 radv_handle_image_transition(cmd_buffer,
1783 view->image,
1784 cmd_buffer->state.attachments[idx].current_layout,
1785 att.layout, 0, 0, &range,
1786 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1787
1788 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1789
1790
1791 }
1792
1793 void
1794 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1795 const struct radv_subpass *subpass, bool transitions)
1796 {
1797 if (transitions) {
1798 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1799
1800 for (unsigned i = 0; i < subpass->color_count; ++i) {
1801 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1802 radv_handle_subpass_image_transition(cmd_buffer,
1803 subpass->color_attachments[i]);
1804 }
1805
1806 for (unsigned i = 0; i < subpass->input_count; ++i) {
1807 radv_handle_subpass_image_transition(cmd_buffer,
1808 subpass->input_attachments[i]);
1809 }
1810
1811 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1812 radv_handle_subpass_image_transition(cmd_buffer,
1813 subpass->depth_stencil_attachment);
1814 }
1815 }
1816
1817 cmd_buffer->state.subpass = subpass;
1818
1819 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1820 }
1821
1822 static void
1823 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1824 struct radv_render_pass *pass,
1825 const VkRenderPassBeginInfo *info)
1826 {
1827 struct radv_cmd_state *state = &cmd_buffer->state;
1828
1829 if (pass->attachment_count == 0) {
1830 state->attachments = NULL;
1831 return;
1832 }
1833
1834 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1835 pass->attachment_count *
1836 sizeof(state->attachments[0]),
1837 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1838 if (state->attachments == NULL) {
1839 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1840 abort();
1841 }
1842
1843 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1844 struct radv_render_pass_attachment *att = &pass->attachments[i];
1845 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1846 VkImageAspectFlags clear_aspects = 0;
1847
1848 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1849 /* color attachment */
1850 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1851 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1852 }
1853 } else {
1854 /* depthstencil attachment */
1855 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1856 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1857 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1858 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1859 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1860 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1861 }
1862 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1863 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1864 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1865 }
1866 }
1867
1868 state->attachments[i].pending_clear_aspects = clear_aspects;
1869 if (clear_aspects && info) {
1870 assert(info->clearValueCount > i);
1871 state->attachments[i].clear_value = info->pClearValues[i];
1872 }
1873
1874 state->attachments[i].current_layout = att->initial_layout;
1875 }
1876 }
1877
1878 VkResult radv_AllocateCommandBuffers(
1879 VkDevice _device,
1880 const VkCommandBufferAllocateInfo *pAllocateInfo,
1881 VkCommandBuffer *pCommandBuffers)
1882 {
1883 RADV_FROM_HANDLE(radv_device, device, _device);
1884 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1885
1886 VkResult result = VK_SUCCESS;
1887 uint32_t i;
1888
1889 memset(pCommandBuffers, 0,
1890 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1891
1892 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1893
1894 if (!list_empty(&pool->free_cmd_buffers)) {
1895 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1896
1897 list_del(&cmd_buffer->pool_link);
1898 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1899
1900 radv_reset_cmd_buffer(cmd_buffer);
1901 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1902 cmd_buffer->level = pAllocateInfo->level;
1903
1904 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1905 result = VK_SUCCESS;
1906 } else {
1907 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1908 &pCommandBuffers[i]);
1909 }
1910 if (result != VK_SUCCESS)
1911 break;
1912 }
1913
1914 if (result != VK_SUCCESS)
1915 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1916 i, pCommandBuffers);
1917
1918 return result;
1919 }
1920
1921 void radv_FreeCommandBuffers(
1922 VkDevice device,
1923 VkCommandPool commandPool,
1924 uint32_t commandBufferCount,
1925 const VkCommandBuffer *pCommandBuffers)
1926 {
1927 for (uint32_t i = 0; i < commandBufferCount; i++) {
1928 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1929
1930 if (cmd_buffer) {
1931 if (cmd_buffer->pool) {
1932 list_del(&cmd_buffer->pool_link);
1933 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1934 } else
1935 radv_cmd_buffer_destroy(cmd_buffer);
1936
1937 }
1938 }
1939 }
1940
1941 VkResult radv_ResetCommandBuffer(
1942 VkCommandBuffer commandBuffer,
1943 VkCommandBufferResetFlags flags)
1944 {
1945 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1946 radv_reset_cmd_buffer(cmd_buffer);
1947 return VK_SUCCESS;
1948 }
1949
1950 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1951 {
1952 struct radv_device *device = cmd_buffer->device;
1953 if (device->gfx_init) {
1954 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1955 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1956 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1957 radeon_emit(cmd_buffer->cs, va);
1958 radeon_emit(cmd_buffer->cs, va >> 32);
1959 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1960 } else
1961 si_init_config(cmd_buffer);
1962 }
1963
1964 VkResult radv_BeginCommandBuffer(
1965 VkCommandBuffer commandBuffer,
1966 const VkCommandBufferBeginInfo *pBeginInfo)
1967 {
1968 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1969 radv_reset_cmd_buffer(cmd_buffer);
1970
1971 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1972 cmd_buffer->state.last_primitive_reset_en = -1;
1973
1974 /* setup initial configuration into command buffer */
1975 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1976 switch (cmd_buffer->queue_family_index) {
1977 case RADV_QUEUE_GENERAL:
1978 emit_gfx_buffer_state(cmd_buffer);
1979 radv_set_db_count_control(cmd_buffer);
1980 break;
1981 case RADV_QUEUE_COMPUTE:
1982 si_init_compute(cmd_buffer);
1983 break;
1984 case RADV_QUEUE_TRANSFER:
1985 default:
1986 break;
1987 }
1988 }
1989
1990 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1991 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1992 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1993
1994 struct radv_subpass *subpass =
1995 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1996
1997 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1998 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1999 }
2000
2001 radv_cmd_buffer_trace_emit(cmd_buffer);
2002 return VK_SUCCESS;
2003 }
2004
2005 void radv_CmdBindVertexBuffers(
2006 VkCommandBuffer commandBuffer,
2007 uint32_t firstBinding,
2008 uint32_t bindingCount,
2009 const VkBuffer* pBuffers,
2010 const VkDeviceSize* pOffsets)
2011 {
2012 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2013 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2014
2015 /* We have to defer setting up vertex buffer since we need the buffer
2016 * stride from the pipeline. */
2017
2018 assert(firstBinding + bindingCount < MAX_VBS);
2019 for (uint32_t i = 0; i < bindingCount; i++) {
2020 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2021 vb[firstBinding + i].offset = pOffsets[i];
2022 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
2023 }
2024 }
2025
2026 void radv_CmdBindIndexBuffer(
2027 VkCommandBuffer commandBuffer,
2028 VkBuffer buffer,
2029 VkDeviceSize offset,
2030 VkIndexType indexType)
2031 {
2032 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2033 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2034
2035 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2036 cmd_buffer->state.index_va = cmd_buffer->device->ws->buffer_get_va(index_buffer->bo);
2037 cmd_buffer->state.index_va += index_buffer->offset + offset;
2038
2039 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2040 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2041 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2042 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2043 }
2044
2045
2046 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2047 struct radv_descriptor_set *set,
2048 unsigned idx)
2049 {
2050 struct radeon_winsys *ws = cmd_buffer->device->ws;
2051
2052 cmd_buffer->state.descriptors[idx] = set;
2053 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2054 if (!set)
2055 return;
2056
2057 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2058
2059 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2060 if (set->descriptors[j])
2061 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2062
2063 if(set->bo)
2064 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2065 }
2066
2067 void radv_CmdBindDescriptorSets(
2068 VkCommandBuffer commandBuffer,
2069 VkPipelineBindPoint pipelineBindPoint,
2070 VkPipelineLayout _layout,
2071 uint32_t firstSet,
2072 uint32_t descriptorSetCount,
2073 const VkDescriptorSet* pDescriptorSets,
2074 uint32_t dynamicOffsetCount,
2075 const uint32_t* pDynamicOffsets)
2076 {
2077 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2078 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2079 unsigned dyn_idx = 0;
2080
2081 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2082 unsigned idx = i + firstSet;
2083 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2084 radv_bind_descriptor_set(cmd_buffer, set, idx);
2085
2086 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2087 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2088 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2089 assert(dyn_idx < dynamicOffsetCount);
2090
2091 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2092 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2093 dst[0] = va;
2094 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2095 dst[2] = range->size;
2096 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2097 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2098 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2099 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2100 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2101 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2102 cmd_buffer->push_constant_stages |=
2103 set->layout->dynamic_shader_stages;
2104 }
2105 }
2106 }
2107
2108 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2109 struct radv_descriptor_set *set,
2110 struct radv_descriptor_set_layout *layout)
2111 {
2112 set->size = layout->size;
2113 set->layout = layout;
2114
2115 if (cmd_buffer->push_descriptors.capacity < set->size) {
2116 size_t new_size = MAX2(set->size, 1024);
2117 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2118 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2119
2120 free(set->mapped_ptr);
2121 set->mapped_ptr = malloc(new_size);
2122
2123 if (!set->mapped_ptr) {
2124 cmd_buffer->push_descriptors.capacity = 0;
2125 cmd_buffer->record_fail = true;
2126 return false;
2127 }
2128
2129 cmd_buffer->push_descriptors.capacity = new_size;
2130 }
2131
2132 return true;
2133 }
2134
2135 void radv_meta_push_descriptor_set(
2136 struct radv_cmd_buffer* cmd_buffer,
2137 VkPipelineBindPoint pipelineBindPoint,
2138 VkPipelineLayout _layout,
2139 uint32_t set,
2140 uint32_t descriptorWriteCount,
2141 const VkWriteDescriptorSet* pDescriptorWrites)
2142 {
2143 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2144 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2145 unsigned bo_offset;
2146
2147 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2148
2149 push_set->size = layout->set[set].layout->size;
2150 push_set->layout = layout->set[set].layout;
2151
2152 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2153 &bo_offset,
2154 (void**) &push_set->mapped_ptr))
2155 return;
2156
2157 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2158 push_set->va += bo_offset;
2159
2160 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2161 radv_descriptor_set_to_handle(push_set),
2162 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2163
2164 cmd_buffer->state.descriptors[set] = push_set;
2165 cmd_buffer->state.descriptors_dirty |= (1u << set);
2166 }
2167
2168 void radv_CmdPushDescriptorSetKHR(
2169 VkCommandBuffer commandBuffer,
2170 VkPipelineBindPoint pipelineBindPoint,
2171 VkPipelineLayout _layout,
2172 uint32_t set,
2173 uint32_t descriptorWriteCount,
2174 const VkWriteDescriptorSet* pDescriptorWrites)
2175 {
2176 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2177 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2178 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2179
2180 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2181
2182 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2183 return;
2184
2185 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2186 radv_descriptor_set_to_handle(push_set),
2187 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2188
2189 cmd_buffer->state.descriptors[set] = push_set;
2190 cmd_buffer->state.descriptors_dirty |= (1u << set);
2191 cmd_buffer->state.push_descriptors_dirty = true;
2192 }
2193
2194 void radv_CmdPushDescriptorSetWithTemplateKHR(
2195 VkCommandBuffer commandBuffer,
2196 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2197 VkPipelineLayout _layout,
2198 uint32_t set,
2199 const void* pData)
2200 {
2201 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2202 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2203 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2204
2205 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2206
2207 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2208 return;
2209
2210 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2211 descriptorUpdateTemplate, pData);
2212
2213 cmd_buffer->state.descriptors[set] = push_set;
2214 cmd_buffer->state.descriptors_dirty |= (1u << set);
2215 cmd_buffer->state.push_descriptors_dirty = true;
2216 }
2217
2218 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2219 VkPipelineLayout layout,
2220 VkShaderStageFlags stageFlags,
2221 uint32_t offset,
2222 uint32_t size,
2223 const void* pValues)
2224 {
2225 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2226 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2227 cmd_buffer->push_constant_stages |= stageFlags;
2228 }
2229
2230 VkResult radv_EndCommandBuffer(
2231 VkCommandBuffer commandBuffer)
2232 {
2233 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2234
2235 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
2236 si_emit_cache_flush(cmd_buffer);
2237
2238 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
2239 cmd_buffer->record_fail)
2240 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2241 return VK_SUCCESS;
2242 }
2243
2244 static void
2245 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2246 {
2247 struct radeon_winsys *ws = cmd_buffer->device->ws;
2248 struct radv_shader_variant *compute_shader;
2249 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2250 uint64_t va;
2251
2252 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2253 return;
2254
2255 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2256
2257 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2258 va = ws->buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2259
2260 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2261 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2262
2263 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2264 cmd_buffer->cs, 16);
2265
2266 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2267 radeon_emit(cmd_buffer->cs, va >> 8);
2268 radeon_emit(cmd_buffer->cs, va >> 40);
2269
2270 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2271 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2272 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2273
2274
2275 cmd_buffer->compute_scratch_size_needed =
2276 MAX2(cmd_buffer->compute_scratch_size_needed,
2277 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2278
2279 /* change these once we have scratch support */
2280 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2281 S_00B860_WAVES(pipeline->max_waves) |
2282 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2283
2284 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2285 radeon_emit(cmd_buffer->cs,
2286 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2287 radeon_emit(cmd_buffer->cs,
2288 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2289 radeon_emit(cmd_buffer->cs,
2290 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2291
2292 assert(cmd_buffer->cs->cdw <= cdw_max);
2293 }
2294
2295 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2296 {
2297 for (unsigned i = 0; i < MAX_SETS; i++) {
2298 if (cmd_buffer->state.descriptors[i])
2299 cmd_buffer->state.descriptors_dirty |= (1u << i);
2300 }
2301 }
2302
2303 void radv_CmdBindPipeline(
2304 VkCommandBuffer commandBuffer,
2305 VkPipelineBindPoint pipelineBindPoint,
2306 VkPipeline _pipeline)
2307 {
2308 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2309 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2310
2311 radv_mark_descriptor_sets_dirty(cmd_buffer);
2312
2313 switch (pipelineBindPoint) {
2314 case VK_PIPELINE_BIND_POINT_COMPUTE:
2315 cmd_buffer->state.compute_pipeline = pipeline;
2316 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2317 break;
2318 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2319 cmd_buffer->state.pipeline = pipeline;
2320 if (!pipeline)
2321 break;
2322
2323 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2324 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2325
2326 /* Apply the dynamic state from the pipeline */
2327 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2328 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2329 &pipeline->dynamic_state,
2330 pipeline->dynamic_state_mask);
2331
2332 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2333 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2334 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2335 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2336
2337 if (radv_pipeline_has_tess(pipeline))
2338 cmd_buffer->tess_rings_needed = true;
2339
2340 if (radv_pipeline_has_gs(pipeline)) {
2341 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2342 AC_UD_SCRATCH_RING_OFFSETS);
2343 if (cmd_buffer->ring_offsets_idx == -1)
2344 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2345 else if (loc->sgpr_idx != -1)
2346 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2347 }
2348 break;
2349 default:
2350 assert(!"invalid bind point");
2351 break;
2352 }
2353 }
2354
2355 void radv_CmdSetViewport(
2356 VkCommandBuffer commandBuffer,
2357 uint32_t firstViewport,
2358 uint32_t viewportCount,
2359 const VkViewport* pViewports)
2360 {
2361 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2362
2363 const uint32_t total_count = firstViewport + viewportCount;
2364 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2365 cmd_buffer->state.dynamic.viewport.count = total_count;
2366
2367 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2368 pViewports, viewportCount * sizeof(*pViewports));
2369
2370 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2371 }
2372
2373 void radv_CmdSetScissor(
2374 VkCommandBuffer commandBuffer,
2375 uint32_t firstScissor,
2376 uint32_t scissorCount,
2377 const VkRect2D* pScissors)
2378 {
2379 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2380
2381 const uint32_t total_count = firstScissor + scissorCount;
2382 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2383 cmd_buffer->state.dynamic.scissor.count = total_count;
2384
2385 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2386 pScissors, scissorCount * sizeof(*pScissors));
2387 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2388 }
2389
2390 void radv_CmdSetLineWidth(
2391 VkCommandBuffer commandBuffer,
2392 float lineWidth)
2393 {
2394 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2395 cmd_buffer->state.dynamic.line_width = lineWidth;
2396 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2397 }
2398
2399 void radv_CmdSetDepthBias(
2400 VkCommandBuffer commandBuffer,
2401 float depthBiasConstantFactor,
2402 float depthBiasClamp,
2403 float depthBiasSlopeFactor)
2404 {
2405 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2406
2407 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2408 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2409 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2410
2411 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2412 }
2413
2414 void radv_CmdSetBlendConstants(
2415 VkCommandBuffer commandBuffer,
2416 const float blendConstants[4])
2417 {
2418 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2419
2420 memcpy(cmd_buffer->state.dynamic.blend_constants,
2421 blendConstants, sizeof(float) * 4);
2422
2423 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2424 }
2425
2426 void radv_CmdSetDepthBounds(
2427 VkCommandBuffer commandBuffer,
2428 float minDepthBounds,
2429 float maxDepthBounds)
2430 {
2431 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2432
2433 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2434 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2435
2436 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2437 }
2438
2439 void radv_CmdSetStencilCompareMask(
2440 VkCommandBuffer commandBuffer,
2441 VkStencilFaceFlags faceMask,
2442 uint32_t compareMask)
2443 {
2444 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2445
2446 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2447 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2448 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2449 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2450
2451 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2452 }
2453
2454 void radv_CmdSetStencilWriteMask(
2455 VkCommandBuffer commandBuffer,
2456 VkStencilFaceFlags faceMask,
2457 uint32_t writeMask)
2458 {
2459 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2460
2461 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2462 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2463 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2464 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2465
2466 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2467 }
2468
2469 void radv_CmdSetStencilReference(
2470 VkCommandBuffer commandBuffer,
2471 VkStencilFaceFlags faceMask,
2472 uint32_t reference)
2473 {
2474 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2475
2476 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2477 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2478 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2479 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2480
2481 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2482 }
2483
2484 void radv_CmdExecuteCommands(
2485 VkCommandBuffer commandBuffer,
2486 uint32_t commandBufferCount,
2487 const VkCommandBuffer* pCmdBuffers)
2488 {
2489 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2490
2491 /* Emit pending flushes on primary prior to executing secondary */
2492 si_emit_cache_flush(primary);
2493
2494 for (uint32_t i = 0; i < commandBufferCount; i++) {
2495 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2496
2497 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2498 secondary->scratch_size_needed);
2499 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2500 secondary->compute_scratch_size_needed);
2501
2502 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2503 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2504 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2505 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2506 if (secondary->tess_rings_needed)
2507 primary->tess_rings_needed = true;
2508 if (secondary->sample_positions_needed)
2509 primary->sample_positions_needed = true;
2510
2511 if (secondary->ring_offsets_idx != -1) {
2512 if (primary->ring_offsets_idx == -1)
2513 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2514 else
2515 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2516 }
2517 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2518 }
2519
2520 /* if we execute secondary we need to re-emit out pipelines */
2521 if (commandBufferCount) {
2522 primary->state.emitted_pipeline = NULL;
2523 primary->state.emitted_compute_pipeline = NULL;
2524 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2525 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2526 primary->state.last_primitive_reset_en = -1;
2527 primary->state.last_primitive_reset_index = 0;
2528 radv_mark_descriptor_sets_dirty(primary);
2529 }
2530 }
2531
2532 VkResult radv_CreateCommandPool(
2533 VkDevice _device,
2534 const VkCommandPoolCreateInfo* pCreateInfo,
2535 const VkAllocationCallbacks* pAllocator,
2536 VkCommandPool* pCmdPool)
2537 {
2538 RADV_FROM_HANDLE(radv_device, device, _device);
2539 struct radv_cmd_pool *pool;
2540
2541 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2542 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2543 if (pool == NULL)
2544 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2545
2546 if (pAllocator)
2547 pool->alloc = *pAllocator;
2548 else
2549 pool->alloc = device->alloc;
2550
2551 list_inithead(&pool->cmd_buffers);
2552 list_inithead(&pool->free_cmd_buffers);
2553
2554 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2555
2556 *pCmdPool = radv_cmd_pool_to_handle(pool);
2557
2558 return VK_SUCCESS;
2559
2560 }
2561
2562 void radv_DestroyCommandPool(
2563 VkDevice _device,
2564 VkCommandPool commandPool,
2565 const VkAllocationCallbacks* pAllocator)
2566 {
2567 RADV_FROM_HANDLE(radv_device, device, _device);
2568 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2569
2570 if (!pool)
2571 return;
2572
2573 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2574 &pool->cmd_buffers, pool_link) {
2575 radv_cmd_buffer_destroy(cmd_buffer);
2576 }
2577
2578 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2579 &pool->free_cmd_buffers, pool_link) {
2580 radv_cmd_buffer_destroy(cmd_buffer);
2581 }
2582
2583 vk_free2(&device->alloc, pAllocator, pool);
2584 }
2585
2586 VkResult radv_ResetCommandPool(
2587 VkDevice device,
2588 VkCommandPool commandPool,
2589 VkCommandPoolResetFlags flags)
2590 {
2591 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2592
2593 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2594 &pool->cmd_buffers, pool_link) {
2595 radv_reset_cmd_buffer(cmd_buffer);
2596 }
2597
2598 return VK_SUCCESS;
2599 }
2600
2601 void radv_TrimCommandPoolKHR(
2602 VkDevice device,
2603 VkCommandPool commandPool,
2604 VkCommandPoolTrimFlagsKHR flags)
2605 {
2606 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2607
2608 if (!pool)
2609 return;
2610
2611 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2612 &pool->free_cmd_buffers, pool_link) {
2613 radv_cmd_buffer_destroy(cmd_buffer);
2614 }
2615 }
2616
2617 void radv_CmdBeginRenderPass(
2618 VkCommandBuffer commandBuffer,
2619 const VkRenderPassBeginInfo* pRenderPassBegin,
2620 VkSubpassContents contents)
2621 {
2622 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2623 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2624 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2625
2626 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2627 cmd_buffer->cs, 2048);
2628
2629 cmd_buffer->state.framebuffer = framebuffer;
2630 cmd_buffer->state.pass = pass;
2631 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2632 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2633
2634 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2635 assert(cmd_buffer->cs->cdw <= cdw_max);
2636
2637 radv_cmd_buffer_clear_subpass(cmd_buffer);
2638 }
2639
2640 void radv_CmdNextSubpass(
2641 VkCommandBuffer commandBuffer,
2642 VkSubpassContents contents)
2643 {
2644 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2645
2646 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2647
2648 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2649 2048);
2650
2651 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2652 radv_cmd_buffer_clear_subpass(cmd_buffer);
2653 }
2654
2655 void radv_CmdDraw(
2656 VkCommandBuffer commandBuffer,
2657 uint32_t vertexCount,
2658 uint32_t instanceCount,
2659 uint32_t firstVertex,
2660 uint32_t firstInstance)
2661 {
2662 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2663
2664 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2665
2666 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2667
2668 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2669 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2670 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2671 radeon_emit(cmd_buffer->cs, firstVertex);
2672 radeon_emit(cmd_buffer->cs, firstInstance);
2673 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2674 radeon_emit(cmd_buffer->cs, 0);
2675
2676 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
2677 radeon_emit(cmd_buffer->cs, instanceCount);
2678
2679 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2680 radeon_emit(cmd_buffer->cs, vertexCount);
2681 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2682 S_0287F0_USE_OPAQUE(0));
2683
2684 assert(cmd_buffer->cs->cdw <= cdw_max);
2685
2686 radv_cmd_buffer_trace_emit(cmd_buffer);
2687 }
2688
2689 void radv_CmdDrawIndexed(
2690 VkCommandBuffer commandBuffer,
2691 uint32_t indexCount,
2692 uint32_t instanceCount,
2693 uint32_t firstIndex,
2694 int32_t vertexOffset,
2695 uint32_t firstInstance)
2696 {
2697 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2698 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2699 uint64_t index_va;
2700
2701 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2702
2703 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2704
2705 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2706 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
2707 2, cmd_buffer->state.index_type);
2708 } else {
2709 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2710 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2711 }
2712
2713 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2714 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2715 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2716 radeon_emit(cmd_buffer->cs, vertexOffset);
2717 radeon_emit(cmd_buffer->cs, firstInstance);
2718 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2719 radeon_emit(cmd_buffer->cs, 0);
2720
2721 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2722 radeon_emit(cmd_buffer->cs, instanceCount);
2723
2724 index_va = cmd_buffer->state.index_va;
2725 index_va += firstIndex * index_size;
2726 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2727 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2728 radeon_emit(cmd_buffer->cs, index_va);
2729 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2730 radeon_emit(cmd_buffer->cs, indexCount);
2731 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2732
2733 assert(cmd_buffer->cs->cdw <= cdw_max);
2734 radv_cmd_buffer_trace_emit(cmd_buffer);
2735 }
2736
2737 static void
2738 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2739 VkBuffer _buffer,
2740 VkDeviceSize offset,
2741 VkBuffer _count_buffer,
2742 VkDeviceSize count_offset,
2743 uint32_t draw_count,
2744 uint32_t stride,
2745 bool indexed)
2746 {
2747 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2748 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2749 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2750 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2751 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2752 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2753 indirect_va += offset + buffer->offset;
2754 uint64_t count_va = 0;
2755
2756 if (count_buffer) {
2757 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2758 count_va += count_offset + count_buffer->offset;
2759 }
2760
2761 if (!draw_count)
2762 return;
2763
2764 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2765 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2766 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2767 assert(base_reg);
2768
2769 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2770 radeon_emit(cs, 1);
2771 radeon_emit(cs, indirect_va);
2772 radeon_emit(cs, indirect_va >> 32);
2773
2774 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2775 PKT3_DRAW_INDIRECT_MULTI,
2776 8, false));
2777 radeon_emit(cs, 0);
2778 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2779 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2780 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2781 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2782 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2783 radeon_emit(cs, draw_count); /* count */
2784 radeon_emit(cs, count_va); /* count_addr */
2785 radeon_emit(cs, count_va >> 32);
2786 radeon_emit(cs, stride); /* stride */
2787 radeon_emit(cs, di_src_sel);
2788 radv_cmd_buffer_trace_emit(cmd_buffer);
2789 }
2790
2791 static void
2792 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2793 VkBuffer buffer,
2794 VkDeviceSize offset,
2795 VkBuffer countBuffer,
2796 VkDeviceSize countBufferOffset,
2797 uint32_t maxDrawCount,
2798 uint32_t stride)
2799 {
2800 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2801 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2802
2803 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2804 cmd_buffer->cs, 14);
2805
2806 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2807 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2808
2809 assert(cmd_buffer->cs->cdw <= cdw_max);
2810 }
2811
2812 static void
2813 radv_cmd_draw_indexed_indirect_count(
2814 VkCommandBuffer commandBuffer,
2815 VkBuffer buffer,
2816 VkDeviceSize offset,
2817 VkBuffer countBuffer,
2818 VkDeviceSize countBufferOffset,
2819 uint32_t maxDrawCount,
2820 uint32_t stride)
2821 {
2822 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2823 uint64_t index_va;
2824 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2825
2826 index_va = cmd_buffer->state.index_va;
2827
2828 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2829
2830 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2831 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2832
2833 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2834 radeon_emit(cmd_buffer->cs, index_va);
2835 radeon_emit(cmd_buffer->cs, index_va >> 32);
2836
2837 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2838 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2839
2840 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2841 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2842
2843 assert(cmd_buffer->cs->cdw <= cdw_max);
2844 }
2845
2846 void radv_CmdDrawIndirect(
2847 VkCommandBuffer commandBuffer,
2848 VkBuffer buffer,
2849 VkDeviceSize offset,
2850 uint32_t drawCount,
2851 uint32_t stride)
2852 {
2853 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2854 VK_NULL_HANDLE, 0, drawCount, stride);
2855 }
2856
2857 void radv_CmdDrawIndexedIndirect(
2858 VkCommandBuffer commandBuffer,
2859 VkBuffer buffer,
2860 VkDeviceSize offset,
2861 uint32_t drawCount,
2862 uint32_t stride)
2863 {
2864 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2865 VK_NULL_HANDLE, 0, drawCount, stride);
2866 }
2867
2868 void radv_CmdDrawIndirectCountAMD(
2869 VkCommandBuffer commandBuffer,
2870 VkBuffer buffer,
2871 VkDeviceSize offset,
2872 VkBuffer countBuffer,
2873 VkDeviceSize countBufferOffset,
2874 uint32_t maxDrawCount,
2875 uint32_t stride)
2876 {
2877 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2878 countBuffer, countBufferOffset,
2879 maxDrawCount, stride);
2880 }
2881
2882 void radv_CmdDrawIndexedIndirectCountAMD(
2883 VkCommandBuffer commandBuffer,
2884 VkBuffer buffer,
2885 VkDeviceSize offset,
2886 VkBuffer countBuffer,
2887 VkDeviceSize countBufferOffset,
2888 uint32_t maxDrawCount,
2889 uint32_t stride)
2890 {
2891 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2892 countBuffer, countBufferOffset,
2893 maxDrawCount, stride);
2894 }
2895
2896 static void
2897 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2898 {
2899 radv_emit_compute_pipeline(cmd_buffer);
2900 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
2901 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2902 VK_SHADER_STAGE_COMPUTE_BIT);
2903 si_emit_cache_flush(cmd_buffer);
2904 }
2905
2906 void radv_CmdDispatch(
2907 VkCommandBuffer commandBuffer,
2908 uint32_t x,
2909 uint32_t y,
2910 uint32_t z)
2911 {
2912 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2913
2914 radv_flush_compute_state(cmd_buffer);
2915
2916 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2917
2918 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2919 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2920 if (loc->sgpr_idx != -1) {
2921 assert(!loc->indirect);
2922 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2923 assert(loc->num_sgprs == grid_used);
2924 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2925 radeon_emit(cmd_buffer->cs, x);
2926 if (grid_used > 1)
2927 radeon_emit(cmd_buffer->cs, y);
2928 if (grid_used > 2)
2929 radeon_emit(cmd_buffer->cs, z);
2930 }
2931
2932 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2933 PKT3_SHADER_TYPE_S(1));
2934 radeon_emit(cmd_buffer->cs, x);
2935 radeon_emit(cmd_buffer->cs, y);
2936 radeon_emit(cmd_buffer->cs, z);
2937 radeon_emit(cmd_buffer->cs, 1);
2938
2939 assert(cmd_buffer->cs->cdw <= cdw_max);
2940 radv_cmd_buffer_trace_emit(cmd_buffer);
2941 }
2942
2943 void radv_CmdDispatchIndirect(
2944 VkCommandBuffer commandBuffer,
2945 VkBuffer _buffer,
2946 VkDeviceSize offset)
2947 {
2948 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2949 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2950 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2951 va += buffer->offset + offset;
2952
2953 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2954
2955 radv_flush_compute_state(cmd_buffer);
2956
2957 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2958 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2959 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2960 if (loc->sgpr_idx != -1) {
2961 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2962 for (unsigned i = 0; i < grid_used; ++i) {
2963 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2964 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2965 COPY_DATA_DST_SEL(COPY_DATA_REG));
2966 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2967 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2968 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2969 radeon_emit(cmd_buffer->cs, 0);
2970 }
2971 }
2972
2973 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2974 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2975 PKT3_SHADER_TYPE_S(1));
2976 radeon_emit(cmd_buffer->cs, va);
2977 radeon_emit(cmd_buffer->cs, va >> 32);
2978 radeon_emit(cmd_buffer->cs, 1);
2979 } else {
2980 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2981 PKT3_SHADER_TYPE_S(1));
2982 radeon_emit(cmd_buffer->cs, 1);
2983 radeon_emit(cmd_buffer->cs, va);
2984 radeon_emit(cmd_buffer->cs, va >> 32);
2985
2986 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2987 PKT3_SHADER_TYPE_S(1));
2988 radeon_emit(cmd_buffer->cs, 0);
2989 radeon_emit(cmd_buffer->cs, 1);
2990 }
2991
2992 assert(cmd_buffer->cs->cdw <= cdw_max);
2993 radv_cmd_buffer_trace_emit(cmd_buffer);
2994 }
2995
2996 void radv_unaligned_dispatch(
2997 struct radv_cmd_buffer *cmd_buffer,
2998 uint32_t x,
2999 uint32_t y,
3000 uint32_t z)
3001 {
3002 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3003 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3004 uint32_t blocks[3], remainder[3];
3005
3006 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
3007 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
3008 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
3009
3010 /* If aligned, these should be an entire block size, not 0 */
3011 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
3012 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
3013 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
3014
3015 radv_flush_compute_state(cmd_buffer);
3016
3017 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
3018
3019 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3020 radeon_emit(cmd_buffer->cs,
3021 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
3022 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3023 radeon_emit(cmd_buffer->cs,
3024 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
3025 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3026 radeon_emit(cmd_buffer->cs,
3027 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
3028 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3029
3030 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3031 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3032 if (loc->sgpr_idx != -1) {
3033 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3034 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
3035 radeon_emit(cmd_buffer->cs, blocks[0]);
3036 if (grid_used > 1)
3037 radeon_emit(cmd_buffer->cs, blocks[1]);
3038 if (grid_used > 2)
3039 radeon_emit(cmd_buffer->cs, blocks[2]);
3040 }
3041 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3042 PKT3_SHADER_TYPE_S(1));
3043 radeon_emit(cmd_buffer->cs, blocks[0]);
3044 radeon_emit(cmd_buffer->cs, blocks[1]);
3045 radeon_emit(cmd_buffer->cs, blocks[2]);
3046 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
3047 S_00B800_PARTIAL_TG_EN(1));
3048
3049 assert(cmd_buffer->cs->cdw <= cdw_max);
3050 radv_cmd_buffer_trace_emit(cmd_buffer);
3051 }
3052
3053 void radv_CmdEndRenderPass(
3054 VkCommandBuffer commandBuffer)
3055 {
3056 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3057
3058 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3059
3060 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3061
3062 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3063 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3064 radv_handle_subpass_image_transition(cmd_buffer,
3065 (VkAttachmentReference){i, layout});
3066 }
3067
3068 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3069
3070 cmd_buffer->state.pass = NULL;
3071 cmd_buffer->state.subpass = NULL;
3072 cmd_buffer->state.attachments = NULL;
3073 cmd_buffer->state.framebuffer = NULL;
3074 }
3075
3076 /*
3077 * For HTILE we have the following interesting clear words:
3078 * 0x0000030f: Uncompressed.
3079 * 0xfffffff0: Clear depth to 1.0
3080 * 0x00000000: Clear depth to 0.0
3081 */
3082 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3083 struct radv_image *image,
3084 const VkImageSubresourceRange *range,
3085 uint32_t clear_word)
3086 {
3087 assert(range->baseMipLevel == 0);
3088 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3089 unsigned layer_count = radv_get_layerCount(image, range);
3090 uint64_t size = image->surface.htile_slice_size * layer_count;
3091 uint64_t offset = image->offset + image->htile_offset +
3092 image->surface.htile_slice_size * range->baseArrayLayer;
3093
3094 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3095 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3096
3097 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3098
3099 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3100 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3101 RADV_CMD_FLAG_INV_VMEM_L1 |
3102 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3103 }
3104
3105 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3106 struct radv_image *image,
3107 VkImageLayout src_layout,
3108 VkImageLayout dst_layout,
3109 unsigned src_queue_mask,
3110 unsigned dst_queue_mask,
3111 const VkImageSubresourceRange *range,
3112 VkImageAspectFlags pending_clears)
3113 {
3114 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3115 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3116 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3117 cmd_buffer->state.render_area.extent.width == image->info.width &&
3118 cmd_buffer->state.render_area.extent.height == image->info.height) {
3119 /* The clear will initialize htile. */
3120 return;
3121 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3122 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3123 /* TODO: merge with the clear if applicable */
3124 radv_initialize_htile(cmd_buffer, image, range, 0);
3125 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3126 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3127 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3128 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3129 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3130 VkImageSubresourceRange local_range = *range;
3131 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3132 local_range.baseMipLevel = 0;
3133 local_range.levelCount = 1;
3134
3135 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3136 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3137
3138 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3139
3140 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3141 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3142 }
3143 }
3144
3145 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3146 struct radv_image *image, uint32_t value)
3147 {
3148 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3149 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3150
3151 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3152 image->cmask.size, value);
3153
3154 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3155 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3156 RADV_CMD_FLAG_INV_VMEM_L1 |
3157 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3158 }
3159
3160 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3161 struct radv_image *image,
3162 VkImageLayout src_layout,
3163 VkImageLayout dst_layout,
3164 unsigned src_queue_mask,
3165 unsigned dst_queue_mask,
3166 const VkImageSubresourceRange *range,
3167 VkImageAspectFlags pending_clears)
3168 {
3169 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3170 if (image->fmask.size)
3171 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3172 else
3173 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3174 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3175 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3176 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3177 }
3178 }
3179
3180 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3181 struct radv_image *image, uint32_t value)
3182 {
3183
3184 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3185 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3186
3187 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3188 image->surface.dcc_size, value);
3189
3190 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3191 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3192 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3193 RADV_CMD_FLAG_INV_VMEM_L1 |
3194 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3195 }
3196
3197 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3198 struct radv_image *image,
3199 VkImageLayout src_layout,
3200 VkImageLayout dst_layout,
3201 unsigned src_queue_mask,
3202 unsigned dst_queue_mask,
3203 const VkImageSubresourceRange *range,
3204 VkImageAspectFlags pending_clears)
3205 {
3206 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3207 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3208 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3209 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3210 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3211 }
3212 }
3213
3214 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3215 struct radv_image *image,
3216 VkImageLayout src_layout,
3217 VkImageLayout dst_layout,
3218 uint32_t src_family,
3219 uint32_t dst_family,
3220 const VkImageSubresourceRange *range,
3221 VkImageAspectFlags pending_clears)
3222 {
3223 if (image->exclusive && src_family != dst_family) {
3224 /* This is an acquire or a release operation and there will be
3225 * a corresponding release/acquire. Do the transition in the
3226 * most flexible queue. */
3227
3228 assert(src_family == cmd_buffer->queue_family_index ||
3229 dst_family == cmd_buffer->queue_family_index);
3230
3231 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3232 return;
3233
3234 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3235 (src_family == RADV_QUEUE_GENERAL ||
3236 dst_family == RADV_QUEUE_GENERAL))
3237 return;
3238 }
3239
3240 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3241 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3242
3243 if (image->surface.htile_size)
3244 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3245 dst_layout, src_queue_mask,
3246 dst_queue_mask, range,
3247 pending_clears);
3248
3249 if (image->cmask.size)
3250 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3251 dst_layout, src_queue_mask,
3252 dst_queue_mask, range,
3253 pending_clears);
3254
3255 if (image->surface.dcc_size)
3256 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3257 dst_layout, src_queue_mask,
3258 dst_queue_mask, range,
3259 pending_clears);
3260 }
3261
3262 void radv_CmdPipelineBarrier(
3263 VkCommandBuffer commandBuffer,
3264 VkPipelineStageFlags srcStageMask,
3265 VkPipelineStageFlags destStageMask,
3266 VkBool32 byRegion,
3267 uint32_t memoryBarrierCount,
3268 const VkMemoryBarrier* pMemoryBarriers,
3269 uint32_t bufferMemoryBarrierCount,
3270 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3271 uint32_t imageMemoryBarrierCount,
3272 const VkImageMemoryBarrier* pImageMemoryBarriers)
3273 {
3274 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3275 enum radv_cmd_flush_bits src_flush_bits = 0;
3276 enum radv_cmd_flush_bits dst_flush_bits = 0;
3277
3278 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3279 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3280 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3281 NULL);
3282 }
3283
3284 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3285 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3286 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3287 NULL);
3288 }
3289
3290 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3291 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3292 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3293 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3294 image);
3295 }
3296
3297 radv_stage_flush(cmd_buffer, srcStageMask);
3298 cmd_buffer->state.flush_bits |= src_flush_bits;
3299
3300 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3301 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3302 radv_handle_image_transition(cmd_buffer, image,
3303 pImageMemoryBarriers[i].oldLayout,
3304 pImageMemoryBarriers[i].newLayout,
3305 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3306 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3307 &pImageMemoryBarriers[i].subresourceRange,
3308 0);
3309 }
3310
3311 cmd_buffer->state.flush_bits |= dst_flush_bits;
3312 }
3313
3314
3315 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3316 struct radv_event *event,
3317 VkPipelineStageFlags stageMask,
3318 unsigned value)
3319 {
3320 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3321 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3322
3323 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3324
3325 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3326
3327 /* TODO: this is overkill. Probably should figure something out from
3328 * the stage mask. */
3329
3330 si_cs_emit_write_event_eop(cs,
3331 cmd_buffer->state.predicating,
3332 cmd_buffer->device->physical_device->rad_info.chip_class,
3333 false,
3334 EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
3335 1, va, 2, value);
3336
3337 assert(cmd_buffer->cs->cdw <= cdw_max);
3338 }
3339
3340 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3341 VkEvent _event,
3342 VkPipelineStageFlags stageMask)
3343 {
3344 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3345 RADV_FROM_HANDLE(radv_event, event, _event);
3346
3347 write_event(cmd_buffer, event, stageMask, 1);
3348 }
3349
3350 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3351 VkEvent _event,
3352 VkPipelineStageFlags stageMask)
3353 {
3354 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3355 RADV_FROM_HANDLE(radv_event, event, _event);
3356
3357 write_event(cmd_buffer, event, stageMask, 0);
3358 }
3359
3360 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3361 uint32_t eventCount,
3362 const VkEvent* pEvents,
3363 VkPipelineStageFlags srcStageMask,
3364 VkPipelineStageFlags dstStageMask,
3365 uint32_t memoryBarrierCount,
3366 const VkMemoryBarrier* pMemoryBarriers,
3367 uint32_t bufferMemoryBarrierCount,
3368 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3369 uint32_t imageMemoryBarrierCount,
3370 const VkImageMemoryBarrier* pImageMemoryBarriers)
3371 {
3372 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3373 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3374
3375 for (unsigned i = 0; i < eventCount; ++i) {
3376 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3377 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3378
3379 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3380
3381 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3382
3383 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3384 assert(cmd_buffer->cs->cdw <= cdw_max);
3385 }
3386
3387
3388 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3389 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3390
3391 radv_handle_image_transition(cmd_buffer, image,
3392 pImageMemoryBarriers[i].oldLayout,
3393 pImageMemoryBarriers[i].newLayout,
3394 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3395 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3396 &pImageMemoryBarriers[i].subresourceRange,
3397 0);
3398 }
3399
3400 /* TODO: figure out how to do memory barriers without waiting */
3401 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3402 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3403 RADV_CMD_FLAG_INV_VMEM_L1 |
3404 RADV_CMD_FLAG_INV_SMEM_L1;
3405 }