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[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 struct radv_sample_locations_state *sample_locs);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109 dest->sample_location.count = src->sample_location.count;
110
111 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
112 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
113 src->viewport.count * sizeof(VkViewport))) {
114 typed_memcpy(dest->viewport.viewports,
115 src->viewport.viewports,
116 src->viewport.count);
117 dest_mask |= RADV_DYNAMIC_VIEWPORT;
118 }
119 }
120
121 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
122 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
123 src->scissor.count * sizeof(VkRect2D))) {
124 typed_memcpy(dest->scissor.scissors,
125 src->scissor.scissors, src->scissor.count);
126 dest_mask |= RADV_DYNAMIC_SCISSOR;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
131 if (dest->line_width != src->line_width) {
132 dest->line_width = src->line_width;
133 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
134 }
135 }
136
137 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
138 if (memcmp(&dest->depth_bias, &src->depth_bias,
139 sizeof(src->depth_bias))) {
140 dest->depth_bias = src->depth_bias;
141 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
142 }
143 }
144
145 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
146 if (memcmp(&dest->blend_constants, &src->blend_constants,
147 sizeof(src->blend_constants))) {
148 typed_memcpy(dest->blend_constants,
149 src->blend_constants, 4);
150 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
151 }
152 }
153
154 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
155 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
156 sizeof(src->depth_bounds))) {
157 dest->depth_bounds = src->depth_bounds;
158 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
159 }
160 }
161
162 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
163 if (memcmp(&dest->stencil_compare_mask,
164 &src->stencil_compare_mask,
165 sizeof(src->stencil_compare_mask))) {
166 dest->stencil_compare_mask = src->stencil_compare_mask;
167 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
168 }
169 }
170
171 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
172 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
173 sizeof(src->stencil_write_mask))) {
174 dest->stencil_write_mask = src->stencil_write_mask;
175 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
176 }
177 }
178
179 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
180 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
181 sizeof(src->stencil_reference))) {
182 dest->stencil_reference = src->stencil_reference;
183 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
184 }
185 }
186
187 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
188 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
189 src->discard_rectangle.count * sizeof(VkRect2D))) {
190 typed_memcpy(dest->discard_rectangle.rectangles,
191 src->discard_rectangle.rectangles,
192 src->discard_rectangle.count);
193 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
194 }
195 }
196
197 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
198 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
199 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
200 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
201 memcmp(&dest->sample_location.locations,
202 &src->sample_location.locations,
203 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
204 dest->sample_location.per_pixel = src->sample_location.per_pixel;
205 dest->sample_location.grid_size = src->sample_location.grid_size;
206 typed_memcpy(dest->sample_location.locations,
207 src->sample_location.locations,
208 src->sample_location.count);
209 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
210 }
211 }
212
213 cmd_buffer->state.dirty |= dest_mask;
214 }
215
216 static void
217 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
218 struct radv_pipeline *pipeline)
219 {
220 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
221 struct radv_shader_info *info;
222
223 if (!pipeline->streamout_shader)
224 return;
225
226 info = &pipeline->streamout_shader->info.info;
227 for (int i = 0; i < MAX_SO_BUFFERS; i++)
228 so->stride_in_dw[i] = info->so.strides[i];
229
230 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
231 }
232
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
234 {
235 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
236 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
237 }
238
239 enum ring_type radv_queue_family_to_ring(int f) {
240 switch (f) {
241 case RADV_QUEUE_GENERAL:
242 return RING_GFX;
243 case RADV_QUEUE_COMPUTE:
244 return RING_COMPUTE;
245 case RADV_QUEUE_TRANSFER:
246 return RING_DMA;
247 default:
248 unreachable("Unknown queue family");
249 }
250 }
251
252 static VkResult radv_create_cmd_buffer(
253 struct radv_device * device,
254 struct radv_cmd_pool * pool,
255 VkCommandBufferLevel level,
256 VkCommandBuffer* pCommandBuffer)
257 {
258 struct radv_cmd_buffer *cmd_buffer;
259 unsigned ring;
260 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
262 if (cmd_buffer == NULL)
263 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 cmd_buffer->device = device;
267 cmd_buffer->pool = pool;
268 cmd_buffer->level = level;
269
270 if (pool) {
271 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
272 cmd_buffer->queue_family_index = pool->queue_family_index;
273
274 } else {
275 /* Init the pool_link so we can safely call list_del when we destroy
276 * the command buffer
277 */
278 list_inithead(&cmd_buffer->pool_link);
279 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
280 }
281
282 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
283
284 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
285 if (!cmd_buffer->cs) {
286 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
287 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
288 }
289
290 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
291
292 list_inithead(&cmd_buffer->upload.list);
293
294 return VK_SUCCESS;
295 }
296
297 static void
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
299 {
300 list_del(&cmd_buffer->pool_link);
301
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
303 &cmd_buffer->upload.list, list) {
304 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
305 list_del(&up->list);
306 free(up);
307 }
308
309 if (cmd_buffer->upload.upload_bo)
310 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
311 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
314 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
315
316 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
317 }
318
319 static VkResult
320 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
321 {
322 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
323
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
325 &cmd_buffer->upload.list, list) {
326 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
327 list_del(&up->list);
328 free(up);
329 }
330
331 cmd_buffer->push_constant_stages = 0;
332 cmd_buffer->scratch_size_needed = 0;
333 cmd_buffer->compute_scratch_size_needed = 0;
334 cmd_buffer->esgs_ring_size_needed = 0;
335 cmd_buffer->gsvs_ring_size_needed = 0;
336 cmd_buffer->tess_rings_needed = false;
337 cmd_buffer->sample_positions_needed = false;
338
339 if (cmd_buffer->upload.upload_bo)
340 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
341 cmd_buffer->upload.upload_bo);
342 cmd_buffer->upload.offset = 0;
343
344 cmd_buffer->record_result = VK_SUCCESS;
345
346 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
347
348 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
349 cmd_buffer->descriptors[i].dirty = 0;
350 cmd_buffer->descriptors[i].valid = 0;
351 cmd_buffer->descriptors[i].push_dirty = false;
352 }
353
354 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
355 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
356 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
357 unsigned fence_offset, eop_bug_offset;
358 void *fence_ptr;
359
360 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
361 &fence_ptr);
362
363 cmd_buffer->gfx9_fence_va =
364 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
365 cmd_buffer->gfx9_fence_va += fence_offset;
366
367 /* Allocate a buffer for the EOP bug on GFX9. */
368 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
369 &eop_bug_offset, &fence_ptr);
370 cmd_buffer->gfx9_eop_bug_va =
371 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
372 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
373 }
374
375 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
376
377 return cmd_buffer->record_result;
378 }
379
380 static bool
381 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
382 uint64_t min_needed)
383 {
384 uint64_t new_size;
385 struct radeon_winsys_bo *bo;
386 struct radv_cmd_buffer_upload *upload;
387 struct radv_device *device = cmd_buffer->device;
388
389 new_size = MAX2(min_needed, 16 * 1024);
390 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
391
392 bo = device->ws->buffer_create(device->ws,
393 new_size, 4096,
394 RADEON_DOMAIN_GTT,
395 RADEON_FLAG_CPU_ACCESS|
396 RADEON_FLAG_NO_INTERPROCESS_SHARING |
397 RADEON_FLAG_32BIT,
398 RADV_BO_PRIORITY_UPLOAD_BUFFER);
399
400 if (!bo) {
401 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
402 return false;
403 }
404
405 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
406 if (cmd_buffer->upload.upload_bo) {
407 upload = malloc(sizeof(*upload));
408
409 if (!upload) {
410 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
411 device->ws->buffer_destroy(bo);
412 return false;
413 }
414
415 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
416 list_add(&upload->list, &cmd_buffer->upload.list);
417 }
418
419 cmd_buffer->upload.upload_bo = bo;
420 cmd_buffer->upload.size = new_size;
421 cmd_buffer->upload.offset = 0;
422 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
423
424 if (!cmd_buffer->upload.map) {
425 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
426 return false;
427 }
428
429 return true;
430 }
431
432 bool
433 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
434 unsigned size,
435 unsigned alignment,
436 unsigned *out_offset,
437 void **ptr)
438 {
439 assert(util_is_power_of_two_nonzero(alignment));
440
441 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
442 if (offset + size > cmd_buffer->upload.size) {
443 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
444 return false;
445 offset = 0;
446 }
447
448 *out_offset = offset;
449 *ptr = cmd_buffer->upload.map + offset;
450
451 cmd_buffer->upload.offset = offset + size;
452 return true;
453 }
454
455 bool
456 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
457 unsigned size, unsigned alignment,
458 const void *data, unsigned *out_offset)
459 {
460 uint8_t *ptr;
461
462 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
463 out_offset, (void **)&ptr))
464 return false;
465
466 if (ptr)
467 memcpy(ptr, data, size);
468
469 return true;
470 }
471
472 static void
473 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
474 unsigned count, const uint32_t *data)
475 {
476 struct radeon_cmdbuf *cs = cmd_buffer->cs;
477
478 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
479
480 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
481 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
482 S_370_WR_CONFIRM(1) |
483 S_370_ENGINE_SEL(V_370_ME));
484 radeon_emit(cs, va);
485 radeon_emit(cs, va >> 32);
486 radeon_emit_array(cs, data, count);
487 }
488
489 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
490 {
491 struct radv_device *device = cmd_buffer->device;
492 struct radeon_cmdbuf *cs = cmd_buffer->cs;
493 uint64_t va;
494
495 va = radv_buffer_get_va(device->trace_bo);
496 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
497 va += 4;
498
499 ++cmd_buffer->state.trace_id;
500 radv_emit_write_data_packet(cmd_buffer, va, 1,
501 &cmd_buffer->state.trace_id);
502
503 radeon_check_space(cmd_buffer->device->ws, cs, 2);
504
505 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
506 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
507 }
508
509 static void
510 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
511 enum radv_cmd_flush_bits flags)
512 {
513 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
514 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
515 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
516
517 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
518
519 /* Force wait for graphics or compute engines to be idle. */
520 si_cs_emit_cache_flush(cmd_buffer->cs,
521 cmd_buffer->device->physical_device->rad_info.chip_class,
522 &cmd_buffer->gfx9_fence_idx,
523 cmd_buffer->gfx9_fence_va,
524 radv_cmd_buffer_uses_mec(cmd_buffer),
525 flags, cmd_buffer->gfx9_eop_bug_va);
526 }
527
528 if (unlikely(cmd_buffer->device->trace_bo))
529 radv_cmd_buffer_trace_emit(cmd_buffer);
530 }
531
532 static void
533 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
534 struct radv_pipeline *pipeline, enum ring_type ring)
535 {
536 struct radv_device *device = cmd_buffer->device;
537 uint32_t data[2];
538 uint64_t va;
539
540 va = radv_buffer_get_va(device->trace_bo);
541
542 switch (ring) {
543 case RING_GFX:
544 va += 8;
545 break;
546 case RING_COMPUTE:
547 va += 16;
548 break;
549 default:
550 assert(!"invalid ring type");
551 }
552
553 data[0] = (uintptr_t)pipeline;
554 data[1] = (uintptr_t)pipeline >> 32;
555
556 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
557 }
558
559 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
560 VkPipelineBindPoint bind_point,
561 struct radv_descriptor_set *set,
562 unsigned idx)
563 {
564 struct radv_descriptor_state *descriptors_state =
565 radv_get_descriptors_state(cmd_buffer, bind_point);
566
567 descriptors_state->sets[idx] = set;
568
569 descriptors_state->valid |= (1u << idx); /* active descriptors */
570 descriptors_state->dirty |= (1u << idx);
571 }
572
573 static void
574 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
575 VkPipelineBindPoint bind_point)
576 {
577 struct radv_descriptor_state *descriptors_state =
578 radv_get_descriptors_state(cmd_buffer, bind_point);
579 struct radv_device *device = cmd_buffer->device;
580 uint32_t data[MAX_SETS * 2] = {};
581 uint64_t va;
582 unsigned i;
583 va = radv_buffer_get_va(device->trace_bo) + 24;
584
585 for_each_bit(i, descriptors_state->valid) {
586 struct radv_descriptor_set *set = descriptors_state->sets[i];
587 data[i * 2] = (uint64_t)(uintptr_t)set;
588 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
589 }
590
591 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
592 }
593
594 struct radv_userdata_info *
595 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
596 gl_shader_stage stage,
597 int idx)
598 {
599 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
600 return &shader->info.user_sgprs_locs.shader_data[idx];
601 }
602
603 static void
604 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
605 struct radv_pipeline *pipeline,
606 gl_shader_stage stage,
607 int idx, uint64_t va)
608 {
609 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
610 uint32_t base_reg = pipeline->user_data_0[stage];
611 if (loc->sgpr_idx == -1)
612 return;
613
614 assert(loc->num_sgprs == 1);
615
616 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
617 base_reg + loc->sgpr_idx * 4, va, false);
618 }
619
620 static void
621 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
622 struct radv_pipeline *pipeline,
623 struct radv_descriptor_state *descriptors_state,
624 gl_shader_stage stage)
625 {
626 struct radv_device *device = cmd_buffer->device;
627 struct radeon_cmdbuf *cs = cmd_buffer->cs;
628 uint32_t sh_base = pipeline->user_data_0[stage];
629 struct radv_userdata_locations *locs =
630 &pipeline->shaders[stage]->info.user_sgprs_locs;
631 unsigned mask = locs->descriptor_sets_enabled;
632
633 mask &= descriptors_state->dirty & descriptors_state->valid;
634
635 while (mask) {
636 int start, count;
637
638 u_bit_scan_consecutive_range(&mask, &start, &count);
639
640 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
641 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
642
643 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
644 for (int i = 0; i < count; i++) {
645 struct radv_descriptor_set *set =
646 descriptors_state->sets[start + i];
647
648 radv_emit_shader_pointer_body(device, cs, set->va, true);
649 }
650 }
651 }
652
653 /**
654 * Convert the user sample locations to hardware sample locations (the values
655 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
656 */
657 static void
658 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
659 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
660 {
661 uint32_t x_offset = x % state->grid_size.width;
662 uint32_t y_offset = y % state->grid_size.height;
663 uint32_t num_samples = (uint32_t)state->per_pixel;
664 VkSampleLocationEXT *user_locs;
665 uint32_t pixel_offset;
666
667 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
668
669 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
670 user_locs = &state->locations[pixel_offset];
671
672 for (uint32_t i = 0; i < num_samples; i++) {
673 float shifted_pos_x = user_locs[i].x - 0.5;
674 float shifted_pos_y = user_locs[i].y - 0.5;
675
676 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
677 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
678
679 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
680 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
681 }
682 }
683
684 /**
685 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
686 * locations.
687 */
688 static void
689 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
690 uint32_t *sample_locs_pixel)
691 {
692 for (uint32_t i = 0; i < num_samples; i++) {
693 uint32_t sample_reg_idx = i / 4;
694 uint32_t sample_loc_idx = i % 4;
695 int32_t pos_x = sample_locs[i].x;
696 int32_t pos_y = sample_locs[i].y;
697
698 uint32_t shift_x = 8 * sample_loc_idx;
699 uint32_t shift_y = shift_x + 4;
700
701 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
702 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
703 }
704 }
705
706 /**
707 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
708 * sample locations.
709 */
710 static uint64_t
711 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
712 VkOffset2D *sample_locs,
713 uint32_t num_samples)
714 {
715 uint32_t centroid_priorities[num_samples];
716 uint32_t sample_mask = num_samples - 1;
717 uint32_t distances[num_samples];
718 uint64_t centroid_priority = 0;
719
720 /* Compute the distances from center for each sample. */
721 for (int i = 0; i < num_samples; i++) {
722 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
723 (sample_locs[i].y * sample_locs[i].y);
724 }
725
726 /* Compute the centroid priorities by looking at the distances array. */
727 for (int i = 0; i < num_samples; i++) {
728 uint32_t min_idx = 0;
729
730 for (int j = 1; j < num_samples; j++) {
731 if (distances[j] < distances[min_idx])
732 min_idx = j;
733 }
734
735 centroid_priorities[i] = min_idx;
736 distances[min_idx] = 0xffffffff;
737 }
738
739 /* Compute the final centroid priority. */
740 for (int i = 0; i < 8; i++) {
741 centroid_priority |=
742 centroid_priorities[i & sample_mask] << (i * 4);
743 }
744
745 return centroid_priority << 32 | centroid_priority;
746 }
747
748 /**
749 * Emit the sample locations that are specified with VK_EXT_sample_locations.
750 */
751 static void
752 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
753 {
754 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
755 struct radv_multisample_state *ms = &pipeline->graphics.ms;
756 struct radv_sample_locations_state *sample_location =
757 &cmd_buffer->state.dynamic.sample_location;
758 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
759 struct radeon_cmdbuf *cs = cmd_buffer->cs;
760 uint32_t sample_locs_pixel[4][2] = {};
761 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
762 uint32_t max_sample_dist = 0;
763 uint64_t centroid_priority;
764
765 if (!cmd_buffer->state.dynamic.sample_location.count)
766 return;
767
768 /* Convert the user sample locations to hardware sample locations. */
769 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
770 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
771 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
772 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
773
774 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
775 for (uint32_t i = 0; i < 4; i++) {
776 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
777 sample_locs_pixel[i]);
778 }
779
780 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
781 centroid_priority =
782 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
783 num_samples);
784
785 /* Compute the maximum sample distance from the specified locations. */
786 for (uint32_t i = 0; i < num_samples; i++) {
787 VkOffset2D offset = sample_locs[0][i];
788 max_sample_dist = MAX2(max_sample_dist,
789 MAX2(abs(offset.x), abs(offset.y)));
790 }
791
792 /* Emit the specified user sample locations. */
793 switch (num_samples) {
794 case 2:
795 case 4:
796 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
797 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
798 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
799 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
800 break;
801 case 8:
802 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
803 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
804 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
805 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
806 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
807 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
808 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
809 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
810 break;
811 default:
812 unreachable("invalid number of samples");
813 }
814
815 /* Emit the maximum sample distance and the centroid priority. */
816 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
817
818 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
819 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
820
821 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
822 radeon_emit(cs, pa_sc_aa_config);
823
824 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
825 radeon_emit(cs, centroid_priority);
826 radeon_emit(cs, centroid_priority >> 32);
827
828 /* GFX9: Flush DFSM when the AA mode changes. */
829 if (cmd_buffer->device->dfsm_allowed) {
830 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
831 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
832 }
833
834 cmd_buffer->state.context_roll_without_scissor_emitted = true;
835 }
836
837 static void
838 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
839 struct radv_pipeline *pipeline,
840 gl_shader_stage stage,
841 int idx, int count, uint32_t *values)
842 {
843 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
844 uint32_t base_reg = pipeline->user_data_0[stage];
845 if (loc->sgpr_idx == -1)
846 return;
847
848 assert(loc->num_sgprs == count);
849
850 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
851 radeon_emit_array(cmd_buffer->cs, values, count);
852 }
853
854 static void
855 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
856 struct radv_pipeline *pipeline)
857 {
858 int num_samples = pipeline->graphics.ms.num_samples;
859 struct radv_multisample_state *ms = &pipeline->graphics.ms;
860 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
861
862 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
863 cmd_buffer->sample_positions_needed = true;
864
865 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
866 return;
867
868 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
869 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
870 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
871
872 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
873
874 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
875
876 /* GFX9: Flush DFSM when the AA mode changes. */
877 if (cmd_buffer->device->dfsm_allowed) {
878 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
879 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
880 }
881
882 cmd_buffer->state.context_roll_without_scissor_emitted = true;
883 }
884
885 static void
886 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
887 struct radv_shader_variant *shader)
888 {
889 uint64_t va;
890
891 if (!shader)
892 return;
893
894 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
895
896 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
897 }
898
899 static void
900 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
901 struct radv_pipeline *pipeline,
902 bool vertex_stage_only)
903 {
904 struct radv_cmd_state *state = &cmd_buffer->state;
905 uint32_t mask = state->prefetch_L2_mask;
906
907 if (vertex_stage_only) {
908 /* Fast prefetch path for starting draws as soon as possible.
909 */
910 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
911 RADV_PREFETCH_VBO_DESCRIPTORS);
912 }
913
914 if (mask & RADV_PREFETCH_VS)
915 radv_emit_shader_prefetch(cmd_buffer,
916 pipeline->shaders[MESA_SHADER_VERTEX]);
917
918 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
919 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
920
921 if (mask & RADV_PREFETCH_TCS)
922 radv_emit_shader_prefetch(cmd_buffer,
923 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
924
925 if (mask & RADV_PREFETCH_TES)
926 radv_emit_shader_prefetch(cmd_buffer,
927 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
928
929 if (mask & RADV_PREFETCH_GS) {
930 radv_emit_shader_prefetch(cmd_buffer,
931 pipeline->shaders[MESA_SHADER_GEOMETRY]);
932 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
933 }
934
935 if (mask & RADV_PREFETCH_PS)
936 radv_emit_shader_prefetch(cmd_buffer,
937 pipeline->shaders[MESA_SHADER_FRAGMENT]);
938
939 state->prefetch_L2_mask &= ~mask;
940 }
941
942 static void
943 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
944 {
945 if (!cmd_buffer->device->physical_device->rbplus_allowed)
946 return;
947
948 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
949 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
950 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
951
952 unsigned sx_ps_downconvert = 0;
953 unsigned sx_blend_opt_epsilon = 0;
954 unsigned sx_blend_opt_control = 0;
955
956 for (unsigned i = 0; i < subpass->color_count; ++i) {
957 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
958 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
959 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
960 continue;
961 }
962
963 int idx = subpass->color_attachments[i].attachment;
964 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
965
966 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
967 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
968 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
969 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
970
971 bool has_alpha, has_rgb;
972
973 /* Set if RGB and A are present. */
974 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
975
976 if (format == V_028C70_COLOR_8 ||
977 format == V_028C70_COLOR_16 ||
978 format == V_028C70_COLOR_32)
979 has_rgb = !has_alpha;
980 else
981 has_rgb = true;
982
983 /* Check the colormask and export format. */
984 if (!(colormask & 0x7))
985 has_rgb = false;
986 if (!(colormask & 0x8))
987 has_alpha = false;
988
989 if (spi_format == V_028714_SPI_SHADER_ZERO) {
990 has_rgb = false;
991 has_alpha = false;
992 }
993
994 /* Disable value checking for disabled channels. */
995 if (!has_rgb)
996 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
997 if (!has_alpha)
998 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
999
1000 /* Enable down-conversion for 32bpp and smaller formats. */
1001 switch (format) {
1002 case V_028C70_COLOR_8:
1003 case V_028C70_COLOR_8_8:
1004 case V_028C70_COLOR_8_8_8_8:
1005 /* For 1 and 2-channel formats, use the superset thereof. */
1006 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1007 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1008 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1009 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1010 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1011 }
1012 break;
1013
1014 case V_028C70_COLOR_5_6_5:
1015 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1016 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1017 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1018 }
1019 break;
1020
1021 case V_028C70_COLOR_1_5_5_5:
1022 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1023 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1024 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1025 }
1026 break;
1027
1028 case V_028C70_COLOR_4_4_4_4:
1029 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1030 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1031 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1032 }
1033 break;
1034
1035 case V_028C70_COLOR_32:
1036 if (swap == V_028C70_SWAP_STD &&
1037 spi_format == V_028714_SPI_SHADER_32_R)
1038 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1039 else if (swap == V_028C70_SWAP_ALT_REV &&
1040 spi_format == V_028714_SPI_SHADER_32_AR)
1041 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1042 break;
1043
1044 case V_028C70_COLOR_16:
1045 case V_028C70_COLOR_16_16:
1046 /* For 1-channel formats, use the superset thereof. */
1047 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1048 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1049 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1050 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1051 if (swap == V_028C70_SWAP_STD ||
1052 swap == V_028C70_SWAP_STD_REV)
1053 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1054 else
1055 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1056 }
1057 break;
1058
1059 case V_028C70_COLOR_10_11_11:
1060 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1061 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1062 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1063 }
1064 break;
1065
1066 case V_028C70_COLOR_2_10_10_10:
1067 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1068 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1069 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1070 }
1071 break;
1072 }
1073 }
1074
1075 for (unsigned i = subpass->color_count; i < 8; ++i) {
1076 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1077 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1078 }
1079 /* TODO: avoid redundantly setting context registers */
1080 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1081 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1082 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1083 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1084
1085 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1086 }
1087
1088 static void
1089 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1090 {
1091 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1092
1093 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1094 return;
1095
1096 radv_update_multisample_state(cmd_buffer, pipeline);
1097
1098 cmd_buffer->scratch_size_needed =
1099 MAX2(cmd_buffer->scratch_size_needed,
1100 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1101
1102 if (!cmd_buffer->state.emitted_pipeline ||
1103 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1104 pipeline->graphics.can_use_guardband)
1105 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1106
1107 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1108
1109 if (!cmd_buffer->state.emitted_pipeline ||
1110 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1111 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1112 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1113 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1114 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1115 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1116 }
1117
1118 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1119 if (!pipeline->shaders[i])
1120 continue;
1121
1122 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1123 pipeline->shaders[i]->bo);
1124 }
1125
1126 if (radv_pipeline_has_gs(pipeline))
1127 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1128 pipeline->gs_copy_shader->bo);
1129
1130 if (unlikely(cmd_buffer->device->trace_bo))
1131 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1132
1133 cmd_buffer->state.emitted_pipeline = pipeline;
1134
1135 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1136 }
1137
1138 static void
1139 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1140 {
1141 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1142 cmd_buffer->state.dynamic.viewport.viewports);
1143 }
1144
1145 static void
1146 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1147 {
1148 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1149
1150 si_write_scissors(cmd_buffer->cs, 0, count,
1151 cmd_buffer->state.dynamic.scissor.scissors,
1152 cmd_buffer->state.dynamic.viewport.viewports,
1153 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1154
1155 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1156 }
1157
1158 static void
1159 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1160 {
1161 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1162 return;
1163
1164 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1165 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1166 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1167 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1168 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1169 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1170 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1171 }
1172 }
1173
1174 static void
1175 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1176 {
1177 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1178
1179 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1180 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1181 }
1182
1183 static void
1184 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1185 {
1186 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1187
1188 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1189 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1190 }
1191
1192 static void
1193 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1194 {
1195 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1196
1197 radeon_set_context_reg_seq(cmd_buffer->cs,
1198 R_028430_DB_STENCILREFMASK, 2);
1199 radeon_emit(cmd_buffer->cs,
1200 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1201 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1202 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1203 S_028430_STENCILOPVAL(1));
1204 radeon_emit(cmd_buffer->cs,
1205 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1206 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1207 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1208 S_028434_STENCILOPVAL_BF(1));
1209 }
1210
1211 static void
1212 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1213 {
1214 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1215
1216 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1217 fui(d->depth_bounds.min));
1218 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1219 fui(d->depth_bounds.max));
1220 }
1221
1222 static void
1223 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1224 {
1225 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1226 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1227 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1228
1229
1230 radeon_set_context_reg_seq(cmd_buffer->cs,
1231 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1232 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1233 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1234 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1235 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1236 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1237 }
1238
1239 static void
1240 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1241 int index,
1242 struct radv_attachment_info *att,
1243 struct radv_image_view *iview,
1244 VkImageLayout layout)
1245 {
1246 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1247 struct radv_color_buffer_info *cb = &att->cb;
1248 uint32_t cb_color_info = cb->cb_color_info;
1249 struct radv_image *image = iview->image;
1250
1251 if (!radv_layout_dcc_compressed(image, layout,
1252 radv_image_queue_family_mask(image,
1253 cmd_buffer->queue_family_index,
1254 cmd_buffer->queue_family_index))) {
1255 cb_color_info &= C_028C70_DCC_ENABLE;
1256 }
1257
1258 if (radv_image_is_tc_compat_cmask(image) &&
1259 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1260 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1261 /* If this bit is set, the FMASK decompression operation
1262 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1263 */
1264 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1265 }
1266
1267 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1268 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1269 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1270 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1271 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1272 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1273 radeon_emit(cmd_buffer->cs, cb_color_info);
1274 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1275 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1276 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1277 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1278 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1279 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1280
1281 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1282 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1283 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1284
1285 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1286 cb->cb_mrt_epitch);
1287 } else {
1288 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1289 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1290 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1291 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1292 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1293 radeon_emit(cmd_buffer->cs, cb_color_info);
1294 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1295 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1296 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1297 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1298 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1299 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1300
1301 if (is_vi) { /* DCC BASE */
1302 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1303 }
1304 }
1305
1306 if (radv_dcc_enabled(image, iview->base_mip)) {
1307 /* Drawing with DCC enabled also compresses colorbuffers. */
1308 VkImageSubresourceRange range = {
1309 .aspectMask = iview->aspect_mask,
1310 .baseMipLevel = iview->base_mip,
1311 .levelCount = iview->level_count,
1312 .baseArrayLayer = iview->base_layer,
1313 .layerCount = iview->layer_count,
1314 };
1315
1316 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1317 }
1318 }
1319
1320 static void
1321 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1322 struct radv_ds_buffer_info *ds,
1323 struct radv_image *image, VkImageLayout layout,
1324 bool requires_cond_exec)
1325 {
1326 uint32_t db_z_info = ds->db_z_info;
1327 uint32_t db_z_info_reg;
1328
1329 if (!radv_image_is_tc_compat_htile(image))
1330 return;
1331
1332 if (!radv_layout_has_htile(image, layout,
1333 radv_image_queue_family_mask(image,
1334 cmd_buffer->queue_family_index,
1335 cmd_buffer->queue_family_index))) {
1336 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1337 }
1338
1339 db_z_info &= C_028040_ZRANGE_PRECISION;
1340
1341 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1342 db_z_info_reg = R_028038_DB_Z_INFO;
1343 } else {
1344 db_z_info_reg = R_028040_DB_Z_INFO;
1345 }
1346
1347 /* When we don't know the last fast clear value we need to emit a
1348 * conditional packet that will eventually skip the following
1349 * SET_CONTEXT_REG packet.
1350 */
1351 if (requires_cond_exec) {
1352 uint64_t va = radv_buffer_get_va(image->bo);
1353 va += image->offset + image->tc_compat_zrange_offset;
1354
1355 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1356 radeon_emit(cmd_buffer->cs, va);
1357 radeon_emit(cmd_buffer->cs, va >> 32);
1358 radeon_emit(cmd_buffer->cs, 0);
1359 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1360 }
1361
1362 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1363 }
1364
1365 static void
1366 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1367 struct radv_ds_buffer_info *ds,
1368 struct radv_image *image,
1369 VkImageLayout layout)
1370 {
1371 uint32_t db_z_info = ds->db_z_info;
1372 uint32_t db_stencil_info = ds->db_stencil_info;
1373
1374 if (!radv_layout_has_htile(image, layout,
1375 radv_image_queue_family_mask(image,
1376 cmd_buffer->queue_family_index,
1377 cmd_buffer->queue_family_index))) {
1378 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1379 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1380 }
1381
1382 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1383 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1384
1385
1386 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1387 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1388 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1389 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1390 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1391
1392 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1393 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1394 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1395 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1396 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1397 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1398 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1399 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1400 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1401 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1402 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1403
1404 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1405 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1406 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1407 } else {
1408 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1409
1410 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1411 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1412 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1413 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1414 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1415 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1416 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1417 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1418 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1419 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1420
1421 }
1422
1423 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1424 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1425
1426 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1427 ds->pa_su_poly_offset_db_fmt_cntl);
1428 }
1429
1430 /**
1431 * Update the fast clear depth/stencil values if the image is bound as a
1432 * depth/stencil buffer.
1433 */
1434 static void
1435 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1436 struct radv_image *image,
1437 VkClearDepthStencilValue ds_clear_value,
1438 VkImageAspectFlags aspects)
1439 {
1440 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1441 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1442 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1443 struct radv_attachment_info *att;
1444 uint32_t att_idx;
1445
1446 if (!framebuffer || !subpass)
1447 return;
1448
1449 if (!subpass->depth_stencil_attachment)
1450 return;
1451
1452 att_idx = subpass->depth_stencil_attachment->attachment;
1453 att = &framebuffer->attachments[att_idx];
1454 if (att->attachment->image != image)
1455 return;
1456
1457 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1458 radeon_emit(cs, ds_clear_value.stencil);
1459 radeon_emit(cs, fui(ds_clear_value.depth));
1460
1461 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1462 * only needed when clearing Z to 0.0.
1463 */
1464 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1465 ds_clear_value.depth == 0.0) {
1466 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1467
1468 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1469 layout, false);
1470 }
1471
1472 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1473 }
1474
1475 /**
1476 * Set the clear depth/stencil values to the image's metadata.
1477 */
1478 static void
1479 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1480 struct radv_image *image,
1481 VkClearDepthStencilValue ds_clear_value,
1482 VkImageAspectFlags aspects)
1483 {
1484 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1485 uint64_t va = radv_buffer_get_va(image->bo);
1486 unsigned reg_offset = 0, reg_count = 0;
1487
1488 va += image->offset + image->clear_value_offset;
1489
1490 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1491 ++reg_count;
1492 } else {
1493 ++reg_offset;
1494 va += 4;
1495 }
1496 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1497 ++reg_count;
1498
1499 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1500 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1501 S_370_WR_CONFIRM(1) |
1502 S_370_ENGINE_SEL(V_370_PFP));
1503 radeon_emit(cs, va);
1504 radeon_emit(cs, va >> 32);
1505 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1506 radeon_emit(cs, ds_clear_value.stencil);
1507 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1508 radeon_emit(cs, fui(ds_clear_value.depth));
1509 }
1510
1511 /**
1512 * Update the TC-compat metadata value for this image.
1513 */
1514 static void
1515 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1516 struct radv_image *image,
1517 uint32_t value)
1518 {
1519 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1520 uint64_t va = radv_buffer_get_va(image->bo);
1521 va += image->offset + image->tc_compat_zrange_offset;
1522
1523 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1524 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1525 S_370_WR_CONFIRM(1) |
1526 S_370_ENGINE_SEL(V_370_PFP));
1527 radeon_emit(cs, va);
1528 radeon_emit(cs, va >> 32);
1529 radeon_emit(cs, value);
1530 }
1531
1532 static void
1533 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1534 struct radv_image *image,
1535 VkClearDepthStencilValue ds_clear_value)
1536 {
1537 uint32_t cond_val;
1538
1539 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1540 * depth clear value is 0.0f.
1541 */
1542 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1543
1544 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1545 }
1546
1547 /**
1548 * Update the clear depth/stencil values for this image.
1549 */
1550 void
1551 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1552 struct radv_image *image,
1553 VkClearDepthStencilValue ds_clear_value,
1554 VkImageAspectFlags aspects)
1555 {
1556 assert(radv_image_has_htile(image));
1557
1558 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1559
1560 if (radv_image_is_tc_compat_htile(image) &&
1561 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1562 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1563 ds_clear_value);
1564 }
1565
1566 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1567 aspects);
1568 }
1569
1570 /**
1571 * Load the clear depth/stencil values from the image's metadata.
1572 */
1573 static void
1574 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1575 struct radv_image *image)
1576 {
1577 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1578 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1579 uint64_t va = radv_buffer_get_va(image->bo);
1580 unsigned reg_offset = 0, reg_count = 0;
1581
1582 va += image->offset + image->clear_value_offset;
1583
1584 if (!radv_image_has_htile(image))
1585 return;
1586
1587 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1588 ++reg_count;
1589 } else {
1590 ++reg_offset;
1591 va += 4;
1592 }
1593 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1594 ++reg_count;
1595
1596 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1597
1598 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1599 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1600 radeon_emit(cs, va);
1601 radeon_emit(cs, va >> 32);
1602 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1603 radeon_emit(cs, reg_count);
1604 } else {
1605 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1606 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1607 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1608 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1609 radeon_emit(cs, va);
1610 radeon_emit(cs, va >> 32);
1611 radeon_emit(cs, reg >> 2);
1612 radeon_emit(cs, 0);
1613
1614 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1615 radeon_emit(cs, 0);
1616 }
1617 }
1618
1619 /*
1620 * With DCC some colors don't require CMASK elimination before being
1621 * used as a texture. This sets a predicate value to determine if the
1622 * cmask eliminate is required.
1623 */
1624 void
1625 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1626 struct radv_image *image,
1627 const VkImageSubresourceRange *range, bool value)
1628 {
1629 uint64_t pred_val = value;
1630 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1631 uint32_t level_count = radv_get_levelCount(image, range);
1632 uint32_t count = 2 * level_count;
1633
1634 assert(radv_dcc_enabled(image, range->baseMipLevel));
1635
1636 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1637 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1638 S_370_WR_CONFIRM(1) |
1639 S_370_ENGINE_SEL(V_370_PFP));
1640 radeon_emit(cmd_buffer->cs, va);
1641 radeon_emit(cmd_buffer->cs, va >> 32);
1642
1643 for (uint32_t l = 0; l < level_count; l++) {
1644 radeon_emit(cmd_buffer->cs, pred_val);
1645 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1646 }
1647 }
1648
1649 /**
1650 * Update the DCC predicate to reflect the compression state.
1651 */
1652 void
1653 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1654 struct radv_image *image,
1655 const VkImageSubresourceRange *range, bool value)
1656 {
1657 uint64_t pred_val = value;
1658 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1659 uint32_t level_count = radv_get_levelCount(image, range);
1660 uint32_t count = 2 * level_count;
1661
1662 assert(radv_dcc_enabled(image, range->baseMipLevel));
1663
1664 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1665 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1666 S_370_WR_CONFIRM(1) |
1667 S_370_ENGINE_SEL(V_370_PFP));
1668 radeon_emit(cmd_buffer->cs, va);
1669 radeon_emit(cmd_buffer->cs, va >> 32);
1670
1671 for (uint32_t l = 0; l < level_count; l++) {
1672 radeon_emit(cmd_buffer->cs, pred_val);
1673 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1674 }
1675 }
1676
1677 /**
1678 * Update the fast clear color values if the image is bound as a color buffer.
1679 */
1680 static void
1681 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1682 struct radv_image *image,
1683 int cb_idx,
1684 uint32_t color_values[2])
1685 {
1686 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1687 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1688 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1689 struct radv_attachment_info *att;
1690 uint32_t att_idx;
1691
1692 if (!framebuffer || !subpass)
1693 return;
1694
1695 att_idx = subpass->color_attachments[cb_idx].attachment;
1696 if (att_idx == VK_ATTACHMENT_UNUSED)
1697 return;
1698
1699 att = &framebuffer->attachments[att_idx];
1700 if (att->attachment->image != image)
1701 return;
1702
1703 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1704 radeon_emit(cs, color_values[0]);
1705 radeon_emit(cs, color_values[1]);
1706
1707 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1708 }
1709
1710 /**
1711 * Set the clear color values to the image's metadata.
1712 */
1713 static void
1714 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1715 struct radv_image *image,
1716 const VkImageSubresourceRange *range,
1717 uint32_t color_values[2])
1718 {
1719 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1720 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1721 uint32_t level_count = radv_get_levelCount(image, range);
1722 uint32_t count = 2 * level_count;
1723
1724 assert(radv_image_has_cmask(image) ||
1725 radv_dcc_enabled(image, range->baseMipLevel));
1726
1727 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1728 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1729 S_370_WR_CONFIRM(1) |
1730 S_370_ENGINE_SEL(V_370_PFP));
1731 radeon_emit(cs, va);
1732 radeon_emit(cs, va >> 32);
1733
1734 for (uint32_t l = 0; l < level_count; l++) {
1735 radeon_emit(cs, color_values[0]);
1736 radeon_emit(cs, color_values[1]);
1737 }
1738 }
1739
1740 /**
1741 * Update the clear color values for this image.
1742 */
1743 void
1744 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1745 const struct radv_image_view *iview,
1746 int cb_idx,
1747 uint32_t color_values[2])
1748 {
1749 struct radv_image *image = iview->image;
1750 VkImageSubresourceRange range = {
1751 .aspectMask = iview->aspect_mask,
1752 .baseMipLevel = iview->base_mip,
1753 .levelCount = iview->level_count,
1754 .baseArrayLayer = iview->base_layer,
1755 .layerCount = iview->layer_count,
1756 };
1757
1758 assert(radv_image_has_cmask(image) ||
1759 radv_dcc_enabled(image, iview->base_mip));
1760
1761 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1762
1763 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1764 color_values);
1765 }
1766
1767 /**
1768 * Load the clear color values from the image's metadata.
1769 */
1770 static void
1771 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1772 struct radv_image_view *iview,
1773 int cb_idx)
1774 {
1775 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1776 struct radv_image *image = iview->image;
1777 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1778
1779 if (!radv_image_has_cmask(image) &&
1780 !radv_dcc_enabled(image, iview->base_mip))
1781 return;
1782
1783 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1784
1785 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1786 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1787 radeon_emit(cs, va);
1788 radeon_emit(cs, va >> 32);
1789 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1790 radeon_emit(cs, 2);
1791 } else {
1792 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1793 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1794 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1795 COPY_DATA_COUNT_SEL);
1796 radeon_emit(cs, va);
1797 radeon_emit(cs, va >> 32);
1798 radeon_emit(cs, reg >> 2);
1799 radeon_emit(cs, 0);
1800
1801 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1802 radeon_emit(cs, 0);
1803 }
1804 }
1805
1806 static void
1807 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1808 {
1809 int i;
1810 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1811 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1812 unsigned num_bpp64_colorbufs = 0;
1813
1814 /* this may happen for inherited secondary recording */
1815 if (!framebuffer)
1816 return;
1817
1818 for (i = 0; i < 8; ++i) {
1819 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1820 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1821 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1822 continue;
1823 }
1824
1825 int idx = subpass->color_attachments[i].attachment;
1826 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1827 struct radv_image_view *iview = att->attachment;
1828 struct radv_image *image = iview->image;
1829 VkImageLayout layout = subpass->color_attachments[i].layout;
1830
1831 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1832
1833 assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1834 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1835 radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
1836
1837 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1838
1839 if (image->planes[0].surface.bpe >= 8)
1840 num_bpp64_colorbufs++;
1841 }
1842
1843 if (subpass->depth_stencil_attachment) {
1844 int idx = subpass->depth_stencil_attachment->attachment;
1845 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1846 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1847 struct radv_image *image = att->attachment->image;
1848 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1849 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1850 cmd_buffer->queue_family_index,
1851 cmd_buffer->queue_family_index);
1852 /* We currently don't support writing decompressed HTILE */
1853 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1854 radv_layout_is_htile_compressed(image, layout, queue_mask));
1855
1856 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1857
1858 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1859 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1860 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1861 }
1862 radv_load_ds_clear_metadata(cmd_buffer, image);
1863 } else {
1864 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1865 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1866 else
1867 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1868
1869 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1870 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1871 }
1872 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1873 S_028208_BR_X(framebuffer->width) |
1874 S_028208_BR_Y(framebuffer->height));
1875
1876 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
1877 bool disable_constant_encode =
1878 cmd_buffer->device->physical_device->has_dcc_constant_encode;
1879 uint8_t watermark = 4; /* Default value for GFX8. */
1880
1881 /* For optimal DCC performance. */
1882 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1883 if (num_bpp64_colorbufs >= 5) {
1884 watermark = 8;
1885 } else {
1886 watermark = 6;
1887 }
1888 }
1889
1890 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1891 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1892 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
1893 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
1894 }
1895
1896 if (cmd_buffer->device->dfsm_allowed) {
1897 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1898 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1899 }
1900
1901 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1902 }
1903
1904 static void
1905 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1906 {
1907 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1908 struct radv_cmd_state *state = &cmd_buffer->state;
1909
1910 if (state->index_type != state->last_index_type) {
1911 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1912 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1913 2, state->index_type);
1914 } else {
1915 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1916 radeon_emit(cs, state->index_type);
1917 }
1918
1919 state->last_index_type = state->index_type;
1920 }
1921
1922 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1923 radeon_emit(cs, state->index_va);
1924 radeon_emit(cs, state->index_va >> 32);
1925
1926 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1927 radeon_emit(cs, state->max_index_count);
1928
1929 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1930 }
1931
1932 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1933 {
1934 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1935 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1936 uint32_t pa_sc_mode_cntl_1 =
1937 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1938 uint32_t db_count_control;
1939
1940 if(!cmd_buffer->state.active_occlusion_queries) {
1941 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1942 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1943 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1944 has_perfect_queries) {
1945 /* Re-enable out-of-order rasterization if the
1946 * bound pipeline supports it and if it's has
1947 * been disabled before starting any perfect
1948 * occlusion queries.
1949 */
1950 radeon_set_context_reg(cmd_buffer->cs,
1951 R_028A4C_PA_SC_MODE_CNTL_1,
1952 pa_sc_mode_cntl_1);
1953 }
1954 }
1955 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1956 } else {
1957 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1958 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1959
1960 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1961 db_count_control =
1962 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1963 S_028004_SAMPLE_RATE(sample_rate) |
1964 S_028004_ZPASS_ENABLE(1) |
1965 S_028004_SLICE_EVEN_ENABLE(1) |
1966 S_028004_SLICE_ODD_ENABLE(1);
1967
1968 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1969 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1970 has_perfect_queries) {
1971 /* If the bound pipeline has enabled
1972 * out-of-order rasterization, we should
1973 * disable it before starting any perfect
1974 * occlusion queries.
1975 */
1976 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1977
1978 radeon_set_context_reg(cmd_buffer->cs,
1979 R_028A4C_PA_SC_MODE_CNTL_1,
1980 pa_sc_mode_cntl_1);
1981 }
1982 } else {
1983 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1984 S_028004_SAMPLE_RATE(sample_rate);
1985 }
1986 }
1987
1988 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1989
1990 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1991 }
1992
1993 static void
1994 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1995 {
1996 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1997
1998 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1999 radv_emit_viewport(cmd_buffer);
2000
2001 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2002 !cmd_buffer->device->physical_device->has_scissor_bug)
2003 radv_emit_scissor(cmd_buffer);
2004
2005 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2006 radv_emit_line_width(cmd_buffer);
2007
2008 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2009 radv_emit_blend_constants(cmd_buffer);
2010
2011 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2012 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2013 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2014 radv_emit_stencil(cmd_buffer);
2015
2016 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2017 radv_emit_depth_bounds(cmd_buffer);
2018
2019 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2020 radv_emit_depth_bias(cmd_buffer);
2021
2022 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2023 radv_emit_discard_rectangle(cmd_buffer);
2024
2025 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2026 radv_emit_sample_locations(cmd_buffer);
2027
2028 cmd_buffer->state.dirty &= ~states;
2029 }
2030
2031 static void
2032 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2033 VkPipelineBindPoint bind_point)
2034 {
2035 struct radv_descriptor_state *descriptors_state =
2036 radv_get_descriptors_state(cmd_buffer, bind_point);
2037 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2038 unsigned bo_offset;
2039
2040 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2041 set->mapped_ptr,
2042 &bo_offset))
2043 return;
2044
2045 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2046 set->va += bo_offset;
2047 }
2048
2049 static void
2050 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2051 VkPipelineBindPoint bind_point)
2052 {
2053 struct radv_descriptor_state *descriptors_state =
2054 radv_get_descriptors_state(cmd_buffer, bind_point);
2055 uint32_t size = MAX_SETS * 4;
2056 uint32_t offset;
2057 void *ptr;
2058
2059 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2060 256, &offset, &ptr))
2061 return;
2062
2063 for (unsigned i = 0; i < MAX_SETS; i++) {
2064 uint32_t *uptr = ((uint32_t *)ptr) + i;
2065 uint64_t set_va = 0;
2066 struct radv_descriptor_set *set = descriptors_state->sets[i];
2067 if (descriptors_state->valid & (1u << i))
2068 set_va = set->va;
2069 uptr[0] = set_va & 0xffffffff;
2070 }
2071
2072 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2073 va += offset;
2074
2075 if (cmd_buffer->state.pipeline) {
2076 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2077 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2078 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2079
2080 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2081 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2082 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2083
2084 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2085 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2086 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2087
2088 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2089 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2090 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2091
2092 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2093 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2094 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2095 }
2096
2097 if (cmd_buffer->state.compute_pipeline)
2098 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2099 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2100 }
2101
2102 static void
2103 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2104 VkShaderStageFlags stages)
2105 {
2106 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2107 VK_PIPELINE_BIND_POINT_COMPUTE :
2108 VK_PIPELINE_BIND_POINT_GRAPHICS;
2109 struct radv_descriptor_state *descriptors_state =
2110 radv_get_descriptors_state(cmd_buffer, bind_point);
2111 struct radv_cmd_state *state = &cmd_buffer->state;
2112 bool flush_indirect_descriptors;
2113
2114 if (!descriptors_state->dirty)
2115 return;
2116
2117 if (descriptors_state->push_dirty)
2118 radv_flush_push_descriptors(cmd_buffer, bind_point);
2119
2120 flush_indirect_descriptors =
2121 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2122 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2123 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2124 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2125
2126 if (flush_indirect_descriptors)
2127 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2128
2129 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2130 cmd_buffer->cs,
2131 MAX_SETS * MESA_SHADER_STAGES * 4);
2132
2133 if (cmd_buffer->state.pipeline) {
2134 radv_foreach_stage(stage, stages) {
2135 if (!cmd_buffer->state.pipeline->shaders[stage])
2136 continue;
2137
2138 radv_emit_descriptor_pointers(cmd_buffer,
2139 cmd_buffer->state.pipeline,
2140 descriptors_state, stage);
2141 }
2142 }
2143
2144 if (cmd_buffer->state.compute_pipeline &&
2145 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2146 radv_emit_descriptor_pointers(cmd_buffer,
2147 cmd_buffer->state.compute_pipeline,
2148 descriptors_state,
2149 MESA_SHADER_COMPUTE);
2150 }
2151
2152 descriptors_state->dirty = 0;
2153 descriptors_state->push_dirty = false;
2154
2155 assert(cmd_buffer->cs->cdw <= cdw_max);
2156
2157 if (unlikely(cmd_buffer->device->trace_bo))
2158 radv_save_descriptors(cmd_buffer, bind_point);
2159 }
2160
2161 static void
2162 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2163 VkShaderStageFlags stages)
2164 {
2165 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2166 ? cmd_buffer->state.compute_pipeline
2167 : cmd_buffer->state.pipeline;
2168 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2169 VK_PIPELINE_BIND_POINT_COMPUTE :
2170 VK_PIPELINE_BIND_POINT_GRAPHICS;
2171 struct radv_descriptor_state *descriptors_state =
2172 radv_get_descriptors_state(cmd_buffer, bind_point);
2173 struct radv_pipeline_layout *layout = pipeline->layout;
2174 struct radv_shader_variant *shader, *prev_shader;
2175 bool need_push_constants = false;
2176 unsigned offset;
2177 void *ptr;
2178 uint64_t va;
2179
2180 stages &= cmd_buffer->push_constant_stages;
2181 if (!stages ||
2182 (!layout->push_constant_size && !layout->dynamic_offset_count))
2183 return;
2184
2185 radv_foreach_stage(stage, stages) {
2186 if (!pipeline->shaders[stage])
2187 continue;
2188
2189 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
2190 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
2191
2192 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
2193 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
2194
2195 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2196 AC_UD_INLINE_PUSH_CONSTANTS,
2197 count,
2198 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2199 }
2200
2201 if (need_push_constants) {
2202 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2203 16 * layout->dynamic_offset_count,
2204 256, &offset, &ptr))
2205 return;
2206
2207 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2208 memcpy((char*)ptr + layout->push_constant_size,
2209 descriptors_state->dynamic_buffers,
2210 16 * layout->dynamic_offset_count);
2211
2212 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2213 va += offset;
2214
2215 MAYBE_UNUSED unsigned cdw_max =
2216 radeon_check_space(cmd_buffer->device->ws,
2217 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2218
2219 prev_shader = NULL;
2220 radv_foreach_stage(stage, stages) {
2221 shader = radv_get_shader(pipeline, stage);
2222
2223 /* Avoid redundantly emitting the address for merged stages. */
2224 if (shader && shader != prev_shader) {
2225 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2226 AC_UD_PUSH_CONSTANTS, va);
2227
2228 prev_shader = shader;
2229 }
2230 }
2231 assert(cmd_buffer->cs->cdw <= cdw_max);
2232 }
2233
2234 cmd_buffer->push_constant_stages &= ~stages;
2235 }
2236
2237 static void
2238 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2239 bool pipeline_is_dirty)
2240 {
2241 if ((pipeline_is_dirty ||
2242 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2243 cmd_buffer->state.pipeline->num_vertex_bindings &&
2244 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
2245 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2246 unsigned vb_offset;
2247 void *vb_ptr;
2248 uint32_t i = 0;
2249 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2250 uint64_t va;
2251
2252 /* allocate some descriptor state for vertex buffers */
2253 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2254 &vb_offset, &vb_ptr))
2255 return;
2256
2257 for (i = 0; i < count; i++) {
2258 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2259 uint32_t offset;
2260 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2261 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2262
2263 if (!buffer)
2264 continue;
2265
2266 va = radv_buffer_get_va(buffer->bo);
2267
2268 offset = cmd_buffer->vertex_bindings[i].offset;
2269 va += offset + buffer->offset;
2270 desc[0] = va;
2271 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2272 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2273 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2274 else
2275 desc[2] = buffer->size - offset;
2276 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2277 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2278 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2279 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2280 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2281 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2282 }
2283
2284 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2285 va += vb_offset;
2286
2287 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2288 AC_UD_VS_VERTEX_BUFFERS, va);
2289
2290 cmd_buffer->state.vb_va = va;
2291 cmd_buffer->state.vb_size = count * 16;
2292 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2293 }
2294 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2295 }
2296
2297 static void
2298 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2299 {
2300 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2301 struct radv_userdata_info *loc;
2302 uint32_t base_reg;
2303
2304 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2305 if (!radv_get_shader(pipeline, stage))
2306 continue;
2307
2308 loc = radv_lookup_user_sgpr(pipeline, stage,
2309 AC_UD_STREAMOUT_BUFFERS);
2310 if (loc->sgpr_idx == -1)
2311 continue;
2312
2313 base_reg = pipeline->user_data_0[stage];
2314
2315 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2316 base_reg + loc->sgpr_idx * 4, va, false);
2317 }
2318
2319 if (pipeline->gs_copy_shader) {
2320 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2321 if (loc->sgpr_idx != -1) {
2322 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2323
2324 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2325 base_reg + loc->sgpr_idx * 4, va, false);
2326 }
2327 }
2328 }
2329
2330 static void
2331 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2332 {
2333 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2334 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2335 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2336 unsigned so_offset;
2337 void *so_ptr;
2338 uint64_t va;
2339
2340 /* Allocate some descriptor state for streamout buffers. */
2341 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2342 MAX_SO_BUFFERS * 16, 256,
2343 &so_offset, &so_ptr))
2344 return;
2345
2346 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2347 struct radv_buffer *buffer = sb[i].buffer;
2348 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2349
2350 if (!(so->enabled_mask & (1 << i)))
2351 continue;
2352
2353 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2354
2355 va += sb[i].offset;
2356
2357 /* Set the descriptor.
2358 *
2359 * On GFX8, the format must be non-INVALID, otherwise
2360 * the buffer will be considered not bound and store
2361 * instructions will be no-ops.
2362 */
2363 desc[0] = va;
2364 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2365 desc[2] = 0xffffffff;
2366 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2367 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2368 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2369 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2370 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2371 }
2372
2373 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2374 va += so_offset;
2375
2376 radv_emit_streamout_buffers(cmd_buffer, va);
2377 }
2378
2379 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2380 }
2381
2382 static void
2383 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2384 {
2385 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2386 radv_flush_streamout_descriptors(cmd_buffer);
2387 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2388 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2389 }
2390
2391 struct radv_draw_info {
2392 /**
2393 * Number of vertices.
2394 */
2395 uint32_t count;
2396
2397 /**
2398 * Index of the first vertex.
2399 */
2400 int32_t vertex_offset;
2401
2402 /**
2403 * First instance id.
2404 */
2405 uint32_t first_instance;
2406
2407 /**
2408 * Number of instances.
2409 */
2410 uint32_t instance_count;
2411
2412 /**
2413 * First index (indexed draws only).
2414 */
2415 uint32_t first_index;
2416
2417 /**
2418 * Whether it's an indexed draw.
2419 */
2420 bool indexed;
2421
2422 /**
2423 * Indirect draw parameters resource.
2424 */
2425 struct radv_buffer *indirect;
2426 uint64_t indirect_offset;
2427 uint32_t stride;
2428
2429 /**
2430 * Draw count parameters resource.
2431 */
2432 struct radv_buffer *count_buffer;
2433 uint64_t count_buffer_offset;
2434
2435 /**
2436 * Stream output parameters resource.
2437 */
2438 struct radv_buffer *strmout_buffer;
2439 uint64_t strmout_buffer_offset;
2440 };
2441
2442 static void
2443 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2444 bool instanced_draw, bool indirect_draw,
2445 bool count_from_stream_output,
2446 uint32_t draw_vertex_count)
2447 {
2448 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2449 struct radv_cmd_state *state = &cmd_buffer->state;
2450 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2451 unsigned ia_multi_vgt_param;
2452
2453 ia_multi_vgt_param =
2454 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2455 indirect_draw,
2456 count_from_stream_output,
2457 draw_vertex_count);
2458
2459 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2460 if (info->chip_class >= GFX9) {
2461 radeon_set_uconfig_reg_idx(cs,
2462 R_030960_IA_MULTI_VGT_PARAM,
2463 4, ia_multi_vgt_param);
2464 } else if (info->chip_class >= GFX7) {
2465 radeon_set_context_reg_idx(cs,
2466 R_028AA8_IA_MULTI_VGT_PARAM,
2467 1, ia_multi_vgt_param);
2468 } else {
2469 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2470 ia_multi_vgt_param);
2471 }
2472 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2473 }
2474 }
2475
2476 static void
2477 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2478 const struct radv_draw_info *draw_info)
2479 {
2480 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2481 struct radv_cmd_state *state = &cmd_buffer->state;
2482 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2483 int32_t primitive_reset_en;
2484
2485 /* Draw state. */
2486 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2487 draw_info->indirect,
2488 !!draw_info->strmout_buffer,
2489 draw_info->indirect ? 0 : draw_info->count);
2490
2491 /* Primitive restart. */
2492 primitive_reset_en =
2493 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2494
2495 if (primitive_reset_en != state->last_primitive_reset_en) {
2496 state->last_primitive_reset_en = primitive_reset_en;
2497 if (info->chip_class >= GFX9) {
2498 radeon_set_uconfig_reg(cs,
2499 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2500 primitive_reset_en);
2501 } else {
2502 radeon_set_context_reg(cs,
2503 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2504 primitive_reset_en);
2505 }
2506 }
2507
2508 if (primitive_reset_en) {
2509 uint32_t primitive_reset_index =
2510 state->index_type ? 0xffffffffu : 0xffffu;
2511
2512 if (primitive_reset_index != state->last_primitive_reset_index) {
2513 radeon_set_context_reg(cs,
2514 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2515 primitive_reset_index);
2516 state->last_primitive_reset_index = primitive_reset_index;
2517 }
2518 }
2519
2520 if (draw_info->strmout_buffer) {
2521 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2522
2523 va += draw_info->strmout_buffer->offset +
2524 draw_info->strmout_buffer_offset;
2525
2526 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2527 draw_info->stride);
2528
2529 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2530 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2531 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2532 COPY_DATA_WR_CONFIRM);
2533 radeon_emit(cs, va);
2534 radeon_emit(cs, va >> 32);
2535 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2536 radeon_emit(cs, 0); /* unused */
2537
2538 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2539 }
2540 }
2541
2542 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2543 VkPipelineStageFlags src_stage_mask)
2544 {
2545 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2546 VK_PIPELINE_STAGE_TRANSFER_BIT |
2547 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2548 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2549 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2550 }
2551
2552 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2553 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2554 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2555 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2556 VK_PIPELINE_STAGE_TRANSFER_BIT |
2557 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2558 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2559 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2560 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2561 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2562 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2563 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2564 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2565 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2566 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2567 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2568 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2569 }
2570 }
2571
2572 static enum radv_cmd_flush_bits
2573 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2574 VkAccessFlags src_flags,
2575 struct radv_image *image)
2576 {
2577 bool flush_CB_meta = true, flush_DB_meta = true;
2578 enum radv_cmd_flush_bits flush_bits = 0;
2579 uint32_t b;
2580
2581 if (image) {
2582 if (!radv_image_has_CB_metadata(image))
2583 flush_CB_meta = false;
2584 if (!radv_image_has_htile(image))
2585 flush_DB_meta = false;
2586 }
2587
2588 for_each_bit(b, src_flags) {
2589 switch ((VkAccessFlagBits)(1 << b)) {
2590 case VK_ACCESS_SHADER_WRITE_BIT:
2591 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2592 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2593 flush_bits |= RADV_CMD_FLAG_WB_L2;
2594 break;
2595 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2596 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2597 if (flush_CB_meta)
2598 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2599 break;
2600 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2601 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2602 if (flush_DB_meta)
2603 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2604 break;
2605 case VK_ACCESS_TRANSFER_WRITE_BIT:
2606 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2607 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2608 RADV_CMD_FLAG_INV_L2;
2609
2610 if (flush_CB_meta)
2611 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2612 if (flush_DB_meta)
2613 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2614 break;
2615 default:
2616 break;
2617 }
2618 }
2619 return flush_bits;
2620 }
2621
2622 static enum radv_cmd_flush_bits
2623 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2624 VkAccessFlags dst_flags,
2625 struct radv_image *image)
2626 {
2627 bool flush_CB_meta = true, flush_DB_meta = true;
2628 enum radv_cmd_flush_bits flush_bits = 0;
2629 bool flush_CB = true, flush_DB = true;
2630 bool image_is_coherent = false;
2631 uint32_t b;
2632
2633 if (image) {
2634 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2635 flush_CB = false;
2636 flush_DB = false;
2637 }
2638
2639 if (!radv_image_has_CB_metadata(image))
2640 flush_CB_meta = false;
2641 if (!radv_image_has_htile(image))
2642 flush_DB_meta = false;
2643
2644 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2645 if (image->info.samples == 1 &&
2646 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2647 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2648 !vk_format_is_stencil(image->vk_format)) {
2649 /* Single-sample color and single-sample depth
2650 * (not stencil) are coherent with shaders on
2651 * GFX9.
2652 */
2653 image_is_coherent = true;
2654 }
2655 }
2656 }
2657
2658 for_each_bit(b, dst_flags) {
2659 switch ((VkAccessFlagBits)(1 << b)) {
2660 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2661 case VK_ACCESS_INDEX_READ_BIT:
2662 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2663 break;
2664 case VK_ACCESS_UNIFORM_READ_BIT:
2665 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2666 break;
2667 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2668 case VK_ACCESS_TRANSFER_READ_BIT:
2669 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2670 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2671 RADV_CMD_FLAG_INV_L2;
2672 break;
2673 case VK_ACCESS_SHADER_READ_BIT:
2674 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2675
2676 if (!image_is_coherent)
2677 flush_bits |= RADV_CMD_FLAG_INV_L2;
2678 break;
2679 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2680 if (flush_CB)
2681 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2682 if (flush_CB_meta)
2683 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2684 break;
2685 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2686 if (flush_DB)
2687 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2688 if (flush_DB_meta)
2689 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2690 break;
2691 default:
2692 break;
2693 }
2694 }
2695 return flush_bits;
2696 }
2697
2698 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2699 const struct radv_subpass_barrier *barrier)
2700 {
2701 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2702 NULL);
2703 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2704 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2705 NULL);
2706 }
2707
2708 uint32_t
2709 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2710 {
2711 struct radv_cmd_state *state = &cmd_buffer->state;
2712 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2713
2714 /* The id of this subpass shouldn't exceed the number of subpasses in
2715 * this render pass minus 1.
2716 */
2717 assert(subpass_id < state->pass->subpass_count);
2718 return subpass_id;
2719 }
2720
2721 static struct radv_sample_locations_state *
2722 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2723 uint32_t att_idx,
2724 bool begin_subpass)
2725 {
2726 struct radv_cmd_state *state = &cmd_buffer->state;
2727 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2728 struct radv_image_view *view = state->framebuffer->attachments[att_idx].attachment;
2729
2730 if (view->image->info.samples == 1)
2731 return NULL;
2732
2733 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2734 /* Return the initial sample locations if this is the initial
2735 * layout transition of the given subpass attachemnt.
2736 */
2737 if (state->attachments[att_idx].sample_location.count > 0)
2738 return &state->attachments[att_idx].sample_location;
2739 } else {
2740 /* Otherwise return the subpass sample locations if defined. */
2741 if (state->subpass_sample_locs) {
2742 /* Because the driver sets the current subpass before
2743 * initial layout transitions, we should use the sample
2744 * locations from the previous subpass to avoid an
2745 * off-by-one problem. Otherwise, use the sample
2746 * locations for the current subpass for final layout
2747 * transitions.
2748 */
2749 if (begin_subpass)
2750 subpass_id--;
2751
2752 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2753 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2754 return &state->subpass_sample_locs[i].sample_location;
2755 }
2756 }
2757 }
2758
2759 return NULL;
2760 }
2761
2762 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2763 struct radv_subpass_attachment att,
2764 bool begin_subpass)
2765 {
2766 unsigned idx = att.attachment;
2767 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2768 struct radv_sample_locations_state *sample_locs;
2769 VkImageSubresourceRange range;
2770 range.aspectMask = 0;
2771 range.baseMipLevel = view->base_mip;
2772 range.levelCount = 1;
2773 range.baseArrayLayer = view->base_layer;
2774 range.layerCount = cmd_buffer->state.framebuffer->layers;
2775
2776 if (cmd_buffer->state.subpass->view_mask) {
2777 /* If the current subpass uses multiview, the driver might have
2778 * performed a fast color/depth clear to the whole image
2779 * (including all layers). To make sure the driver will
2780 * decompress the image correctly (if needed), we have to
2781 * account for the "real" number of layers. If the view mask is
2782 * sparse, this will decompress more layers than needed.
2783 */
2784 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2785 }
2786
2787 /* Get the subpass sample locations for the given attachment, if NULL
2788 * is returned the driver will use the default HW locations.
2789 */
2790 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2791 begin_subpass);
2792
2793 radv_handle_image_transition(cmd_buffer,
2794 view->image,
2795 cmd_buffer->state.attachments[idx].current_layout,
2796 att.layout, 0, 0, &range, sample_locs);
2797
2798 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2799
2800
2801 }
2802
2803 void
2804 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2805 const struct radv_subpass *subpass)
2806 {
2807 cmd_buffer->state.subpass = subpass;
2808
2809 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2810 }
2811
2812 static VkResult
2813 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2814 struct radv_render_pass *pass,
2815 const VkRenderPassBeginInfo *info)
2816 {
2817 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2818 vk_find_struct_const(info->pNext,
2819 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
2820 struct radv_cmd_state *state = &cmd_buffer->state;
2821 struct radv_framebuffer *framebuffer = state->framebuffer;
2822
2823 if (!sample_locs) {
2824 state->subpass_sample_locs = NULL;
2825 return VK_SUCCESS;
2826 }
2827
2828 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
2829 const VkAttachmentSampleLocationsEXT *att_sample_locs =
2830 &sample_locs->pAttachmentInitialSampleLocations[i];
2831 uint32_t att_idx = att_sample_locs->attachmentIndex;
2832 struct radv_attachment_info *att = &framebuffer->attachments[att_idx];
2833 struct radv_image *image = att->attachment->image;
2834
2835 assert(vk_format_is_depth_or_stencil(image->vk_format));
2836
2837 /* From the Vulkan spec 1.1.108:
2838 *
2839 * "If the image referenced by the framebuffer attachment at
2840 * index attachmentIndex was not created with
2841 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2842 * then the values specified in sampleLocationsInfo are
2843 * ignored."
2844 */
2845 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
2846 continue;
2847
2848 const VkSampleLocationsInfoEXT *sample_locs_info =
2849 &att_sample_locs->sampleLocationsInfo;
2850
2851 state->attachments[att_idx].sample_location.per_pixel =
2852 sample_locs_info->sampleLocationsPerPixel;
2853 state->attachments[att_idx].sample_location.grid_size =
2854 sample_locs_info->sampleLocationGridSize;
2855 state->attachments[att_idx].sample_location.count =
2856 sample_locs_info->sampleLocationsCount;
2857 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
2858 sample_locs_info->pSampleLocations,
2859 sample_locs_info->sampleLocationsCount);
2860 }
2861
2862 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
2863 sample_locs->postSubpassSampleLocationsCount *
2864 sizeof(state->subpass_sample_locs[0]),
2865 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2866 if (state->subpass_sample_locs == NULL) {
2867 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2868 return cmd_buffer->record_result;
2869 }
2870
2871 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
2872
2873 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
2874 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
2875 &sample_locs->pPostSubpassSampleLocations[i];
2876 const VkSampleLocationsInfoEXT *sample_locs_info =
2877 &subpass_sample_locs_info->sampleLocationsInfo;
2878
2879 state->subpass_sample_locs[i].subpass_idx =
2880 subpass_sample_locs_info->subpassIndex;
2881 state->subpass_sample_locs[i].sample_location.per_pixel =
2882 sample_locs_info->sampleLocationsPerPixel;
2883 state->subpass_sample_locs[i].sample_location.grid_size =
2884 sample_locs_info->sampleLocationGridSize;
2885 state->subpass_sample_locs[i].sample_location.count =
2886 sample_locs_info->sampleLocationsCount;
2887 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
2888 sample_locs_info->pSampleLocations,
2889 sample_locs_info->sampleLocationsCount);
2890 }
2891
2892 return VK_SUCCESS;
2893 }
2894
2895 static VkResult
2896 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2897 struct radv_render_pass *pass,
2898 const VkRenderPassBeginInfo *info)
2899 {
2900 struct radv_cmd_state *state = &cmd_buffer->state;
2901
2902 if (pass->attachment_count == 0) {
2903 state->attachments = NULL;
2904 return VK_SUCCESS;
2905 }
2906
2907 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2908 pass->attachment_count *
2909 sizeof(state->attachments[0]),
2910 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2911 if (state->attachments == NULL) {
2912 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2913 return cmd_buffer->record_result;
2914 }
2915
2916 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2917 struct radv_render_pass_attachment *att = &pass->attachments[i];
2918 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2919 VkImageAspectFlags clear_aspects = 0;
2920
2921 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2922 /* color attachment */
2923 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2924 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2925 }
2926 } else {
2927 /* depthstencil attachment */
2928 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2929 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2930 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2931 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2932 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2933 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2934 }
2935 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2936 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2937 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2938 }
2939 }
2940
2941 state->attachments[i].pending_clear_aspects = clear_aspects;
2942 state->attachments[i].cleared_views = 0;
2943 if (clear_aspects && info) {
2944 assert(info->clearValueCount > i);
2945 state->attachments[i].clear_value = info->pClearValues[i];
2946 }
2947
2948 state->attachments[i].current_layout = att->initial_layout;
2949 state->attachments[i].sample_location.count = 0;
2950 }
2951
2952 return VK_SUCCESS;
2953 }
2954
2955 VkResult radv_AllocateCommandBuffers(
2956 VkDevice _device,
2957 const VkCommandBufferAllocateInfo *pAllocateInfo,
2958 VkCommandBuffer *pCommandBuffers)
2959 {
2960 RADV_FROM_HANDLE(radv_device, device, _device);
2961 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2962
2963 VkResult result = VK_SUCCESS;
2964 uint32_t i;
2965
2966 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2967
2968 if (!list_empty(&pool->free_cmd_buffers)) {
2969 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2970
2971 list_del(&cmd_buffer->pool_link);
2972 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2973
2974 result = radv_reset_cmd_buffer(cmd_buffer);
2975 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2976 cmd_buffer->level = pAllocateInfo->level;
2977
2978 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2979 } else {
2980 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2981 &pCommandBuffers[i]);
2982 }
2983 if (result != VK_SUCCESS)
2984 break;
2985 }
2986
2987 if (result != VK_SUCCESS) {
2988 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2989 i, pCommandBuffers);
2990
2991 /* From the Vulkan 1.0.66 spec:
2992 *
2993 * "vkAllocateCommandBuffers can be used to create multiple
2994 * command buffers. If the creation of any of those command
2995 * buffers fails, the implementation must destroy all
2996 * successfully created command buffer objects from this
2997 * command, set all entries of the pCommandBuffers array to
2998 * NULL and return the error."
2999 */
3000 memset(pCommandBuffers, 0,
3001 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3002 }
3003
3004 return result;
3005 }
3006
3007 void radv_FreeCommandBuffers(
3008 VkDevice device,
3009 VkCommandPool commandPool,
3010 uint32_t commandBufferCount,
3011 const VkCommandBuffer *pCommandBuffers)
3012 {
3013 for (uint32_t i = 0; i < commandBufferCount; i++) {
3014 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3015
3016 if (cmd_buffer) {
3017 if (cmd_buffer->pool) {
3018 list_del(&cmd_buffer->pool_link);
3019 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3020 } else
3021 radv_cmd_buffer_destroy(cmd_buffer);
3022
3023 }
3024 }
3025 }
3026
3027 VkResult radv_ResetCommandBuffer(
3028 VkCommandBuffer commandBuffer,
3029 VkCommandBufferResetFlags flags)
3030 {
3031 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3032 return radv_reset_cmd_buffer(cmd_buffer);
3033 }
3034
3035 VkResult radv_BeginCommandBuffer(
3036 VkCommandBuffer commandBuffer,
3037 const VkCommandBufferBeginInfo *pBeginInfo)
3038 {
3039 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3040 VkResult result = VK_SUCCESS;
3041
3042 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3043 /* If the command buffer has already been resetted with
3044 * vkResetCommandBuffer, no need to do it again.
3045 */
3046 result = radv_reset_cmd_buffer(cmd_buffer);
3047 if (result != VK_SUCCESS)
3048 return result;
3049 }
3050
3051 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3052 cmd_buffer->state.last_primitive_reset_en = -1;
3053 cmd_buffer->state.last_index_type = -1;
3054 cmd_buffer->state.last_num_instances = -1;
3055 cmd_buffer->state.last_vertex_offset = -1;
3056 cmd_buffer->state.last_first_instance = -1;
3057 cmd_buffer->state.predication_type = -1;
3058 cmd_buffer->usage_flags = pBeginInfo->flags;
3059
3060 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3061 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3062 assert(pBeginInfo->pInheritanceInfo);
3063 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3064 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3065
3066 struct radv_subpass *subpass =
3067 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3068
3069 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3070 if (result != VK_SUCCESS)
3071 return result;
3072
3073 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3074 }
3075
3076 if (unlikely(cmd_buffer->device->trace_bo)) {
3077 struct radv_device *device = cmd_buffer->device;
3078
3079 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3080 device->trace_bo);
3081
3082 radv_cmd_buffer_trace_emit(cmd_buffer);
3083 }
3084
3085 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3086
3087 return result;
3088 }
3089
3090 void radv_CmdBindVertexBuffers(
3091 VkCommandBuffer commandBuffer,
3092 uint32_t firstBinding,
3093 uint32_t bindingCount,
3094 const VkBuffer* pBuffers,
3095 const VkDeviceSize* pOffsets)
3096 {
3097 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3098 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3099 bool changed = false;
3100
3101 /* We have to defer setting up vertex buffer since we need the buffer
3102 * stride from the pipeline. */
3103
3104 assert(firstBinding + bindingCount <= MAX_VBS);
3105 for (uint32_t i = 0; i < bindingCount; i++) {
3106 uint32_t idx = firstBinding + i;
3107
3108 if (!changed &&
3109 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3110 vb[idx].offset != pOffsets[i])) {
3111 changed = true;
3112 }
3113
3114 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3115 vb[idx].offset = pOffsets[i];
3116
3117 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3118 vb[idx].buffer->bo);
3119 }
3120
3121 if (!changed) {
3122 /* No state changes. */
3123 return;
3124 }
3125
3126 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3127 }
3128
3129 void radv_CmdBindIndexBuffer(
3130 VkCommandBuffer commandBuffer,
3131 VkBuffer buffer,
3132 VkDeviceSize offset,
3133 VkIndexType indexType)
3134 {
3135 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3136 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3137
3138 if (cmd_buffer->state.index_buffer == index_buffer &&
3139 cmd_buffer->state.index_offset == offset &&
3140 cmd_buffer->state.index_type == indexType) {
3141 /* No state changes. */
3142 return;
3143 }
3144
3145 cmd_buffer->state.index_buffer = index_buffer;
3146 cmd_buffer->state.index_offset = offset;
3147 cmd_buffer->state.index_type = indexType; /* vk matches hw */
3148 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3149 cmd_buffer->state.index_va += index_buffer->offset + offset;
3150
3151 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
3152 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
3153 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3154 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3155 }
3156
3157
3158 static void
3159 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3160 VkPipelineBindPoint bind_point,
3161 struct radv_descriptor_set *set, unsigned idx)
3162 {
3163 struct radeon_winsys *ws = cmd_buffer->device->ws;
3164
3165 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3166
3167 assert(set);
3168 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3169
3170 if (!cmd_buffer->device->use_global_bo_list) {
3171 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3172 if (set->descriptors[j])
3173 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3174 }
3175
3176 if(set->bo)
3177 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3178 }
3179
3180 void radv_CmdBindDescriptorSets(
3181 VkCommandBuffer commandBuffer,
3182 VkPipelineBindPoint pipelineBindPoint,
3183 VkPipelineLayout _layout,
3184 uint32_t firstSet,
3185 uint32_t descriptorSetCount,
3186 const VkDescriptorSet* pDescriptorSets,
3187 uint32_t dynamicOffsetCount,
3188 const uint32_t* pDynamicOffsets)
3189 {
3190 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3191 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3192 unsigned dyn_idx = 0;
3193
3194 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3195 struct radv_descriptor_state *descriptors_state =
3196 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3197
3198 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3199 unsigned idx = i + firstSet;
3200 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3201 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3202
3203 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3204 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3205 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3206 assert(dyn_idx < dynamicOffsetCount);
3207
3208 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3209 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3210 dst[0] = va;
3211 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3212 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3213 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3214 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3215 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3216 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3217 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3218 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3219 cmd_buffer->push_constant_stages |=
3220 set->layout->dynamic_shader_stages;
3221 }
3222 }
3223 }
3224
3225 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3226 struct radv_descriptor_set *set,
3227 struct radv_descriptor_set_layout *layout,
3228 VkPipelineBindPoint bind_point)
3229 {
3230 struct radv_descriptor_state *descriptors_state =
3231 radv_get_descriptors_state(cmd_buffer, bind_point);
3232 set->size = layout->size;
3233 set->layout = layout;
3234
3235 if (descriptors_state->push_set.capacity < set->size) {
3236 size_t new_size = MAX2(set->size, 1024);
3237 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3238 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3239
3240 free(set->mapped_ptr);
3241 set->mapped_ptr = malloc(new_size);
3242
3243 if (!set->mapped_ptr) {
3244 descriptors_state->push_set.capacity = 0;
3245 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3246 return false;
3247 }
3248
3249 descriptors_state->push_set.capacity = new_size;
3250 }
3251
3252 return true;
3253 }
3254
3255 void radv_meta_push_descriptor_set(
3256 struct radv_cmd_buffer* cmd_buffer,
3257 VkPipelineBindPoint pipelineBindPoint,
3258 VkPipelineLayout _layout,
3259 uint32_t set,
3260 uint32_t descriptorWriteCount,
3261 const VkWriteDescriptorSet* pDescriptorWrites)
3262 {
3263 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3264 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3265 unsigned bo_offset;
3266
3267 assert(set == 0);
3268 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3269
3270 push_set->size = layout->set[set].layout->size;
3271 push_set->layout = layout->set[set].layout;
3272
3273 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3274 &bo_offset,
3275 (void**) &push_set->mapped_ptr))
3276 return;
3277
3278 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3279 push_set->va += bo_offset;
3280
3281 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3282 radv_descriptor_set_to_handle(push_set),
3283 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3284
3285 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3286 }
3287
3288 void radv_CmdPushDescriptorSetKHR(
3289 VkCommandBuffer commandBuffer,
3290 VkPipelineBindPoint pipelineBindPoint,
3291 VkPipelineLayout _layout,
3292 uint32_t set,
3293 uint32_t descriptorWriteCount,
3294 const VkWriteDescriptorSet* pDescriptorWrites)
3295 {
3296 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3297 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3298 struct radv_descriptor_state *descriptors_state =
3299 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3300 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3301
3302 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3303
3304 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3305 layout->set[set].layout,
3306 pipelineBindPoint))
3307 return;
3308
3309 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3310 * because it is invalid, according to Vulkan spec.
3311 */
3312 for (int i = 0; i < descriptorWriteCount; i++) {
3313 MAYBE_UNUSED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3314 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3315 }
3316
3317 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3318 radv_descriptor_set_to_handle(push_set),
3319 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3320
3321 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3322 descriptors_state->push_dirty = true;
3323 }
3324
3325 void radv_CmdPushDescriptorSetWithTemplateKHR(
3326 VkCommandBuffer commandBuffer,
3327 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3328 VkPipelineLayout _layout,
3329 uint32_t set,
3330 const void* pData)
3331 {
3332 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3333 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3334 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3335 struct radv_descriptor_state *descriptors_state =
3336 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3337 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3338
3339 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3340
3341 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3342 layout->set[set].layout,
3343 templ->bind_point))
3344 return;
3345
3346 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3347 descriptorUpdateTemplate, pData);
3348
3349 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3350 descriptors_state->push_dirty = true;
3351 }
3352
3353 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3354 VkPipelineLayout layout,
3355 VkShaderStageFlags stageFlags,
3356 uint32_t offset,
3357 uint32_t size,
3358 const void* pValues)
3359 {
3360 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3361 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3362 cmd_buffer->push_constant_stages |= stageFlags;
3363 }
3364
3365 VkResult radv_EndCommandBuffer(
3366 VkCommandBuffer commandBuffer)
3367 {
3368 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3369
3370 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3371 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3372 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3373
3374 /* Make sure to sync all pending active queries at the end of
3375 * command buffer.
3376 */
3377 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3378
3379 si_emit_cache_flush(cmd_buffer);
3380 }
3381
3382 /* Make sure CP DMA is idle at the end of IBs because the kernel
3383 * doesn't wait for it.
3384 */
3385 si_cp_dma_wait_for_idle(cmd_buffer);
3386
3387 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3388 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3389
3390 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3391 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3392
3393 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3394
3395 return cmd_buffer->record_result;
3396 }
3397
3398 static void
3399 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3400 {
3401 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3402
3403 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3404 return;
3405
3406 assert(!pipeline->ctx_cs.cdw);
3407
3408 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3409
3410 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3411 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3412
3413 cmd_buffer->compute_scratch_size_needed =
3414 MAX2(cmd_buffer->compute_scratch_size_needed,
3415 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3416
3417 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3418 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3419
3420 if (unlikely(cmd_buffer->device->trace_bo))
3421 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3422 }
3423
3424 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3425 VkPipelineBindPoint bind_point)
3426 {
3427 struct radv_descriptor_state *descriptors_state =
3428 radv_get_descriptors_state(cmd_buffer, bind_point);
3429
3430 descriptors_state->dirty |= descriptors_state->valid;
3431 }
3432
3433 void radv_CmdBindPipeline(
3434 VkCommandBuffer commandBuffer,
3435 VkPipelineBindPoint pipelineBindPoint,
3436 VkPipeline _pipeline)
3437 {
3438 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3439 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3440
3441 switch (pipelineBindPoint) {
3442 case VK_PIPELINE_BIND_POINT_COMPUTE:
3443 if (cmd_buffer->state.compute_pipeline == pipeline)
3444 return;
3445 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3446
3447 cmd_buffer->state.compute_pipeline = pipeline;
3448 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3449 break;
3450 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3451 if (cmd_buffer->state.pipeline == pipeline)
3452 return;
3453 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3454
3455 cmd_buffer->state.pipeline = pipeline;
3456 if (!pipeline)
3457 break;
3458
3459 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3460 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3461
3462 /* the new vertex shader might not have the same user regs */
3463 cmd_buffer->state.last_first_instance = -1;
3464 cmd_buffer->state.last_vertex_offset = -1;
3465
3466 /* Prefetch all pipeline shaders at first draw time. */
3467 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3468
3469 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3470 radv_bind_streamout_state(cmd_buffer, pipeline);
3471
3472 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3473 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3474 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3475 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3476
3477 if (radv_pipeline_has_tess(pipeline))
3478 cmd_buffer->tess_rings_needed = true;
3479 break;
3480 default:
3481 assert(!"invalid bind point");
3482 break;
3483 }
3484 }
3485
3486 void radv_CmdSetViewport(
3487 VkCommandBuffer commandBuffer,
3488 uint32_t firstViewport,
3489 uint32_t viewportCount,
3490 const VkViewport* pViewports)
3491 {
3492 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3493 struct radv_cmd_state *state = &cmd_buffer->state;
3494 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3495
3496 assert(firstViewport < MAX_VIEWPORTS);
3497 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3498
3499 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3500 pViewports, viewportCount * sizeof(*pViewports))) {
3501 return;
3502 }
3503
3504 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3505 viewportCount * sizeof(*pViewports));
3506
3507 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3508 }
3509
3510 void radv_CmdSetScissor(
3511 VkCommandBuffer commandBuffer,
3512 uint32_t firstScissor,
3513 uint32_t scissorCount,
3514 const VkRect2D* pScissors)
3515 {
3516 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3517 struct radv_cmd_state *state = &cmd_buffer->state;
3518 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3519
3520 assert(firstScissor < MAX_SCISSORS);
3521 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3522
3523 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3524 scissorCount * sizeof(*pScissors))) {
3525 return;
3526 }
3527
3528 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3529 scissorCount * sizeof(*pScissors));
3530
3531 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3532 }
3533
3534 void radv_CmdSetLineWidth(
3535 VkCommandBuffer commandBuffer,
3536 float lineWidth)
3537 {
3538 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3539
3540 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3541 return;
3542
3543 cmd_buffer->state.dynamic.line_width = lineWidth;
3544 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3545 }
3546
3547 void radv_CmdSetDepthBias(
3548 VkCommandBuffer commandBuffer,
3549 float depthBiasConstantFactor,
3550 float depthBiasClamp,
3551 float depthBiasSlopeFactor)
3552 {
3553 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3554 struct radv_cmd_state *state = &cmd_buffer->state;
3555
3556 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3557 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3558 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3559 return;
3560 }
3561
3562 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3563 state->dynamic.depth_bias.clamp = depthBiasClamp;
3564 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3565
3566 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3567 }
3568
3569 void radv_CmdSetBlendConstants(
3570 VkCommandBuffer commandBuffer,
3571 const float blendConstants[4])
3572 {
3573 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3574 struct radv_cmd_state *state = &cmd_buffer->state;
3575
3576 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3577 return;
3578
3579 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3580
3581 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3582 }
3583
3584 void radv_CmdSetDepthBounds(
3585 VkCommandBuffer commandBuffer,
3586 float minDepthBounds,
3587 float maxDepthBounds)
3588 {
3589 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3590 struct radv_cmd_state *state = &cmd_buffer->state;
3591
3592 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3593 state->dynamic.depth_bounds.max == maxDepthBounds) {
3594 return;
3595 }
3596
3597 state->dynamic.depth_bounds.min = minDepthBounds;
3598 state->dynamic.depth_bounds.max = maxDepthBounds;
3599
3600 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3601 }
3602
3603 void radv_CmdSetStencilCompareMask(
3604 VkCommandBuffer commandBuffer,
3605 VkStencilFaceFlags faceMask,
3606 uint32_t compareMask)
3607 {
3608 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3609 struct radv_cmd_state *state = &cmd_buffer->state;
3610 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3611 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3612
3613 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3614 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3615 return;
3616 }
3617
3618 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3619 state->dynamic.stencil_compare_mask.front = compareMask;
3620 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3621 state->dynamic.stencil_compare_mask.back = compareMask;
3622
3623 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3624 }
3625
3626 void radv_CmdSetStencilWriteMask(
3627 VkCommandBuffer commandBuffer,
3628 VkStencilFaceFlags faceMask,
3629 uint32_t writeMask)
3630 {
3631 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3632 struct radv_cmd_state *state = &cmd_buffer->state;
3633 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3634 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3635
3636 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3637 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3638 return;
3639 }
3640
3641 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3642 state->dynamic.stencil_write_mask.front = writeMask;
3643 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3644 state->dynamic.stencil_write_mask.back = writeMask;
3645
3646 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3647 }
3648
3649 void radv_CmdSetStencilReference(
3650 VkCommandBuffer commandBuffer,
3651 VkStencilFaceFlags faceMask,
3652 uint32_t reference)
3653 {
3654 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3655 struct radv_cmd_state *state = &cmd_buffer->state;
3656 bool front_same = state->dynamic.stencil_reference.front == reference;
3657 bool back_same = state->dynamic.stencil_reference.back == reference;
3658
3659 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3660 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3661 return;
3662 }
3663
3664 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3665 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3666 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3667 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3668
3669 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3670 }
3671
3672 void radv_CmdSetDiscardRectangleEXT(
3673 VkCommandBuffer commandBuffer,
3674 uint32_t firstDiscardRectangle,
3675 uint32_t discardRectangleCount,
3676 const VkRect2D* pDiscardRectangles)
3677 {
3678 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3679 struct radv_cmd_state *state = &cmd_buffer->state;
3680 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3681
3682 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3683 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3684
3685 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3686 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3687 return;
3688 }
3689
3690 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3691 pDiscardRectangles, discardRectangleCount);
3692
3693 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3694 }
3695
3696 void radv_CmdSetSampleLocationsEXT(
3697 VkCommandBuffer commandBuffer,
3698 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3699 {
3700 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3701 struct radv_cmd_state *state = &cmd_buffer->state;
3702
3703 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3704
3705 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3706 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3707 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3708 typed_memcpy(&state->dynamic.sample_location.locations[0],
3709 pSampleLocationsInfo->pSampleLocations,
3710 pSampleLocationsInfo->sampleLocationsCount);
3711
3712 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3713 }
3714
3715 void radv_CmdExecuteCommands(
3716 VkCommandBuffer commandBuffer,
3717 uint32_t commandBufferCount,
3718 const VkCommandBuffer* pCmdBuffers)
3719 {
3720 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3721
3722 assert(commandBufferCount > 0);
3723
3724 /* Emit pending flushes on primary prior to executing secondary */
3725 si_emit_cache_flush(primary);
3726
3727 for (uint32_t i = 0; i < commandBufferCount; i++) {
3728 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3729
3730 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3731 secondary->scratch_size_needed);
3732 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3733 secondary->compute_scratch_size_needed);
3734
3735 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3736 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3737 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3738 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3739 if (secondary->tess_rings_needed)
3740 primary->tess_rings_needed = true;
3741 if (secondary->sample_positions_needed)
3742 primary->sample_positions_needed = true;
3743
3744 if (!secondary->state.framebuffer &&
3745 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
3746 /* Emit the framebuffer state from primary if secondary
3747 * has been recorded without a framebuffer, otherwise
3748 * fast color/depth clears can't work.
3749 */
3750 radv_emit_framebuffer_state(primary);
3751 }
3752
3753 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3754
3755
3756 /* When the secondary command buffer is compute only we don't
3757 * need to re-emit the current graphics pipeline.
3758 */
3759 if (secondary->state.emitted_pipeline) {
3760 primary->state.emitted_pipeline =
3761 secondary->state.emitted_pipeline;
3762 }
3763
3764 /* When the secondary command buffer is graphics only we don't
3765 * need to re-emit the current compute pipeline.
3766 */
3767 if (secondary->state.emitted_compute_pipeline) {
3768 primary->state.emitted_compute_pipeline =
3769 secondary->state.emitted_compute_pipeline;
3770 }
3771
3772 /* Only re-emit the draw packets when needed. */
3773 if (secondary->state.last_primitive_reset_en != -1) {
3774 primary->state.last_primitive_reset_en =
3775 secondary->state.last_primitive_reset_en;
3776 }
3777
3778 if (secondary->state.last_primitive_reset_index) {
3779 primary->state.last_primitive_reset_index =
3780 secondary->state.last_primitive_reset_index;
3781 }
3782
3783 if (secondary->state.last_ia_multi_vgt_param) {
3784 primary->state.last_ia_multi_vgt_param =
3785 secondary->state.last_ia_multi_vgt_param;
3786 }
3787
3788 primary->state.last_first_instance = secondary->state.last_first_instance;
3789 primary->state.last_num_instances = secondary->state.last_num_instances;
3790 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3791
3792 if (secondary->state.last_index_type != -1) {
3793 primary->state.last_index_type =
3794 secondary->state.last_index_type;
3795 }
3796 }
3797
3798 /* After executing commands from secondary buffers we have to dirty
3799 * some states.
3800 */
3801 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3802 RADV_CMD_DIRTY_INDEX_BUFFER |
3803 RADV_CMD_DIRTY_DYNAMIC_ALL;
3804 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3805 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3806 }
3807
3808 VkResult radv_CreateCommandPool(
3809 VkDevice _device,
3810 const VkCommandPoolCreateInfo* pCreateInfo,
3811 const VkAllocationCallbacks* pAllocator,
3812 VkCommandPool* pCmdPool)
3813 {
3814 RADV_FROM_HANDLE(radv_device, device, _device);
3815 struct radv_cmd_pool *pool;
3816
3817 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3818 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3819 if (pool == NULL)
3820 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3821
3822 if (pAllocator)
3823 pool->alloc = *pAllocator;
3824 else
3825 pool->alloc = device->alloc;
3826
3827 list_inithead(&pool->cmd_buffers);
3828 list_inithead(&pool->free_cmd_buffers);
3829
3830 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3831
3832 *pCmdPool = radv_cmd_pool_to_handle(pool);
3833
3834 return VK_SUCCESS;
3835
3836 }
3837
3838 void radv_DestroyCommandPool(
3839 VkDevice _device,
3840 VkCommandPool commandPool,
3841 const VkAllocationCallbacks* pAllocator)
3842 {
3843 RADV_FROM_HANDLE(radv_device, device, _device);
3844 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3845
3846 if (!pool)
3847 return;
3848
3849 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3850 &pool->cmd_buffers, pool_link) {
3851 radv_cmd_buffer_destroy(cmd_buffer);
3852 }
3853
3854 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3855 &pool->free_cmd_buffers, pool_link) {
3856 radv_cmd_buffer_destroy(cmd_buffer);
3857 }
3858
3859 vk_free2(&device->alloc, pAllocator, pool);
3860 }
3861
3862 VkResult radv_ResetCommandPool(
3863 VkDevice device,
3864 VkCommandPool commandPool,
3865 VkCommandPoolResetFlags flags)
3866 {
3867 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3868 VkResult result;
3869
3870 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3871 &pool->cmd_buffers, pool_link) {
3872 result = radv_reset_cmd_buffer(cmd_buffer);
3873 if (result != VK_SUCCESS)
3874 return result;
3875 }
3876
3877 return VK_SUCCESS;
3878 }
3879
3880 void radv_TrimCommandPool(
3881 VkDevice device,
3882 VkCommandPool commandPool,
3883 VkCommandPoolTrimFlags flags)
3884 {
3885 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3886
3887 if (!pool)
3888 return;
3889
3890 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3891 &pool->free_cmd_buffers, pool_link) {
3892 radv_cmd_buffer_destroy(cmd_buffer);
3893 }
3894 }
3895
3896 static void
3897 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3898 uint32_t subpass_id)
3899 {
3900 struct radv_cmd_state *state = &cmd_buffer->state;
3901 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3902
3903 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3904 cmd_buffer->cs, 4096);
3905
3906 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3907
3908 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3909
3910 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3911 const uint32_t a = subpass->attachments[i].attachment;
3912 if (a == VK_ATTACHMENT_UNUSED)
3913 continue;
3914
3915 radv_handle_subpass_image_transition(cmd_buffer,
3916 subpass->attachments[i],
3917 true);
3918 }
3919
3920 radv_cmd_buffer_clear_subpass(cmd_buffer);
3921
3922 assert(cmd_buffer->cs->cdw <= cdw_max);
3923 }
3924
3925 static void
3926 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3927 {
3928 struct radv_cmd_state *state = &cmd_buffer->state;
3929 const struct radv_subpass *subpass = state->subpass;
3930 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3931
3932 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3933
3934 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3935 const uint32_t a = subpass->attachments[i].attachment;
3936 if (a == VK_ATTACHMENT_UNUSED)
3937 continue;
3938
3939 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
3940 continue;
3941
3942 VkImageLayout layout = state->pass->attachments[a].final_layout;
3943 struct radv_subpass_attachment att = { a, layout };
3944 radv_handle_subpass_image_transition(cmd_buffer, att, false);
3945 }
3946 }
3947
3948 void radv_CmdBeginRenderPass(
3949 VkCommandBuffer commandBuffer,
3950 const VkRenderPassBeginInfo* pRenderPassBegin,
3951 VkSubpassContents contents)
3952 {
3953 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3954 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3955 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3956 VkResult result;
3957
3958 cmd_buffer->state.framebuffer = framebuffer;
3959 cmd_buffer->state.pass = pass;
3960 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3961
3962 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3963 if (result != VK_SUCCESS)
3964 return;
3965
3966 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
3967 if (result != VK_SUCCESS)
3968 return;
3969
3970 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
3971 }
3972
3973 void radv_CmdBeginRenderPass2KHR(
3974 VkCommandBuffer commandBuffer,
3975 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3976 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3977 {
3978 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3979 pSubpassBeginInfo->contents);
3980 }
3981
3982 void radv_CmdNextSubpass(
3983 VkCommandBuffer commandBuffer,
3984 VkSubpassContents contents)
3985 {
3986 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3987
3988 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
3989 radv_cmd_buffer_end_subpass(cmd_buffer);
3990 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
3991 }
3992
3993 void radv_CmdNextSubpass2KHR(
3994 VkCommandBuffer commandBuffer,
3995 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3996 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3997 {
3998 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3999 }
4000
4001 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4002 {
4003 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4004 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4005 if (!radv_get_shader(pipeline, stage))
4006 continue;
4007
4008 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4009 if (loc->sgpr_idx == -1)
4010 continue;
4011 uint32_t base_reg = pipeline->user_data_0[stage];
4012 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4013
4014 }
4015 if (pipeline->gs_copy_shader) {
4016 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4017 if (loc->sgpr_idx != -1) {
4018 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4019 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4020 }
4021 }
4022 }
4023
4024 static void
4025 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4026 uint32_t vertex_count,
4027 bool use_opaque)
4028 {
4029 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4030 radeon_emit(cmd_buffer->cs, vertex_count);
4031 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4032 S_0287F0_USE_OPAQUE(use_opaque));
4033 }
4034
4035 static void
4036 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4037 uint64_t index_va,
4038 uint32_t index_count)
4039 {
4040 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4041 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4042 radeon_emit(cmd_buffer->cs, index_va);
4043 radeon_emit(cmd_buffer->cs, index_va >> 32);
4044 radeon_emit(cmd_buffer->cs, index_count);
4045 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4046 }
4047
4048 static void
4049 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4050 bool indexed,
4051 uint32_t draw_count,
4052 uint64_t count_va,
4053 uint32_t stride)
4054 {
4055 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4056 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4057 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4058 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
4059 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4060 bool predicating = cmd_buffer->state.predicating;
4061 assert(base_reg);
4062
4063 /* just reset draw state for vertex data */
4064 cmd_buffer->state.last_first_instance = -1;
4065 cmd_buffer->state.last_num_instances = -1;
4066 cmd_buffer->state.last_vertex_offset = -1;
4067
4068 if (draw_count == 1 && !count_va && !draw_id_enable) {
4069 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4070 PKT3_DRAW_INDIRECT, 3, predicating));
4071 radeon_emit(cs, 0);
4072 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4073 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4074 radeon_emit(cs, di_src_sel);
4075 } else {
4076 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4077 PKT3_DRAW_INDIRECT_MULTI,
4078 8, predicating));
4079 radeon_emit(cs, 0);
4080 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4081 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4082 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4083 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4084 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4085 radeon_emit(cs, draw_count); /* count */
4086 radeon_emit(cs, count_va); /* count_addr */
4087 radeon_emit(cs, count_va >> 32);
4088 radeon_emit(cs, stride); /* stride */
4089 radeon_emit(cs, di_src_sel);
4090 }
4091 }
4092
4093 static void
4094 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4095 const struct radv_draw_info *info)
4096 {
4097 struct radv_cmd_state *state = &cmd_buffer->state;
4098 struct radeon_winsys *ws = cmd_buffer->device->ws;
4099 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4100
4101 if (info->indirect) {
4102 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4103 uint64_t count_va = 0;
4104
4105 va += info->indirect->offset + info->indirect_offset;
4106
4107 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4108
4109 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4110 radeon_emit(cs, 1);
4111 radeon_emit(cs, va);
4112 radeon_emit(cs, va >> 32);
4113
4114 if (info->count_buffer) {
4115 count_va = radv_buffer_get_va(info->count_buffer->bo);
4116 count_va += info->count_buffer->offset +
4117 info->count_buffer_offset;
4118
4119 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4120 }
4121
4122 if (!state->subpass->view_mask) {
4123 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4124 info->indexed,
4125 info->count,
4126 count_va,
4127 info->stride);
4128 } else {
4129 unsigned i;
4130 for_each_bit(i, state->subpass->view_mask) {
4131 radv_emit_view_index(cmd_buffer, i);
4132
4133 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4134 info->indexed,
4135 info->count,
4136 count_va,
4137 info->stride);
4138 }
4139 }
4140 } else {
4141 assert(state->pipeline->graphics.vtx_base_sgpr);
4142
4143 if (info->vertex_offset != state->last_vertex_offset ||
4144 info->first_instance != state->last_first_instance) {
4145 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4146 state->pipeline->graphics.vtx_emit_num);
4147
4148 radeon_emit(cs, info->vertex_offset);
4149 radeon_emit(cs, info->first_instance);
4150 if (state->pipeline->graphics.vtx_emit_num == 3)
4151 radeon_emit(cs, 0);
4152 state->last_first_instance = info->first_instance;
4153 state->last_vertex_offset = info->vertex_offset;
4154 }
4155
4156 if (state->last_num_instances != info->instance_count) {
4157 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4158 radeon_emit(cs, info->instance_count);
4159 state->last_num_instances = info->instance_count;
4160 }
4161
4162 if (info->indexed) {
4163 int index_size = state->index_type ? 4 : 2;
4164 uint64_t index_va;
4165
4166 index_va = state->index_va;
4167 index_va += info->first_index * index_size;
4168
4169 if (!state->subpass->view_mask) {
4170 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4171 index_va,
4172 info->count);
4173 } else {
4174 unsigned i;
4175 for_each_bit(i, state->subpass->view_mask) {
4176 radv_emit_view_index(cmd_buffer, i);
4177
4178 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4179 index_va,
4180 info->count);
4181 }
4182 }
4183 } else {
4184 if (!state->subpass->view_mask) {
4185 radv_cs_emit_draw_packet(cmd_buffer,
4186 info->count,
4187 !!info->strmout_buffer);
4188 } else {
4189 unsigned i;
4190 for_each_bit(i, state->subpass->view_mask) {
4191 radv_emit_view_index(cmd_buffer, i);
4192
4193 radv_cs_emit_draw_packet(cmd_buffer,
4194 info->count,
4195 !!info->strmout_buffer);
4196 }
4197 }
4198 }
4199 }
4200 }
4201
4202 /*
4203 * Vega and raven have a bug which triggers if there are multiple context
4204 * register contexts active at the same time with different scissor values.
4205 *
4206 * There are two possible workarounds:
4207 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4208 * there is only ever 1 active set of scissor values at the same time.
4209 *
4210 * 2) Whenever the hardware switches contexts we have to set the scissor
4211 * registers again even if it is a noop. That way the new context gets
4212 * the correct scissor values.
4213 *
4214 * This implements option 2. radv_need_late_scissor_emission needs to
4215 * return true on affected HW if radv_emit_all_graphics_states sets
4216 * any context registers.
4217 */
4218 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4219 const struct radv_draw_info *info)
4220 {
4221 struct radv_cmd_state *state = &cmd_buffer->state;
4222
4223 if (!cmd_buffer->device->physical_device->has_scissor_bug)
4224 return false;
4225
4226 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4227 return true;
4228
4229 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4230
4231 /* Index, vertex and streamout buffers don't change context regs, and
4232 * pipeline is already handled.
4233 */
4234 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4235 RADV_CMD_DIRTY_VERTEX_BUFFER |
4236 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4237 RADV_CMD_DIRTY_PIPELINE);
4238
4239 if (cmd_buffer->state.dirty & used_states)
4240 return true;
4241
4242 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4243 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
4244 return true;
4245
4246 return false;
4247 }
4248
4249 static void
4250 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4251 const struct radv_draw_info *info)
4252 {
4253 bool late_scissor_emission;
4254
4255 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4256 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4257 radv_emit_rbplus_state(cmd_buffer);
4258
4259 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4260 radv_emit_graphics_pipeline(cmd_buffer);
4261
4262 /* This should be before the cmd_buffer->state.dirty is cleared
4263 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4264 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4265 late_scissor_emission =
4266 radv_need_late_scissor_emission(cmd_buffer, info);
4267
4268 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4269 radv_emit_framebuffer_state(cmd_buffer);
4270
4271 if (info->indexed) {
4272 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4273 radv_emit_index_buffer(cmd_buffer);
4274 } else {
4275 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4276 * so the state must be re-emitted before the next indexed
4277 * draw.
4278 */
4279 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4280 cmd_buffer->state.last_index_type = -1;
4281 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4282 }
4283 }
4284
4285 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4286
4287 radv_emit_draw_registers(cmd_buffer, info);
4288
4289 if (late_scissor_emission)
4290 radv_emit_scissor(cmd_buffer);
4291 }
4292
4293 static void
4294 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4295 const struct radv_draw_info *info)
4296 {
4297 struct radeon_info *rad_info =
4298 &cmd_buffer->device->physical_device->rad_info;
4299 bool has_prefetch =
4300 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4301 bool pipeline_is_dirty =
4302 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4303 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4304
4305 MAYBE_UNUSED unsigned cdw_max =
4306 radeon_check_space(cmd_buffer->device->ws,
4307 cmd_buffer->cs, 4096);
4308
4309 if (likely(!info->indirect)) {
4310 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4311 * no workaround for indirect draws, but we can at least skip
4312 * direct draws.
4313 */
4314 if (unlikely(!info->instance_count))
4315 return;
4316
4317 /* Handle count == 0. */
4318 if (unlikely(!info->count && !info->strmout_buffer))
4319 return;
4320 }
4321
4322 /* Use optimal packet order based on whether we need to sync the
4323 * pipeline.
4324 */
4325 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4326 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4327 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4328 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4329 /* If we have to wait for idle, set all states first, so that
4330 * all SET packets are processed in parallel with previous draw
4331 * calls. Then upload descriptors, set shader pointers, and
4332 * draw, and prefetch at the end. This ensures that the time
4333 * the CUs are idle is very short. (there are only SET_SH
4334 * packets between the wait and the draw)
4335 */
4336 radv_emit_all_graphics_states(cmd_buffer, info);
4337 si_emit_cache_flush(cmd_buffer);
4338 /* <-- CUs are idle here --> */
4339
4340 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4341
4342 radv_emit_draw_packets(cmd_buffer, info);
4343 /* <-- CUs are busy here --> */
4344
4345 /* Start prefetches after the draw has been started. Both will
4346 * run in parallel, but starting the draw first is more
4347 * important.
4348 */
4349 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4350 radv_emit_prefetch_L2(cmd_buffer,
4351 cmd_buffer->state.pipeline, false);
4352 }
4353 } else {
4354 /* If we don't wait for idle, start prefetches first, then set
4355 * states, and draw at the end.
4356 */
4357 si_emit_cache_flush(cmd_buffer);
4358
4359 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4360 /* Only prefetch the vertex shader and VBO descriptors
4361 * in order to start the draw as soon as possible.
4362 */
4363 radv_emit_prefetch_L2(cmd_buffer,
4364 cmd_buffer->state.pipeline, true);
4365 }
4366
4367 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4368
4369 radv_emit_all_graphics_states(cmd_buffer, info);
4370 radv_emit_draw_packets(cmd_buffer, info);
4371
4372 /* Prefetch the remaining shaders after the draw has been
4373 * started.
4374 */
4375 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4376 radv_emit_prefetch_L2(cmd_buffer,
4377 cmd_buffer->state.pipeline, false);
4378 }
4379 }
4380
4381 /* Workaround for a VGT hang when streamout is enabled.
4382 * It must be done after drawing.
4383 */
4384 if (cmd_buffer->state.streamout.streamout_enabled &&
4385 (rad_info->family == CHIP_HAWAII ||
4386 rad_info->family == CHIP_TONGA ||
4387 rad_info->family == CHIP_FIJI)) {
4388 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4389 }
4390
4391 assert(cmd_buffer->cs->cdw <= cdw_max);
4392 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4393 }
4394
4395 void radv_CmdDraw(
4396 VkCommandBuffer commandBuffer,
4397 uint32_t vertexCount,
4398 uint32_t instanceCount,
4399 uint32_t firstVertex,
4400 uint32_t firstInstance)
4401 {
4402 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4403 struct radv_draw_info info = {};
4404
4405 info.count = vertexCount;
4406 info.instance_count = instanceCount;
4407 info.first_instance = firstInstance;
4408 info.vertex_offset = firstVertex;
4409
4410 radv_draw(cmd_buffer, &info);
4411 }
4412
4413 void radv_CmdDrawIndexed(
4414 VkCommandBuffer commandBuffer,
4415 uint32_t indexCount,
4416 uint32_t instanceCount,
4417 uint32_t firstIndex,
4418 int32_t vertexOffset,
4419 uint32_t firstInstance)
4420 {
4421 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4422 struct radv_draw_info info = {};
4423
4424 info.indexed = true;
4425 info.count = indexCount;
4426 info.instance_count = instanceCount;
4427 info.first_index = firstIndex;
4428 info.vertex_offset = vertexOffset;
4429 info.first_instance = firstInstance;
4430
4431 radv_draw(cmd_buffer, &info);
4432 }
4433
4434 void radv_CmdDrawIndirect(
4435 VkCommandBuffer commandBuffer,
4436 VkBuffer _buffer,
4437 VkDeviceSize offset,
4438 uint32_t drawCount,
4439 uint32_t stride)
4440 {
4441 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4442 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4443 struct radv_draw_info info = {};
4444
4445 info.count = drawCount;
4446 info.indirect = buffer;
4447 info.indirect_offset = offset;
4448 info.stride = stride;
4449
4450 radv_draw(cmd_buffer, &info);
4451 }
4452
4453 void radv_CmdDrawIndexedIndirect(
4454 VkCommandBuffer commandBuffer,
4455 VkBuffer _buffer,
4456 VkDeviceSize offset,
4457 uint32_t drawCount,
4458 uint32_t stride)
4459 {
4460 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4461 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4462 struct radv_draw_info info = {};
4463
4464 info.indexed = true;
4465 info.count = drawCount;
4466 info.indirect = buffer;
4467 info.indirect_offset = offset;
4468 info.stride = stride;
4469
4470 radv_draw(cmd_buffer, &info);
4471 }
4472
4473 void radv_CmdDrawIndirectCountKHR(
4474 VkCommandBuffer commandBuffer,
4475 VkBuffer _buffer,
4476 VkDeviceSize offset,
4477 VkBuffer _countBuffer,
4478 VkDeviceSize countBufferOffset,
4479 uint32_t maxDrawCount,
4480 uint32_t stride)
4481 {
4482 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4483 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4484 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4485 struct radv_draw_info info = {};
4486
4487 info.count = maxDrawCount;
4488 info.indirect = buffer;
4489 info.indirect_offset = offset;
4490 info.count_buffer = count_buffer;
4491 info.count_buffer_offset = countBufferOffset;
4492 info.stride = stride;
4493
4494 radv_draw(cmd_buffer, &info);
4495 }
4496
4497 void radv_CmdDrawIndexedIndirectCountKHR(
4498 VkCommandBuffer commandBuffer,
4499 VkBuffer _buffer,
4500 VkDeviceSize offset,
4501 VkBuffer _countBuffer,
4502 VkDeviceSize countBufferOffset,
4503 uint32_t maxDrawCount,
4504 uint32_t stride)
4505 {
4506 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4507 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4508 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4509 struct radv_draw_info info = {};
4510
4511 info.indexed = true;
4512 info.count = maxDrawCount;
4513 info.indirect = buffer;
4514 info.indirect_offset = offset;
4515 info.count_buffer = count_buffer;
4516 info.count_buffer_offset = countBufferOffset;
4517 info.stride = stride;
4518
4519 radv_draw(cmd_buffer, &info);
4520 }
4521
4522 struct radv_dispatch_info {
4523 /**
4524 * Determine the layout of the grid (in block units) to be used.
4525 */
4526 uint32_t blocks[3];
4527
4528 /**
4529 * A starting offset for the grid. If unaligned is set, the offset
4530 * must still be aligned.
4531 */
4532 uint32_t offsets[3];
4533 /**
4534 * Whether it's an unaligned compute dispatch.
4535 */
4536 bool unaligned;
4537
4538 /**
4539 * Indirect compute parameters resource.
4540 */
4541 struct radv_buffer *indirect;
4542 uint64_t indirect_offset;
4543 };
4544
4545 static void
4546 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4547 const struct radv_dispatch_info *info)
4548 {
4549 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4550 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4551 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4552 struct radeon_winsys *ws = cmd_buffer->device->ws;
4553 bool predicating = cmd_buffer->state.predicating;
4554 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4555 struct radv_userdata_info *loc;
4556
4557 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4558 AC_UD_CS_GRID_SIZE);
4559
4560 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4561
4562 if (info->indirect) {
4563 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4564
4565 va += info->indirect->offset + info->indirect_offset;
4566
4567 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4568
4569 if (loc->sgpr_idx != -1) {
4570 for (unsigned i = 0; i < 3; ++i) {
4571 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4572 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4573 COPY_DATA_DST_SEL(COPY_DATA_REG));
4574 radeon_emit(cs, (va + 4 * i));
4575 radeon_emit(cs, (va + 4 * i) >> 32);
4576 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4577 + loc->sgpr_idx * 4) >> 2) + i);
4578 radeon_emit(cs, 0);
4579 }
4580 }
4581
4582 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4583 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4584 PKT3_SHADER_TYPE_S(1));
4585 radeon_emit(cs, va);
4586 radeon_emit(cs, va >> 32);
4587 radeon_emit(cs, dispatch_initiator);
4588 } else {
4589 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4590 PKT3_SHADER_TYPE_S(1));
4591 radeon_emit(cs, 1);
4592 radeon_emit(cs, va);
4593 radeon_emit(cs, va >> 32);
4594
4595 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4596 PKT3_SHADER_TYPE_S(1));
4597 radeon_emit(cs, 0);
4598 radeon_emit(cs, dispatch_initiator);
4599 }
4600 } else {
4601 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4602 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4603
4604 if (info->unaligned) {
4605 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4606 unsigned remainder[3];
4607
4608 /* If aligned, these should be an entire block size,
4609 * not 0.
4610 */
4611 remainder[0] = blocks[0] + cs_block_size[0] -
4612 align_u32_npot(blocks[0], cs_block_size[0]);
4613 remainder[1] = blocks[1] + cs_block_size[1] -
4614 align_u32_npot(blocks[1], cs_block_size[1]);
4615 remainder[2] = blocks[2] + cs_block_size[2] -
4616 align_u32_npot(blocks[2], cs_block_size[2]);
4617
4618 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4619 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4620 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4621
4622 for(unsigned i = 0; i < 3; ++i) {
4623 assert(offsets[i] % cs_block_size[i] == 0);
4624 offsets[i] /= cs_block_size[i];
4625 }
4626
4627 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4628 radeon_emit(cs,
4629 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4630 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4631 radeon_emit(cs,
4632 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4633 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4634 radeon_emit(cs,
4635 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4636 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4637
4638 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4639 }
4640
4641 if (loc->sgpr_idx != -1) {
4642 assert(loc->num_sgprs == 3);
4643
4644 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4645 loc->sgpr_idx * 4, 3);
4646 radeon_emit(cs, blocks[0]);
4647 radeon_emit(cs, blocks[1]);
4648 radeon_emit(cs, blocks[2]);
4649 }
4650
4651 if (offsets[0] || offsets[1] || offsets[2]) {
4652 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4653 radeon_emit(cs, offsets[0]);
4654 radeon_emit(cs, offsets[1]);
4655 radeon_emit(cs, offsets[2]);
4656
4657 /* The blocks in the packet are not counts but end values. */
4658 for (unsigned i = 0; i < 3; ++i)
4659 blocks[i] += offsets[i];
4660 } else {
4661 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4662 }
4663
4664 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4665 PKT3_SHADER_TYPE_S(1));
4666 radeon_emit(cs, blocks[0]);
4667 radeon_emit(cs, blocks[1]);
4668 radeon_emit(cs, blocks[2]);
4669 radeon_emit(cs, dispatch_initiator);
4670 }
4671
4672 assert(cmd_buffer->cs->cdw <= cdw_max);
4673 }
4674
4675 static void
4676 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4677 {
4678 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4679 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4680 }
4681
4682 static void
4683 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4684 const struct radv_dispatch_info *info)
4685 {
4686 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4687 bool has_prefetch =
4688 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4689 bool pipeline_is_dirty = pipeline &&
4690 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4691
4692 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4693 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4694 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4695 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4696 /* If we have to wait for idle, set all states first, so that
4697 * all SET packets are processed in parallel with previous draw
4698 * calls. Then upload descriptors, set shader pointers, and
4699 * dispatch, and prefetch at the end. This ensures that the
4700 * time the CUs are idle is very short. (there are only SET_SH
4701 * packets between the wait and the draw)
4702 */
4703 radv_emit_compute_pipeline(cmd_buffer);
4704 si_emit_cache_flush(cmd_buffer);
4705 /* <-- CUs are idle here --> */
4706
4707 radv_upload_compute_shader_descriptors(cmd_buffer);
4708
4709 radv_emit_dispatch_packets(cmd_buffer, info);
4710 /* <-- CUs are busy here --> */
4711
4712 /* Start prefetches after the dispatch has been started. Both
4713 * will run in parallel, but starting the dispatch first is
4714 * more important.
4715 */
4716 if (has_prefetch && pipeline_is_dirty) {
4717 radv_emit_shader_prefetch(cmd_buffer,
4718 pipeline->shaders[MESA_SHADER_COMPUTE]);
4719 }
4720 } else {
4721 /* If we don't wait for idle, start prefetches first, then set
4722 * states, and dispatch at the end.
4723 */
4724 si_emit_cache_flush(cmd_buffer);
4725
4726 if (has_prefetch && pipeline_is_dirty) {
4727 radv_emit_shader_prefetch(cmd_buffer,
4728 pipeline->shaders[MESA_SHADER_COMPUTE]);
4729 }
4730
4731 radv_upload_compute_shader_descriptors(cmd_buffer);
4732
4733 radv_emit_compute_pipeline(cmd_buffer);
4734 radv_emit_dispatch_packets(cmd_buffer, info);
4735 }
4736
4737 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4738 }
4739
4740 void radv_CmdDispatchBase(
4741 VkCommandBuffer commandBuffer,
4742 uint32_t base_x,
4743 uint32_t base_y,
4744 uint32_t base_z,
4745 uint32_t x,
4746 uint32_t y,
4747 uint32_t z)
4748 {
4749 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4750 struct radv_dispatch_info info = {};
4751
4752 info.blocks[0] = x;
4753 info.blocks[1] = y;
4754 info.blocks[2] = z;
4755
4756 info.offsets[0] = base_x;
4757 info.offsets[1] = base_y;
4758 info.offsets[2] = base_z;
4759 radv_dispatch(cmd_buffer, &info);
4760 }
4761
4762 void radv_CmdDispatch(
4763 VkCommandBuffer commandBuffer,
4764 uint32_t x,
4765 uint32_t y,
4766 uint32_t z)
4767 {
4768 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4769 }
4770
4771 void radv_CmdDispatchIndirect(
4772 VkCommandBuffer commandBuffer,
4773 VkBuffer _buffer,
4774 VkDeviceSize offset)
4775 {
4776 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4777 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4778 struct radv_dispatch_info info = {};
4779
4780 info.indirect = buffer;
4781 info.indirect_offset = offset;
4782
4783 radv_dispatch(cmd_buffer, &info);
4784 }
4785
4786 void radv_unaligned_dispatch(
4787 struct radv_cmd_buffer *cmd_buffer,
4788 uint32_t x,
4789 uint32_t y,
4790 uint32_t z)
4791 {
4792 struct radv_dispatch_info info = {};
4793
4794 info.blocks[0] = x;
4795 info.blocks[1] = y;
4796 info.blocks[2] = z;
4797 info.unaligned = 1;
4798
4799 radv_dispatch(cmd_buffer, &info);
4800 }
4801
4802 void radv_CmdEndRenderPass(
4803 VkCommandBuffer commandBuffer)
4804 {
4805 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4806
4807 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4808
4809 radv_cmd_buffer_end_subpass(cmd_buffer);
4810
4811 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4812 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4813
4814 cmd_buffer->state.pass = NULL;
4815 cmd_buffer->state.subpass = NULL;
4816 cmd_buffer->state.attachments = NULL;
4817 cmd_buffer->state.framebuffer = NULL;
4818 cmd_buffer->state.subpass_sample_locs = NULL;
4819 }
4820
4821 void radv_CmdEndRenderPass2KHR(
4822 VkCommandBuffer commandBuffer,
4823 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4824 {
4825 radv_CmdEndRenderPass(commandBuffer);
4826 }
4827
4828 /*
4829 * For HTILE we have the following interesting clear words:
4830 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4831 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4832 * 0xfffffff0: Clear depth to 1.0
4833 * 0x00000000: Clear depth to 0.0
4834 */
4835 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4836 struct radv_image *image,
4837 const VkImageSubresourceRange *range,
4838 uint32_t clear_word)
4839 {
4840 assert(range->baseMipLevel == 0);
4841 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4842 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4843 struct radv_cmd_state *state = &cmd_buffer->state;
4844 VkClearDepthStencilValue value = {};
4845
4846 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4847 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4848
4849 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
4850
4851 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4852
4853 if (vk_format_is_stencil(image->vk_format))
4854 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4855
4856 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4857
4858 if (radv_image_is_tc_compat_htile(image)) {
4859 /* Initialize the TC-compat metada value to 0 because by
4860 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4861 * need have to conditionally update its value when performing
4862 * a fast depth clear.
4863 */
4864 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4865 }
4866 }
4867
4868 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4869 struct radv_image *image,
4870 VkImageLayout src_layout,
4871 VkImageLayout dst_layout,
4872 unsigned src_queue_mask,
4873 unsigned dst_queue_mask,
4874 const VkImageSubresourceRange *range,
4875 struct radv_sample_locations_state *sample_locs)
4876 {
4877 if (!radv_image_has_htile(image))
4878 return;
4879
4880 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4881 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4882
4883 if (radv_layout_is_htile_compressed(image, dst_layout,
4884 dst_queue_mask)) {
4885 clear_value = 0;
4886 }
4887
4888 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4889 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4890 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4891 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4892 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4893 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4894 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4895 VkImageSubresourceRange local_range = *range;
4896 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4897 local_range.baseMipLevel = 0;
4898 local_range.levelCount = 1;
4899
4900 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4901 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4902
4903 radv_decompress_depth_image_inplace(cmd_buffer, image,
4904 &local_range, sample_locs);
4905
4906 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4907 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4908 }
4909 }
4910
4911 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4912 struct radv_image *image,
4913 const VkImageSubresourceRange *range,
4914 uint32_t value)
4915 {
4916 struct radv_cmd_state *state = &cmd_buffer->state;
4917
4918 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4919 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4920
4921 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
4922
4923 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4924 }
4925
4926 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4927 struct radv_image *image,
4928 const VkImageSubresourceRange *range)
4929 {
4930 struct radv_cmd_state *state = &cmd_buffer->state;
4931 static const uint32_t fmask_clear_values[4] = {
4932 0x00000000,
4933 0x02020202,
4934 0xE4E4E4E4,
4935 0x76543210
4936 };
4937 uint32_t log2_samples = util_logbase2(image->info.samples);
4938 uint32_t value = fmask_clear_values[log2_samples];
4939
4940 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4941 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4942
4943 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
4944
4945 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4946 }
4947
4948 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4949 struct radv_image *image,
4950 const VkImageSubresourceRange *range, uint32_t value)
4951 {
4952 struct radv_cmd_state *state = &cmd_buffer->state;
4953 unsigned size = 0;
4954
4955 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4956 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4957
4958 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
4959
4960 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
4961 /* When DCC is enabled with mipmaps, some levels might not
4962 * support fast clears and we have to initialize them as "fully
4963 * expanded".
4964 */
4965 /* Compute the size of all fast clearable DCC levels. */
4966 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
4967 struct legacy_surf_level *surf_level =
4968 &image->planes[0].surface.u.legacy.level[i];
4969 unsigned dcc_fast_clear_size =
4970 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
4971
4972 if (!dcc_fast_clear_size)
4973 break;
4974
4975 size = surf_level->dcc_offset + dcc_fast_clear_size;
4976 }
4977
4978 /* Initialize the mipmap levels without DCC. */
4979 if (size != image->planes[0].surface.dcc_size) {
4980 state->flush_bits |=
4981 radv_fill_buffer(cmd_buffer, image->bo,
4982 image->offset + image->dcc_offset + size,
4983 image->planes[0].surface.dcc_size - size,
4984 0xffffffff);
4985 }
4986 }
4987
4988 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4989 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4990 }
4991
4992 /**
4993 * Initialize DCC/FMASK/CMASK metadata for a color image.
4994 */
4995 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4996 struct radv_image *image,
4997 VkImageLayout src_layout,
4998 VkImageLayout dst_layout,
4999 unsigned src_queue_mask,
5000 unsigned dst_queue_mask,
5001 const VkImageSubresourceRange *range)
5002 {
5003 if (radv_image_has_cmask(image)) {
5004 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5005
5006 /* TODO: clarify this. */
5007 if (radv_image_has_fmask(image)) {
5008 value = 0xccccccccu;
5009 }
5010
5011 radv_initialise_cmask(cmd_buffer, image, range, value);
5012 }
5013
5014 if (radv_image_has_fmask(image)) {
5015 radv_initialize_fmask(cmd_buffer, image, range);
5016 }
5017
5018 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5019 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5020 bool need_decompress_pass = false;
5021
5022 if (radv_layout_dcc_compressed(image, dst_layout,
5023 dst_queue_mask)) {
5024 value = 0x20202020u;
5025 need_decompress_pass = true;
5026 }
5027
5028 radv_initialize_dcc(cmd_buffer, image, range, value);
5029
5030 radv_update_fce_metadata(cmd_buffer, image, range,
5031 need_decompress_pass);
5032 }
5033
5034 if (radv_image_has_cmask(image) ||
5035 radv_dcc_enabled(image, range->baseMipLevel)) {
5036 uint32_t color_values[2] = {};
5037 radv_set_color_clear_metadata(cmd_buffer, image, range,
5038 color_values);
5039 }
5040 }
5041
5042 /**
5043 * Handle color image transitions for DCC/FMASK/CMASK.
5044 */
5045 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5046 struct radv_image *image,
5047 VkImageLayout src_layout,
5048 VkImageLayout dst_layout,
5049 unsigned src_queue_mask,
5050 unsigned dst_queue_mask,
5051 const VkImageSubresourceRange *range)
5052 {
5053 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5054 radv_init_color_image_metadata(cmd_buffer, image,
5055 src_layout, dst_layout,
5056 src_queue_mask, dst_queue_mask,
5057 range);
5058 return;
5059 }
5060
5061 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5062 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5063 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5064 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
5065 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
5066 radv_decompress_dcc(cmd_buffer, image, range);
5067 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5068 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5069 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5070 }
5071 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5072 bool fce_eliminate = false, fmask_expand = false;
5073
5074 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5075 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5076 fce_eliminate = true;
5077 }
5078
5079 if (radv_image_has_fmask(image)) {
5080 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5081 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5082 /* A FMASK decompress is required before doing
5083 * a MSAA decompress using FMASK.
5084 */
5085 fmask_expand = true;
5086 }
5087 }
5088
5089 if (fce_eliminate || fmask_expand)
5090 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5091
5092 if (fmask_expand)
5093 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5094 }
5095 }
5096
5097 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5098 struct radv_image *image,
5099 VkImageLayout src_layout,
5100 VkImageLayout dst_layout,
5101 uint32_t src_family,
5102 uint32_t dst_family,
5103 const VkImageSubresourceRange *range,
5104 struct radv_sample_locations_state *sample_locs)
5105 {
5106 if (image->exclusive && src_family != dst_family) {
5107 /* This is an acquire or a release operation and there will be
5108 * a corresponding release/acquire. Do the transition in the
5109 * most flexible queue. */
5110
5111 assert(src_family == cmd_buffer->queue_family_index ||
5112 dst_family == cmd_buffer->queue_family_index);
5113
5114 if (src_family == VK_QUEUE_FAMILY_EXTERNAL)
5115 return;
5116
5117 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5118 return;
5119
5120 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5121 (src_family == RADV_QUEUE_GENERAL ||
5122 dst_family == RADV_QUEUE_GENERAL))
5123 return;
5124 }
5125
5126 if (src_layout == dst_layout)
5127 return;
5128
5129 unsigned src_queue_mask =
5130 radv_image_queue_family_mask(image, src_family,
5131 cmd_buffer->queue_family_index);
5132 unsigned dst_queue_mask =
5133 radv_image_queue_family_mask(image, dst_family,
5134 cmd_buffer->queue_family_index);
5135
5136 if (vk_format_is_depth(image->vk_format)) {
5137 radv_handle_depth_image_transition(cmd_buffer, image,
5138 src_layout, dst_layout,
5139 src_queue_mask, dst_queue_mask,
5140 range, sample_locs);
5141 } else {
5142 radv_handle_color_image_transition(cmd_buffer, image,
5143 src_layout, dst_layout,
5144 src_queue_mask, dst_queue_mask,
5145 range);
5146 }
5147 }
5148
5149 struct radv_barrier_info {
5150 uint32_t eventCount;
5151 const VkEvent *pEvents;
5152 VkPipelineStageFlags srcStageMask;
5153 VkPipelineStageFlags dstStageMask;
5154 };
5155
5156 static void
5157 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5158 uint32_t memoryBarrierCount,
5159 const VkMemoryBarrier *pMemoryBarriers,
5160 uint32_t bufferMemoryBarrierCount,
5161 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5162 uint32_t imageMemoryBarrierCount,
5163 const VkImageMemoryBarrier *pImageMemoryBarriers,
5164 const struct radv_barrier_info *info)
5165 {
5166 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5167 enum radv_cmd_flush_bits src_flush_bits = 0;
5168 enum radv_cmd_flush_bits dst_flush_bits = 0;
5169
5170 for (unsigned i = 0; i < info->eventCount; ++i) {
5171 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5172 uint64_t va = radv_buffer_get_va(event->bo);
5173
5174 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5175
5176 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5177
5178 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5179 assert(cmd_buffer->cs->cdw <= cdw_max);
5180 }
5181
5182 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5183 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5184 NULL);
5185 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5186 NULL);
5187 }
5188
5189 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5190 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5191 NULL);
5192 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5193 NULL);
5194 }
5195
5196 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5197 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5198
5199 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5200 image);
5201 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5202 image);
5203 }
5204
5205 /* The Vulkan spec 1.1.98 says:
5206 *
5207 * "An execution dependency with only
5208 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5209 * will only prevent that stage from executing in subsequently
5210 * submitted commands. As this stage does not perform any actual
5211 * execution, this is not observable - in effect, it does not delay
5212 * processing of subsequent commands. Similarly an execution dependency
5213 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5214 * will effectively not wait for any prior commands to complete."
5215 */
5216 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5217 radv_stage_flush(cmd_buffer, info->srcStageMask);
5218 cmd_buffer->state.flush_bits |= src_flush_bits;
5219
5220 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5221 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5222
5223 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5224 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5225 SAMPLE_LOCATIONS_INFO_EXT);
5226 struct radv_sample_locations_state sample_locations = {};
5227
5228 if (sample_locs_info) {
5229 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5230 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5231 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5232 sample_locations.count = sample_locs_info->sampleLocationsCount;
5233 typed_memcpy(&sample_locations.locations[0],
5234 sample_locs_info->pSampleLocations,
5235 sample_locs_info->sampleLocationsCount);
5236 }
5237
5238 radv_handle_image_transition(cmd_buffer, image,
5239 pImageMemoryBarriers[i].oldLayout,
5240 pImageMemoryBarriers[i].newLayout,
5241 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5242 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5243 &pImageMemoryBarriers[i].subresourceRange,
5244 sample_locs_info ? &sample_locations : NULL);
5245 }
5246
5247 /* Make sure CP DMA is idle because the driver might have performed a
5248 * DMA operation for copying or filling buffers/images.
5249 */
5250 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5251 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5252 si_cp_dma_wait_for_idle(cmd_buffer);
5253
5254 cmd_buffer->state.flush_bits |= dst_flush_bits;
5255 }
5256
5257 void radv_CmdPipelineBarrier(
5258 VkCommandBuffer commandBuffer,
5259 VkPipelineStageFlags srcStageMask,
5260 VkPipelineStageFlags destStageMask,
5261 VkBool32 byRegion,
5262 uint32_t memoryBarrierCount,
5263 const VkMemoryBarrier* pMemoryBarriers,
5264 uint32_t bufferMemoryBarrierCount,
5265 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5266 uint32_t imageMemoryBarrierCount,
5267 const VkImageMemoryBarrier* pImageMemoryBarriers)
5268 {
5269 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5270 struct radv_barrier_info info;
5271
5272 info.eventCount = 0;
5273 info.pEvents = NULL;
5274 info.srcStageMask = srcStageMask;
5275 info.dstStageMask = destStageMask;
5276
5277 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5278 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5279 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5280 }
5281
5282
5283 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5284 struct radv_event *event,
5285 VkPipelineStageFlags stageMask,
5286 unsigned value)
5287 {
5288 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5289 uint64_t va = radv_buffer_get_va(event->bo);
5290
5291 si_emit_cache_flush(cmd_buffer);
5292
5293 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5294
5295 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5296
5297 /* Flags that only require a top-of-pipe event. */
5298 VkPipelineStageFlags top_of_pipe_flags =
5299 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5300
5301 /* Flags that only require a post-index-fetch event. */
5302 VkPipelineStageFlags post_index_fetch_flags =
5303 top_of_pipe_flags |
5304 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5305 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5306
5307 /* Make sure CP DMA is idle because the driver might have performed a
5308 * DMA operation for copying or filling buffers/images.
5309 */
5310 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5311 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5312 si_cp_dma_wait_for_idle(cmd_buffer);
5313
5314 /* TODO: Emit EOS events for syncing PS/CS stages. */
5315
5316 if (!(stageMask & ~top_of_pipe_flags)) {
5317 /* Just need to sync the PFP engine. */
5318 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5319 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5320 S_370_WR_CONFIRM(1) |
5321 S_370_ENGINE_SEL(V_370_PFP));
5322 radeon_emit(cs, va);
5323 radeon_emit(cs, va >> 32);
5324 radeon_emit(cs, value);
5325 } else if (!(stageMask & ~post_index_fetch_flags)) {
5326 /* Sync ME because PFP reads index and indirect buffers. */
5327 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5328 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5329 S_370_WR_CONFIRM(1) |
5330 S_370_ENGINE_SEL(V_370_ME));
5331 radeon_emit(cs, va);
5332 radeon_emit(cs, va >> 32);
5333 radeon_emit(cs, value);
5334 } else {
5335 /* Otherwise, sync all prior GPU work using an EOP event. */
5336 si_cs_emit_write_event_eop(cs,
5337 cmd_buffer->device->physical_device->rad_info.chip_class,
5338 radv_cmd_buffer_uses_mec(cmd_buffer),
5339 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5340 EOP_DATA_SEL_VALUE_32BIT, va, value,
5341 cmd_buffer->gfx9_eop_bug_va);
5342 }
5343
5344 assert(cmd_buffer->cs->cdw <= cdw_max);
5345 }
5346
5347 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5348 VkEvent _event,
5349 VkPipelineStageFlags stageMask)
5350 {
5351 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5352 RADV_FROM_HANDLE(radv_event, event, _event);
5353
5354 write_event(cmd_buffer, event, stageMask, 1);
5355 }
5356
5357 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5358 VkEvent _event,
5359 VkPipelineStageFlags stageMask)
5360 {
5361 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5362 RADV_FROM_HANDLE(radv_event, event, _event);
5363
5364 write_event(cmd_buffer, event, stageMask, 0);
5365 }
5366
5367 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5368 uint32_t eventCount,
5369 const VkEvent* pEvents,
5370 VkPipelineStageFlags srcStageMask,
5371 VkPipelineStageFlags dstStageMask,
5372 uint32_t memoryBarrierCount,
5373 const VkMemoryBarrier* pMemoryBarriers,
5374 uint32_t bufferMemoryBarrierCount,
5375 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5376 uint32_t imageMemoryBarrierCount,
5377 const VkImageMemoryBarrier* pImageMemoryBarriers)
5378 {
5379 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5380 struct radv_barrier_info info;
5381
5382 info.eventCount = eventCount;
5383 info.pEvents = pEvents;
5384 info.srcStageMask = 0;
5385
5386 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5387 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5388 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5389 }
5390
5391
5392 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5393 uint32_t deviceMask)
5394 {
5395 /* No-op */
5396 }
5397
5398 /* VK_EXT_conditional_rendering */
5399 void radv_CmdBeginConditionalRenderingEXT(
5400 VkCommandBuffer commandBuffer,
5401 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5402 {
5403 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5404 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5405 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5406 bool draw_visible = true;
5407 uint64_t pred_value = 0;
5408 uint64_t va, new_va;
5409 unsigned pred_offset;
5410
5411 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5412
5413 /* By default, if the 32-bit value at offset in buffer memory is zero,
5414 * then the rendering commands are discarded, otherwise they are
5415 * executed as normal. If the inverted flag is set, all commands are
5416 * discarded if the value is non zero.
5417 */
5418 if (pConditionalRenderingBegin->flags &
5419 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5420 draw_visible = false;
5421 }
5422
5423 si_emit_cache_flush(cmd_buffer);
5424
5425 /* From the Vulkan spec 1.1.107:
5426 *
5427 * "If the 32-bit value at offset in buffer memory is zero, then the
5428 * rendering commands are discarded, otherwise they are executed as
5429 * normal. If the value of the predicate in buffer memory changes while
5430 * conditional rendering is active, the rendering commands may be
5431 * discarded in an implementation-dependent way. Some implementations
5432 * may latch the value of the predicate upon beginning conditional
5433 * rendering while others may read it before every rendering command."
5434 *
5435 * But, the AMD hardware treats the predicate as a 64-bit value which
5436 * means we need a workaround in the driver. Luckily, it's not required
5437 * to support if the value changes when predication is active.
5438 *
5439 * The workaround is as follows:
5440 * 1) allocate a 64-value in the upload BO and initialize it to 0
5441 * 2) copy the 32-bit predicate value to the upload BO
5442 * 3) use the new allocated VA address for predication
5443 *
5444 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5445 * in ME (+ sync PFP) instead of PFP.
5446 */
5447 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5448
5449 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5450
5451 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5452 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5453 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5454 COPY_DATA_WR_CONFIRM);
5455 radeon_emit(cs, va);
5456 radeon_emit(cs, va >> 32);
5457 radeon_emit(cs, new_va);
5458 radeon_emit(cs, new_va >> 32);
5459
5460 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5461 radeon_emit(cs, 0);
5462
5463 /* Enable predication for this command buffer. */
5464 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5465 cmd_buffer->state.predicating = true;
5466
5467 /* Store conditional rendering user info. */
5468 cmd_buffer->state.predication_type = draw_visible;
5469 cmd_buffer->state.predication_va = new_va;
5470 }
5471
5472 void radv_CmdEndConditionalRenderingEXT(
5473 VkCommandBuffer commandBuffer)
5474 {
5475 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5476
5477 /* Disable predication for this command buffer. */
5478 si_emit_set_predication_state(cmd_buffer, false, 0);
5479 cmd_buffer->state.predicating = false;
5480
5481 /* Reset conditional rendering user info. */
5482 cmd_buffer->state.predication_type = -1;
5483 cmd_buffer->state.predication_va = 0;
5484 }
5485
5486 /* VK_EXT_transform_feedback */
5487 void radv_CmdBindTransformFeedbackBuffersEXT(
5488 VkCommandBuffer commandBuffer,
5489 uint32_t firstBinding,
5490 uint32_t bindingCount,
5491 const VkBuffer* pBuffers,
5492 const VkDeviceSize* pOffsets,
5493 const VkDeviceSize* pSizes)
5494 {
5495 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5496 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5497 uint8_t enabled_mask = 0;
5498
5499 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5500 for (uint32_t i = 0; i < bindingCount; i++) {
5501 uint32_t idx = firstBinding + i;
5502
5503 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5504 sb[idx].offset = pOffsets[i];
5505 sb[idx].size = pSizes[i];
5506
5507 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5508 sb[idx].buffer->bo);
5509
5510 enabled_mask |= 1 << idx;
5511 }
5512
5513 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5514
5515 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5516 }
5517
5518 static void
5519 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5520 {
5521 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5522 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5523
5524 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5525 radeon_emit(cs,
5526 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5527 S_028B94_RAST_STREAM(0) |
5528 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5529 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5530 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5531 radeon_emit(cs, so->hw_enabled_mask &
5532 so->enabled_stream_buffers_mask);
5533
5534 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5535 }
5536
5537 static void
5538 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5539 {
5540 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5541 bool old_streamout_enabled = so->streamout_enabled;
5542 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5543
5544 so->streamout_enabled = enable;
5545
5546 so->hw_enabled_mask = so->enabled_mask |
5547 (so->enabled_mask << 4) |
5548 (so->enabled_mask << 8) |
5549 (so->enabled_mask << 12);
5550
5551 if ((old_streamout_enabled != so->streamout_enabled) ||
5552 (old_hw_enabled_mask != so->hw_enabled_mask))
5553 radv_emit_streamout_enable(cmd_buffer);
5554 }
5555
5556 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5557 {
5558 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5559 unsigned reg_strmout_cntl;
5560
5561 /* The register is at different places on different ASICs. */
5562 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5563 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5564 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5565 } else {
5566 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5567 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5568 }
5569
5570 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5571 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5572
5573 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5574 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5575 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5576 radeon_emit(cs, 0);
5577 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5578 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5579 radeon_emit(cs, 4); /* poll interval */
5580 }
5581
5582 void radv_CmdBeginTransformFeedbackEXT(
5583 VkCommandBuffer commandBuffer,
5584 uint32_t firstCounterBuffer,
5585 uint32_t counterBufferCount,
5586 const VkBuffer* pCounterBuffers,
5587 const VkDeviceSize* pCounterBufferOffsets)
5588 {
5589 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5590 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5591 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5592 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5593 uint32_t i;
5594
5595 radv_flush_vgt_streamout(cmd_buffer);
5596
5597 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5598 for_each_bit(i, so->enabled_mask) {
5599 int32_t counter_buffer_idx = i - firstCounterBuffer;
5600 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5601 counter_buffer_idx = -1;
5602
5603 /* AMD GCN binds streamout buffers as shader resources.
5604 * VGT only counts primitives and tells the shader through
5605 * SGPRs what to do.
5606 */
5607 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5608 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5609 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5610
5611 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5612
5613 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5614 /* The array of counter buffers is optional. */
5615 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5616 uint64_t va = radv_buffer_get_va(buffer->bo);
5617
5618 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5619
5620 /* Append */
5621 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5622 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5623 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5624 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5625 radeon_emit(cs, 0); /* unused */
5626 radeon_emit(cs, 0); /* unused */
5627 radeon_emit(cs, va); /* src address lo */
5628 radeon_emit(cs, va >> 32); /* src address hi */
5629
5630 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5631 } else {
5632 /* Start from the beginning. */
5633 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5634 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5635 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5636 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5637 radeon_emit(cs, 0); /* unused */
5638 radeon_emit(cs, 0); /* unused */
5639 radeon_emit(cs, 0); /* unused */
5640 radeon_emit(cs, 0); /* unused */
5641 }
5642 }
5643
5644 radv_set_streamout_enable(cmd_buffer, true);
5645 }
5646
5647 void radv_CmdEndTransformFeedbackEXT(
5648 VkCommandBuffer commandBuffer,
5649 uint32_t firstCounterBuffer,
5650 uint32_t counterBufferCount,
5651 const VkBuffer* pCounterBuffers,
5652 const VkDeviceSize* pCounterBufferOffsets)
5653 {
5654 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5655 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5656 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5657 uint32_t i;
5658
5659 radv_flush_vgt_streamout(cmd_buffer);
5660
5661 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5662 for_each_bit(i, so->enabled_mask) {
5663 int32_t counter_buffer_idx = i - firstCounterBuffer;
5664 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5665 counter_buffer_idx = -1;
5666
5667 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5668 /* The array of counters buffer is optional. */
5669 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5670 uint64_t va = radv_buffer_get_va(buffer->bo);
5671
5672 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5673
5674 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5675 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5676 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5677 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5678 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5679 radeon_emit(cs, va); /* dst address lo */
5680 radeon_emit(cs, va >> 32); /* dst address hi */
5681 radeon_emit(cs, 0); /* unused */
5682 radeon_emit(cs, 0); /* unused */
5683
5684 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5685 }
5686
5687 /* Deactivate transform feedback by zeroing the buffer size.
5688 * The counters (primitives generated, primitives emitted) may
5689 * be enabled even if there is not buffer bound. This ensures
5690 * that the primitives-emitted query won't increment.
5691 */
5692 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5693
5694 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5695 }
5696
5697 radv_set_streamout_enable(cmd_buffer, false);
5698 }
5699
5700 void radv_CmdDrawIndirectByteCountEXT(
5701 VkCommandBuffer commandBuffer,
5702 uint32_t instanceCount,
5703 uint32_t firstInstance,
5704 VkBuffer _counterBuffer,
5705 VkDeviceSize counterBufferOffset,
5706 uint32_t counterOffset,
5707 uint32_t vertexStride)
5708 {
5709 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5710 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5711 struct radv_draw_info info = {};
5712
5713 info.instance_count = instanceCount;
5714 info.first_instance = firstInstance;
5715 info.strmout_buffer = counterBuffer;
5716 info.strmout_buffer_offset = counterBufferOffset;
5717 info.stride = vertexStride;
5718
5719 radv_draw(cmd_buffer, &info);
5720 }
5721
5722 /* VK_AMD_buffer_marker */
5723 void radv_CmdWriteBufferMarkerAMD(
5724 VkCommandBuffer commandBuffer,
5725 VkPipelineStageFlagBits pipelineStage,
5726 VkBuffer dstBuffer,
5727 VkDeviceSize dstOffset,
5728 uint32_t marker)
5729 {
5730 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5731 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
5732 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5733 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
5734
5735 si_emit_cache_flush(cmd_buffer);
5736
5737 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
5738 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5739 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
5740 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5741 COPY_DATA_WR_CONFIRM);
5742 radeon_emit(cs, marker);
5743 radeon_emit(cs, 0);
5744 radeon_emit(cs, va);
5745 radeon_emit(cs, va >> 32);
5746 } else {
5747 si_cs_emit_write_event_eop(cs,
5748 cmd_buffer->device->physical_device->rad_info.chip_class,
5749 radv_cmd_buffer_uses_mec(cmd_buffer),
5750 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5751 EOP_DATA_SEL_VALUE_32BIT,
5752 va, marker,
5753 cmd_buffer->gfx9_eop_bug_va);
5754 }
5755 }