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[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 int src_family,
42 int dst_family,
43 VkImageSubresourceRange range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static bool
191 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
192 uint64_t min_needed)
193 {
194 uint64_t new_size;
195 struct radeon_winsys_bo *bo;
196 struct radv_cmd_buffer_upload *upload;
197 struct radv_device *device = cmd_buffer->device;
198
199 new_size = MAX2(min_needed, 16 * 1024);
200 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
201
202 bo = device->ws->buffer_create(device->ws,
203 new_size, 4096,
204 RADEON_DOMAIN_GTT,
205 RADEON_FLAG_CPU_ACCESS);
206
207 if (!bo) {
208 cmd_buffer->record_fail = true;
209 return false;
210 }
211
212 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
213 if (cmd_buffer->upload.upload_bo) {
214 upload = malloc(sizeof(*upload));
215
216 if (!upload) {
217 cmd_buffer->record_fail = true;
218 device->ws->buffer_destroy(bo);
219 return false;
220 }
221
222 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
223 list_add(&upload->list, &cmd_buffer->upload.list);
224 }
225
226 cmd_buffer->upload.upload_bo = bo;
227 cmd_buffer->upload.size = new_size;
228 cmd_buffer->upload.offset = 0;
229 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
230
231 if (!cmd_buffer->upload.map) {
232 cmd_buffer->record_fail = true;
233 return false;
234 }
235
236 return true;
237 }
238
239 bool
240 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
241 unsigned size,
242 unsigned alignment,
243 unsigned *out_offset,
244 void **ptr)
245 {
246 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
247 if (offset + size > cmd_buffer->upload.size) {
248 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
249 return false;
250 offset = 0;
251 }
252
253 *out_offset = offset;
254 *ptr = cmd_buffer->upload.map + offset;
255
256 cmd_buffer->upload.offset = offset + size;
257 return true;
258 }
259
260 bool
261 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
262 unsigned size, unsigned alignment,
263 const void *data, unsigned *out_offset)
264 {
265 uint8_t *ptr;
266
267 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
268 out_offset, (void **)&ptr))
269 return false;
270
271 if (ptr)
272 memcpy(ptr, data, size);
273
274 return true;
275 }
276
277 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
278 {
279 struct radv_device *device = cmd_buffer->device;
280 struct radeon_winsys_cs *cs = cmd_buffer->cs;
281 uint64_t va;
282
283 if (!device->trace_bo)
284 return;
285
286 va = device->ws->buffer_get_va(device->trace_bo);
287
288 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
289
290 ++cmd_buffer->state.trace_id;
291 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
292 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
293 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
294 S_370_WR_CONFIRM(1) |
295 S_370_ENGINE_SEL(V_370_ME));
296 radeon_emit(cs, va);
297 radeon_emit(cs, va >> 32);
298 radeon_emit(cs, cmd_buffer->state.trace_id);
299 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
300 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
301 }
302
303 static void
304 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
305 struct radv_pipeline *pipeline)
306 {
307 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
308 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
309 8);
310 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
311 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
312 }
313
314 static void
315 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
316 struct radv_pipeline *pipeline)
317 {
318 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
319 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
320 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
321
322 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
323 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
324 }
325
326 /* 12.4 fixed-point */
327 static unsigned radv_pack_float_12p4(float x)
328 {
329 return x <= 0 ? 0 :
330 x >= 4096 ? 0xffff : x * 16;
331 }
332
333 static uint32_t
334 shader_stage_to_user_data_0(gl_shader_stage stage)
335 {
336 switch (stage) {
337 case MESA_SHADER_FRAGMENT:
338 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
339 case MESA_SHADER_VERTEX:
340 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
341 case MESA_SHADER_COMPUTE:
342 return R_00B900_COMPUTE_USER_DATA_0;
343 default:
344 unreachable("unknown shader");
345 }
346 }
347
348 static struct ac_userdata_info *
349 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
350 gl_shader_stage stage,
351 int idx)
352 {
353 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
354 }
355
356 static void
357 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
358 struct radv_pipeline *pipeline,
359 gl_shader_stage stage,
360 int idx, uint64_t va)
361 {
362 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
363 uint32_t base_reg = shader_stage_to_user_data_0(stage);
364 if (loc->sgpr_idx == -1)
365 return;
366 assert(loc->num_sgprs == 2);
367 assert(!loc->indirect);
368 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
369 radeon_emit(cmd_buffer->cs, va);
370 radeon_emit(cmd_buffer->cs, va >> 32);
371 }
372
373 static void
374 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
375 struct radv_pipeline *pipeline)
376 {
377 int num_samples = pipeline->graphics.ms.num_samples;
378 struct radv_multisample_state *ms = &pipeline->graphics.ms;
379 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
380
381 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
382 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
383 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
384
385 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
386 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
387
388 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
389 return;
390
391 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
392 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
393 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
394
395 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
396
397 uint32_t samples_offset;
398 void *samples_ptr;
399 void *src;
400 radv_cmd_buffer_upload_alloc(cmd_buffer, num_samples * 4 * 2, 256, &samples_offset,
401 &samples_ptr);
402 switch (num_samples) {
403 case 1:
404 src = cmd_buffer->device->sample_locations_1x;
405 break;
406 case 2:
407 src = cmd_buffer->device->sample_locations_2x;
408 break;
409 case 4:
410 src = cmd_buffer->device->sample_locations_4x;
411 break;
412 case 8:
413 src = cmd_buffer->device->sample_locations_8x;
414 break;
415 case 16:
416 src = cmd_buffer->device->sample_locations_16x;
417 break;
418 }
419 memcpy(samples_ptr, src, num_samples * 4 * 2);
420
421 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
422 va += samples_offset;
423
424 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
425 AC_UD_PS_SAMPLE_POS, va);
426 }
427
428 static void
429 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
430 struct radv_pipeline *pipeline)
431 {
432 struct radv_raster_state *raster = &pipeline->graphics.raster;
433
434 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
435 raster->pa_cl_clip_cntl);
436
437 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
438 raster->spi_interp_control);
439
440 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
441 unsigned tmp = (unsigned)(1.0 * 8.0);
442 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
443 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
444 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
445
446 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
447 raster->pa_su_vtx_cntl);
448
449 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
450 raster->pa_su_sc_mode_cntl);
451 }
452
453 static void
454 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
455 struct radv_pipeline *pipeline)
456 {
457 struct radeon_winsys *ws = cmd_buffer->device->ws;
458 struct radv_shader_variant *vs;
459 uint64_t va;
460 unsigned export_count;
461 unsigned clip_dist_mask, cull_dist_mask, total_mask;
462
463 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
464
465 vs = pipeline->shaders[MESA_SHADER_VERTEX];
466 va = ws->buffer_get_va(vs->bo);
467 ws->cs_add_buffer(cmd_buffer->cs, vs->bo, 8);
468
469 clip_dist_mask = vs->info.vs.clip_dist_mask;
470 cull_dist_mask = vs->info.vs.cull_dist_mask;
471 total_mask = clip_dist_mask | cull_dist_mask;
472 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, 0);
473 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
474
475 export_count = MAX2(1, vs->info.vs.param_exports);
476 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
477 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
478 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
479 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
480 S_02870C_POS1_EXPORT_FORMAT(vs->info.vs.pos_exports > 1 ?
481 V_02870C_SPI_SHADER_4COMP :
482 V_02870C_SPI_SHADER_NONE) |
483 S_02870C_POS2_EXPORT_FORMAT(vs->info.vs.pos_exports > 2 ?
484 V_02870C_SPI_SHADER_4COMP :
485 V_02870C_SPI_SHADER_NONE) |
486 S_02870C_POS3_EXPORT_FORMAT(vs->info.vs.pos_exports > 3 ?
487 V_02870C_SPI_SHADER_4COMP :
488 V_02870C_SPI_SHADER_NONE));
489
490 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
491 radeon_emit(cmd_buffer->cs, va >> 8);
492 radeon_emit(cmd_buffer->cs, va >> 40);
493 radeon_emit(cmd_buffer->cs, vs->rsrc1);
494 radeon_emit(cmd_buffer->cs, vs->rsrc2);
495
496 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
497 S_028818_VTX_W0_FMT(1) |
498 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
499 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
500 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
501
502 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
503 S_02881C_USE_VTX_POINT_SIZE(vs->info.vs.writes_pointsize) |
504 S_02881C_USE_VTX_RENDER_TARGET_INDX(vs->info.vs.writes_layer) |
505 S_02881C_USE_VTX_VIEWPORT_INDX(vs->info.vs.writes_viewport_index) |
506 S_02881C_VS_OUT_MISC_VEC_ENA(vs->info.vs.writes_pointsize ||
507 vs->info.vs.writes_layer ||
508 vs->info.vs.writes_viewport_index) |
509 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
510 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
511 pipeline->graphics.raster.pa_cl_vs_out_cntl |
512 cull_dist_mask << 8 |
513 clip_dist_mask);
514
515 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
516 S_028AB4_REUSE_OFF(vs->info.vs.writes_viewport_index));
517 }
518
519
520
521 static void
522 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
523 struct radv_pipeline *pipeline)
524 {
525 struct radeon_winsys *ws = cmd_buffer->device->ws;
526 struct radv_shader_variant *ps, *vs;
527 uint64_t va;
528 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
529 struct radv_blend_state *blend = &pipeline->graphics.blend;
530 unsigned ps_offset = 0;
531 unsigned z_order;
532 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
533
534 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
535 vs = pipeline->shaders[MESA_SHADER_VERTEX];
536 va = ws->buffer_get_va(ps->bo);
537 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
538
539 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
540 radeon_emit(cmd_buffer->cs, va >> 8);
541 radeon_emit(cmd_buffer->cs, va >> 40);
542 radeon_emit(cmd_buffer->cs, ps->rsrc1);
543 radeon_emit(cmd_buffer->cs, ps->rsrc2);
544
545 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
546 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
547 else
548 z_order = V_02880C_LATE_Z;
549
550
551 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
552 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
553 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
554 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
555 S_02880C_Z_ORDER(z_order) |
556 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
557 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
558 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory));
559
560 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
561 ps->config.spi_ps_input_ena);
562
563 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
564 ps->config.spi_ps_input_addr);
565
566 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(0);
567 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
568 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
569
570 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
571
572 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
573 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
574 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
575 V_028710_SPI_SHADER_ZERO);
576
577 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
578
579 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
580 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
581
582 if (ps->info.fs.has_pcoord) {
583 unsigned val;
584 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
585 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
586 ps_offset = 1;
587 }
588
589 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
590 unsigned vs_offset, flat_shade;
591 unsigned val;
592
593 if (!(ps->info.fs.input_mask & (1u << i)))
594 continue;
595
596
597 if (!(vs->info.vs.export_mask & (1u << i))) {
598 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset,
599 S_028644_OFFSET(0x20));
600 ++ps_offset;
601 continue;
602 }
603
604 vs_offset = util_bitcount(vs->info.vs.export_mask & ((1u << i) - 1));
605 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
606
607 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
608 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
609 ++ps_offset;
610 }
611 }
612
613 static void
614 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
615 struct radv_pipeline *pipeline)
616 {
617 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
618 return;
619
620 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
621 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
622 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
623 radv_update_multisample_state(cmd_buffer, pipeline);
624 radv_emit_vertex_shader(cmd_buffer, pipeline);
625 radv_emit_fragment_shader(cmd_buffer, pipeline);
626
627 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
628 pipeline->graphics.prim_restart_enable);
629
630 cmd_buffer->scratch_size_needed =
631 MAX2(cmd_buffer->scratch_size_needed,
632 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
633
634 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
635 S_0286E8_WAVES(pipeline->max_waves) |
636 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
637 cmd_buffer->state.emitted_pipeline = pipeline;
638 }
639
640 static void
641 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
642 {
643 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
644 cmd_buffer->state.dynamic.viewport.viewports);
645 }
646
647 static void
648 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
649 {
650 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
651 si_write_scissors(cmd_buffer->cs, 0, count,
652 cmd_buffer->state.dynamic.scissor.scissors);
653 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
654 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
655 }
656
657 static void
658 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
659 int index,
660 struct radv_color_buffer_info *cb)
661 {
662 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
663 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
664 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
665 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
666 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
667 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
668 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
669 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
670 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
671 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
672 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
673 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
674 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
675
676 if (is_vi) { /* DCC BASE */
677 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
678 }
679 }
680
681 static void
682 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
683 struct radv_ds_buffer_info *ds,
684 struct radv_image *image,
685 VkImageLayout layout)
686 {
687 uint32_t db_z_info = ds->db_z_info;
688
689 if (!radv_layout_has_htile(image, layout))
690 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
691
692 if (!radv_layout_can_expclear(image, layout))
693 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
694
695 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
696 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
697
698 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
699 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
700 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
701 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
702 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
703 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
704 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
705 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
706 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
707 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
708
709 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
710 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
711 ds->pa_su_poly_offset_db_fmt_cntl);
712 }
713
714 /*
715 * To hw resolve multisample images both src and dst need to have the same
716 * micro tiling mode. However we don't always know in advance when creating
717 * the images. This function gets called if we have a resolve attachment,
718 * and tests if the attachment image has the same tiling mode, then it
719 * checks if the generated framebuffer data has the same tiling mode, and
720 * updates it if not.
721 */
722 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
723 struct radv_attachment_info *att,
724 uint32_t micro_tile_mode)
725 {
726 struct radv_image *image = att->attachment->image;
727 uint32_t tile_mode_index;
728 if (image->surface.nsamples <= 1)
729 return;
730
731 if (image->surface.micro_tile_mode != micro_tile_mode) {
732 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
733 }
734
735 if (att->cb.micro_tile_mode != micro_tile_mode) {
736 tile_mode_index = image->surface.tiling_index[0];
737
738 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
739 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
740 att->cb.micro_tile_mode = micro_tile_mode;
741 }
742 }
743
744 void
745 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
746 struct radv_image *image,
747 VkClearDepthStencilValue ds_clear_value,
748 VkImageAspectFlags aspects)
749 {
750 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
751 va += image->offset + image->clear_value_offset;
752 unsigned reg_offset = 0, reg_count = 0;
753
754 if (!image->htile.size || !aspects)
755 return;
756
757 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
758 ++reg_count;
759 } else {
760 ++reg_offset;
761 va += 4;
762 }
763 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
764 ++reg_count;
765
766 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
767
768 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
769 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
770 S_370_WR_CONFIRM(1) |
771 S_370_ENGINE_SEL(V_370_PFP));
772 radeon_emit(cmd_buffer->cs, va);
773 radeon_emit(cmd_buffer->cs, va >> 32);
774 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
775 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
776 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
777 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
778
779 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
780 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
781 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
782 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
783 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
784 }
785
786 static void
787 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
788 struct radv_image *image)
789 {
790 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
791 va += image->offset + image->clear_value_offset;
792
793 if (!image->htile.size)
794 return;
795
796 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
797
798 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
799 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
800 COPY_DATA_DST_SEL(COPY_DATA_REG) |
801 COPY_DATA_COUNT_SEL);
802 radeon_emit(cmd_buffer->cs, va);
803 radeon_emit(cmd_buffer->cs, va >> 32);
804 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
805 radeon_emit(cmd_buffer->cs, 0);
806
807 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
808 radeon_emit(cmd_buffer->cs, 0);
809 }
810
811 void
812 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
813 struct radv_image *image,
814 int idx,
815 uint32_t color_values[2])
816 {
817 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
818 va += image->offset + image->clear_value_offset;
819
820 if (!image->cmask.size && !image->surface.dcc_size)
821 return;
822
823 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
824
825 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
826 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
827 S_370_WR_CONFIRM(1) |
828 S_370_ENGINE_SEL(V_370_PFP));
829 radeon_emit(cmd_buffer->cs, va);
830 radeon_emit(cmd_buffer->cs, va >> 32);
831 radeon_emit(cmd_buffer->cs, color_values[0]);
832 radeon_emit(cmd_buffer->cs, color_values[1]);
833
834 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
835 radeon_emit(cmd_buffer->cs, color_values[0]);
836 radeon_emit(cmd_buffer->cs, color_values[1]);
837 }
838
839 static void
840 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
841 struct radv_image *image,
842 int idx)
843 {
844 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
845 va += image->offset + image->clear_value_offset;
846
847 if (!image->cmask.size && !image->surface.dcc_size)
848 return;
849
850 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
851 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
852
853 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
854 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
855 COPY_DATA_DST_SEL(COPY_DATA_REG) |
856 COPY_DATA_COUNT_SEL);
857 radeon_emit(cmd_buffer->cs, va);
858 radeon_emit(cmd_buffer->cs, va >> 32);
859 radeon_emit(cmd_buffer->cs, reg >> 2);
860 radeon_emit(cmd_buffer->cs, 0);
861
862 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
863 radeon_emit(cmd_buffer->cs, 0);
864 }
865
866 void
867 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
868 {
869 int i;
870 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
871 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
872 int dst_resolve_micro_tile_mode = -1;
873
874 if (subpass->has_resolve) {
875 uint32_t a = subpass->resolve_attachments[0].attachment;
876 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
877 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
878 }
879 for (i = 0; i < subpass->color_count; ++i) {
880 int idx = subpass->color_attachments[i].attachment;
881 struct radv_attachment_info *att = &framebuffer->attachments[idx];
882
883 if (dst_resolve_micro_tile_mode != -1) {
884 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
885 att, dst_resolve_micro_tile_mode);
886 }
887 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
888
889 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
890 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
891
892 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
893 }
894
895 for (i = subpass->color_count; i < 8; i++)
896 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
897 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
898
899 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
900 int idx = subpass->depth_stencil_attachment.attachment;
901 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
902 struct radv_attachment_info *att = &framebuffer->attachments[idx];
903 struct radv_image *image = att->attachment->image;
904 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
905
906 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
907
908 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
909 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
910 cmd_buffer->state.offset_scale = att->ds.offset_scale;
911 }
912 radv_load_depth_clear_regs(cmd_buffer, image);
913 } else {
914 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
915 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
916 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
917 }
918 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
919 S_028208_BR_X(framebuffer->width) |
920 S_028208_BR_Y(framebuffer->height));
921 }
922
923 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
924 {
925 uint32_t db_count_control;
926
927 if(!cmd_buffer->state.active_occlusion_queries) {
928 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
929 db_count_control = 0;
930 } else {
931 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
932 }
933 } else {
934 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
935 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
936 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
937 S_028004_ZPASS_ENABLE(1) |
938 S_028004_SLICE_EVEN_ENABLE(1) |
939 S_028004_SLICE_ODD_ENABLE(1);
940 } else {
941 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
942 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
943 }
944 }
945
946 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
947 }
948
949 static void
950 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
951 {
952 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
953
954 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
955 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
956 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
957 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
958 }
959
960 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
961 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
962 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
963 }
964
965 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
966 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
967 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
968 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
969 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
970 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
971 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
972 S_028430_STENCILOPVAL(1));
973 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
974 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
975 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
976 S_028434_STENCILOPVAL_BF(1));
977 }
978
979 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
980 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
981 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
982 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
983 }
984
985 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
986 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
987 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
988 unsigned slope = fui(d->depth_bias.slope * 16.0f);
989 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
990
991 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
992 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
993 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
994 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
995 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
996 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
997 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
998 }
999 }
1000
1001 cmd_buffer->state.dirty = 0;
1002 }
1003
1004 static void
1005 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1006 struct radv_pipeline *pipeline,
1007 int idx,
1008 uint64_t va,
1009 gl_shader_stage stage)
1010 {
1011 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1012 uint32_t base_reg = shader_stage_to_user_data_0(stage);
1013
1014 if (desc_set_loc->sgpr_idx == -1)
1015 return;
1016
1017 assert(!desc_set_loc->indirect);
1018 assert(desc_set_loc->num_sgprs == 2);
1019 radeon_set_sh_reg_seq(cmd_buffer->cs,
1020 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1021 radeon_emit(cmd_buffer->cs, va);
1022 radeon_emit(cmd_buffer->cs, va >> 32);
1023 }
1024
1025 static void
1026 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1027 struct radv_pipeline *pipeline,
1028 VkShaderStageFlags stages,
1029 struct radv_descriptor_set *set,
1030 unsigned idx)
1031 {
1032 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1033 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1034 idx, set->va,
1035 MESA_SHADER_FRAGMENT);
1036
1037 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1038 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1039 idx, set->va,
1040 MESA_SHADER_VERTEX);
1041
1042 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1043 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1044 idx, set->va,
1045 MESA_SHADER_COMPUTE);
1046 }
1047
1048 static void
1049 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1050 struct radv_pipeline *pipeline,
1051 VkShaderStageFlags stages)
1052 {
1053 unsigned i;
1054 if (!cmd_buffer->state.descriptors_dirty)
1055 return;
1056
1057 for (i = 0; i < MAX_SETS; i++) {
1058 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1059 continue;
1060 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1061 if (!set)
1062 continue;
1063
1064 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1065 }
1066 cmd_buffer->state.descriptors_dirty = 0;
1067 }
1068
1069 static void
1070 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1071 struct radv_pipeline *pipeline,
1072 VkShaderStageFlags stages)
1073 {
1074 struct radv_pipeline_layout *layout = pipeline->layout;
1075 unsigned offset;
1076 void *ptr;
1077 uint64_t va;
1078
1079 stages &= cmd_buffer->push_constant_stages;
1080 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1081 return;
1082
1083 radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1084 16 * layout->dynamic_offset_count,
1085 256, &offset, &ptr);
1086
1087 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1088 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1089 16 * layout->dynamic_offset_count);
1090
1091 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1092 va += offset;
1093
1094 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1095 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1096 AC_UD_PUSH_CONSTANTS, va);
1097
1098 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1099 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1100 AC_UD_PUSH_CONSTANTS, va);
1101
1102 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1103 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1104 AC_UD_PUSH_CONSTANTS, va);
1105
1106 cmd_buffer->push_constant_stages &= ~stages;
1107 }
1108
1109 static void
1110 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer)
1111 {
1112 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1113 struct radv_device *device = cmd_buffer->device;
1114 uint32_t ia_multi_vgt_param;
1115 uint32_t ls_hs_config = 0;
1116
1117 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1118 cmd_buffer->cs, 4096);
1119
1120 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1121 cmd_buffer->state.pipeline->num_vertex_attribs) {
1122 unsigned vb_offset;
1123 void *vb_ptr;
1124 uint32_t i = 0;
1125 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1126 uint64_t va;
1127
1128 /* allocate some descriptor state for vertex buffers */
1129 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1130 &vb_offset, &vb_ptr);
1131
1132 for (i = 0; i < num_attribs; i++) {
1133 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1134 uint32_t offset;
1135 int vb = cmd_buffer->state.pipeline->va_binding[i];
1136 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1137 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1138
1139 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1140 va = device->ws->buffer_get_va(buffer->bo);
1141
1142 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1143 va += offset + buffer->offset;
1144 desc[0] = va;
1145 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1146 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1147 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1148 else
1149 desc[2] = buffer->size - offset;
1150 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1151 }
1152
1153 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1154 va += vb_offset;
1155
1156 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1157 AC_UD_VS_VERTEX_BUFFERS, va);
1158 }
1159
1160 cmd_buffer->state.vertex_descriptors_dirty = false;
1161 cmd_buffer->state.vb_dirty = 0;
1162 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1163 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1164
1165 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1166 radv_emit_framebuffer_state(cmd_buffer);
1167
1168 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1169 radv_emit_viewport(cmd_buffer);
1170
1171 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR))
1172 radv_emit_scissor(cmd_buffer);
1173
1174 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1175 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, 0);
1176 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer);
1177
1178 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1179 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1180 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
1181 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1182 } else {
1183 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1184 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1185 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
1186 }
1187 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1188 }
1189
1190 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1191
1192 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1193 VK_SHADER_STAGE_ALL_GRAPHICS);
1194 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1195 VK_SHADER_STAGE_ALL_GRAPHICS);
1196
1197 assert(cmd_buffer->cs->cdw <= cdw_max);
1198
1199 si_emit_cache_flush(cmd_buffer);
1200 }
1201
1202 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1203 VkPipelineStageFlags src_stage_mask)
1204 {
1205 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1206 VK_PIPELINE_STAGE_TRANSFER_BIT |
1207 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1208 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1209 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1210 }
1211
1212 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1213 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1214 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1215 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1216 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1217 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1218 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1219 VK_PIPELINE_STAGE_TRANSFER_BIT |
1220 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1221 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1222 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1223 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1224 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1225 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1226 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1227 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1228 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1229 }
1230 }
1231
1232 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1233 {
1234 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1235
1236 /* TODO: actual cache flushes */
1237 }
1238
1239 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1240 VkAttachmentReference att)
1241 {
1242 unsigned idx = att.attachment;
1243 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1244 VkImageSubresourceRange range;
1245 range.aspectMask = 0;
1246 range.baseMipLevel = view->base_mip;
1247 range.levelCount = 1;
1248 range.baseArrayLayer = view->base_layer;
1249 range.layerCount = cmd_buffer->state.framebuffer->layers;
1250
1251 radv_handle_image_transition(cmd_buffer,
1252 view->image,
1253 cmd_buffer->state.attachments[idx].current_layout,
1254 att.layout, 0, 0, range,
1255 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1256
1257 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1258
1259
1260 }
1261
1262 void
1263 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1264 const struct radv_subpass *subpass, bool transitions)
1265 {
1266 if (transitions) {
1267 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1268
1269 for (unsigned i = 0; i < subpass->color_count; ++i) {
1270 radv_handle_subpass_image_transition(cmd_buffer,
1271 subpass->color_attachments[i]);
1272 }
1273
1274 for (unsigned i = 0; i < subpass->input_count; ++i) {
1275 radv_handle_subpass_image_transition(cmd_buffer,
1276 subpass->input_attachments[i]);
1277 }
1278
1279 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1280 radv_handle_subpass_image_transition(cmd_buffer,
1281 subpass->depth_stencil_attachment);
1282 }
1283 }
1284
1285 cmd_buffer->state.subpass = subpass;
1286
1287 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1288 }
1289
1290 static void
1291 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1292 struct radv_render_pass *pass,
1293 const VkRenderPassBeginInfo *info)
1294 {
1295 struct radv_cmd_state *state = &cmd_buffer->state;
1296
1297 if (pass->attachment_count == 0) {
1298 state->attachments = NULL;
1299 return;
1300 }
1301
1302 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1303 pass->attachment_count *
1304 sizeof(state->attachments[0]),
1305 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1306 if (state->attachments == NULL) {
1307 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1308 abort();
1309 }
1310
1311 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1312 struct radv_render_pass_attachment *att = &pass->attachments[i];
1313 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1314 VkImageAspectFlags clear_aspects = 0;
1315
1316 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1317 /* color attachment */
1318 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1319 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1320 }
1321 } else {
1322 /* depthstencil attachment */
1323 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1324 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1325 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1326 }
1327 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1328 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1329 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1330 }
1331 }
1332
1333 state->attachments[i].pending_clear_aspects = clear_aspects;
1334 if (clear_aspects && info) {
1335 assert(info->clearValueCount > i);
1336 state->attachments[i].clear_value = info->pClearValues[i];
1337 }
1338
1339 state->attachments[i].current_layout = att->initial_layout;
1340 }
1341 }
1342
1343 VkResult radv_AllocateCommandBuffers(
1344 VkDevice _device,
1345 const VkCommandBufferAllocateInfo *pAllocateInfo,
1346 VkCommandBuffer *pCommandBuffers)
1347 {
1348 RADV_FROM_HANDLE(radv_device, device, _device);
1349 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1350
1351 VkResult result = VK_SUCCESS;
1352 uint32_t i;
1353
1354 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1355 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1356 &pCommandBuffers[i]);
1357 if (result != VK_SUCCESS)
1358 break;
1359 }
1360
1361 if (result != VK_SUCCESS)
1362 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1363 i, pCommandBuffers);
1364
1365 return result;
1366 }
1367
1368 static void
1369 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
1370 {
1371 list_del(&cmd_buffer->pool_link);
1372
1373 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1374 &cmd_buffer->upload.list, list) {
1375 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1376 list_del(&up->list);
1377 free(up);
1378 }
1379
1380 if (cmd_buffer->upload.upload_bo)
1381 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
1382 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
1383 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1384 }
1385
1386 void radv_FreeCommandBuffers(
1387 VkDevice device,
1388 VkCommandPool commandPool,
1389 uint32_t commandBufferCount,
1390 const VkCommandBuffer *pCommandBuffers)
1391 {
1392 for (uint32_t i = 0; i < commandBufferCount; i++) {
1393 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1394
1395 if (cmd_buffer)
1396 radv_cmd_buffer_destroy(cmd_buffer);
1397 }
1398 }
1399
1400 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
1401 {
1402
1403 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
1404
1405 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1406 &cmd_buffer->upload.list, list) {
1407 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1408 list_del(&up->list);
1409 free(up);
1410 }
1411
1412 cmd_buffer->scratch_size_needed = 0;
1413 cmd_buffer->compute_scratch_size_needed = 0;
1414 if (cmd_buffer->upload.upload_bo)
1415 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
1416 cmd_buffer->upload.upload_bo, 8);
1417 cmd_buffer->upload.offset = 0;
1418
1419 cmd_buffer->record_fail = false;
1420 }
1421
1422 VkResult radv_ResetCommandBuffer(
1423 VkCommandBuffer commandBuffer,
1424 VkCommandBufferResetFlags flags)
1425 {
1426 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1427 radv_reset_cmd_buffer(cmd_buffer);
1428 return VK_SUCCESS;
1429 }
1430
1431 VkResult radv_BeginCommandBuffer(
1432 VkCommandBuffer commandBuffer,
1433 const VkCommandBufferBeginInfo *pBeginInfo)
1434 {
1435 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1436 radv_reset_cmd_buffer(cmd_buffer);
1437
1438 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1439
1440 /* setup initial configuration into command buffer */
1441 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1442 switch (cmd_buffer->queue_family_index) {
1443 case RADV_QUEUE_GENERAL:
1444 /* Flush read caches at the beginning of CS not flushed by the kernel. */
1445 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_ICACHE |
1446 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1447 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1448 RADV_CMD_FLAG_INV_VMEM_L1 |
1449 RADV_CMD_FLAG_INV_SMEM_L1 |
1450 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
1451 RADV_CMD_FLAG_INV_GLOBAL_L2;
1452 si_init_config(cmd_buffer->device->physical_device, cmd_buffer);
1453 radv_set_db_count_control(cmd_buffer);
1454 si_emit_cache_flush(cmd_buffer);
1455 break;
1456 case RADV_QUEUE_COMPUTE:
1457 cmd_buffer->state.flush_bits = RADV_CMD_FLAG_INV_ICACHE |
1458 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1459 RADV_CMD_FLAG_INV_VMEM_L1 |
1460 RADV_CMD_FLAG_INV_SMEM_L1 |
1461 RADV_CMD_FLAG_INV_GLOBAL_L2;
1462 si_init_compute(cmd_buffer->device->physical_device, cmd_buffer);
1463 si_emit_cache_flush(cmd_buffer);
1464 break;
1465 case RADV_QUEUE_TRANSFER:
1466 default:
1467 break;
1468 }
1469 }
1470
1471 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1472 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1473 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1474
1475 struct radv_subpass *subpass =
1476 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1477
1478 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1479 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1480 }
1481
1482 return VK_SUCCESS;
1483 }
1484
1485 void radv_CmdBindVertexBuffers(
1486 VkCommandBuffer commandBuffer,
1487 uint32_t firstBinding,
1488 uint32_t bindingCount,
1489 const VkBuffer* pBuffers,
1490 const VkDeviceSize* pOffsets)
1491 {
1492 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1493 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1494
1495 /* We have to defer setting up vertex buffer since we need the buffer
1496 * stride from the pipeline. */
1497
1498 assert(firstBinding + bindingCount < MAX_VBS);
1499 for (uint32_t i = 0; i < bindingCount; i++) {
1500 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1501 vb[firstBinding + i].offset = pOffsets[i];
1502 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1503 }
1504 }
1505
1506 void radv_CmdBindIndexBuffer(
1507 VkCommandBuffer commandBuffer,
1508 VkBuffer buffer,
1509 VkDeviceSize offset,
1510 VkIndexType indexType)
1511 {
1512 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1513
1514 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1515 cmd_buffer->state.index_offset = offset;
1516 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1517 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1518 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1519 }
1520
1521
1522 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1523 struct radv_descriptor_set *set,
1524 unsigned idx)
1525 {
1526 struct radeon_winsys *ws = cmd_buffer->device->ws;
1527
1528 cmd_buffer->state.descriptors[idx] = set;
1529 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1530 if (!set)
1531 return;
1532
1533 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1534 if (set->descriptors[j])
1535 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1536
1537 if(set->bo)
1538 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1539 }
1540
1541 void radv_CmdBindDescriptorSets(
1542 VkCommandBuffer commandBuffer,
1543 VkPipelineBindPoint pipelineBindPoint,
1544 VkPipelineLayout _layout,
1545 uint32_t firstSet,
1546 uint32_t descriptorSetCount,
1547 const VkDescriptorSet* pDescriptorSets,
1548 uint32_t dynamicOffsetCount,
1549 const uint32_t* pDynamicOffsets)
1550 {
1551 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1552 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1553 unsigned dyn_idx = 0;
1554
1555 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1556 cmd_buffer->cs, MAX_SETS * 4 * 6);
1557
1558 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1559 unsigned idx = i + firstSet;
1560 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1561 radv_bind_descriptor_set(cmd_buffer, set, idx);
1562
1563 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1564 unsigned idx = j + layout->set[i].dynamic_offset_start;
1565 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1566 assert(dyn_idx < dynamicOffsetCount);
1567
1568 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1569 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1570 dst[0] = va;
1571 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1572 dst[2] = range->size;
1573 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1574 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1575 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1576 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1577 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1578 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1579 cmd_buffer->push_constant_stages |=
1580 set->layout->dynamic_shader_stages;
1581 }
1582 }
1583
1584 assert(cmd_buffer->cs->cdw <= cdw_max);
1585 }
1586
1587 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1588 VkPipelineLayout layout,
1589 VkShaderStageFlags stageFlags,
1590 uint32_t offset,
1591 uint32_t size,
1592 const void* pValues)
1593 {
1594 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1595 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1596 cmd_buffer->push_constant_stages |= stageFlags;
1597 }
1598
1599 VkResult radv_EndCommandBuffer(
1600 VkCommandBuffer commandBuffer)
1601 {
1602 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1603
1604 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
1605 si_emit_cache_flush(cmd_buffer);
1606 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1607 cmd_buffer->record_fail)
1608 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1609 return VK_SUCCESS;
1610 }
1611
1612 static void
1613 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1614 {
1615 struct radeon_winsys *ws = cmd_buffer->device->ws;
1616 struct radv_shader_variant *compute_shader;
1617 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1618 uint64_t va;
1619
1620 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1621 return;
1622
1623 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1624
1625 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1626 va = ws->buffer_get_va(compute_shader->bo);
1627
1628 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1629
1630 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1631 cmd_buffer->cs, 16);
1632
1633 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1634 radeon_emit(cmd_buffer->cs, va >> 8);
1635 radeon_emit(cmd_buffer->cs, va >> 40);
1636
1637 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1638 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1639 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1640
1641
1642 cmd_buffer->compute_scratch_size_needed =
1643 MAX2(cmd_buffer->compute_scratch_size_needed,
1644 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1645
1646 /* change these once we have scratch support */
1647 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1648 S_00B860_WAVES(pipeline->max_waves) |
1649 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1650
1651 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1652 radeon_emit(cmd_buffer->cs,
1653 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1654 radeon_emit(cmd_buffer->cs,
1655 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1656 radeon_emit(cmd_buffer->cs,
1657 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1658
1659 assert(cmd_buffer->cs->cdw <= cdw_max);
1660 }
1661
1662
1663 void radv_CmdBindPipeline(
1664 VkCommandBuffer commandBuffer,
1665 VkPipelineBindPoint pipelineBindPoint,
1666 VkPipeline _pipeline)
1667 {
1668 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1669 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1670
1671 for (unsigned i = 0; i < MAX_SETS; i++) {
1672 if (cmd_buffer->state.descriptors[i])
1673 cmd_buffer->state.descriptors_dirty |= (1 << i);
1674 }
1675
1676 switch (pipelineBindPoint) {
1677 case VK_PIPELINE_BIND_POINT_COMPUTE:
1678 cmd_buffer->state.compute_pipeline = pipeline;
1679 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
1680 break;
1681 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1682 cmd_buffer->state.pipeline = pipeline;
1683 cmd_buffer->state.vertex_descriptors_dirty = true;
1684 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1685 cmd_buffer->push_constant_stages |= pipeline->active_stages;
1686
1687 /* Apply the dynamic state from the pipeline */
1688 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
1689 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
1690 &pipeline->dynamic_state,
1691 pipeline->dynamic_state_mask);
1692 break;
1693 default:
1694 assert(!"invalid bind point");
1695 break;
1696 }
1697 }
1698
1699 void radv_CmdSetViewport(
1700 VkCommandBuffer commandBuffer,
1701 uint32_t firstViewport,
1702 uint32_t viewportCount,
1703 const VkViewport* pViewports)
1704 {
1705 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1706
1707 const uint32_t total_count = firstViewport + viewportCount;
1708 if (cmd_buffer->state.dynamic.viewport.count < total_count)
1709 cmd_buffer->state.dynamic.viewport.count = total_count;
1710
1711 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
1712 pViewports, viewportCount * sizeof(*pViewports));
1713
1714 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
1715 }
1716
1717 void radv_CmdSetScissor(
1718 VkCommandBuffer commandBuffer,
1719 uint32_t firstScissor,
1720 uint32_t scissorCount,
1721 const VkRect2D* pScissors)
1722 {
1723 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1724
1725 const uint32_t total_count = firstScissor + scissorCount;
1726 if (cmd_buffer->state.dynamic.scissor.count < total_count)
1727 cmd_buffer->state.dynamic.scissor.count = total_count;
1728
1729 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
1730 pScissors, scissorCount * sizeof(*pScissors));
1731 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1732 }
1733
1734 void radv_CmdSetLineWidth(
1735 VkCommandBuffer commandBuffer,
1736 float lineWidth)
1737 {
1738 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1739 cmd_buffer->state.dynamic.line_width = lineWidth;
1740 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1741 }
1742
1743 void radv_CmdSetDepthBias(
1744 VkCommandBuffer commandBuffer,
1745 float depthBiasConstantFactor,
1746 float depthBiasClamp,
1747 float depthBiasSlopeFactor)
1748 {
1749 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1750
1751 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
1752 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
1753 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
1754
1755 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1756 }
1757
1758 void radv_CmdSetBlendConstants(
1759 VkCommandBuffer commandBuffer,
1760 const float blendConstants[4])
1761 {
1762 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1763
1764 memcpy(cmd_buffer->state.dynamic.blend_constants,
1765 blendConstants, sizeof(float) * 4);
1766
1767 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
1768 }
1769
1770 void radv_CmdSetDepthBounds(
1771 VkCommandBuffer commandBuffer,
1772 float minDepthBounds,
1773 float maxDepthBounds)
1774 {
1775 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1776
1777 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
1778 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
1779
1780 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
1781 }
1782
1783 void radv_CmdSetStencilCompareMask(
1784 VkCommandBuffer commandBuffer,
1785 VkStencilFaceFlags faceMask,
1786 uint32_t compareMask)
1787 {
1788 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1789
1790 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1791 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
1792 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1793 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
1794
1795 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1796 }
1797
1798 void radv_CmdSetStencilWriteMask(
1799 VkCommandBuffer commandBuffer,
1800 VkStencilFaceFlags faceMask,
1801 uint32_t writeMask)
1802 {
1803 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1804
1805 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1806 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
1807 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1808 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
1809
1810 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1811 }
1812
1813 void radv_CmdSetStencilReference(
1814 VkCommandBuffer commandBuffer,
1815 VkStencilFaceFlags faceMask,
1816 uint32_t reference)
1817 {
1818 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1819
1820 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1821 cmd_buffer->state.dynamic.stencil_reference.front = reference;
1822 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1823 cmd_buffer->state.dynamic.stencil_reference.back = reference;
1824
1825 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1826 }
1827
1828
1829 void radv_CmdExecuteCommands(
1830 VkCommandBuffer commandBuffer,
1831 uint32_t commandBufferCount,
1832 const VkCommandBuffer* pCmdBuffers)
1833 {
1834 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
1835
1836 for (uint32_t i = 0; i < commandBufferCount; i++) {
1837 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
1838
1839 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
1840 secondary->scratch_size_needed);
1841 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
1842 secondary->compute_scratch_size_needed);
1843
1844 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
1845 }
1846
1847 /* if we execute secondary we need to re-emit out pipelines */
1848 if (commandBufferCount) {
1849 primary->state.emitted_pipeline = NULL;
1850 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1851 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
1852 }
1853 }
1854
1855 VkResult radv_CreateCommandPool(
1856 VkDevice _device,
1857 const VkCommandPoolCreateInfo* pCreateInfo,
1858 const VkAllocationCallbacks* pAllocator,
1859 VkCommandPool* pCmdPool)
1860 {
1861 RADV_FROM_HANDLE(radv_device, device, _device);
1862 struct radv_cmd_pool *pool;
1863
1864 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
1865 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1866 if (pool == NULL)
1867 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1868
1869 if (pAllocator)
1870 pool->alloc = *pAllocator;
1871 else
1872 pool->alloc = device->alloc;
1873
1874 list_inithead(&pool->cmd_buffers);
1875
1876 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
1877
1878 *pCmdPool = radv_cmd_pool_to_handle(pool);
1879
1880 return VK_SUCCESS;
1881
1882 }
1883
1884 void radv_DestroyCommandPool(
1885 VkDevice _device,
1886 VkCommandPool commandPool,
1887 const VkAllocationCallbacks* pAllocator)
1888 {
1889 RADV_FROM_HANDLE(radv_device, device, _device);
1890 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
1891
1892 if (!pool)
1893 return;
1894
1895 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
1896 &pool->cmd_buffers, pool_link) {
1897 radv_cmd_buffer_destroy(cmd_buffer);
1898 }
1899
1900 vk_free2(&device->alloc, pAllocator, pool);
1901 }
1902
1903 VkResult radv_ResetCommandPool(
1904 VkDevice device,
1905 VkCommandPool commandPool,
1906 VkCommandPoolResetFlags flags)
1907 {
1908 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
1909
1910 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
1911 &pool->cmd_buffers, pool_link) {
1912 radv_reset_cmd_buffer(cmd_buffer);
1913 }
1914
1915 return VK_SUCCESS;
1916 }
1917
1918 void radv_CmdBeginRenderPass(
1919 VkCommandBuffer commandBuffer,
1920 const VkRenderPassBeginInfo* pRenderPassBegin,
1921 VkSubpassContents contents)
1922 {
1923 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1924 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
1925 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
1926
1927 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1928 cmd_buffer->cs, 2048);
1929
1930 cmd_buffer->state.framebuffer = framebuffer;
1931 cmd_buffer->state.pass = pass;
1932 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
1933 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
1934
1935 si_emit_cache_flush(cmd_buffer);
1936
1937 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
1938 assert(cmd_buffer->cs->cdw <= cdw_max);
1939
1940 radv_cmd_buffer_clear_subpass(cmd_buffer);
1941 }
1942
1943 void radv_CmdNextSubpass(
1944 VkCommandBuffer commandBuffer,
1945 VkSubpassContents contents)
1946 {
1947 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1948
1949 si_emit_cache_flush(cmd_buffer);
1950 radv_cmd_buffer_resolve_subpass(cmd_buffer);
1951
1952 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
1953 2048);
1954
1955 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
1956 radv_cmd_buffer_clear_subpass(cmd_buffer);
1957 }
1958
1959 void radv_CmdDraw(
1960 VkCommandBuffer commandBuffer,
1961 uint32_t vertexCount,
1962 uint32_t instanceCount,
1963 uint32_t firstVertex,
1964 uint32_t firstInstance)
1965 {
1966 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1967 radv_cmd_buffer_flush_state(cmd_buffer);
1968
1969 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1970
1971 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1972 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
1973 if (loc->sgpr_idx != -1) {
1974 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4, 2);
1975 radeon_emit(cmd_buffer->cs, firstVertex);
1976 radeon_emit(cmd_buffer->cs, firstInstance);
1977 }
1978 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
1979 radeon_emit(cmd_buffer->cs, instanceCount);
1980
1981 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
1982 radeon_emit(cmd_buffer->cs, vertexCount);
1983 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1984 S_0287F0_USE_OPAQUE(0));
1985
1986 assert(cmd_buffer->cs->cdw <= cdw_max);
1987
1988 radv_cmd_buffer_trace_emit(cmd_buffer);
1989 }
1990
1991 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
1992 {
1993 uint32_t primitive_reset_index = cmd_buffer->state.last_primitive_reset_index ? 0xffffffffu : 0xffffu;
1994
1995 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
1996 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1997 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1998 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1999 primitive_reset_index);
2000 }
2001 }
2002
2003 void radv_CmdDrawIndexed(
2004 VkCommandBuffer commandBuffer,
2005 uint32_t indexCount,
2006 uint32_t instanceCount,
2007 uint32_t firstIndex,
2008 int32_t vertexOffset,
2009 uint32_t firstInstance)
2010 {
2011 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2012 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2013 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2014 uint64_t index_va;
2015
2016 radv_cmd_buffer_flush_state(cmd_buffer);
2017 radv_emit_primitive_reset_index(cmd_buffer);
2018
2019 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 14);
2020
2021 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2022 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2023
2024 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2025 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2026 if (loc->sgpr_idx != -1) {
2027 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4, 2);
2028 radeon_emit(cmd_buffer->cs, vertexOffset);
2029 radeon_emit(cmd_buffer->cs, firstInstance);
2030 }
2031 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2032 radeon_emit(cmd_buffer->cs, instanceCount);
2033
2034 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2035 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2036 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2037 radeon_emit(cmd_buffer->cs, index_max_size);
2038 radeon_emit(cmd_buffer->cs, index_va);
2039 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2040 radeon_emit(cmd_buffer->cs, indexCount);
2041 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2042
2043 assert(cmd_buffer->cs->cdw <= cdw_max);
2044 radv_cmd_buffer_trace_emit(cmd_buffer);
2045 }
2046
2047 static void
2048 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2049 VkBuffer _buffer,
2050 VkDeviceSize offset,
2051 VkBuffer _count_buffer,
2052 VkDeviceSize count_offset,
2053 uint32_t draw_count,
2054 uint32_t stride,
2055 bool indexed)
2056 {
2057 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2058 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2059 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2060 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2061 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2062 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2063 indirect_va += offset + buffer->offset;
2064 uint64_t count_va = 0;
2065
2066 if (count_buffer) {
2067 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2068 count_va += count_offset + count_buffer->offset;
2069 }
2070
2071 if (!draw_count)
2072 return;
2073
2074 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2075
2076 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2077 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2078 assert(loc->sgpr_idx != -1);
2079 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2080 radeon_emit(cs, 1);
2081 radeon_emit(cs, indirect_va);
2082 radeon_emit(cs, indirect_va >> 32);
2083
2084 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2085 PKT3_DRAW_INDIRECT_MULTI,
2086 8, false));
2087 radeon_emit(cs, 0);
2088 radeon_emit(cs, ((R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2089 radeon_emit(cs, ((R_00B130_SPI_SHADER_USER_DATA_VS_0 + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2090 radeon_emit(cs, S_2C3_COUNT_INDIRECT_ENABLE(!!count_va)); /* draw_index and count_indirect enable */
2091 radeon_emit(cs, draw_count); /* count */
2092 radeon_emit(cs, count_va); /* count_addr */
2093 radeon_emit(cs, count_va >> 32);
2094 radeon_emit(cs, stride); /* stride */
2095 radeon_emit(cs, di_src_sel);
2096 radv_cmd_buffer_trace_emit(cmd_buffer);
2097 }
2098
2099 static void
2100 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2101 VkBuffer buffer,
2102 VkDeviceSize offset,
2103 VkBuffer countBuffer,
2104 VkDeviceSize countBufferOffset,
2105 uint32_t maxDrawCount,
2106 uint32_t stride)
2107 {
2108 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2109 radv_cmd_buffer_flush_state(cmd_buffer);
2110
2111 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2112 cmd_buffer->cs, 14);
2113
2114 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2115 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2116
2117 assert(cmd_buffer->cs->cdw <= cdw_max);
2118 }
2119
2120 static void
2121 radv_cmd_draw_indexed_indirect_count(
2122 VkCommandBuffer commandBuffer,
2123 VkBuffer buffer,
2124 VkDeviceSize offset,
2125 VkBuffer countBuffer,
2126 VkDeviceSize countBufferOffset,
2127 uint32_t maxDrawCount,
2128 uint32_t stride)
2129 {
2130 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2131 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2132 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2133 uint64_t index_va;
2134 radv_cmd_buffer_flush_state(cmd_buffer);
2135 radv_emit_primitive_reset_index(cmd_buffer);
2136
2137 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2138 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2139
2140 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2141
2142 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2143 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2144
2145 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2146 radeon_emit(cmd_buffer->cs, index_va);
2147 radeon_emit(cmd_buffer->cs, index_va >> 32);
2148
2149 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2150 radeon_emit(cmd_buffer->cs, index_max_size);
2151
2152 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2153 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2154
2155 assert(cmd_buffer->cs->cdw <= cdw_max);
2156 }
2157
2158 void radv_CmdDrawIndirect(
2159 VkCommandBuffer commandBuffer,
2160 VkBuffer buffer,
2161 VkDeviceSize offset,
2162 uint32_t drawCount,
2163 uint32_t stride)
2164 {
2165 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2166 VK_NULL_HANDLE, 0, drawCount, stride);
2167 }
2168
2169 void radv_CmdDrawIndexedIndirect(
2170 VkCommandBuffer commandBuffer,
2171 VkBuffer buffer,
2172 VkDeviceSize offset,
2173 uint32_t drawCount,
2174 uint32_t stride)
2175 {
2176 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2177 VK_NULL_HANDLE, 0, drawCount, stride);
2178 }
2179
2180 void radv_CmdDrawIndirectCountAMD(
2181 VkCommandBuffer commandBuffer,
2182 VkBuffer buffer,
2183 VkDeviceSize offset,
2184 VkBuffer countBuffer,
2185 VkDeviceSize countBufferOffset,
2186 uint32_t maxDrawCount,
2187 uint32_t stride)
2188 {
2189 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2190 countBuffer, countBufferOffset,
2191 maxDrawCount, stride);
2192 }
2193
2194 void radv_CmdDrawIndexedIndirectCountAMD(
2195 VkCommandBuffer commandBuffer,
2196 VkBuffer buffer,
2197 VkDeviceSize offset,
2198 VkBuffer countBuffer,
2199 VkDeviceSize countBufferOffset,
2200 uint32_t maxDrawCount,
2201 uint32_t stride)
2202 {
2203 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2204 countBuffer, countBufferOffset,
2205 maxDrawCount, stride);
2206 }
2207
2208 static void
2209 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2210 {
2211 radv_emit_compute_pipeline(cmd_buffer);
2212 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2213 VK_SHADER_STAGE_COMPUTE_BIT);
2214 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2215 VK_SHADER_STAGE_COMPUTE_BIT);
2216 si_emit_cache_flush(cmd_buffer);
2217 }
2218
2219 void radv_CmdDispatch(
2220 VkCommandBuffer commandBuffer,
2221 uint32_t x,
2222 uint32_t y,
2223 uint32_t z)
2224 {
2225 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2226
2227 radv_flush_compute_state(cmd_buffer);
2228
2229 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2230
2231 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2232 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2233 if (loc->sgpr_idx != -1) {
2234 assert(!loc->indirect);
2235 assert(loc->num_sgprs == 3);
2236 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2237 radeon_emit(cmd_buffer->cs, x);
2238 radeon_emit(cmd_buffer->cs, y);
2239 radeon_emit(cmd_buffer->cs, z);
2240 }
2241
2242 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2243 PKT3_SHADER_TYPE_S(1));
2244 radeon_emit(cmd_buffer->cs, x);
2245 radeon_emit(cmd_buffer->cs, y);
2246 radeon_emit(cmd_buffer->cs, z);
2247 radeon_emit(cmd_buffer->cs, 1);
2248
2249 assert(cmd_buffer->cs->cdw <= cdw_max);
2250 radv_cmd_buffer_trace_emit(cmd_buffer);
2251 }
2252
2253 void radv_CmdDispatchIndirect(
2254 VkCommandBuffer commandBuffer,
2255 VkBuffer _buffer,
2256 VkDeviceSize offset)
2257 {
2258 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2259 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2260 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2261 va += buffer->offset + offset;
2262
2263 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2264
2265 radv_flush_compute_state(cmd_buffer);
2266
2267 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2268 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2269 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2270 if (loc->sgpr_idx != -1) {
2271 for (unsigned i = 0; i < 3; ++i) {
2272 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2273 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2274 COPY_DATA_DST_SEL(COPY_DATA_REG));
2275 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2276 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2277 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2278 radeon_emit(cmd_buffer->cs, 0);
2279 }
2280 }
2281
2282 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2283 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2284 PKT3_SHADER_TYPE_S(1));
2285 radeon_emit(cmd_buffer->cs, va);
2286 radeon_emit(cmd_buffer->cs, va >> 32);
2287 radeon_emit(cmd_buffer->cs, 1);
2288 } else {
2289 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2290 PKT3_SHADER_TYPE_S(1));
2291 radeon_emit(cmd_buffer->cs, 1);
2292 radeon_emit(cmd_buffer->cs, va);
2293 radeon_emit(cmd_buffer->cs, va >> 32);
2294
2295 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2296 PKT3_SHADER_TYPE_S(1));
2297 radeon_emit(cmd_buffer->cs, 0);
2298 radeon_emit(cmd_buffer->cs, 1);
2299 }
2300
2301 assert(cmd_buffer->cs->cdw <= cdw_max);
2302 radv_cmd_buffer_trace_emit(cmd_buffer);
2303 }
2304
2305 void radv_unaligned_dispatch(
2306 struct radv_cmd_buffer *cmd_buffer,
2307 uint32_t x,
2308 uint32_t y,
2309 uint32_t z)
2310 {
2311 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2312 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2313 uint32_t blocks[3], remainder[3];
2314
2315 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2316 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2317 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2318
2319 /* If aligned, these should be an entire block size, not 0 */
2320 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2321 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2322 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2323
2324 radv_flush_compute_state(cmd_buffer);
2325
2326 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2327
2328 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2329 radeon_emit(cmd_buffer->cs,
2330 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2331 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2332 radeon_emit(cmd_buffer->cs,
2333 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2334 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2335 radeon_emit(cmd_buffer->cs,
2336 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2337 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2338
2339 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2340 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2341 if (loc->sgpr_idx != -1) {
2342 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2343 radeon_emit(cmd_buffer->cs, blocks[0]);
2344 radeon_emit(cmd_buffer->cs, blocks[1]);
2345 radeon_emit(cmd_buffer->cs, blocks[2]);
2346 }
2347 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2348 PKT3_SHADER_TYPE_S(1));
2349 radeon_emit(cmd_buffer->cs, blocks[0]);
2350 radeon_emit(cmd_buffer->cs, blocks[1]);
2351 radeon_emit(cmd_buffer->cs, blocks[2]);
2352 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2353 S_00B800_PARTIAL_TG_EN(1));
2354
2355 assert(cmd_buffer->cs->cdw <= cdw_max);
2356 radv_cmd_buffer_trace_emit(cmd_buffer);
2357 }
2358
2359 void radv_CmdEndRenderPass(
2360 VkCommandBuffer commandBuffer)
2361 {
2362 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2363
2364 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2365
2366 si_emit_cache_flush(cmd_buffer);
2367 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2368
2369 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2370 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2371 radv_handle_subpass_image_transition(cmd_buffer,
2372 (VkAttachmentReference){i, layout});
2373 }
2374
2375 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2376
2377 cmd_buffer->state.pass = NULL;
2378 cmd_buffer->state.subpass = NULL;
2379 cmd_buffer->state.attachments = NULL;
2380 cmd_buffer->state.framebuffer = NULL;
2381 }
2382
2383
2384 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2385 struct radv_image *image)
2386 {
2387
2388 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2389 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2390
2391 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->htile.offset,
2392 image->htile.size, 0xffffffff);
2393
2394 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2395 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2396 RADV_CMD_FLAG_INV_VMEM_L1 |
2397 RADV_CMD_FLAG_INV_GLOBAL_L2;
2398 }
2399
2400 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2401 struct radv_image *image,
2402 VkImageLayout src_layout,
2403 VkImageLayout dst_layout,
2404 VkImageSubresourceRange range,
2405 VkImageAspectFlags pending_clears)
2406 {
2407 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2408 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2409 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2410 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2411 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2412 /* The clear will initialize htile. */
2413 return;
2414 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2415 radv_layout_has_htile(image, dst_layout)) {
2416 /* TODO: merge with the clear if applicable */
2417 radv_initialize_htile(cmd_buffer, image);
2418 } else if (!radv_layout_has_htile(image, src_layout) &&
2419 radv_layout_has_htile(image, dst_layout)) {
2420 radv_initialize_htile(cmd_buffer, image);
2421 } else if ((radv_layout_has_htile(image, src_layout) &&
2422 !radv_layout_has_htile(image, dst_layout)) ||
2423 (radv_layout_is_htile_compressed(image, src_layout) &&
2424 !radv_layout_is_htile_compressed(image, dst_layout))) {
2425
2426 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2427 range.baseMipLevel = 0;
2428 range.levelCount = 1;
2429
2430 radv_decompress_depth_image_inplace(cmd_buffer, image, &range);
2431 }
2432 }
2433
2434 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2435 struct radv_image *image, uint32_t value)
2436 {
2437 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2438 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2439
2440 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2441 image->cmask.size, value);
2442
2443 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2444 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2445 RADV_CMD_FLAG_INV_VMEM_L1 |
2446 RADV_CMD_FLAG_INV_GLOBAL_L2;
2447 }
2448
2449 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2450 struct radv_image *image,
2451 VkImageLayout src_layout,
2452 VkImageLayout dst_layout,
2453 unsigned src_queue_mask,
2454 unsigned dst_queue_mask,
2455 VkImageSubresourceRange range,
2456 VkImageAspectFlags pending_clears)
2457 {
2458 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2459 if (image->fmask.size)
2460 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2461 else
2462 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2463 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2464 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2465 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2466 }
2467 }
2468
2469 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2470 struct radv_image *image, uint32_t value)
2471 {
2472
2473 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2474 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2475
2476 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2477 image->surface.dcc_size, value);
2478
2479 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2480 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2481 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2482 RADV_CMD_FLAG_INV_VMEM_L1 |
2483 RADV_CMD_FLAG_INV_GLOBAL_L2;
2484 }
2485
2486 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2487 struct radv_image *image,
2488 VkImageLayout src_layout,
2489 VkImageLayout dst_layout,
2490 unsigned src_queue_mask,
2491 unsigned dst_queue_mask,
2492 VkImageSubresourceRange range,
2493 VkImageAspectFlags pending_clears)
2494 {
2495 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2496 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2497 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2498 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2499 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2500 }
2501 }
2502
2503 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2504 struct radv_image *image,
2505 VkImageLayout src_layout,
2506 VkImageLayout dst_layout,
2507 int src_family,
2508 int dst_family,
2509 VkImageSubresourceRange range,
2510 VkImageAspectFlags pending_clears)
2511 {
2512 if (image->exclusive && src_family != dst_family) {
2513 /* This is an acquire or a release operation and there will be
2514 * a corresponding release/acquire. Do the transition in the
2515 * most flexible queue. */
2516
2517 assert(src_family == cmd_buffer->queue_family_index ||
2518 dst_family == cmd_buffer->queue_family_index);
2519
2520 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
2521 return;
2522
2523 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
2524 (src_family == RADV_QUEUE_GENERAL ||
2525 dst_family == RADV_QUEUE_GENERAL))
2526 return;
2527 }
2528
2529 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family);
2530 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family);
2531
2532 if (image->htile.size)
2533 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2534 dst_layout, range, pending_clears);
2535
2536 if (image->cmask.size)
2537 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2538 dst_layout, src_queue_mask,
2539 dst_queue_mask, range,
2540 pending_clears);
2541
2542 if (image->surface.dcc_size)
2543 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2544 dst_layout, src_queue_mask,
2545 dst_queue_mask, range,
2546 pending_clears);
2547 }
2548
2549 void radv_CmdPipelineBarrier(
2550 VkCommandBuffer commandBuffer,
2551 VkPipelineStageFlags srcStageMask,
2552 VkPipelineStageFlags destStageMask,
2553 VkBool32 byRegion,
2554 uint32_t memoryBarrierCount,
2555 const VkMemoryBarrier* pMemoryBarriers,
2556 uint32_t bufferMemoryBarrierCount,
2557 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2558 uint32_t imageMemoryBarrierCount,
2559 const VkImageMemoryBarrier* pImageMemoryBarriers)
2560 {
2561 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2562 VkAccessFlags src_flags = 0;
2563 VkAccessFlags dst_flags = 0;
2564 uint32_t b;
2565 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2566 src_flags |= pMemoryBarriers[i].srcAccessMask;
2567 dst_flags |= pMemoryBarriers[i].dstAccessMask;
2568 }
2569
2570 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2571 src_flags |= pBufferMemoryBarriers[i].srcAccessMask;
2572 dst_flags |= pBufferMemoryBarriers[i].dstAccessMask;
2573 }
2574
2575 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2576 src_flags |= pImageMemoryBarriers[i].srcAccessMask;
2577 dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
2578 }
2579
2580 enum radv_cmd_flush_bits flush_bits = 0;
2581 for_each_bit(b, src_flags) {
2582 switch ((VkAccessFlagBits)(1 << b)) {
2583 case VK_ACCESS_SHADER_WRITE_BIT:
2584 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2585 break;
2586 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2587 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2588 break;
2589 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2590 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2591 break;
2592 case VK_ACCESS_TRANSFER_WRITE_BIT:
2593 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2594 break;
2595 default:
2596 break;
2597 }
2598 }
2599 cmd_buffer->state.flush_bits |= flush_bits;
2600
2601 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2602 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2603 radv_handle_image_transition(cmd_buffer, image,
2604 pImageMemoryBarriers[i].oldLayout,
2605 pImageMemoryBarriers[i].newLayout,
2606 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2607 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2608 pImageMemoryBarriers[i].subresourceRange,
2609 0);
2610 }
2611
2612 flush_bits = 0;
2613
2614 for_each_bit(b, dst_flags) {
2615 switch ((VkAccessFlagBits)(1 << b)) {
2616 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2617 case VK_ACCESS_INDEX_READ_BIT:
2618 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2619 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2620 break;
2621 case VK_ACCESS_UNIFORM_READ_BIT:
2622 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2623 break;
2624 case VK_ACCESS_SHADER_READ_BIT:
2625 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2626 break;
2627 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2628 case VK_ACCESS_TRANSFER_READ_BIT:
2629 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2630 flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER | RADV_CMD_FLAG_INV_GLOBAL_L2;
2631 default:
2632 break;
2633 }
2634 }
2635
2636 flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2637 RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2638
2639 cmd_buffer->state.flush_bits |= flush_bits;
2640 }
2641
2642
2643 static void write_event(struct radv_cmd_buffer *cmd_buffer,
2644 struct radv_event *event,
2645 VkPipelineStageFlags stageMask,
2646 unsigned value)
2647 {
2648 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2649 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2650
2651 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2652
2653 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
2654
2655 /* TODO: this is overkill. Probably should figure something out from
2656 * the stage mask. */
2657
2658 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
2659 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2660 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2661 EVENT_INDEX(5));
2662 radeon_emit(cs, va);
2663 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2664 radeon_emit(cs, 2);
2665 radeon_emit(cs, 0);
2666 }
2667
2668 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2669 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2670 EVENT_INDEX(5));
2671 radeon_emit(cs, va);
2672 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2673 radeon_emit(cs, value);
2674 radeon_emit(cs, 0);
2675
2676 assert(cmd_buffer->cs->cdw <= cdw_max);
2677 }
2678
2679 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
2680 VkEvent _event,
2681 VkPipelineStageFlags stageMask)
2682 {
2683 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2684 RADV_FROM_HANDLE(radv_event, event, _event);
2685
2686 write_event(cmd_buffer, event, stageMask, 1);
2687 }
2688
2689 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
2690 VkEvent _event,
2691 VkPipelineStageFlags stageMask)
2692 {
2693 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2694 RADV_FROM_HANDLE(radv_event, event, _event);
2695
2696 write_event(cmd_buffer, event, stageMask, 0);
2697 }
2698
2699 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
2700 uint32_t eventCount,
2701 const VkEvent* pEvents,
2702 VkPipelineStageFlags srcStageMask,
2703 VkPipelineStageFlags dstStageMask,
2704 uint32_t memoryBarrierCount,
2705 const VkMemoryBarrier* pMemoryBarriers,
2706 uint32_t bufferMemoryBarrierCount,
2707 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2708 uint32_t imageMemoryBarrierCount,
2709 const VkImageMemoryBarrier* pImageMemoryBarriers)
2710 {
2711 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2712 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2713
2714 for (unsigned i = 0; i < eventCount; ++i) {
2715 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
2716 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2717
2718 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2719
2720 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
2721
2722 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
2723 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
2724 radeon_emit(cs, va);
2725 radeon_emit(cs, va >> 32);
2726 radeon_emit(cs, 1); /* reference value */
2727 radeon_emit(cs, 0xffffffff); /* mask */
2728 radeon_emit(cs, 4); /* poll interval */
2729
2730 assert(cmd_buffer->cs->cdw <= cdw_max);
2731 }
2732
2733
2734 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2735 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2736
2737 radv_handle_image_transition(cmd_buffer, image,
2738 pImageMemoryBarriers[i].oldLayout,
2739 pImageMemoryBarriers[i].newLayout,
2740 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2741 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2742 pImageMemoryBarriers[i].subresourceRange,
2743 0);
2744 }
2745
2746 /* TODO: figure out how to do memory barriers without waiting */
2747 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
2748 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2749 RADV_CMD_FLAG_INV_VMEM_L1 |
2750 RADV_CMD_FLAG_INV_SMEM_L1;
2751 }