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radv: set the predicate for indirect/indexed draw commands
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safely call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
314 cmd_buffer->descriptors[i].dirty = 0;
315 cmd_buffer->descriptors[i].valid = 0;
316 cmd_buffer->descriptors[i].push_dirty = false;
317 }
318
319 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
320 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
321 unsigned eop_bug_offset;
322 void *fence_ptr;
323
324 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
325 &cmd_buffer->gfx9_fence_offset,
326 &fence_ptr);
327 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
328
329 /* Allocate a buffer for the EOP bug on GFX9. */
330 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
331 &eop_bug_offset, &fence_ptr);
332 cmd_buffer->gfx9_eop_bug_va =
333 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
334 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
335 }
336
337 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
338
339 return cmd_buffer->record_result;
340 }
341
342 static bool
343 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
344 uint64_t min_needed)
345 {
346 uint64_t new_size;
347 struct radeon_winsys_bo *bo;
348 struct radv_cmd_buffer_upload *upload;
349 struct radv_device *device = cmd_buffer->device;
350
351 new_size = MAX2(min_needed, 16 * 1024);
352 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
353
354 bo = device->ws->buffer_create(device->ws,
355 new_size, 4096,
356 RADEON_DOMAIN_GTT,
357 RADEON_FLAG_CPU_ACCESS|
358 RADEON_FLAG_NO_INTERPROCESS_SHARING |
359 RADEON_FLAG_32BIT);
360
361 if (!bo) {
362 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
363 return false;
364 }
365
366 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
367 if (cmd_buffer->upload.upload_bo) {
368 upload = malloc(sizeof(*upload));
369
370 if (!upload) {
371 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
372 device->ws->buffer_destroy(bo);
373 return false;
374 }
375
376 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
377 list_add(&upload->list, &cmd_buffer->upload.list);
378 }
379
380 cmd_buffer->upload.upload_bo = bo;
381 cmd_buffer->upload.size = new_size;
382 cmd_buffer->upload.offset = 0;
383 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
384
385 if (!cmd_buffer->upload.map) {
386 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
387 return false;
388 }
389
390 return true;
391 }
392
393 bool
394 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
395 unsigned size,
396 unsigned alignment,
397 unsigned *out_offset,
398 void **ptr)
399 {
400 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
401 if (offset + size > cmd_buffer->upload.size) {
402 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
403 return false;
404 offset = 0;
405 }
406
407 *out_offset = offset;
408 *ptr = cmd_buffer->upload.map + offset;
409
410 cmd_buffer->upload.offset = offset + size;
411 return true;
412 }
413
414 bool
415 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
416 unsigned size, unsigned alignment,
417 const void *data, unsigned *out_offset)
418 {
419 uint8_t *ptr;
420
421 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
422 out_offset, (void **)&ptr))
423 return false;
424
425 if (ptr)
426 memcpy(ptr, data, size);
427
428 return true;
429 }
430
431 static void
432 radv_emit_write_data_packet(struct radeon_cmdbuf *cs, uint64_t va,
433 unsigned count, const uint32_t *data)
434 {
435 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
436 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
437 S_370_WR_CONFIRM(1) |
438 S_370_ENGINE_SEL(V_370_ME));
439 radeon_emit(cs, va);
440 radeon_emit(cs, va >> 32);
441 radeon_emit_array(cs, data, count);
442 }
443
444 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
445 {
446 struct radv_device *device = cmd_buffer->device;
447 struct radeon_cmdbuf *cs = cmd_buffer->cs;
448 uint64_t va;
449
450 va = radv_buffer_get_va(device->trace_bo);
451 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
452 va += 4;
453
454 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
455
456 ++cmd_buffer->state.trace_id;
457 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
458 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
459 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
460 }
461
462 static void
463 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
464 enum radv_cmd_flush_bits flags)
465 {
466 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
467 uint32_t *ptr = NULL;
468 uint64_t va = 0;
469
470 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
471 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
472
473 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
474 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
475 cmd_buffer->gfx9_fence_offset;
476 ptr = &cmd_buffer->gfx9_fence_idx;
477 }
478
479 /* Force wait for graphics or compute engines to be idle. */
480 si_cs_emit_cache_flush(cmd_buffer->cs,
481 cmd_buffer->device->physical_device->rad_info.chip_class,
482 ptr, va,
483 radv_cmd_buffer_uses_mec(cmd_buffer),
484 flags, cmd_buffer->gfx9_eop_bug_va);
485 }
486
487 if (unlikely(cmd_buffer->device->trace_bo))
488 radv_cmd_buffer_trace_emit(cmd_buffer);
489 }
490
491 static void
492 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
493 struct radv_pipeline *pipeline, enum ring_type ring)
494 {
495 struct radv_device *device = cmd_buffer->device;
496 struct radeon_cmdbuf *cs = cmd_buffer->cs;
497 uint32_t data[2];
498 uint64_t va;
499
500 va = radv_buffer_get_va(device->trace_bo);
501
502 switch (ring) {
503 case RING_GFX:
504 va += 8;
505 break;
506 case RING_COMPUTE:
507 va += 16;
508 break;
509 default:
510 assert(!"invalid ring type");
511 }
512
513 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
514 cmd_buffer->cs, 6);
515
516 data[0] = (uintptr_t)pipeline;
517 data[1] = (uintptr_t)pipeline >> 32;
518
519 radv_emit_write_data_packet(cs, va, 2, data);
520 }
521
522 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
523 VkPipelineBindPoint bind_point,
524 struct radv_descriptor_set *set,
525 unsigned idx)
526 {
527 struct radv_descriptor_state *descriptors_state =
528 radv_get_descriptors_state(cmd_buffer, bind_point);
529
530 descriptors_state->sets[idx] = set;
531
532 descriptors_state->valid |= (1u << idx); /* active descriptors */
533 descriptors_state->dirty |= (1u << idx);
534 }
535
536 static void
537 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
538 VkPipelineBindPoint bind_point)
539 {
540 struct radv_descriptor_state *descriptors_state =
541 radv_get_descriptors_state(cmd_buffer, bind_point);
542 struct radv_device *device = cmd_buffer->device;
543 struct radeon_cmdbuf *cs = cmd_buffer->cs;
544 uint32_t data[MAX_SETS * 2] = {};
545 uint64_t va;
546 unsigned i;
547 va = radv_buffer_get_va(device->trace_bo) + 24;
548
549 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
550 cmd_buffer->cs, 4 + MAX_SETS * 2);
551
552 for_each_bit(i, descriptors_state->valid) {
553 struct radv_descriptor_set *set = descriptors_state->sets[i];
554 data[i * 2] = (uintptr_t)set;
555 data[i * 2 + 1] = (uintptr_t)set >> 32;
556 }
557
558 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
559 }
560
561 struct radv_userdata_info *
562 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
563 gl_shader_stage stage,
564 int idx)
565 {
566 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
567 return &shader->info.user_sgprs_locs.shader_data[idx];
568 }
569
570 static void
571 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
572 struct radv_pipeline *pipeline,
573 gl_shader_stage stage,
574 int idx, uint64_t va)
575 {
576 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
577 uint32_t base_reg = pipeline->user_data_0[stage];
578 if (loc->sgpr_idx == -1)
579 return;
580
581 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
582 assert(!loc->indirect);
583
584 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
585 base_reg + loc->sgpr_idx * 4, va, false);
586 }
587
588 static void
589 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
590 struct radv_pipeline *pipeline,
591 struct radv_descriptor_state *descriptors_state,
592 gl_shader_stage stage)
593 {
594 struct radv_device *device = cmd_buffer->device;
595 struct radeon_cmdbuf *cs = cmd_buffer->cs;
596 uint32_t sh_base = pipeline->user_data_0[stage];
597 struct radv_userdata_locations *locs =
598 &pipeline->shaders[stage]->info.user_sgprs_locs;
599 unsigned mask = locs->descriptor_sets_enabled;
600
601 mask &= descriptors_state->dirty & descriptors_state->valid;
602
603 while (mask) {
604 int start, count;
605
606 u_bit_scan_consecutive_range(&mask, &start, &count);
607
608 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
609 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
610
611 radv_emit_shader_pointer_head(cs, sh_offset, count,
612 HAVE_32BIT_POINTERS);
613 for (int i = 0; i < count; i++) {
614 struct radv_descriptor_set *set =
615 descriptors_state->sets[start + i];
616
617 radv_emit_shader_pointer_body(device, cs, set->va,
618 HAVE_32BIT_POINTERS);
619 }
620 }
621 }
622
623 static void
624 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
625 struct radv_pipeline *pipeline)
626 {
627 int num_samples = pipeline->graphics.ms.num_samples;
628 struct radv_multisample_state *ms = &pipeline->graphics.ms;
629 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
630
631 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
632 cmd_buffer->sample_positions_needed = true;
633
634 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
635 return;
636
637 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
638 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
639 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
640
641 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
642
643 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
644
645 /* GFX9: Flush DFSM when the AA mode changes. */
646 if (cmd_buffer->device->dfsm_allowed) {
647 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
648 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
649 }
650 }
651
652 static void
653 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
654 struct radv_shader_variant *shader)
655 {
656 uint64_t va;
657
658 if (!shader)
659 return;
660
661 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
662
663 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
664 }
665
666 static void
667 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
668 struct radv_pipeline *pipeline,
669 bool vertex_stage_only)
670 {
671 struct radv_cmd_state *state = &cmd_buffer->state;
672 uint32_t mask = state->prefetch_L2_mask;
673
674 if (vertex_stage_only) {
675 /* Fast prefetch path for starting draws as soon as possible.
676 */
677 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
678 RADV_PREFETCH_VBO_DESCRIPTORS);
679 }
680
681 if (mask & RADV_PREFETCH_VS)
682 radv_emit_shader_prefetch(cmd_buffer,
683 pipeline->shaders[MESA_SHADER_VERTEX]);
684
685 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
686 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
687
688 if (mask & RADV_PREFETCH_TCS)
689 radv_emit_shader_prefetch(cmd_buffer,
690 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
691
692 if (mask & RADV_PREFETCH_TES)
693 radv_emit_shader_prefetch(cmd_buffer,
694 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
695
696 if (mask & RADV_PREFETCH_GS) {
697 radv_emit_shader_prefetch(cmd_buffer,
698 pipeline->shaders[MESA_SHADER_GEOMETRY]);
699 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
700 }
701
702 if (mask & RADV_PREFETCH_PS)
703 radv_emit_shader_prefetch(cmd_buffer,
704 pipeline->shaders[MESA_SHADER_FRAGMENT]);
705
706 state->prefetch_L2_mask &= ~mask;
707 }
708
709 static void
710 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
711 {
712 if (!cmd_buffer->device->physical_device->rbplus_allowed)
713 return;
714
715 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
716 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
717 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
718
719 unsigned sx_ps_downconvert = 0;
720 unsigned sx_blend_opt_epsilon = 0;
721 unsigned sx_blend_opt_control = 0;
722
723 for (unsigned i = 0; i < subpass->color_count; ++i) {
724 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
725 continue;
726
727 int idx = subpass->color_attachments[i].attachment;
728 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
729
730 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
731 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
732 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
733 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
734
735 bool has_alpha, has_rgb;
736
737 /* Set if RGB and A are present. */
738 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
739
740 if (format == V_028C70_COLOR_8 ||
741 format == V_028C70_COLOR_16 ||
742 format == V_028C70_COLOR_32)
743 has_rgb = !has_alpha;
744 else
745 has_rgb = true;
746
747 /* Check the colormask and export format. */
748 if (!(colormask & 0x7))
749 has_rgb = false;
750 if (!(colormask & 0x8))
751 has_alpha = false;
752
753 if (spi_format == V_028714_SPI_SHADER_ZERO) {
754 has_rgb = false;
755 has_alpha = false;
756 }
757
758 /* Disable value checking for disabled channels. */
759 if (!has_rgb)
760 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
761 if (!has_alpha)
762 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
763
764 /* Enable down-conversion for 32bpp and smaller formats. */
765 switch (format) {
766 case V_028C70_COLOR_8:
767 case V_028C70_COLOR_8_8:
768 case V_028C70_COLOR_8_8_8_8:
769 /* For 1 and 2-channel formats, use the superset thereof. */
770 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
771 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
772 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
773 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
774 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
775 }
776 break;
777
778 case V_028C70_COLOR_5_6_5:
779 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
780 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
781 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
782 }
783 break;
784
785 case V_028C70_COLOR_1_5_5_5:
786 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
787 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
788 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
789 }
790 break;
791
792 case V_028C70_COLOR_4_4_4_4:
793 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
794 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
795 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
796 }
797 break;
798
799 case V_028C70_COLOR_32:
800 if (swap == V_028C70_SWAP_STD &&
801 spi_format == V_028714_SPI_SHADER_32_R)
802 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
803 else if (swap == V_028C70_SWAP_ALT_REV &&
804 spi_format == V_028714_SPI_SHADER_32_AR)
805 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
806 break;
807
808 case V_028C70_COLOR_16:
809 case V_028C70_COLOR_16_16:
810 /* For 1-channel formats, use the superset thereof. */
811 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
812 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
813 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
814 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
815 if (swap == V_028C70_SWAP_STD ||
816 swap == V_028C70_SWAP_STD_REV)
817 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
818 else
819 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
820 }
821 break;
822
823 case V_028C70_COLOR_10_11_11:
824 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
825 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
826 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
827 }
828 break;
829
830 case V_028C70_COLOR_2_10_10_10:
831 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
832 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
833 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
834 }
835 break;
836 }
837 }
838
839 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
840 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
841 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
842 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
843 }
844
845 static void
846 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
847 {
848 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
849
850 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
851 return;
852
853 radv_update_multisample_state(cmd_buffer, pipeline);
854
855 cmd_buffer->scratch_size_needed =
856 MAX2(cmd_buffer->scratch_size_needed,
857 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
858
859 if (!cmd_buffer->state.emitted_pipeline ||
860 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
861 pipeline->graphics.can_use_guardband)
862 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
863
864 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
865
866 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
867 if (!pipeline->shaders[i])
868 continue;
869
870 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
871 pipeline->shaders[i]->bo);
872 }
873
874 if (radv_pipeline_has_gs(pipeline))
875 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
876 pipeline->gs_copy_shader->bo);
877
878 if (unlikely(cmd_buffer->device->trace_bo))
879 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
880
881 cmd_buffer->state.emitted_pipeline = pipeline;
882
883 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
884 }
885
886 static void
887 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
888 {
889 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
890 cmd_buffer->state.dynamic.viewport.viewports);
891 }
892
893 static void
894 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
895 {
896 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
897
898 si_write_scissors(cmd_buffer->cs, 0, count,
899 cmd_buffer->state.dynamic.scissor.scissors,
900 cmd_buffer->state.dynamic.viewport.viewports,
901 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
902 }
903
904 static void
905 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
906 {
907 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
908 return;
909
910 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
911 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
912 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
913 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
914 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
915 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
916 S_028214_BR_Y(rect.offset.y + rect.extent.height));
917 }
918 }
919
920 static void
921 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
922 {
923 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
924
925 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
926 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
927 }
928
929 static void
930 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
931 {
932 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
933
934 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
935 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
936 }
937
938 static void
939 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
940 {
941 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
942
943 radeon_set_context_reg_seq(cmd_buffer->cs,
944 R_028430_DB_STENCILREFMASK, 2);
945 radeon_emit(cmd_buffer->cs,
946 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
947 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
948 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
949 S_028430_STENCILOPVAL(1));
950 radeon_emit(cmd_buffer->cs,
951 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
952 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
953 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
954 S_028434_STENCILOPVAL_BF(1));
955 }
956
957 static void
958 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
959 {
960 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
961
962 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
963 fui(d->depth_bounds.min));
964 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
965 fui(d->depth_bounds.max));
966 }
967
968 static void
969 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
970 {
971 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
972 unsigned slope = fui(d->depth_bias.slope * 16.0f);
973 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
974
975
976 radeon_set_context_reg_seq(cmd_buffer->cs,
977 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
978 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
979 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
980 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
981 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
982 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
983 }
984
985 static void
986 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
987 int index,
988 struct radv_attachment_info *att,
989 struct radv_image *image,
990 VkImageLayout layout)
991 {
992 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
993 struct radv_color_buffer_info *cb = &att->cb;
994 uint32_t cb_color_info = cb->cb_color_info;
995
996 if (!radv_layout_dcc_compressed(image, layout,
997 radv_image_queue_family_mask(image,
998 cmd_buffer->queue_family_index,
999 cmd_buffer->queue_family_index))) {
1000 cb_color_info &= C_028C70_DCC_ENABLE;
1001 }
1002
1003 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1004 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1005 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1006 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1007 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1008 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1009 radeon_emit(cmd_buffer->cs, cb_color_info);
1010 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1011 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1012 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1013 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1014 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1015 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1016
1017 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1018 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1019 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1020
1021 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1022 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1023 } else {
1024 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1025 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1026 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1027 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1028 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1029 radeon_emit(cmd_buffer->cs, cb_color_info);
1030 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1031 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1032 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1033 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1034 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1035 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1036
1037 if (is_vi) { /* DCC BASE */
1038 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1039 }
1040 }
1041 }
1042
1043 static void
1044 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1045 struct radv_ds_buffer_info *ds,
1046 struct radv_image *image, VkImageLayout layout,
1047 bool requires_cond_write)
1048 {
1049 uint32_t db_z_info = ds->db_z_info;
1050 uint32_t db_z_info_reg;
1051
1052 if (!radv_image_is_tc_compat_htile(image))
1053 return;
1054
1055 if (!radv_layout_has_htile(image, layout,
1056 radv_image_queue_family_mask(image,
1057 cmd_buffer->queue_family_index,
1058 cmd_buffer->queue_family_index))) {
1059 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1060 }
1061
1062 db_z_info &= C_028040_ZRANGE_PRECISION;
1063
1064 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1065 db_z_info_reg = R_028038_DB_Z_INFO;
1066 } else {
1067 db_z_info_reg = R_028040_DB_Z_INFO;
1068 }
1069
1070 /* When we don't know the last fast clear value we need to emit a
1071 * conditional packet, otherwise we can update DB_Z_INFO directly.
1072 */
1073 if (requires_cond_write) {
1074 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1075
1076 const uint32_t write_space = 0 << 8; /* register */
1077 const uint32_t poll_space = 1 << 4; /* memory */
1078 const uint32_t function = 3 << 0; /* equal to the reference */
1079 const uint32_t options = write_space | poll_space | function;
1080 radeon_emit(cmd_buffer->cs, options);
1081
1082 /* poll address - location of the depth clear value */
1083 uint64_t va = radv_buffer_get_va(image->bo);
1084 va += image->offset + image->clear_value_offset;
1085
1086 /* In presence of stencil format, we have to adjust the base
1087 * address because the first value is the stencil clear value.
1088 */
1089 if (vk_format_is_stencil(image->vk_format))
1090 va += 4;
1091
1092 radeon_emit(cmd_buffer->cs, va);
1093 radeon_emit(cmd_buffer->cs, va >> 32);
1094
1095 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1096 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1097 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1098 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1099 radeon_emit(cmd_buffer->cs, db_z_info);
1100 } else {
1101 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1102 }
1103 }
1104
1105 static void
1106 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1107 struct radv_ds_buffer_info *ds,
1108 struct radv_image *image,
1109 VkImageLayout layout)
1110 {
1111 uint32_t db_z_info = ds->db_z_info;
1112 uint32_t db_stencil_info = ds->db_stencil_info;
1113
1114 if (!radv_layout_has_htile(image, layout,
1115 radv_image_queue_family_mask(image,
1116 cmd_buffer->queue_family_index,
1117 cmd_buffer->queue_family_index))) {
1118 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1119 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1120 }
1121
1122 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1123 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1124
1125
1126 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1127 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1128 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1129 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1130 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1131
1132 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1133 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1134 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1135 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1136 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1137 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1138 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1139 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1140 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1141 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1142 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1143
1144 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1145 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1146 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1147 } else {
1148 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1149
1150 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1151 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1152 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1153 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1154 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1155 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1156 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1157 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1158 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1159 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1160
1161 }
1162
1163 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1164 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1165
1166 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1167 ds->pa_su_poly_offset_db_fmt_cntl);
1168 }
1169
1170 /**
1171 * Update the fast clear depth/stencil values if the image is bound as a
1172 * depth/stencil buffer.
1173 */
1174 static void
1175 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1176 struct radv_image *image,
1177 VkClearDepthStencilValue ds_clear_value,
1178 VkImageAspectFlags aspects)
1179 {
1180 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1181 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1182 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1183 struct radv_attachment_info *att;
1184 uint32_t att_idx;
1185
1186 if (!framebuffer || !subpass)
1187 return;
1188
1189 att_idx = subpass->depth_stencil_attachment.attachment;
1190 if (att_idx == VK_ATTACHMENT_UNUSED)
1191 return;
1192
1193 att = &framebuffer->attachments[att_idx];
1194 if (att->attachment->image != image)
1195 return;
1196
1197 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1198 radeon_emit(cs, ds_clear_value.stencil);
1199 radeon_emit(cs, fui(ds_clear_value.depth));
1200
1201 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1202 * only needed when clearing Z to 0.0.
1203 */
1204 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1205 ds_clear_value.depth == 0.0) {
1206 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1207
1208 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1209 layout, false);
1210 }
1211 }
1212
1213 /**
1214 * Set the clear depth/stencil values to the image's metadata.
1215 */
1216 static void
1217 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1218 struct radv_image *image,
1219 VkClearDepthStencilValue ds_clear_value,
1220 VkImageAspectFlags aspects)
1221 {
1222 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1223 uint64_t va = radv_buffer_get_va(image->bo);
1224 unsigned reg_offset = 0, reg_count = 0;
1225
1226 va += image->offset + image->clear_value_offset;
1227
1228 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1229 ++reg_count;
1230 } else {
1231 ++reg_offset;
1232 va += 4;
1233 }
1234 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1235 ++reg_count;
1236
1237 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1238 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1239 S_370_WR_CONFIRM(1) |
1240 S_370_ENGINE_SEL(V_370_PFP));
1241 radeon_emit(cs, va);
1242 radeon_emit(cs, va >> 32);
1243 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1244 radeon_emit(cs, ds_clear_value.stencil);
1245 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1246 radeon_emit(cs, fui(ds_clear_value.depth));
1247 }
1248
1249 /**
1250 * Update the clear depth/stencil values for this image.
1251 */
1252 void
1253 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1254 struct radv_image *image,
1255 VkClearDepthStencilValue ds_clear_value,
1256 VkImageAspectFlags aspects)
1257 {
1258 assert(radv_image_has_htile(image));
1259
1260 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1261
1262 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1263 aspects);
1264 }
1265
1266 /**
1267 * Load the clear depth/stencil values from the image's metadata.
1268 */
1269 static void
1270 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1271 struct radv_image *image)
1272 {
1273 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1274 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1275 uint64_t va = radv_buffer_get_va(image->bo);
1276 unsigned reg_offset = 0, reg_count = 0;
1277
1278 va += image->offset + image->clear_value_offset;
1279
1280 if (!radv_image_has_htile(image))
1281 return;
1282
1283 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1284 ++reg_count;
1285 } else {
1286 ++reg_offset;
1287 va += 4;
1288 }
1289 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1290 ++reg_count;
1291
1292 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1293 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1294 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1295 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1296 radeon_emit(cs, va);
1297 radeon_emit(cs, va >> 32);
1298 radeon_emit(cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1299 radeon_emit(cs, 0);
1300
1301 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1302 radeon_emit(cs, 0);
1303 }
1304
1305 /*
1306 * With DCC some colors don't require CMASK elimination before being
1307 * used as a texture. This sets a predicate value to determine if the
1308 * cmask eliminate is required.
1309 */
1310 void
1311 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1312 struct radv_image *image,
1313 bool value)
1314 {
1315 uint64_t pred_val = value;
1316 uint64_t va = radv_buffer_get_va(image->bo);
1317 va += image->offset + image->dcc_pred_offset;
1318
1319 assert(radv_image_has_dcc(image));
1320
1321 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1322 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1323 S_370_WR_CONFIRM(1) |
1324 S_370_ENGINE_SEL(V_370_PFP));
1325 radeon_emit(cmd_buffer->cs, va);
1326 radeon_emit(cmd_buffer->cs, va >> 32);
1327 radeon_emit(cmd_buffer->cs, pred_val);
1328 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1329 }
1330
1331 /**
1332 * Update the fast clear color values if the image is bound as a color buffer.
1333 */
1334 static void
1335 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1336 struct radv_image *image,
1337 int cb_idx,
1338 uint32_t color_values[2])
1339 {
1340 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1341 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1342 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1343 struct radv_attachment_info *att;
1344 uint32_t att_idx;
1345
1346 if (!framebuffer || !subpass)
1347 return;
1348
1349 att_idx = subpass->color_attachments[cb_idx].attachment;
1350 if (att_idx == VK_ATTACHMENT_UNUSED)
1351 return;
1352
1353 att = &framebuffer->attachments[att_idx];
1354 if (att->attachment->image != image)
1355 return;
1356
1357 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1358 radeon_emit(cs, color_values[0]);
1359 radeon_emit(cs, color_values[1]);
1360 }
1361
1362 /**
1363 * Set the clear color values to the image's metadata.
1364 */
1365 static void
1366 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1367 struct radv_image *image,
1368 uint32_t color_values[2])
1369 {
1370 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1371 uint64_t va = radv_buffer_get_va(image->bo);
1372
1373 va += image->offset + image->clear_value_offset;
1374
1375 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1376
1377 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1378 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1379 S_370_WR_CONFIRM(1) |
1380 S_370_ENGINE_SEL(V_370_PFP));
1381 radeon_emit(cs, va);
1382 radeon_emit(cs, va >> 32);
1383 radeon_emit(cs, color_values[0]);
1384 radeon_emit(cs, color_values[1]);
1385 }
1386
1387 /**
1388 * Update the clear color values for this image.
1389 */
1390 void
1391 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1392 struct radv_image *image,
1393 int cb_idx,
1394 uint32_t color_values[2])
1395 {
1396 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1397
1398 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1399
1400 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1401 color_values);
1402 }
1403
1404 /**
1405 * Load the clear color values from the image's metadata.
1406 */
1407 static void
1408 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1409 struct radv_image *image,
1410 int cb_idx)
1411 {
1412 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1413 uint64_t va = radv_buffer_get_va(image->bo);
1414
1415 va += image->offset + image->clear_value_offset;
1416
1417 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1418 return;
1419
1420 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1421
1422 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1423 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1424 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1425 COPY_DATA_COUNT_SEL);
1426 radeon_emit(cs, va);
1427 radeon_emit(cs, va >> 32);
1428 radeon_emit(cs, reg >> 2);
1429 radeon_emit(cs, 0);
1430
1431 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1432 radeon_emit(cs, 0);
1433 }
1434
1435 static void
1436 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1437 {
1438 int i;
1439 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1440 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1441
1442 /* this may happen for inherited secondary recording */
1443 if (!framebuffer)
1444 return;
1445
1446 for (i = 0; i < 8; ++i) {
1447 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1448 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1449 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1450 continue;
1451 }
1452
1453 int idx = subpass->color_attachments[i].attachment;
1454 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1455 struct radv_image *image = att->attachment->image;
1456 VkImageLayout layout = subpass->color_attachments[i].layout;
1457
1458 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1459
1460 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1461 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1462
1463 radv_load_color_clear_metadata(cmd_buffer, image, i);
1464 }
1465
1466 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1467 int idx = subpass->depth_stencil_attachment.attachment;
1468 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1469 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1470 struct radv_image *image = att->attachment->image;
1471 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1472 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1473 cmd_buffer->queue_family_index,
1474 cmd_buffer->queue_family_index);
1475 /* We currently don't support writing decompressed HTILE */
1476 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1477 radv_layout_is_htile_compressed(image, layout, queue_mask));
1478
1479 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1480
1481 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1482 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1483 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1484 }
1485 radv_load_ds_clear_metadata(cmd_buffer, image);
1486 } else {
1487 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1488 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1489 else
1490 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1491
1492 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1493 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1494 }
1495 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1496 S_028208_BR_X(framebuffer->width) |
1497 S_028208_BR_Y(framebuffer->height));
1498
1499 if (cmd_buffer->device->dfsm_allowed) {
1500 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1501 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1502 }
1503
1504 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1505 }
1506
1507 static void
1508 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1509 {
1510 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1511 struct radv_cmd_state *state = &cmd_buffer->state;
1512
1513 if (state->index_type != state->last_index_type) {
1514 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1515 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1516 2, state->index_type);
1517 } else {
1518 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1519 radeon_emit(cs, state->index_type);
1520 }
1521
1522 state->last_index_type = state->index_type;
1523 }
1524
1525 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1526 radeon_emit(cs, state->index_va);
1527 radeon_emit(cs, state->index_va >> 32);
1528
1529 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1530 radeon_emit(cs, state->max_index_count);
1531
1532 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1533 }
1534
1535 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1536 {
1537 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1538 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1539 uint32_t pa_sc_mode_cntl_1 =
1540 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1541 uint32_t db_count_control;
1542
1543 if(!cmd_buffer->state.active_occlusion_queries) {
1544 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1545 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1546 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1547 has_perfect_queries) {
1548 /* Re-enable out-of-order rasterization if the
1549 * bound pipeline supports it and if it's has
1550 * been disabled before starting any perfect
1551 * occlusion queries.
1552 */
1553 radeon_set_context_reg(cmd_buffer->cs,
1554 R_028A4C_PA_SC_MODE_CNTL_1,
1555 pa_sc_mode_cntl_1);
1556 }
1557 db_count_control = 0;
1558 } else {
1559 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1560 }
1561 } else {
1562 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1563 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1564
1565 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1566 db_count_control =
1567 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1568 S_028004_SAMPLE_RATE(sample_rate) |
1569 S_028004_ZPASS_ENABLE(1) |
1570 S_028004_SLICE_EVEN_ENABLE(1) |
1571 S_028004_SLICE_ODD_ENABLE(1);
1572
1573 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1574 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1575 has_perfect_queries) {
1576 /* If the bound pipeline has enabled
1577 * out-of-order rasterization, we should
1578 * disable it before starting any perfect
1579 * occlusion queries.
1580 */
1581 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1582
1583 radeon_set_context_reg(cmd_buffer->cs,
1584 R_028A4C_PA_SC_MODE_CNTL_1,
1585 pa_sc_mode_cntl_1);
1586 }
1587 } else {
1588 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1589 S_028004_SAMPLE_RATE(sample_rate);
1590 }
1591 }
1592
1593 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1594 }
1595
1596 static void
1597 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1598 {
1599 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1600
1601 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1602 radv_emit_viewport(cmd_buffer);
1603
1604 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1605 !cmd_buffer->device->physical_device->has_scissor_bug)
1606 radv_emit_scissor(cmd_buffer);
1607
1608 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1609 radv_emit_line_width(cmd_buffer);
1610
1611 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1612 radv_emit_blend_constants(cmd_buffer);
1613
1614 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1615 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1616 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1617 radv_emit_stencil(cmd_buffer);
1618
1619 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1620 radv_emit_depth_bounds(cmd_buffer);
1621
1622 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1623 radv_emit_depth_bias(cmd_buffer);
1624
1625 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1626 radv_emit_discard_rectangle(cmd_buffer);
1627
1628 cmd_buffer->state.dirty &= ~states;
1629 }
1630
1631 static void
1632 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1633 VkPipelineBindPoint bind_point)
1634 {
1635 struct radv_descriptor_state *descriptors_state =
1636 radv_get_descriptors_state(cmd_buffer, bind_point);
1637 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1638 unsigned bo_offset;
1639
1640 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1641 set->mapped_ptr,
1642 &bo_offset))
1643 return;
1644
1645 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1646 set->va += bo_offset;
1647 }
1648
1649 static void
1650 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1651 VkPipelineBindPoint bind_point)
1652 {
1653 struct radv_descriptor_state *descriptors_state =
1654 radv_get_descriptors_state(cmd_buffer, bind_point);
1655 uint32_t size = MAX_SETS * 2 * 4;
1656 uint32_t offset;
1657 void *ptr;
1658
1659 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1660 256, &offset, &ptr))
1661 return;
1662
1663 for (unsigned i = 0; i < MAX_SETS; i++) {
1664 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1665 uint64_t set_va = 0;
1666 struct radv_descriptor_set *set = descriptors_state->sets[i];
1667 if (descriptors_state->valid & (1u << i))
1668 set_va = set->va;
1669 uptr[0] = set_va & 0xffffffff;
1670 uptr[1] = set_va >> 32;
1671 }
1672
1673 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1674 va += offset;
1675
1676 if (cmd_buffer->state.pipeline) {
1677 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1678 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1679 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1680
1681 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1682 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1683 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1684
1685 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1686 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1687 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1688
1689 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1690 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1691 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1692
1693 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1694 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1695 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1696 }
1697
1698 if (cmd_buffer->state.compute_pipeline)
1699 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1700 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1701 }
1702
1703 static void
1704 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1705 VkShaderStageFlags stages)
1706 {
1707 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1708 VK_PIPELINE_BIND_POINT_COMPUTE :
1709 VK_PIPELINE_BIND_POINT_GRAPHICS;
1710 struct radv_descriptor_state *descriptors_state =
1711 radv_get_descriptors_state(cmd_buffer, bind_point);
1712
1713 if (!descriptors_state->dirty)
1714 return;
1715
1716 if (descriptors_state->push_dirty)
1717 radv_flush_push_descriptors(cmd_buffer, bind_point);
1718
1719 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1720 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1721 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1722 }
1723
1724 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1725 cmd_buffer->cs,
1726 MAX_SETS * MESA_SHADER_STAGES * 4);
1727
1728 if (cmd_buffer->state.pipeline) {
1729 radv_foreach_stage(stage, stages) {
1730 if (!cmd_buffer->state.pipeline->shaders[stage])
1731 continue;
1732
1733 radv_emit_descriptor_pointers(cmd_buffer,
1734 cmd_buffer->state.pipeline,
1735 descriptors_state, stage);
1736 }
1737 }
1738
1739 if (cmd_buffer->state.compute_pipeline &&
1740 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1741 radv_emit_descriptor_pointers(cmd_buffer,
1742 cmd_buffer->state.compute_pipeline,
1743 descriptors_state,
1744 MESA_SHADER_COMPUTE);
1745 }
1746
1747 descriptors_state->dirty = 0;
1748 descriptors_state->push_dirty = false;
1749
1750 if (unlikely(cmd_buffer->device->trace_bo))
1751 radv_save_descriptors(cmd_buffer, bind_point);
1752
1753 assert(cmd_buffer->cs->cdw <= cdw_max);
1754 }
1755
1756 static void
1757 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1758 VkShaderStageFlags stages)
1759 {
1760 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1761 ? cmd_buffer->state.compute_pipeline
1762 : cmd_buffer->state.pipeline;
1763 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1764 VK_PIPELINE_BIND_POINT_COMPUTE :
1765 VK_PIPELINE_BIND_POINT_GRAPHICS;
1766 struct radv_descriptor_state *descriptors_state =
1767 radv_get_descriptors_state(cmd_buffer, bind_point);
1768 struct radv_pipeline_layout *layout = pipeline->layout;
1769 struct radv_shader_variant *shader, *prev_shader;
1770 unsigned offset;
1771 void *ptr;
1772 uint64_t va;
1773
1774 stages &= cmd_buffer->push_constant_stages;
1775 if (!stages ||
1776 (!layout->push_constant_size && !layout->dynamic_offset_count))
1777 return;
1778
1779 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1780 16 * layout->dynamic_offset_count,
1781 256, &offset, &ptr))
1782 return;
1783
1784 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1785 memcpy((char*)ptr + layout->push_constant_size,
1786 descriptors_state->dynamic_buffers,
1787 16 * layout->dynamic_offset_count);
1788
1789 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1790 va += offset;
1791
1792 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1793 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1794
1795 prev_shader = NULL;
1796 radv_foreach_stage(stage, stages) {
1797 shader = radv_get_shader(pipeline, stage);
1798
1799 /* Avoid redundantly emitting the address for merged stages. */
1800 if (shader && shader != prev_shader) {
1801 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1802 AC_UD_PUSH_CONSTANTS, va);
1803
1804 prev_shader = shader;
1805 }
1806 }
1807
1808 cmd_buffer->push_constant_stages &= ~stages;
1809 assert(cmd_buffer->cs->cdw <= cdw_max);
1810 }
1811
1812 static void
1813 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1814 bool pipeline_is_dirty)
1815 {
1816 if ((pipeline_is_dirty ||
1817 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1818 cmd_buffer->state.pipeline->vertex_elements.count &&
1819 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1820 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1821 unsigned vb_offset;
1822 void *vb_ptr;
1823 uint32_t i = 0;
1824 uint32_t count = velems->count;
1825 uint64_t va;
1826
1827 /* allocate some descriptor state for vertex buffers */
1828 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1829 &vb_offset, &vb_ptr))
1830 return;
1831
1832 for (i = 0; i < count; i++) {
1833 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1834 uint32_t offset;
1835 int vb = velems->binding[i];
1836 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1837 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1838
1839 va = radv_buffer_get_va(buffer->bo);
1840
1841 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1842 va += offset + buffer->offset;
1843 desc[0] = va;
1844 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1845 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1846 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1847 else
1848 desc[2] = buffer->size - offset;
1849 desc[3] = velems->rsrc_word3[i];
1850 }
1851
1852 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1853 va += vb_offset;
1854
1855 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1856 AC_UD_VS_VERTEX_BUFFERS, va);
1857
1858 cmd_buffer->state.vb_va = va;
1859 cmd_buffer->state.vb_size = count * 16;
1860 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1861 }
1862 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1863 }
1864
1865 static void
1866 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1867 {
1868 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1869 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1870 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1871 }
1872
1873 static void
1874 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1875 bool instanced_draw, bool indirect_draw,
1876 uint32_t draw_vertex_count)
1877 {
1878 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1879 struct radv_cmd_state *state = &cmd_buffer->state;
1880 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1881 uint32_t ia_multi_vgt_param;
1882 int32_t primitive_reset_en;
1883
1884 /* Draw state. */
1885 ia_multi_vgt_param =
1886 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1887 indirect_draw, draw_vertex_count);
1888
1889 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1890 if (info->chip_class >= GFX9) {
1891 radeon_set_uconfig_reg_idx(cs,
1892 R_030960_IA_MULTI_VGT_PARAM,
1893 4, ia_multi_vgt_param);
1894 } else if (info->chip_class >= CIK) {
1895 radeon_set_context_reg_idx(cs,
1896 R_028AA8_IA_MULTI_VGT_PARAM,
1897 1, ia_multi_vgt_param);
1898 } else {
1899 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1900 ia_multi_vgt_param);
1901 }
1902 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1903 }
1904
1905 /* Primitive restart. */
1906 primitive_reset_en =
1907 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1908
1909 if (primitive_reset_en != state->last_primitive_reset_en) {
1910 state->last_primitive_reset_en = primitive_reset_en;
1911 if (info->chip_class >= GFX9) {
1912 radeon_set_uconfig_reg(cs,
1913 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1914 primitive_reset_en);
1915 } else {
1916 radeon_set_context_reg(cs,
1917 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1918 primitive_reset_en);
1919 }
1920 }
1921
1922 if (primitive_reset_en) {
1923 uint32_t primitive_reset_index =
1924 state->index_type ? 0xffffffffu : 0xffffu;
1925
1926 if (primitive_reset_index != state->last_primitive_reset_index) {
1927 radeon_set_context_reg(cs,
1928 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1929 primitive_reset_index);
1930 state->last_primitive_reset_index = primitive_reset_index;
1931 }
1932 }
1933 }
1934
1935 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1936 VkPipelineStageFlags src_stage_mask)
1937 {
1938 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1939 VK_PIPELINE_STAGE_TRANSFER_BIT |
1940 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1941 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1942 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1943 }
1944
1945 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1946 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1947 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1948 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1949 VK_PIPELINE_STAGE_TRANSFER_BIT |
1950 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1951 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1952 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1953 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1954 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1955 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1956 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
1957 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1958 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1959 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT)) {
1960 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1961 }
1962 }
1963
1964 static enum radv_cmd_flush_bits
1965 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1966 VkAccessFlags src_flags,
1967 struct radv_image *image)
1968 {
1969 bool flush_CB_meta = true, flush_DB_meta = true;
1970 enum radv_cmd_flush_bits flush_bits = 0;
1971 uint32_t b;
1972
1973 if (image && !radv_image_has_CB_metadata(image))
1974 flush_CB_meta = false;
1975 if (image && !radv_image_has_htile(image))
1976 flush_DB_meta = false;
1977
1978 for_each_bit(b, src_flags) {
1979 switch ((VkAccessFlagBits)(1 << b)) {
1980 case VK_ACCESS_SHADER_WRITE_BIT:
1981 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1982 break;
1983 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1984 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
1985 if (flush_CB_meta)
1986 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1987 break;
1988 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1989 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
1990 if (flush_DB_meta)
1991 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1992 break;
1993 case VK_ACCESS_TRANSFER_WRITE_BIT:
1994 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1995 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1996 RADV_CMD_FLAG_INV_GLOBAL_L2;
1997
1998 if (flush_CB_meta)
1999 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2000 if (flush_DB_meta)
2001 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2002 break;
2003 default:
2004 break;
2005 }
2006 }
2007 return flush_bits;
2008 }
2009
2010 static enum radv_cmd_flush_bits
2011 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2012 VkAccessFlags dst_flags,
2013 struct radv_image *image)
2014 {
2015 enum radv_cmd_flush_bits flush_bits = 0;
2016 uint32_t b;
2017 for_each_bit(b, dst_flags) {
2018 switch ((VkAccessFlagBits)(1 << b)) {
2019 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2020 case VK_ACCESS_INDEX_READ_BIT:
2021 break;
2022 case VK_ACCESS_UNIFORM_READ_BIT:
2023 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2024 break;
2025 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2026 case VK_ACCESS_SHADER_READ_BIT:
2027 case VK_ACCESS_TRANSFER_READ_BIT:
2028 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2029 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2030 RADV_CMD_FLAG_INV_GLOBAL_L2;
2031 break;
2032 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2033 /* TODO: change to image && when the image gets passed
2034 * through from the subpass. */
2035 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2036 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2037 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2038 break;
2039 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2040 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2041 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2042 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2043 break;
2044 default:
2045 break;
2046 }
2047 }
2048 return flush_bits;
2049 }
2050
2051 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2052 {
2053 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2054 NULL);
2055 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2056 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2057 NULL);
2058 }
2059
2060 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2061 struct radv_subpass_attachment att)
2062 {
2063 unsigned idx = att.attachment;
2064 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2065 VkImageSubresourceRange range;
2066 range.aspectMask = 0;
2067 range.baseMipLevel = view->base_mip;
2068 range.levelCount = 1;
2069 range.baseArrayLayer = view->base_layer;
2070 range.layerCount = cmd_buffer->state.framebuffer->layers;
2071
2072 radv_handle_image_transition(cmd_buffer,
2073 view->image,
2074 cmd_buffer->state.attachments[idx].current_layout,
2075 att.layout, 0, 0, &range,
2076 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2077
2078 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2079
2080
2081 }
2082
2083 void
2084 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2085 const struct radv_subpass *subpass, bool transitions)
2086 {
2087 if (transitions) {
2088 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2089
2090 for (unsigned i = 0; i < subpass->color_count; ++i) {
2091 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2092 radv_handle_subpass_image_transition(cmd_buffer,
2093 subpass->color_attachments[i]);
2094 }
2095
2096 for (unsigned i = 0; i < subpass->input_count; ++i) {
2097 radv_handle_subpass_image_transition(cmd_buffer,
2098 subpass->input_attachments[i]);
2099 }
2100
2101 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2102 radv_handle_subpass_image_transition(cmd_buffer,
2103 subpass->depth_stencil_attachment);
2104 }
2105 }
2106
2107 cmd_buffer->state.subpass = subpass;
2108
2109 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2110 }
2111
2112 static VkResult
2113 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2114 struct radv_render_pass *pass,
2115 const VkRenderPassBeginInfo *info)
2116 {
2117 struct radv_cmd_state *state = &cmd_buffer->state;
2118
2119 if (pass->attachment_count == 0) {
2120 state->attachments = NULL;
2121 return VK_SUCCESS;
2122 }
2123
2124 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2125 pass->attachment_count *
2126 sizeof(state->attachments[0]),
2127 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2128 if (state->attachments == NULL) {
2129 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2130 return cmd_buffer->record_result;
2131 }
2132
2133 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2134 struct radv_render_pass_attachment *att = &pass->attachments[i];
2135 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2136 VkImageAspectFlags clear_aspects = 0;
2137
2138 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2139 /* color attachment */
2140 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2141 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2142 }
2143 } else {
2144 /* depthstencil attachment */
2145 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2146 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2147 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2148 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2149 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2150 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2151 }
2152 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2153 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2154 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2155 }
2156 }
2157
2158 state->attachments[i].pending_clear_aspects = clear_aspects;
2159 state->attachments[i].cleared_views = 0;
2160 if (clear_aspects && info) {
2161 assert(info->clearValueCount > i);
2162 state->attachments[i].clear_value = info->pClearValues[i];
2163 }
2164
2165 state->attachments[i].current_layout = att->initial_layout;
2166 }
2167
2168 return VK_SUCCESS;
2169 }
2170
2171 VkResult radv_AllocateCommandBuffers(
2172 VkDevice _device,
2173 const VkCommandBufferAllocateInfo *pAllocateInfo,
2174 VkCommandBuffer *pCommandBuffers)
2175 {
2176 RADV_FROM_HANDLE(radv_device, device, _device);
2177 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2178
2179 VkResult result = VK_SUCCESS;
2180 uint32_t i;
2181
2182 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2183
2184 if (!list_empty(&pool->free_cmd_buffers)) {
2185 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2186
2187 list_del(&cmd_buffer->pool_link);
2188 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2189
2190 result = radv_reset_cmd_buffer(cmd_buffer);
2191 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2192 cmd_buffer->level = pAllocateInfo->level;
2193
2194 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2195 } else {
2196 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2197 &pCommandBuffers[i]);
2198 }
2199 if (result != VK_SUCCESS)
2200 break;
2201 }
2202
2203 if (result != VK_SUCCESS) {
2204 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2205 i, pCommandBuffers);
2206
2207 /* From the Vulkan 1.0.66 spec:
2208 *
2209 * "vkAllocateCommandBuffers can be used to create multiple
2210 * command buffers. If the creation of any of those command
2211 * buffers fails, the implementation must destroy all
2212 * successfully created command buffer objects from this
2213 * command, set all entries of the pCommandBuffers array to
2214 * NULL and return the error."
2215 */
2216 memset(pCommandBuffers, 0,
2217 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2218 }
2219
2220 return result;
2221 }
2222
2223 void radv_FreeCommandBuffers(
2224 VkDevice device,
2225 VkCommandPool commandPool,
2226 uint32_t commandBufferCount,
2227 const VkCommandBuffer *pCommandBuffers)
2228 {
2229 for (uint32_t i = 0; i < commandBufferCount; i++) {
2230 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2231
2232 if (cmd_buffer) {
2233 if (cmd_buffer->pool) {
2234 list_del(&cmd_buffer->pool_link);
2235 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2236 } else
2237 radv_cmd_buffer_destroy(cmd_buffer);
2238
2239 }
2240 }
2241 }
2242
2243 VkResult radv_ResetCommandBuffer(
2244 VkCommandBuffer commandBuffer,
2245 VkCommandBufferResetFlags flags)
2246 {
2247 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2248 return radv_reset_cmd_buffer(cmd_buffer);
2249 }
2250
2251 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2252 {
2253 struct radv_device *device = cmd_buffer->device;
2254 if (device->gfx_init) {
2255 uint64_t va = radv_buffer_get_va(device->gfx_init);
2256 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init);
2257 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2258 radeon_emit(cmd_buffer->cs, va);
2259 radeon_emit(cmd_buffer->cs, va >> 32);
2260 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2261 } else
2262 si_init_config(cmd_buffer);
2263 }
2264
2265 VkResult radv_BeginCommandBuffer(
2266 VkCommandBuffer commandBuffer,
2267 const VkCommandBufferBeginInfo *pBeginInfo)
2268 {
2269 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2270 VkResult result = VK_SUCCESS;
2271
2272 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2273 /* If the command buffer has already been resetted with
2274 * vkResetCommandBuffer, no need to do it again.
2275 */
2276 result = radv_reset_cmd_buffer(cmd_buffer);
2277 if (result != VK_SUCCESS)
2278 return result;
2279 }
2280
2281 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2282 cmd_buffer->state.last_primitive_reset_en = -1;
2283 cmd_buffer->state.last_index_type = -1;
2284 cmd_buffer->state.last_num_instances = -1;
2285 cmd_buffer->state.last_vertex_offset = -1;
2286 cmd_buffer->state.last_first_instance = -1;
2287 cmd_buffer->usage_flags = pBeginInfo->flags;
2288
2289 /* setup initial configuration into command buffer */
2290 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2291 switch (cmd_buffer->queue_family_index) {
2292 case RADV_QUEUE_GENERAL:
2293 emit_gfx_buffer_state(cmd_buffer);
2294 break;
2295 case RADV_QUEUE_COMPUTE:
2296 si_init_compute(cmd_buffer);
2297 break;
2298 case RADV_QUEUE_TRANSFER:
2299 default:
2300 break;
2301 }
2302 }
2303
2304 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2305 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2306 assert(pBeginInfo->pInheritanceInfo);
2307 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2308 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2309
2310 struct radv_subpass *subpass =
2311 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2312
2313 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2314 if (result != VK_SUCCESS)
2315 return result;
2316
2317 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2318 }
2319
2320 if (unlikely(cmd_buffer->device->trace_bo)) {
2321 struct radv_device *device = cmd_buffer->device;
2322
2323 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2324 device->trace_bo);
2325
2326 radv_cmd_buffer_trace_emit(cmd_buffer);
2327 }
2328
2329 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2330
2331 return result;
2332 }
2333
2334 void radv_CmdBindVertexBuffers(
2335 VkCommandBuffer commandBuffer,
2336 uint32_t firstBinding,
2337 uint32_t bindingCount,
2338 const VkBuffer* pBuffers,
2339 const VkDeviceSize* pOffsets)
2340 {
2341 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2342 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2343 bool changed = false;
2344
2345 /* We have to defer setting up vertex buffer since we need the buffer
2346 * stride from the pipeline. */
2347
2348 assert(firstBinding + bindingCount <= MAX_VBS);
2349 for (uint32_t i = 0; i < bindingCount; i++) {
2350 uint32_t idx = firstBinding + i;
2351
2352 if (!changed &&
2353 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2354 vb[idx].offset != pOffsets[i])) {
2355 changed = true;
2356 }
2357
2358 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2359 vb[idx].offset = pOffsets[i];
2360
2361 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2362 vb[idx].buffer->bo);
2363 }
2364
2365 if (!changed) {
2366 /* No state changes. */
2367 return;
2368 }
2369
2370 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2371 }
2372
2373 void radv_CmdBindIndexBuffer(
2374 VkCommandBuffer commandBuffer,
2375 VkBuffer buffer,
2376 VkDeviceSize offset,
2377 VkIndexType indexType)
2378 {
2379 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2380 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2381
2382 if (cmd_buffer->state.index_buffer == index_buffer &&
2383 cmd_buffer->state.index_offset == offset &&
2384 cmd_buffer->state.index_type == indexType) {
2385 /* No state changes. */
2386 return;
2387 }
2388
2389 cmd_buffer->state.index_buffer = index_buffer;
2390 cmd_buffer->state.index_offset = offset;
2391 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2392 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2393 cmd_buffer->state.index_va += index_buffer->offset + offset;
2394
2395 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2396 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2397 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2398 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2399 }
2400
2401
2402 static void
2403 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2404 VkPipelineBindPoint bind_point,
2405 struct radv_descriptor_set *set, unsigned idx)
2406 {
2407 struct radeon_winsys *ws = cmd_buffer->device->ws;
2408
2409 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2410
2411 assert(set);
2412 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2413
2414 if (!cmd_buffer->device->use_global_bo_list) {
2415 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2416 if (set->descriptors[j])
2417 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2418 }
2419
2420 if(set->bo)
2421 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2422 }
2423
2424 void radv_CmdBindDescriptorSets(
2425 VkCommandBuffer commandBuffer,
2426 VkPipelineBindPoint pipelineBindPoint,
2427 VkPipelineLayout _layout,
2428 uint32_t firstSet,
2429 uint32_t descriptorSetCount,
2430 const VkDescriptorSet* pDescriptorSets,
2431 uint32_t dynamicOffsetCount,
2432 const uint32_t* pDynamicOffsets)
2433 {
2434 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2435 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2436 unsigned dyn_idx = 0;
2437
2438 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2439 struct radv_descriptor_state *descriptors_state =
2440 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2441
2442 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2443 unsigned idx = i + firstSet;
2444 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2445 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2446
2447 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2448 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2449 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2450 assert(dyn_idx < dynamicOffsetCount);
2451
2452 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2453 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2454 dst[0] = va;
2455 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2456 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2457 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2458 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2459 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2460 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2461 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2462 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2463 cmd_buffer->push_constant_stages |=
2464 set->layout->dynamic_shader_stages;
2465 }
2466 }
2467 }
2468
2469 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2470 struct radv_descriptor_set *set,
2471 struct radv_descriptor_set_layout *layout,
2472 VkPipelineBindPoint bind_point)
2473 {
2474 struct radv_descriptor_state *descriptors_state =
2475 radv_get_descriptors_state(cmd_buffer, bind_point);
2476 set->size = layout->size;
2477 set->layout = layout;
2478
2479 if (descriptors_state->push_set.capacity < set->size) {
2480 size_t new_size = MAX2(set->size, 1024);
2481 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2482 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2483
2484 free(set->mapped_ptr);
2485 set->mapped_ptr = malloc(new_size);
2486
2487 if (!set->mapped_ptr) {
2488 descriptors_state->push_set.capacity = 0;
2489 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2490 return false;
2491 }
2492
2493 descriptors_state->push_set.capacity = new_size;
2494 }
2495
2496 return true;
2497 }
2498
2499 void radv_meta_push_descriptor_set(
2500 struct radv_cmd_buffer* cmd_buffer,
2501 VkPipelineBindPoint pipelineBindPoint,
2502 VkPipelineLayout _layout,
2503 uint32_t set,
2504 uint32_t descriptorWriteCount,
2505 const VkWriteDescriptorSet* pDescriptorWrites)
2506 {
2507 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2508 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2509 unsigned bo_offset;
2510
2511 assert(set == 0);
2512 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2513
2514 push_set->size = layout->set[set].layout->size;
2515 push_set->layout = layout->set[set].layout;
2516
2517 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2518 &bo_offset,
2519 (void**) &push_set->mapped_ptr))
2520 return;
2521
2522 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2523 push_set->va += bo_offset;
2524
2525 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2526 radv_descriptor_set_to_handle(push_set),
2527 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2528
2529 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2530 }
2531
2532 void radv_CmdPushDescriptorSetKHR(
2533 VkCommandBuffer commandBuffer,
2534 VkPipelineBindPoint pipelineBindPoint,
2535 VkPipelineLayout _layout,
2536 uint32_t set,
2537 uint32_t descriptorWriteCount,
2538 const VkWriteDescriptorSet* pDescriptorWrites)
2539 {
2540 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2541 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2542 struct radv_descriptor_state *descriptors_state =
2543 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2544 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2545
2546 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2547
2548 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2549 layout->set[set].layout,
2550 pipelineBindPoint))
2551 return;
2552
2553 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2554 radv_descriptor_set_to_handle(push_set),
2555 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2556
2557 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2558 descriptors_state->push_dirty = true;
2559 }
2560
2561 void radv_CmdPushDescriptorSetWithTemplateKHR(
2562 VkCommandBuffer commandBuffer,
2563 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2564 VkPipelineLayout _layout,
2565 uint32_t set,
2566 const void* pData)
2567 {
2568 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2569 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2570 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2571 struct radv_descriptor_state *descriptors_state =
2572 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2573 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2574
2575 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2576
2577 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2578 layout->set[set].layout,
2579 templ->bind_point))
2580 return;
2581
2582 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2583 descriptorUpdateTemplate, pData);
2584
2585 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2586 descriptors_state->push_dirty = true;
2587 }
2588
2589 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2590 VkPipelineLayout layout,
2591 VkShaderStageFlags stageFlags,
2592 uint32_t offset,
2593 uint32_t size,
2594 const void* pValues)
2595 {
2596 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2597 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2598 cmd_buffer->push_constant_stages |= stageFlags;
2599 }
2600
2601 VkResult radv_EndCommandBuffer(
2602 VkCommandBuffer commandBuffer)
2603 {
2604 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2605
2606 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2607 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2608 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2609 si_emit_cache_flush(cmd_buffer);
2610 }
2611
2612 /* Make sure CP DMA is idle at the end of IBs because the kernel
2613 * doesn't wait for it.
2614 */
2615 si_cp_dma_wait_for_idle(cmd_buffer);
2616
2617 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2618
2619 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2620 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2621
2622 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2623
2624 return cmd_buffer->record_result;
2625 }
2626
2627 static void
2628 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2629 {
2630 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2631
2632 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2633 return;
2634
2635 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2636
2637 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2638 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2639
2640 cmd_buffer->compute_scratch_size_needed =
2641 MAX2(cmd_buffer->compute_scratch_size_needed,
2642 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2643
2644 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2645 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2646
2647 if (unlikely(cmd_buffer->device->trace_bo))
2648 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2649 }
2650
2651 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2652 VkPipelineBindPoint bind_point)
2653 {
2654 struct radv_descriptor_state *descriptors_state =
2655 radv_get_descriptors_state(cmd_buffer, bind_point);
2656
2657 descriptors_state->dirty |= descriptors_state->valid;
2658 }
2659
2660 void radv_CmdBindPipeline(
2661 VkCommandBuffer commandBuffer,
2662 VkPipelineBindPoint pipelineBindPoint,
2663 VkPipeline _pipeline)
2664 {
2665 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2666 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2667
2668 switch (pipelineBindPoint) {
2669 case VK_PIPELINE_BIND_POINT_COMPUTE:
2670 if (cmd_buffer->state.compute_pipeline == pipeline)
2671 return;
2672 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2673
2674 cmd_buffer->state.compute_pipeline = pipeline;
2675 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2676 break;
2677 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2678 if (cmd_buffer->state.pipeline == pipeline)
2679 return;
2680 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2681
2682 cmd_buffer->state.pipeline = pipeline;
2683 if (!pipeline)
2684 break;
2685
2686 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2687 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2688
2689 /* the new vertex shader might not have the same user regs */
2690 cmd_buffer->state.last_first_instance = -1;
2691 cmd_buffer->state.last_vertex_offset = -1;
2692
2693 /* Prefetch all pipeline shaders at first draw time. */
2694 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2695
2696 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2697
2698 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2699 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2700 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2701 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2702
2703 if (radv_pipeline_has_tess(pipeline))
2704 cmd_buffer->tess_rings_needed = true;
2705 break;
2706 default:
2707 assert(!"invalid bind point");
2708 break;
2709 }
2710 }
2711
2712 void radv_CmdSetViewport(
2713 VkCommandBuffer commandBuffer,
2714 uint32_t firstViewport,
2715 uint32_t viewportCount,
2716 const VkViewport* pViewports)
2717 {
2718 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2719 struct radv_cmd_state *state = &cmd_buffer->state;
2720 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2721
2722 assert(firstViewport < MAX_VIEWPORTS);
2723 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2724
2725 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2726 viewportCount * sizeof(*pViewports));
2727
2728 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2729 }
2730
2731 void radv_CmdSetScissor(
2732 VkCommandBuffer commandBuffer,
2733 uint32_t firstScissor,
2734 uint32_t scissorCount,
2735 const VkRect2D* pScissors)
2736 {
2737 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2738 struct radv_cmd_state *state = &cmd_buffer->state;
2739 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2740
2741 assert(firstScissor < MAX_SCISSORS);
2742 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2743
2744 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2745 scissorCount * sizeof(*pScissors));
2746
2747 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2748 }
2749
2750 void radv_CmdSetLineWidth(
2751 VkCommandBuffer commandBuffer,
2752 float lineWidth)
2753 {
2754 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2755 cmd_buffer->state.dynamic.line_width = lineWidth;
2756 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2757 }
2758
2759 void radv_CmdSetDepthBias(
2760 VkCommandBuffer commandBuffer,
2761 float depthBiasConstantFactor,
2762 float depthBiasClamp,
2763 float depthBiasSlopeFactor)
2764 {
2765 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2766
2767 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2768 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2769 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2770
2771 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2772 }
2773
2774 void radv_CmdSetBlendConstants(
2775 VkCommandBuffer commandBuffer,
2776 const float blendConstants[4])
2777 {
2778 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2779
2780 memcpy(cmd_buffer->state.dynamic.blend_constants,
2781 blendConstants, sizeof(float) * 4);
2782
2783 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2784 }
2785
2786 void radv_CmdSetDepthBounds(
2787 VkCommandBuffer commandBuffer,
2788 float minDepthBounds,
2789 float maxDepthBounds)
2790 {
2791 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2792
2793 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2794 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2795
2796 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2797 }
2798
2799 void radv_CmdSetStencilCompareMask(
2800 VkCommandBuffer commandBuffer,
2801 VkStencilFaceFlags faceMask,
2802 uint32_t compareMask)
2803 {
2804 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2805
2806 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2807 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2808 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2809 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2810
2811 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2812 }
2813
2814 void radv_CmdSetStencilWriteMask(
2815 VkCommandBuffer commandBuffer,
2816 VkStencilFaceFlags faceMask,
2817 uint32_t writeMask)
2818 {
2819 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2820
2821 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2822 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2823 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2824 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2825
2826 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2827 }
2828
2829 void radv_CmdSetStencilReference(
2830 VkCommandBuffer commandBuffer,
2831 VkStencilFaceFlags faceMask,
2832 uint32_t reference)
2833 {
2834 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2835
2836 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2837 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2838 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2839 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2840
2841 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2842 }
2843
2844 void radv_CmdSetDiscardRectangleEXT(
2845 VkCommandBuffer commandBuffer,
2846 uint32_t firstDiscardRectangle,
2847 uint32_t discardRectangleCount,
2848 const VkRect2D* pDiscardRectangles)
2849 {
2850 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2851 struct radv_cmd_state *state = &cmd_buffer->state;
2852 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2853
2854 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2855 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2856
2857 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2858 pDiscardRectangles, discardRectangleCount);
2859
2860 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2861 }
2862
2863 void radv_CmdExecuteCommands(
2864 VkCommandBuffer commandBuffer,
2865 uint32_t commandBufferCount,
2866 const VkCommandBuffer* pCmdBuffers)
2867 {
2868 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2869
2870 assert(commandBufferCount > 0);
2871
2872 /* Emit pending flushes on primary prior to executing secondary */
2873 si_emit_cache_flush(primary);
2874
2875 for (uint32_t i = 0; i < commandBufferCount; i++) {
2876 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2877
2878 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2879 secondary->scratch_size_needed);
2880 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2881 secondary->compute_scratch_size_needed);
2882
2883 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2884 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2885 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2886 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2887 if (secondary->tess_rings_needed)
2888 primary->tess_rings_needed = true;
2889 if (secondary->sample_positions_needed)
2890 primary->sample_positions_needed = true;
2891
2892 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2893
2894
2895 /* When the secondary command buffer is compute only we don't
2896 * need to re-emit the current graphics pipeline.
2897 */
2898 if (secondary->state.emitted_pipeline) {
2899 primary->state.emitted_pipeline =
2900 secondary->state.emitted_pipeline;
2901 }
2902
2903 /* When the secondary command buffer is graphics only we don't
2904 * need to re-emit the current compute pipeline.
2905 */
2906 if (secondary->state.emitted_compute_pipeline) {
2907 primary->state.emitted_compute_pipeline =
2908 secondary->state.emitted_compute_pipeline;
2909 }
2910
2911 /* Only re-emit the draw packets when needed. */
2912 if (secondary->state.last_primitive_reset_en != -1) {
2913 primary->state.last_primitive_reset_en =
2914 secondary->state.last_primitive_reset_en;
2915 }
2916
2917 if (secondary->state.last_primitive_reset_index) {
2918 primary->state.last_primitive_reset_index =
2919 secondary->state.last_primitive_reset_index;
2920 }
2921
2922 if (secondary->state.last_ia_multi_vgt_param) {
2923 primary->state.last_ia_multi_vgt_param =
2924 secondary->state.last_ia_multi_vgt_param;
2925 }
2926
2927 primary->state.last_first_instance = secondary->state.last_first_instance;
2928 primary->state.last_num_instances = secondary->state.last_num_instances;
2929 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2930
2931 if (secondary->state.last_index_type != -1) {
2932 primary->state.last_index_type =
2933 secondary->state.last_index_type;
2934 }
2935 }
2936
2937 /* After executing commands from secondary buffers we have to dirty
2938 * some states.
2939 */
2940 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2941 RADV_CMD_DIRTY_INDEX_BUFFER |
2942 RADV_CMD_DIRTY_DYNAMIC_ALL;
2943 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2944 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2945 }
2946
2947 VkResult radv_CreateCommandPool(
2948 VkDevice _device,
2949 const VkCommandPoolCreateInfo* pCreateInfo,
2950 const VkAllocationCallbacks* pAllocator,
2951 VkCommandPool* pCmdPool)
2952 {
2953 RADV_FROM_HANDLE(radv_device, device, _device);
2954 struct radv_cmd_pool *pool;
2955
2956 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2957 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2958 if (pool == NULL)
2959 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2960
2961 if (pAllocator)
2962 pool->alloc = *pAllocator;
2963 else
2964 pool->alloc = device->alloc;
2965
2966 list_inithead(&pool->cmd_buffers);
2967 list_inithead(&pool->free_cmd_buffers);
2968
2969 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2970
2971 *pCmdPool = radv_cmd_pool_to_handle(pool);
2972
2973 return VK_SUCCESS;
2974
2975 }
2976
2977 void radv_DestroyCommandPool(
2978 VkDevice _device,
2979 VkCommandPool commandPool,
2980 const VkAllocationCallbacks* pAllocator)
2981 {
2982 RADV_FROM_HANDLE(radv_device, device, _device);
2983 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2984
2985 if (!pool)
2986 return;
2987
2988 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2989 &pool->cmd_buffers, pool_link) {
2990 radv_cmd_buffer_destroy(cmd_buffer);
2991 }
2992
2993 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2994 &pool->free_cmd_buffers, pool_link) {
2995 radv_cmd_buffer_destroy(cmd_buffer);
2996 }
2997
2998 vk_free2(&device->alloc, pAllocator, pool);
2999 }
3000
3001 VkResult radv_ResetCommandPool(
3002 VkDevice device,
3003 VkCommandPool commandPool,
3004 VkCommandPoolResetFlags flags)
3005 {
3006 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3007 VkResult result;
3008
3009 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3010 &pool->cmd_buffers, pool_link) {
3011 result = radv_reset_cmd_buffer(cmd_buffer);
3012 if (result != VK_SUCCESS)
3013 return result;
3014 }
3015
3016 return VK_SUCCESS;
3017 }
3018
3019 void radv_TrimCommandPool(
3020 VkDevice device,
3021 VkCommandPool commandPool,
3022 VkCommandPoolTrimFlagsKHR flags)
3023 {
3024 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3025
3026 if (!pool)
3027 return;
3028
3029 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3030 &pool->free_cmd_buffers, pool_link) {
3031 radv_cmd_buffer_destroy(cmd_buffer);
3032 }
3033 }
3034
3035 void radv_CmdBeginRenderPass(
3036 VkCommandBuffer commandBuffer,
3037 const VkRenderPassBeginInfo* pRenderPassBegin,
3038 VkSubpassContents contents)
3039 {
3040 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3041 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3042 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3043
3044 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3045 cmd_buffer->cs, 2048);
3046 MAYBE_UNUSED VkResult result;
3047
3048 cmd_buffer->state.framebuffer = framebuffer;
3049 cmd_buffer->state.pass = pass;
3050 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3051
3052 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3053 if (result != VK_SUCCESS)
3054 return;
3055
3056 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3057 assert(cmd_buffer->cs->cdw <= cdw_max);
3058
3059 radv_cmd_buffer_clear_subpass(cmd_buffer);
3060 }
3061
3062 void radv_CmdBeginRenderPass2KHR(
3063 VkCommandBuffer commandBuffer,
3064 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3065 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3066 {
3067 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3068 pSubpassBeginInfo->contents);
3069 }
3070
3071 void radv_CmdNextSubpass(
3072 VkCommandBuffer commandBuffer,
3073 VkSubpassContents contents)
3074 {
3075 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3076
3077 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3078
3079 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3080 2048);
3081
3082 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3083 radv_cmd_buffer_clear_subpass(cmd_buffer);
3084 }
3085
3086 void radv_CmdNextSubpass2KHR(
3087 VkCommandBuffer commandBuffer,
3088 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3089 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3090 {
3091 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3092 }
3093
3094 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3095 {
3096 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3097 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3098 if (!radv_get_shader(pipeline, stage))
3099 continue;
3100
3101 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3102 if (loc->sgpr_idx == -1)
3103 continue;
3104 uint32_t base_reg = pipeline->user_data_0[stage];
3105 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3106
3107 }
3108 if (pipeline->gs_copy_shader) {
3109 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3110 if (loc->sgpr_idx != -1) {
3111 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3112 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3113 }
3114 }
3115 }
3116
3117 static void
3118 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3119 uint32_t vertex_count)
3120 {
3121 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3122 radeon_emit(cmd_buffer->cs, vertex_count);
3123 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3124 S_0287F0_USE_OPAQUE(0));
3125 }
3126
3127 static void
3128 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3129 uint64_t index_va,
3130 uint32_t index_count)
3131 {
3132 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3133 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3134 radeon_emit(cmd_buffer->cs, index_va);
3135 radeon_emit(cmd_buffer->cs, index_va >> 32);
3136 radeon_emit(cmd_buffer->cs, index_count);
3137 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3138 }
3139
3140 static void
3141 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3142 bool indexed,
3143 uint32_t draw_count,
3144 uint64_t count_va,
3145 uint32_t stride)
3146 {
3147 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3148 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3149 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3150 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3151 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3152 bool predicating = cmd_buffer->state.predicating;
3153 assert(base_reg);
3154
3155 /* just reset draw state for vertex data */
3156 cmd_buffer->state.last_first_instance = -1;
3157 cmd_buffer->state.last_num_instances = -1;
3158 cmd_buffer->state.last_vertex_offset = -1;
3159
3160 if (draw_count == 1 && !count_va && !draw_id_enable) {
3161 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3162 PKT3_DRAW_INDIRECT, 3, predicating));
3163 radeon_emit(cs, 0);
3164 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3165 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3166 radeon_emit(cs, di_src_sel);
3167 } else {
3168 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3169 PKT3_DRAW_INDIRECT_MULTI,
3170 8, predicating));
3171 radeon_emit(cs, 0);
3172 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3173 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3174 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3175 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3176 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3177 radeon_emit(cs, draw_count); /* count */
3178 radeon_emit(cs, count_va); /* count_addr */
3179 radeon_emit(cs, count_va >> 32);
3180 radeon_emit(cs, stride); /* stride */
3181 radeon_emit(cs, di_src_sel);
3182 }
3183 }
3184
3185 struct radv_draw_info {
3186 /**
3187 * Number of vertices.
3188 */
3189 uint32_t count;
3190
3191 /**
3192 * Index of the first vertex.
3193 */
3194 int32_t vertex_offset;
3195
3196 /**
3197 * First instance id.
3198 */
3199 uint32_t first_instance;
3200
3201 /**
3202 * Number of instances.
3203 */
3204 uint32_t instance_count;
3205
3206 /**
3207 * First index (indexed draws only).
3208 */
3209 uint32_t first_index;
3210
3211 /**
3212 * Whether it's an indexed draw.
3213 */
3214 bool indexed;
3215
3216 /**
3217 * Indirect draw parameters resource.
3218 */
3219 struct radv_buffer *indirect;
3220 uint64_t indirect_offset;
3221 uint32_t stride;
3222
3223 /**
3224 * Draw count parameters resource.
3225 */
3226 struct radv_buffer *count_buffer;
3227 uint64_t count_buffer_offset;
3228 };
3229
3230 static void
3231 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3232 const struct radv_draw_info *info)
3233 {
3234 struct radv_cmd_state *state = &cmd_buffer->state;
3235 struct radeon_winsys *ws = cmd_buffer->device->ws;
3236 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3237
3238 if (info->indirect) {
3239 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3240 uint64_t count_va = 0;
3241
3242 va += info->indirect->offset + info->indirect_offset;
3243
3244 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3245
3246 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3247 radeon_emit(cs, 1);
3248 radeon_emit(cs, va);
3249 radeon_emit(cs, va >> 32);
3250
3251 if (info->count_buffer) {
3252 count_va = radv_buffer_get_va(info->count_buffer->bo);
3253 count_va += info->count_buffer->offset +
3254 info->count_buffer_offset;
3255
3256 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3257 }
3258
3259 if (!state->subpass->view_mask) {
3260 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3261 info->indexed,
3262 info->count,
3263 count_va,
3264 info->stride);
3265 } else {
3266 unsigned i;
3267 for_each_bit(i, state->subpass->view_mask) {
3268 radv_emit_view_index(cmd_buffer, i);
3269
3270 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3271 info->indexed,
3272 info->count,
3273 count_va,
3274 info->stride);
3275 }
3276 }
3277 } else {
3278 assert(state->pipeline->graphics.vtx_base_sgpr);
3279
3280 if (info->vertex_offset != state->last_vertex_offset ||
3281 info->first_instance != state->last_first_instance) {
3282 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3283 state->pipeline->graphics.vtx_emit_num);
3284
3285 radeon_emit(cs, info->vertex_offset);
3286 radeon_emit(cs, info->first_instance);
3287 if (state->pipeline->graphics.vtx_emit_num == 3)
3288 radeon_emit(cs, 0);
3289 state->last_first_instance = info->first_instance;
3290 state->last_vertex_offset = info->vertex_offset;
3291 }
3292
3293 if (state->last_num_instances != info->instance_count) {
3294 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3295 radeon_emit(cs, info->instance_count);
3296 state->last_num_instances = info->instance_count;
3297 }
3298
3299 if (info->indexed) {
3300 int index_size = state->index_type ? 4 : 2;
3301 uint64_t index_va;
3302
3303 index_va = state->index_va;
3304 index_va += info->first_index * index_size;
3305
3306 if (!state->subpass->view_mask) {
3307 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3308 index_va,
3309 info->count);
3310 } else {
3311 unsigned i;
3312 for_each_bit(i, state->subpass->view_mask) {
3313 radv_emit_view_index(cmd_buffer, i);
3314
3315 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3316 index_va,
3317 info->count);
3318 }
3319 }
3320 } else {
3321 if (!state->subpass->view_mask) {
3322 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3323 } else {
3324 unsigned i;
3325 for_each_bit(i, state->subpass->view_mask) {
3326 radv_emit_view_index(cmd_buffer, i);
3327
3328 radv_cs_emit_draw_packet(cmd_buffer,
3329 info->count);
3330 }
3331 }
3332 }
3333 }
3334 }
3335
3336 /*
3337 * Vega and raven have a bug which triggers if there are multiple context
3338 * register contexts active at the same time with different scissor values.
3339 *
3340 * There are two possible workarounds:
3341 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3342 * there is only ever 1 active set of scissor values at the same time.
3343 *
3344 * 2) Whenever the hardware switches contexts we have to set the scissor
3345 * registers again even if it is a noop. That way the new context gets
3346 * the correct scissor values.
3347 *
3348 * This implements option 2. radv_need_late_scissor_emission needs to
3349 * return true on affected HW if radv_emit_all_graphics_states sets
3350 * any context registers.
3351 */
3352 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3353 bool indexed_draw)
3354 {
3355 struct radv_cmd_state *state = &cmd_buffer->state;
3356
3357 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3358 return false;
3359
3360 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3361
3362 /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3363 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_VERTEX_BUFFER | RADV_CMD_DIRTY_PIPELINE);
3364
3365 /* Assume all state changes except these two can imply context rolls. */
3366 if (cmd_buffer->state.dirty & used_states)
3367 return true;
3368
3369 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3370 return true;
3371
3372 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3373 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3374 return true;
3375
3376 return false;
3377 }
3378
3379 static void
3380 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3381 const struct radv_draw_info *info)
3382 {
3383 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3384
3385 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3386 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3387 radv_emit_rbplus_state(cmd_buffer);
3388
3389 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3390 radv_emit_graphics_pipeline(cmd_buffer);
3391
3392 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3393 radv_emit_framebuffer_state(cmd_buffer);
3394
3395 if (info->indexed) {
3396 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3397 radv_emit_index_buffer(cmd_buffer);
3398 } else {
3399 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3400 * so the state must be re-emitted before the next indexed
3401 * draw.
3402 */
3403 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3404 cmd_buffer->state.last_index_type = -1;
3405 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3406 }
3407 }
3408
3409 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3410
3411 radv_emit_draw_registers(cmd_buffer, info->indexed,
3412 info->instance_count > 1, info->indirect,
3413 info->indirect ? 0 : info->count);
3414
3415 if (late_scissor_emission)
3416 radv_emit_scissor(cmd_buffer);
3417 }
3418
3419 static void
3420 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3421 const struct radv_draw_info *info)
3422 {
3423 bool has_prefetch =
3424 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3425 bool pipeline_is_dirty =
3426 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3427 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3428
3429 MAYBE_UNUSED unsigned cdw_max =
3430 radeon_check_space(cmd_buffer->device->ws,
3431 cmd_buffer->cs, 4096);
3432
3433 /* Use optimal packet order based on whether we need to sync the
3434 * pipeline.
3435 */
3436 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3437 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3438 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3439 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3440 /* If we have to wait for idle, set all states first, so that
3441 * all SET packets are processed in parallel with previous draw
3442 * calls. Then upload descriptors, set shader pointers, and
3443 * draw, and prefetch at the end. This ensures that the time
3444 * the CUs are idle is very short. (there are only SET_SH
3445 * packets between the wait and the draw)
3446 */
3447 radv_emit_all_graphics_states(cmd_buffer, info);
3448 si_emit_cache_flush(cmd_buffer);
3449 /* <-- CUs are idle here --> */
3450
3451 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3452
3453 radv_emit_draw_packets(cmd_buffer, info);
3454 /* <-- CUs are busy here --> */
3455
3456 /* Start prefetches after the draw has been started. Both will
3457 * run in parallel, but starting the draw first is more
3458 * important.
3459 */
3460 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3461 radv_emit_prefetch_L2(cmd_buffer,
3462 cmd_buffer->state.pipeline, false);
3463 }
3464 } else {
3465 /* If we don't wait for idle, start prefetches first, then set
3466 * states, and draw at the end.
3467 */
3468 si_emit_cache_flush(cmd_buffer);
3469
3470 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3471 /* Only prefetch the vertex shader and VBO descriptors
3472 * in order to start the draw as soon as possible.
3473 */
3474 radv_emit_prefetch_L2(cmd_buffer,
3475 cmd_buffer->state.pipeline, true);
3476 }
3477
3478 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3479
3480 radv_emit_all_graphics_states(cmd_buffer, info);
3481 radv_emit_draw_packets(cmd_buffer, info);
3482
3483 /* Prefetch the remaining shaders after the draw has been
3484 * started.
3485 */
3486 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3487 radv_emit_prefetch_L2(cmd_buffer,
3488 cmd_buffer->state.pipeline, false);
3489 }
3490 }
3491
3492 assert(cmd_buffer->cs->cdw <= cdw_max);
3493 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3494 }
3495
3496 void radv_CmdDraw(
3497 VkCommandBuffer commandBuffer,
3498 uint32_t vertexCount,
3499 uint32_t instanceCount,
3500 uint32_t firstVertex,
3501 uint32_t firstInstance)
3502 {
3503 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3504 struct radv_draw_info info = {};
3505
3506 info.count = vertexCount;
3507 info.instance_count = instanceCount;
3508 info.first_instance = firstInstance;
3509 info.vertex_offset = firstVertex;
3510
3511 radv_draw(cmd_buffer, &info);
3512 }
3513
3514 void radv_CmdDrawIndexed(
3515 VkCommandBuffer commandBuffer,
3516 uint32_t indexCount,
3517 uint32_t instanceCount,
3518 uint32_t firstIndex,
3519 int32_t vertexOffset,
3520 uint32_t firstInstance)
3521 {
3522 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3523 struct radv_draw_info info = {};
3524
3525 info.indexed = true;
3526 info.count = indexCount;
3527 info.instance_count = instanceCount;
3528 info.first_index = firstIndex;
3529 info.vertex_offset = vertexOffset;
3530 info.first_instance = firstInstance;
3531
3532 radv_draw(cmd_buffer, &info);
3533 }
3534
3535 void radv_CmdDrawIndirect(
3536 VkCommandBuffer commandBuffer,
3537 VkBuffer _buffer,
3538 VkDeviceSize offset,
3539 uint32_t drawCount,
3540 uint32_t stride)
3541 {
3542 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3543 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3544 struct radv_draw_info info = {};
3545
3546 info.count = drawCount;
3547 info.indirect = buffer;
3548 info.indirect_offset = offset;
3549 info.stride = stride;
3550
3551 radv_draw(cmd_buffer, &info);
3552 }
3553
3554 void radv_CmdDrawIndexedIndirect(
3555 VkCommandBuffer commandBuffer,
3556 VkBuffer _buffer,
3557 VkDeviceSize offset,
3558 uint32_t drawCount,
3559 uint32_t stride)
3560 {
3561 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3562 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3563 struct radv_draw_info info = {};
3564
3565 info.indexed = true;
3566 info.count = drawCount;
3567 info.indirect = buffer;
3568 info.indirect_offset = offset;
3569 info.stride = stride;
3570
3571 radv_draw(cmd_buffer, &info);
3572 }
3573
3574 void radv_CmdDrawIndirectCountAMD(
3575 VkCommandBuffer commandBuffer,
3576 VkBuffer _buffer,
3577 VkDeviceSize offset,
3578 VkBuffer _countBuffer,
3579 VkDeviceSize countBufferOffset,
3580 uint32_t maxDrawCount,
3581 uint32_t stride)
3582 {
3583 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3584 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3585 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3586 struct radv_draw_info info = {};
3587
3588 info.count = maxDrawCount;
3589 info.indirect = buffer;
3590 info.indirect_offset = offset;
3591 info.count_buffer = count_buffer;
3592 info.count_buffer_offset = countBufferOffset;
3593 info.stride = stride;
3594
3595 radv_draw(cmd_buffer, &info);
3596 }
3597
3598 void radv_CmdDrawIndexedIndirectCountAMD(
3599 VkCommandBuffer commandBuffer,
3600 VkBuffer _buffer,
3601 VkDeviceSize offset,
3602 VkBuffer _countBuffer,
3603 VkDeviceSize countBufferOffset,
3604 uint32_t maxDrawCount,
3605 uint32_t stride)
3606 {
3607 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3608 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3609 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3610 struct radv_draw_info info = {};
3611
3612 info.indexed = true;
3613 info.count = maxDrawCount;
3614 info.indirect = buffer;
3615 info.indirect_offset = offset;
3616 info.count_buffer = count_buffer;
3617 info.count_buffer_offset = countBufferOffset;
3618 info.stride = stride;
3619
3620 radv_draw(cmd_buffer, &info);
3621 }
3622
3623 void radv_CmdDrawIndirectCountKHR(
3624 VkCommandBuffer commandBuffer,
3625 VkBuffer _buffer,
3626 VkDeviceSize offset,
3627 VkBuffer _countBuffer,
3628 VkDeviceSize countBufferOffset,
3629 uint32_t maxDrawCount,
3630 uint32_t stride)
3631 {
3632 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3633 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3634 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3635 struct radv_draw_info info = {};
3636
3637 info.count = maxDrawCount;
3638 info.indirect = buffer;
3639 info.indirect_offset = offset;
3640 info.count_buffer = count_buffer;
3641 info.count_buffer_offset = countBufferOffset;
3642 info.stride = stride;
3643
3644 radv_draw(cmd_buffer, &info);
3645 }
3646
3647 void radv_CmdDrawIndexedIndirectCountKHR(
3648 VkCommandBuffer commandBuffer,
3649 VkBuffer _buffer,
3650 VkDeviceSize offset,
3651 VkBuffer _countBuffer,
3652 VkDeviceSize countBufferOffset,
3653 uint32_t maxDrawCount,
3654 uint32_t stride)
3655 {
3656 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3657 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3658 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3659 struct radv_draw_info info = {};
3660
3661 info.indexed = true;
3662 info.count = maxDrawCount;
3663 info.indirect = buffer;
3664 info.indirect_offset = offset;
3665 info.count_buffer = count_buffer;
3666 info.count_buffer_offset = countBufferOffset;
3667 info.stride = stride;
3668
3669 radv_draw(cmd_buffer, &info);
3670 }
3671
3672 struct radv_dispatch_info {
3673 /**
3674 * Determine the layout of the grid (in block units) to be used.
3675 */
3676 uint32_t blocks[3];
3677
3678 /**
3679 * A starting offset for the grid. If unaligned is set, the offset
3680 * must still be aligned.
3681 */
3682 uint32_t offsets[3];
3683 /**
3684 * Whether it's an unaligned compute dispatch.
3685 */
3686 bool unaligned;
3687
3688 /**
3689 * Indirect compute parameters resource.
3690 */
3691 struct radv_buffer *indirect;
3692 uint64_t indirect_offset;
3693 };
3694
3695 static void
3696 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3697 const struct radv_dispatch_info *info)
3698 {
3699 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3700 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3701 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3702 struct radeon_winsys *ws = cmd_buffer->device->ws;
3703 bool predicating = cmd_buffer->state.predicating;
3704 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3705 struct radv_userdata_info *loc;
3706
3707 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3708 AC_UD_CS_GRID_SIZE);
3709
3710 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3711
3712 if (info->indirect) {
3713 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3714
3715 va += info->indirect->offset + info->indirect_offset;
3716
3717 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3718
3719 if (loc->sgpr_idx != -1) {
3720 for (unsigned i = 0; i < 3; ++i) {
3721 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3722 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3723 COPY_DATA_DST_SEL(COPY_DATA_REG));
3724 radeon_emit(cs, (va + 4 * i));
3725 radeon_emit(cs, (va + 4 * i) >> 32);
3726 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3727 + loc->sgpr_idx * 4) >> 2) + i);
3728 radeon_emit(cs, 0);
3729 }
3730 }
3731
3732 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3733 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
3734 PKT3_SHADER_TYPE_S(1));
3735 radeon_emit(cs, va);
3736 radeon_emit(cs, va >> 32);
3737 radeon_emit(cs, dispatch_initiator);
3738 } else {
3739 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3740 PKT3_SHADER_TYPE_S(1));
3741 radeon_emit(cs, 1);
3742 radeon_emit(cs, va);
3743 radeon_emit(cs, va >> 32);
3744
3745 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
3746 PKT3_SHADER_TYPE_S(1));
3747 radeon_emit(cs, 0);
3748 radeon_emit(cs, dispatch_initiator);
3749 }
3750 } else {
3751 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3752 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3753
3754 if (info->unaligned) {
3755 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3756 unsigned remainder[3];
3757
3758 /* If aligned, these should be an entire block size,
3759 * not 0.
3760 */
3761 remainder[0] = blocks[0] + cs_block_size[0] -
3762 align_u32_npot(blocks[0], cs_block_size[0]);
3763 remainder[1] = blocks[1] + cs_block_size[1] -
3764 align_u32_npot(blocks[1], cs_block_size[1]);
3765 remainder[2] = blocks[2] + cs_block_size[2] -
3766 align_u32_npot(blocks[2], cs_block_size[2]);
3767
3768 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3769 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3770 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3771
3772 for(unsigned i = 0; i < 3; ++i) {
3773 assert(offsets[i] % cs_block_size[i] == 0);
3774 offsets[i] /= cs_block_size[i];
3775 }
3776
3777 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3778 radeon_emit(cs,
3779 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3780 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3781 radeon_emit(cs,
3782 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3783 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3784 radeon_emit(cs,
3785 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3786 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3787
3788 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3789 }
3790
3791 if (loc->sgpr_idx != -1) {
3792 assert(!loc->indirect);
3793 assert(loc->num_sgprs == 3);
3794
3795 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3796 loc->sgpr_idx * 4, 3);
3797 radeon_emit(cs, blocks[0]);
3798 radeon_emit(cs, blocks[1]);
3799 radeon_emit(cs, blocks[2]);
3800 }
3801
3802 if (offsets[0] || offsets[1] || offsets[2]) {
3803 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3804 radeon_emit(cs, offsets[0]);
3805 radeon_emit(cs, offsets[1]);
3806 radeon_emit(cs, offsets[2]);
3807
3808 /* The blocks in the packet are not counts but end values. */
3809 for (unsigned i = 0; i < 3; ++i)
3810 blocks[i] += offsets[i];
3811 } else {
3812 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3813 }
3814
3815 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
3816 PKT3_SHADER_TYPE_S(1));
3817 radeon_emit(cs, blocks[0]);
3818 radeon_emit(cs, blocks[1]);
3819 radeon_emit(cs, blocks[2]);
3820 radeon_emit(cs, dispatch_initiator);
3821 }
3822
3823 assert(cmd_buffer->cs->cdw <= cdw_max);
3824 }
3825
3826 static void
3827 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3828 {
3829 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3830 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3831 }
3832
3833 static void
3834 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3835 const struct radv_dispatch_info *info)
3836 {
3837 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3838 bool has_prefetch =
3839 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3840 bool pipeline_is_dirty = pipeline &&
3841 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3842
3843 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3844 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3845 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3846 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3847 /* If we have to wait for idle, set all states first, so that
3848 * all SET packets are processed in parallel with previous draw
3849 * calls. Then upload descriptors, set shader pointers, and
3850 * dispatch, and prefetch at the end. This ensures that the
3851 * time the CUs are idle is very short. (there are only SET_SH
3852 * packets between the wait and the draw)
3853 */
3854 radv_emit_compute_pipeline(cmd_buffer);
3855 si_emit_cache_flush(cmd_buffer);
3856 /* <-- CUs are idle here --> */
3857
3858 radv_upload_compute_shader_descriptors(cmd_buffer);
3859
3860 radv_emit_dispatch_packets(cmd_buffer, info);
3861 /* <-- CUs are busy here --> */
3862
3863 /* Start prefetches after the dispatch has been started. Both
3864 * will run in parallel, but starting the dispatch first is
3865 * more important.
3866 */
3867 if (has_prefetch && pipeline_is_dirty) {
3868 radv_emit_shader_prefetch(cmd_buffer,
3869 pipeline->shaders[MESA_SHADER_COMPUTE]);
3870 }
3871 } else {
3872 /* If we don't wait for idle, start prefetches first, then set
3873 * states, and dispatch at the end.
3874 */
3875 si_emit_cache_flush(cmd_buffer);
3876
3877 if (has_prefetch && pipeline_is_dirty) {
3878 radv_emit_shader_prefetch(cmd_buffer,
3879 pipeline->shaders[MESA_SHADER_COMPUTE]);
3880 }
3881
3882 radv_upload_compute_shader_descriptors(cmd_buffer);
3883
3884 radv_emit_compute_pipeline(cmd_buffer);
3885 radv_emit_dispatch_packets(cmd_buffer, info);
3886 }
3887
3888 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3889 }
3890
3891 void radv_CmdDispatchBase(
3892 VkCommandBuffer commandBuffer,
3893 uint32_t base_x,
3894 uint32_t base_y,
3895 uint32_t base_z,
3896 uint32_t x,
3897 uint32_t y,
3898 uint32_t z)
3899 {
3900 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3901 struct radv_dispatch_info info = {};
3902
3903 info.blocks[0] = x;
3904 info.blocks[1] = y;
3905 info.blocks[2] = z;
3906
3907 info.offsets[0] = base_x;
3908 info.offsets[1] = base_y;
3909 info.offsets[2] = base_z;
3910 radv_dispatch(cmd_buffer, &info);
3911 }
3912
3913 void radv_CmdDispatch(
3914 VkCommandBuffer commandBuffer,
3915 uint32_t x,
3916 uint32_t y,
3917 uint32_t z)
3918 {
3919 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3920 }
3921
3922 void radv_CmdDispatchIndirect(
3923 VkCommandBuffer commandBuffer,
3924 VkBuffer _buffer,
3925 VkDeviceSize offset)
3926 {
3927 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3928 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3929 struct radv_dispatch_info info = {};
3930
3931 info.indirect = buffer;
3932 info.indirect_offset = offset;
3933
3934 radv_dispatch(cmd_buffer, &info);
3935 }
3936
3937 void radv_unaligned_dispatch(
3938 struct radv_cmd_buffer *cmd_buffer,
3939 uint32_t x,
3940 uint32_t y,
3941 uint32_t z)
3942 {
3943 struct radv_dispatch_info info = {};
3944
3945 info.blocks[0] = x;
3946 info.blocks[1] = y;
3947 info.blocks[2] = z;
3948 info.unaligned = 1;
3949
3950 radv_dispatch(cmd_buffer, &info);
3951 }
3952
3953 void radv_CmdEndRenderPass(
3954 VkCommandBuffer commandBuffer)
3955 {
3956 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3957
3958 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3959
3960 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3961
3962 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3963 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3964 radv_handle_subpass_image_transition(cmd_buffer,
3965 (struct radv_subpass_attachment){i, layout});
3966 }
3967
3968 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3969
3970 cmd_buffer->state.pass = NULL;
3971 cmd_buffer->state.subpass = NULL;
3972 cmd_buffer->state.attachments = NULL;
3973 cmd_buffer->state.framebuffer = NULL;
3974 }
3975
3976 void radv_CmdEndRenderPass2KHR(
3977 VkCommandBuffer commandBuffer,
3978 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3979 {
3980 radv_CmdEndRenderPass(commandBuffer);
3981 }
3982
3983 /*
3984 * For HTILE we have the following interesting clear words:
3985 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3986 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3987 * 0xfffffff0: Clear depth to 1.0
3988 * 0x00000000: Clear depth to 0.0
3989 */
3990 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3991 struct radv_image *image,
3992 const VkImageSubresourceRange *range,
3993 uint32_t clear_word)
3994 {
3995 assert(range->baseMipLevel == 0);
3996 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3997 unsigned layer_count = radv_get_layerCount(image, range);
3998 uint64_t size = image->surface.htile_slice_size * layer_count;
3999 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4000 uint64_t offset = image->offset + image->htile_offset +
4001 image->surface.htile_slice_size * range->baseArrayLayer;
4002 struct radv_cmd_state *state = &cmd_buffer->state;
4003 VkClearDepthStencilValue value = {};
4004
4005 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4006 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4007
4008 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4009 size, clear_word);
4010
4011 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4012
4013 if (vk_format_is_stencil(image->vk_format))
4014 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4015
4016 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4017 }
4018
4019 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4020 struct radv_image *image,
4021 VkImageLayout src_layout,
4022 VkImageLayout dst_layout,
4023 unsigned src_queue_mask,
4024 unsigned dst_queue_mask,
4025 const VkImageSubresourceRange *range,
4026 VkImageAspectFlags pending_clears)
4027 {
4028 if (!radv_image_has_htile(image))
4029 return;
4030
4031 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4032 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4033 /* TODO: merge with the clear if applicable */
4034 radv_initialize_htile(cmd_buffer, image, range, 0);
4035 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4036 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4037 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4038 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4039 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4040 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4041 VkImageSubresourceRange local_range = *range;
4042 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4043 local_range.baseMipLevel = 0;
4044 local_range.levelCount = 1;
4045
4046 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4047 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4048
4049 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4050
4051 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4052 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4053 }
4054 }
4055
4056 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4057 struct radv_image *image, uint32_t value)
4058 {
4059 struct radv_cmd_state *state = &cmd_buffer->state;
4060
4061 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4062 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4063
4064 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4065
4066 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4067 }
4068
4069 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4070 struct radv_image *image, uint32_t value)
4071 {
4072 struct radv_cmd_state *state = &cmd_buffer->state;
4073
4074 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4075 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4076
4077 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4078
4079 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4080 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4081 }
4082
4083 /**
4084 * Initialize DCC/FMASK/CMASK metadata for a color image.
4085 */
4086 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4087 struct radv_image *image,
4088 VkImageLayout src_layout,
4089 VkImageLayout dst_layout,
4090 unsigned src_queue_mask,
4091 unsigned dst_queue_mask)
4092 {
4093 if (radv_image_has_cmask(image)) {
4094 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4095
4096 /* TODO: clarify this. */
4097 if (radv_image_has_fmask(image)) {
4098 value = 0xccccccccu;
4099 }
4100
4101 radv_initialise_cmask(cmd_buffer, image, value);
4102 }
4103
4104 if (radv_image_has_dcc(image)) {
4105 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4106
4107 if (radv_layout_dcc_compressed(image, dst_layout,
4108 dst_queue_mask)) {
4109 value = 0x20202020u;
4110 }
4111
4112 radv_initialize_dcc(cmd_buffer, image, value);
4113
4114 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image, false);
4115 }
4116
4117 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4118 uint32_t color_values[2] = {};
4119 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4120 }
4121 }
4122
4123 /**
4124 * Handle color image transitions for DCC/FMASK/CMASK.
4125 */
4126 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4127 struct radv_image *image,
4128 VkImageLayout src_layout,
4129 VkImageLayout dst_layout,
4130 unsigned src_queue_mask,
4131 unsigned dst_queue_mask,
4132 const VkImageSubresourceRange *range)
4133 {
4134 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4135 radv_init_color_image_metadata(cmd_buffer, image,
4136 src_layout, dst_layout,
4137 src_queue_mask, dst_queue_mask);
4138 return;
4139 }
4140
4141 if (radv_image_has_dcc(image)) {
4142 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4143 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4144 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4145 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4146 radv_decompress_dcc(cmd_buffer, image, range);
4147 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4148 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4149 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4150 }
4151 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4152 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4153 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4154 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4155 }
4156 }
4157 }
4158
4159 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4160 struct radv_image *image,
4161 VkImageLayout src_layout,
4162 VkImageLayout dst_layout,
4163 uint32_t src_family,
4164 uint32_t dst_family,
4165 const VkImageSubresourceRange *range,
4166 VkImageAspectFlags pending_clears)
4167 {
4168 if (image->exclusive && src_family != dst_family) {
4169 /* This is an acquire or a release operation and there will be
4170 * a corresponding release/acquire. Do the transition in the
4171 * most flexible queue. */
4172
4173 assert(src_family == cmd_buffer->queue_family_index ||
4174 dst_family == cmd_buffer->queue_family_index);
4175
4176 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4177 return;
4178
4179 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4180 (src_family == RADV_QUEUE_GENERAL ||
4181 dst_family == RADV_QUEUE_GENERAL))
4182 return;
4183 }
4184
4185 unsigned src_queue_mask =
4186 radv_image_queue_family_mask(image, src_family,
4187 cmd_buffer->queue_family_index);
4188 unsigned dst_queue_mask =
4189 radv_image_queue_family_mask(image, dst_family,
4190 cmd_buffer->queue_family_index);
4191
4192 if (vk_format_is_depth(image->vk_format)) {
4193 radv_handle_depth_image_transition(cmd_buffer, image,
4194 src_layout, dst_layout,
4195 src_queue_mask, dst_queue_mask,
4196 range, pending_clears);
4197 } else {
4198 radv_handle_color_image_transition(cmd_buffer, image,
4199 src_layout, dst_layout,
4200 src_queue_mask, dst_queue_mask,
4201 range);
4202 }
4203 }
4204
4205 struct radv_barrier_info {
4206 uint32_t eventCount;
4207 const VkEvent *pEvents;
4208 VkPipelineStageFlags srcStageMask;
4209 };
4210
4211 static void
4212 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4213 uint32_t memoryBarrierCount,
4214 const VkMemoryBarrier *pMemoryBarriers,
4215 uint32_t bufferMemoryBarrierCount,
4216 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4217 uint32_t imageMemoryBarrierCount,
4218 const VkImageMemoryBarrier *pImageMemoryBarriers,
4219 const struct radv_barrier_info *info)
4220 {
4221 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4222 enum radv_cmd_flush_bits src_flush_bits = 0;
4223 enum radv_cmd_flush_bits dst_flush_bits = 0;
4224
4225 for (unsigned i = 0; i < info->eventCount; ++i) {
4226 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4227 uint64_t va = radv_buffer_get_va(event->bo);
4228
4229 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4230
4231 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4232
4233 si_emit_wait_fence(cs, va, 1, 0xffffffff);
4234 assert(cmd_buffer->cs->cdw <= cdw_max);
4235 }
4236
4237 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4238 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4239 NULL);
4240 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4241 NULL);
4242 }
4243
4244 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4245 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4246 NULL);
4247 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4248 NULL);
4249 }
4250
4251 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4252 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4253
4254 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4255 image);
4256 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4257 image);
4258 }
4259
4260 radv_stage_flush(cmd_buffer, info->srcStageMask);
4261 cmd_buffer->state.flush_bits |= src_flush_bits;
4262
4263 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4264 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4265 radv_handle_image_transition(cmd_buffer, image,
4266 pImageMemoryBarriers[i].oldLayout,
4267 pImageMemoryBarriers[i].newLayout,
4268 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4269 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4270 &pImageMemoryBarriers[i].subresourceRange,
4271 0);
4272 }
4273
4274 /* Make sure CP DMA is idle because the driver might have performed a
4275 * DMA operation for copying or filling buffers/images.
4276 */
4277 si_cp_dma_wait_for_idle(cmd_buffer);
4278
4279 cmd_buffer->state.flush_bits |= dst_flush_bits;
4280 }
4281
4282 void radv_CmdPipelineBarrier(
4283 VkCommandBuffer commandBuffer,
4284 VkPipelineStageFlags srcStageMask,
4285 VkPipelineStageFlags destStageMask,
4286 VkBool32 byRegion,
4287 uint32_t memoryBarrierCount,
4288 const VkMemoryBarrier* pMemoryBarriers,
4289 uint32_t bufferMemoryBarrierCount,
4290 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4291 uint32_t imageMemoryBarrierCount,
4292 const VkImageMemoryBarrier* pImageMemoryBarriers)
4293 {
4294 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4295 struct radv_barrier_info info;
4296
4297 info.eventCount = 0;
4298 info.pEvents = NULL;
4299 info.srcStageMask = srcStageMask;
4300
4301 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4302 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4303 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4304 }
4305
4306
4307 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4308 struct radv_event *event,
4309 VkPipelineStageFlags stageMask,
4310 unsigned value)
4311 {
4312 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4313 uint64_t va = radv_buffer_get_va(event->bo);
4314
4315 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4316
4317 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4318
4319 /* Flags that only require a top-of-pipe event. */
4320 VkPipelineStageFlags top_of_pipe_flags =
4321 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4322
4323 /* Flags that only require a post-index-fetch event. */
4324 VkPipelineStageFlags post_index_fetch_flags =
4325 top_of_pipe_flags |
4326 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4327 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4328
4329 /* Make sure CP DMA is idle because the driver might have performed a
4330 * DMA operation for copying or filling buffers/images.
4331 */
4332 si_cp_dma_wait_for_idle(cmd_buffer);
4333
4334 /* TODO: Emit EOS events for syncing PS/CS stages. */
4335
4336 if (!(stageMask & ~top_of_pipe_flags)) {
4337 /* Just need to sync the PFP engine. */
4338 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4339 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4340 S_370_WR_CONFIRM(1) |
4341 S_370_ENGINE_SEL(V_370_PFP));
4342 radeon_emit(cs, va);
4343 radeon_emit(cs, va >> 32);
4344 radeon_emit(cs, value);
4345 } else if (!(stageMask & ~post_index_fetch_flags)) {
4346 /* Sync ME because PFP reads index and indirect buffers. */
4347 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4348 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4349 S_370_WR_CONFIRM(1) |
4350 S_370_ENGINE_SEL(V_370_ME));
4351 radeon_emit(cs, va);
4352 radeon_emit(cs, va >> 32);
4353 radeon_emit(cs, value);
4354 } else {
4355 /* Otherwise, sync all prior GPU work using an EOP event. */
4356 si_cs_emit_write_event_eop(cs,
4357 cmd_buffer->device->physical_device->rad_info.chip_class,
4358 radv_cmd_buffer_uses_mec(cmd_buffer),
4359 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4360 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4361 cmd_buffer->gfx9_eop_bug_va);
4362 }
4363
4364 assert(cmd_buffer->cs->cdw <= cdw_max);
4365 }
4366
4367 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4368 VkEvent _event,
4369 VkPipelineStageFlags stageMask)
4370 {
4371 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4372 RADV_FROM_HANDLE(radv_event, event, _event);
4373
4374 write_event(cmd_buffer, event, stageMask, 1);
4375 }
4376
4377 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4378 VkEvent _event,
4379 VkPipelineStageFlags stageMask)
4380 {
4381 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4382 RADV_FROM_HANDLE(radv_event, event, _event);
4383
4384 write_event(cmd_buffer, event, stageMask, 0);
4385 }
4386
4387 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4388 uint32_t eventCount,
4389 const VkEvent* pEvents,
4390 VkPipelineStageFlags srcStageMask,
4391 VkPipelineStageFlags dstStageMask,
4392 uint32_t memoryBarrierCount,
4393 const VkMemoryBarrier* pMemoryBarriers,
4394 uint32_t bufferMemoryBarrierCount,
4395 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4396 uint32_t imageMemoryBarrierCount,
4397 const VkImageMemoryBarrier* pImageMemoryBarriers)
4398 {
4399 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4400 struct radv_barrier_info info;
4401
4402 info.eventCount = eventCount;
4403 info.pEvents = pEvents;
4404 info.srcStageMask = 0;
4405
4406 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4407 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4408 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4409 }
4410
4411
4412 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4413 uint32_t deviceMask)
4414 {
4415 /* No-op */
4416 }