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[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 uint32_t src_family,
42 uint32_t dst_family,
43 VkImageSubresourceRange range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static bool
191 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
192 uint64_t min_needed)
193 {
194 uint64_t new_size;
195 struct radeon_winsys_bo *bo;
196 struct radv_cmd_buffer_upload *upload;
197 struct radv_device *device = cmd_buffer->device;
198
199 new_size = MAX2(min_needed, 16 * 1024);
200 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
201
202 bo = device->ws->buffer_create(device->ws,
203 new_size, 4096,
204 RADEON_DOMAIN_GTT,
205 RADEON_FLAG_CPU_ACCESS);
206
207 if (!bo) {
208 cmd_buffer->record_fail = true;
209 return false;
210 }
211
212 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
213 if (cmd_buffer->upload.upload_bo) {
214 upload = malloc(sizeof(*upload));
215
216 if (!upload) {
217 cmd_buffer->record_fail = true;
218 device->ws->buffer_destroy(bo);
219 return false;
220 }
221
222 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
223 list_add(&upload->list, &cmd_buffer->upload.list);
224 }
225
226 cmd_buffer->upload.upload_bo = bo;
227 cmd_buffer->upload.size = new_size;
228 cmd_buffer->upload.offset = 0;
229 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
230
231 if (!cmd_buffer->upload.map) {
232 cmd_buffer->record_fail = true;
233 return false;
234 }
235
236 return true;
237 }
238
239 bool
240 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
241 unsigned size,
242 unsigned alignment,
243 unsigned *out_offset,
244 void **ptr)
245 {
246 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
247 if (offset + size > cmd_buffer->upload.size) {
248 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
249 return false;
250 offset = 0;
251 }
252
253 *out_offset = offset;
254 *ptr = cmd_buffer->upload.map + offset;
255
256 cmd_buffer->upload.offset = offset + size;
257 return true;
258 }
259
260 bool
261 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
262 unsigned size, unsigned alignment,
263 const void *data, unsigned *out_offset)
264 {
265 uint8_t *ptr;
266
267 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
268 out_offset, (void **)&ptr))
269 return false;
270
271 if (ptr)
272 memcpy(ptr, data, size);
273
274 return true;
275 }
276
277 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
278 {
279 struct radv_device *device = cmd_buffer->device;
280 struct radeon_winsys_cs *cs = cmd_buffer->cs;
281 uint64_t va;
282
283 if (!device->trace_bo)
284 return;
285
286 va = device->ws->buffer_get_va(device->trace_bo);
287
288 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
289
290 ++cmd_buffer->state.trace_id;
291 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
292 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
293 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
294 S_370_WR_CONFIRM(1) |
295 S_370_ENGINE_SEL(V_370_ME));
296 radeon_emit(cs, va);
297 radeon_emit(cs, va >> 32);
298 radeon_emit(cs, cmd_buffer->state.trace_id);
299 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
300 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
301 }
302
303 static void
304 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
305 struct radv_pipeline *pipeline)
306 {
307 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
308 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
309 8);
310 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
311 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
312 }
313
314 static void
315 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
316 struct radv_pipeline *pipeline)
317 {
318 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
319 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
320 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
321
322 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
323 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
324 }
325
326 /* 12.4 fixed-point */
327 static unsigned radv_pack_float_12p4(float x)
328 {
329 return x <= 0 ? 0 :
330 x >= 4096 ? 0xffff : x * 16;
331 }
332
333 static uint32_t
334 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs)
335 {
336 switch (stage) {
337 case MESA_SHADER_FRAGMENT:
338 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
339 case MESA_SHADER_VERTEX:
340 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
341 case MESA_SHADER_GEOMETRY:
342 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
343 case MESA_SHADER_COMPUTE:
344 return R_00B900_COMPUTE_USER_DATA_0;
345 default:
346 unreachable("unknown shader");
347 }
348 }
349
350 static struct ac_userdata_info *
351 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
352 gl_shader_stage stage,
353 int idx)
354 {
355 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
356 }
357
358 static void
359 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
360 struct radv_pipeline *pipeline,
361 gl_shader_stage stage,
362 int idx, uint64_t va)
363 {
364 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
365 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline));
366 if (loc->sgpr_idx == -1)
367 return;
368 assert(loc->num_sgprs == 2);
369 assert(!loc->indirect);
370 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
371 radeon_emit(cmd_buffer->cs, va);
372 radeon_emit(cmd_buffer->cs, va >> 32);
373 }
374
375 static void
376 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
377 struct radv_pipeline *pipeline)
378 {
379 int num_samples = pipeline->graphics.ms.num_samples;
380 struct radv_multisample_state *ms = &pipeline->graphics.ms;
381 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
382
383 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
384 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
385 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
386
387 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
388 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
389
390 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
391 return;
392
393 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
394 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
395 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
396
397 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
398
399 uint32_t samples_offset;
400 void *samples_ptr;
401 void *src;
402 radv_cmd_buffer_upload_alloc(cmd_buffer, num_samples * 4 * 2, 256, &samples_offset,
403 &samples_ptr);
404 switch (num_samples) {
405 case 1:
406 src = cmd_buffer->device->sample_locations_1x;
407 break;
408 case 2:
409 src = cmd_buffer->device->sample_locations_2x;
410 break;
411 case 4:
412 src = cmd_buffer->device->sample_locations_4x;
413 break;
414 case 8:
415 src = cmd_buffer->device->sample_locations_8x;
416 break;
417 case 16:
418 src = cmd_buffer->device->sample_locations_16x;
419 break;
420 default:
421 unreachable("unknown number of samples");
422 }
423 memcpy(samples_ptr, src, num_samples * 4 * 2);
424
425 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
426 va += samples_offset;
427
428 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
429 AC_UD_PS_SAMPLE_POS, va);
430 }
431
432 static void
433 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
434 struct radv_pipeline *pipeline)
435 {
436 struct radv_raster_state *raster = &pipeline->graphics.raster;
437
438 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
439 raster->pa_cl_clip_cntl);
440
441 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
442 raster->spi_interp_control);
443
444 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
445 unsigned tmp = (unsigned)(1.0 * 8.0);
446 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
447 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
448 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
449
450 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
451 raster->pa_su_vtx_cntl);
452
453 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
454 raster->pa_su_sc_mode_cntl);
455 }
456
457 static void
458 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
459 struct radv_pipeline *pipeline,
460 struct radv_shader_variant *shader)
461 {
462 struct radeon_winsys *ws = cmd_buffer->device->ws;
463 uint64_t va = ws->buffer_get_va(shader->bo);
464 unsigned export_count;
465
466 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
467
468 export_count = MAX2(1, shader->info.vs.param_exports);
469 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
470 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
471
472 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
473 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
474 S_02870C_POS1_EXPORT_FORMAT(shader->info.vs.pos_exports > 1 ?
475 V_02870C_SPI_SHADER_4COMP :
476 V_02870C_SPI_SHADER_NONE) |
477 S_02870C_POS2_EXPORT_FORMAT(shader->info.vs.pos_exports > 2 ?
478 V_02870C_SPI_SHADER_4COMP :
479 V_02870C_SPI_SHADER_NONE) |
480 S_02870C_POS3_EXPORT_FORMAT(shader->info.vs.pos_exports > 3 ?
481 V_02870C_SPI_SHADER_4COMP :
482 V_02870C_SPI_SHADER_NONE));
483
484
485 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
486 radeon_emit(cmd_buffer->cs, va >> 8);
487 radeon_emit(cmd_buffer->cs, va >> 40);
488 radeon_emit(cmd_buffer->cs, shader->rsrc1);
489 radeon_emit(cmd_buffer->cs, shader->rsrc2);
490
491 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
492 S_028818_VTX_W0_FMT(1) |
493 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
494 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
495 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
496
497 unsigned clip_dist_mask, cull_dist_mask, total_mask;
498 clip_dist_mask = shader->info.vs.clip_dist_mask;
499 cull_dist_mask = shader->info.vs.cull_dist_mask;
500 total_mask = clip_dist_mask | cull_dist_mask;
501
502 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
503 S_02881C_USE_VTX_POINT_SIZE(shader->info.vs.writes_pointsize) |
504 S_02881C_USE_VTX_RENDER_TARGET_INDX(shader->info.vs.writes_layer) |
505 S_02881C_USE_VTX_VIEWPORT_INDX(shader->info.vs.writes_viewport_index) |
506 S_02881C_VS_OUT_MISC_VEC_ENA(shader->info.vs.writes_pointsize ||
507 shader->info.vs.writes_layer ||
508 shader->info.vs.writes_viewport_index) |
509 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
510 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
511 pipeline->graphics.raster.pa_cl_vs_out_cntl |
512 cull_dist_mask << 8 |
513 clip_dist_mask);
514
515 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
516 S_028AB4_REUSE_OFF(shader->info.vs.writes_viewport_index));
517 }
518
519 static void
520 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
521 struct radv_shader_variant *shader)
522 {
523 struct radeon_winsys *ws = cmd_buffer->device->ws;
524 uint64_t va = ws->buffer_get_va(shader->bo);
525
526 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
527
528 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
529 shader->info.vs.esgs_itemsize / 4);
530 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
531 radeon_emit(cmd_buffer->cs, va >> 8);
532 radeon_emit(cmd_buffer->cs, va >> 40);
533 radeon_emit(cmd_buffer->cs, shader->rsrc1);
534 radeon_emit(cmd_buffer->cs, shader->rsrc2);
535 }
536
537 static void
538 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
539 struct radv_pipeline *pipeline)
540 {
541 struct radv_shader_variant *vs;
542
543 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
544
545 vs = pipeline->shaders[MESA_SHADER_VERTEX];
546
547 if (vs->info.vs.as_es)
548 radv_emit_hw_es(cmd_buffer, vs);
549 else
550 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
551
552 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
553 }
554
555 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
556 {
557 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
558 unsigned cut_mode;
559
560 if (gs_max_vert_out <= 128) {
561 cut_mode = V_028A40_GS_CUT_128;
562 } else if (gs_max_vert_out <= 256) {
563 cut_mode = V_028A40_GS_CUT_256;
564 } else if (gs_max_vert_out <= 512) {
565 cut_mode = V_028A40_GS_CUT_512;
566 } else {
567 assert(gs_max_vert_out <= 1024);
568 cut_mode = V_028A40_GS_CUT_1024;
569 }
570
571 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
572 S_028A40_CUT_MODE(cut_mode)|
573 S_028A40_ES_WRITE_OPTIMIZE(1) |
574 S_028A40_GS_WRITE_OPTIMIZE(1);
575 }
576
577 static void
578 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
579 struct radv_pipeline *pipeline)
580 {
581 struct radeon_winsys *ws = cmd_buffer->device->ws;
582 struct radv_shader_variant *gs;
583 uint64_t va;
584
585 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
586 if (!gs) {
587 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, 0);
588 return;
589 }
590
591 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
592
593 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
594
595 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
596 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
597 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
598 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
599
600 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
601
602 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
603
604 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
605 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
606 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
607 radeon_emit(cmd_buffer->cs, 0);
608 radeon_emit(cmd_buffer->cs, 0);
609 radeon_emit(cmd_buffer->cs, 0);
610
611 uint32_t gs_num_invocations = gs->info.gs.invocations;
612 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
613 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
614 S_028B90_ENABLE(gs_num_invocations > 0));
615
616 va = ws->buffer_get_va(gs->bo);
617 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
618 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
619 radeon_emit(cmd_buffer->cs, va >> 8);
620 radeon_emit(cmd_buffer->cs, va >> 40);
621 radeon_emit(cmd_buffer->cs, gs->rsrc1);
622 radeon_emit(cmd_buffer->cs, gs->rsrc2);
623
624 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
625
626 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
627 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
628 if (loc->sgpr_idx != -1) {
629 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
630 uint32_t num_entries = 64;
631 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
632
633 if (is_vi)
634 num_entries *= stride;
635
636 stride = S_008F04_STRIDE(stride);
637 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
638 radeon_emit(cmd_buffer->cs, stride);
639 radeon_emit(cmd_buffer->cs, num_entries);
640 }
641 }
642
643 static void
644 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
645 struct radv_pipeline *pipeline)
646 {
647 struct radeon_winsys *ws = cmd_buffer->device->ws;
648 struct radv_shader_variant *ps, *vs;
649 uint64_t va;
650 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
651 struct radv_blend_state *blend = &pipeline->graphics.blend;
652 unsigned ps_offset = 0;
653 unsigned z_order;
654 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
655
656 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
657 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : pipeline->shaders[MESA_SHADER_VERTEX];
658 va = ws->buffer_get_va(ps->bo);
659 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
660
661 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
662 radeon_emit(cmd_buffer->cs, va >> 8);
663 radeon_emit(cmd_buffer->cs, va >> 40);
664 radeon_emit(cmd_buffer->cs, ps->rsrc1);
665 radeon_emit(cmd_buffer->cs, ps->rsrc2);
666
667 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
668 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
669 else
670 z_order = V_02880C_LATE_Z;
671
672
673 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
674 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
675 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
676 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
677 S_02880C_Z_ORDER(z_order) |
678 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
679 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
680 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory));
681
682 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
683 ps->config.spi_ps_input_ena);
684
685 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
686 ps->config.spi_ps_input_addr);
687
688 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(0);
689 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
690 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
691
692 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
693
694 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
695 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
696 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
697 V_028710_SPI_SHADER_ZERO);
698
699 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
700
701 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
702 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
703
704 if (ps->info.fs.has_pcoord) {
705 unsigned val;
706 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
707 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
708 ps_offset++;
709 }
710
711 if (ps->info.fs.prim_id_input && (vs->info.vs.prim_id_output != 0xffffffff)) {
712 unsigned vs_offset, flat_shade;
713 unsigned val;
714 vs_offset = vs->info.vs.prim_id_output;
715 flat_shade = true;
716 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
717 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
718 ++ps_offset;
719 }
720
721 if (ps->info.fs.layer_input && (vs->info.vs.layer_output != 0xffffffff)) {
722 unsigned vs_offset, flat_shade;
723 unsigned val;
724 vs_offset = vs->info.vs.layer_output;
725 flat_shade = true;
726 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
727 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
728 ++ps_offset;
729 }
730
731 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
732 unsigned vs_offset, flat_shade;
733 unsigned val;
734
735 if (!(ps->info.fs.input_mask & (1u << i)))
736 continue;
737
738
739 if (!(vs->info.vs.export_mask & (1u << i))) {
740 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset,
741 S_028644_OFFSET(0x20));
742 ++ps_offset;
743 continue;
744 }
745
746 vs_offset = util_bitcount(vs->info.vs.export_mask & ((1u << i) - 1));
747 if (vs->info.vs.prim_id_output != 0xffffffff) {
748 if (vs_offset >= vs->info.vs.prim_id_output)
749 vs_offset++;
750 }
751 if (vs->info.vs.layer_output != 0xffffffff) {
752 if (vs_offset >= vs->info.vs.layer_output)
753 vs_offset++;
754 }
755 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
756
757 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
758 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
759 ++ps_offset;
760 }
761 }
762
763 static void
764 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
765 struct radv_pipeline *pipeline)
766 {
767 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
768 return;
769
770 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
771 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
772 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
773 radv_update_multisample_state(cmd_buffer, pipeline);
774 radv_emit_vertex_shader(cmd_buffer, pipeline);
775 radv_emit_geometry_shader(cmd_buffer, pipeline);
776 radv_emit_fragment_shader(cmd_buffer, pipeline);
777
778 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
779 pipeline->graphics.prim_restart_enable);
780
781 cmd_buffer->scratch_size_needed =
782 MAX2(cmd_buffer->scratch_size_needed,
783 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
784
785 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
786 S_0286E8_WAVES(pipeline->max_waves) |
787 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
788 cmd_buffer->state.emitted_pipeline = pipeline;
789 }
790
791 static void
792 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
793 {
794 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
795 cmd_buffer->state.dynamic.viewport.viewports);
796 }
797
798 static void
799 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
800 {
801 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
802 si_write_scissors(cmd_buffer->cs, 0, count,
803 cmd_buffer->state.dynamic.scissor.scissors);
804 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
805 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
806 }
807
808 static void
809 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
810 int index,
811 struct radv_color_buffer_info *cb)
812 {
813 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
814 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
815 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
816 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
817 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
818 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
819 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
820 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
821 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
822 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
823 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
824 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
825 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
826
827 if (is_vi) { /* DCC BASE */
828 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
829 }
830 }
831
832 static void
833 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
834 struct radv_ds_buffer_info *ds,
835 struct radv_image *image,
836 VkImageLayout layout)
837 {
838 uint32_t db_z_info = ds->db_z_info;
839
840 if (!radv_layout_has_htile(image, layout))
841 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
842
843 if (!radv_layout_can_expclear(image, layout))
844 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
845
846 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
847 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
848
849 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
850 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
851 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
852 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
853 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
854 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
855 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
856 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
857 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
858 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
859
860 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
861 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
862 ds->pa_su_poly_offset_db_fmt_cntl);
863 }
864
865 /*
866 * To hw resolve multisample images both src and dst need to have the same
867 * micro tiling mode. However we don't always know in advance when creating
868 * the images. This function gets called if we have a resolve attachment,
869 * and tests if the attachment image has the same tiling mode, then it
870 * checks if the generated framebuffer data has the same tiling mode, and
871 * updates it if not.
872 */
873 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
874 struct radv_attachment_info *att,
875 uint32_t micro_tile_mode)
876 {
877 struct radv_image *image = att->attachment->image;
878 uint32_t tile_mode_index;
879 if (image->surface.nsamples <= 1)
880 return;
881
882 if (image->surface.micro_tile_mode != micro_tile_mode) {
883 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
884 }
885
886 if (att->cb.micro_tile_mode != micro_tile_mode) {
887 tile_mode_index = image->surface.tiling_index[0];
888
889 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
890 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
891 att->cb.micro_tile_mode = micro_tile_mode;
892 }
893 }
894
895 void
896 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
897 struct radv_image *image,
898 VkClearDepthStencilValue ds_clear_value,
899 VkImageAspectFlags aspects)
900 {
901 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
902 va += image->offset + image->clear_value_offset;
903 unsigned reg_offset = 0, reg_count = 0;
904
905 if (!image->htile.size || !aspects)
906 return;
907
908 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
909 ++reg_count;
910 } else {
911 ++reg_offset;
912 va += 4;
913 }
914 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
915 ++reg_count;
916
917 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
918
919 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
920 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
921 S_370_WR_CONFIRM(1) |
922 S_370_ENGINE_SEL(V_370_PFP));
923 radeon_emit(cmd_buffer->cs, va);
924 radeon_emit(cmd_buffer->cs, va >> 32);
925 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
926 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
927 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
928 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
929
930 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
931 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
932 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
933 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
934 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
935 }
936
937 static void
938 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
939 struct radv_image *image)
940 {
941 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
942 va += image->offset + image->clear_value_offset;
943
944 if (!image->htile.size)
945 return;
946
947 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
948
949 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
950 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
951 COPY_DATA_DST_SEL(COPY_DATA_REG) |
952 COPY_DATA_COUNT_SEL);
953 radeon_emit(cmd_buffer->cs, va);
954 radeon_emit(cmd_buffer->cs, va >> 32);
955 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
956 radeon_emit(cmd_buffer->cs, 0);
957
958 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
959 radeon_emit(cmd_buffer->cs, 0);
960 }
961
962 void
963 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
964 struct radv_image *image,
965 int idx,
966 uint32_t color_values[2])
967 {
968 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
969 va += image->offset + image->clear_value_offset;
970
971 if (!image->cmask.size && !image->surface.dcc_size)
972 return;
973
974 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
975
976 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
977 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
978 S_370_WR_CONFIRM(1) |
979 S_370_ENGINE_SEL(V_370_PFP));
980 radeon_emit(cmd_buffer->cs, va);
981 radeon_emit(cmd_buffer->cs, va >> 32);
982 radeon_emit(cmd_buffer->cs, color_values[0]);
983 radeon_emit(cmd_buffer->cs, color_values[1]);
984
985 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
986 radeon_emit(cmd_buffer->cs, color_values[0]);
987 radeon_emit(cmd_buffer->cs, color_values[1]);
988 }
989
990 static void
991 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
992 struct radv_image *image,
993 int idx)
994 {
995 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
996 va += image->offset + image->clear_value_offset;
997
998 if (!image->cmask.size && !image->surface.dcc_size)
999 return;
1000
1001 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1002 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1003
1004 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1005 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1006 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1007 COPY_DATA_COUNT_SEL);
1008 radeon_emit(cmd_buffer->cs, va);
1009 radeon_emit(cmd_buffer->cs, va >> 32);
1010 radeon_emit(cmd_buffer->cs, reg >> 2);
1011 radeon_emit(cmd_buffer->cs, 0);
1012
1013 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1014 radeon_emit(cmd_buffer->cs, 0);
1015 }
1016
1017 void
1018 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1019 {
1020 int i;
1021 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1022 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1023 int dst_resolve_micro_tile_mode = -1;
1024
1025 if (subpass->has_resolve) {
1026 uint32_t a = subpass->resolve_attachments[0].attachment;
1027 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
1028 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
1029 }
1030 for (i = 0; i < subpass->color_count; ++i) {
1031 int idx = subpass->color_attachments[i].attachment;
1032 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1033
1034 if (dst_resolve_micro_tile_mode != -1) {
1035 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
1036 att, dst_resolve_micro_tile_mode);
1037 }
1038 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1039
1040 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1041 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1042
1043 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1044 }
1045
1046 for (i = subpass->color_count; i < 8; i++)
1047 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1048 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1049
1050 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1051 int idx = subpass->depth_stencil_attachment.attachment;
1052 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1053 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1054 struct radv_image *image = att->attachment->image;
1055 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1056
1057 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1058
1059 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1060 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1061 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1062 }
1063 radv_load_depth_clear_regs(cmd_buffer, image);
1064 } else {
1065 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1066 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1067 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1068 }
1069 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1070 S_028208_BR_X(framebuffer->width) |
1071 S_028208_BR_Y(framebuffer->height));
1072 }
1073
1074 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1075 {
1076 uint32_t db_count_control;
1077
1078 if(!cmd_buffer->state.active_occlusion_queries) {
1079 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1080 db_count_control = 0;
1081 } else {
1082 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1083 }
1084 } else {
1085 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1086 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1087 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1088 S_028004_ZPASS_ENABLE(1) |
1089 S_028004_SLICE_EVEN_ENABLE(1) |
1090 S_028004_SLICE_ODD_ENABLE(1);
1091 } else {
1092 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1093 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1094 }
1095 }
1096
1097 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1098 }
1099
1100 static void
1101 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1102 {
1103 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1104
1105 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1106 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1107 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1108 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1109 }
1110
1111 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1112 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1113 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1114 }
1115
1116 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1117 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1118 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1119 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1120 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1121 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1122 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1123 S_028430_STENCILOPVAL(1));
1124 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1125 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1126 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1127 S_028434_STENCILOPVAL_BF(1));
1128 }
1129
1130 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1131 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1132 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1133 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1134 }
1135
1136 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1137 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1138 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1139 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1140 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1141
1142 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1143 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1144 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1145 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1146 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1147 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1148 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1149 }
1150 }
1151
1152 cmd_buffer->state.dirty = 0;
1153 }
1154
1155 static void
1156 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1157 struct radv_pipeline *pipeline,
1158 int idx,
1159 uint64_t va,
1160 gl_shader_stage stage)
1161 {
1162 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1163 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline));
1164
1165 if (desc_set_loc->sgpr_idx == -1)
1166 return;
1167
1168 assert(!desc_set_loc->indirect);
1169 assert(desc_set_loc->num_sgprs == 2);
1170 radeon_set_sh_reg_seq(cmd_buffer->cs,
1171 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1172 radeon_emit(cmd_buffer->cs, va);
1173 radeon_emit(cmd_buffer->cs, va >> 32);
1174 }
1175
1176 static void
1177 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1178 struct radv_pipeline *pipeline,
1179 VkShaderStageFlags stages,
1180 struct radv_descriptor_set *set,
1181 unsigned idx)
1182 {
1183 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1184 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1185 idx, set->va,
1186 MESA_SHADER_FRAGMENT);
1187
1188 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1189 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1190 idx, set->va,
1191 MESA_SHADER_VERTEX);
1192
1193 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1194 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1195 idx, set->va,
1196 MESA_SHADER_GEOMETRY);
1197
1198 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1199 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1200 idx, set->va,
1201 MESA_SHADER_COMPUTE);
1202 }
1203
1204 static void
1205 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1206 struct radv_pipeline *pipeline,
1207 VkShaderStageFlags stages)
1208 {
1209 unsigned i;
1210 if (!cmd_buffer->state.descriptors_dirty)
1211 return;
1212
1213 for (i = 0; i < MAX_SETS; i++) {
1214 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1215 continue;
1216 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1217 if (!set)
1218 continue;
1219
1220 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1221 }
1222 cmd_buffer->state.descriptors_dirty = 0;
1223 }
1224
1225 static void
1226 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1227 struct radv_pipeline *pipeline,
1228 VkShaderStageFlags stages)
1229 {
1230 struct radv_pipeline_layout *layout = pipeline->layout;
1231 unsigned offset;
1232 void *ptr;
1233 uint64_t va;
1234
1235 stages &= cmd_buffer->push_constant_stages;
1236 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1237 return;
1238
1239 radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1240 16 * layout->dynamic_offset_count,
1241 256, &offset, &ptr);
1242
1243 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1244 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1245 16 * layout->dynamic_offset_count);
1246
1247 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1248 va += offset;
1249
1250 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1251 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1252 AC_UD_PUSH_CONSTANTS, va);
1253
1254 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1255 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1256 AC_UD_PUSH_CONSTANTS, va);
1257
1258 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1259 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1260 AC_UD_PUSH_CONSTANTS, va);
1261
1262 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1263 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1264 AC_UD_PUSH_CONSTANTS, va);
1265
1266 cmd_buffer->push_constant_stages &= ~stages;
1267 }
1268
1269 static void
1270 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer)
1271 {
1272 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1273 struct radv_device *device = cmd_buffer->device;
1274 uint32_t ia_multi_vgt_param;
1275 uint32_t ls_hs_config = 0;
1276
1277 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1278 cmd_buffer->cs, 4096);
1279
1280 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1281 cmd_buffer->state.pipeline->num_vertex_attribs) {
1282 unsigned vb_offset;
1283 void *vb_ptr;
1284 uint32_t i = 0;
1285 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1286 uint64_t va;
1287
1288 /* allocate some descriptor state for vertex buffers */
1289 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1290 &vb_offset, &vb_ptr);
1291
1292 for (i = 0; i < num_attribs; i++) {
1293 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1294 uint32_t offset;
1295 int vb = cmd_buffer->state.pipeline->va_binding[i];
1296 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1297 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1298
1299 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1300 va = device->ws->buffer_get_va(buffer->bo);
1301
1302 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1303 va += offset + buffer->offset;
1304 desc[0] = va;
1305 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1306 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1307 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1308 else
1309 desc[2] = buffer->size - offset;
1310 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1311 }
1312
1313 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1314 va += vb_offset;
1315
1316 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1317 AC_UD_VS_VERTEX_BUFFERS, va);
1318 }
1319
1320 cmd_buffer->state.vertex_descriptors_dirty = false;
1321 cmd_buffer->state.vb_dirty = 0;
1322 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1323 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1324
1325 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1326 radv_emit_framebuffer_state(cmd_buffer);
1327
1328 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1329 radv_emit_viewport(cmd_buffer);
1330
1331 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR))
1332 radv_emit_scissor(cmd_buffer);
1333
1334 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1335 uint32_t stages = 0;
1336
1337 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1338 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1339 S_028B54_GS_EN(1) |
1340 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1341
1342 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, stages);
1343 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer);
1344
1345 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1346 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1347 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
1348 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1349 } else {
1350 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1351 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1352 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
1353 }
1354 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1355 }
1356
1357 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1358
1359 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1360 VK_SHADER_STAGE_ALL_GRAPHICS);
1361 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1362 VK_SHADER_STAGE_ALL_GRAPHICS);
1363
1364 assert(cmd_buffer->cs->cdw <= cdw_max);
1365
1366 si_emit_cache_flush(cmd_buffer);
1367 }
1368
1369 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1370 VkPipelineStageFlags src_stage_mask)
1371 {
1372 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1373 VK_PIPELINE_STAGE_TRANSFER_BIT |
1374 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1375 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1376 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1377 }
1378
1379 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1380 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1381 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1382 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1383 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1384 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1385 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1386 VK_PIPELINE_STAGE_TRANSFER_BIT |
1387 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1388 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1389 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1390 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1391 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1392 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1393 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1394 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1395 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1396 }
1397 }
1398
1399 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1400 {
1401 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1402
1403 /* TODO: actual cache flushes */
1404 }
1405
1406 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1407 VkAttachmentReference att)
1408 {
1409 unsigned idx = att.attachment;
1410 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1411 VkImageSubresourceRange range;
1412 range.aspectMask = 0;
1413 range.baseMipLevel = view->base_mip;
1414 range.levelCount = 1;
1415 range.baseArrayLayer = view->base_layer;
1416 range.layerCount = cmd_buffer->state.framebuffer->layers;
1417
1418 radv_handle_image_transition(cmd_buffer,
1419 view->image,
1420 cmd_buffer->state.attachments[idx].current_layout,
1421 att.layout, 0, 0, range,
1422 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1423
1424 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1425
1426
1427 }
1428
1429 void
1430 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1431 const struct radv_subpass *subpass, bool transitions)
1432 {
1433 if (transitions) {
1434 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1435
1436 for (unsigned i = 0; i < subpass->color_count; ++i) {
1437 radv_handle_subpass_image_transition(cmd_buffer,
1438 subpass->color_attachments[i]);
1439 }
1440
1441 for (unsigned i = 0; i < subpass->input_count; ++i) {
1442 radv_handle_subpass_image_transition(cmd_buffer,
1443 subpass->input_attachments[i]);
1444 }
1445
1446 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1447 radv_handle_subpass_image_transition(cmd_buffer,
1448 subpass->depth_stencil_attachment);
1449 }
1450 }
1451
1452 cmd_buffer->state.subpass = subpass;
1453
1454 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1455 }
1456
1457 static void
1458 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1459 struct radv_render_pass *pass,
1460 const VkRenderPassBeginInfo *info)
1461 {
1462 struct radv_cmd_state *state = &cmd_buffer->state;
1463
1464 if (pass->attachment_count == 0) {
1465 state->attachments = NULL;
1466 return;
1467 }
1468
1469 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1470 pass->attachment_count *
1471 sizeof(state->attachments[0]),
1472 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1473 if (state->attachments == NULL) {
1474 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1475 abort();
1476 }
1477
1478 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1479 struct radv_render_pass_attachment *att = &pass->attachments[i];
1480 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1481 VkImageAspectFlags clear_aspects = 0;
1482
1483 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1484 /* color attachment */
1485 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1486 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1487 }
1488 } else {
1489 /* depthstencil attachment */
1490 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1491 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1492 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1493 }
1494 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1495 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1496 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1497 }
1498 }
1499
1500 state->attachments[i].pending_clear_aspects = clear_aspects;
1501 if (clear_aspects && info) {
1502 assert(info->clearValueCount > i);
1503 state->attachments[i].clear_value = info->pClearValues[i];
1504 }
1505
1506 state->attachments[i].current_layout = att->initial_layout;
1507 }
1508 }
1509
1510 VkResult radv_AllocateCommandBuffers(
1511 VkDevice _device,
1512 const VkCommandBufferAllocateInfo *pAllocateInfo,
1513 VkCommandBuffer *pCommandBuffers)
1514 {
1515 RADV_FROM_HANDLE(radv_device, device, _device);
1516 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1517
1518 VkResult result = VK_SUCCESS;
1519 uint32_t i;
1520
1521 memset(pCommandBuffers, 0,
1522 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1523
1524 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1525 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1526 &pCommandBuffers[i]);
1527 if (result != VK_SUCCESS)
1528 break;
1529 }
1530
1531 if (result != VK_SUCCESS)
1532 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1533 i, pCommandBuffers);
1534
1535 return result;
1536 }
1537
1538 static void
1539 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
1540 {
1541 list_del(&cmd_buffer->pool_link);
1542
1543 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1544 &cmd_buffer->upload.list, list) {
1545 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1546 list_del(&up->list);
1547 free(up);
1548 }
1549
1550 if (cmd_buffer->upload.upload_bo)
1551 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
1552 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
1553 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1554 }
1555
1556 void radv_FreeCommandBuffers(
1557 VkDevice device,
1558 VkCommandPool commandPool,
1559 uint32_t commandBufferCount,
1560 const VkCommandBuffer *pCommandBuffers)
1561 {
1562 for (uint32_t i = 0; i < commandBufferCount; i++) {
1563 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1564
1565 if (cmd_buffer)
1566 radv_cmd_buffer_destroy(cmd_buffer);
1567 }
1568 }
1569
1570 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
1571 {
1572
1573 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
1574
1575 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1576 &cmd_buffer->upload.list, list) {
1577 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1578 list_del(&up->list);
1579 free(up);
1580 }
1581
1582 cmd_buffer->scratch_size_needed = 0;
1583 cmd_buffer->compute_scratch_size_needed = 0;
1584 cmd_buffer->esgs_ring_size_needed = 0;
1585 cmd_buffer->gsvs_ring_size_needed = 0;
1586
1587 if (cmd_buffer->upload.upload_bo)
1588 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
1589 cmd_buffer->upload.upload_bo, 8);
1590 cmd_buffer->upload.offset = 0;
1591
1592 cmd_buffer->record_fail = false;
1593
1594 cmd_buffer->ring_offsets_idx = -1;
1595 }
1596
1597 VkResult radv_ResetCommandBuffer(
1598 VkCommandBuffer commandBuffer,
1599 VkCommandBufferResetFlags flags)
1600 {
1601 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1602 radv_reset_cmd_buffer(cmd_buffer);
1603 return VK_SUCCESS;
1604 }
1605
1606 VkResult radv_BeginCommandBuffer(
1607 VkCommandBuffer commandBuffer,
1608 const VkCommandBufferBeginInfo *pBeginInfo)
1609 {
1610 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1611 radv_reset_cmd_buffer(cmd_buffer);
1612
1613 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1614
1615 /* setup initial configuration into command buffer */
1616 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1617 switch (cmd_buffer->queue_family_index) {
1618 case RADV_QUEUE_GENERAL:
1619 /* Flush read caches at the beginning of CS not flushed by the kernel. */
1620 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_ICACHE |
1621 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1622 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1623 RADV_CMD_FLAG_INV_VMEM_L1 |
1624 RADV_CMD_FLAG_INV_SMEM_L1 |
1625 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
1626 RADV_CMD_FLAG_INV_GLOBAL_L2;
1627 si_init_config(cmd_buffer->device->physical_device, cmd_buffer);
1628 radv_set_db_count_control(cmd_buffer);
1629 si_emit_cache_flush(cmd_buffer);
1630 break;
1631 case RADV_QUEUE_COMPUTE:
1632 cmd_buffer->state.flush_bits = RADV_CMD_FLAG_INV_ICACHE |
1633 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1634 RADV_CMD_FLAG_INV_VMEM_L1 |
1635 RADV_CMD_FLAG_INV_SMEM_L1 |
1636 RADV_CMD_FLAG_INV_GLOBAL_L2;
1637 si_init_compute(cmd_buffer->device->physical_device, cmd_buffer);
1638 si_emit_cache_flush(cmd_buffer);
1639 break;
1640 case RADV_QUEUE_TRANSFER:
1641 default:
1642 break;
1643 }
1644 }
1645
1646 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1647 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1648 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1649
1650 struct radv_subpass *subpass =
1651 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1652
1653 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1654 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1655 }
1656
1657 return VK_SUCCESS;
1658 }
1659
1660 void radv_CmdBindVertexBuffers(
1661 VkCommandBuffer commandBuffer,
1662 uint32_t firstBinding,
1663 uint32_t bindingCount,
1664 const VkBuffer* pBuffers,
1665 const VkDeviceSize* pOffsets)
1666 {
1667 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1668 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1669
1670 /* We have to defer setting up vertex buffer since we need the buffer
1671 * stride from the pipeline. */
1672
1673 assert(firstBinding + bindingCount < MAX_VBS);
1674 for (uint32_t i = 0; i < bindingCount; i++) {
1675 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1676 vb[firstBinding + i].offset = pOffsets[i];
1677 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1678 }
1679 }
1680
1681 void radv_CmdBindIndexBuffer(
1682 VkCommandBuffer commandBuffer,
1683 VkBuffer buffer,
1684 VkDeviceSize offset,
1685 VkIndexType indexType)
1686 {
1687 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1688
1689 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1690 cmd_buffer->state.index_offset = offset;
1691 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1692 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1693 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1694 }
1695
1696
1697 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1698 struct radv_descriptor_set *set,
1699 unsigned idx)
1700 {
1701 struct radeon_winsys *ws = cmd_buffer->device->ws;
1702
1703 cmd_buffer->state.descriptors[idx] = set;
1704 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1705 if (!set)
1706 return;
1707
1708 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1709 if (set->descriptors[j])
1710 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1711
1712 if(set->bo)
1713 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1714 }
1715
1716 void radv_CmdBindDescriptorSets(
1717 VkCommandBuffer commandBuffer,
1718 VkPipelineBindPoint pipelineBindPoint,
1719 VkPipelineLayout _layout,
1720 uint32_t firstSet,
1721 uint32_t descriptorSetCount,
1722 const VkDescriptorSet* pDescriptorSets,
1723 uint32_t dynamicOffsetCount,
1724 const uint32_t* pDynamicOffsets)
1725 {
1726 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1727 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1728 unsigned dyn_idx = 0;
1729
1730 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1731 cmd_buffer->cs, MAX_SETS * 4 * 6);
1732
1733 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1734 unsigned idx = i + firstSet;
1735 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1736 radv_bind_descriptor_set(cmd_buffer, set, idx);
1737
1738 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1739 unsigned idx = j + layout->set[i].dynamic_offset_start;
1740 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1741 assert(dyn_idx < dynamicOffsetCount);
1742
1743 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1744 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1745 dst[0] = va;
1746 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1747 dst[2] = range->size;
1748 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1749 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1750 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1751 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1752 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1753 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1754 cmd_buffer->push_constant_stages |=
1755 set->layout->dynamic_shader_stages;
1756 }
1757 }
1758
1759 assert(cmd_buffer->cs->cdw <= cdw_max);
1760 }
1761
1762 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1763 VkPipelineLayout layout,
1764 VkShaderStageFlags stageFlags,
1765 uint32_t offset,
1766 uint32_t size,
1767 const void* pValues)
1768 {
1769 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1770 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1771 cmd_buffer->push_constant_stages |= stageFlags;
1772 }
1773
1774 VkResult radv_EndCommandBuffer(
1775 VkCommandBuffer commandBuffer)
1776 {
1777 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1778
1779 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
1780 si_emit_cache_flush(cmd_buffer);
1781
1782 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1783 cmd_buffer->record_fail)
1784 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1785 return VK_SUCCESS;
1786 }
1787
1788 static void
1789 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1790 {
1791 struct radeon_winsys *ws = cmd_buffer->device->ws;
1792 struct radv_shader_variant *compute_shader;
1793 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1794 uint64_t va;
1795
1796 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1797 return;
1798
1799 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1800
1801 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1802 va = ws->buffer_get_va(compute_shader->bo);
1803
1804 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1805
1806 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1807 cmd_buffer->cs, 16);
1808
1809 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1810 radeon_emit(cmd_buffer->cs, va >> 8);
1811 radeon_emit(cmd_buffer->cs, va >> 40);
1812
1813 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1814 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1815 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1816
1817
1818 cmd_buffer->compute_scratch_size_needed =
1819 MAX2(cmd_buffer->compute_scratch_size_needed,
1820 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1821
1822 /* change these once we have scratch support */
1823 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1824 S_00B860_WAVES(pipeline->max_waves) |
1825 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1826
1827 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1828 radeon_emit(cmd_buffer->cs,
1829 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1830 radeon_emit(cmd_buffer->cs,
1831 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1832 radeon_emit(cmd_buffer->cs,
1833 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1834
1835 assert(cmd_buffer->cs->cdw <= cdw_max);
1836 }
1837
1838
1839 void radv_CmdBindPipeline(
1840 VkCommandBuffer commandBuffer,
1841 VkPipelineBindPoint pipelineBindPoint,
1842 VkPipeline _pipeline)
1843 {
1844 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1845 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1846
1847 for (unsigned i = 0; i < MAX_SETS; i++) {
1848 if (cmd_buffer->state.descriptors[i])
1849 cmd_buffer->state.descriptors_dirty |= (1 << i);
1850 }
1851
1852 switch (pipelineBindPoint) {
1853 case VK_PIPELINE_BIND_POINT_COMPUTE:
1854 cmd_buffer->state.compute_pipeline = pipeline;
1855 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
1856 break;
1857 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1858 cmd_buffer->state.pipeline = pipeline;
1859 cmd_buffer->state.vertex_descriptors_dirty = true;
1860 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1861 cmd_buffer->push_constant_stages |= pipeline->active_stages;
1862
1863 /* Apply the dynamic state from the pipeline */
1864 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
1865 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
1866 &pipeline->dynamic_state,
1867 pipeline->dynamic_state_mask);
1868
1869 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
1870 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
1871 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
1872 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
1873
1874 if (radv_pipeline_has_gs(pipeline)) {
1875 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1876 AC_UD_SCRATCH_RING_OFFSETS);
1877 if (cmd_buffer->ring_offsets_idx == -1)
1878 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
1879 else if (loc->sgpr_idx != -1)
1880 assert(loc->sgpr_idx != cmd_buffer->ring_offsets_idx);
1881 }
1882 break;
1883 default:
1884 assert(!"invalid bind point");
1885 break;
1886 }
1887 }
1888
1889 void radv_CmdSetViewport(
1890 VkCommandBuffer commandBuffer,
1891 uint32_t firstViewport,
1892 uint32_t viewportCount,
1893 const VkViewport* pViewports)
1894 {
1895 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1896
1897 const uint32_t total_count = firstViewport + viewportCount;
1898 if (cmd_buffer->state.dynamic.viewport.count < total_count)
1899 cmd_buffer->state.dynamic.viewport.count = total_count;
1900
1901 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
1902 pViewports, viewportCount * sizeof(*pViewports));
1903
1904 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
1905 }
1906
1907 void radv_CmdSetScissor(
1908 VkCommandBuffer commandBuffer,
1909 uint32_t firstScissor,
1910 uint32_t scissorCount,
1911 const VkRect2D* pScissors)
1912 {
1913 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1914
1915 const uint32_t total_count = firstScissor + scissorCount;
1916 if (cmd_buffer->state.dynamic.scissor.count < total_count)
1917 cmd_buffer->state.dynamic.scissor.count = total_count;
1918
1919 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
1920 pScissors, scissorCount * sizeof(*pScissors));
1921 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1922 }
1923
1924 void radv_CmdSetLineWidth(
1925 VkCommandBuffer commandBuffer,
1926 float lineWidth)
1927 {
1928 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1929 cmd_buffer->state.dynamic.line_width = lineWidth;
1930 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1931 }
1932
1933 void radv_CmdSetDepthBias(
1934 VkCommandBuffer commandBuffer,
1935 float depthBiasConstantFactor,
1936 float depthBiasClamp,
1937 float depthBiasSlopeFactor)
1938 {
1939 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1940
1941 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
1942 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
1943 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
1944
1945 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1946 }
1947
1948 void radv_CmdSetBlendConstants(
1949 VkCommandBuffer commandBuffer,
1950 const float blendConstants[4])
1951 {
1952 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1953
1954 memcpy(cmd_buffer->state.dynamic.blend_constants,
1955 blendConstants, sizeof(float) * 4);
1956
1957 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
1958 }
1959
1960 void radv_CmdSetDepthBounds(
1961 VkCommandBuffer commandBuffer,
1962 float minDepthBounds,
1963 float maxDepthBounds)
1964 {
1965 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1966
1967 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
1968 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
1969
1970 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
1971 }
1972
1973 void radv_CmdSetStencilCompareMask(
1974 VkCommandBuffer commandBuffer,
1975 VkStencilFaceFlags faceMask,
1976 uint32_t compareMask)
1977 {
1978 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1979
1980 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1981 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
1982 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1983 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
1984
1985 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1986 }
1987
1988 void radv_CmdSetStencilWriteMask(
1989 VkCommandBuffer commandBuffer,
1990 VkStencilFaceFlags faceMask,
1991 uint32_t writeMask)
1992 {
1993 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1994
1995 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1996 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
1997 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1998 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
1999
2000 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2001 }
2002
2003 void radv_CmdSetStencilReference(
2004 VkCommandBuffer commandBuffer,
2005 VkStencilFaceFlags faceMask,
2006 uint32_t reference)
2007 {
2008 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2009
2010 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2011 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2012 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2013 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2014
2015 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2016 }
2017
2018
2019 void radv_CmdExecuteCommands(
2020 VkCommandBuffer commandBuffer,
2021 uint32_t commandBufferCount,
2022 const VkCommandBuffer* pCmdBuffers)
2023 {
2024 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2025
2026 for (uint32_t i = 0; i < commandBufferCount; i++) {
2027 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2028
2029 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2030 secondary->scratch_size_needed);
2031 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2032 secondary->compute_scratch_size_needed);
2033
2034 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2035 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2036 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2037 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2038
2039 if (secondary->ring_offsets_idx != -1) {
2040 if (primary->ring_offsets_idx == -1)
2041 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2042 else
2043 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2044 }
2045 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2046 }
2047
2048 /* if we execute secondary we need to re-emit out pipelines */
2049 if (commandBufferCount) {
2050 primary->state.emitted_pipeline = NULL;
2051 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2052 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2053 }
2054 }
2055
2056 VkResult radv_CreateCommandPool(
2057 VkDevice _device,
2058 const VkCommandPoolCreateInfo* pCreateInfo,
2059 const VkAllocationCallbacks* pAllocator,
2060 VkCommandPool* pCmdPool)
2061 {
2062 RADV_FROM_HANDLE(radv_device, device, _device);
2063 struct radv_cmd_pool *pool;
2064
2065 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2066 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2067 if (pool == NULL)
2068 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2069
2070 if (pAllocator)
2071 pool->alloc = *pAllocator;
2072 else
2073 pool->alloc = device->alloc;
2074
2075 list_inithead(&pool->cmd_buffers);
2076
2077 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2078
2079 *pCmdPool = radv_cmd_pool_to_handle(pool);
2080
2081 return VK_SUCCESS;
2082
2083 }
2084
2085 void radv_DestroyCommandPool(
2086 VkDevice _device,
2087 VkCommandPool commandPool,
2088 const VkAllocationCallbacks* pAllocator)
2089 {
2090 RADV_FROM_HANDLE(radv_device, device, _device);
2091 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2092
2093 if (!pool)
2094 return;
2095
2096 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2097 &pool->cmd_buffers, pool_link) {
2098 radv_cmd_buffer_destroy(cmd_buffer);
2099 }
2100
2101 vk_free2(&device->alloc, pAllocator, pool);
2102 }
2103
2104 VkResult radv_ResetCommandPool(
2105 VkDevice device,
2106 VkCommandPool commandPool,
2107 VkCommandPoolResetFlags flags)
2108 {
2109 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2110
2111 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2112 &pool->cmd_buffers, pool_link) {
2113 radv_reset_cmd_buffer(cmd_buffer);
2114 }
2115
2116 return VK_SUCCESS;
2117 }
2118
2119 void radv_TrimCommandPoolKHR(
2120 VkDevice device,
2121 VkCommandPool commandPool,
2122 VkCommandPoolTrimFlagsKHR flags)
2123 {
2124 }
2125
2126 void radv_CmdBeginRenderPass(
2127 VkCommandBuffer commandBuffer,
2128 const VkRenderPassBeginInfo* pRenderPassBegin,
2129 VkSubpassContents contents)
2130 {
2131 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2132 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2133 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2134
2135 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2136 cmd_buffer->cs, 2048);
2137
2138 cmd_buffer->state.framebuffer = framebuffer;
2139 cmd_buffer->state.pass = pass;
2140 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2141 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2142
2143 si_emit_cache_flush(cmd_buffer);
2144
2145 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2146 assert(cmd_buffer->cs->cdw <= cdw_max);
2147
2148 radv_cmd_buffer_clear_subpass(cmd_buffer);
2149 }
2150
2151 void radv_CmdNextSubpass(
2152 VkCommandBuffer commandBuffer,
2153 VkSubpassContents contents)
2154 {
2155 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2156
2157 si_emit_cache_flush(cmd_buffer);
2158 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2159
2160 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2161 2048);
2162
2163 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2164 radv_cmd_buffer_clear_subpass(cmd_buffer);
2165 }
2166
2167 void radv_CmdDraw(
2168 VkCommandBuffer commandBuffer,
2169 uint32_t vertexCount,
2170 uint32_t instanceCount,
2171 uint32_t firstVertex,
2172 uint32_t firstInstance)
2173 {
2174 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2175 radv_cmd_buffer_flush_state(cmd_buffer);
2176
2177 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2178
2179 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2180 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2181 if (loc->sgpr_idx != -1) {
2182 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2183 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2184 radeon_emit(cmd_buffer->cs, firstVertex);
2185 radeon_emit(cmd_buffer->cs, firstInstance);
2186 radeon_emit(cmd_buffer->cs, 0);
2187 }
2188 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2189 radeon_emit(cmd_buffer->cs, instanceCount);
2190
2191 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2192 radeon_emit(cmd_buffer->cs, vertexCount);
2193 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2194 S_0287F0_USE_OPAQUE(0));
2195
2196 assert(cmd_buffer->cs->cdw <= cdw_max);
2197
2198 radv_cmd_buffer_trace_emit(cmd_buffer);
2199 }
2200
2201 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2202 {
2203 uint32_t primitive_reset_index = cmd_buffer->state.last_primitive_reset_index ? 0xffffffffu : 0xffffu;
2204
2205 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
2206 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
2207 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
2208 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2209 primitive_reset_index);
2210 }
2211 }
2212
2213 void radv_CmdDrawIndexed(
2214 VkCommandBuffer commandBuffer,
2215 uint32_t indexCount,
2216 uint32_t instanceCount,
2217 uint32_t firstIndex,
2218 int32_t vertexOffset,
2219 uint32_t firstInstance)
2220 {
2221 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2222 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2223 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2224 uint64_t index_va;
2225
2226 radv_cmd_buffer_flush_state(cmd_buffer);
2227 radv_emit_primitive_reset_index(cmd_buffer);
2228
2229 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2230
2231 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2232 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2233
2234 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2235 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2236 if (loc->sgpr_idx != -1) {
2237 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2238 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2239 radeon_emit(cmd_buffer->cs, vertexOffset);
2240 radeon_emit(cmd_buffer->cs, firstInstance);
2241 radeon_emit(cmd_buffer->cs, 0);
2242 }
2243 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2244 radeon_emit(cmd_buffer->cs, instanceCount);
2245
2246 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2247 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2248 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2249 radeon_emit(cmd_buffer->cs, index_max_size);
2250 radeon_emit(cmd_buffer->cs, index_va);
2251 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2252 radeon_emit(cmd_buffer->cs, indexCount);
2253 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2254
2255 assert(cmd_buffer->cs->cdw <= cdw_max);
2256 radv_cmd_buffer_trace_emit(cmd_buffer);
2257 }
2258
2259 static void
2260 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2261 VkBuffer _buffer,
2262 VkDeviceSize offset,
2263 VkBuffer _count_buffer,
2264 VkDeviceSize count_offset,
2265 uint32_t draw_count,
2266 uint32_t stride,
2267 bool indexed)
2268 {
2269 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2270 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2271 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2272 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2273 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2274 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2275 indirect_va += offset + buffer->offset;
2276 uint64_t count_va = 0;
2277
2278 if (count_buffer) {
2279 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2280 count_va += count_offset + count_buffer->offset;
2281 }
2282
2283 if (!draw_count)
2284 return;
2285
2286 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2287
2288 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2289 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2290 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2291 assert(loc->sgpr_idx != -1);
2292 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2293 radeon_emit(cs, 1);
2294 radeon_emit(cs, indirect_va);
2295 radeon_emit(cs, indirect_va >> 32);
2296
2297 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2298 PKT3_DRAW_INDIRECT_MULTI,
2299 8, false));
2300 radeon_emit(cs, 0);
2301 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2302 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2303 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2304 S_2C3_DRAW_INDEX_ENABLE(1) |
2305 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2306 radeon_emit(cs, draw_count); /* count */
2307 radeon_emit(cs, count_va); /* count_addr */
2308 radeon_emit(cs, count_va >> 32);
2309 radeon_emit(cs, stride); /* stride */
2310 radeon_emit(cs, di_src_sel);
2311 radv_cmd_buffer_trace_emit(cmd_buffer);
2312 }
2313
2314 static void
2315 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2316 VkBuffer buffer,
2317 VkDeviceSize offset,
2318 VkBuffer countBuffer,
2319 VkDeviceSize countBufferOffset,
2320 uint32_t maxDrawCount,
2321 uint32_t stride)
2322 {
2323 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2324 radv_cmd_buffer_flush_state(cmd_buffer);
2325
2326 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2327 cmd_buffer->cs, 14);
2328
2329 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2330 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2331
2332 assert(cmd_buffer->cs->cdw <= cdw_max);
2333 }
2334
2335 static void
2336 radv_cmd_draw_indexed_indirect_count(
2337 VkCommandBuffer commandBuffer,
2338 VkBuffer buffer,
2339 VkDeviceSize offset,
2340 VkBuffer countBuffer,
2341 VkDeviceSize countBufferOffset,
2342 uint32_t maxDrawCount,
2343 uint32_t stride)
2344 {
2345 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2346 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2347 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2348 uint64_t index_va;
2349 radv_cmd_buffer_flush_state(cmd_buffer);
2350 radv_emit_primitive_reset_index(cmd_buffer);
2351
2352 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2353 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2354
2355 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2356
2357 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2358 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2359
2360 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2361 radeon_emit(cmd_buffer->cs, index_va);
2362 radeon_emit(cmd_buffer->cs, index_va >> 32);
2363
2364 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2365 radeon_emit(cmd_buffer->cs, index_max_size);
2366
2367 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2368 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2369
2370 assert(cmd_buffer->cs->cdw <= cdw_max);
2371 }
2372
2373 void radv_CmdDrawIndirect(
2374 VkCommandBuffer commandBuffer,
2375 VkBuffer buffer,
2376 VkDeviceSize offset,
2377 uint32_t drawCount,
2378 uint32_t stride)
2379 {
2380 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2381 VK_NULL_HANDLE, 0, drawCount, stride);
2382 }
2383
2384 void radv_CmdDrawIndexedIndirect(
2385 VkCommandBuffer commandBuffer,
2386 VkBuffer buffer,
2387 VkDeviceSize offset,
2388 uint32_t drawCount,
2389 uint32_t stride)
2390 {
2391 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2392 VK_NULL_HANDLE, 0, drawCount, stride);
2393 }
2394
2395 void radv_CmdDrawIndirectCountAMD(
2396 VkCommandBuffer commandBuffer,
2397 VkBuffer buffer,
2398 VkDeviceSize offset,
2399 VkBuffer countBuffer,
2400 VkDeviceSize countBufferOffset,
2401 uint32_t maxDrawCount,
2402 uint32_t stride)
2403 {
2404 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2405 countBuffer, countBufferOffset,
2406 maxDrawCount, stride);
2407 }
2408
2409 void radv_CmdDrawIndexedIndirectCountAMD(
2410 VkCommandBuffer commandBuffer,
2411 VkBuffer buffer,
2412 VkDeviceSize offset,
2413 VkBuffer countBuffer,
2414 VkDeviceSize countBufferOffset,
2415 uint32_t maxDrawCount,
2416 uint32_t stride)
2417 {
2418 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2419 countBuffer, countBufferOffset,
2420 maxDrawCount, stride);
2421 }
2422
2423 static void
2424 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2425 {
2426 radv_emit_compute_pipeline(cmd_buffer);
2427 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2428 VK_SHADER_STAGE_COMPUTE_BIT);
2429 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2430 VK_SHADER_STAGE_COMPUTE_BIT);
2431 si_emit_cache_flush(cmd_buffer);
2432 }
2433
2434 void radv_CmdDispatch(
2435 VkCommandBuffer commandBuffer,
2436 uint32_t x,
2437 uint32_t y,
2438 uint32_t z)
2439 {
2440 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2441
2442 radv_flush_compute_state(cmd_buffer);
2443
2444 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2445
2446 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2447 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2448 if (loc->sgpr_idx != -1) {
2449 assert(!loc->indirect);
2450 assert(loc->num_sgprs == 3);
2451 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2452 radeon_emit(cmd_buffer->cs, x);
2453 radeon_emit(cmd_buffer->cs, y);
2454 radeon_emit(cmd_buffer->cs, z);
2455 }
2456
2457 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2458 PKT3_SHADER_TYPE_S(1));
2459 radeon_emit(cmd_buffer->cs, x);
2460 radeon_emit(cmd_buffer->cs, y);
2461 radeon_emit(cmd_buffer->cs, z);
2462 radeon_emit(cmd_buffer->cs, 1);
2463
2464 assert(cmd_buffer->cs->cdw <= cdw_max);
2465 radv_cmd_buffer_trace_emit(cmd_buffer);
2466 }
2467
2468 void radv_CmdDispatchIndirect(
2469 VkCommandBuffer commandBuffer,
2470 VkBuffer _buffer,
2471 VkDeviceSize offset)
2472 {
2473 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2474 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2475 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2476 va += buffer->offset + offset;
2477
2478 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2479
2480 radv_flush_compute_state(cmd_buffer);
2481
2482 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2483 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2484 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2485 if (loc->sgpr_idx != -1) {
2486 for (unsigned i = 0; i < 3; ++i) {
2487 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2488 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2489 COPY_DATA_DST_SEL(COPY_DATA_REG));
2490 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2491 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2492 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2493 radeon_emit(cmd_buffer->cs, 0);
2494 }
2495 }
2496
2497 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2498 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2499 PKT3_SHADER_TYPE_S(1));
2500 radeon_emit(cmd_buffer->cs, va);
2501 radeon_emit(cmd_buffer->cs, va >> 32);
2502 radeon_emit(cmd_buffer->cs, 1);
2503 } else {
2504 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2505 PKT3_SHADER_TYPE_S(1));
2506 radeon_emit(cmd_buffer->cs, 1);
2507 radeon_emit(cmd_buffer->cs, va);
2508 radeon_emit(cmd_buffer->cs, va >> 32);
2509
2510 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2511 PKT3_SHADER_TYPE_S(1));
2512 radeon_emit(cmd_buffer->cs, 0);
2513 radeon_emit(cmd_buffer->cs, 1);
2514 }
2515
2516 assert(cmd_buffer->cs->cdw <= cdw_max);
2517 radv_cmd_buffer_trace_emit(cmd_buffer);
2518 }
2519
2520 void radv_unaligned_dispatch(
2521 struct radv_cmd_buffer *cmd_buffer,
2522 uint32_t x,
2523 uint32_t y,
2524 uint32_t z)
2525 {
2526 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2527 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2528 uint32_t blocks[3], remainder[3];
2529
2530 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2531 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2532 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2533
2534 /* If aligned, these should be an entire block size, not 0 */
2535 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2536 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2537 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2538
2539 radv_flush_compute_state(cmd_buffer);
2540
2541 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2542
2543 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2544 radeon_emit(cmd_buffer->cs,
2545 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2546 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2547 radeon_emit(cmd_buffer->cs,
2548 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2549 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2550 radeon_emit(cmd_buffer->cs,
2551 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2552 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2553
2554 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2555 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2556 if (loc->sgpr_idx != -1) {
2557 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2558 radeon_emit(cmd_buffer->cs, blocks[0]);
2559 radeon_emit(cmd_buffer->cs, blocks[1]);
2560 radeon_emit(cmd_buffer->cs, blocks[2]);
2561 }
2562 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2563 PKT3_SHADER_TYPE_S(1));
2564 radeon_emit(cmd_buffer->cs, blocks[0]);
2565 radeon_emit(cmd_buffer->cs, blocks[1]);
2566 radeon_emit(cmd_buffer->cs, blocks[2]);
2567 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2568 S_00B800_PARTIAL_TG_EN(1));
2569
2570 assert(cmd_buffer->cs->cdw <= cdw_max);
2571 radv_cmd_buffer_trace_emit(cmd_buffer);
2572 }
2573
2574 void radv_CmdEndRenderPass(
2575 VkCommandBuffer commandBuffer)
2576 {
2577 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2578
2579 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2580
2581 si_emit_cache_flush(cmd_buffer);
2582 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2583
2584 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2585 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2586 radv_handle_subpass_image_transition(cmd_buffer,
2587 (VkAttachmentReference){i, layout});
2588 }
2589
2590 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2591
2592 cmd_buffer->state.pass = NULL;
2593 cmd_buffer->state.subpass = NULL;
2594 cmd_buffer->state.attachments = NULL;
2595 cmd_buffer->state.framebuffer = NULL;
2596 }
2597
2598
2599 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2600 struct radv_image *image)
2601 {
2602
2603 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2604 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2605
2606 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->htile.offset,
2607 image->htile.size, 0xffffffff);
2608
2609 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2610 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2611 RADV_CMD_FLAG_INV_VMEM_L1 |
2612 RADV_CMD_FLAG_INV_GLOBAL_L2;
2613 }
2614
2615 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2616 struct radv_image *image,
2617 VkImageLayout src_layout,
2618 VkImageLayout dst_layout,
2619 VkImageSubresourceRange range,
2620 VkImageAspectFlags pending_clears)
2621 {
2622 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2623 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2624 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2625 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2626 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2627 /* The clear will initialize htile. */
2628 return;
2629 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2630 radv_layout_has_htile(image, dst_layout)) {
2631 /* TODO: merge with the clear if applicable */
2632 radv_initialize_htile(cmd_buffer, image);
2633 } else if (!radv_layout_has_htile(image, src_layout) &&
2634 radv_layout_has_htile(image, dst_layout)) {
2635 radv_initialize_htile(cmd_buffer, image);
2636 } else if ((radv_layout_has_htile(image, src_layout) &&
2637 !radv_layout_has_htile(image, dst_layout)) ||
2638 (radv_layout_is_htile_compressed(image, src_layout) &&
2639 !radv_layout_is_htile_compressed(image, dst_layout))) {
2640
2641 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2642 range.baseMipLevel = 0;
2643 range.levelCount = 1;
2644
2645 radv_decompress_depth_image_inplace(cmd_buffer, image, &range);
2646 }
2647 }
2648
2649 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2650 struct radv_image *image, uint32_t value)
2651 {
2652 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2653 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2654
2655 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2656 image->cmask.size, value);
2657
2658 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2659 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2660 RADV_CMD_FLAG_INV_VMEM_L1 |
2661 RADV_CMD_FLAG_INV_GLOBAL_L2;
2662 }
2663
2664 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2665 struct radv_image *image,
2666 VkImageLayout src_layout,
2667 VkImageLayout dst_layout,
2668 unsigned src_queue_mask,
2669 unsigned dst_queue_mask,
2670 VkImageSubresourceRange range,
2671 VkImageAspectFlags pending_clears)
2672 {
2673 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2674 if (image->fmask.size)
2675 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2676 else
2677 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2678 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2679 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2680 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2681 }
2682 }
2683
2684 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2685 struct radv_image *image, uint32_t value)
2686 {
2687
2688 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2689 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2690
2691 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2692 image->surface.dcc_size, value);
2693
2694 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2695 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2696 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2697 RADV_CMD_FLAG_INV_VMEM_L1 |
2698 RADV_CMD_FLAG_INV_GLOBAL_L2;
2699 }
2700
2701 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2702 struct radv_image *image,
2703 VkImageLayout src_layout,
2704 VkImageLayout dst_layout,
2705 unsigned src_queue_mask,
2706 unsigned dst_queue_mask,
2707 VkImageSubresourceRange range,
2708 VkImageAspectFlags pending_clears)
2709 {
2710 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2711 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2712 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2713 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2714 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2715 }
2716 }
2717
2718 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2719 struct radv_image *image,
2720 VkImageLayout src_layout,
2721 VkImageLayout dst_layout,
2722 uint32_t src_family,
2723 uint32_t dst_family,
2724 VkImageSubresourceRange range,
2725 VkImageAspectFlags pending_clears)
2726 {
2727 if (image->exclusive && src_family != dst_family) {
2728 /* This is an acquire or a release operation and there will be
2729 * a corresponding release/acquire. Do the transition in the
2730 * most flexible queue. */
2731
2732 assert(src_family == cmd_buffer->queue_family_index ||
2733 dst_family == cmd_buffer->queue_family_index);
2734
2735 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
2736 return;
2737
2738 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
2739 (src_family == RADV_QUEUE_GENERAL ||
2740 dst_family == RADV_QUEUE_GENERAL))
2741 return;
2742 }
2743
2744 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
2745 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
2746
2747 if (image->htile.size)
2748 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2749 dst_layout, range, pending_clears);
2750
2751 if (image->cmask.size)
2752 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2753 dst_layout, src_queue_mask,
2754 dst_queue_mask, range,
2755 pending_clears);
2756
2757 if (image->surface.dcc_size)
2758 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2759 dst_layout, src_queue_mask,
2760 dst_queue_mask, range,
2761 pending_clears);
2762 }
2763
2764 void radv_CmdPipelineBarrier(
2765 VkCommandBuffer commandBuffer,
2766 VkPipelineStageFlags srcStageMask,
2767 VkPipelineStageFlags destStageMask,
2768 VkBool32 byRegion,
2769 uint32_t memoryBarrierCount,
2770 const VkMemoryBarrier* pMemoryBarriers,
2771 uint32_t bufferMemoryBarrierCount,
2772 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2773 uint32_t imageMemoryBarrierCount,
2774 const VkImageMemoryBarrier* pImageMemoryBarriers)
2775 {
2776 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2777 VkAccessFlags src_flags = 0;
2778 VkAccessFlags dst_flags = 0;
2779 uint32_t b;
2780 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2781 src_flags |= pMemoryBarriers[i].srcAccessMask;
2782 dst_flags |= pMemoryBarriers[i].dstAccessMask;
2783 }
2784
2785 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2786 src_flags |= pBufferMemoryBarriers[i].srcAccessMask;
2787 dst_flags |= pBufferMemoryBarriers[i].dstAccessMask;
2788 }
2789
2790 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2791 src_flags |= pImageMemoryBarriers[i].srcAccessMask;
2792 dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
2793 }
2794
2795 enum radv_cmd_flush_bits flush_bits = 0;
2796 for_each_bit(b, src_flags) {
2797 switch ((VkAccessFlagBits)(1 << b)) {
2798 case VK_ACCESS_SHADER_WRITE_BIT:
2799 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2800 break;
2801 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2802 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2803 break;
2804 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2805 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2806 break;
2807 case VK_ACCESS_TRANSFER_WRITE_BIT:
2808 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2809 break;
2810 default:
2811 break;
2812 }
2813 }
2814 cmd_buffer->state.flush_bits |= flush_bits;
2815
2816 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2817 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2818 radv_handle_image_transition(cmd_buffer, image,
2819 pImageMemoryBarriers[i].oldLayout,
2820 pImageMemoryBarriers[i].newLayout,
2821 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2822 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2823 pImageMemoryBarriers[i].subresourceRange,
2824 0);
2825 }
2826
2827 flush_bits = 0;
2828
2829 for_each_bit(b, dst_flags) {
2830 switch ((VkAccessFlagBits)(1 << b)) {
2831 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2832 case VK_ACCESS_INDEX_READ_BIT:
2833 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2834 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2835 break;
2836 case VK_ACCESS_UNIFORM_READ_BIT:
2837 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2838 break;
2839 case VK_ACCESS_SHADER_READ_BIT:
2840 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2841 break;
2842 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2843 case VK_ACCESS_TRANSFER_READ_BIT:
2844 case VK_ACCESS_TRANSFER_WRITE_BIT:
2845 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2846 flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER | RADV_CMD_FLAG_INV_GLOBAL_L2;
2847 default:
2848 break;
2849 }
2850 }
2851
2852 flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2853 RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2854
2855 cmd_buffer->state.flush_bits |= flush_bits;
2856 }
2857
2858
2859 static void write_event(struct radv_cmd_buffer *cmd_buffer,
2860 struct radv_event *event,
2861 VkPipelineStageFlags stageMask,
2862 unsigned value)
2863 {
2864 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2865 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2866
2867 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2868
2869 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
2870
2871 /* TODO: this is overkill. Probably should figure something out from
2872 * the stage mask. */
2873
2874 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
2875 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2876 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2877 EVENT_INDEX(5));
2878 radeon_emit(cs, va);
2879 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2880 radeon_emit(cs, 2);
2881 radeon_emit(cs, 0);
2882 }
2883
2884 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2885 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2886 EVENT_INDEX(5));
2887 radeon_emit(cs, va);
2888 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2889 radeon_emit(cs, value);
2890 radeon_emit(cs, 0);
2891
2892 assert(cmd_buffer->cs->cdw <= cdw_max);
2893 }
2894
2895 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
2896 VkEvent _event,
2897 VkPipelineStageFlags stageMask)
2898 {
2899 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2900 RADV_FROM_HANDLE(radv_event, event, _event);
2901
2902 write_event(cmd_buffer, event, stageMask, 1);
2903 }
2904
2905 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
2906 VkEvent _event,
2907 VkPipelineStageFlags stageMask)
2908 {
2909 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2910 RADV_FROM_HANDLE(radv_event, event, _event);
2911
2912 write_event(cmd_buffer, event, stageMask, 0);
2913 }
2914
2915 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
2916 uint32_t eventCount,
2917 const VkEvent* pEvents,
2918 VkPipelineStageFlags srcStageMask,
2919 VkPipelineStageFlags dstStageMask,
2920 uint32_t memoryBarrierCount,
2921 const VkMemoryBarrier* pMemoryBarriers,
2922 uint32_t bufferMemoryBarrierCount,
2923 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2924 uint32_t imageMemoryBarrierCount,
2925 const VkImageMemoryBarrier* pImageMemoryBarriers)
2926 {
2927 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2928 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2929
2930 for (unsigned i = 0; i < eventCount; ++i) {
2931 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
2932 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2933
2934 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2935
2936 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
2937
2938 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
2939 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
2940 radeon_emit(cs, va);
2941 radeon_emit(cs, va >> 32);
2942 radeon_emit(cs, 1); /* reference value */
2943 radeon_emit(cs, 0xffffffff); /* mask */
2944 radeon_emit(cs, 4); /* poll interval */
2945
2946 assert(cmd_buffer->cs->cdw <= cdw_max);
2947 }
2948
2949
2950 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2951 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2952
2953 radv_handle_image_transition(cmd_buffer, image,
2954 pImageMemoryBarriers[i].oldLayout,
2955 pImageMemoryBarriers[i].newLayout,
2956 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2957 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2958 pImageMemoryBarriers[i].subresourceRange,
2959 0);
2960 }
2961
2962 /* TODO: figure out how to do memory barriers without waiting */
2963 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
2964 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2965 RADV_CMD_FLAG_INV_VMEM_L1 |
2966 RADV_CMD_FLAG_INV_SMEM_L1;
2967 }