2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
33 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
57 VkImageLayout dst_layout
,
60 const VkImageSubresourceRange
*range
,
61 struct radv_sample_locations_state
*sample_locs
);
63 const struct radv_dynamic_state default_dynamic_state
= {
76 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
81 .stencil_compare_mask
= {
85 .stencil_write_mask
= {
89 .stencil_reference
= {
96 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
97 const struct radv_dynamic_state
*src
)
99 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
100 uint32_t copy_mask
= src
->mask
;
101 uint32_t dest_mask
= 0;
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
106 dest
->viewport
.count
= src
->viewport
.count
;
107 dest
->scissor
.count
= src
->scissor
.count
;
108 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
109 dest
->sample_location
.count
= src
->sample_location
.count
;
111 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
112 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
113 src
->viewport
.count
* sizeof(VkViewport
))) {
114 typed_memcpy(dest
->viewport
.viewports
,
115 src
->viewport
.viewports
,
116 src
->viewport
.count
);
117 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
121 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
122 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
123 src
->scissor
.count
* sizeof(VkRect2D
))) {
124 typed_memcpy(dest
->scissor
.scissors
,
125 src
->scissor
.scissors
, src
->scissor
.count
);
126 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
130 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
131 if (dest
->line_width
!= src
->line_width
) {
132 dest
->line_width
= src
->line_width
;
133 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
137 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
138 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
139 sizeof(src
->depth_bias
))) {
140 dest
->depth_bias
= src
->depth_bias
;
141 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
145 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
146 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
147 sizeof(src
->blend_constants
))) {
148 typed_memcpy(dest
->blend_constants
,
149 src
->blend_constants
, 4);
150 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
154 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
155 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
156 sizeof(src
->depth_bounds
))) {
157 dest
->depth_bounds
= src
->depth_bounds
;
158 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
162 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
163 if (memcmp(&dest
->stencil_compare_mask
,
164 &src
->stencil_compare_mask
,
165 sizeof(src
->stencil_compare_mask
))) {
166 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
167 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
171 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
172 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
173 sizeof(src
->stencil_write_mask
))) {
174 dest
->stencil_write_mask
= src
->stencil_write_mask
;
175 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
179 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
180 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
181 sizeof(src
->stencil_reference
))) {
182 dest
->stencil_reference
= src
->stencil_reference
;
183 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
187 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
188 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
189 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
190 typed_memcpy(dest
->discard_rectangle
.rectangles
,
191 src
->discard_rectangle
.rectangles
,
192 src
->discard_rectangle
.count
);
193 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
197 if (copy_mask
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
198 if (dest
->sample_location
.per_pixel
!= src
->sample_location
.per_pixel
||
199 dest
->sample_location
.grid_size
.width
!= src
->sample_location
.grid_size
.width
||
200 dest
->sample_location
.grid_size
.height
!= src
->sample_location
.grid_size
.height
||
201 memcmp(&dest
->sample_location
.locations
,
202 &src
->sample_location
.locations
,
203 src
->sample_location
.count
* sizeof(VkSampleLocationEXT
))) {
204 dest
->sample_location
.per_pixel
= src
->sample_location
.per_pixel
;
205 dest
->sample_location
.grid_size
= src
->sample_location
.grid_size
;
206 typed_memcpy(dest
->sample_location
.locations
,
207 src
->sample_location
.locations
,
208 src
->sample_location
.count
);
209 dest_mask
|= RADV_DYNAMIC_SAMPLE_LOCATIONS
;
213 cmd_buffer
->state
.dirty
|= dest_mask
;
217 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
218 struct radv_pipeline
*pipeline
)
220 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
221 struct radv_shader_info
*info
;
223 if (!pipeline
->streamout_shader
)
226 info
= &pipeline
->streamout_shader
->info
.info
;
227 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
228 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
230 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
235 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
236 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
239 enum ring_type
radv_queue_family_to_ring(int f
) {
241 case RADV_QUEUE_GENERAL
:
243 case RADV_QUEUE_COMPUTE
:
245 case RADV_QUEUE_TRANSFER
:
248 unreachable("Unknown queue family");
252 static VkResult
radv_create_cmd_buffer(
253 struct radv_device
* device
,
254 struct radv_cmd_pool
* pool
,
255 VkCommandBufferLevel level
,
256 VkCommandBuffer
* pCommandBuffer
)
258 struct radv_cmd_buffer
*cmd_buffer
;
260 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
262 if (cmd_buffer
== NULL
)
263 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
265 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
266 cmd_buffer
->device
= device
;
267 cmd_buffer
->pool
= pool
;
268 cmd_buffer
->level
= level
;
271 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
272 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
275 /* Init the pool_link so we can safely call list_del when we destroy
278 list_inithead(&cmd_buffer
->pool_link
);
279 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
282 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
284 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
285 if (!cmd_buffer
->cs
) {
286 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
287 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
290 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
292 list_inithead(&cmd_buffer
->upload
.list
);
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
300 list_del(&cmd_buffer
->pool_link
);
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
303 &cmd_buffer
->upload
.list
, list
) {
304 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
309 if (cmd_buffer
->upload
.upload_bo
)
310 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
311 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
313 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
314 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
316 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
320 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
322 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
325 &cmd_buffer
->upload
.list
, list
) {
326 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
331 cmd_buffer
->push_constant_stages
= 0;
332 cmd_buffer
->scratch_size_needed
= 0;
333 cmd_buffer
->compute_scratch_size_needed
= 0;
334 cmd_buffer
->esgs_ring_size_needed
= 0;
335 cmd_buffer
->gsvs_ring_size_needed
= 0;
336 cmd_buffer
->tess_rings_needed
= false;
337 cmd_buffer
->sample_positions_needed
= false;
339 if (cmd_buffer
->upload
.upload_bo
)
340 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
341 cmd_buffer
->upload
.upload_bo
);
342 cmd_buffer
->upload
.offset
= 0;
344 cmd_buffer
->record_result
= VK_SUCCESS
;
346 memset(cmd_buffer
->vertex_bindings
, 0, sizeof(cmd_buffer
->vertex_bindings
));
348 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
349 cmd_buffer
->descriptors
[i
].dirty
= 0;
350 cmd_buffer
->descriptors
[i
].valid
= 0;
351 cmd_buffer
->descriptors
[i
].push_dirty
= false;
354 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
355 cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
356 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
357 unsigned fence_offset
, eop_bug_offset
;
360 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 8, &fence_offset
,
363 cmd_buffer
->gfx9_fence_va
=
364 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
365 cmd_buffer
->gfx9_fence_va
+= fence_offset
;
367 /* Allocate a buffer for the EOP bug on GFX9. */
368 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 8,
369 &eop_bug_offset
, &fence_ptr
);
370 cmd_buffer
->gfx9_eop_bug_va
=
371 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
372 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
375 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
377 return cmd_buffer
->record_result
;
381 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
385 struct radeon_winsys_bo
*bo
;
386 struct radv_cmd_buffer_upload
*upload
;
387 struct radv_device
*device
= cmd_buffer
->device
;
389 new_size
= MAX2(min_needed
, 16 * 1024);
390 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
392 bo
= device
->ws
->buffer_create(device
->ws
,
395 RADEON_FLAG_CPU_ACCESS
|
396 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
398 RADV_BO_PRIORITY_UPLOAD_BUFFER
);
401 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
405 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
406 if (cmd_buffer
->upload
.upload_bo
) {
407 upload
= malloc(sizeof(*upload
));
410 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
411 device
->ws
->buffer_destroy(bo
);
415 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
416 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
419 cmd_buffer
->upload
.upload_bo
= bo
;
420 cmd_buffer
->upload
.size
= new_size
;
421 cmd_buffer
->upload
.offset
= 0;
422 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
424 if (!cmd_buffer
->upload
.map
) {
425 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
433 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
436 unsigned *out_offset
,
439 assert(util_is_power_of_two_nonzero(alignment
));
441 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
442 if (offset
+ size
> cmd_buffer
->upload
.size
) {
443 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
448 *out_offset
= offset
;
449 *ptr
= cmd_buffer
->upload
.map
+ offset
;
451 cmd_buffer
->upload
.offset
= offset
+ size
;
456 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
457 unsigned size
, unsigned alignment
,
458 const void *data
, unsigned *out_offset
)
462 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
463 out_offset
, (void **)&ptr
))
467 memcpy(ptr
, data
, size
);
473 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
474 unsigned count
, const uint32_t *data
)
476 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
478 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
480 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
481 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
482 S_370_WR_CONFIRM(1) |
483 S_370_ENGINE_SEL(V_370_ME
));
485 radeon_emit(cs
, va
>> 32);
486 radeon_emit_array(cs
, data
, count
);
489 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
491 struct radv_device
*device
= cmd_buffer
->device
;
492 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
495 va
= radv_buffer_get_va(device
->trace_bo
);
496 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
499 ++cmd_buffer
->state
.trace_id
;
500 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
501 &cmd_buffer
->state
.trace_id
);
503 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
505 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
506 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
510 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
511 enum radv_cmd_flush_bits flags
)
513 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
514 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
515 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
517 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
519 /* Force wait for graphics or compute engines to be idle. */
520 si_cs_emit_cache_flush(cmd_buffer
->cs
,
521 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
522 &cmd_buffer
->gfx9_fence_idx
,
523 cmd_buffer
->gfx9_fence_va
,
524 radv_cmd_buffer_uses_mec(cmd_buffer
),
525 flags
, cmd_buffer
->gfx9_eop_bug_va
);
528 if (unlikely(cmd_buffer
->device
->trace_bo
))
529 radv_cmd_buffer_trace_emit(cmd_buffer
);
533 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
534 struct radv_pipeline
*pipeline
, enum ring_type ring
)
536 struct radv_device
*device
= cmd_buffer
->device
;
540 va
= radv_buffer_get_va(device
->trace_bo
);
550 assert(!"invalid ring type");
553 data
[0] = (uintptr_t)pipeline
;
554 data
[1] = (uintptr_t)pipeline
>> 32;
556 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
559 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
560 VkPipelineBindPoint bind_point
,
561 struct radv_descriptor_set
*set
,
564 struct radv_descriptor_state
*descriptors_state
=
565 radv_get_descriptors_state(cmd_buffer
, bind_point
);
567 descriptors_state
->sets
[idx
] = set
;
569 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
570 descriptors_state
->dirty
|= (1u << idx
);
574 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
575 VkPipelineBindPoint bind_point
)
577 struct radv_descriptor_state
*descriptors_state
=
578 radv_get_descriptors_state(cmd_buffer
, bind_point
);
579 struct radv_device
*device
= cmd_buffer
->device
;
580 uint32_t data
[MAX_SETS
* 2] = {};
583 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
585 for_each_bit(i
, descriptors_state
->valid
) {
586 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
587 data
[i
* 2] = (uint64_t)(uintptr_t)set
;
588 data
[i
* 2 + 1] = (uint64_t)(uintptr_t)set
>> 32;
591 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
594 struct radv_userdata_info
*
595 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
596 gl_shader_stage stage
,
599 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
600 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
604 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
605 struct radv_pipeline
*pipeline
,
606 gl_shader_stage stage
,
607 int idx
, uint64_t va
)
609 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
610 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
611 if (loc
->sgpr_idx
== -1)
614 assert(loc
->num_sgprs
== 1);
616 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
617 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
621 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
622 struct radv_pipeline
*pipeline
,
623 struct radv_descriptor_state
*descriptors_state
,
624 gl_shader_stage stage
)
626 struct radv_device
*device
= cmd_buffer
->device
;
627 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
628 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
629 struct radv_userdata_locations
*locs
=
630 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
631 unsigned mask
= locs
->descriptor_sets_enabled
;
633 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
638 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
640 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
641 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
643 radv_emit_shader_pointer_head(cs
, sh_offset
, count
, true);
644 for (int i
= 0; i
< count
; i
++) {
645 struct radv_descriptor_set
*set
=
646 descriptors_state
->sets
[start
+ i
];
648 radv_emit_shader_pointer_body(device
, cs
, set
->va
, true);
654 * Convert the user sample locations to hardware sample locations (the values
655 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
658 radv_convert_user_sample_locs(struct radv_sample_locations_state
*state
,
659 uint32_t x
, uint32_t y
, VkOffset2D
*sample_locs
)
661 uint32_t x_offset
= x
% state
->grid_size
.width
;
662 uint32_t y_offset
= y
% state
->grid_size
.height
;
663 uint32_t num_samples
= (uint32_t)state
->per_pixel
;
664 VkSampleLocationEXT
*user_locs
;
665 uint32_t pixel_offset
;
667 pixel_offset
= (x_offset
+ y_offset
* state
->grid_size
.width
) * num_samples
;
669 assert(pixel_offset
<= MAX_SAMPLE_LOCATIONS
);
670 user_locs
= &state
->locations
[pixel_offset
];
672 for (uint32_t i
= 0; i
< num_samples
; i
++) {
673 float shifted_pos_x
= user_locs
[i
].x
- 0.5;
674 float shifted_pos_y
= user_locs
[i
].y
- 0.5;
676 int32_t scaled_pos_x
= floor(shifted_pos_x
* 16);
677 int32_t scaled_pos_y
= floor(shifted_pos_y
* 16);
679 sample_locs
[i
].x
= CLAMP(scaled_pos_x
, -8, 7);
680 sample_locs
[i
].y
= CLAMP(scaled_pos_y
, -8, 7);
685 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
689 radv_compute_sample_locs_pixel(uint32_t num_samples
, VkOffset2D
*sample_locs
,
690 uint32_t *sample_locs_pixel
)
692 for (uint32_t i
= 0; i
< num_samples
; i
++) {
693 uint32_t sample_reg_idx
= i
/ 4;
694 uint32_t sample_loc_idx
= i
% 4;
695 int32_t pos_x
= sample_locs
[i
].x
;
696 int32_t pos_y
= sample_locs
[i
].y
;
698 uint32_t shift_x
= 8 * sample_loc_idx
;
699 uint32_t shift_y
= shift_x
+ 4;
701 sample_locs_pixel
[sample_reg_idx
] |= (pos_x
& 0xf) << shift_x
;
702 sample_locs_pixel
[sample_reg_idx
] |= (pos_y
& 0xf) << shift_y
;
707 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
711 radv_compute_centroid_priority(struct radv_cmd_buffer
*cmd_buffer
,
712 VkOffset2D
*sample_locs
,
713 uint32_t num_samples
)
715 uint32_t centroid_priorities
[num_samples
];
716 uint32_t sample_mask
= num_samples
- 1;
717 uint32_t distances
[num_samples
];
718 uint64_t centroid_priority
= 0;
720 /* Compute the distances from center for each sample. */
721 for (int i
= 0; i
< num_samples
; i
++) {
722 distances
[i
] = (sample_locs
[i
].x
* sample_locs
[i
].x
) +
723 (sample_locs
[i
].y
* sample_locs
[i
].y
);
726 /* Compute the centroid priorities by looking at the distances array. */
727 for (int i
= 0; i
< num_samples
; i
++) {
728 uint32_t min_idx
= 0;
730 for (int j
= 1; j
< num_samples
; j
++) {
731 if (distances
[j
] < distances
[min_idx
])
735 centroid_priorities
[i
] = min_idx
;
736 distances
[min_idx
] = 0xffffffff;
739 /* Compute the final centroid priority. */
740 for (int i
= 0; i
< 8; i
++) {
742 centroid_priorities
[i
& sample_mask
] << (i
* 4);
745 return centroid_priority
<< 32 | centroid_priority
;
749 * Emit the sample locations that are specified with VK_EXT_sample_locations.
752 radv_emit_sample_locations(struct radv_cmd_buffer
*cmd_buffer
)
754 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
755 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
756 struct radv_sample_locations_state
*sample_location
=
757 &cmd_buffer
->state
.dynamic
.sample_location
;
758 uint32_t num_samples
= (uint32_t)sample_location
->per_pixel
;
759 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
760 uint32_t sample_locs_pixel
[4][2] = {};
761 VkOffset2D sample_locs
[4][8]; /* 8 is the max. sample count supported */
762 uint32_t max_sample_dist
= 0;
763 uint64_t centroid_priority
;
765 if (!cmd_buffer
->state
.dynamic
.sample_location
.count
)
768 /* Convert the user sample locations to hardware sample locations. */
769 radv_convert_user_sample_locs(sample_location
, 0, 0, sample_locs
[0]);
770 radv_convert_user_sample_locs(sample_location
, 1, 0, sample_locs
[1]);
771 radv_convert_user_sample_locs(sample_location
, 0, 1, sample_locs
[2]);
772 radv_convert_user_sample_locs(sample_location
, 1, 1, sample_locs
[3]);
774 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
775 for (uint32_t i
= 0; i
< 4; i
++) {
776 radv_compute_sample_locs_pixel(num_samples
, sample_locs
[i
],
777 sample_locs_pixel
[i
]);
780 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
782 radv_compute_centroid_priority(cmd_buffer
, sample_locs
[0],
785 /* Compute the maximum sample distance from the specified locations. */
786 for (uint32_t i
= 0; i
< num_samples
; i
++) {
787 VkOffset2D offset
= sample_locs
[0][i
];
788 max_sample_dist
= MAX2(max_sample_dist
,
789 MAX2(abs(offset
.x
), abs(offset
.y
)));
792 /* Emit the specified user sample locations. */
793 switch (num_samples
) {
796 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
797 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
798 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
799 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
802 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
803 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
804 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
805 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
806 radeon_set_context_reg(cs
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, sample_locs_pixel
[0][1]);
807 radeon_set_context_reg(cs
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, sample_locs_pixel
[1][1]);
808 radeon_set_context_reg(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, sample_locs_pixel
[2][1]);
809 radeon_set_context_reg(cs
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, sample_locs_pixel
[3][1]);
812 unreachable("invalid number of samples");
815 /* Emit the maximum sample distance and the centroid priority. */
816 uint32_t pa_sc_aa_config
= ms
->pa_sc_aa_config
;
818 pa_sc_aa_config
&= C_028BE0_MAX_SAMPLE_DIST
;
819 pa_sc_aa_config
|= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist
);
821 radeon_set_context_reg_seq(cs
, R_028BE0_PA_SC_AA_CONFIG
, 1);
822 radeon_emit(cs
, pa_sc_aa_config
);
824 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
825 radeon_emit(cs
, centroid_priority
);
826 radeon_emit(cs
, centroid_priority
>> 32);
828 /* GFX9: Flush DFSM when the AA mode changes. */
829 if (cmd_buffer
->device
->dfsm_allowed
) {
830 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
831 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
834 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
838 radv_emit_inline_push_consts(struct radv_cmd_buffer
*cmd_buffer
,
839 struct radv_pipeline
*pipeline
,
840 gl_shader_stage stage
,
841 int idx
, int count
, uint32_t *values
)
843 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
844 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
845 if (loc
->sgpr_idx
== -1)
848 assert(loc
->num_sgprs
== count
);
850 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, count
);
851 radeon_emit_array(cmd_buffer
->cs
, values
, count
);
855 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
856 struct radv_pipeline
*pipeline
)
858 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
859 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
860 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
862 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
)
863 cmd_buffer
->sample_positions_needed
= true;
865 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
868 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
869 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
870 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
872 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
874 radv_emit_default_sample_locations(cmd_buffer
->cs
, num_samples
);
876 /* GFX9: Flush DFSM when the AA mode changes. */
877 if (cmd_buffer
->device
->dfsm_allowed
) {
878 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
879 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
882 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
886 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
887 struct radv_shader_variant
*shader
)
894 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
896 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
900 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
901 struct radv_pipeline
*pipeline
,
902 bool vertex_stage_only
)
904 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
905 uint32_t mask
= state
->prefetch_L2_mask
;
907 if (vertex_stage_only
) {
908 /* Fast prefetch path for starting draws as soon as possible.
910 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
911 RADV_PREFETCH_VBO_DESCRIPTORS
);
914 if (mask
& RADV_PREFETCH_VS
)
915 radv_emit_shader_prefetch(cmd_buffer
,
916 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
918 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
919 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
921 if (mask
& RADV_PREFETCH_TCS
)
922 radv_emit_shader_prefetch(cmd_buffer
,
923 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
925 if (mask
& RADV_PREFETCH_TES
)
926 radv_emit_shader_prefetch(cmd_buffer
,
927 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
929 if (mask
& RADV_PREFETCH_GS
) {
930 radv_emit_shader_prefetch(cmd_buffer
,
931 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
932 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
935 if (mask
& RADV_PREFETCH_PS
)
936 radv_emit_shader_prefetch(cmd_buffer
,
937 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
939 state
->prefetch_L2_mask
&= ~mask
;
943 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
945 if (!cmd_buffer
->device
->physical_device
->rbplus_allowed
)
948 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
949 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
950 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
952 unsigned sx_ps_downconvert
= 0;
953 unsigned sx_blend_opt_epsilon
= 0;
954 unsigned sx_blend_opt_control
= 0;
956 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
957 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
958 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
959 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
963 int idx
= subpass
->color_attachments
[i
].attachment
;
964 struct radv_color_buffer_info
*cb
= &framebuffer
->attachments
[idx
].cb
;
966 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
967 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
968 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
969 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
971 bool has_alpha
, has_rgb
;
973 /* Set if RGB and A are present. */
974 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
976 if (format
== V_028C70_COLOR_8
||
977 format
== V_028C70_COLOR_16
||
978 format
== V_028C70_COLOR_32
)
979 has_rgb
= !has_alpha
;
983 /* Check the colormask and export format. */
984 if (!(colormask
& 0x7))
986 if (!(colormask
& 0x8))
989 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
994 /* Disable value checking for disabled channels. */
996 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
998 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1000 /* Enable down-conversion for 32bpp and smaller formats. */
1002 case V_028C70_COLOR_8
:
1003 case V_028C70_COLOR_8_8
:
1004 case V_028C70_COLOR_8_8_8_8
:
1005 /* For 1 and 2-channel formats, use the superset thereof. */
1006 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
1007 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1008 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1009 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
1010 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
1014 case V_028C70_COLOR_5_6_5
:
1015 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1016 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
1017 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
1021 case V_028C70_COLOR_1_5_5_5
:
1022 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1023 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
1024 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
1028 case V_028C70_COLOR_4_4_4_4
:
1029 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1030 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
1031 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
1035 case V_028C70_COLOR_32
:
1036 if (swap
== V_028C70_SWAP_STD
&&
1037 spi_format
== V_028714_SPI_SHADER_32_R
)
1038 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
1039 else if (swap
== V_028C70_SWAP_ALT_REV
&&
1040 spi_format
== V_028714_SPI_SHADER_32_AR
)
1041 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
1044 case V_028C70_COLOR_16
:
1045 case V_028C70_COLOR_16_16
:
1046 /* For 1-channel formats, use the superset thereof. */
1047 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
1048 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
1049 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1050 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1051 if (swap
== V_028C70_SWAP_STD
||
1052 swap
== V_028C70_SWAP_STD_REV
)
1053 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
1055 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
1059 case V_028C70_COLOR_10_11_11
:
1060 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1061 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
1062 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
1066 case V_028C70_COLOR_2_10_10_10
:
1067 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1068 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
1069 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
1075 for (unsigned i
= subpass
->color_count
; i
< 8; ++i
) {
1076 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1077 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1079 /* TODO: avoid redundantly setting context registers */
1080 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
1081 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
1082 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
1083 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
1085 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1089 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1091 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1093 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
1096 radv_update_multisample_state(cmd_buffer
, pipeline
);
1098 cmd_buffer
->scratch_size_needed
=
1099 MAX2(cmd_buffer
->scratch_size_needed
,
1100 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
1102 if (!cmd_buffer
->state
.emitted_pipeline
||
1103 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1104 pipeline
->graphics
.can_use_guardband
)
1105 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1107 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
1109 if (!cmd_buffer
->state
.emitted_pipeline
||
1110 cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.cdw
!= pipeline
->ctx_cs
.cdw
||
1111 cmd_buffer
->state
.emitted_pipeline
->ctx_cs_hash
!= pipeline
->ctx_cs_hash
||
1112 memcmp(cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.buf
,
1113 pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
* 4)) {
1114 radeon_emit_array(cmd_buffer
->cs
, pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
);
1115 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1118 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
1119 if (!pipeline
->shaders
[i
])
1122 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1123 pipeline
->shaders
[i
]->bo
);
1126 if (radv_pipeline_has_gs(pipeline
))
1127 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1128 pipeline
->gs_copy_shader
->bo
);
1130 if (unlikely(cmd_buffer
->device
->trace_bo
))
1131 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1133 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1135 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1139 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1141 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1142 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1146 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1148 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1150 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1151 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1152 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1153 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1155 cmd_buffer
->state
.context_roll_without_scissor_emitted
= false;
1159 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
1161 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
1164 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
1165 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
1166 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
1167 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
1168 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
1169 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
1170 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
1175 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1177 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1179 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1180 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1184 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1186 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1188 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1189 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1193 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1195 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1197 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1198 R_028430_DB_STENCILREFMASK
, 2);
1199 radeon_emit(cmd_buffer
->cs
,
1200 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1201 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1202 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1203 S_028430_STENCILOPVAL(1));
1204 radeon_emit(cmd_buffer
->cs
,
1205 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1206 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1207 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1208 S_028434_STENCILOPVAL_BF(1));
1212 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1214 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1216 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1217 fui(d
->depth_bounds
.min
));
1218 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1219 fui(d
->depth_bounds
.max
));
1223 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
1225 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1226 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1227 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1230 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1231 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1232 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1233 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1234 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1235 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1236 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1240 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1242 struct radv_attachment_info
*att
,
1243 struct radv_image_view
*iview
,
1244 VkImageLayout layout
)
1246 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
;
1247 struct radv_color_buffer_info
*cb
= &att
->cb
;
1248 uint32_t cb_color_info
= cb
->cb_color_info
;
1249 struct radv_image
*image
= iview
->image
;
1251 if (!radv_layout_dcc_compressed(image
, layout
,
1252 radv_image_queue_family_mask(image
,
1253 cmd_buffer
->queue_family_index
,
1254 cmd_buffer
->queue_family_index
))) {
1255 cb_color_info
&= C_028C70_DCC_ENABLE
;
1258 if (radv_image_is_tc_compat_cmask(image
) &&
1259 (radv_is_fmask_decompress_pipeline(cmd_buffer
) ||
1260 radv_is_dcc_decompress_pipeline(cmd_buffer
))) {
1261 /* If this bit is set, the FMASK decompression operation
1262 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1264 cb_color_info
&= C_028C70_FMASK_COMPRESS_1FRAG_ONLY
;
1267 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1268 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1269 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1270 radeon_emit(cmd_buffer
->cs
, 0);
1271 radeon_emit(cmd_buffer
->cs
, 0);
1272 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1273 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1274 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1275 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1276 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1277 radeon_emit(cmd_buffer
->cs
, 0);
1278 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1279 radeon_emit(cmd_buffer
->cs
, 0);
1281 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 1);
1282 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1284 radeon_set_context_reg(cmd_buffer
->cs
, R_028E40_CB_COLOR0_BASE_EXT
+ index
* 4,
1285 cb
->cb_color_base
>> 32);
1286 radeon_set_context_reg(cmd_buffer
->cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ index
* 4,
1287 cb
->cb_color_cmask
>> 32);
1288 radeon_set_context_reg(cmd_buffer
->cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ index
* 4,
1289 cb
->cb_color_fmask
>> 32);
1290 radeon_set_context_reg(cmd_buffer
->cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ index
* 4,
1291 cb
->cb_dcc_base
>> 32);
1292 radeon_set_context_reg(cmd_buffer
->cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ index
* 4,
1293 cb
->cb_color_attrib2
);
1294 radeon_set_context_reg(cmd_buffer
->cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ index
* 4,
1295 cb
->cb_color_attrib3
);
1296 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1297 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1298 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1299 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1300 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1301 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1302 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1303 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1304 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1305 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1306 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1307 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1308 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1310 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1311 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1312 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1314 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1317 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1318 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1319 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1320 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1321 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1322 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1323 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1324 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1325 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1326 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1327 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1328 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1330 if (is_vi
) { /* DCC BASE */
1331 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1335 if (radv_dcc_enabled(image
, iview
->base_mip
)) {
1336 /* Drawing with DCC enabled also compresses colorbuffers. */
1337 VkImageSubresourceRange range
= {
1338 .aspectMask
= iview
->aspect_mask
,
1339 .baseMipLevel
= iview
->base_mip
,
1340 .levelCount
= iview
->level_count
,
1341 .baseArrayLayer
= iview
->base_layer
,
1342 .layerCount
= iview
->layer_count
,
1345 radv_update_dcc_metadata(cmd_buffer
, image
, &range
, true);
1350 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1351 struct radv_ds_buffer_info
*ds
,
1352 struct radv_image
*image
, VkImageLayout layout
,
1353 bool requires_cond_exec
)
1355 uint32_t db_z_info
= ds
->db_z_info
;
1356 uint32_t db_z_info_reg
;
1358 if (!radv_image_is_tc_compat_htile(image
))
1361 if (!radv_layout_has_htile(image
, layout
,
1362 radv_image_queue_family_mask(image
,
1363 cmd_buffer
->queue_family_index
,
1364 cmd_buffer
->queue_family_index
))) {
1365 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1368 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1370 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1371 db_z_info_reg
= R_028038_DB_Z_INFO
;
1373 db_z_info_reg
= R_028040_DB_Z_INFO
;
1376 /* When we don't know the last fast clear value we need to emit a
1377 * conditional packet that will eventually skip the following
1378 * SET_CONTEXT_REG packet.
1380 if (requires_cond_exec
) {
1381 uint64_t va
= radv_buffer_get_va(image
->bo
);
1382 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1384 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_EXEC
, 3, 0));
1385 radeon_emit(cmd_buffer
->cs
, va
);
1386 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1387 radeon_emit(cmd_buffer
->cs
, 0);
1388 radeon_emit(cmd_buffer
->cs
, 3); /* SET_CONTEXT_REG size */
1391 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1395 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1396 struct radv_ds_buffer_info
*ds
,
1397 struct radv_image
*image
,
1398 VkImageLayout layout
)
1400 uint32_t db_z_info
= ds
->db_z_info
;
1401 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1403 if (!radv_layout_has_htile(image
, layout
,
1404 radv_image_queue_family_mask(image
,
1405 cmd_buffer
->queue_family_index
,
1406 cmd_buffer
->queue_family_index
))) {
1407 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1408 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1411 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1412 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1414 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1415 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1416 radeon_set_context_reg(cmd_buffer
->cs
, R_02801C_DB_DEPTH_SIZE_XY
, ds
->db_depth_size
);
1418 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 7);
1419 radeon_emit(cmd_buffer
->cs
, S_02803C_RESOURCE_LEVEL(1));
1420 radeon_emit(cmd_buffer
->cs
, db_z_info
);
1421 radeon_emit(cmd_buffer
->cs
, db_stencil_info
);
1422 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1423 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1424 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1425 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1427 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
1428 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1429 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1430 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1431 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1432 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1433 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1434 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1435 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1436 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1437 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1439 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1440 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1441 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1442 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1443 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1444 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1445 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1446 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1447 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1448 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1449 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1451 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1452 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1453 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1455 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1457 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1458 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1459 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1460 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1461 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1462 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1463 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1464 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1465 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1466 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1470 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1471 radv_update_zrange_precision(cmd_buffer
, ds
, image
, layout
, true);
1473 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1474 ds
->pa_su_poly_offset_db_fmt_cntl
);
1478 * Update the fast clear depth/stencil values if the image is bound as a
1479 * depth/stencil buffer.
1482 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1483 struct radv_image
*image
,
1484 VkClearDepthStencilValue ds_clear_value
,
1485 VkImageAspectFlags aspects
)
1487 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1488 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1489 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1490 struct radv_attachment_info
*att
;
1493 if (!framebuffer
|| !subpass
)
1496 if (!subpass
->depth_stencil_attachment
)
1499 att_idx
= subpass
->depth_stencil_attachment
->attachment
;
1500 att
= &framebuffer
->attachments
[att_idx
];
1501 if (att
->attachment
->image
!= image
)
1504 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1505 radeon_emit(cs
, ds_clear_value
.stencil
);
1506 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1508 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1509 * only needed when clearing Z to 0.0.
1511 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1512 ds_clear_value
.depth
== 0.0) {
1513 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1515 radv_update_zrange_precision(cmd_buffer
, &att
->ds
, image
,
1519 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1523 * Set the clear depth/stencil values to the image's metadata.
1526 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1527 struct radv_image
*image
,
1528 VkClearDepthStencilValue ds_clear_value
,
1529 VkImageAspectFlags aspects
)
1531 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1532 uint64_t va
= radv_buffer_get_va(image
->bo
);
1533 unsigned reg_offset
= 0, reg_count
= 0;
1535 va
+= image
->offset
+ image
->clear_value_offset
;
1537 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1543 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1546 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, cmd_buffer
->state
.predicating
));
1547 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1548 S_370_WR_CONFIRM(1) |
1549 S_370_ENGINE_SEL(V_370_PFP
));
1550 radeon_emit(cs
, va
);
1551 radeon_emit(cs
, va
>> 32);
1552 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1553 radeon_emit(cs
, ds_clear_value
.stencil
);
1554 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1555 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1559 * Update the TC-compat metadata value for this image.
1562 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1563 struct radv_image
*image
,
1566 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1567 uint64_t va
= radv_buffer_get_va(image
->bo
);
1568 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1570 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, cmd_buffer
->state
.predicating
));
1571 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1572 S_370_WR_CONFIRM(1) |
1573 S_370_ENGINE_SEL(V_370_PFP
));
1574 radeon_emit(cs
, va
);
1575 radeon_emit(cs
, va
>> 32);
1576 radeon_emit(cs
, value
);
1580 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1581 struct radv_image
*image
,
1582 VkClearDepthStencilValue ds_clear_value
)
1586 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1587 * depth clear value is 0.0f.
1589 cond_val
= ds_clear_value
.depth
== 0.0f
? UINT_MAX
: 0;
1591 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, cond_val
);
1595 * Update the clear depth/stencil values for this image.
1598 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1599 struct radv_image
*image
,
1600 VkClearDepthStencilValue ds_clear_value
,
1601 VkImageAspectFlags aspects
)
1603 assert(radv_image_has_htile(image
));
1605 radv_set_ds_clear_metadata(cmd_buffer
, image
, ds_clear_value
, aspects
);
1607 if (radv_image_is_tc_compat_htile(image
) &&
1608 (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
1609 radv_update_tc_compat_zrange_metadata(cmd_buffer
, image
,
1613 radv_update_bound_fast_clear_ds(cmd_buffer
, image
, ds_clear_value
,
1618 * Load the clear depth/stencil values from the image's metadata.
1621 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1622 struct radv_image
*image
)
1624 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1625 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1626 uint64_t va
= radv_buffer_get_va(image
->bo
);
1627 unsigned reg_offset
= 0, reg_count
= 0;
1629 va
+= image
->offset
+ image
->clear_value_offset
;
1631 if (!radv_image_has_htile(image
))
1634 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1640 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1643 uint32_t reg
= R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
;
1645 if (cmd_buffer
->device
->physical_device
->has_load_ctx_reg_pkt
) {
1646 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, 0));
1647 radeon_emit(cs
, va
);
1648 radeon_emit(cs
, va
>> 32);
1649 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1650 radeon_emit(cs
, reg_count
);
1652 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1653 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1654 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1655 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1656 radeon_emit(cs
, va
);
1657 radeon_emit(cs
, va
>> 32);
1658 radeon_emit(cs
, reg
>> 2);
1661 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1667 * With DCC some colors don't require CMASK elimination before being
1668 * used as a texture. This sets a predicate value to determine if the
1669 * cmask eliminate is required.
1672 radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1673 struct radv_image
*image
,
1674 const VkImageSubresourceRange
*range
, bool value
)
1676 uint64_t pred_val
= value
;
1677 uint64_t va
= radv_image_get_fce_pred_va(image
, range
->baseMipLevel
);
1678 uint32_t level_count
= radv_get_levelCount(image
, range
);
1679 uint32_t count
= 2 * level_count
;
1681 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1683 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1684 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1685 S_370_WR_CONFIRM(1) |
1686 S_370_ENGINE_SEL(V_370_PFP
));
1687 radeon_emit(cmd_buffer
->cs
, va
);
1688 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1690 for (uint32_t l
= 0; l
< level_count
; l
++) {
1691 radeon_emit(cmd_buffer
->cs
, pred_val
);
1692 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1697 * Update the DCC predicate to reflect the compression state.
1700 radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1701 struct radv_image
*image
,
1702 const VkImageSubresourceRange
*range
, bool value
)
1704 uint64_t pred_val
= value
;
1705 uint64_t va
= radv_image_get_dcc_pred_va(image
, range
->baseMipLevel
);
1706 uint32_t level_count
= radv_get_levelCount(image
, range
);
1707 uint32_t count
= 2 * level_count
;
1709 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
1711 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
1712 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1713 S_370_WR_CONFIRM(1) |
1714 S_370_ENGINE_SEL(V_370_PFP
));
1715 radeon_emit(cmd_buffer
->cs
, va
);
1716 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1718 for (uint32_t l
= 0; l
< level_count
; l
++) {
1719 radeon_emit(cmd_buffer
->cs
, pred_val
);
1720 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1725 * Update the fast clear color values if the image is bound as a color buffer.
1728 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1729 struct radv_image
*image
,
1731 uint32_t color_values
[2])
1733 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1734 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1735 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1736 struct radv_attachment_info
*att
;
1739 if (!framebuffer
|| !subpass
)
1742 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1743 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1746 att
= &framebuffer
->attachments
[att_idx
];
1747 if (att
->attachment
->image
!= image
)
1750 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1751 radeon_emit(cs
, color_values
[0]);
1752 radeon_emit(cs
, color_values
[1]);
1754 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1758 * Set the clear color values to the image's metadata.
1761 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1762 struct radv_image
*image
,
1763 const VkImageSubresourceRange
*range
,
1764 uint32_t color_values
[2])
1766 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1767 uint64_t va
= radv_image_get_fast_clear_va(image
, range
->baseMipLevel
);
1768 uint32_t level_count
= radv_get_levelCount(image
, range
);
1769 uint32_t count
= 2 * level_count
;
1771 assert(radv_image_has_cmask(image
) ||
1772 radv_dcc_enabled(image
, range
->baseMipLevel
));
1774 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, cmd_buffer
->state
.predicating
));
1775 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1776 S_370_WR_CONFIRM(1) |
1777 S_370_ENGINE_SEL(V_370_PFP
));
1778 radeon_emit(cs
, va
);
1779 radeon_emit(cs
, va
>> 32);
1781 for (uint32_t l
= 0; l
< level_count
; l
++) {
1782 radeon_emit(cs
, color_values
[0]);
1783 radeon_emit(cs
, color_values
[1]);
1788 * Update the clear color values for this image.
1791 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1792 const struct radv_image_view
*iview
,
1794 uint32_t color_values
[2])
1796 struct radv_image
*image
= iview
->image
;
1797 VkImageSubresourceRange range
= {
1798 .aspectMask
= iview
->aspect_mask
,
1799 .baseMipLevel
= iview
->base_mip
,
1800 .levelCount
= iview
->level_count
,
1801 .baseArrayLayer
= iview
->base_layer
,
1802 .layerCount
= iview
->layer_count
,
1805 assert(radv_image_has_cmask(image
) ||
1806 radv_dcc_enabled(image
, iview
->base_mip
));
1808 radv_set_color_clear_metadata(cmd_buffer
, image
, &range
, color_values
);
1810 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1815 * Load the clear color values from the image's metadata.
1818 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1819 struct radv_image_view
*iview
,
1822 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1823 struct radv_image
*image
= iview
->image
;
1824 uint64_t va
= radv_image_get_fast_clear_va(image
, iview
->base_mip
);
1826 if (!radv_image_has_cmask(image
) &&
1827 !radv_dcc_enabled(image
, iview
->base_mip
))
1830 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1832 if (cmd_buffer
->device
->physical_device
->has_load_ctx_reg_pkt
) {
1833 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, cmd_buffer
->state
.predicating
));
1834 radeon_emit(cs
, va
);
1835 radeon_emit(cs
, va
>> 32);
1836 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1839 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1840 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1841 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1842 COPY_DATA_COUNT_SEL
);
1843 radeon_emit(cs
, va
);
1844 radeon_emit(cs
, va
>> 32);
1845 radeon_emit(cs
, reg
>> 2);
1848 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1854 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1857 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1858 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1859 unsigned num_bpp64_colorbufs
= 0;
1861 /* this may happen for inherited secondary recording */
1865 for (i
= 0; i
< 8; ++i
) {
1866 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1867 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1868 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1872 int idx
= subpass
->color_attachments
[i
].attachment
;
1873 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1874 struct radv_image_view
*iview
= att
->attachment
;
1875 struct radv_image
*image
= iview
->image
;
1876 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
1878 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1880 assert(att
->attachment
->aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
| VK_IMAGE_ASPECT_PLANE_0_BIT
|
1881 VK_IMAGE_ASPECT_PLANE_1_BIT
| VK_IMAGE_ASPECT_PLANE_2_BIT
));
1882 radv_emit_fb_color_state(cmd_buffer
, i
, att
, iview
, layout
);
1884 radv_load_color_clear_metadata(cmd_buffer
, iview
, i
);
1886 if (image
->planes
[0].surface
.bpe
>= 8)
1887 num_bpp64_colorbufs
++;
1890 if (subpass
->depth_stencil_attachment
) {
1891 int idx
= subpass
->depth_stencil_attachment
->attachment
;
1892 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1893 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1894 struct radv_image
*image
= att
->attachment
->image
;
1895 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1896 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1897 cmd_buffer
->queue_family_index
,
1898 cmd_buffer
->queue_family_index
);
1899 /* We currently don't support writing decompressed HTILE */
1900 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1901 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1903 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1905 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1906 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1907 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1909 radv_load_ds_clear_metadata(cmd_buffer
, image
);
1911 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
)
1912 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1914 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1916 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1917 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1919 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1920 S_028208_BR_X(framebuffer
->width
) |
1921 S_028208_BR_Y(framebuffer
->height
));
1923 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
) {
1924 bool disable_constant_encode
=
1925 cmd_buffer
->device
->physical_device
->has_dcc_constant_encode
;
1926 uint8_t watermark
= 4; /* Default value for GFX8. */
1928 /* For optimal DCC performance. */
1929 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1930 if (num_bpp64_colorbufs
>= 5) {
1937 radeon_set_context_reg(cmd_buffer
->cs
, R_028424_CB_DCC_CONTROL
,
1938 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1939 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
1940 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode
));
1943 if (cmd_buffer
->device
->dfsm_allowed
) {
1944 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1945 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1948 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
1952 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1954 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1955 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1957 if (state
->index_type
!= state
->last_index_type
) {
1958 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1959 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
1960 2, state
->index_type
);
1962 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1963 radeon_emit(cs
, state
->index_type
);
1966 state
->last_index_type
= state
->index_type
;
1969 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
1970 radeon_emit(cs
, state
->index_va
);
1971 radeon_emit(cs
, state
->index_va
>> 32);
1973 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1974 radeon_emit(cs
, state
->max_index_count
);
1976 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
1979 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1981 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
1982 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1983 uint32_t pa_sc_mode_cntl_1
=
1984 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
1985 uint32_t db_count_control
;
1987 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1988 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1989 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1990 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1991 has_perfect_queries
) {
1992 /* Re-enable out-of-order rasterization if the
1993 * bound pipeline supports it and if it's has
1994 * been disabled before starting any perfect
1995 * occlusion queries.
1997 radeon_set_context_reg(cmd_buffer
->cs
,
1998 R_028A4C_PA_SC_MODE_CNTL_1
,
2002 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
2004 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2005 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
2007 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2009 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
2010 S_028004_SAMPLE_RATE(sample_rate
) |
2011 S_028004_ZPASS_ENABLE(1) |
2012 S_028004_SLICE_EVEN_ENABLE(1) |
2013 S_028004_SLICE_ODD_ENABLE(1);
2015 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2016 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2017 has_perfect_queries
) {
2018 /* If the bound pipeline has enabled
2019 * out-of-order rasterization, we should
2020 * disable it before starting any perfect
2021 * occlusion queries.
2023 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
2025 radeon_set_context_reg(cmd_buffer
->cs
,
2026 R_028A4C_PA_SC_MODE_CNTL_1
,
2030 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
2031 S_028004_SAMPLE_RATE(sample_rate
);
2035 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
2037 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
2041 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
2043 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
2045 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
2046 radv_emit_viewport(cmd_buffer
);
2048 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
2049 !cmd_buffer
->device
->physical_device
->has_scissor_bug
)
2050 radv_emit_scissor(cmd_buffer
);
2052 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
2053 radv_emit_line_width(cmd_buffer
);
2055 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
2056 radv_emit_blend_constants(cmd_buffer
);
2058 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
2059 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
2060 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
2061 radv_emit_stencil(cmd_buffer
);
2063 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
2064 radv_emit_depth_bounds(cmd_buffer
);
2066 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
2067 radv_emit_depth_bias(cmd_buffer
);
2069 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
2070 radv_emit_discard_rectangle(cmd_buffer
);
2072 if (states
& RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
)
2073 radv_emit_sample_locations(cmd_buffer
);
2075 cmd_buffer
->state
.dirty
&= ~states
;
2079 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2080 VkPipelineBindPoint bind_point
)
2082 struct radv_descriptor_state
*descriptors_state
=
2083 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2084 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
2087 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
2092 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2093 set
->va
+= bo_offset
;
2097 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
2098 VkPipelineBindPoint bind_point
)
2100 struct radv_descriptor_state
*descriptors_state
=
2101 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2102 uint32_t size
= MAX_SETS
* 4;
2106 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
2107 256, &offset
, &ptr
))
2110 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2111 uint32_t *uptr
= ((uint32_t *)ptr
) + i
;
2112 uint64_t set_va
= 0;
2113 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
2114 if (descriptors_state
->valid
& (1u << i
))
2116 uptr
[0] = set_va
& 0xffffffff;
2119 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2122 if (cmd_buffer
->state
.pipeline
) {
2123 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
2124 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2125 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2127 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
2128 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
2129 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2131 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
2132 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2133 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2135 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2136 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
2137 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2139 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2140 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
2141 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2144 if (cmd_buffer
->state
.compute_pipeline
)
2145 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
2146 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2150 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2151 VkShaderStageFlags stages
)
2153 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2154 VK_PIPELINE_BIND_POINT_COMPUTE
:
2155 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2156 struct radv_descriptor_state
*descriptors_state
=
2157 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2158 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2159 bool flush_indirect_descriptors
;
2161 if (!descriptors_state
->dirty
)
2164 if (descriptors_state
->push_dirty
)
2165 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
2167 flush_indirect_descriptors
=
2168 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
2169 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
2170 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
2171 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
2173 if (flush_indirect_descriptors
)
2174 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
2176 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2178 MAX_SETS
* MESA_SHADER_STAGES
* 4);
2180 if (cmd_buffer
->state
.pipeline
) {
2181 radv_foreach_stage(stage
, stages
) {
2182 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
2185 radv_emit_descriptor_pointers(cmd_buffer
,
2186 cmd_buffer
->state
.pipeline
,
2187 descriptors_state
, stage
);
2191 if (cmd_buffer
->state
.compute_pipeline
&&
2192 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
2193 radv_emit_descriptor_pointers(cmd_buffer
,
2194 cmd_buffer
->state
.compute_pipeline
,
2196 MESA_SHADER_COMPUTE
);
2199 descriptors_state
->dirty
= 0;
2200 descriptors_state
->push_dirty
= false;
2202 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2204 if (unlikely(cmd_buffer
->device
->trace_bo
))
2205 radv_save_descriptors(cmd_buffer
, bind_point
);
2209 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
2210 VkShaderStageFlags stages
)
2212 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
2213 ? cmd_buffer
->state
.compute_pipeline
2214 : cmd_buffer
->state
.pipeline
;
2215 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2216 VK_PIPELINE_BIND_POINT_COMPUTE
:
2217 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2218 struct radv_descriptor_state
*descriptors_state
=
2219 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2220 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
2221 struct radv_shader_variant
*shader
, *prev_shader
;
2222 bool need_push_constants
= false;
2227 stages
&= cmd_buffer
->push_constant_stages
;
2229 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
2232 radv_foreach_stage(stage
, stages
) {
2233 if (!pipeline
->shaders
[stage
])
2236 need_push_constants
|= pipeline
->shaders
[stage
]->info
.info
.loads_push_constants
;
2237 need_push_constants
|= pipeline
->shaders
[stage
]->info
.info
.loads_dynamic_offsets
;
2239 uint8_t base
= pipeline
->shaders
[stage
]->info
.info
.base_inline_push_consts
;
2240 uint8_t count
= pipeline
->shaders
[stage
]->info
.info
.num_inline_push_consts
;
2242 radv_emit_inline_push_consts(cmd_buffer
, pipeline
, stage
,
2243 AC_UD_INLINE_PUSH_CONSTANTS
,
2245 (uint32_t *)&cmd_buffer
->push_constants
[base
* 4]);
2248 if (need_push_constants
) {
2249 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
2250 16 * layout
->dynamic_offset_count
,
2251 256, &offset
, &ptr
))
2254 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
2255 memcpy((char*)ptr
+ layout
->push_constant_size
,
2256 descriptors_state
->dynamic_buffers
,
2257 16 * layout
->dynamic_offset_count
);
2259 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2262 MAYBE_UNUSED
unsigned cdw_max
=
2263 radeon_check_space(cmd_buffer
->device
->ws
,
2264 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
2267 radv_foreach_stage(stage
, stages
) {
2268 shader
= radv_get_shader(pipeline
, stage
);
2270 /* Avoid redundantly emitting the address for merged stages. */
2271 if (shader
&& shader
!= prev_shader
) {
2272 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
2273 AC_UD_PUSH_CONSTANTS
, va
);
2275 prev_shader
= shader
;
2278 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2281 cmd_buffer
->push_constant_stages
&= ~stages
;
2285 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2286 bool pipeline_is_dirty
)
2288 if ((pipeline_is_dirty
||
2289 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
2290 cmd_buffer
->state
.pipeline
->num_vertex_bindings
&&
2291 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.has_vertex_buffers
) {
2292 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
2296 uint32_t count
= cmd_buffer
->state
.pipeline
->num_vertex_bindings
;
2299 /* allocate some descriptor state for vertex buffers */
2300 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
2301 &vb_offset
, &vb_ptr
))
2304 for (i
= 0; i
< count
; i
++) {
2305 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
2307 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[i
].buffer
;
2308 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[i
];
2313 va
= radv_buffer_get_va(buffer
->bo
);
2315 offset
= cmd_buffer
->vertex_bindings
[i
].offset
;
2316 va
+= offset
+ buffer
->offset
;
2318 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
2319 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= GFX7
&& stride
)
2320 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
2322 desc
[2] = buffer
->size
- offset
;
2323 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2324 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2325 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2326 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2328 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2329 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT
) |
2330 S_008F0C_OOB_SELECT(1) |
2331 S_008F0C_RESOURCE_LEVEL(1);
2333 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
2334 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2338 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2341 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2342 AC_UD_VS_VERTEX_BUFFERS
, va
);
2344 cmd_buffer
->state
.vb_va
= va
;
2345 cmd_buffer
->state
.vb_size
= count
* 16;
2346 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
2348 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
2352 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
2354 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2355 struct radv_userdata_info
*loc
;
2358 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2359 if (!radv_get_shader(pipeline
, stage
))
2362 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
2363 AC_UD_STREAMOUT_BUFFERS
);
2364 if (loc
->sgpr_idx
== -1)
2367 base_reg
= pipeline
->user_data_0
[stage
];
2369 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2370 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2373 if (pipeline
->gs_copy_shader
) {
2374 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
2375 if (loc
->sgpr_idx
!= -1) {
2376 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2378 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2379 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2385 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
2387 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
2388 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
2389 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
2394 /* Allocate some descriptor state for streamout buffers. */
2395 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
2396 MAX_SO_BUFFERS
* 16, 256,
2397 &so_offset
, &so_ptr
))
2400 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
2401 struct radv_buffer
*buffer
= sb
[i
].buffer
;
2402 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
2404 if (!(so
->enabled_mask
& (1 << i
)))
2407 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
2411 /* Set the descriptor.
2413 * On GFX8, the format must be non-INVALID, otherwise
2414 * the buffer will be considered not bound and store
2415 * instructions will be no-ops.
2418 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2419 desc
[2] = 0xffffffff;
2420 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2421 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2422 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2423 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2424 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2427 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2430 radv_emit_streamout_buffers(cmd_buffer
, va
);
2433 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
2437 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
2439 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
2440 radv_flush_streamout_descriptors(cmd_buffer
);
2441 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2442 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2445 struct radv_draw_info
{
2447 * Number of vertices.
2452 * Index of the first vertex.
2454 int32_t vertex_offset
;
2457 * First instance id.
2459 uint32_t first_instance
;
2462 * Number of instances.
2464 uint32_t instance_count
;
2467 * First index (indexed draws only).
2469 uint32_t first_index
;
2472 * Whether it's an indexed draw.
2477 * Indirect draw parameters resource.
2479 struct radv_buffer
*indirect
;
2480 uint64_t indirect_offset
;
2484 * Draw count parameters resource.
2486 struct radv_buffer
*count_buffer
;
2487 uint64_t count_buffer_offset
;
2490 * Stream output parameters resource.
2492 struct radv_buffer
*strmout_buffer
;
2493 uint64_t strmout_buffer_offset
;
2497 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
2498 bool instanced_draw
, bool indirect_draw
,
2499 bool count_from_stream_output
,
2500 uint32_t draw_vertex_count
)
2502 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2503 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2504 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2505 unsigned ia_multi_vgt_param
;
2507 ia_multi_vgt_param
=
2508 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
2510 count_from_stream_output
,
2513 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2514 if (info
->chip_class
>= GFX9
) {
2515 radeon_set_uconfig_reg_idx(cs
,
2516 R_030960_IA_MULTI_VGT_PARAM
,
2517 4, ia_multi_vgt_param
);
2518 } else if (info
->chip_class
>= GFX7
) {
2519 radeon_set_context_reg_idx(cs
,
2520 R_028AA8_IA_MULTI_VGT_PARAM
,
2521 1, ia_multi_vgt_param
);
2523 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2524 ia_multi_vgt_param
);
2526 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
2531 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
,
2532 const struct radv_draw_info
*draw_info
)
2534 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2535 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2536 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2537 int32_t primitive_reset_en
;
2540 if (info
->chip_class
< GFX10
) {
2541 si_emit_ia_multi_vgt_param(cmd_buffer
, draw_info
->instance_count
> 1,
2542 draw_info
->indirect
,
2543 !!draw_info
->strmout_buffer
,
2544 draw_info
->indirect
? 0 : draw_info
->count
);
2547 /* Primitive restart. */
2548 primitive_reset_en
=
2549 draw_info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
;
2551 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
2552 state
->last_primitive_reset_en
= primitive_reset_en
;
2553 if (info
->chip_class
>= GFX9
) {
2554 radeon_set_uconfig_reg(cs
,
2555 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
2556 primitive_reset_en
);
2558 radeon_set_context_reg(cs
,
2559 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
2560 primitive_reset_en
);
2564 if (primitive_reset_en
) {
2565 uint32_t primitive_reset_index
=
2566 state
->index_type
? 0xffffffffu
: 0xffffu
;
2568 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
2569 radeon_set_context_reg(cs
,
2570 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
2571 primitive_reset_index
);
2572 state
->last_primitive_reset_index
= primitive_reset_index
;
2576 if (draw_info
->strmout_buffer
) {
2577 uint64_t va
= radv_buffer_get_va(draw_info
->strmout_buffer
->bo
);
2579 va
+= draw_info
->strmout_buffer
->offset
+
2580 draw_info
->strmout_buffer_offset
;
2582 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
2585 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2586 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2587 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2588 COPY_DATA_WR_CONFIRM
);
2589 radeon_emit(cs
, va
);
2590 radeon_emit(cs
, va
>> 32);
2591 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
2592 radeon_emit(cs
, 0); /* unused */
2594 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, draw_info
->strmout_buffer
->bo
);
2598 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
2599 VkPipelineStageFlags src_stage_mask
)
2601 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
2602 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2603 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2604 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2605 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
2608 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
2609 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
2610 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
2611 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
2612 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2613 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2614 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
2615 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2616 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2617 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
2618 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
2619 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
2620 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
2621 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
2622 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
2623 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
2624 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
2628 static enum radv_cmd_flush_bits
2629 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2630 VkAccessFlags src_flags
,
2631 struct radv_image
*image
)
2633 bool flush_CB_meta
= true, flush_DB_meta
= true;
2634 enum radv_cmd_flush_bits flush_bits
= 0;
2638 if (!radv_image_has_CB_metadata(image
))
2639 flush_CB_meta
= false;
2640 if (!radv_image_has_htile(image
))
2641 flush_DB_meta
= false;
2644 for_each_bit(b
, src_flags
) {
2645 switch ((VkAccessFlagBits
)(1 << b
)) {
2646 case VK_ACCESS_SHADER_WRITE_BIT
:
2647 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
2648 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2649 flush_bits
|= RADV_CMD_FLAG_WB_L2
;
2651 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2652 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2654 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2656 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2657 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2659 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2661 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2662 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2663 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2664 RADV_CMD_FLAG_INV_L2
;
2667 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2669 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2678 static enum radv_cmd_flush_bits
2679 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2680 VkAccessFlags dst_flags
,
2681 struct radv_image
*image
)
2683 bool flush_CB_meta
= true, flush_DB_meta
= true;
2684 enum radv_cmd_flush_bits flush_bits
= 0;
2685 bool flush_CB
= true, flush_DB
= true;
2686 bool image_is_coherent
= false;
2690 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
2695 if (!radv_image_has_CB_metadata(image
))
2696 flush_CB_meta
= false;
2697 if (!radv_image_has_htile(image
))
2698 flush_DB_meta
= false;
2700 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2701 if (image
->info
.samples
== 1 &&
2702 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
2703 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
2704 !vk_format_is_stencil(image
->vk_format
)) {
2705 /* Single-sample color and single-sample depth
2706 * (not stencil) are coherent with shaders on
2709 image_is_coherent
= true;
2714 for_each_bit(b
, dst_flags
) {
2715 switch ((VkAccessFlagBits
)(1 << b
)) {
2716 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2717 case VK_ACCESS_INDEX_READ_BIT
:
2718 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2720 case VK_ACCESS_UNIFORM_READ_BIT
:
2721 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
| RADV_CMD_FLAG_INV_SCACHE
;
2723 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2724 case VK_ACCESS_TRANSFER_READ_BIT
:
2725 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2726 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
|
2727 RADV_CMD_FLAG_INV_L2
;
2729 case VK_ACCESS_SHADER_READ_BIT
:
2730 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
;
2732 if (!image_is_coherent
)
2733 flush_bits
|= RADV_CMD_FLAG_INV_L2
;
2735 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2737 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2739 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2741 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2743 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2745 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2754 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2755 const struct radv_subpass_barrier
*barrier
)
2757 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2759 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2760 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2765 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
)
2767 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2768 uint32_t subpass_id
= state
->subpass
- state
->pass
->subpasses
;
2770 /* The id of this subpass shouldn't exceed the number of subpasses in
2771 * this render pass minus 1.
2773 assert(subpass_id
< state
->pass
->subpass_count
);
2777 static struct radv_sample_locations_state
*
2778 radv_get_attachment_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
2782 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2783 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
2784 struct radv_image_view
*view
= state
->framebuffer
->attachments
[att_idx
].attachment
;
2786 if (view
->image
->info
.samples
== 1)
2789 if (state
->pass
->attachments
[att_idx
].first_subpass_idx
== subpass_id
) {
2790 /* Return the initial sample locations if this is the initial
2791 * layout transition of the given subpass attachemnt.
2793 if (state
->attachments
[att_idx
].sample_location
.count
> 0)
2794 return &state
->attachments
[att_idx
].sample_location
;
2796 /* Otherwise return the subpass sample locations if defined. */
2797 if (state
->subpass_sample_locs
) {
2798 /* Because the driver sets the current subpass before
2799 * initial layout transitions, we should use the sample
2800 * locations from the previous subpass to avoid an
2801 * off-by-one problem. Otherwise, use the sample
2802 * locations for the current subpass for final layout
2808 for (uint32_t i
= 0; i
< state
->num_subpass_sample_locs
; i
++) {
2809 if (state
->subpass_sample_locs
[i
].subpass_idx
== subpass_id
)
2810 return &state
->subpass_sample_locs
[i
].sample_location
;
2818 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2819 struct radv_subpass_attachment att
,
2822 unsigned idx
= att
.attachment
;
2823 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
2824 struct radv_sample_locations_state
*sample_locs
;
2825 VkImageSubresourceRange range
;
2826 range
.aspectMask
= 0;
2827 range
.baseMipLevel
= view
->base_mip
;
2828 range
.levelCount
= 1;
2829 range
.baseArrayLayer
= view
->base_layer
;
2830 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2832 if (cmd_buffer
->state
.subpass
->view_mask
) {
2833 /* If the current subpass uses multiview, the driver might have
2834 * performed a fast color/depth clear to the whole image
2835 * (including all layers). To make sure the driver will
2836 * decompress the image correctly (if needed), we have to
2837 * account for the "real" number of layers. If the view mask is
2838 * sparse, this will decompress more layers than needed.
2840 range
.layerCount
= util_last_bit(cmd_buffer
->state
.subpass
->view_mask
);
2843 /* Get the subpass sample locations for the given attachment, if NULL
2844 * is returned the driver will use the default HW locations.
2846 sample_locs
= radv_get_attachment_sample_locations(cmd_buffer
, idx
,
2849 radv_handle_image_transition(cmd_buffer
,
2851 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2852 att
.layout
, 0, 0, &range
, sample_locs
);
2854 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2860 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2861 const struct radv_subpass
*subpass
)
2863 cmd_buffer
->state
.subpass
= subpass
;
2865 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2869 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
2870 struct radv_render_pass
*pass
,
2871 const VkRenderPassBeginInfo
*info
)
2873 const struct VkRenderPassSampleLocationsBeginInfoEXT
*sample_locs
=
2874 vk_find_struct_const(info
->pNext
,
2875 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT
);
2876 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2877 struct radv_framebuffer
*framebuffer
= state
->framebuffer
;
2880 state
->subpass_sample_locs
= NULL
;
2884 for (uint32_t i
= 0; i
< sample_locs
->attachmentInitialSampleLocationsCount
; i
++) {
2885 const VkAttachmentSampleLocationsEXT
*att_sample_locs
=
2886 &sample_locs
->pAttachmentInitialSampleLocations
[i
];
2887 uint32_t att_idx
= att_sample_locs
->attachmentIndex
;
2888 struct radv_attachment_info
*att
= &framebuffer
->attachments
[att_idx
];
2889 struct radv_image
*image
= att
->attachment
->image
;
2891 assert(vk_format_is_depth_or_stencil(image
->vk_format
));
2893 /* From the Vulkan spec 1.1.108:
2895 * "If the image referenced by the framebuffer attachment at
2896 * index attachmentIndex was not created with
2897 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2898 * then the values specified in sampleLocationsInfo are
2901 if (!(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
))
2904 const VkSampleLocationsInfoEXT
*sample_locs_info
=
2905 &att_sample_locs
->sampleLocationsInfo
;
2907 state
->attachments
[att_idx
].sample_location
.per_pixel
=
2908 sample_locs_info
->sampleLocationsPerPixel
;
2909 state
->attachments
[att_idx
].sample_location
.grid_size
=
2910 sample_locs_info
->sampleLocationGridSize
;
2911 state
->attachments
[att_idx
].sample_location
.count
=
2912 sample_locs_info
->sampleLocationsCount
;
2913 typed_memcpy(&state
->attachments
[att_idx
].sample_location
.locations
[0],
2914 sample_locs_info
->pSampleLocations
,
2915 sample_locs_info
->sampleLocationsCount
);
2918 state
->subpass_sample_locs
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2919 sample_locs
->postSubpassSampleLocationsCount
*
2920 sizeof(state
->subpass_sample_locs
[0]),
2921 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2922 if (state
->subpass_sample_locs
== NULL
) {
2923 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2924 return cmd_buffer
->record_result
;
2927 state
->num_subpass_sample_locs
= sample_locs
->postSubpassSampleLocationsCount
;
2929 for (uint32_t i
= 0; i
< sample_locs
->postSubpassSampleLocationsCount
; i
++) {
2930 const VkSubpassSampleLocationsEXT
*subpass_sample_locs_info
=
2931 &sample_locs
->pPostSubpassSampleLocations
[i
];
2932 const VkSampleLocationsInfoEXT
*sample_locs_info
=
2933 &subpass_sample_locs_info
->sampleLocationsInfo
;
2935 state
->subpass_sample_locs
[i
].subpass_idx
=
2936 subpass_sample_locs_info
->subpassIndex
;
2937 state
->subpass_sample_locs
[i
].sample_location
.per_pixel
=
2938 sample_locs_info
->sampleLocationsPerPixel
;
2939 state
->subpass_sample_locs
[i
].sample_location
.grid_size
=
2940 sample_locs_info
->sampleLocationGridSize
;
2941 state
->subpass_sample_locs
[i
].sample_location
.count
=
2942 sample_locs_info
->sampleLocationsCount
;
2943 typed_memcpy(&state
->subpass_sample_locs
[i
].sample_location
.locations
[0],
2944 sample_locs_info
->pSampleLocations
,
2945 sample_locs_info
->sampleLocationsCount
);
2952 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
2953 struct radv_render_pass
*pass
,
2954 const VkRenderPassBeginInfo
*info
)
2956 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2958 if (pass
->attachment_count
== 0) {
2959 state
->attachments
= NULL
;
2963 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2964 pass
->attachment_count
*
2965 sizeof(state
->attachments
[0]),
2966 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2967 if (state
->attachments
== NULL
) {
2968 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2969 return cmd_buffer
->record_result
;
2972 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
2973 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
2974 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
2975 VkImageAspectFlags clear_aspects
= 0;
2977 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2978 /* color attachment */
2979 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2980 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
2983 /* depthstencil attachment */
2984 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2985 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2986 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
2987 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2988 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
2989 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2991 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2992 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2993 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2997 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
2998 state
->attachments
[i
].cleared_views
= 0;
2999 if (clear_aspects
&& info
) {
3000 assert(info
->clearValueCount
> i
);
3001 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
3004 state
->attachments
[i
].current_layout
= att
->initial_layout
;
3005 state
->attachments
[i
].sample_location
.count
= 0;
3011 VkResult
radv_AllocateCommandBuffers(
3013 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
3014 VkCommandBuffer
*pCommandBuffers
)
3016 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3017 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
3019 VkResult result
= VK_SUCCESS
;
3022 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
3024 if (!list_empty(&pool
->free_cmd_buffers
)) {
3025 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
3027 list_del(&cmd_buffer
->pool_link
);
3028 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
3030 result
= radv_reset_cmd_buffer(cmd_buffer
);
3031 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
3032 cmd_buffer
->level
= pAllocateInfo
->level
;
3034 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
3036 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
3037 &pCommandBuffers
[i
]);
3039 if (result
!= VK_SUCCESS
)
3043 if (result
!= VK_SUCCESS
) {
3044 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
3045 i
, pCommandBuffers
);
3047 /* From the Vulkan 1.0.66 spec:
3049 * "vkAllocateCommandBuffers can be used to create multiple
3050 * command buffers. If the creation of any of those command
3051 * buffers fails, the implementation must destroy all
3052 * successfully created command buffer objects from this
3053 * command, set all entries of the pCommandBuffers array to
3054 * NULL and return the error."
3056 memset(pCommandBuffers
, 0,
3057 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
3063 void radv_FreeCommandBuffers(
3065 VkCommandPool commandPool
,
3066 uint32_t commandBufferCount
,
3067 const VkCommandBuffer
*pCommandBuffers
)
3069 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3070 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
3073 if (cmd_buffer
->pool
) {
3074 list_del(&cmd_buffer
->pool_link
);
3075 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
3077 radv_cmd_buffer_destroy(cmd_buffer
);
3083 VkResult
radv_ResetCommandBuffer(
3084 VkCommandBuffer commandBuffer
,
3085 VkCommandBufferResetFlags flags
)
3087 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3088 return radv_reset_cmd_buffer(cmd_buffer
);
3091 VkResult
radv_BeginCommandBuffer(
3092 VkCommandBuffer commandBuffer
,
3093 const VkCommandBufferBeginInfo
*pBeginInfo
)
3095 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3096 VkResult result
= VK_SUCCESS
;
3098 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
3099 /* If the command buffer has already been resetted with
3100 * vkResetCommandBuffer, no need to do it again.
3102 result
= radv_reset_cmd_buffer(cmd_buffer
);
3103 if (result
!= VK_SUCCESS
)
3107 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
3108 cmd_buffer
->state
.last_primitive_reset_en
= -1;
3109 cmd_buffer
->state
.last_index_type
= -1;
3110 cmd_buffer
->state
.last_num_instances
= -1;
3111 cmd_buffer
->state
.last_vertex_offset
= -1;
3112 cmd_buffer
->state
.last_first_instance
= -1;
3113 cmd_buffer
->state
.predication_type
= -1;
3114 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
3116 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
3117 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
3118 assert(pBeginInfo
->pInheritanceInfo
);
3119 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
3120 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
3122 struct radv_subpass
*subpass
=
3123 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
3125 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
3126 if (result
!= VK_SUCCESS
)
3129 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
3132 if (unlikely(cmd_buffer
->device
->trace_bo
)) {
3133 struct radv_device
*device
= cmd_buffer
->device
;
3135 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
,
3138 radv_cmd_buffer_trace_emit(cmd_buffer
);
3141 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
3146 void radv_CmdBindVertexBuffers(
3147 VkCommandBuffer commandBuffer
,
3148 uint32_t firstBinding
,
3149 uint32_t bindingCount
,
3150 const VkBuffer
* pBuffers
,
3151 const VkDeviceSize
* pOffsets
)
3153 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3154 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
3155 bool changed
= false;
3157 /* We have to defer setting up vertex buffer since we need the buffer
3158 * stride from the pipeline. */
3160 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
3161 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
3162 uint32_t idx
= firstBinding
+ i
;
3165 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
3166 vb
[idx
].offset
!= pOffsets
[i
])) {
3170 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
3171 vb
[idx
].offset
= pOffsets
[i
];
3173 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3174 vb
[idx
].buffer
->bo
);
3178 /* No state changes. */
3182 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
3185 void radv_CmdBindIndexBuffer(
3186 VkCommandBuffer commandBuffer
,
3188 VkDeviceSize offset
,
3189 VkIndexType indexType
)
3191 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3192 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
3194 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
3195 cmd_buffer
->state
.index_offset
== offset
&&
3196 cmd_buffer
->state
.index_type
== indexType
) {
3197 /* No state changes. */
3201 cmd_buffer
->state
.index_buffer
= index_buffer
;
3202 cmd_buffer
->state
.index_offset
= offset
;
3203 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
3204 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
3205 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
3207 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
3208 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
3209 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3210 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
3215 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3216 VkPipelineBindPoint bind_point
,
3217 struct radv_descriptor_set
*set
, unsigned idx
)
3219 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3221 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
3224 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
3226 if (!cmd_buffer
->device
->use_global_bo_list
) {
3227 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
3228 if (set
->descriptors
[j
])
3229 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
3233 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
3236 void radv_CmdBindDescriptorSets(
3237 VkCommandBuffer commandBuffer
,
3238 VkPipelineBindPoint pipelineBindPoint
,
3239 VkPipelineLayout _layout
,
3241 uint32_t descriptorSetCount
,
3242 const VkDescriptorSet
* pDescriptorSets
,
3243 uint32_t dynamicOffsetCount
,
3244 const uint32_t* pDynamicOffsets
)
3246 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3247 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3248 unsigned dyn_idx
= 0;
3250 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
3251 struct radv_descriptor_state
*descriptors_state
=
3252 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3254 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
3255 unsigned idx
= i
+ firstSet
;
3256 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
3257 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
3259 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
3260 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
3261 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
3262 assert(dyn_idx
< dynamicOffsetCount
);
3264 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
3265 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
3267 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
3268 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
3269 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3270 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3271 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3272 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3274 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3275 dst
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3276 S_008F0C_OOB_SELECT(3) |
3277 S_008F0C_RESOURCE_LEVEL(1);
3279 dst
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3280 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3283 cmd_buffer
->push_constant_stages
|=
3284 set
->layout
->dynamic_shader_stages
;
3289 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3290 struct radv_descriptor_set
*set
,
3291 struct radv_descriptor_set_layout
*layout
,
3292 VkPipelineBindPoint bind_point
)
3294 struct radv_descriptor_state
*descriptors_state
=
3295 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3296 set
->size
= layout
->size
;
3297 set
->layout
= layout
;
3299 if (descriptors_state
->push_set
.capacity
< set
->size
) {
3300 size_t new_size
= MAX2(set
->size
, 1024);
3301 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
3302 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
3304 free(set
->mapped_ptr
);
3305 set
->mapped_ptr
= malloc(new_size
);
3307 if (!set
->mapped_ptr
) {
3308 descriptors_state
->push_set
.capacity
= 0;
3309 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3313 descriptors_state
->push_set
.capacity
= new_size
;
3319 void radv_meta_push_descriptor_set(
3320 struct radv_cmd_buffer
* cmd_buffer
,
3321 VkPipelineBindPoint pipelineBindPoint
,
3322 VkPipelineLayout _layout
,
3324 uint32_t descriptorWriteCount
,
3325 const VkWriteDescriptorSet
* pDescriptorWrites
)
3327 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3328 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
3332 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3334 push_set
->size
= layout
->set
[set
].layout
->size
;
3335 push_set
->layout
= layout
->set
[set
].layout
;
3337 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
3339 (void**) &push_set
->mapped_ptr
))
3342 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
3343 push_set
->va
+= bo_offset
;
3345 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3346 radv_descriptor_set_to_handle(push_set
),
3347 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3349 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3352 void radv_CmdPushDescriptorSetKHR(
3353 VkCommandBuffer commandBuffer
,
3354 VkPipelineBindPoint pipelineBindPoint
,
3355 VkPipelineLayout _layout
,
3357 uint32_t descriptorWriteCount
,
3358 const VkWriteDescriptorSet
* pDescriptorWrites
)
3360 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3361 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3362 struct radv_descriptor_state
*descriptors_state
=
3363 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3364 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3366 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3368 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3369 layout
->set
[set
].layout
,
3373 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3374 * because it is invalid, according to Vulkan spec.
3376 for (int i
= 0; i
< descriptorWriteCount
; i
++) {
3377 MAYBE_UNUSED
const VkWriteDescriptorSet
*writeset
= &pDescriptorWrites
[i
];
3378 assert(writeset
->descriptorType
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
);
3381 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3382 radv_descriptor_set_to_handle(push_set
),
3383 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3385 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3386 descriptors_state
->push_dirty
= true;
3389 void radv_CmdPushDescriptorSetWithTemplateKHR(
3390 VkCommandBuffer commandBuffer
,
3391 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
3392 VkPipelineLayout _layout
,
3396 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3397 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3398 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
3399 struct radv_descriptor_state
*descriptors_state
=
3400 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
3401 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3403 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3405 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3406 layout
->set
[set
].layout
,
3410 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
3411 descriptorUpdateTemplate
, pData
);
3413 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
3414 descriptors_state
->push_dirty
= true;
3417 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
3418 VkPipelineLayout layout
,
3419 VkShaderStageFlags stageFlags
,
3422 const void* pValues
)
3424 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3425 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
3426 cmd_buffer
->push_constant_stages
|= stageFlags
;
3429 VkResult
radv_EndCommandBuffer(
3430 VkCommandBuffer commandBuffer
)
3432 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3434 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
3435 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX6
)
3436 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WB_L2
;
3438 /* Make sure to sync all pending active queries at the end of
3441 cmd_buffer
->state
.flush_bits
|= cmd_buffer
->active_query_flush_bits
;
3443 si_emit_cache_flush(cmd_buffer
);
3446 /* Make sure CP DMA is idle at the end of IBs because the kernel
3447 * doesn't wait for it.
3449 si_cp_dma_wait_for_idle(cmd_buffer
);
3451 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3452 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
3454 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
3455 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3457 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
3459 return cmd_buffer
->record_result
;
3463 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
3465 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3467 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
3470 assert(!pipeline
->ctx_cs
.cdw
);
3472 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
3474 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
3475 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
3477 cmd_buffer
->compute_scratch_size_needed
=
3478 MAX2(cmd_buffer
->compute_scratch_size_needed
,
3479 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
3481 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3482 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
3484 if (unlikely(cmd_buffer
->device
->trace_bo
))
3485 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
3488 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
3489 VkPipelineBindPoint bind_point
)
3491 struct radv_descriptor_state
*descriptors_state
=
3492 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3494 descriptors_state
->dirty
|= descriptors_state
->valid
;
3497 void radv_CmdBindPipeline(
3498 VkCommandBuffer commandBuffer
,
3499 VkPipelineBindPoint pipelineBindPoint
,
3500 VkPipeline _pipeline
)
3502 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3503 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
3505 switch (pipelineBindPoint
) {
3506 case VK_PIPELINE_BIND_POINT_COMPUTE
:
3507 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
3509 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3511 cmd_buffer
->state
.compute_pipeline
= pipeline
;
3512 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3514 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
3515 if (cmd_buffer
->state
.pipeline
== pipeline
)
3517 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3519 cmd_buffer
->state
.pipeline
= pipeline
;
3523 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
3524 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
3526 /* the new vertex shader might not have the same user regs */
3527 cmd_buffer
->state
.last_first_instance
= -1;
3528 cmd_buffer
->state
.last_vertex_offset
= -1;
3530 /* Prefetch all pipeline shaders at first draw time. */
3531 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
3533 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
3534 radv_bind_streamout_state(cmd_buffer
, pipeline
);
3536 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
3537 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
3538 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
3539 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
3541 if (radv_pipeline_has_tess(pipeline
))
3542 cmd_buffer
->tess_rings_needed
= true;
3545 assert(!"invalid bind point");
3550 void radv_CmdSetViewport(
3551 VkCommandBuffer commandBuffer
,
3552 uint32_t firstViewport
,
3553 uint32_t viewportCount
,
3554 const VkViewport
* pViewports
)
3556 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3557 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3558 MAYBE_UNUSED
const uint32_t total_count
= firstViewport
+ viewportCount
;
3560 assert(firstViewport
< MAX_VIEWPORTS
);
3561 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
3563 if (!memcmp(state
->dynamic
.viewport
.viewports
+ firstViewport
,
3564 pViewports
, viewportCount
* sizeof(*pViewports
))) {
3568 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
3569 viewportCount
* sizeof(*pViewports
));
3571 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
3574 void radv_CmdSetScissor(
3575 VkCommandBuffer commandBuffer
,
3576 uint32_t firstScissor
,
3577 uint32_t scissorCount
,
3578 const VkRect2D
* pScissors
)
3580 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3581 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3582 MAYBE_UNUSED
const uint32_t total_count
= firstScissor
+ scissorCount
;
3584 assert(firstScissor
< MAX_SCISSORS
);
3585 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
3587 if (!memcmp(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3588 scissorCount
* sizeof(*pScissors
))) {
3592 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3593 scissorCount
* sizeof(*pScissors
));
3595 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
3598 void radv_CmdSetLineWidth(
3599 VkCommandBuffer commandBuffer
,
3602 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3604 if (cmd_buffer
->state
.dynamic
.line_width
== lineWidth
)
3607 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
3608 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
3611 void radv_CmdSetDepthBias(
3612 VkCommandBuffer commandBuffer
,
3613 float depthBiasConstantFactor
,
3614 float depthBiasClamp
,
3615 float depthBiasSlopeFactor
)
3617 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3618 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3620 if (state
->dynamic
.depth_bias
.bias
== depthBiasConstantFactor
&&
3621 state
->dynamic
.depth_bias
.clamp
== depthBiasClamp
&&
3622 state
->dynamic
.depth_bias
.slope
== depthBiasSlopeFactor
) {
3626 state
->dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
3627 state
->dynamic
.depth_bias
.clamp
= depthBiasClamp
;
3628 state
->dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
3630 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
3633 void radv_CmdSetBlendConstants(
3634 VkCommandBuffer commandBuffer
,
3635 const float blendConstants
[4])
3637 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3638 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3640 if (!memcmp(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4))
3643 memcpy(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4);
3645 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
3648 void radv_CmdSetDepthBounds(
3649 VkCommandBuffer commandBuffer
,
3650 float minDepthBounds
,
3651 float maxDepthBounds
)
3653 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3654 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3656 if (state
->dynamic
.depth_bounds
.min
== minDepthBounds
&&
3657 state
->dynamic
.depth_bounds
.max
== maxDepthBounds
) {
3661 state
->dynamic
.depth_bounds
.min
= minDepthBounds
;
3662 state
->dynamic
.depth_bounds
.max
= maxDepthBounds
;
3664 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
3667 void radv_CmdSetStencilCompareMask(
3668 VkCommandBuffer commandBuffer
,
3669 VkStencilFaceFlags faceMask
,
3670 uint32_t compareMask
)
3672 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3673 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3674 bool front_same
= state
->dynamic
.stencil_compare_mask
.front
== compareMask
;
3675 bool back_same
= state
->dynamic
.stencil_compare_mask
.back
== compareMask
;
3677 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3678 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3682 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3683 state
->dynamic
.stencil_compare_mask
.front
= compareMask
;
3684 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3685 state
->dynamic
.stencil_compare_mask
.back
= compareMask
;
3687 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
3690 void radv_CmdSetStencilWriteMask(
3691 VkCommandBuffer commandBuffer
,
3692 VkStencilFaceFlags faceMask
,
3695 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3696 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3697 bool front_same
= state
->dynamic
.stencil_write_mask
.front
== writeMask
;
3698 bool back_same
= state
->dynamic
.stencil_write_mask
.back
== writeMask
;
3700 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3701 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3705 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3706 state
->dynamic
.stencil_write_mask
.front
= writeMask
;
3707 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3708 state
->dynamic
.stencil_write_mask
.back
= writeMask
;
3710 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
3713 void radv_CmdSetStencilReference(
3714 VkCommandBuffer commandBuffer
,
3715 VkStencilFaceFlags faceMask
,
3718 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3719 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3720 bool front_same
= state
->dynamic
.stencil_reference
.front
== reference
;
3721 bool back_same
= state
->dynamic
.stencil_reference
.back
== reference
;
3723 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3724 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3728 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3729 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
3730 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3731 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
3733 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
3736 void radv_CmdSetDiscardRectangleEXT(
3737 VkCommandBuffer commandBuffer
,
3738 uint32_t firstDiscardRectangle
,
3739 uint32_t discardRectangleCount
,
3740 const VkRect2D
* pDiscardRectangles
)
3742 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3743 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3744 MAYBE_UNUSED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
3746 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
3747 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
3749 if (!memcmp(state
->dynamic
.discard_rectangle
.rectangles
+ firstDiscardRectangle
,
3750 pDiscardRectangles
, discardRectangleCount
* sizeof(*pDiscardRectangles
))) {
3754 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
3755 pDiscardRectangles
, discardRectangleCount
);
3757 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
3760 void radv_CmdSetSampleLocationsEXT(
3761 VkCommandBuffer commandBuffer
,
3762 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
3764 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3765 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3767 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
3769 state
->dynamic
.sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
3770 state
->dynamic
.sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
3771 state
->dynamic
.sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
3772 typed_memcpy(&state
->dynamic
.sample_location
.locations
[0],
3773 pSampleLocationsInfo
->pSampleLocations
,
3774 pSampleLocationsInfo
->sampleLocationsCount
);
3776 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
;
3779 void radv_CmdExecuteCommands(
3780 VkCommandBuffer commandBuffer
,
3781 uint32_t commandBufferCount
,
3782 const VkCommandBuffer
* pCmdBuffers
)
3784 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
3786 assert(commandBufferCount
> 0);
3788 /* Emit pending flushes on primary prior to executing secondary */
3789 si_emit_cache_flush(primary
);
3791 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3792 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
3794 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
3795 secondary
->scratch_size_needed
);
3796 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
3797 secondary
->compute_scratch_size_needed
);
3799 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
3800 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
3801 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
3802 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
3803 if (secondary
->tess_rings_needed
)
3804 primary
->tess_rings_needed
= true;
3805 if (secondary
->sample_positions_needed
)
3806 primary
->sample_positions_needed
= true;
3808 if (!secondary
->state
.framebuffer
&&
3809 (primary
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)) {
3810 /* Emit the framebuffer state from primary if secondary
3811 * has been recorded without a framebuffer, otherwise
3812 * fast color/depth clears can't work.
3814 radv_emit_framebuffer_state(primary
);
3817 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
3820 /* When the secondary command buffer is compute only we don't
3821 * need to re-emit the current graphics pipeline.
3823 if (secondary
->state
.emitted_pipeline
) {
3824 primary
->state
.emitted_pipeline
=
3825 secondary
->state
.emitted_pipeline
;
3828 /* When the secondary command buffer is graphics only we don't
3829 * need to re-emit the current compute pipeline.
3831 if (secondary
->state
.emitted_compute_pipeline
) {
3832 primary
->state
.emitted_compute_pipeline
=
3833 secondary
->state
.emitted_compute_pipeline
;
3836 /* Only re-emit the draw packets when needed. */
3837 if (secondary
->state
.last_primitive_reset_en
!= -1) {
3838 primary
->state
.last_primitive_reset_en
=
3839 secondary
->state
.last_primitive_reset_en
;
3842 if (secondary
->state
.last_primitive_reset_index
) {
3843 primary
->state
.last_primitive_reset_index
=
3844 secondary
->state
.last_primitive_reset_index
;
3847 if (secondary
->state
.last_ia_multi_vgt_param
) {
3848 primary
->state
.last_ia_multi_vgt_param
=
3849 secondary
->state
.last_ia_multi_vgt_param
;
3852 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
3853 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
3854 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
3856 if (secondary
->state
.last_index_type
!= -1) {
3857 primary
->state
.last_index_type
=
3858 secondary
->state
.last_index_type
;
3862 /* After executing commands from secondary buffers we have to dirty
3865 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
3866 RADV_CMD_DIRTY_INDEX_BUFFER
|
3867 RADV_CMD_DIRTY_DYNAMIC_ALL
;
3868 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
3869 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
3872 VkResult
radv_CreateCommandPool(
3874 const VkCommandPoolCreateInfo
* pCreateInfo
,
3875 const VkAllocationCallbacks
* pAllocator
,
3876 VkCommandPool
* pCmdPool
)
3878 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3879 struct radv_cmd_pool
*pool
;
3881 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
3882 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3884 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3887 pool
->alloc
= *pAllocator
;
3889 pool
->alloc
= device
->alloc
;
3891 list_inithead(&pool
->cmd_buffers
);
3892 list_inithead(&pool
->free_cmd_buffers
);
3894 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
3896 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
3902 void radv_DestroyCommandPool(
3904 VkCommandPool commandPool
,
3905 const VkAllocationCallbacks
* pAllocator
)
3907 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3908 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3913 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3914 &pool
->cmd_buffers
, pool_link
) {
3915 radv_cmd_buffer_destroy(cmd_buffer
);
3918 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3919 &pool
->free_cmd_buffers
, pool_link
) {
3920 radv_cmd_buffer_destroy(cmd_buffer
);
3923 vk_free2(&device
->alloc
, pAllocator
, pool
);
3926 VkResult
radv_ResetCommandPool(
3928 VkCommandPool commandPool
,
3929 VkCommandPoolResetFlags flags
)
3931 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3934 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
3935 &pool
->cmd_buffers
, pool_link
) {
3936 result
= radv_reset_cmd_buffer(cmd_buffer
);
3937 if (result
!= VK_SUCCESS
)
3944 void radv_TrimCommandPool(
3946 VkCommandPool commandPool
,
3947 VkCommandPoolTrimFlags flags
)
3949 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3954 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3955 &pool
->free_cmd_buffers
, pool_link
) {
3956 radv_cmd_buffer_destroy(cmd_buffer
);
3961 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer
*cmd_buffer
,
3962 uint32_t subpass_id
)
3964 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3965 struct radv_subpass
*subpass
= &state
->pass
->subpasses
[subpass_id
];
3967 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
3968 cmd_buffer
->cs
, 4096);
3970 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
3972 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
3974 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3975 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3976 if (a
== VK_ATTACHMENT_UNUSED
)
3979 radv_handle_subpass_image_transition(cmd_buffer
,
3980 subpass
->attachments
[i
],
3984 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3986 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3990 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer
*cmd_buffer
)
3992 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3993 const struct radv_subpass
*subpass
= state
->subpass
;
3994 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
3996 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3998 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3999 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4000 if (a
== VK_ATTACHMENT_UNUSED
)
4003 if (state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4006 VkImageLayout layout
= state
->pass
->attachments
[a
].final_layout
;
4007 struct radv_subpass_attachment att
= { a
, layout
};
4008 radv_handle_subpass_image_transition(cmd_buffer
, att
, false);
4012 void radv_CmdBeginRenderPass(
4013 VkCommandBuffer commandBuffer
,
4014 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4015 VkSubpassContents contents
)
4017 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4018 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4019 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4022 cmd_buffer
->state
.framebuffer
= framebuffer
;
4023 cmd_buffer
->state
.pass
= pass
;
4024 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4026 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
4027 if (result
!= VK_SUCCESS
)
4030 result
= radv_cmd_state_setup_sample_locations(cmd_buffer
, pass
, pRenderPassBegin
);
4031 if (result
!= VK_SUCCESS
)
4034 radv_cmd_buffer_begin_subpass(cmd_buffer
, 0);
4037 void radv_CmdBeginRenderPass2KHR(
4038 VkCommandBuffer commandBuffer
,
4039 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4040 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4042 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
4043 pSubpassBeginInfo
->contents
);
4046 void radv_CmdNextSubpass(
4047 VkCommandBuffer commandBuffer
,
4048 VkSubpassContents contents
)
4050 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4052 uint32_t prev_subpass
= radv_get_subpass_id(cmd_buffer
);
4053 radv_cmd_buffer_end_subpass(cmd_buffer
);
4054 radv_cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4057 void radv_CmdNextSubpass2KHR(
4058 VkCommandBuffer commandBuffer
,
4059 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4060 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4062 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
4065 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
4067 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
4068 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
4069 if (!radv_get_shader(pipeline
, stage
))
4072 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
4073 if (loc
->sgpr_idx
== -1)
4075 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
4076 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4079 if (pipeline
->gs_copy_shader
) {
4080 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
4081 if (loc
->sgpr_idx
!= -1) {
4082 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
4083 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4089 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4090 uint32_t vertex_count
,
4093 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
4094 radeon_emit(cmd_buffer
->cs
, vertex_count
);
4095 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
4096 S_0287F0_USE_OPAQUE(use_opaque
));
4100 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
4102 uint32_t index_count
)
4104 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
4105 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
4106 radeon_emit(cmd_buffer
->cs
, index_va
);
4107 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
4108 radeon_emit(cmd_buffer
->cs
, index_count
);
4109 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
4113 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4115 uint32_t draw_count
,
4119 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4120 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
4121 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
4122 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
;
4123 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
4124 bool predicating
= cmd_buffer
->state
.predicating
;
4127 /* just reset draw state for vertex data */
4128 cmd_buffer
->state
.last_first_instance
= -1;
4129 cmd_buffer
->state
.last_num_instances
= -1;
4130 cmd_buffer
->state
.last_vertex_offset
= -1;
4132 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
4133 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
4134 PKT3_DRAW_INDIRECT
, 3, predicating
));
4136 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4137 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4138 radeon_emit(cs
, di_src_sel
);
4140 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
4141 PKT3_DRAW_INDIRECT_MULTI
,
4144 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4145 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4146 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
4147 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
4148 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
4149 radeon_emit(cs
, draw_count
); /* count */
4150 radeon_emit(cs
, count_va
); /* count_addr */
4151 radeon_emit(cs
, count_va
>> 32);
4152 radeon_emit(cs
, stride
); /* stride */
4153 radeon_emit(cs
, di_src_sel
);
4158 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
4159 const struct radv_draw_info
*info
)
4161 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4162 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4163 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4165 if (info
->indirect
) {
4166 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4167 uint64_t count_va
= 0;
4169 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4171 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4173 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
4175 radeon_emit(cs
, va
);
4176 radeon_emit(cs
, va
>> 32);
4178 if (info
->count_buffer
) {
4179 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
4180 count_va
+= info
->count_buffer
->offset
+
4181 info
->count_buffer_offset
;
4183 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
4186 if (!state
->subpass
->view_mask
) {
4187 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4194 for_each_bit(i
, state
->subpass
->view_mask
) {
4195 radv_emit_view_index(cmd_buffer
, i
);
4197 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4205 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
4207 if (info
->vertex_offset
!= state
->last_vertex_offset
||
4208 info
->first_instance
!= state
->last_first_instance
) {
4209 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
4210 state
->pipeline
->graphics
.vtx_emit_num
);
4212 radeon_emit(cs
, info
->vertex_offset
);
4213 radeon_emit(cs
, info
->first_instance
);
4214 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
4216 state
->last_first_instance
= info
->first_instance
;
4217 state
->last_vertex_offset
= info
->vertex_offset
;
4220 if (state
->last_num_instances
!= info
->instance_count
) {
4221 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
4222 radeon_emit(cs
, info
->instance_count
);
4223 state
->last_num_instances
= info
->instance_count
;
4226 if (info
->indexed
) {
4227 int index_size
= state
->index_type
? 4 : 2;
4230 index_va
= state
->index_va
;
4231 index_va
+= info
->first_index
* index_size
;
4233 if (!state
->subpass
->view_mask
) {
4234 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4239 for_each_bit(i
, state
->subpass
->view_mask
) {
4240 radv_emit_view_index(cmd_buffer
, i
);
4242 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4248 if (!state
->subpass
->view_mask
) {
4249 radv_cs_emit_draw_packet(cmd_buffer
,
4251 !!info
->strmout_buffer
);
4254 for_each_bit(i
, state
->subpass
->view_mask
) {
4255 radv_emit_view_index(cmd_buffer
, i
);
4257 radv_cs_emit_draw_packet(cmd_buffer
,
4259 !!info
->strmout_buffer
);
4267 * Vega and raven have a bug which triggers if there are multiple context
4268 * register contexts active at the same time with different scissor values.
4270 * There are two possible workarounds:
4271 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4272 * there is only ever 1 active set of scissor values at the same time.
4274 * 2) Whenever the hardware switches contexts we have to set the scissor
4275 * registers again even if it is a noop. That way the new context gets
4276 * the correct scissor values.
4278 * This implements option 2. radv_need_late_scissor_emission needs to
4279 * return true on affected HW if radv_emit_all_graphics_states sets
4280 * any context registers.
4282 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
4283 const struct radv_draw_info
*info
)
4285 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4287 if (!cmd_buffer
->device
->physical_device
->has_scissor_bug
)
4290 if (cmd_buffer
->state
.context_roll_without_scissor_emitted
|| info
->strmout_buffer
)
4293 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
4295 /* Index, vertex and streamout buffers don't change context regs, and
4296 * pipeline is already handled.
4298 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
|
4299 RADV_CMD_DIRTY_VERTEX_BUFFER
|
4300 RADV_CMD_DIRTY_STREAMOUT_BUFFER
|
4301 RADV_CMD_DIRTY_PIPELINE
);
4303 if (cmd_buffer
->state
.dirty
& used_states
)
4306 if (info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
&&
4307 (state
->index_type
? 0xffffffffu
: 0xffffu
) != state
->last_primitive_reset_index
)
4314 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
4315 const struct radv_draw_info
*info
)
4317 bool late_scissor_emission
;
4319 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
4320 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
4321 radv_emit_rbplus_state(cmd_buffer
);
4323 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
4324 radv_emit_graphics_pipeline(cmd_buffer
);
4326 /* This should be before the cmd_buffer->state.dirty is cleared
4327 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4328 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4329 late_scissor_emission
=
4330 radv_need_late_scissor_emission(cmd_buffer
, info
);
4332 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
4333 radv_emit_framebuffer_state(cmd_buffer
);
4335 if (info
->indexed
) {
4336 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
4337 radv_emit_index_buffer(cmd_buffer
);
4339 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4340 * so the state must be re-emitted before the next indexed
4343 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4344 cmd_buffer
->state
.last_index_type
= -1;
4345 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
4349 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
4351 radv_emit_draw_registers(cmd_buffer
, info
);
4353 if (late_scissor_emission
)
4354 radv_emit_scissor(cmd_buffer
);
4358 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
4359 const struct radv_draw_info
*info
)
4361 struct radeon_info
*rad_info
=
4362 &cmd_buffer
->device
->physical_device
->rad_info
;
4364 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4365 bool pipeline_is_dirty
=
4366 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
4367 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
4369 MAYBE_UNUSED
unsigned cdw_max
=
4370 radeon_check_space(cmd_buffer
->device
->ws
,
4371 cmd_buffer
->cs
, 4096);
4373 if (likely(!info
->indirect
)) {
4374 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4375 * no workaround for indirect draws, but we can at least skip
4378 if (unlikely(!info
->instance_count
))
4381 /* Handle count == 0. */
4382 if (unlikely(!info
->count
&& !info
->strmout_buffer
))
4386 /* Use optimal packet order based on whether we need to sync the
4389 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4390 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4391 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4392 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4393 /* If we have to wait for idle, set all states first, so that
4394 * all SET packets are processed in parallel with previous draw
4395 * calls. Then upload descriptors, set shader pointers, and
4396 * draw, and prefetch at the end. This ensures that the time
4397 * the CUs are idle is very short. (there are only SET_SH
4398 * packets between the wait and the draw)
4400 radv_emit_all_graphics_states(cmd_buffer
, info
);
4401 si_emit_cache_flush(cmd_buffer
);
4402 /* <-- CUs are idle here --> */
4404 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4406 radv_emit_draw_packets(cmd_buffer
, info
);
4407 /* <-- CUs are busy here --> */
4409 /* Start prefetches after the draw has been started. Both will
4410 * run in parallel, but starting the draw first is more
4413 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4414 radv_emit_prefetch_L2(cmd_buffer
,
4415 cmd_buffer
->state
.pipeline
, false);
4418 /* If we don't wait for idle, start prefetches first, then set
4419 * states, and draw at the end.
4421 si_emit_cache_flush(cmd_buffer
);
4423 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4424 /* Only prefetch the vertex shader and VBO descriptors
4425 * in order to start the draw as soon as possible.
4427 radv_emit_prefetch_L2(cmd_buffer
,
4428 cmd_buffer
->state
.pipeline
, true);
4431 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4433 radv_emit_all_graphics_states(cmd_buffer
, info
);
4434 radv_emit_draw_packets(cmd_buffer
, info
);
4436 /* Prefetch the remaining shaders after the draw has been
4439 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4440 radv_emit_prefetch_L2(cmd_buffer
,
4441 cmd_buffer
->state
.pipeline
, false);
4445 /* Workaround for a VGT hang when streamout is enabled.
4446 * It must be done after drawing.
4448 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
4449 (rad_info
->family
== CHIP_HAWAII
||
4450 rad_info
->family
== CHIP_TONGA
||
4451 rad_info
->family
== CHIP_FIJI
)) {
4452 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
4455 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4456 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
4460 VkCommandBuffer commandBuffer
,
4461 uint32_t vertexCount
,
4462 uint32_t instanceCount
,
4463 uint32_t firstVertex
,
4464 uint32_t firstInstance
)
4466 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4467 struct radv_draw_info info
= {};
4469 info
.count
= vertexCount
;
4470 info
.instance_count
= instanceCount
;
4471 info
.first_instance
= firstInstance
;
4472 info
.vertex_offset
= firstVertex
;
4474 radv_draw(cmd_buffer
, &info
);
4477 void radv_CmdDrawIndexed(
4478 VkCommandBuffer commandBuffer
,
4479 uint32_t indexCount
,
4480 uint32_t instanceCount
,
4481 uint32_t firstIndex
,
4482 int32_t vertexOffset
,
4483 uint32_t firstInstance
)
4485 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4486 struct radv_draw_info info
= {};
4488 info
.indexed
= true;
4489 info
.count
= indexCount
;
4490 info
.instance_count
= instanceCount
;
4491 info
.first_index
= firstIndex
;
4492 info
.vertex_offset
= vertexOffset
;
4493 info
.first_instance
= firstInstance
;
4495 radv_draw(cmd_buffer
, &info
);
4498 void radv_CmdDrawIndirect(
4499 VkCommandBuffer commandBuffer
,
4501 VkDeviceSize offset
,
4505 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4506 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4507 struct radv_draw_info info
= {};
4509 info
.count
= drawCount
;
4510 info
.indirect
= buffer
;
4511 info
.indirect_offset
= offset
;
4512 info
.stride
= stride
;
4514 radv_draw(cmd_buffer
, &info
);
4517 void radv_CmdDrawIndexedIndirect(
4518 VkCommandBuffer commandBuffer
,
4520 VkDeviceSize offset
,
4524 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4525 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4526 struct radv_draw_info info
= {};
4528 info
.indexed
= true;
4529 info
.count
= drawCount
;
4530 info
.indirect
= buffer
;
4531 info
.indirect_offset
= offset
;
4532 info
.stride
= stride
;
4534 radv_draw(cmd_buffer
, &info
);
4537 void radv_CmdDrawIndirectCountKHR(
4538 VkCommandBuffer commandBuffer
,
4540 VkDeviceSize offset
,
4541 VkBuffer _countBuffer
,
4542 VkDeviceSize countBufferOffset
,
4543 uint32_t maxDrawCount
,
4546 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4547 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4548 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4549 struct radv_draw_info info
= {};
4551 info
.count
= maxDrawCount
;
4552 info
.indirect
= buffer
;
4553 info
.indirect_offset
= offset
;
4554 info
.count_buffer
= count_buffer
;
4555 info
.count_buffer_offset
= countBufferOffset
;
4556 info
.stride
= stride
;
4558 radv_draw(cmd_buffer
, &info
);
4561 void radv_CmdDrawIndexedIndirectCountKHR(
4562 VkCommandBuffer commandBuffer
,
4564 VkDeviceSize offset
,
4565 VkBuffer _countBuffer
,
4566 VkDeviceSize countBufferOffset
,
4567 uint32_t maxDrawCount
,
4570 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4571 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4572 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4573 struct radv_draw_info info
= {};
4575 info
.indexed
= true;
4576 info
.count
= maxDrawCount
;
4577 info
.indirect
= buffer
;
4578 info
.indirect_offset
= offset
;
4579 info
.count_buffer
= count_buffer
;
4580 info
.count_buffer_offset
= countBufferOffset
;
4581 info
.stride
= stride
;
4583 radv_draw(cmd_buffer
, &info
);
4586 struct radv_dispatch_info
{
4588 * Determine the layout of the grid (in block units) to be used.
4593 * A starting offset for the grid. If unaligned is set, the offset
4594 * must still be aligned.
4596 uint32_t offsets
[3];
4598 * Whether it's an unaligned compute dispatch.
4603 * Indirect compute parameters resource.
4605 struct radv_buffer
*indirect
;
4606 uint64_t indirect_offset
;
4610 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
4611 const struct radv_dispatch_info
*info
)
4613 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4614 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4615 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
4616 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4617 bool predicating
= cmd_buffer
->state
.predicating
;
4618 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4619 struct radv_userdata_info
*loc
;
4621 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
4622 AC_UD_CS_GRID_SIZE
);
4624 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
4626 if (info
->indirect
) {
4627 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4629 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4631 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4633 if (loc
->sgpr_idx
!= -1) {
4634 for (unsigned i
= 0; i
< 3; ++i
) {
4635 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
4636 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
4637 COPY_DATA_DST_SEL(COPY_DATA_REG
));
4638 radeon_emit(cs
, (va
+ 4 * i
));
4639 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
4640 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
4641 + loc
->sgpr_idx
* 4) >> 2) + i
);
4646 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
4647 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
4648 PKT3_SHADER_TYPE_S(1));
4649 radeon_emit(cs
, va
);
4650 radeon_emit(cs
, va
>> 32);
4651 radeon_emit(cs
, dispatch_initiator
);
4653 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
4654 PKT3_SHADER_TYPE_S(1));
4656 radeon_emit(cs
, va
);
4657 radeon_emit(cs
, va
>> 32);
4659 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
4660 PKT3_SHADER_TYPE_S(1));
4662 radeon_emit(cs
, dispatch_initiator
);
4665 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
4666 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
4668 if (info
->unaligned
) {
4669 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
4670 unsigned remainder
[3];
4672 /* If aligned, these should be an entire block size,
4675 remainder
[0] = blocks
[0] + cs_block_size
[0] -
4676 align_u32_npot(blocks
[0], cs_block_size
[0]);
4677 remainder
[1] = blocks
[1] + cs_block_size
[1] -
4678 align_u32_npot(blocks
[1], cs_block_size
[1]);
4679 remainder
[2] = blocks
[2] + cs_block_size
[2] -
4680 align_u32_npot(blocks
[2], cs_block_size
[2]);
4682 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
4683 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
4684 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
4686 for(unsigned i
= 0; i
< 3; ++i
) {
4687 assert(offsets
[i
] % cs_block_size
[i
] == 0);
4688 offsets
[i
] /= cs_block_size
[i
];
4691 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
4693 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
4694 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
4696 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
4697 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
4699 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
4700 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
4702 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
4705 if (loc
->sgpr_idx
!= -1) {
4706 assert(loc
->num_sgprs
== 3);
4708 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
4709 loc
->sgpr_idx
* 4, 3);
4710 radeon_emit(cs
, blocks
[0]);
4711 radeon_emit(cs
, blocks
[1]);
4712 radeon_emit(cs
, blocks
[2]);
4715 if (offsets
[0] || offsets
[1] || offsets
[2]) {
4716 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
4717 radeon_emit(cs
, offsets
[0]);
4718 radeon_emit(cs
, offsets
[1]);
4719 radeon_emit(cs
, offsets
[2]);
4721 /* The blocks in the packet are not counts but end values. */
4722 for (unsigned i
= 0; i
< 3; ++i
)
4723 blocks
[i
] += offsets
[i
];
4725 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
4728 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
4729 PKT3_SHADER_TYPE_S(1));
4730 radeon_emit(cs
, blocks
[0]);
4731 radeon_emit(cs
, blocks
[1]);
4732 radeon_emit(cs
, blocks
[2]);
4733 radeon_emit(cs
, dispatch_initiator
);
4736 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4740 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
4742 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4743 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4747 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
4748 const struct radv_dispatch_info
*info
)
4750 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4752 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4753 bool pipeline_is_dirty
= pipeline
&&
4754 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
4756 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4757 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4758 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4759 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4760 /* If we have to wait for idle, set all states first, so that
4761 * all SET packets are processed in parallel with previous draw
4762 * calls. Then upload descriptors, set shader pointers, and
4763 * dispatch, and prefetch at the end. This ensures that the
4764 * time the CUs are idle is very short. (there are only SET_SH
4765 * packets between the wait and the draw)
4767 radv_emit_compute_pipeline(cmd_buffer
);
4768 si_emit_cache_flush(cmd_buffer
);
4769 /* <-- CUs are idle here --> */
4771 radv_upload_compute_shader_descriptors(cmd_buffer
);
4773 radv_emit_dispatch_packets(cmd_buffer
, info
);
4774 /* <-- CUs are busy here --> */
4776 /* Start prefetches after the dispatch has been started. Both
4777 * will run in parallel, but starting the dispatch first is
4780 if (has_prefetch
&& pipeline_is_dirty
) {
4781 radv_emit_shader_prefetch(cmd_buffer
,
4782 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4785 /* If we don't wait for idle, start prefetches first, then set
4786 * states, and dispatch at the end.
4788 si_emit_cache_flush(cmd_buffer
);
4790 if (has_prefetch
&& pipeline_is_dirty
) {
4791 radv_emit_shader_prefetch(cmd_buffer
,
4792 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4795 radv_upload_compute_shader_descriptors(cmd_buffer
);
4797 radv_emit_compute_pipeline(cmd_buffer
);
4798 radv_emit_dispatch_packets(cmd_buffer
, info
);
4801 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
4804 void radv_CmdDispatchBase(
4805 VkCommandBuffer commandBuffer
,
4813 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4814 struct radv_dispatch_info info
= {};
4820 info
.offsets
[0] = base_x
;
4821 info
.offsets
[1] = base_y
;
4822 info
.offsets
[2] = base_z
;
4823 radv_dispatch(cmd_buffer
, &info
);
4826 void radv_CmdDispatch(
4827 VkCommandBuffer commandBuffer
,
4832 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
4835 void radv_CmdDispatchIndirect(
4836 VkCommandBuffer commandBuffer
,
4838 VkDeviceSize offset
)
4840 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4841 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4842 struct radv_dispatch_info info
= {};
4844 info
.indirect
= buffer
;
4845 info
.indirect_offset
= offset
;
4847 radv_dispatch(cmd_buffer
, &info
);
4850 void radv_unaligned_dispatch(
4851 struct radv_cmd_buffer
*cmd_buffer
,
4856 struct radv_dispatch_info info
= {};
4863 radv_dispatch(cmd_buffer
, &info
);
4866 void radv_CmdEndRenderPass(
4867 VkCommandBuffer commandBuffer
)
4869 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4871 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
4873 radv_cmd_buffer_end_subpass(cmd_buffer
);
4875 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
4876 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
4878 cmd_buffer
->state
.pass
= NULL
;
4879 cmd_buffer
->state
.subpass
= NULL
;
4880 cmd_buffer
->state
.attachments
= NULL
;
4881 cmd_buffer
->state
.framebuffer
= NULL
;
4882 cmd_buffer
->state
.subpass_sample_locs
= NULL
;
4885 void radv_CmdEndRenderPass2KHR(
4886 VkCommandBuffer commandBuffer
,
4887 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4889 radv_CmdEndRenderPass(commandBuffer
);
4893 * For HTILE we have the following interesting clear words:
4894 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4895 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4896 * 0xfffffff0: Clear depth to 1.0
4897 * 0x00000000: Clear depth to 0.0
4899 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
4900 struct radv_image
*image
,
4901 const VkImageSubresourceRange
*range
,
4902 uint32_t clear_word
)
4904 assert(range
->baseMipLevel
== 0);
4905 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
4906 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4907 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4908 VkClearDepthStencilValue value
= {};
4910 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4911 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4913 state
->flush_bits
|= radv_clear_htile(cmd_buffer
, image
, range
, clear_word
);
4915 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4917 if (vk_format_is_stencil(image
->vk_format
))
4918 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
4920 radv_set_ds_clear_metadata(cmd_buffer
, image
, value
, aspects
);
4922 if (radv_image_is_tc_compat_htile(image
)) {
4923 /* Initialize the TC-compat metada value to 0 because by
4924 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4925 * need have to conditionally update its value when performing
4926 * a fast depth clear.
4928 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, 0);
4932 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4933 struct radv_image
*image
,
4934 VkImageLayout src_layout
,
4935 VkImageLayout dst_layout
,
4936 unsigned src_queue_mask
,
4937 unsigned dst_queue_mask
,
4938 const VkImageSubresourceRange
*range
,
4939 struct radv_sample_locations_state
*sample_locs
)
4941 if (!radv_image_has_htile(image
))
4944 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
4945 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
4947 if (radv_layout_is_htile_compressed(image
, dst_layout
,
4952 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
4953 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4954 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4955 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
4956 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
4957 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4958 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4959 VkImageSubresourceRange local_range
= *range
;
4960 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4961 local_range
.baseMipLevel
= 0;
4962 local_range
.levelCount
= 1;
4964 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4965 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4967 radv_decompress_depth_image_inplace(cmd_buffer
, image
,
4968 &local_range
, sample_locs
);
4970 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4971 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4975 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
4976 struct radv_image
*image
,
4977 const VkImageSubresourceRange
*range
,
4980 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4982 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4983 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4985 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, range
, value
);
4987 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4990 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
4991 struct radv_image
*image
,
4992 const VkImageSubresourceRange
*range
)
4994 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4995 static const uint32_t fmask_clear_values
[4] = {
5001 uint32_t log2_samples
= util_logbase2(image
->info
.samples
);
5002 uint32_t value
= fmask_clear_values
[log2_samples
];
5004 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5005 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5007 state
->flush_bits
|= radv_clear_fmask(cmd_buffer
, image
, range
, value
);
5009 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5012 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
5013 struct radv_image
*image
,
5014 const VkImageSubresourceRange
*range
, uint32_t value
)
5016 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5019 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5020 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5022 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, range
, value
);
5024 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX8
) {
5025 /* When DCC is enabled with mipmaps, some levels might not
5026 * support fast clears and we have to initialize them as "fully
5029 /* Compute the size of all fast clearable DCC levels. */
5030 for (unsigned i
= 0; i
< image
->planes
[0].surface
.num_dcc_levels
; i
++) {
5031 struct legacy_surf_level
*surf_level
=
5032 &image
->planes
[0].surface
.u
.legacy
.level
[i
];
5033 unsigned dcc_fast_clear_size
=
5034 surf_level
->dcc_slice_fast_clear_size
* image
->info
.array_size
;
5036 if (!dcc_fast_clear_size
)
5039 size
= surf_level
->dcc_offset
+ dcc_fast_clear_size
;
5042 /* Initialize the mipmap levels without DCC. */
5043 if (size
!= image
->planes
[0].surface
.dcc_size
) {
5044 state
->flush_bits
|=
5045 radv_fill_buffer(cmd_buffer
, image
->bo
,
5046 image
->offset
+ image
->dcc_offset
+ size
,
5047 image
->planes
[0].surface
.dcc_size
- size
,
5052 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5053 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5057 * Initialize DCC/FMASK/CMASK metadata for a color image.
5059 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
5060 struct radv_image
*image
,
5061 VkImageLayout src_layout
,
5062 VkImageLayout dst_layout
,
5063 unsigned src_queue_mask
,
5064 unsigned dst_queue_mask
,
5065 const VkImageSubresourceRange
*range
)
5067 if (radv_image_has_cmask(image
)) {
5068 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5070 /* TODO: clarify this. */
5071 if (radv_image_has_fmask(image
)) {
5072 value
= 0xccccccccu
;
5075 radv_initialise_cmask(cmd_buffer
, image
, range
, value
);
5078 if (radv_image_has_fmask(image
)) {
5079 radv_initialize_fmask(cmd_buffer
, image
, range
);
5082 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5083 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5084 bool need_decompress_pass
= false;
5086 if (radv_layout_dcc_compressed(image
, dst_layout
,
5088 value
= 0x20202020u
;
5089 need_decompress_pass
= true;
5092 radv_initialize_dcc(cmd_buffer
, image
, range
, value
);
5094 radv_update_fce_metadata(cmd_buffer
, image
, range
,
5095 need_decompress_pass
);
5098 if (radv_image_has_cmask(image
) ||
5099 radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5100 uint32_t color_values
[2] = {};
5101 radv_set_color_clear_metadata(cmd_buffer
, image
, range
,
5107 * Handle color image transitions for DCC/FMASK/CMASK.
5109 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5110 struct radv_image
*image
,
5111 VkImageLayout src_layout
,
5112 VkImageLayout dst_layout
,
5113 unsigned src_queue_mask
,
5114 unsigned dst_queue_mask
,
5115 const VkImageSubresourceRange
*range
)
5117 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5118 radv_init_color_image_metadata(cmd_buffer
, image
,
5119 src_layout
, dst_layout
,
5120 src_queue_mask
, dst_queue_mask
,
5125 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5126 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
5127 radv_initialize_dcc(cmd_buffer
, image
, range
, 0xffffffffu
);
5128 } else if (radv_layout_dcc_compressed(image
, src_layout
, src_queue_mask
) &&
5129 !radv_layout_dcc_compressed(image
, dst_layout
, dst_queue_mask
)) {
5130 radv_decompress_dcc(cmd_buffer
, image
, range
);
5131 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
5132 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
5133 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5135 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
5136 bool fce_eliminate
= false, fmask_expand
= false;
5138 if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
5139 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
5140 fce_eliminate
= true;
5143 if (radv_image_has_fmask(image
)) {
5144 if (src_layout
!= VK_IMAGE_LAYOUT_GENERAL
&&
5145 dst_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5146 /* A FMASK decompress is required before doing
5147 * a MSAA decompress using FMASK.
5149 fmask_expand
= true;
5153 if (fce_eliminate
|| fmask_expand
)
5154 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
5157 radv_expand_fmask_image_inplace(cmd_buffer
, image
, range
);
5161 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5162 struct radv_image
*image
,
5163 VkImageLayout src_layout
,
5164 VkImageLayout dst_layout
,
5165 uint32_t src_family
,
5166 uint32_t dst_family
,
5167 const VkImageSubresourceRange
*range
,
5168 struct radv_sample_locations_state
*sample_locs
)
5170 if (image
->exclusive
&& src_family
!= dst_family
) {
5171 /* This is an acquire or a release operation and there will be
5172 * a corresponding release/acquire. Do the transition in the
5173 * most flexible queue. */
5175 assert(src_family
== cmd_buffer
->queue_family_index
||
5176 dst_family
== cmd_buffer
->queue_family_index
);
5178 if (src_family
== VK_QUEUE_FAMILY_EXTERNAL
||
5179 src_family
== VK_QUEUE_FAMILY_FOREIGN_EXT
)
5182 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
5185 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
5186 (src_family
== RADV_QUEUE_GENERAL
||
5187 dst_family
== RADV_QUEUE_GENERAL
))
5191 if (src_layout
== dst_layout
)
5194 unsigned src_queue_mask
=
5195 radv_image_queue_family_mask(image
, src_family
,
5196 cmd_buffer
->queue_family_index
);
5197 unsigned dst_queue_mask
=
5198 radv_image_queue_family_mask(image
, dst_family
,
5199 cmd_buffer
->queue_family_index
);
5201 if (vk_format_is_depth(image
->vk_format
)) {
5202 radv_handle_depth_image_transition(cmd_buffer
, image
,
5203 src_layout
, dst_layout
,
5204 src_queue_mask
, dst_queue_mask
,
5205 range
, sample_locs
);
5207 radv_handle_color_image_transition(cmd_buffer
, image
,
5208 src_layout
, dst_layout
,
5209 src_queue_mask
, dst_queue_mask
,
5214 struct radv_barrier_info
{
5215 uint32_t eventCount
;
5216 const VkEvent
*pEvents
;
5217 VkPipelineStageFlags srcStageMask
;
5218 VkPipelineStageFlags dstStageMask
;
5222 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
5223 uint32_t memoryBarrierCount
,
5224 const VkMemoryBarrier
*pMemoryBarriers
,
5225 uint32_t bufferMemoryBarrierCount
,
5226 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
5227 uint32_t imageMemoryBarrierCount
,
5228 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
5229 const struct radv_barrier_info
*info
)
5231 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5232 enum radv_cmd_flush_bits src_flush_bits
= 0;
5233 enum radv_cmd_flush_bits dst_flush_bits
= 0;
5235 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
5236 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
5237 uint64_t va
= radv_buffer_get_va(event
->bo
);
5239 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5241 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
5243 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
5244 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5247 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
5248 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
5250 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
5254 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
5255 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
5257 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
5261 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5262 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5264 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
5266 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
5270 /* The Vulkan spec 1.1.98 says:
5272 * "An execution dependency with only
5273 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5274 * will only prevent that stage from executing in subsequently
5275 * submitted commands. As this stage does not perform any actual
5276 * execution, this is not observable - in effect, it does not delay
5277 * processing of subsequent commands. Similarly an execution dependency
5278 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5279 * will effectively not wait for any prior commands to complete."
5281 if (info
->dstStageMask
!= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
)
5282 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
5283 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
5285 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5286 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5288 const struct VkSampleLocationsInfoEXT
*sample_locs_info
=
5289 vk_find_struct_const(pImageMemoryBarriers
[i
].pNext
,
5290 SAMPLE_LOCATIONS_INFO_EXT
);
5291 struct radv_sample_locations_state sample_locations
= {};
5293 if (sample_locs_info
) {
5294 assert(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
);
5295 sample_locations
.per_pixel
= sample_locs_info
->sampleLocationsPerPixel
;
5296 sample_locations
.grid_size
= sample_locs_info
->sampleLocationGridSize
;
5297 sample_locations
.count
= sample_locs_info
->sampleLocationsCount
;
5298 typed_memcpy(&sample_locations
.locations
[0],
5299 sample_locs_info
->pSampleLocations
,
5300 sample_locs_info
->sampleLocationsCount
);
5303 radv_handle_image_transition(cmd_buffer
, image
,
5304 pImageMemoryBarriers
[i
].oldLayout
,
5305 pImageMemoryBarriers
[i
].newLayout
,
5306 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
5307 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
5308 &pImageMemoryBarriers
[i
].subresourceRange
,
5309 sample_locs_info
? &sample_locations
: NULL
);
5312 /* Make sure CP DMA is idle because the driver might have performed a
5313 * DMA operation for copying or filling buffers/images.
5315 if (info
->srcStageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5316 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5317 si_cp_dma_wait_for_idle(cmd_buffer
);
5319 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
5322 void radv_CmdPipelineBarrier(
5323 VkCommandBuffer commandBuffer
,
5324 VkPipelineStageFlags srcStageMask
,
5325 VkPipelineStageFlags destStageMask
,
5327 uint32_t memoryBarrierCount
,
5328 const VkMemoryBarrier
* pMemoryBarriers
,
5329 uint32_t bufferMemoryBarrierCount
,
5330 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5331 uint32_t imageMemoryBarrierCount
,
5332 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5334 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5335 struct radv_barrier_info info
;
5337 info
.eventCount
= 0;
5338 info
.pEvents
= NULL
;
5339 info
.srcStageMask
= srcStageMask
;
5340 info
.dstStageMask
= destStageMask
;
5342 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5343 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5344 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5348 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
5349 struct radv_event
*event
,
5350 VkPipelineStageFlags stageMask
,
5353 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5354 uint64_t va
= radv_buffer_get_va(event
->bo
);
5356 si_emit_cache_flush(cmd_buffer
);
5358 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5360 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 21);
5362 /* Flags that only require a top-of-pipe event. */
5363 VkPipelineStageFlags top_of_pipe_flags
=
5364 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
5366 /* Flags that only require a post-index-fetch event. */
5367 VkPipelineStageFlags post_index_fetch_flags
=
5369 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
5370 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
5372 /* Make sure CP DMA is idle because the driver might have performed a
5373 * DMA operation for copying or filling buffers/images.
5375 if (stageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5376 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5377 si_cp_dma_wait_for_idle(cmd_buffer
);
5379 /* TODO: Emit EOS events for syncing PS/CS stages. */
5381 if (!(stageMask
& ~top_of_pipe_flags
)) {
5382 /* Just need to sync the PFP engine. */
5383 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5384 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5385 S_370_WR_CONFIRM(1) |
5386 S_370_ENGINE_SEL(V_370_PFP
));
5387 radeon_emit(cs
, va
);
5388 radeon_emit(cs
, va
>> 32);
5389 radeon_emit(cs
, value
);
5390 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
5391 /* Sync ME because PFP reads index and indirect buffers. */
5392 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5393 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5394 S_370_WR_CONFIRM(1) |
5395 S_370_ENGINE_SEL(V_370_ME
));
5396 radeon_emit(cs
, va
);
5397 radeon_emit(cs
, va
>> 32);
5398 radeon_emit(cs
, value
);
5400 /* Otherwise, sync all prior GPU work using an EOP event. */
5401 si_cs_emit_write_event_eop(cs
,
5402 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
5403 radv_cmd_buffer_uses_mec(cmd_buffer
),
5404 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
5405 EOP_DATA_SEL_VALUE_32BIT
, va
, value
,
5406 cmd_buffer
->gfx9_eop_bug_va
);
5409 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5412 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
5414 VkPipelineStageFlags stageMask
)
5416 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5417 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5419 write_event(cmd_buffer
, event
, stageMask
, 1);
5422 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
5424 VkPipelineStageFlags stageMask
)
5426 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5427 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5429 write_event(cmd_buffer
, event
, stageMask
, 0);
5432 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
5433 uint32_t eventCount
,
5434 const VkEvent
* pEvents
,
5435 VkPipelineStageFlags srcStageMask
,
5436 VkPipelineStageFlags dstStageMask
,
5437 uint32_t memoryBarrierCount
,
5438 const VkMemoryBarrier
* pMemoryBarriers
,
5439 uint32_t bufferMemoryBarrierCount
,
5440 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5441 uint32_t imageMemoryBarrierCount
,
5442 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5444 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5445 struct radv_barrier_info info
;
5447 info
.eventCount
= eventCount
;
5448 info
.pEvents
= pEvents
;
5449 info
.srcStageMask
= 0;
5451 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5452 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5453 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5457 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
5458 uint32_t deviceMask
)
5463 /* VK_EXT_conditional_rendering */
5464 void radv_CmdBeginConditionalRenderingEXT(
5465 VkCommandBuffer commandBuffer
,
5466 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5468 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5469 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5470 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5471 bool draw_visible
= true;
5472 uint64_t pred_value
= 0;
5473 uint64_t va
, new_va
;
5474 unsigned pred_offset
;
5476 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
5478 /* By default, if the 32-bit value at offset in buffer memory is zero,
5479 * then the rendering commands are discarded, otherwise they are
5480 * executed as normal. If the inverted flag is set, all commands are
5481 * discarded if the value is non zero.
5483 if (pConditionalRenderingBegin
->flags
&
5484 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
5485 draw_visible
= false;
5488 si_emit_cache_flush(cmd_buffer
);
5490 /* From the Vulkan spec 1.1.107:
5492 * "If the 32-bit value at offset in buffer memory is zero, then the
5493 * rendering commands are discarded, otherwise they are executed as
5494 * normal. If the value of the predicate in buffer memory changes while
5495 * conditional rendering is active, the rendering commands may be
5496 * discarded in an implementation-dependent way. Some implementations
5497 * may latch the value of the predicate upon beginning conditional
5498 * rendering while others may read it before every rendering command."
5500 * But, the AMD hardware treats the predicate as a 64-bit value which
5501 * means we need a workaround in the driver. Luckily, it's not required
5502 * to support if the value changes when predication is active.
5504 * The workaround is as follows:
5505 * 1) allocate a 64-value in the upload BO and initialize it to 0
5506 * 2) copy the 32-bit predicate value to the upload BO
5507 * 3) use the new allocated VA address for predication
5509 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5510 * in ME (+ sync PFP) instead of PFP.
5512 radv_cmd_buffer_upload_data(cmd_buffer
, 8, 16, &pred_value
, &pred_offset
);
5514 new_va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
) + pred_offset
;
5516 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5517 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
5518 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
5519 COPY_DATA_WR_CONFIRM
);
5520 radeon_emit(cs
, va
);
5521 radeon_emit(cs
, va
>> 32);
5522 radeon_emit(cs
, new_va
);
5523 radeon_emit(cs
, new_va
>> 32);
5525 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
5528 /* Enable predication for this command buffer. */
5529 si_emit_set_predication_state(cmd_buffer
, draw_visible
, new_va
);
5530 cmd_buffer
->state
.predicating
= true;
5532 /* Store conditional rendering user info. */
5533 cmd_buffer
->state
.predication_type
= draw_visible
;
5534 cmd_buffer
->state
.predication_va
= new_va
;
5537 void radv_CmdEndConditionalRenderingEXT(
5538 VkCommandBuffer commandBuffer
)
5540 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5542 /* Disable predication for this command buffer. */
5543 si_emit_set_predication_state(cmd_buffer
, false, 0);
5544 cmd_buffer
->state
.predicating
= false;
5546 /* Reset conditional rendering user info. */
5547 cmd_buffer
->state
.predication_type
= -1;
5548 cmd_buffer
->state
.predication_va
= 0;
5551 /* VK_EXT_transform_feedback */
5552 void radv_CmdBindTransformFeedbackBuffersEXT(
5553 VkCommandBuffer commandBuffer
,
5554 uint32_t firstBinding
,
5555 uint32_t bindingCount
,
5556 const VkBuffer
* pBuffers
,
5557 const VkDeviceSize
* pOffsets
,
5558 const VkDeviceSize
* pSizes
)
5560 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5561 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5562 uint8_t enabled_mask
= 0;
5564 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
5565 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
5566 uint32_t idx
= firstBinding
+ i
;
5568 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
5569 sb
[idx
].offset
= pOffsets
[i
];
5570 sb
[idx
].size
= pSizes
[i
];
5572 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
5573 sb
[idx
].buffer
->bo
);
5575 enabled_mask
|= 1 << idx
;
5578 cmd_buffer
->state
.streamout
.enabled_mask
|= enabled_mask
;
5580 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
5584 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
5586 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5587 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5589 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
5591 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
5592 S_028B94_RAST_STREAM(0) |
5593 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
5594 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
5595 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
5596 radeon_emit(cs
, so
->hw_enabled_mask
&
5597 so
->enabled_stream_buffers_mask
);
5599 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5603 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
5605 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5606 bool old_streamout_enabled
= so
->streamout_enabled
;
5607 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
5609 so
->streamout_enabled
= enable
;
5611 so
->hw_enabled_mask
= so
->enabled_mask
|
5612 (so
->enabled_mask
<< 4) |
5613 (so
->enabled_mask
<< 8) |
5614 (so
->enabled_mask
<< 12);
5616 if ((old_streamout_enabled
!= so
->streamout_enabled
) ||
5617 (old_hw_enabled_mask
!= so
->hw_enabled_mask
))
5618 radv_emit_streamout_enable(cmd_buffer
);
5621 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
5623 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5624 unsigned reg_strmout_cntl
;
5626 /* The register is at different places on different ASICs. */
5627 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
5628 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
5629 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
5631 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
5632 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
5635 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
5636 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
5638 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
5639 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
5640 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
5642 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5643 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5644 radeon_emit(cs
, 4); /* poll interval */
5647 void radv_CmdBeginTransformFeedbackEXT(
5648 VkCommandBuffer commandBuffer
,
5649 uint32_t firstCounterBuffer
,
5650 uint32_t counterBufferCount
,
5651 const VkBuffer
* pCounterBuffers
,
5652 const VkDeviceSize
* pCounterBufferOffsets
)
5654 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5655 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5656 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5657 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5660 radv_flush_vgt_streamout(cmd_buffer
);
5662 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5663 for_each_bit(i
, so
->enabled_mask
) {
5664 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5665 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5666 counter_buffer_idx
= -1;
5668 /* AMD GCN binds streamout buffers as shader resources.
5669 * VGT only counts primitives and tells the shader through
5672 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
5673 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
5674 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
5676 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5678 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
5679 /* The array of counter buffers is optional. */
5680 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5681 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
5683 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5686 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5687 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5688 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5689 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
5690 radeon_emit(cs
, 0); /* unused */
5691 radeon_emit(cs
, 0); /* unused */
5692 radeon_emit(cs
, va
); /* src address lo */
5693 radeon_emit(cs
, va
>> 32); /* src address hi */
5695 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5697 /* Start from the beginning. */
5698 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5699 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5700 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5701 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
5702 radeon_emit(cs
, 0); /* unused */
5703 radeon_emit(cs
, 0); /* unused */
5704 radeon_emit(cs
, 0); /* unused */
5705 radeon_emit(cs
, 0); /* unused */
5709 radv_set_streamout_enable(cmd_buffer
, true);
5712 void radv_CmdEndTransformFeedbackEXT(
5713 VkCommandBuffer commandBuffer
,
5714 uint32_t firstCounterBuffer
,
5715 uint32_t counterBufferCount
,
5716 const VkBuffer
* pCounterBuffers
,
5717 const VkDeviceSize
* pCounterBufferOffsets
)
5719 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5720 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5721 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5724 radv_flush_vgt_streamout(cmd_buffer
);
5726 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5727 for_each_bit(i
, so
->enabled_mask
) {
5728 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5729 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5730 counter_buffer_idx
= -1;
5732 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
5733 /* The array of counters buffer is optional. */
5734 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5735 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
5737 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5739 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5740 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5741 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5742 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
5743 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
5744 radeon_emit(cs
, va
); /* dst address lo */
5745 radeon_emit(cs
, va
>> 32); /* dst address hi */
5746 radeon_emit(cs
, 0); /* unused */
5747 radeon_emit(cs
, 0); /* unused */
5749 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5752 /* Deactivate transform feedback by zeroing the buffer size.
5753 * The counters (primitives generated, primitives emitted) may
5754 * be enabled even if there is not buffer bound. This ensures
5755 * that the primitives-emitted query won't increment.
5757 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
5759 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5762 radv_set_streamout_enable(cmd_buffer
, false);
5765 void radv_CmdDrawIndirectByteCountEXT(
5766 VkCommandBuffer commandBuffer
,
5767 uint32_t instanceCount
,
5768 uint32_t firstInstance
,
5769 VkBuffer _counterBuffer
,
5770 VkDeviceSize counterBufferOffset
,
5771 uint32_t counterOffset
,
5772 uint32_t vertexStride
)
5774 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5775 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
5776 struct radv_draw_info info
= {};
5778 info
.instance_count
= instanceCount
;
5779 info
.first_instance
= firstInstance
;
5780 info
.strmout_buffer
= counterBuffer
;
5781 info
.strmout_buffer_offset
= counterBufferOffset
;
5782 info
.stride
= vertexStride
;
5784 radv_draw(cmd_buffer
, &info
);
5787 /* VK_AMD_buffer_marker */
5788 void radv_CmdWriteBufferMarkerAMD(
5789 VkCommandBuffer commandBuffer
,
5790 VkPipelineStageFlagBits pipelineStage
,
5792 VkDeviceSize dstOffset
,
5795 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5796 RADV_FROM_HANDLE(radv_buffer
, buffer
, dstBuffer
);
5797 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5798 uint64_t va
= radv_buffer_get_va(buffer
->bo
) + dstOffset
;
5800 si_emit_cache_flush(cmd_buffer
);
5802 if (!(pipelineStage
& ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
)) {
5803 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5804 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_IMM
) |
5805 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
5806 COPY_DATA_WR_CONFIRM
);
5807 radeon_emit(cs
, marker
);
5809 radeon_emit(cs
, va
);
5810 radeon_emit(cs
, va
>> 32);
5812 si_cs_emit_write_event_eop(cs
,
5813 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
5814 radv_cmd_buffer_uses_mec(cmd_buffer
),
5815 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
5816 EOP_DATA_SEL_VALUE_32BIT
,
5818 cmd_buffer
->gfx9_eop_bug_va
);