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radv: propagate VK_ERROR_OUT_OF_HOST_MEMORY to vk{Begin,End}CommandBuffer()
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "gfx9d.h"
33 #include "vk_format.h"
34 #include "radv_meta.h"
35
36 #include "ac_debug.h"
37
38 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
39 struct radv_image *image,
40 VkImageLayout src_layout,
41 VkImageLayout dst_layout,
42 uint32_t src_family,
43 uint32_t dst_family,
44 const VkImageSubresourceRange *range,
45 VkImageAspectFlags pending_clears);
46
47 const struct radv_dynamic_state default_dynamic_state = {
48 .viewport = {
49 .count = 0,
50 },
51 .scissor = {
52 .count = 0,
53 },
54 .line_width = 1.0f,
55 .depth_bias = {
56 .bias = 0.0f,
57 .clamp = 0.0f,
58 .slope = 0.0f,
59 },
60 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
61 .depth_bounds = {
62 .min = 0.0f,
63 .max = 1.0f,
64 },
65 .stencil_compare_mask = {
66 .front = ~0u,
67 .back = ~0u,
68 },
69 .stencil_write_mask = {
70 .front = ~0u,
71 .back = ~0u,
72 },
73 .stencil_reference = {
74 .front = 0u,
75 .back = 0u,
76 },
77 };
78
79 void
80 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
81 const struct radv_dynamic_state *src,
82 uint32_t copy_mask)
83 {
84 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
85 dest->viewport.count = src->viewport.count;
86 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
87 src->viewport.count);
88 }
89
90 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
91 dest->scissor.count = src->scissor.count;
92 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
93 src->scissor.count);
94 }
95
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
97 dest->line_width = src->line_width;
98
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
100 dest->depth_bias = src->depth_bias;
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
103 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
106 dest->depth_bounds = src->depth_bounds;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
109 dest->stencil_compare_mask = src->stencil_compare_mask;
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
112 dest->stencil_write_mask = src->stencil_write_mask;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
115 dest->stencil_reference = src->stencil_reference;
116 }
117
118 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
119 {
120 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
121 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
122 }
123
124 enum ring_type radv_queue_family_to_ring(int f) {
125 switch (f) {
126 case RADV_QUEUE_GENERAL:
127 return RING_GFX;
128 case RADV_QUEUE_COMPUTE:
129 return RING_COMPUTE;
130 case RADV_QUEUE_TRANSFER:
131 return RING_DMA;
132 default:
133 unreachable("Unknown queue family");
134 }
135 }
136
137 static VkResult radv_create_cmd_buffer(
138 struct radv_device * device,
139 struct radv_cmd_pool * pool,
140 VkCommandBufferLevel level,
141 VkCommandBuffer* pCommandBuffer)
142 {
143 struct radv_cmd_buffer *cmd_buffer;
144 VkResult result;
145 unsigned ring;
146 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
147 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
148 if (cmd_buffer == NULL)
149 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
150
151 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
152 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
153 cmd_buffer->device = device;
154 cmd_buffer->pool = pool;
155 cmd_buffer->level = level;
156
157 if (pool) {
158 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
159 cmd_buffer->queue_family_index = pool->queue_family_index;
160
161 } else {
162 /* Init the pool_link so we can safefly call list_del when we destroy
163 * the command buffer
164 */
165 list_inithead(&cmd_buffer->pool_link);
166 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
167 }
168
169 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
170
171 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
172 if (!cmd_buffer->cs) {
173 result = VK_ERROR_OUT_OF_HOST_MEMORY;
174 goto fail;
175 }
176
177 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
178
179 cmd_buffer->upload.offset = 0;
180 cmd_buffer->upload.size = 0;
181 list_inithead(&cmd_buffer->upload.list);
182
183 return VK_SUCCESS;
184
185 fail:
186 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
187
188 return result;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
211 {
212
213 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
214
215 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
216 &cmd_buffer->upload.list, list) {
217 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
218 list_del(&up->list);
219 free(up);
220 }
221
222 cmd_buffer->scratch_size_needed = 0;
223 cmd_buffer->compute_scratch_size_needed = 0;
224 cmd_buffer->esgs_ring_size_needed = 0;
225 cmd_buffer->gsvs_ring_size_needed = 0;
226 cmd_buffer->tess_rings_needed = false;
227 cmd_buffer->sample_positions_needed = false;
228
229 if (cmd_buffer->upload.upload_bo)
230 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
231 cmd_buffer->upload.upload_bo, 8);
232 cmd_buffer->upload.offset = 0;
233
234 cmd_buffer->record_result = VK_SUCCESS;
235
236 cmd_buffer->ring_offsets_idx = -1;
237
238 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
239 void *fence_ptr;
240 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
241 &cmd_buffer->gfx9_fence_offset,
242 &fence_ptr);
243 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
244 }
245 }
246
247 static bool
248 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
249 uint64_t min_needed)
250 {
251 uint64_t new_size;
252 struct radeon_winsys_bo *bo;
253 struct radv_cmd_buffer_upload *upload;
254 struct radv_device *device = cmd_buffer->device;
255
256 new_size = MAX2(min_needed, 16 * 1024);
257 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
258
259 bo = device->ws->buffer_create(device->ws,
260 new_size, 4096,
261 RADEON_DOMAIN_GTT,
262 RADEON_FLAG_CPU_ACCESS);
263
264 if (!bo) {
265 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
266 return false;
267 }
268
269 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
270 if (cmd_buffer->upload.upload_bo) {
271 upload = malloc(sizeof(*upload));
272
273 if (!upload) {
274 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
275 device->ws->buffer_destroy(bo);
276 return false;
277 }
278
279 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
280 list_add(&upload->list, &cmd_buffer->upload.list);
281 }
282
283 cmd_buffer->upload.upload_bo = bo;
284 cmd_buffer->upload.size = new_size;
285 cmd_buffer->upload.offset = 0;
286 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
287
288 if (!cmd_buffer->upload.map) {
289 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
290 return false;
291 }
292
293 return true;
294 }
295
296 bool
297 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
298 unsigned size,
299 unsigned alignment,
300 unsigned *out_offset,
301 void **ptr)
302 {
303 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
304 if (offset + size > cmd_buffer->upload.size) {
305 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
306 return false;
307 offset = 0;
308 }
309
310 *out_offset = offset;
311 *ptr = cmd_buffer->upload.map + offset;
312
313 cmd_buffer->upload.offset = offset + size;
314 return true;
315 }
316
317 bool
318 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
319 unsigned size, unsigned alignment,
320 const void *data, unsigned *out_offset)
321 {
322 uint8_t *ptr;
323
324 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
325 out_offset, (void **)&ptr))
326 return false;
327
328 if (ptr)
329 memcpy(ptr, data, size);
330
331 return true;
332 }
333
334 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
335 {
336 struct radv_device *device = cmd_buffer->device;
337 struct radeon_winsys_cs *cs = cmd_buffer->cs;
338 uint64_t va;
339
340 if (!device->trace_bo)
341 return;
342
343 va = device->ws->buffer_get_va(device->trace_bo);
344
345 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
346
347 ++cmd_buffer->state.trace_id;
348 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
349 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
350 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
351 S_370_WR_CONFIRM(1) |
352 S_370_ENGINE_SEL(V_370_ME));
353 radeon_emit(cs, va);
354 radeon_emit(cs, va >> 32);
355 radeon_emit(cs, cmd_buffer->state.trace_id);
356 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
357 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
358 }
359
360 static void
361 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
362 struct radv_pipeline *pipeline)
363 {
364 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
365 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
366 8);
367 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
369
370 if (cmd_buffer->device->physical_device->has_rbplus) {
371
372 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
373 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
374
375 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
376 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
377 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
378 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
379 }
380 }
381
382 static void
383 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
384 struct radv_pipeline *pipeline)
385 {
386 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
387 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
388 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
389
390 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
391 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
392 }
393
394 /* 12.4 fixed-point */
395 static unsigned radv_pack_float_12p4(float x)
396 {
397 return x <= 0 ? 0 :
398 x >= 4096 ? 0xffff : x * 16;
399 }
400
401 uint32_t
402 radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
403 {
404 switch (stage) {
405 case MESA_SHADER_FRAGMENT:
406 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
407 case MESA_SHADER_VERTEX:
408 if (has_tess)
409 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
410 else
411 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
412 case MESA_SHADER_GEOMETRY:
413 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
414 case MESA_SHADER_COMPUTE:
415 return R_00B900_COMPUTE_USER_DATA_0;
416 case MESA_SHADER_TESS_CTRL:
417 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
418 case MESA_SHADER_TESS_EVAL:
419 if (has_gs)
420 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
421 else
422 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
423 default:
424 unreachable("unknown shader");
425 }
426 }
427
428 struct ac_userdata_info *
429 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
430 gl_shader_stage stage,
431 int idx)
432 {
433 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
434 }
435
436 static void
437 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
438 struct radv_pipeline *pipeline,
439 gl_shader_stage stage,
440 int idx, uint64_t va)
441 {
442 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
443 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
444 if (loc->sgpr_idx == -1)
445 return;
446 assert(loc->num_sgprs == 2);
447 assert(!loc->indirect);
448 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
449 radeon_emit(cmd_buffer->cs, va);
450 radeon_emit(cmd_buffer->cs, va >> 32);
451 }
452
453 static void
454 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
455 struct radv_pipeline *pipeline)
456 {
457 int num_samples = pipeline->graphics.ms.num_samples;
458 struct radv_multisample_state *ms = &pipeline->graphics.ms;
459 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
460
461 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
462 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
463 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
464
465 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
466 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
467
468 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
469 return;
470
471 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
472 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
473 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
474
475 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
476
477 /* GFX9: Flush DFSM when the AA mode changes. */
478 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
479 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
480 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
481 }
482 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
483 uint32_t offset;
484 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
485 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
486 if (loc->sgpr_idx == -1)
487 return;
488 assert(loc->num_sgprs == 1);
489 assert(!loc->indirect);
490 switch (num_samples) {
491 default:
492 offset = 0;
493 break;
494 case 2:
495 offset = 1;
496 break;
497 case 4:
498 offset = 3;
499 break;
500 case 8:
501 offset = 7;
502 break;
503 case 16:
504 offset = 15;
505 break;
506 }
507
508 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
509 cmd_buffer->sample_positions_needed = true;
510 }
511 }
512
513 static void
514 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
515 struct radv_pipeline *pipeline)
516 {
517 struct radv_raster_state *raster = &pipeline->graphics.raster;
518
519 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
520 raster->pa_cl_clip_cntl);
521
522 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
523 raster->spi_interp_control);
524
525 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
526 unsigned tmp = (unsigned)(1.0 * 8.0);
527 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
528 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
529 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
530
531 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
532 raster->pa_su_vtx_cntl);
533
534 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
535 raster->pa_su_sc_mode_cntl);
536 }
537
538 static inline void
539 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
540 unsigned size)
541 {
542 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
543 si_cp_dma_prefetch(cmd_buffer, va, size);
544 }
545
546 static void
547 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
548 struct radv_pipeline *pipeline,
549 struct radv_shader_variant *shader,
550 struct ac_vs_output_info *outinfo)
551 {
552 struct radeon_winsys *ws = cmd_buffer->device->ws;
553 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
554 unsigned export_count;
555
556 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
557 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
558
559 export_count = MAX2(1, outinfo->param_exports);
560 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
561 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
562
563 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
564 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
565 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
566 V_02870C_SPI_SHADER_4COMP :
567 V_02870C_SPI_SHADER_NONE) |
568 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
569 V_02870C_SPI_SHADER_4COMP :
570 V_02870C_SPI_SHADER_NONE) |
571 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
572 V_02870C_SPI_SHADER_4COMP :
573 V_02870C_SPI_SHADER_NONE));
574
575
576 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
577 radeon_emit(cmd_buffer->cs, va >> 8);
578 radeon_emit(cmd_buffer->cs, va >> 40);
579 radeon_emit(cmd_buffer->cs, shader->rsrc1);
580 radeon_emit(cmd_buffer->cs, shader->rsrc2);
581
582 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
583 S_028818_VTX_W0_FMT(1) |
584 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
585 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
586 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
587
588
589 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
590 pipeline->graphics.pa_cl_vs_out_cntl);
591
592 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
593 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
594 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
595 }
596
597 static void
598 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
599 struct radv_shader_variant *shader,
600 struct ac_es_output_info *outinfo)
601 {
602 struct radeon_winsys *ws = cmd_buffer->device->ws;
603 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
604
605 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
606 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
607
608 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
609 outinfo->esgs_itemsize / 4);
610 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
611 radeon_emit(cmd_buffer->cs, va >> 8);
612 radeon_emit(cmd_buffer->cs, va >> 40);
613 radeon_emit(cmd_buffer->cs, shader->rsrc1);
614 radeon_emit(cmd_buffer->cs, shader->rsrc2);
615 }
616
617 static void
618 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
619 struct radv_shader_variant *shader)
620 {
621 struct radeon_winsys *ws = cmd_buffer->device->ws;
622 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
623 uint32_t rsrc2 = shader->rsrc2;
624
625 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
626 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
627
628 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
629 radeon_emit(cmd_buffer->cs, va >> 8);
630 radeon_emit(cmd_buffer->cs, va >> 40);
631
632 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
633 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
634 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
635 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
636
637 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
638 radeon_emit(cmd_buffer->cs, shader->rsrc1);
639 radeon_emit(cmd_buffer->cs, rsrc2);
640 }
641
642 static void
643 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
644 struct radv_shader_variant *shader)
645 {
646 struct radeon_winsys *ws = cmd_buffer->device->ws;
647 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
648
649 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
650 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
651
652 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
653 radeon_emit(cmd_buffer->cs, va >> 8);
654 radeon_emit(cmd_buffer->cs, va >> 40);
655 radeon_emit(cmd_buffer->cs, shader->rsrc1);
656 radeon_emit(cmd_buffer->cs, shader->rsrc2);
657 }
658
659 static void
660 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
661 struct radv_pipeline *pipeline)
662 {
663 struct radv_shader_variant *vs;
664
665 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
666
667 vs = pipeline->shaders[MESA_SHADER_VERTEX];
668
669 if (vs->info.vs.as_ls)
670 radv_emit_hw_ls(cmd_buffer, vs);
671 else if (vs->info.vs.as_es)
672 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
673 else
674 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
675
676 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
677 }
678
679
680 static void
681 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
682 struct radv_pipeline *pipeline)
683 {
684 if (!radv_pipeline_has_tess(pipeline))
685 return;
686
687 struct radv_shader_variant *tes, *tcs;
688
689 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
690 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
691
692 if (tes->info.tes.as_es)
693 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
694 else
695 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
696
697 radv_emit_hw_hs(cmd_buffer, tcs);
698
699 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
700 pipeline->graphics.tess.tf_param);
701
702 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
703 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
704 pipeline->graphics.tess.ls_hs_config);
705 else
706 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
707 pipeline->graphics.tess.ls_hs_config);
708
709 struct ac_userdata_info *loc;
710
711 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
712 if (loc->sgpr_idx != -1) {
713 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
714 assert(loc->num_sgprs == 4);
715 assert(!loc->indirect);
716 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
717 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
718 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
719 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
720 pipeline->graphics.tess.num_tcs_input_cp << 26);
721 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
722 }
723
724 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
725 if (loc->sgpr_idx != -1) {
726 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
727 assert(loc->num_sgprs == 1);
728 assert(!loc->indirect);
729
730 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
731 pipeline->graphics.tess.offchip_layout);
732 }
733
734 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
735 if (loc->sgpr_idx != -1) {
736 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
737 assert(loc->num_sgprs == 1);
738 assert(!loc->indirect);
739
740 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
741 pipeline->graphics.tess.tcs_in_layout);
742 }
743 }
744
745 static void
746 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
747 struct radv_pipeline *pipeline)
748 {
749 struct radeon_winsys *ws = cmd_buffer->device->ws;
750 struct radv_shader_variant *gs;
751 uint64_t va;
752
753 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
754
755 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
756 if (!gs)
757 return;
758
759 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
760
761 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
762 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
763 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
764 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
765
766 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
767
768 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
769
770 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
771 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
772 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
773 radeon_emit(cmd_buffer->cs, 0);
774 radeon_emit(cmd_buffer->cs, 0);
775 radeon_emit(cmd_buffer->cs, 0);
776
777 uint32_t gs_num_invocations = gs->info.gs.invocations;
778 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
779 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
780 S_028B90_ENABLE(gs_num_invocations > 0));
781
782 va = ws->buffer_get_va(gs->bo) + gs->bo_offset;
783 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
784 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
785
786 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
787 radeon_emit(cmd_buffer->cs, va >> 8);
788 radeon_emit(cmd_buffer->cs, va >> 40);
789 radeon_emit(cmd_buffer->cs, gs->rsrc1);
790 radeon_emit(cmd_buffer->cs, gs->rsrc2);
791
792 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
793
794 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
795 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
796 if (loc->sgpr_idx != -1) {
797 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
798 uint32_t num_entries = 64;
799 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
800
801 if (is_vi)
802 num_entries *= stride;
803
804 stride = S_008F04_STRIDE(stride);
805 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
806 radeon_emit(cmd_buffer->cs, stride);
807 radeon_emit(cmd_buffer->cs, num_entries);
808 }
809 }
810
811 static void
812 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
813 struct radv_pipeline *pipeline)
814 {
815 struct radeon_winsys *ws = cmd_buffer->device->ws;
816 struct radv_shader_variant *ps;
817 uint64_t va;
818 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
819 struct radv_blend_state *blend = &pipeline->graphics.blend;
820 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
821
822 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
823 va = ws->buffer_get_va(ps->bo) + ps->bo_offset;
824 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
825 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
826
827 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
828 radeon_emit(cmd_buffer->cs, va >> 8);
829 radeon_emit(cmd_buffer->cs, va >> 40);
830 radeon_emit(cmd_buffer->cs, ps->rsrc1);
831 radeon_emit(cmd_buffer->cs, ps->rsrc2);
832
833 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
834 pipeline->graphics.db_shader_control);
835
836 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
837 ps->config.spi_ps_input_ena);
838
839 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
840 ps->config.spi_ps_input_addr);
841
842 if (ps->info.info.ps.force_persample)
843 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
844
845 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
846 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
847
848 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
849
850 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
851 pipeline->graphics.shader_z_format);
852
853 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
854
855 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
856 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
857
858 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
859 /* optimise this? */
860 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
861 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
862 }
863
864 if (pipeline->graphics.ps_input_cntl_num) {
865 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
866 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
867 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
868 }
869 }
870 }
871
872 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
873 struct radv_pipeline *pipeline)
874 {
875 uint32_t vtx_reuse_depth = 30;
876 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
877 return;
878
879 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
880 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
881 vtx_reuse_depth = 14;
882 }
883 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
884 vtx_reuse_depth);
885 }
886
887 static void
888 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
889 struct radv_pipeline *pipeline)
890 {
891 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
892 return;
893
894 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
895 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
896 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
897 radv_update_multisample_state(cmd_buffer, pipeline);
898 radv_emit_vertex_shader(cmd_buffer, pipeline);
899 radv_emit_tess_shaders(cmd_buffer, pipeline);
900 radv_emit_geometry_shader(cmd_buffer, pipeline);
901 radv_emit_fragment_shader(cmd_buffer, pipeline);
902 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
903
904 cmd_buffer->scratch_size_needed =
905 MAX2(cmd_buffer->scratch_size_needed,
906 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
907
908 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
909 S_0286E8_WAVES(pipeline->max_waves) |
910 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
911
912 if (!cmd_buffer->state.emitted_pipeline ||
913 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
914 pipeline->graphics.can_use_guardband)
915 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
916
917 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
918
919 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
920 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
921 } else {
922 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
923 }
924 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
925
926 cmd_buffer->state.emitted_pipeline = pipeline;
927 }
928
929 static void
930 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
931 {
932 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
933 cmd_buffer->state.dynamic.viewport.viewports);
934 }
935
936 static void
937 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
938 {
939 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
940 si_write_scissors(cmd_buffer->cs, 0, count,
941 cmd_buffer->state.dynamic.scissor.scissors,
942 cmd_buffer->state.dynamic.viewport.viewports,
943 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
944 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
945 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
946 }
947
948 static void
949 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
950 int index,
951 struct radv_color_buffer_info *cb)
952 {
953 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
954
955 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
956 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
957 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
958 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
959 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
960 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
961 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
962 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
963 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
964 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
965 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
966 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
967 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
968
969 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
970 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
971 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
972
973 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
974 cb->gfx9_epitch);
975 } else {
976 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
977 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
978 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
979 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
980 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
981 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
982 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
983 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
984 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
985 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
986 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
987 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
988
989 if (is_vi) { /* DCC BASE */
990 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
991 }
992 }
993 }
994
995 static void
996 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
997 struct radv_ds_buffer_info *ds,
998 struct radv_image *image,
999 VkImageLayout layout)
1000 {
1001 uint32_t db_z_info = ds->db_z_info;
1002 uint32_t db_stencil_info = ds->db_stencil_info;
1003
1004 if (!radv_layout_has_htile(image, layout,
1005 radv_image_queue_family_mask(image,
1006 cmd_buffer->queue_family_index,
1007 cmd_buffer->queue_family_index))) {
1008 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1009 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1010 }
1011
1012 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1013 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1014
1015
1016 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1017 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1018 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1019 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1020 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1021
1022 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1023 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1024 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1025 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1026 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1027 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1028 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1029 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1030 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1031 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1032 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1033
1034 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1035 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1036 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1037 } else {
1038 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1039
1040 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1041 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1042 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1043 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1044 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1045 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1046 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1047 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1048 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1049 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1050
1051 }
1052
1053 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1054 ds->pa_su_poly_offset_db_fmt_cntl);
1055 }
1056
1057 void
1058 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1059 struct radv_image *image,
1060 VkClearDepthStencilValue ds_clear_value,
1061 VkImageAspectFlags aspects)
1062 {
1063 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1064 va += image->offset + image->clear_value_offset;
1065 unsigned reg_offset = 0, reg_count = 0;
1066
1067 if (!image->surface.htile_size || !aspects)
1068 return;
1069
1070 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1071 ++reg_count;
1072 } else {
1073 ++reg_offset;
1074 va += 4;
1075 }
1076 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1077 ++reg_count;
1078
1079 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1080
1081 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1082 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1083 S_370_WR_CONFIRM(1) |
1084 S_370_ENGINE_SEL(V_370_PFP));
1085 radeon_emit(cmd_buffer->cs, va);
1086 radeon_emit(cmd_buffer->cs, va >> 32);
1087 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1088 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1089 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1090 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1091
1092 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1093 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1094 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1095 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1096 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1097 }
1098
1099 static void
1100 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1101 struct radv_image *image)
1102 {
1103 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1104 va += image->offset + image->clear_value_offset;
1105
1106 if (!image->surface.htile_size)
1107 return;
1108
1109 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1110
1111 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1112 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1113 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1114 COPY_DATA_COUNT_SEL);
1115 radeon_emit(cmd_buffer->cs, va);
1116 radeon_emit(cmd_buffer->cs, va >> 32);
1117 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1118 radeon_emit(cmd_buffer->cs, 0);
1119
1120 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1121 radeon_emit(cmd_buffer->cs, 0);
1122 }
1123
1124 /*
1125 *with DCC some colors don't require CMASK elimiation before being
1126 * used as a texture. This sets a predicate value to determine if the
1127 * cmask eliminate is required.
1128 */
1129 void
1130 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1131 struct radv_image *image,
1132 bool value)
1133 {
1134 uint64_t pred_val = value;
1135 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1136 va += image->offset + image->dcc_pred_offset;
1137
1138 if (!image->surface.dcc_size)
1139 return;
1140
1141 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1142
1143 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1144 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1145 S_370_WR_CONFIRM(1) |
1146 S_370_ENGINE_SEL(V_370_PFP));
1147 radeon_emit(cmd_buffer->cs, va);
1148 radeon_emit(cmd_buffer->cs, va >> 32);
1149 radeon_emit(cmd_buffer->cs, pred_val);
1150 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1151 }
1152
1153 void
1154 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1155 struct radv_image *image,
1156 int idx,
1157 uint32_t color_values[2])
1158 {
1159 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1160 va += image->offset + image->clear_value_offset;
1161
1162 if (!image->cmask.size && !image->surface.dcc_size)
1163 return;
1164
1165 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1166
1167 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1168 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1169 S_370_WR_CONFIRM(1) |
1170 S_370_ENGINE_SEL(V_370_PFP));
1171 radeon_emit(cmd_buffer->cs, va);
1172 radeon_emit(cmd_buffer->cs, va >> 32);
1173 radeon_emit(cmd_buffer->cs, color_values[0]);
1174 radeon_emit(cmd_buffer->cs, color_values[1]);
1175
1176 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1177 radeon_emit(cmd_buffer->cs, color_values[0]);
1178 radeon_emit(cmd_buffer->cs, color_values[1]);
1179 }
1180
1181 static void
1182 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1183 struct radv_image *image,
1184 int idx)
1185 {
1186 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1187 va += image->offset + image->clear_value_offset;
1188
1189 if (!image->cmask.size && !image->surface.dcc_size)
1190 return;
1191
1192 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1193 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1194
1195 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1196 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1197 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1198 COPY_DATA_COUNT_SEL);
1199 radeon_emit(cmd_buffer->cs, va);
1200 radeon_emit(cmd_buffer->cs, va >> 32);
1201 radeon_emit(cmd_buffer->cs, reg >> 2);
1202 radeon_emit(cmd_buffer->cs, 0);
1203
1204 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1205 radeon_emit(cmd_buffer->cs, 0);
1206 }
1207
1208 void
1209 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1210 {
1211 int i;
1212 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1213 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1214
1215 /* this may happen for inherited secondary recording */
1216 if (!framebuffer)
1217 return;
1218
1219 for (i = 0; i < 8; ++i) {
1220 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1221 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1222 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1223 continue;
1224 }
1225
1226 int idx = subpass->color_attachments[i].attachment;
1227 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1228
1229 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1230
1231 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1232 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1233
1234 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1235 }
1236
1237 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1238 int idx = subpass->depth_stencil_attachment.attachment;
1239 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1240 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1241 struct radv_image *image = att->attachment->image;
1242 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1243 uint32_t queue_mask = radv_image_queue_family_mask(image,
1244 cmd_buffer->queue_family_index,
1245 cmd_buffer->queue_family_index);
1246 /* We currently don't support writing decompressed HTILE */
1247 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1248 radv_layout_is_htile_compressed(image, layout, queue_mask));
1249
1250 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1251
1252 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1253 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1254 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1255 }
1256 radv_load_depth_clear_regs(cmd_buffer, image);
1257 } else {
1258 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1259 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1260 else
1261 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1262
1263 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1264 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1265 }
1266 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1267 S_028208_BR_X(framebuffer->width) |
1268 S_028208_BR_Y(framebuffer->height));
1269
1270 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1271 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1272 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1273 }
1274 }
1275
1276 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1277 {
1278 uint32_t db_count_control;
1279
1280 if(!cmd_buffer->state.active_occlusion_queries) {
1281 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1282 db_count_control = 0;
1283 } else {
1284 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1285 }
1286 } else {
1287 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1288 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1289 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1290 S_028004_ZPASS_ENABLE(1) |
1291 S_028004_SLICE_EVEN_ENABLE(1) |
1292 S_028004_SLICE_ODD_ENABLE(1);
1293 } else {
1294 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1295 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1296 }
1297 }
1298
1299 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1300 }
1301
1302 static void
1303 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1304 {
1305 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1306
1307 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1308 return;
1309
1310 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1311 radv_emit_viewport(cmd_buffer);
1312
1313 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1314 radv_emit_scissor(cmd_buffer);
1315
1316 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1317 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1318 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1319 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1320 }
1321
1322 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1323 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1324 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1325 }
1326
1327 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1328 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1329 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1330 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1331 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1332 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1333 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1334 S_028430_STENCILOPVAL(1));
1335 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1336 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1337 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1338 S_028434_STENCILOPVAL_BF(1));
1339 }
1340
1341 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1342 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1343 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1344 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1345 }
1346
1347 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1348 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1349 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1350 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1351 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1352
1353 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1354 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1355 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1356 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1357 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1358 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1359 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1360 }
1361 }
1362
1363 cmd_buffer->state.dirty = 0;
1364 }
1365
1366 static void
1367 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1368 struct radv_pipeline *pipeline,
1369 int idx,
1370 uint64_t va,
1371 gl_shader_stage stage)
1372 {
1373 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1374 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1375
1376 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1377 return;
1378
1379 assert(!desc_set_loc->indirect);
1380 assert(desc_set_loc->num_sgprs == 2);
1381 radeon_set_sh_reg_seq(cmd_buffer->cs,
1382 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1383 radeon_emit(cmd_buffer->cs, va);
1384 radeon_emit(cmd_buffer->cs, va >> 32);
1385 }
1386
1387 static void
1388 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1389 VkShaderStageFlags stages,
1390 struct radv_descriptor_set *set,
1391 unsigned idx)
1392 {
1393 if (cmd_buffer->state.pipeline) {
1394 radv_foreach_stage(stage, stages) {
1395 if (cmd_buffer->state.pipeline->shaders[stage])
1396 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1397 idx, set->va,
1398 stage);
1399 }
1400 }
1401
1402 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1403 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1404 idx, set->va,
1405 MESA_SHADER_COMPUTE);
1406 }
1407
1408 static void
1409 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1410 {
1411 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1412 uint32_t *ptr = NULL;
1413 unsigned bo_offset;
1414
1415 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1416 &bo_offset,
1417 (void**) &ptr))
1418 return;
1419
1420 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1421 set->va += bo_offset;
1422
1423 memcpy(ptr, set->mapped_ptr, set->size);
1424 }
1425
1426 static void
1427 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1428 {
1429 uint32_t size = MAX_SETS * 2 * 4;
1430 uint32_t offset;
1431 void *ptr;
1432
1433 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1434 256, &offset, &ptr))
1435 return;
1436
1437 for (unsigned i = 0; i < MAX_SETS; i++) {
1438 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1439 uint64_t set_va = 0;
1440 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1441 if (set)
1442 set_va = set->va;
1443 uptr[0] = set_va & 0xffffffff;
1444 uptr[1] = set_va >> 32;
1445 }
1446
1447 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1448 va += offset;
1449
1450 if (cmd_buffer->state.pipeline) {
1451 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1452 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1453 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1454
1455 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1456 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1457 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1458
1459 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1460 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1461 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1462
1463 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1464 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1465 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1466
1467 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1468 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1469 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1470 }
1471
1472 if (cmd_buffer->state.compute_pipeline)
1473 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1474 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1475 }
1476
1477 static void
1478 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1479 VkShaderStageFlags stages)
1480 {
1481 unsigned i;
1482
1483 if (!cmd_buffer->state.descriptors_dirty)
1484 return;
1485
1486 if (cmd_buffer->state.push_descriptors_dirty)
1487 radv_flush_push_descriptors(cmd_buffer);
1488
1489 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1490 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1491 radv_flush_indirect_descriptor_sets(cmd_buffer);
1492 }
1493
1494 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1495 cmd_buffer->cs,
1496 MAX_SETS * MESA_SHADER_STAGES * 4);
1497
1498 for (i = 0; i < MAX_SETS; i++) {
1499 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1500 continue;
1501 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1502 if (!set)
1503 continue;
1504
1505 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1506 }
1507 cmd_buffer->state.descriptors_dirty = 0;
1508 cmd_buffer->state.push_descriptors_dirty = false;
1509 assert(cmd_buffer->cs->cdw <= cdw_max);
1510 }
1511
1512 static void
1513 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1514 struct radv_pipeline *pipeline,
1515 VkShaderStageFlags stages)
1516 {
1517 struct radv_pipeline_layout *layout = pipeline->layout;
1518 unsigned offset;
1519 void *ptr;
1520 uint64_t va;
1521
1522 stages &= cmd_buffer->push_constant_stages;
1523 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1524 return;
1525
1526 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1527 16 * layout->dynamic_offset_count,
1528 256, &offset, &ptr))
1529 return;
1530
1531 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1532 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1533 16 * layout->dynamic_offset_count);
1534
1535 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1536 va += offset;
1537
1538 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1539 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1540
1541 radv_foreach_stage(stage, stages) {
1542 if (pipeline->shaders[stage]) {
1543 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1544 AC_UD_PUSH_CONSTANTS, va);
1545 }
1546 }
1547
1548 cmd_buffer->push_constant_stages &= ~stages;
1549 assert(cmd_buffer->cs->cdw <= cdw_max);
1550 }
1551
1552 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1553 bool indexed_draw)
1554 {
1555 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1556
1557 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1558 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1559 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1560 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1561 primitive_reset_en);
1562 } else {
1563 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1564 primitive_reset_en);
1565 }
1566 }
1567
1568 if (primitive_reset_en) {
1569 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1570
1571 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1572 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1573 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1574 primitive_reset_index);
1575 }
1576 }
1577 }
1578
1579 static void
1580 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1581 {
1582 struct radv_device *device = cmd_buffer->device;
1583
1584 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1585 cmd_buffer->state.pipeline->num_vertex_attribs &&
1586 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1587 unsigned vb_offset;
1588 void *vb_ptr;
1589 uint32_t i = 0;
1590 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1591 uint64_t va;
1592
1593 /* allocate some descriptor state for vertex buffers */
1594 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1595 &vb_offset, &vb_ptr);
1596
1597 for (i = 0; i < num_attribs; i++) {
1598 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1599 uint32_t offset;
1600 int vb = cmd_buffer->state.pipeline->va_binding[i];
1601 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1602 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1603
1604 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1605 va = device->ws->buffer_get_va(buffer->bo);
1606
1607 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1608 va += offset + buffer->offset;
1609 desc[0] = va;
1610 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1611 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1612 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1613 else
1614 desc[2] = buffer->size - offset;
1615 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1616 }
1617
1618 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1619 va += vb_offset;
1620
1621 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1622 AC_UD_VS_VERTEX_BUFFERS, va);
1623 }
1624 cmd_buffer->state.vb_dirty = 0;
1625 }
1626
1627 static void
1628 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1629 bool indexed_draw, bool instanced_draw,
1630 bool indirect_draw,
1631 uint32_t draw_vertex_count)
1632 {
1633 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1634 uint32_t ia_multi_vgt_param;
1635
1636 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1637 cmd_buffer->cs, 4096);
1638
1639 radv_cmd_buffer_update_vertex_descriptors(cmd_buffer);
1640
1641 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1642 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1643
1644 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1645 radv_emit_framebuffer_state(cmd_buffer);
1646
1647 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1648 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1649 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1650 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1651 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1652 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1653 else
1654 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1655 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1656 }
1657
1658 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1659
1660 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1661
1662 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1663 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1664 VK_SHADER_STAGE_ALL_GRAPHICS);
1665
1666 assert(cmd_buffer->cs->cdw <= cdw_max);
1667
1668 si_emit_cache_flush(cmd_buffer);
1669 }
1670
1671 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1672 VkPipelineStageFlags src_stage_mask)
1673 {
1674 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1675 VK_PIPELINE_STAGE_TRANSFER_BIT |
1676 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1677 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1678 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1679 }
1680
1681 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1682 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1683 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1684 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1685 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1686 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1687 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1688 VK_PIPELINE_STAGE_TRANSFER_BIT |
1689 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1690 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1691 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1692 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1693 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1694 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1695 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1696 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1697 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1698 }
1699 }
1700
1701 static enum radv_cmd_flush_bits
1702 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1703 VkAccessFlags src_flags)
1704 {
1705 enum radv_cmd_flush_bits flush_bits = 0;
1706 uint32_t b;
1707 for_each_bit(b, src_flags) {
1708 switch ((VkAccessFlagBits)(1 << b)) {
1709 case VK_ACCESS_SHADER_WRITE_BIT:
1710 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1711 break;
1712 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1713 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1714 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1715 break;
1716 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1717 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1718 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1719 break;
1720 case VK_ACCESS_TRANSFER_WRITE_BIT:
1721 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1722 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1723 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1724 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1725 RADV_CMD_FLAG_INV_GLOBAL_L2;
1726 break;
1727 default:
1728 break;
1729 }
1730 }
1731 return flush_bits;
1732 }
1733
1734 static enum radv_cmd_flush_bits
1735 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1736 VkAccessFlags dst_flags,
1737 struct radv_image *image)
1738 {
1739 enum radv_cmd_flush_bits flush_bits = 0;
1740 uint32_t b;
1741 for_each_bit(b, dst_flags) {
1742 switch ((VkAccessFlagBits)(1 << b)) {
1743 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1744 case VK_ACCESS_INDEX_READ_BIT:
1745 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1746 break;
1747 case VK_ACCESS_UNIFORM_READ_BIT:
1748 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1749 break;
1750 case VK_ACCESS_SHADER_READ_BIT:
1751 case VK_ACCESS_TRANSFER_READ_BIT:
1752 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1753 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1754 RADV_CMD_FLAG_INV_GLOBAL_L2;
1755 break;
1756 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1757 /* TODO: change to image && when the image gets passed
1758 * through from the subpass. */
1759 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1760 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1761 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1762 break;
1763 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1764 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1765 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1766 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1767 break;
1768 default:
1769 break;
1770 }
1771 }
1772 return flush_bits;
1773 }
1774
1775 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1776 {
1777 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1778 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1779 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1780 NULL);
1781 }
1782
1783 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1784 VkAttachmentReference att)
1785 {
1786 unsigned idx = att.attachment;
1787 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1788 VkImageSubresourceRange range;
1789 range.aspectMask = 0;
1790 range.baseMipLevel = view->base_mip;
1791 range.levelCount = 1;
1792 range.baseArrayLayer = view->base_layer;
1793 range.layerCount = cmd_buffer->state.framebuffer->layers;
1794
1795 radv_handle_image_transition(cmd_buffer,
1796 view->image,
1797 cmd_buffer->state.attachments[idx].current_layout,
1798 att.layout, 0, 0, &range,
1799 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1800
1801 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1802
1803
1804 }
1805
1806 void
1807 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1808 const struct radv_subpass *subpass, bool transitions)
1809 {
1810 if (transitions) {
1811 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1812
1813 for (unsigned i = 0; i < subpass->color_count; ++i) {
1814 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1815 radv_handle_subpass_image_transition(cmd_buffer,
1816 subpass->color_attachments[i]);
1817 }
1818
1819 for (unsigned i = 0; i < subpass->input_count; ++i) {
1820 radv_handle_subpass_image_transition(cmd_buffer,
1821 subpass->input_attachments[i]);
1822 }
1823
1824 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1825 radv_handle_subpass_image_transition(cmd_buffer,
1826 subpass->depth_stencil_attachment);
1827 }
1828 }
1829
1830 cmd_buffer->state.subpass = subpass;
1831
1832 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1833 }
1834
1835 static VkResult
1836 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1837 struct radv_render_pass *pass,
1838 const VkRenderPassBeginInfo *info)
1839 {
1840 struct radv_cmd_state *state = &cmd_buffer->state;
1841
1842 if (pass->attachment_count == 0) {
1843 state->attachments = NULL;
1844 return VK_SUCCESS;
1845 }
1846
1847 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1848 pass->attachment_count *
1849 sizeof(state->attachments[0]),
1850 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1851 if (state->attachments == NULL) {
1852 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1853 return cmd_buffer->record_result;
1854 }
1855
1856 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1857 struct radv_render_pass_attachment *att = &pass->attachments[i];
1858 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1859 VkImageAspectFlags clear_aspects = 0;
1860
1861 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1862 /* color attachment */
1863 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1864 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1865 }
1866 } else {
1867 /* depthstencil attachment */
1868 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1869 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1870 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1871 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1872 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1873 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1874 }
1875 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1876 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1877 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1878 }
1879 }
1880
1881 state->attachments[i].pending_clear_aspects = clear_aspects;
1882 state->attachments[i].cleared_views = 0;
1883 if (clear_aspects && info) {
1884 assert(info->clearValueCount > i);
1885 state->attachments[i].clear_value = info->pClearValues[i];
1886 }
1887
1888 state->attachments[i].current_layout = att->initial_layout;
1889 }
1890
1891 return VK_SUCCESS;
1892 }
1893
1894 VkResult radv_AllocateCommandBuffers(
1895 VkDevice _device,
1896 const VkCommandBufferAllocateInfo *pAllocateInfo,
1897 VkCommandBuffer *pCommandBuffers)
1898 {
1899 RADV_FROM_HANDLE(radv_device, device, _device);
1900 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1901
1902 VkResult result = VK_SUCCESS;
1903 uint32_t i;
1904
1905 memset(pCommandBuffers, 0,
1906 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1907
1908 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1909
1910 if (!list_empty(&pool->free_cmd_buffers)) {
1911 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1912
1913 list_del(&cmd_buffer->pool_link);
1914 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1915
1916 radv_reset_cmd_buffer(cmd_buffer);
1917 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1918 cmd_buffer->level = pAllocateInfo->level;
1919
1920 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1921 result = VK_SUCCESS;
1922 } else {
1923 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1924 &pCommandBuffers[i]);
1925 }
1926 if (result != VK_SUCCESS)
1927 break;
1928 }
1929
1930 if (result != VK_SUCCESS)
1931 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1932 i, pCommandBuffers);
1933
1934 return result;
1935 }
1936
1937 void radv_FreeCommandBuffers(
1938 VkDevice device,
1939 VkCommandPool commandPool,
1940 uint32_t commandBufferCount,
1941 const VkCommandBuffer *pCommandBuffers)
1942 {
1943 for (uint32_t i = 0; i < commandBufferCount; i++) {
1944 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1945
1946 if (cmd_buffer) {
1947 if (cmd_buffer->pool) {
1948 list_del(&cmd_buffer->pool_link);
1949 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1950 } else
1951 radv_cmd_buffer_destroy(cmd_buffer);
1952
1953 }
1954 }
1955 }
1956
1957 VkResult radv_ResetCommandBuffer(
1958 VkCommandBuffer commandBuffer,
1959 VkCommandBufferResetFlags flags)
1960 {
1961 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1962 radv_reset_cmd_buffer(cmd_buffer);
1963 return VK_SUCCESS;
1964 }
1965
1966 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1967 {
1968 struct radv_device *device = cmd_buffer->device;
1969 if (device->gfx_init) {
1970 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1971 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1972 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1973 radeon_emit(cmd_buffer->cs, va);
1974 radeon_emit(cmd_buffer->cs, va >> 32);
1975 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1976 } else
1977 si_init_config(cmd_buffer);
1978 }
1979
1980 VkResult radv_BeginCommandBuffer(
1981 VkCommandBuffer commandBuffer,
1982 const VkCommandBufferBeginInfo *pBeginInfo)
1983 {
1984 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1985 VkResult result = VK_SUCCESS;
1986
1987 radv_reset_cmd_buffer(cmd_buffer);
1988
1989 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1990 cmd_buffer->state.last_primitive_reset_en = -1;
1991
1992 /* setup initial configuration into command buffer */
1993 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1994 switch (cmd_buffer->queue_family_index) {
1995 case RADV_QUEUE_GENERAL:
1996 emit_gfx_buffer_state(cmd_buffer);
1997 radv_set_db_count_control(cmd_buffer);
1998 break;
1999 case RADV_QUEUE_COMPUTE:
2000 si_init_compute(cmd_buffer);
2001 break;
2002 case RADV_QUEUE_TRANSFER:
2003 default:
2004 break;
2005 }
2006 }
2007
2008 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2009 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2010 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2011
2012 struct radv_subpass *subpass =
2013 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2014
2015 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2016 if (result != VK_SUCCESS)
2017 return result;
2018
2019 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2020 }
2021
2022 radv_cmd_buffer_trace_emit(cmd_buffer);
2023 return result;
2024 }
2025
2026 void radv_CmdBindVertexBuffers(
2027 VkCommandBuffer commandBuffer,
2028 uint32_t firstBinding,
2029 uint32_t bindingCount,
2030 const VkBuffer* pBuffers,
2031 const VkDeviceSize* pOffsets)
2032 {
2033 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2034 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2035
2036 /* We have to defer setting up vertex buffer since we need the buffer
2037 * stride from the pipeline. */
2038
2039 assert(firstBinding + bindingCount <= MAX_VBS);
2040 for (uint32_t i = 0; i < bindingCount; i++) {
2041 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2042 vb[firstBinding + i].offset = pOffsets[i];
2043 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
2044 }
2045 }
2046
2047 void radv_CmdBindIndexBuffer(
2048 VkCommandBuffer commandBuffer,
2049 VkBuffer buffer,
2050 VkDeviceSize offset,
2051 VkIndexType indexType)
2052 {
2053 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2054 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2055
2056 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2057 cmd_buffer->state.index_va = cmd_buffer->device->ws->buffer_get_va(index_buffer->bo);
2058 cmd_buffer->state.index_va += index_buffer->offset + offset;
2059
2060 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2061 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2062 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2063 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2064 }
2065
2066
2067 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2068 struct radv_descriptor_set *set,
2069 unsigned idx)
2070 {
2071 struct radeon_winsys *ws = cmd_buffer->device->ws;
2072
2073 cmd_buffer->state.descriptors[idx] = set;
2074 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2075 if (!set)
2076 return;
2077
2078 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2079
2080 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2081 if (set->descriptors[j])
2082 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2083
2084 if(set->bo)
2085 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2086 }
2087
2088 void radv_CmdBindDescriptorSets(
2089 VkCommandBuffer commandBuffer,
2090 VkPipelineBindPoint pipelineBindPoint,
2091 VkPipelineLayout _layout,
2092 uint32_t firstSet,
2093 uint32_t descriptorSetCount,
2094 const VkDescriptorSet* pDescriptorSets,
2095 uint32_t dynamicOffsetCount,
2096 const uint32_t* pDynamicOffsets)
2097 {
2098 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2099 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2100 unsigned dyn_idx = 0;
2101
2102 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2103 unsigned idx = i + firstSet;
2104 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2105 radv_bind_descriptor_set(cmd_buffer, set, idx);
2106
2107 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2108 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2109 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2110 assert(dyn_idx < dynamicOffsetCount);
2111
2112 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2113 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2114 dst[0] = va;
2115 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2116 dst[2] = range->size;
2117 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2118 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2119 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2120 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2121 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2122 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2123 cmd_buffer->push_constant_stages |=
2124 set->layout->dynamic_shader_stages;
2125 }
2126 }
2127 }
2128
2129 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2130 struct radv_descriptor_set *set,
2131 struct radv_descriptor_set_layout *layout)
2132 {
2133 set->size = layout->size;
2134 set->layout = layout;
2135
2136 if (cmd_buffer->push_descriptors.capacity < set->size) {
2137 size_t new_size = MAX2(set->size, 1024);
2138 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2139 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2140
2141 free(set->mapped_ptr);
2142 set->mapped_ptr = malloc(new_size);
2143
2144 if (!set->mapped_ptr) {
2145 cmd_buffer->push_descriptors.capacity = 0;
2146 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2147 return false;
2148 }
2149
2150 cmd_buffer->push_descriptors.capacity = new_size;
2151 }
2152
2153 return true;
2154 }
2155
2156 void radv_meta_push_descriptor_set(
2157 struct radv_cmd_buffer* cmd_buffer,
2158 VkPipelineBindPoint pipelineBindPoint,
2159 VkPipelineLayout _layout,
2160 uint32_t set,
2161 uint32_t descriptorWriteCount,
2162 const VkWriteDescriptorSet* pDescriptorWrites)
2163 {
2164 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2165 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2166 unsigned bo_offset;
2167
2168 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2169
2170 push_set->size = layout->set[set].layout->size;
2171 push_set->layout = layout->set[set].layout;
2172
2173 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2174 &bo_offset,
2175 (void**) &push_set->mapped_ptr))
2176 return;
2177
2178 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2179 push_set->va += bo_offset;
2180
2181 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2182 radv_descriptor_set_to_handle(push_set),
2183 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2184
2185 cmd_buffer->state.descriptors[set] = push_set;
2186 cmd_buffer->state.descriptors_dirty |= (1u << set);
2187 }
2188
2189 void radv_CmdPushDescriptorSetKHR(
2190 VkCommandBuffer commandBuffer,
2191 VkPipelineBindPoint pipelineBindPoint,
2192 VkPipelineLayout _layout,
2193 uint32_t set,
2194 uint32_t descriptorWriteCount,
2195 const VkWriteDescriptorSet* pDescriptorWrites)
2196 {
2197 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2198 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2199 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2200
2201 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2202
2203 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2204 return;
2205
2206 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2207 radv_descriptor_set_to_handle(push_set),
2208 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2209
2210 cmd_buffer->state.descriptors[set] = push_set;
2211 cmd_buffer->state.descriptors_dirty |= (1u << set);
2212 cmd_buffer->state.push_descriptors_dirty = true;
2213 }
2214
2215 void radv_CmdPushDescriptorSetWithTemplateKHR(
2216 VkCommandBuffer commandBuffer,
2217 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2218 VkPipelineLayout _layout,
2219 uint32_t set,
2220 const void* pData)
2221 {
2222 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2223 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2224 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2225
2226 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2227
2228 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2229 return;
2230
2231 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2232 descriptorUpdateTemplate, pData);
2233
2234 cmd_buffer->state.descriptors[set] = push_set;
2235 cmd_buffer->state.descriptors_dirty |= (1u << set);
2236 cmd_buffer->state.push_descriptors_dirty = true;
2237 }
2238
2239 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2240 VkPipelineLayout layout,
2241 VkShaderStageFlags stageFlags,
2242 uint32_t offset,
2243 uint32_t size,
2244 const void* pValues)
2245 {
2246 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2247 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2248 cmd_buffer->push_constant_stages |= stageFlags;
2249 }
2250
2251 VkResult radv_EndCommandBuffer(
2252 VkCommandBuffer commandBuffer)
2253 {
2254 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2255
2256 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2257 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2258 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2259 si_emit_cache_flush(cmd_buffer);
2260 }
2261
2262 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2263 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2264
2265 return cmd_buffer->record_result;
2266 }
2267
2268 static void
2269 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2270 {
2271 struct radeon_winsys *ws = cmd_buffer->device->ws;
2272 struct radv_shader_variant *compute_shader;
2273 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2274 uint64_t va;
2275
2276 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2277 return;
2278
2279 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2280
2281 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2282 va = ws->buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2283
2284 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2285 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2286
2287 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2288 cmd_buffer->cs, 16);
2289
2290 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2291 radeon_emit(cmd_buffer->cs, va >> 8);
2292 radeon_emit(cmd_buffer->cs, va >> 40);
2293
2294 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2295 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2296 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2297
2298
2299 cmd_buffer->compute_scratch_size_needed =
2300 MAX2(cmd_buffer->compute_scratch_size_needed,
2301 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2302
2303 /* change these once we have scratch support */
2304 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2305 S_00B860_WAVES(pipeline->max_waves) |
2306 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2307
2308 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2309 radeon_emit(cmd_buffer->cs,
2310 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2311 radeon_emit(cmd_buffer->cs,
2312 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2313 radeon_emit(cmd_buffer->cs,
2314 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2315
2316 assert(cmd_buffer->cs->cdw <= cdw_max);
2317 }
2318
2319 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2320 {
2321 for (unsigned i = 0; i < MAX_SETS; i++) {
2322 if (cmd_buffer->state.descriptors[i])
2323 cmd_buffer->state.descriptors_dirty |= (1u << i);
2324 }
2325 }
2326
2327 void radv_CmdBindPipeline(
2328 VkCommandBuffer commandBuffer,
2329 VkPipelineBindPoint pipelineBindPoint,
2330 VkPipeline _pipeline)
2331 {
2332 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2333 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2334
2335 radv_mark_descriptor_sets_dirty(cmd_buffer);
2336
2337 switch (pipelineBindPoint) {
2338 case VK_PIPELINE_BIND_POINT_COMPUTE:
2339 cmd_buffer->state.compute_pipeline = pipeline;
2340 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2341 break;
2342 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2343 cmd_buffer->state.pipeline = pipeline;
2344 if (!pipeline)
2345 break;
2346
2347 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2348 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2349
2350 /* Apply the dynamic state from the pipeline */
2351 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2352 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2353 &pipeline->dynamic_state,
2354 pipeline->dynamic_state_mask);
2355
2356 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2357 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2358 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2359 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2360
2361 if (radv_pipeline_has_tess(pipeline))
2362 cmd_buffer->tess_rings_needed = true;
2363
2364 if (radv_pipeline_has_gs(pipeline)) {
2365 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2366 AC_UD_SCRATCH_RING_OFFSETS);
2367 if (cmd_buffer->ring_offsets_idx == -1)
2368 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2369 else if (loc->sgpr_idx != -1)
2370 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2371 }
2372 break;
2373 default:
2374 assert(!"invalid bind point");
2375 break;
2376 }
2377 }
2378
2379 void radv_CmdSetViewport(
2380 VkCommandBuffer commandBuffer,
2381 uint32_t firstViewport,
2382 uint32_t viewportCount,
2383 const VkViewport* pViewports)
2384 {
2385 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2386
2387 const uint32_t total_count = firstViewport + viewportCount;
2388 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2389 cmd_buffer->state.dynamic.viewport.count = total_count;
2390
2391 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2392 pViewports, viewportCount * sizeof(*pViewports));
2393
2394 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2395 }
2396
2397 void radv_CmdSetScissor(
2398 VkCommandBuffer commandBuffer,
2399 uint32_t firstScissor,
2400 uint32_t scissorCount,
2401 const VkRect2D* pScissors)
2402 {
2403 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2404
2405 const uint32_t total_count = firstScissor + scissorCount;
2406 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2407 cmd_buffer->state.dynamic.scissor.count = total_count;
2408
2409 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2410 pScissors, scissorCount * sizeof(*pScissors));
2411 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2412 }
2413
2414 void radv_CmdSetLineWidth(
2415 VkCommandBuffer commandBuffer,
2416 float lineWidth)
2417 {
2418 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2419 cmd_buffer->state.dynamic.line_width = lineWidth;
2420 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2421 }
2422
2423 void radv_CmdSetDepthBias(
2424 VkCommandBuffer commandBuffer,
2425 float depthBiasConstantFactor,
2426 float depthBiasClamp,
2427 float depthBiasSlopeFactor)
2428 {
2429 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2430
2431 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2432 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2433 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2434
2435 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2436 }
2437
2438 void radv_CmdSetBlendConstants(
2439 VkCommandBuffer commandBuffer,
2440 const float blendConstants[4])
2441 {
2442 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2443
2444 memcpy(cmd_buffer->state.dynamic.blend_constants,
2445 blendConstants, sizeof(float) * 4);
2446
2447 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2448 }
2449
2450 void radv_CmdSetDepthBounds(
2451 VkCommandBuffer commandBuffer,
2452 float minDepthBounds,
2453 float maxDepthBounds)
2454 {
2455 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2456
2457 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2458 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2459
2460 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2461 }
2462
2463 void radv_CmdSetStencilCompareMask(
2464 VkCommandBuffer commandBuffer,
2465 VkStencilFaceFlags faceMask,
2466 uint32_t compareMask)
2467 {
2468 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2469
2470 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2471 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2472 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2473 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2474
2475 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2476 }
2477
2478 void radv_CmdSetStencilWriteMask(
2479 VkCommandBuffer commandBuffer,
2480 VkStencilFaceFlags faceMask,
2481 uint32_t writeMask)
2482 {
2483 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2484
2485 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2486 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2487 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2488 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2489
2490 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2491 }
2492
2493 void radv_CmdSetStencilReference(
2494 VkCommandBuffer commandBuffer,
2495 VkStencilFaceFlags faceMask,
2496 uint32_t reference)
2497 {
2498 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2499
2500 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2501 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2502 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2503 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2504
2505 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2506 }
2507
2508 void radv_CmdExecuteCommands(
2509 VkCommandBuffer commandBuffer,
2510 uint32_t commandBufferCount,
2511 const VkCommandBuffer* pCmdBuffers)
2512 {
2513 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2514
2515 /* Emit pending flushes on primary prior to executing secondary */
2516 si_emit_cache_flush(primary);
2517
2518 for (uint32_t i = 0; i < commandBufferCount; i++) {
2519 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2520
2521 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2522 secondary->scratch_size_needed);
2523 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2524 secondary->compute_scratch_size_needed);
2525
2526 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2527 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2528 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2529 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2530 if (secondary->tess_rings_needed)
2531 primary->tess_rings_needed = true;
2532 if (secondary->sample_positions_needed)
2533 primary->sample_positions_needed = true;
2534
2535 if (secondary->ring_offsets_idx != -1) {
2536 if (primary->ring_offsets_idx == -1)
2537 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2538 else
2539 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2540 }
2541 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2542 }
2543
2544 /* if we execute secondary we need to re-emit out pipelines */
2545 if (commandBufferCount) {
2546 primary->state.emitted_pipeline = NULL;
2547 primary->state.emitted_compute_pipeline = NULL;
2548 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2549 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2550 primary->state.last_primitive_reset_en = -1;
2551 primary->state.last_primitive_reset_index = 0;
2552 radv_mark_descriptor_sets_dirty(primary);
2553 }
2554 }
2555
2556 VkResult radv_CreateCommandPool(
2557 VkDevice _device,
2558 const VkCommandPoolCreateInfo* pCreateInfo,
2559 const VkAllocationCallbacks* pAllocator,
2560 VkCommandPool* pCmdPool)
2561 {
2562 RADV_FROM_HANDLE(radv_device, device, _device);
2563 struct radv_cmd_pool *pool;
2564
2565 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2566 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2567 if (pool == NULL)
2568 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2569
2570 if (pAllocator)
2571 pool->alloc = *pAllocator;
2572 else
2573 pool->alloc = device->alloc;
2574
2575 list_inithead(&pool->cmd_buffers);
2576 list_inithead(&pool->free_cmd_buffers);
2577
2578 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2579
2580 *pCmdPool = radv_cmd_pool_to_handle(pool);
2581
2582 return VK_SUCCESS;
2583
2584 }
2585
2586 void radv_DestroyCommandPool(
2587 VkDevice _device,
2588 VkCommandPool commandPool,
2589 const VkAllocationCallbacks* pAllocator)
2590 {
2591 RADV_FROM_HANDLE(radv_device, device, _device);
2592 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2593
2594 if (!pool)
2595 return;
2596
2597 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2598 &pool->cmd_buffers, pool_link) {
2599 radv_cmd_buffer_destroy(cmd_buffer);
2600 }
2601
2602 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2603 &pool->free_cmd_buffers, pool_link) {
2604 radv_cmd_buffer_destroy(cmd_buffer);
2605 }
2606
2607 vk_free2(&device->alloc, pAllocator, pool);
2608 }
2609
2610 VkResult radv_ResetCommandPool(
2611 VkDevice device,
2612 VkCommandPool commandPool,
2613 VkCommandPoolResetFlags flags)
2614 {
2615 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2616
2617 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2618 &pool->cmd_buffers, pool_link) {
2619 radv_reset_cmd_buffer(cmd_buffer);
2620 }
2621
2622 return VK_SUCCESS;
2623 }
2624
2625 void radv_TrimCommandPoolKHR(
2626 VkDevice device,
2627 VkCommandPool commandPool,
2628 VkCommandPoolTrimFlagsKHR flags)
2629 {
2630 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2631
2632 if (!pool)
2633 return;
2634
2635 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2636 &pool->free_cmd_buffers, pool_link) {
2637 radv_cmd_buffer_destroy(cmd_buffer);
2638 }
2639 }
2640
2641 void radv_CmdBeginRenderPass(
2642 VkCommandBuffer commandBuffer,
2643 const VkRenderPassBeginInfo* pRenderPassBegin,
2644 VkSubpassContents contents)
2645 {
2646 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2647 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2648 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2649
2650 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2651 cmd_buffer->cs, 2048);
2652 MAYBE_UNUSED VkResult result;
2653
2654 cmd_buffer->state.framebuffer = framebuffer;
2655 cmd_buffer->state.pass = pass;
2656 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2657 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2658 if (result != VK_SUCCESS)
2659 cmd_buffer->record_result = result;
2660
2661 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2662 assert(cmd_buffer->cs->cdw <= cdw_max);
2663
2664 radv_cmd_buffer_clear_subpass(cmd_buffer);
2665 }
2666
2667 void radv_CmdNextSubpass(
2668 VkCommandBuffer commandBuffer,
2669 VkSubpassContents contents)
2670 {
2671 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2672
2673 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2674
2675 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2676 2048);
2677
2678 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2679 radv_cmd_buffer_clear_subpass(cmd_buffer);
2680 }
2681
2682 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2683 {
2684 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2685 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2686 if (!pipeline->shaders[stage])
2687 continue;
2688 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2689 if (loc->sgpr_idx == -1)
2690 continue;
2691 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2692 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2693
2694 }
2695 if (pipeline->gs_copy_shader) {
2696 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2697 if (loc->sgpr_idx != -1) {
2698 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2699 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2700 }
2701 }
2702 }
2703
2704 static void
2705 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2706 uint32_t vertex_count)
2707 {
2708 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2709 radeon_emit(cmd_buffer->cs, vertex_count);
2710 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2711 S_0287F0_USE_OPAQUE(0));
2712 }
2713
2714 void radv_CmdDraw(
2715 VkCommandBuffer commandBuffer,
2716 uint32_t vertexCount,
2717 uint32_t instanceCount,
2718 uint32_t firstVertex,
2719 uint32_t firstInstance)
2720 {
2721 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2722
2723 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2724
2725 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 20 * MAX_VIEWS);
2726
2727 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2728 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2729 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2730 radeon_emit(cmd_buffer->cs, firstVertex);
2731 radeon_emit(cmd_buffer->cs, firstInstance);
2732 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2733 radeon_emit(cmd_buffer->cs, 0);
2734
2735 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
2736 radeon_emit(cmd_buffer->cs, instanceCount);
2737
2738 if (!cmd_buffer->state.subpass->view_mask) {
2739 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2740 } else {
2741 unsigned i;
2742 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2743 radv_emit_view_index(cmd_buffer, i);
2744
2745 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2746 }
2747 }
2748
2749 assert(cmd_buffer->cs->cdw <= cdw_max);
2750
2751 radv_cmd_buffer_trace_emit(cmd_buffer);
2752 }
2753
2754
2755 static void
2756 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2757 uint64_t index_va,
2758 uint32_t index_count)
2759 {
2760 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2761 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2762 radeon_emit(cmd_buffer->cs, index_va);
2763 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2764 radeon_emit(cmd_buffer->cs, index_count);
2765 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2766 }
2767
2768 void radv_CmdDrawIndexed(
2769 VkCommandBuffer commandBuffer,
2770 uint32_t indexCount,
2771 uint32_t instanceCount,
2772 uint32_t firstIndex,
2773 int32_t vertexOffset,
2774 uint32_t firstInstance)
2775 {
2776 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2777 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2778 uint64_t index_va;
2779
2780 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2781
2782 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 26 * MAX_VIEWS);
2783
2784 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2785 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
2786 2, cmd_buffer->state.index_type);
2787 } else {
2788 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2789 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2790 }
2791
2792 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2793 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2794 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2795 radeon_emit(cmd_buffer->cs, vertexOffset);
2796 radeon_emit(cmd_buffer->cs, firstInstance);
2797 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2798 radeon_emit(cmd_buffer->cs, 0);
2799
2800 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2801 radeon_emit(cmd_buffer->cs, instanceCount);
2802
2803 index_va = cmd_buffer->state.index_va;
2804 index_va += firstIndex * index_size;
2805 if (!cmd_buffer->state.subpass->view_mask) {
2806 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2807 } else {
2808 unsigned i;
2809 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2810 radv_emit_view_index(cmd_buffer, i);
2811
2812 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2813 }
2814 }
2815
2816 assert(cmd_buffer->cs->cdw <= cdw_max);
2817 radv_cmd_buffer_trace_emit(cmd_buffer);
2818 }
2819
2820 static void
2821 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2822 bool indexed,
2823 uint32_t draw_count,
2824 uint64_t count_va,
2825 uint32_t stride)
2826 {
2827 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2828 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2829 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2830 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2831 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2832 assert(base_reg);
2833
2834 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2835 PKT3_DRAW_INDIRECT_MULTI,
2836 8, false));
2837 radeon_emit(cs, 0);
2838 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2839 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2840 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2841 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2842 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2843 radeon_emit(cs, draw_count); /* count */
2844 radeon_emit(cs, count_va); /* count_addr */
2845 radeon_emit(cs, count_va >> 32);
2846 radeon_emit(cs, stride); /* stride */
2847 radeon_emit(cs, di_src_sel);
2848 }
2849
2850 static void
2851 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2852 VkBuffer _buffer,
2853 VkDeviceSize offset,
2854 VkBuffer _count_buffer,
2855 VkDeviceSize count_offset,
2856 uint32_t draw_count,
2857 uint32_t stride,
2858 bool indexed)
2859 {
2860 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2861 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2862 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2863
2864 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2865 indirect_va += offset + buffer->offset;
2866 uint64_t count_va = 0;
2867
2868 if (count_buffer) {
2869 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2870 count_va += count_offset + count_buffer->offset;
2871 }
2872
2873 if (!draw_count)
2874 return;
2875
2876 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2877
2878 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2879 radeon_emit(cs, 1);
2880 radeon_emit(cs, indirect_va);
2881 radeon_emit(cs, indirect_va >> 32);
2882
2883 if (!cmd_buffer->state.subpass->view_mask) {
2884 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
2885 } else {
2886 unsigned i;
2887 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2888 radv_emit_view_index(cmd_buffer, i);
2889
2890 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
2891 }
2892 }
2893 radv_cmd_buffer_trace_emit(cmd_buffer);
2894 }
2895
2896 static void
2897 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2898 VkBuffer buffer,
2899 VkDeviceSize offset,
2900 VkBuffer countBuffer,
2901 VkDeviceSize countBufferOffset,
2902 uint32_t maxDrawCount,
2903 uint32_t stride)
2904 {
2905 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2906 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2907
2908 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2909 cmd_buffer->cs, 24 * MAX_VIEWS);
2910
2911 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2912 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2913
2914 assert(cmd_buffer->cs->cdw <= cdw_max);
2915 }
2916
2917 static void
2918 radv_cmd_draw_indexed_indirect_count(
2919 VkCommandBuffer commandBuffer,
2920 VkBuffer buffer,
2921 VkDeviceSize offset,
2922 VkBuffer countBuffer,
2923 VkDeviceSize countBufferOffset,
2924 uint32_t maxDrawCount,
2925 uint32_t stride)
2926 {
2927 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2928 uint64_t index_va;
2929 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2930
2931 index_va = cmd_buffer->state.index_va;
2932
2933 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 31 * MAX_VIEWS);
2934
2935 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2936 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2937
2938 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2939 radeon_emit(cmd_buffer->cs, index_va);
2940 radeon_emit(cmd_buffer->cs, index_va >> 32);
2941
2942 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2943 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2944
2945 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2946 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2947
2948 assert(cmd_buffer->cs->cdw <= cdw_max);
2949 }
2950
2951 void radv_CmdDrawIndirect(
2952 VkCommandBuffer commandBuffer,
2953 VkBuffer buffer,
2954 VkDeviceSize offset,
2955 uint32_t drawCount,
2956 uint32_t stride)
2957 {
2958 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2959 VK_NULL_HANDLE, 0, drawCount, stride);
2960 }
2961
2962 void radv_CmdDrawIndexedIndirect(
2963 VkCommandBuffer commandBuffer,
2964 VkBuffer buffer,
2965 VkDeviceSize offset,
2966 uint32_t drawCount,
2967 uint32_t stride)
2968 {
2969 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2970 VK_NULL_HANDLE, 0, drawCount, stride);
2971 }
2972
2973 void radv_CmdDrawIndirectCountAMD(
2974 VkCommandBuffer commandBuffer,
2975 VkBuffer buffer,
2976 VkDeviceSize offset,
2977 VkBuffer countBuffer,
2978 VkDeviceSize countBufferOffset,
2979 uint32_t maxDrawCount,
2980 uint32_t stride)
2981 {
2982 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2983 countBuffer, countBufferOffset,
2984 maxDrawCount, stride);
2985 }
2986
2987 void radv_CmdDrawIndexedIndirectCountAMD(
2988 VkCommandBuffer commandBuffer,
2989 VkBuffer buffer,
2990 VkDeviceSize offset,
2991 VkBuffer countBuffer,
2992 VkDeviceSize countBufferOffset,
2993 uint32_t maxDrawCount,
2994 uint32_t stride)
2995 {
2996 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2997 countBuffer, countBufferOffset,
2998 maxDrawCount, stride);
2999 }
3000
3001 static void
3002 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
3003 {
3004 radv_emit_compute_pipeline(cmd_buffer);
3005 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3006 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3007 VK_SHADER_STAGE_COMPUTE_BIT);
3008 si_emit_cache_flush(cmd_buffer);
3009 }
3010
3011 void radv_CmdDispatch(
3012 VkCommandBuffer commandBuffer,
3013 uint32_t x,
3014 uint32_t y,
3015 uint32_t z)
3016 {
3017 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3018
3019 radv_flush_compute_state(cmd_buffer);
3020
3021 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
3022
3023 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3024 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3025 if (loc->sgpr_idx != -1) {
3026 assert(!loc->indirect);
3027 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3028 assert(loc->num_sgprs == grid_used);
3029 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
3030 radeon_emit(cmd_buffer->cs, x);
3031 if (grid_used > 1)
3032 radeon_emit(cmd_buffer->cs, y);
3033 if (grid_used > 2)
3034 radeon_emit(cmd_buffer->cs, z);
3035 }
3036
3037 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3038 PKT3_SHADER_TYPE_S(1));
3039 radeon_emit(cmd_buffer->cs, x);
3040 radeon_emit(cmd_buffer->cs, y);
3041 radeon_emit(cmd_buffer->cs, z);
3042 radeon_emit(cmd_buffer->cs, 1);
3043
3044 assert(cmd_buffer->cs->cdw <= cdw_max);
3045 radv_cmd_buffer_trace_emit(cmd_buffer);
3046 }
3047
3048 void radv_CmdDispatchIndirect(
3049 VkCommandBuffer commandBuffer,
3050 VkBuffer _buffer,
3051 VkDeviceSize offset)
3052 {
3053 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3054 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3055 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
3056 va += buffer->offset + offset;
3057
3058 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
3059
3060 radv_flush_compute_state(cmd_buffer);
3061
3062 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
3063 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3064 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3065 if (loc->sgpr_idx != -1) {
3066 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3067 for (unsigned i = 0; i < grid_used; ++i) {
3068 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
3069 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3070 COPY_DATA_DST_SEL(COPY_DATA_REG));
3071 radeon_emit(cmd_buffer->cs, (va + 4 * i));
3072 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
3073 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
3074 radeon_emit(cmd_buffer->cs, 0);
3075 }
3076 }
3077
3078 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3079 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3080 PKT3_SHADER_TYPE_S(1));
3081 radeon_emit(cmd_buffer->cs, va);
3082 radeon_emit(cmd_buffer->cs, va >> 32);
3083 radeon_emit(cmd_buffer->cs, 1);
3084 } else {
3085 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
3086 PKT3_SHADER_TYPE_S(1));
3087 radeon_emit(cmd_buffer->cs, 1);
3088 radeon_emit(cmd_buffer->cs, va);
3089 radeon_emit(cmd_buffer->cs, va >> 32);
3090
3091 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3092 PKT3_SHADER_TYPE_S(1));
3093 radeon_emit(cmd_buffer->cs, 0);
3094 radeon_emit(cmd_buffer->cs, 1);
3095 }
3096
3097 assert(cmd_buffer->cs->cdw <= cdw_max);
3098 radv_cmd_buffer_trace_emit(cmd_buffer);
3099 }
3100
3101 void radv_unaligned_dispatch(
3102 struct radv_cmd_buffer *cmd_buffer,
3103 uint32_t x,
3104 uint32_t y,
3105 uint32_t z)
3106 {
3107 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3108 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3109 uint32_t blocks[3], remainder[3];
3110
3111 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
3112 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
3113 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
3114
3115 /* If aligned, these should be an entire block size, not 0 */
3116 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
3117 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
3118 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
3119
3120 radv_flush_compute_state(cmd_buffer);
3121
3122 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
3123
3124 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3125 radeon_emit(cmd_buffer->cs,
3126 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
3127 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3128 radeon_emit(cmd_buffer->cs,
3129 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
3130 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3131 radeon_emit(cmd_buffer->cs,
3132 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
3133 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3134
3135 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3136 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3137 if (loc->sgpr_idx != -1) {
3138 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3139 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
3140 radeon_emit(cmd_buffer->cs, blocks[0]);
3141 if (grid_used > 1)
3142 radeon_emit(cmd_buffer->cs, blocks[1]);
3143 if (grid_used > 2)
3144 radeon_emit(cmd_buffer->cs, blocks[2]);
3145 }
3146 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3147 PKT3_SHADER_TYPE_S(1));
3148 radeon_emit(cmd_buffer->cs, blocks[0]);
3149 radeon_emit(cmd_buffer->cs, blocks[1]);
3150 radeon_emit(cmd_buffer->cs, blocks[2]);
3151 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
3152 S_00B800_PARTIAL_TG_EN(1));
3153
3154 assert(cmd_buffer->cs->cdw <= cdw_max);
3155 radv_cmd_buffer_trace_emit(cmd_buffer);
3156 }
3157
3158 void radv_CmdEndRenderPass(
3159 VkCommandBuffer commandBuffer)
3160 {
3161 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3162
3163 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3164
3165 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3166
3167 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3168 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3169 radv_handle_subpass_image_transition(cmd_buffer,
3170 (VkAttachmentReference){i, layout});
3171 }
3172
3173 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3174
3175 cmd_buffer->state.pass = NULL;
3176 cmd_buffer->state.subpass = NULL;
3177 cmd_buffer->state.attachments = NULL;
3178 cmd_buffer->state.framebuffer = NULL;
3179 }
3180
3181 /*
3182 * For HTILE we have the following interesting clear words:
3183 * 0x0000030f: Uncompressed.
3184 * 0xfffffff0: Clear depth to 1.0
3185 * 0x00000000: Clear depth to 0.0
3186 */
3187 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3188 struct radv_image *image,
3189 const VkImageSubresourceRange *range,
3190 uint32_t clear_word)
3191 {
3192 assert(range->baseMipLevel == 0);
3193 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3194 unsigned layer_count = radv_get_layerCount(image, range);
3195 uint64_t size = image->surface.htile_slice_size * layer_count;
3196 uint64_t offset = image->offset + image->htile_offset +
3197 image->surface.htile_slice_size * range->baseArrayLayer;
3198
3199 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3200 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3201
3202 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3203
3204 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3205 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3206 RADV_CMD_FLAG_INV_VMEM_L1 |
3207 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3208 }
3209
3210 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3211 struct radv_image *image,
3212 VkImageLayout src_layout,
3213 VkImageLayout dst_layout,
3214 unsigned src_queue_mask,
3215 unsigned dst_queue_mask,
3216 const VkImageSubresourceRange *range,
3217 VkImageAspectFlags pending_clears)
3218 {
3219 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3220 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3221 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3222 cmd_buffer->state.render_area.extent.width == image->info.width &&
3223 cmd_buffer->state.render_area.extent.height == image->info.height) {
3224 /* The clear will initialize htile. */
3225 return;
3226 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3227 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3228 /* TODO: merge with the clear if applicable */
3229 radv_initialize_htile(cmd_buffer, image, range, 0);
3230 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3231 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3232 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3233 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3234 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3235 VkImageSubresourceRange local_range = *range;
3236 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3237 local_range.baseMipLevel = 0;
3238 local_range.levelCount = 1;
3239
3240 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3241 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3242
3243 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3244
3245 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3246 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3247 }
3248 }
3249
3250 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3251 struct radv_image *image, uint32_t value)
3252 {
3253 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3254 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3255
3256 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3257 image->cmask.size, value);
3258
3259 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3260 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3261 RADV_CMD_FLAG_INV_VMEM_L1 |
3262 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3263 }
3264
3265 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3266 struct radv_image *image,
3267 VkImageLayout src_layout,
3268 VkImageLayout dst_layout,
3269 unsigned src_queue_mask,
3270 unsigned dst_queue_mask,
3271 const VkImageSubresourceRange *range,
3272 VkImageAspectFlags pending_clears)
3273 {
3274 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3275 if (image->fmask.size)
3276 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3277 else
3278 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3279 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3280 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3281 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3282 }
3283 }
3284
3285 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3286 struct radv_image *image, uint32_t value)
3287 {
3288
3289 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3290 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3291
3292 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3293 image->surface.dcc_size, value);
3294
3295 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3296 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3297 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3298 RADV_CMD_FLAG_INV_VMEM_L1 |
3299 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3300 }
3301
3302 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3303 struct radv_image *image,
3304 VkImageLayout src_layout,
3305 VkImageLayout dst_layout,
3306 unsigned src_queue_mask,
3307 unsigned dst_queue_mask,
3308 const VkImageSubresourceRange *range,
3309 VkImageAspectFlags pending_clears)
3310 {
3311 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3312 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3313 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3314 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3315 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3316 }
3317 }
3318
3319 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3320 struct radv_image *image,
3321 VkImageLayout src_layout,
3322 VkImageLayout dst_layout,
3323 uint32_t src_family,
3324 uint32_t dst_family,
3325 const VkImageSubresourceRange *range,
3326 VkImageAspectFlags pending_clears)
3327 {
3328 if (image->exclusive && src_family != dst_family) {
3329 /* This is an acquire or a release operation and there will be
3330 * a corresponding release/acquire. Do the transition in the
3331 * most flexible queue. */
3332
3333 assert(src_family == cmd_buffer->queue_family_index ||
3334 dst_family == cmd_buffer->queue_family_index);
3335
3336 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3337 return;
3338
3339 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3340 (src_family == RADV_QUEUE_GENERAL ||
3341 dst_family == RADV_QUEUE_GENERAL))
3342 return;
3343 }
3344
3345 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3346 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3347
3348 if (image->surface.htile_size)
3349 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3350 dst_layout, src_queue_mask,
3351 dst_queue_mask, range,
3352 pending_clears);
3353
3354 if (image->cmask.size)
3355 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3356 dst_layout, src_queue_mask,
3357 dst_queue_mask, range,
3358 pending_clears);
3359
3360 if (image->surface.dcc_size)
3361 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3362 dst_layout, src_queue_mask,
3363 dst_queue_mask, range,
3364 pending_clears);
3365 }
3366
3367 void radv_CmdPipelineBarrier(
3368 VkCommandBuffer commandBuffer,
3369 VkPipelineStageFlags srcStageMask,
3370 VkPipelineStageFlags destStageMask,
3371 VkBool32 byRegion,
3372 uint32_t memoryBarrierCount,
3373 const VkMemoryBarrier* pMemoryBarriers,
3374 uint32_t bufferMemoryBarrierCount,
3375 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3376 uint32_t imageMemoryBarrierCount,
3377 const VkImageMemoryBarrier* pImageMemoryBarriers)
3378 {
3379 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3380 enum radv_cmd_flush_bits src_flush_bits = 0;
3381 enum radv_cmd_flush_bits dst_flush_bits = 0;
3382
3383 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3384 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3385 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3386 NULL);
3387 }
3388
3389 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3390 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3391 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3392 NULL);
3393 }
3394
3395 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3396 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3397 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3398 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3399 image);
3400 }
3401
3402 radv_stage_flush(cmd_buffer, srcStageMask);
3403 cmd_buffer->state.flush_bits |= src_flush_bits;
3404
3405 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3406 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3407 radv_handle_image_transition(cmd_buffer, image,
3408 pImageMemoryBarriers[i].oldLayout,
3409 pImageMemoryBarriers[i].newLayout,
3410 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3411 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3412 &pImageMemoryBarriers[i].subresourceRange,
3413 0);
3414 }
3415
3416 cmd_buffer->state.flush_bits |= dst_flush_bits;
3417 }
3418
3419
3420 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3421 struct radv_event *event,
3422 VkPipelineStageFlags stageMask,
3423 unsigned value)
3424 {
3425 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3426 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3427
3428 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3429
3430 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3431
3432 /* TODO: this is overkill. Probably should figure something out from
3433 * the stage mask. */
3434
3435 si_cs_emit_write_event_eop(cs,
3436 cmd_buffer->state.predicating,
3437 cmd_buffer->device->physical_device->rad_info.chip_class,
3438 false,
3439 EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
3440 1, va, 2, value);
3441
3442 assert(cmd_buffer->cs->cdw <= cdw_max);
3443 }
3444
3445 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3446 VkEvent _event,
3447 VkPipelineStageFlags stageMask)
3448 {
3449 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3450 RADV_FROM_HANDLE(radv_event, event, _event);
3451
3452 write_event(cmd_buffer, event, stageMask, 1);
3453 }
3454
3455 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3456 VkEvent _event,
3457 VkPipelineStageFlags stageMask)
3458 {
3459 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3460 RADV_FROM_HANDLE(radv_event, event, _event);
3461
3462 write_event(cmd_buffer, event, stageMask, 0);
3463 }
3464
3465 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3466 uint32_t eventCount,
3467 const VkEvent* pEvents,
3468 VkPipelineStageFlags srcStageMask,
3469 VkPipelineStageFlags dstStageMask,
3470 uint32_t memoryBarrierCount,
3471 const VkMemoryBarrier* pMemoryBarriers,
3472 uint32_t bufferMemoryBarrierCount,
3473 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3474 uint32_t imageMemoryBarrierCount,
3475 const VkImageMemoryBarrier* pImageMemoryBarriers)
3476 {
3477 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3478 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3479
3480 for (unsigned i = 0; i < eventCount; ++i) {
3481 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3482 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3483
3484 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3485
3486 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3487
3488 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3489 assert(cmd_buffer->cs->cdw <= cdw_max);
3490 }
3491
3492
3493 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3494 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3495
3496 radv_handle_image_transition(cmd_buffer, image,
3497 pImageMemoryBarriers[i].oldLayout,
3498 pImageMemoryBarriers[i].newLayout,
3499 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3500 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3501 &pImageMemoryBarriers[i].subresourceRange,
3502 0);
3503 }
3504
3505 /* TODO: figure out how to do memory barriers without waiting */
3506 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3507 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3508 RADV_CMD_FLAG_INV_VMEM_L1 |
3509 RADV_CMD_FLAG_INV_SMEM_L1;
3510 }