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radv: compute prim_vertex_count at draw time
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 .line_stipple = {
96 .factor = 0u,
97 .pattern = 0u,
98 },
99 };
100
101 static void
102 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
103 const struct radv_dynamic_state *src)
104 {
105 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
106 uint32_t copy_mask = src->mask;
107 uint32_t dest_mask = 0;
108
109 /* Make sure to copy the number of viewports/scissors because they can
110 * only be specified at pipeline creation time.
111 */
112 dest->viewport.count = src->viewport.count;
113 dest->scissor.count = src->scissor.count;
114 dest->discard_rectangle.count = src->discard_rectangle.count;
115 dest->sample_location.count = src->sample_location.count;
116
117 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
118 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
119 src->viewport.count * sizeof(VkViewport))) {
120 typed_memcpy(dest->viewport.viewports,
121 src->viewport.viewports,
122 src->viewport.count);
123 dest_mask |= RADV_DYNAMIC_VIEWPORT;
124 }
125 }
126
127 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
128 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
129 src->scissor.count * sizeof(VkRect2D))) {
130 typed_memcpy(dest->scissor.scissors,
131 src->scissor.scissors, src->scissor.count);
132 dest_mask |= RADV_DYNAMIC_SCISSOR;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
137 if (dest->line_width != src->line_width) {
138 dest->line_width = src->line_width;
139 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
144 if (memcmp(&dest->depth_bias, &src->depth_bias,
145 sizeof(src->depth_bias))) {
146 dest->depth_bias = src->depth_bias;
147 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
148 }
149 }
150
151 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
152 if (memcmp(&dest->blend_constants, &src->blend_constants,
153 sizeof(src->blend_constants))) {
154 typed_memcpy(dest->blend_constants,
155 src->blend_constants, 4);
156 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
161 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
162 sizeof(src->depth_bounds))) {
163 dest->depth_bounds = src->depth_bounds;
164 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
165 }
166 }
167
168 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
169 if (memcmp(&dest->stencil_compare_mask,
170 &src->stencil_compare_mask,
171 sizeof(src->stencil_compare_mask))) {
172 dest->stencil_compare_mask = src->stencil_compare_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
178 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
179 sizeof(src->stencil_write_mask))) {
180 dest->stencil_write_mask = src->stencil_write_mask;
181 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
186 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
187 sizeof(src->stencil_reference))) {
188 dest->stencil_reference = src->stencil_reference;
189 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
190 }
191 }
192
193 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
194 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
195 src->discard_rectangle.count * sizeof(VkRect2D))) {
196 typed_memcpy(dest->discard_rectangle.rectangles,
197 src->discard_rectangle.rectangles,
198 src->discard_rectangle.count);
199 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
200 }
201 }
202
203 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
204 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
205 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
206 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
207 memcmp(&dest->sample_location.locations,
208 &src->sample_location.locations,
209 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
210 dest->sample_location.per_pixel = src->sample_location.per_pixel;
211 dest->sample_location.grid_size = src->sample_location.grid_size;
212 typed_memcpy(dest->sample_location.locations,
213 src->sample_location.locations,
214 src->sample_location.count);
215 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
216 }
217 }
218
219 if (copy_mask & RADV_DYNAMIC_LINE_STIPPLE) {
220 if (memcmp(&dest->line_stipple, &src->line_stipple,
221 sizeof(src->line_stipple))) {
222 dest->line_stipple = src->line_stipple;
223 dest_mask |= RADV_DYNAMIC_LINE_STIPPLE;
224 }
225 }
226
227 cmd_buffer->state.dirty |= dest_mask;
228 }
229
230 static void
231 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
232 struct radv_pipeline *pipeline)
233 {
234 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
235 struct radv_shader_info *info;
236
237 if (!pipeline->streamout_shader ||
238 cmd_buffer->device->physical_device->use_ngg_streamout)
239 return;
240
241 info = &pipeline->streamout_shader->info;
242 for (int i = 0; i < MAX_SO_BUFFERS; i++)
243 so->stride_in_dw[i] = info->so.strides[i];
244
245 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
246 }
247
248 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
249 {
250 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
251 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
252 }
253
254 enum ring_type radv_queue_family_to_ring(int f) {
255 switch (f) {
256 case RADV_QUEUE_GENERAL:
257 return RING_GFX;
258 case RADV_QUEUE_COMPUTE:
259 return RING_COMPUTE;
260 case RADV_QUEUE_TRANSFER:
261 return RING_DMA;
262 default:
263 unreachable("Unknown queue family");
264 }
265 }
266
267 static VkResult radv_create_cmd_buffer(
268 struct radv_device * device,
269 struct radv_cmd_pool * pool,
270 VkCommandBufferLevel level,
271 VkCommandBuffer* pCommandBuffer)
272 {
273 struct radv_cmd_buffer *cmd_buffer;
274 unsigned ring;
275 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
276 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
277 if (cmd_buffer == NULL)
278 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
279
280 vk_object_base_init(&device->vk, &cmd_buffer->base,
281 VK_OBJECT_TYPE_COMMAND_BUFFER);
282
283 cmd_buffer->device = device;
284 cmd_buffer->pool = pool;
285 cmd_buffer->level = level;
286
287 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
288 cmd_buffer->queue_family_index = pool->queue_family_index;
289
290 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
291
292 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
293 if (!cmd_buffer->cs) {
294 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
295 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
296 }
297
298 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
299
300 list_inithead(&cmd_buffer->upload.list);
301
302 return VK_SUCCESS;
303 }
304
305 static void
306 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
307 {
308 list_del(&cmd_buffer->pool_link);
309
310 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
311 &cmd_buffer->upload.list, list) {
312 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
313 list_del(&up->list);
314 free(up);
315 }
316
317 if (cmd_buffer->upload.upload_bo)
318 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
319 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
320
321 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
322 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
323
324 vk_object_base_finish(&cmd_buffer->base);
325
326 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
327 }
328
329 static VkResult
330 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
331 {
332 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
333
334 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
335 &cmd_buffer->upload.list, list) {
336 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
337 list_del(&up->list);
338 free(up);
339 }
340
341 cmd_buffer->push_constant_stages = 0;
342 cmd_buffer->scratch_size_per_wave_needed = 0;
343 cmd_buffer->scratch_waves_wanted = 0;
344 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
345 cmd_buffer->compute_scratch_waves_wanted = 0;
346 cmd_buffer->esgs_ring_size_needed = 0;
347 cmd_buffer->gsvs_ring_size_needed = 0;
348 cmd_buffer->tess_rings_needed = false;
349 cmd_buffer->gds_needed = false;
350 cmd_buffer->gds_oa_needed = false;
351 cmd_buffer->sample_positions_needed = false;
352
353 if (cmd_buffer->upload.upload_bo)
354 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
355 cmd_buffer->upload.upload_bo);
356 cmd_buffer->upload.offset = 0;
357
358 cmd_buffer->record_result = VK_SUCCESS;
359
360 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
361
362 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
363 cmd_buffer->descriptors[i].dirty = 0;
364 cmd_buffer->descriptors[i].valid = 0;
365 cmd_buffer->descriptors[i].push_dirty = false;
366 }
367
368 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
369 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
370 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
371 unsigned fence_offset, eop_bug_offset;
372 void *fence_ptr;
373
374 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
375 &fence_ptr);
376
377 cmd_buffer->gfx9_fence_va =
378 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
379 cmd_buffer->gfx9_fence_va += fence_offset;
380
381 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
382 /* Allocate a buffer for the EOP bug on GFX9. */
383 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
384 &eop_bug_offset, &fence_ptr);
385 cmd_buffer->gfx9_eop_bug_va =
386 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
387 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
388 }
389 }
390
391 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
392
393 return cmd_buffer->record_result;
394 }
395
396 static bool
397 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
398 uint64_t min_needed)
399 {
400 uint64_t new_size;
401 struct radeon_winsys_bo *bo;
402 struct radv_cmd_buffer_upload *upload;
403 struct radv_device *device = cmd_buffer->device;
404
405 new_size = MAX2(min_needed, 16 * 1024);
406 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
407
408 bo = device->ws->buffer_create(device->ws,
409 new_size, 4096,
410 RADEON_DOMAIN_GTT,
411 RADEON_FLAG_CPU_ACCESS|
412 RADEON_FLAG_NO_INTERPROCESS_SHARING |
413 RADEON_FLAG_32BIT,
414 RADV_BO_PRIORITY_UPLOAD_BUFFER);
415
416 if (!bo) {
417 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
418 return false;
419 }
420
421 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
422 if (cmd_buffer->upload.upload_bo) {
423 upload = malloc(sizeof(*upload));
424
425 if (!upload) {
426 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
427 device->ws->buffer_destroy(bo);
428 return false;
429 }
430
431 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
432 list_add(&upload->list, &cmd_buffer->upload.list);
433 }
434
435 cmd_buffer->upload.upload_bo = bo;
436 cmd_buffer->upload.size = new_size;
437 cmd_buffer->upload.offset = 0;
438 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
439
440 if (!cmd_buffer->upload.map) {
441 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
442 return false;
443 }
444
445 return true;
446 }
447
448 bool
449 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
450 unsigned size,
451 unsigned alignment,
452 unsigned *out_offset,
453 void **ptr)
454 {
455 assert(util_is_power_of_two_nonzero(alignment));
456
457 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
458 if (offset + size > cmd_buffer->upload.size) {
459 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
460 return false;
461 offset = 0;
462 }
463
464 *out_offset = offset;
465 *ptr = cmd_buffer->upload.map + offset;
466
467 cmd_buffer->upload.offset = offset + size;
468 return true;
469 }
470
471 bool
472 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
473 unsigned size, unsigned alignment,
474 const void *data, unsigned *out_offset)
475 {
476 uint8_t *ptr;
477
478 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
479 out_offset, (void **)&ptr))
480 return false;
481
482 if (ptr)
483 memcpy(ptr, data, size);
484
485 return true;
486 }
487
488 static void
489 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
490 unsigned count, const uint32_t *data)
491 {
492 struct radeon_cmdbuf *cs = cmd_buffer->cs;
493
494 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
495
496 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
497 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
498 S_370_WR_CONFIRM(1) |
499 S_370_ENGINE_SEL(V_370_ME));
500 radeon_emit(cs, va);
501 radeon_emit(cs, va >> 32);
502 radeon_emit_array(cs, data, count);
503 }
504
505 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
506 {
507 struct radv_device *device = cmd_buffer->device;
508 struct radeon_cmdbuf *cs = cmd_buffer->cs;
509 uint64_t va;
510
511 va = radv_buffer_get_va(device->trace_bo);
512 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
513 va += 4;
514
515 ++cmd_buffer->state.trace_id;
516 radv_emit_write_data_packet(cmd_buffer, va, 1,
517 &cmd_buffer->state.trace_id);
518
519 radeon_check_space(cmd_buffer->device->ws, cs, 2);
520
521 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
522 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
523 }
524
525 static void
526 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
527 enum radv_cmd_flush_bits flags)
528 {
529 if (unlikely(cmd_buffer->device->thread_trace_bo)) {
530 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
531 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));
532 }
533
534 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
535 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
536 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
537
538 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
539
540 /* Force wait for graphics or compute engines to be idle. */
541 si_cs_emit_cache_flush(cmd_buffer->cs,
542 cmd_buffer->device->physical_device->rad_info.chip_class,
543 &cmd_buffer->gfx9_fence_idx,
544 cmd_buffer->gfx9_fence_va,
545 radv_cmd_buffer_uses_mec(cmd_buffer),
546 flags, cmd_buffer->gfx9_eop_bug_va);
547 }
548
549 if (unlikely(cmd_buffer->device->trace_bo))
550 radv_cmd_buffer_trace_emit(cmd_buffer);
551 }
552
553 static void
554 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
555 struct radv_pipeline *pipeline, enum ring_type ring)
556 {
557 struct radv_device *device = cmd_buffer->device;
558 uint32_t data[2];
559 uint64_t va;
560
561 va = radv_buffer_get_va(device->trace_bo);
562
563 switch (ring) {
564 case RING_GFX:
565 va += 8;
566 break;
567 case RING_COMPUTE:
568 va += 16;
569 break;
570 default:
571 assert(!"invalid ring type");
572 }
573
574 uint64_t pipeline_address = (uintptr_t)pipeline;
575 data[0] = pipeline_address;
576 data[1] = pipeline_address >> 32;
577
578 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
579 }
580
581 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
582 VkPipelineBindPoint bind_point,
583 struct radv_descriptor_set *set,
584 unsigned idx)
585 {
586 struct radv_descriptor_state *descriptors_state =
587 radv_get_descriptors_state(cmd_buffer, bind_point);
588
589 descriptors_state->sets[idx] = set;
590
591 descriptors_state->valid |= (1u << idx); /* active descriptors */
592 descriptors_state->dirty |= (1u << idx);
593 }
594
595 static void
596 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
597 VkPipelineBindPoint bind_point)
598 {
599 struct radv_descriptor_state *descriptors_state =
600 radv_get_descriptors_state(cmd_buffer, bind_point);
601 struct radv_device *device = cmd_buffer->device;
602 uint32_t data[MAX_SETS * 2] = {};
603 uint64_t va;
604 unsigned i;
605 va = radv_buffer_get_va(device->trace_bo) + 24;
606
607 for_each_bit(i, descriptors_state->valid) {
608 struct radv_descriptor_set *set = descriptors_state->sets[i];
609 data[i * 2] = (uint64_t)(uintptr_t)set;
610 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
611 }
612
613 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
614 }
615
616 struct radv_userdata_info *
617 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
618 gl_shader_stage stage,
619 int idx)
620 {
621 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
622 return &shader->info.user_sgprs_locs.shader_data[idx];
623 }
624
625 static void
626 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
627 struct radv_pipeline *pipeline,
628 gl_shader_stage stage,
629 int idx, uint64_t va)
630 {
631 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
632 uint32_t base_reg = pipeline->user_data_0[stage];
633 if (loc->sgpr_idx == -1)
634 return;
635
636 assert(loc->num_sgprs == 1);
637
638 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
639 base_reg + loc->sgpr_idx * 4, va, false);
640 }
641
642 static void
643 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
644 struct radv_pipeline *pipeline,
645 struct radv_descriptor_state *descriptors_state,
646 gl_shader_stage stage)
647 {
648 struct radv_device *device = cmd_buffer->device;
649 struct radeon_cmdbuf *cs = cmd_buffer->cs;
650 uint32_t sh_base = pipeline->user_data_0[stage];
651 struct radv_userdata_locations *locs =
652 &pipeline->shaders[stage]->info.user_sgprs_locs;
653 unsigned mask = locs->descriptor_sets_enabled;
654
655 mask &= descriptors_state->dirty & descriptors_state->valid;
656
657 while (mask) {
658 int start, count;
659
660 u_bit_scan_consecutive_range(&mask, &start, &count);
661
662 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
663 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
664
665 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
666 for (int i = 0; i < count; i++) {
667 struct radv_descriptor_set *set =
668 descriptors_state->sets[start + i];
669
670 radv_emit_shader_pointer_body(device, cs, set->va, true);
671 }
672 }
673 }
674
675 /**
676 * Convert the user sample locations to hardware sample locations (the values
677 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
678 */
679 static void
680 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
681 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
682 {
683 uint32_t x_offset = x % state->grid_size.width;
684 uint32_t y_offset = y % state->grid_size.height;
685 uint32_t num_samples = (uint32_t)state->per_pixel;
686 VkSampleLocationEXT *user_locs;
687 uint32_t pixel_offset;
688
689 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
690
691 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
692 user_locs = &state->locations[pixel_offset];
693
694 for (uint32_t i = 0; i < num_samples; i++) {
695 float shifted_pos_x = user_locs[i].x - 0.5;
696 float shifted_pos_y = user_locs[i].y - 0.5;
697
698 int32_t scaled_pos_x = floorf(shifted_pos_x * 16);
699 int32_t scaled_pos_y = floorf(shifted_pos_y * 16);
700
701 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
702 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
703 }
704 }
705
706 /**
707 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
708 * locations.
709 */
710 static void
711 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
712 uint32_t *sample_locs_pixel)
713 {
714 for (uint32_t i = 0; i < num_samples; i++) {
715 uint32_t sample_reg_idx = i / 4;
716 uint32_t sample_loc_idx = i % 4;
717 int32_t pos_x = sample_locs[i].x;
718 int32_t pos_y = sample_locs[i].y;
719
720 uint32_t shift_x = 8 * sample_loc_idx;
721 uint32_t shift_y = shift_x + 4;
722
723 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
724 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
725 }
726 }
727
728 /**
729 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
730 * sample locations.
731 */
732 static uint64_t
733 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
734 VkOffset2D *sample_locs,
735 uint32_t num_samples)
736 {
737 uint32_t centroid_priorities[num_samples];
738 uint32_t sample_mask = num_samples - 1;
739 uint32_t distances[num_samples];
740 uint64_t centroid_priority = 0;
741
742 /* Compute the distances from center for each sample. */
743 for (int i = 0; i < num_samples; i++) {
744 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
745 (sample_locs[i].y * sample_locs[i].y);
746 }
747
748 /* Compute the centroid priorities by looking at the distances array. */
749 for (int i = 0; i < num_samples; i++) {
750 uint32_t min_idx = 0;
751
752 for (int j = 1; j < num_samples; j++) {
753 if (distances[j] < distances[min_idx])
754 min_idx = j;
755 }
756
757 centroid_priorities[i] = min_idx;
758 distances[min_idx] = 0xffffffff;
759 }
760
761 /* Compute the final centroid priority. */
762 for (int i = 0; i < 8; i++) {
763 centroid_priority |=
764 centroid_priorities[i & sample_mask] << (i * 4);
765 }
766
767 return centroid_priority << 32 | centroid_priority;
768 }
769
770 /**
771 * Emit the sample locations that are specified with VK_EXT_sample_locations.
772 */
773 static void
774 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
775 {
776 struct radv_sample_locations_state *sample_location =
777 &cmd_buffer->state.dynamic.sample_location;
778 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
779 struct radeon_cmdbuf *cs = cmd_buffer->cs;
780 uint32_t sample_locs_pixel[4][2] = {};
781 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
782 uint32_t max_sample_dist = 0;
783 uint64_t centroid_priority;
784
785 if (!cmd_buffer->state.dynamic.sample_location.count)
786 return;
787
788 /* Convert the user sample locations to hardware sample locations. */
789 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
790 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
791 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
792 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
793
794 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
795 for (uint32_t i = 0; i < 4; i++) {
796 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
797 sample_locs_pixel[i]);
798 }
799
800 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
801 centroid_priority =
802 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
803 num_samples);
804
805 /* Compute the maximum sample distance from the specified locations. */
806 for (unsigned i = 0; i < 4; ++i) {
807 for (uint32_t j = 0; j < num_samples; j++) {
808 VkOffset2D offset = sample_locs[i][j];
809 max_sample_dist = MAX2(max_sample_dist,
810 MAX2(abs(offset.x), abs(offset.y)));
811 }
812 }
813
814 /* Emit the specified user sample locations. */
815 switch (num_samples) {
816 case 2:
817 case 4:
818 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
819 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
820 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
821 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
822 break;
823 case 8:
824 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
825 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
826 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
827 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
828 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
829 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
830 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
831 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
832 break;
833 default:
834 unreachable("invalid number of samples");
835 }
836
837 /* Emit the maximum sample distance and the centroid priority. */
838 radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
839 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist),
840 ~C_028BE0_MAX_SAMPLE_DIST);
841
842 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
843 radeon_emit(cs, centroid_priority);
844 radeon_emit(cs, centroid_priority >> 32);
845
846 /* GFX9: Flush DFSM when the AA mode changes. */
847 if (cmd_buffer->device->dfsm_allowed) {
848 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
849 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
850 }
851
852 cmd_buffer->state.context_roll_without_scissor_emitted = true;
853 }
854
855 static void
856 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
857 struct radv_pipeline *pipeline,
858 gl_shader_stage stage,
859 int idx, int count, uint32_t *values)
860 {
861 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
862 uint32_t base_reg = pipeline->user_data_0[stage];
863 if (loc->sgpr_idx == -1)
864 return;
865
866 assert(loc->num_sgprs == count);
867
868 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
869 radeon_emit_array(cmd_buffer->cs, values, count);
870 }
871
872 static void
873 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
874 struct radv_pipeline *pipeline)
875 {
876 int num_samples = pipeline->graphics.ms.num_samples;
877 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
878
879 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
880 cmd_buffer->sample_positions_needed = true;
881
882 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
883 return;
884
885 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
886
887 cmd_buffer->state.context_roll_without_scissor_emitted = true;
888 }
889
890 static void
891 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
892 struct radv_pipeline *pipeline)
893 {
894 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
895
896
897 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
898 return;
899
900 if (old_pipeline &&
901 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
902 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
903 return;
904
905 bool binning_flush = false;
906 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
907 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
908 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
909 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
910 binning_flush = !old_pipeline ||
911 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
912 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
913 }
914
915 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
916 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
917 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
918
919 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
920 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
921 pipeline->graphics.binning.db_dfsm_control);
922 } else {
923 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
924 pipeline->graphics.binning.db_dfsm_control);
925 }
926
927 cmd_buffer->state.context_roll_without_scissor_emitted = true;
928 }
929
930
931 static void
932 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
933 struct radv_shader_variant *shader)
934 {
935 uint64_t va;
936
937 if (!shader)
938 return;
939
940 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
941
942 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
943 }
944
945 static void
946 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
947 struct radv_pipeline *pipeline,
948 bool vertex_stage_only)
949 {
950 struct radv_cmd_state *state = &cmd_buffer->state;
951 uint32_t mask = state->prefetch_L2_mask;
952
953 if (vertex_stage_only) {
954 /* Fast prefetch path for starting draws as soon as possible.
955 */
956 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
957 RADV_PREFETCH_VBO_DESCRIPTORS);
958 }
959
960 if (mask & RADV_PREFETCH_VS)
961 radv_emit_shader_prefetch(cmd_buffer,
962 pipeline->shaders[MESA_SHADER_VERTEX]);
963
964 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
965 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
966
967 if (mask & RADV_PREFETCH_TCS)
968 radv_emit_shader_prefetch(cmd_buffer,
969 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
970
971 if (mask & RADV_PREFETCH_TES)
972 radv_emit_shader_prefetch(cmd_buffer,
973 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
974
975 if (mask & RADV_PREFETCH_GS) {
976 radv_emit_shader_prefetch(cmd_buffer,
977 pipeline->shaders[MESA_SHADER_GEOMETRY]);
978 if (radv_pipeline_has_gs_copy_shader(pipeline))
979 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
980 }
981
982 if (mask & RADV_PREFETCH_PS)
983 radv_emit_shader_prefetch(cmd_buffer,
984 pipeline->shaders[MESA_SHADER_FRAGMENT]);
985
986 state->prefetch_L2_mask &= ~mask;
987 }
988
989 static void
990 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
991 {
992 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
993 return;
994
995 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
996 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
997
998 unsigned sx_ps_downconvert = 0;
999 unsigned sx_blend_opt_epsilon = 0;
1000 unsigned sx_blend_opt_control = 0;
1001
1002 if (!cmd_buffer->state.attachments || !subpass)
1003 return;
1004
1005 for (unsigned i = 0; i < subpass->color_count; ++i) {
1006 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1007 /* We don't set the DISABLE bits, because the HW can't have holes,
1008 * so the SPI color format is set to 32-bit 1-component. */
1009 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1010 continue;
1011 }
1012
1013 int idx = subpass->color_attachments[i].attachment;
1014 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1015
1016 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1017 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1018 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1019 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1020
1021 bool has_alpha, has_rgb;
1022
1023 /* Set if RGB and A are present. */
1024 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1025
1026 if (format == V_028C70_COLOR_8 ||
1027 format == V_028C70_COLOR_16 ||
1028 format == V_028C70_COLOR_32)
1029 has_rgb = !has_alpha;
1030 else
1031 has_rgb = true;
1032
1033 /* Check the colormask and export format. */
1034 if (!(colormask & 0x7))
1035 has_rgb = false;
1036 if (!(colormask & 0x8))
1037 has_alpha = false;
1038
1039 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1040 has_rgb = false;
1041 has_alpha = false;
1042 }
1043
1044 /* Disable value checking for disabled channels. */
1045 if (!has_rgb)
1046 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1047 if (!has_alpha)
1048 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1049
1050 /* Enable down-conversion for 32bpp and smaller formats. */
1051 switch (format) {
1052 case V_028C70_COLOR_8:
1053 case V_028C70_COLOR_8_8:
1054 case V_028C70_COLOR_8_8_8_8:
1055 /* For 1 and 2-channel formats, use the superset thereof. */
1056 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1057 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1058 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1059 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1060 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1061 }
1062 break;
1063
1064 case V_028C70_COLOR_5_6_5:
1065 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1066 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1067 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1068 }
1069 break;
1070
1071 case V_028C70_COLOR_1_5_5_5:
1072 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1073 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1074 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1075 }
1076 break;
1077
1078 case V_028C70_COLOR_4_4_4_4:
1079 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1080 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1081 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1082 }
1083 break;
1084
1085 case V_028C70_COLOR_32:
1086 if (swap == V_028C70_SWAP_STD &&
1087 spi_format == V_028714_SPI_SHADER_32_R)
1088 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1089 else if (swap == V_028C70_SWAP_ALT_REV &&
1090 spi_format == V_028714_SPI_SHADER_32_AR)
1091 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1092 break;
1093
1094 case V_028C70_COLOR_16:
1095 case V_028C70_COLOR_16_16:
1096 /* For 1-channel formats, use the superset thereof. */
1097 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1098 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1099 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1100 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1101 if (swap == V_028C70_SWAP_STD ||
1102 swap == V_028C70_SWAP_STD_REV)
1103 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1104 else
1105 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1106 }
1107 break;
1108
1109 case V_028C70_COLOR_10_11_11:
1110 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1111 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1112 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1113 }
1114 break;
1115
1116 case V_028C70_COLOR_2_10_10_10:
1117 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1118 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1119 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1120 }
1121 break;
1122 }
1123 }
1124
1125 /* Do not set the DISABLE bits for the unused attachments, as that
1126 * breaks dual source blending in SkQP and does not seem to improve
1127 * performance. */
1128
1129 if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&
1130 sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&
1131 sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)
1132 return;
1133
1134 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1135 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1136 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1137 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1138
1139 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1140
1141 cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
1142 cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
1143 cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
1144 }
1145
1146 static void
1147 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
1148 {
1149 if (!cmd_buffer->device->pbb_allowed)
1150 return;
1151
1152 struct radv_binning_settings settings =
1153 radv_get_binning_settings(cmd_buffer->device->physical_device);
1154 bool break_for_new_ps =
1155 (!cmd_buffer->state.emitted_pipeline ||
1156 cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=
1157 cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
1158 (settings.context_states_per_bin > 1 ||
1159 settings.persistent_states_per_bin > 1);
1160 bool break_for_new_cb_target_mask =
1161 (!cmd_buffer->state.emitted_pipeline ||
1162 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1163 cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
1164 settings.context_states_per_bin > 1;
1165
1166 if (!break_for_new_ps && !break_for_new_cb_target_mask)
1167 return;
1168
1169 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1170 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1171 }
1172
1173 static void
1174 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1175 {
1176 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1177
1178 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1179 return;
1180
1181 radv_update_multisample_state(cmd_buffer, pipeline);
1182 radv_update_binning_state(cmd_buffer, pipeline);
1183
1184 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1185 pipeline->scratch_bytes_per_wave);
1186 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1187 pipeline->max_waves);
1188
1189 if (!cmd_buffer->state.emitted_pipeline ||
1190 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1191 pipeline->graphics.can_use_guardband)
1192 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1193
1194 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1195
1196 if (!cmd_buffer->state.emitted_pipeline ||
1197 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1198 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1199 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1200 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1201 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1202 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1203 }
1204
1205 radv_emit_batch_break_on_new_ps(cmd_buffer);
1206
1207 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1208 if (!pipeline->shaders[i])
1209 continue;
1210
1211 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1212 pipeline->shaders[i]->bo);
1213 }
1214
1215 if (radv_pipeline_has_gs_copy_shader(pipeline))
1216 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1217 pipeline->gs_copy_shader->bo);
1218
1219 if (unlikely(cmd_buffer->device->trace_bo))
1220 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1221
1222 cmd_buffer->state.emitted_pipeline = pipeline;
1223
1224 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1225 }
1226
1227 static void
1228 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1229 {
1230 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1231 cmd_buffer->state.dynamic.viewport.viewports);
1232 }
1233
1234 static void
1235 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1236 {
1237 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1238
1239 si_write_scissors(cmd_buffer->cs, 0, count,
1240 cmd_buffer->state.dynamic.scissor.scissors,
1241 cmd_buffer->state.dynamic.viewport.viewports,
1242 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1243
1244 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1245 }
1246
1247 static void
1248 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1249 {
1250 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1251 return;
1252
1253 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1254 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1255 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1256 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1257 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1258 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1259 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1260 }
1261 }
1262
1263 static void
1264 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1265 {
1266 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1267
1268 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1269 S_028A08_WIDTH(CLAMP(width, 0, 0xFFFF)));
1270 }
1271
1272 static void
1273 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1274 {
1275 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1276
1277 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1278 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1279 }
1280
1281 static void
1282 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1283 {
1284 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1285
1286 radeon_set_context_reg_seq(cmd_buffer->cs,
1287 R_028430_DB_STENCILREFMASK, 2);
1288 radeon_emit(cmd_buffer->cs,
1289 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1290 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1291 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1292 S_028430_STENCILOPVAL(1));
1293 radeon_emit(cmd_buffer->cs,
1294 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1295 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1296 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1297 S_028434_STENCILOPVAL_BF(1));
1298 }
1299
1300 static void
1301 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1302 {
1303 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1304
1305 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1306 fui(d->depth_bounds.min));
1307 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1308 fui(d->depth_bounds.max));
1309 }
1310
1311 static void
1312 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1313 {
1314 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1315 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1316 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1317
1318
1319 radeon_set_context_reg_seq(cmd_buffer->cs,
1320 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1321 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1322 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1323 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1324 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1325 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1326 }
1327
1328 static void
1329 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)
1330 {
1331 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1332 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1333 uint32_t auto_reset_cntl = 1;
1334
1335 if (pipeline->graphics.topology == V_008958_DI_PT_LINESTRIP)
1336 auto_reset_cntl = 2;
1337
1338 radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,
1339 S_028A0C_LINE_PATTERN(d->line_stipple.pattern) |
1340 S_028A0C_REPEAT_COUNT(d->line_stipple.factor - 1) |
1341 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl));
1342 }
1343
1344 static void
1345 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1346 int index,
1347 struct radv_color_buffer_info *cb,
1348 struct radv_image_view *iview,
1349 VkImageLayout layout,
1350 bool in_render_loop)
1351 {
1352 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1353 uint32_t cb_color_info = cb->cb_color_info;
1354 struct radv_image *image = iview->image;
1355
1356 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1357 radv_image_queue_family_mask(image,
1358 cmd_buffer->queue_family_index,
1359 cmd_buffer->queue_family_index))) {
1360 cb_color_info &= C_028C70_DCC_ENABLE;
1361 }
1362
1363 if (!radv_layout_can_fast_clear(image, layout, in_render_loop,
1364 radv_image_queue_family_mask(image,
1365 cmd_buffer->queue_family_index,
1366 cmd_buffer->queue_family_index))) {
1367 cb_color_info &= C_028C70_COMPRESSION;
1368 }
1369
1370 if (radv_image_is_tc_compat_cmask(image) &&
1371 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1372 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1373 /* If this bit is set, the FMASK decompression operation
1374 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1375 */
1376 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1377 }
1378
1379 if (radv_image_has_fmask(image) &&
1380 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1381 radv_is_hw_resolve_pipeline(cmd_buffer))) {
1382 /* Make sure FMASK is enabled if it has been cleared because:
1383 *
1384 * 1) it's required for FMASK_DECOMPRESS operations to avoid
1385 * GPU hangs
1386 * 2) it's necessary for CB_RESOLVE which can read compressed
1387 * FMASK data anyways.
1388 */
1389 cb_color_info |= S_028C70_COMPRESSION(1);
1390 }
1391
1392 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1393 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1394 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1395 radeon_emit(cmd_buffer->cs, 0);
1396 radeon_emit(cmd_buffer->cs, 0);
1397 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1398 radeon_emit(cmd_buffer->cs, cb_color_info);
1399 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1400 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1401 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1402 radeon_emit(cmd_buffer->cs, 0);
1403 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1404 radeon_emit(cmd_buffer->cs, 0);
1405
1406 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1407 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1408
1409 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1410 cb->cb_color_base >> 32);
1411 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1412 cb->cb_color_cmask >> 32);
1413 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1414 cb->cb_color_fmask >> 32);
1415 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1416 cb->cb_dcc_base >> 32);
1417 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1418 cb->cb_color_attrib2);
1419 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1420 cb->cb_color_attrib3);
1421 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1422 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1423 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1424 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1425 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1426 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1427 radeon_emit(cmd_buffer->cs, cb_color_info);
1428 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1429 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1430 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1431 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1432 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1433 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1434
1435 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1436 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1437 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1438
1439 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1440 cb->cb_mrt_epitch);
1441 } else {
1442 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1443 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1444 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1445 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1446 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1447 radeon_emit(cmd_buffer->cs, cb_color_info);
1448 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1449 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1450 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1451 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1452 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1453 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1454
1455 if (is_vi) { /* DCC BASE */
1456 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1457 }
1458 }
1459
1460 if (radv_dcc_enabled(image, iview->base_mip)) {
1461 /* Drawing with DCC enabled also compresses colorbuffers. */
1462 VkImageSubresourceRange range = {
1463 .aspectMask = iview->aspect_mask,
1464 .baseMipLevel = iview->base_mip,
1465 .levelCount = iview->level_count,
1466 .baseArrayLayer = iview->base_layer,
1467 .layerCount = iview->layer_count,
1468 };
1469
1470 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1471 }
1472 }
1473
1474 static void
1475 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1476 struct radv_ds_buffer_info *ds,
1477 const struct radv_image_view *iview,
1478 VkImageLayout layout,
1479 bool in_render_loop, bool requires_cond_exec)
1480 {
1481 const struct radv_image *image = iview->image;
1482 uint32_t db_z_info = ds->db_z_info;
1483 uint32_t db_z_info_reg;
1484
1485 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1486 !radv_image_is_tc_compat_htile(image))
1487 return;
1488
1489 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1490 radv_image_queue_family_mask(image,
1491 cmd_buffer->queue_family_index,
1492 cmd_buffer->queue_family_index))) {
1493 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1494 }
1495
1496 db_z_info &= C_028040_ZRANGE_PRECISION;
1497
1498 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1499 db_z_info_reg = R_028038_DB_Z_INFO;
1500 } else {
1501 db_z_info_reg = R_028040_DB_Z_INFO;
1502 }
1503
1504 /* When we don't know the last fast clear value we need to emit a
1505 * conditional packet that will eventually skip the following
1506 * SET_CONTEXT_REG packet.
1507 */
1508 if (requires_cond_exec) {
1509 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1510
1511 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1512 radeon_emit(cmd_buffer->cs, va);
1513 radeon_emit(cmd_buffer->cs, va >> 32);
1514 radeon_emit(cmd_buffer->cs, 0);
1515 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1516 }
1517
1518 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1519 }
1520
1521 static void
1522 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1523 struct radv_ds_buffer_info *ds,
1524 struct radv_image_view *iview,
1525 VkImageLayout layout,
1526 bool in_render_loop)
1527 {
1528 const struct radv_image *image = iview->image;
1529 uint32_t db_z_info = ds->db_z_info;
1530 uint32_t db_stencil_info = ds->db_stencil_info;
1531
1532 if (!radv_layout_is_htile_compressed(image, layout, in_render_loop,
1533 radv_image_queue_family_mask(image,
1534 cmd_buffer->queue_family_index,
1535 cmd_buffer->queue_family_index))) {
1536 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1537 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1538 }
1539
1540 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1541 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1542
1543 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1544 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1545 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1546
1547 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1548 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1549 radeon_emit(cmd_buffer->cs, db_z_info);
1550 radeon_emit(cmd_buffer->cs, db_stencil_info);
1551 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1552 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1553 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1554 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1555
1556 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1557 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1558 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1559 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1560 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1561 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1562 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1563 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1564 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1565 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1566 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1567
1568 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1569 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1570 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1571 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1572 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1573 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1574 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1575 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1576 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1577 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1578 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1579
1580 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1581 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1582 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1583 } else {
1584 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1585
1586 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1587 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1588 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1589 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1590 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1591 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1592 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1593 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1594 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1595 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1596
1597 }
1598
1599 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1600 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1601 in_render_loop, true);
1602
1603 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1604 ds->pa_su_poly_offset_db_fmt_cntl);
1605 }
1606
1607 /**
1608 * Update the fast clear depth/stencil values if the image is bound as a
1609 * depth/stencil buffer.
1610 */
1611 static void
1612 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1613 const struct radv_image_view *iview,
1614 VkClearDepthStencilValue ds_clear_value,
1615 VkImageAspectFlags aspects)
1616 {
1617 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1618 const struct radv_image *image = iview->image;
1619 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1620 uint32_t att_idx;
1621
1622 if (!cmd_buffer->state.attachments || !subpass)
1623 return;
1624
1625 if (!subpass->depth_stencil_attachment)
1626 return;
1627
1628 att_idx = subpass->depth_stencil_attachment->attachment;
1629 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1630 return;
1631
1632 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1633 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1634 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1635 radeon_emit(cs, ds_clear_value.stencil);
1636 radeon_emit(cs, fui(ds_clear_value.depth));
1637 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1638 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1639 radeon_emit(cs, fui(ds_clear_value.depth));
1640 } else {
1641 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1642 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1643 radeon_emit(cs, ds_clear_value.stencil);
1644 }
1645
1646 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1647 * only needed when clearing Z to 0.0.
1648 */
1649 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1650 ds_clear_value.depth == 0.0) {
1651 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1652 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1653
1654 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1655 iview, layout, in_render_loop, false);
1656 }
1657
1658 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1659 }
1660
1661 /**
1662 * Set the clear depth/stencil values to the image's metadata.
1663 */
1664 static void
1665 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1666 struct radv_image *image,
1667 const VkImageSubresourceRange *range,
1668 VkClearDepthStencilValue ds_clear_value,
1669 VkImageAspectFlags aspects)
1670 {
1671 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1672 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1673 uint32_t level_count = radv_get_levelCount(image, range);
1674
1675 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1676 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1677 /* Use the fastest way when both aspects are used. */
1678 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1679 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1680 S_370_WR_CONFIRM(1) |
1681 S_370_ENGINE_SEL(V_370_PFP));
1682 radeon_emit(cs, va);
1683 radeon_emit(cs, va >> 32);
1684
1685 for (uint32_t l = 0; l < level_count; l++) {
1686 radeon_emit(cs, ds_clear_value.stencil);
1687 radeon_emit(cs, fui(ds_clear_value.depth));
1688 }
1689 } else {
1690 /* Otherwise we need one WRITE_DATA packet per level. */
1691 for (uint32_t l = 0; l < level_count; l++) {
1692 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1693 unsigned value;
1694
1695 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1696 value = fui(ds_clear_value.depth);
1697 va += 4;
1698 } else {
1699 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1700 value = ds_clear_value.stencil;
1701 }
1702
1703 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1704 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1705 S_370_WR_CONFIRM(1) |
1706 S_370_ENGINE_SEL(V_370_PFP));
1707 radeon_emit(cs, va);
1708 radeon_emit(cs, va >> 32);
1709 radeon_emit(cs, value);
1710 }
1711 }
1712 }
1713
1714 /**
1715 * Update the TC-compat metadata value for this image.
1716 */
1717 static void
1718 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1719 struct radv_image *image,
1720 const VkImageSubresourceRange *range,
1721 uint32_t value)
1722 {
1723 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1724
1725 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1726 return;
1727
1728 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1729 uint32_t level_count = radv_get_levelCount(image, range);
1730
1731 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1732 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1733 S_370_WR_CONFIRM(1) |
1734 S_370_ENGINE_SEL(V_370_PFP));
1735 radeon_emit(cs, va);
1736 radeon_emit(cs, va >> 32);
1737
1738 for (uint32_t l = 0; l < level_count; l++)
1739 radeon_emit(cs, value);
1740 }
1741
1742 static void
1743 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1744 const struct radv_image_view *iview,
1745 VkClearDepthStencilValue ds_clear_value)
1746 {
1747 VkImageSubresourceRange range = {
1748 .aspectMask = iview->aspect_mask,
1749 .baseMipLevel = iview->base_mip,
1750 .levelCount = iview->level_count,
1751 .baseArrayLayer = iview->base_layer,
1752 .layerCount = iview->layer_count,
1753 };
1754 uint32_t cond_val;
1755
1756 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1757 * depth clear value is 0.0f.
1758 */
1759 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1760
1761 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1762 cond_val);
1763 }
1764
1765 /**
1766 * Update the clear depth/stencil values for this image.
1767 */
1768 void
1769 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1770 const struct radv_image_view *iview,
1771 VkClearDepthStencilValue ds_clear_value,
1772 VkImageAspectFlags aspects)
1773 {
1774 VkImageSubresourceRange range = {
1775 .aspectMask = iview->aspect_mask,
1776 .baseMipLevel = iview->base_mip,
1777 .levelCount = iview->level_count,
1778 .baseArrayLayer = iview->base_layer,
1779 .layerCount = iview->layer_count,
1780 };
1781 struct radv_image *image = iview->image;
1782
1783 assert(radv_image_has_htile(image));
1784
1785 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1786 ds_clear_value, aspects);
1787
1788 if (radv_image_is_tc_compat_htile(image) &&
1789 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1790 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1791 ds_clear_value);
1792 }
1793
1794 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1795 aspects);
1796 }
1797
1798 /**
1799 * Load the clear depth/stencil values from the image's metadata.
1800 */
1801 static void
1802 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1803 const struct radv_image_view *iview)
1804 {
1805 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1806 const struct radv_image *image = iview->image;
1807 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1808 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1809 unsigned reg_offset = 0, reg_count = 0;
1810
1811 if (!radv_image_has_htile(image))
1812 return;
1813
1814 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1815 ++reg_count;
1816 } else {
1817 ++reg_offset;
1818 va += 4;
1819 }
1820 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1821 ++reg_count;
1822
1823 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1824
1825 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1826 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
1827 radeon_emit(cs, va);
1828 radeon_emit(cs, va >> 32);
1829 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1830 radeon_emit(cs, reg_count);
1831 } else {
1832 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1833 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1834 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1835 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1836 radeon_emit(cs, va);
1837 radeon_emit(cs, va >> 32);
1838 radeon_emit(cs, reg >> 2);
1839 radeon_emit(cs, 0);
1840
1841 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1842 radeon_emit(cs, 0);
1843 }
1844 }
1845
1846 /*
1847 * With DCC some colors don't require CMASK elimination before being
1848 * used as a texture. This sets a predicate value to determine if the
1849 * cmask eliminate is required.
1850 */
1851 void
1852 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1853 struct radv_image *image,
1854 const VkImageSubresourceRange *range, bool value)
1855 {
1856 uint64_t pred_val = value;
1857 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1858 uint32_t level_count = radv_get_levelCount(image, range);
1859 uint32_t count = 2 * level_count;
1860
1861 assert(radv_dcc_enabled(image, range->baseMipLevel));
1862
1863 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1864 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1865 S_370_WR_CONFIRM(1) |
1866 S_370_ENGINE_SEL(V_370_PFP));
1867 radeon_emit(cmd_buffer->cs, va);
1868 radeon_emit(cmd_buffer->cs, va >> 32);
1869
1870 for (uint32_t l = 0; l < level_count; l++) {
1871 radeon_emit(cmd_buffer->cs, pred_val);
1872 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1873 }
1874 }
1875
1876 /**
1877 * Update the DCC predicate to reflect the compression state.
1878 */
1879 void
1880 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1881 struct radv_image *image,
1882 const VkImageSubresourceRange *range, bool value)
1883 {
1884 uint64_t pred_val = value;
1885 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1886 uint32_t level_count = radv_get_levelCount(image, range);
1887 uint32_t count = 2 * level_count;
1888
1889 assert(radv_dcc_enabled(image, range->baseMipLevel));
1890
1891 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1892 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1893 S_370_WR_CONFIRM(1) |
1894 S_370_ENGINE_SEL(V_370_PFP));
1895 radeon_emit(cmd_buffer->cs, va);
1896 radeon_emit(cmd_buffer->cs, va >> 32);
1897
1898 for (uint32_t l = 0; l < level_count; l++) {
1899 radeon_emit(cmd_buffer->cs, pred_val);
1900 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1901 }
1902 }
1903
1904 /**
1905 * Update the fast clear color values if the image is bound as a color buffer.
1906 */
1907 static void
1908 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1909 struct radv_image *image,
1910 int cb_idx,
1911 uint32_t color_values[2])
1912 {
1913 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1914 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1915 uint32_t att_idx;
1916
1917 if (!cmd_buffer->state.attachments || !subpass)
1918 return;
1919
1920 att_idx = subpass->color_attachments[cb_idx].attachment;
1921 if (att_idx == VK_ATTACHMENT_UNUSED)
1922 return;
1923
1924 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1925 return;
1926
1927 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1928 radeon_emit(cs, color_values[0]);
1929 radeon_emit(cs, color_values[1]);
1930
1931 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1932 }
1933
1934 /**
1935 * Set the clear color values to the image's metadata.
1936 */
1937 static void
1938 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1939 struct radv_image *image,
1940 const VkImageSubresourceRange *range,
1941 uint32_t color_values[2])
1942 {
1943 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1944 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1945 uint32_t level_count = radv_get_levelCount(image, range);
1946 uint32_t count = 2 * level_count;
1947
1948 assert(radv_image_has_cmask(image) ||
1949 radv_dcc_enabled(image, range->baseMipLevel));
1950
1951 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1952 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1953 S_370_WR_CONFIRM(1) |
1954 S_370_ENGINE_SEL(V_370_PFP));
1955 radeon_emit(cs, va);
1956 radeon_emit(cs, va >> 32);
1957
1958 for (uint32_t l = 0; l < level_count; l++) {
1959 radeon_emit(cs, color_values[0]);
1960 radeon_emit(cs, color_values[1]);
1961 }
1962 }
1963
1964 /**
1965 * Update the clear color values for this image.
1966 */
1967 void
1968 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1969 const struct radv_image_view *iview,
1970 int cb_idx,
1971 uint32_t color_values[2])
1972 {
1973 struct radv_image *image = iview->image;
1974 VkImageSubresourceRange range = {
1975 .aspectMask = iview->aspect_mask,
1976 .baseMipLevel = iview->base_mip,
1977 .levelCount = iview->level_count,
1978 .baseArrayLayer = iview->base_layer,
1979 .layerCount = iview->layer_count,
1980 };
1981
1982 assert(radv_image_has_cmask(image) ||
1983 radv_dcc_enabled(image, iview->base_mip));
1984
1985 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1986
1987 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1988 color_values);
1989 }
1990
1991 /**
1992 * Load the clear color values from the image's metadata.
1993 */
1994 static void
1995 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1996 struct radv_image_view *iview,
1997 int cb_idx)
1998 {
1999 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2000 struct radv_image *image = iview->image;
2001 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
2002
2003 if (!radv_image_has_cmask(image) &&
2004 !radv_dcc_enabled(image, iview->base_mip))
2005 return;
2006
2007 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
2008
2009 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
2010 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
2011 radeon_emit(cs, va);
2012 radeon_emit(cs, va >> 32);
2013 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
2014 radeon_emit(cs, 2);
2015 } else {
2016 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
2017 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2018 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2019 COPY_DATA_COUNT_SEL);
2020 radeon_emit(cs, va);
2021 radeon_emit(cs, va >> 32);
2022 radeon_emit(cs, reg >> 2);
2023 radeon_emit(cs, 0);
2024
2025 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
2026 radeon_emit(cs, 0);
2027 }
2028 }
2029
2030 static void
2031 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
2032 {
2033 int i;
2034 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
2035 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2036
2037 /* this may happen for inherited secondary recording */
2038 if (!framebuffer)
2039 return;
2040
2041 for (i = 0; i < 8; ++i) {
2042 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
2043 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2044 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2045 continue;
2046 }
2047
2048 int idx = subpass->color_attachments[i].attachment;
2049 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2050 VkImageLayout layout = subpass->color_attachments[i].layout;
2051 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
2052
2053 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
2054
2055 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
2056 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
2057 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
2058
2059 radv_load_color_clear_metadata(cmd_buffer, iview, i);
2060 }
2061
2062 if (subpass->depth_stencil_attachment) {
2063 int idx = subpass->depth_stencil_attachment->attachment;
2064 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
2065 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
2066 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
2067 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
2068
2069 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2070
2071 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2072 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2073 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2074 }
2075 radv_load_ds_clear_metadata(cmd_buffer, iview);
2076 } else {
2077 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2078 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2079 else
2080 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2081
2082 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2083 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2084 }
2085 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2086 S_028208_BR_X(framebuffer->width) |
2087 S_028208_BR_Y(framebuffer->height));
2088
2089 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2090 bool disable_constant_encode =
2091 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2092 enum chip_class chip_class =
2093 cmd_buffer->device->physical_device->rad_info.chip_class;
2094 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2095
2096 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2097 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2098 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2099 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2100 }
2101
2102 if (cmd_buffer->device->dfsm_allowed) {
2103 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2104 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2105 }
2106
2107 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2108 }
2109
2110 static void
2111 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
2112 {
2113 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2114 struct radv_cmd_state *state = &cmd_buffer->state;
2115
2116 if (state->index_type != state->last_index_type) {
2117 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2118 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2119 cs, R_03090C_VGT_INDEX_TYPE,
2120 2, state->index_type);
2121 } else {
2122 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2123 radeon_emit(cs, state->index_type);
2124 }
2125
2126 state->last_index_type = state->index_type;
2127 }
2128
2129 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2130 * the index_va and max_index_count already. */
2131 if (!indirect)
2132 return;
2133
2134 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2135 radeon_emit(cs, state->index_va);
2136 radeon_emit(cs, state->index_va >> 32);
2137
2138 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2139 radeon_emit(cs, state->max_index_count);
2140
2141 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2142 }
2143
2144 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2145 {
2146 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2147 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2148 uint32_t pa_sc_mode_cntl_1 =
2149 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2150 uint32_t db_count_control;
2151
2152 if(!cmd_buffer->state.active_occlusion_queries) {
2153 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2154 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2155 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2156 has_perfect_queries) {
2157 /* Re-enable out-of-order rasterization if the
2158 * bound pipeline supports it and if it's has
2159 * been disabled before starting any perfect
2160 * occlusion queries.
2161 */
2162 radeon_set_context_reg(cmd_buffer->cs,
2163 R_028A4C_PA_SC_MODE_CNTL_1,
2164 pa_sc_mode_cntl_1);
2165 }
2166 }
2167 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2168 } else {
2169 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2170 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2171 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2172
2173 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2174 /* Always enable PERFECT_ZPASS_COUNTS due to issues with partially
2175 * covered tiles, discards, and early depth testing. For more details,
2176 * see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218 */
2177 db_count_control =
2178 S_028004_PERFECT_ZPASS_COUNTS(1) |
2179 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2180 S_028004_SAMPLE_RATE(sample_rate) |
2181 S_028004_ZPASS_ENABLE(1) |
2182 S_028004_SLICE_EVEN_ENABLE(1) |
2183 S_028004_SLICE_ODD_ENABLE(1);
2184
2185 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2186 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2187 has_perfect_queries) {
2188 /* If the bound pipeline has enabled
2189 * out-of-order rasterization, we should
2190 * disable it before starting any perfect
2191 * occlusion queries.
2192 */
2193 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2194
2195 radeon_set_context_reg(cmd_buffer->cs,
2196 R_028A4C_PA_SC_MODE_CNTL_1,
2197 pa_sc_mode_cntl_1);
2198 }
2199 } else {
2200 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2201 S_028004_SAMPLE_RATE(sample_rate);
2202 }
2203 }
2204
2205 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2206
2207 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2208 }
2209
2210 static void
2211 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2212 {
2213 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2214
2215 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2216 radv_emit_viewport(cmd_buffer);
2217
2218 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2219 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2220 radv_emit_scissor(cmd_buffer);
2221
2222 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2223 radv_emit_line_width(cmd_buffer);
2224
2225 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2226 radv_emit_blend_constants(cmd_buffer);
2227
2228 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2229 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2230 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2231 radv_emit_stencil(cmd_buffer);
2232
2233 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2234 radv_emit_depth_bounds(cmd_buffer);
2235
2236 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2237 radv_emit_depth_bias(cmd_buffer);
2238
2239 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2240 radv_emit_discard_rectangle(cmd_buffer);
2241
2242 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2243 radv_emit_sample_locations(cmd_buffer);
2244
2245 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2246 radv_emit_line_stipple(cmd_buffer);
2247
2248 cmd_buffer->state.dirty &= ~states;
2249 }
2250
2251 static void
2252 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2253 VkPipelineBindPoint bind_point)
2254 {
2255 struct radv_descriptor_state *descriptors_state =
2256 radv_get_descriptors_state(cmd_buffer, bind_point);
2257 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2258 unsigned bo_offset;
2259
2260 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2261 set->mapped_ptr,
2262 &bo_offset))
2263 return;
2264
2265 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2266 set->va += bo_offset;
2267 }
2268
2269 static void
2270 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2271 VkPipelineBindPoint bind_point)
2272 {
2273 struct radv_descriptor_state *descriptors_state =
2274 radv_get_descriptors_state(cmd_buffer, bind_point);
2275 uint32_t size = MAX_SETS * 4;
2276 uint32_t offset;
2277 void *ptr;
2278
2279 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2280 256, &offset, &ptr))
2281 return;
2282
2283 for (unsigned i = 0; i < MAX_SETS; i++) {
2284 uint32_t *uptr = ((uint32_t *)ptr) + i;
2285 uint64_t set_va = 0;
2286 struct radv_descriptor_set *set = descriptors_state->sets[i];
2287 if (descriptors_state->valid & (1u << i))
2288 set_va = set->va;
2289 uptr[0] = set_va & 0xffffffff;
2290 }
2291
2292 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2293 va += offset;
2294
2295 if (cmd_buffer->state.pipeline) {
2296 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2297 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2298 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2299
2300 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2301 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2302 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2303
2304 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2305 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2306 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2307
2308 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2309 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2310 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2311
2312 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2313 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2314 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2315 }
2316
2317 if (cmd_buffer->state.compute_pipeline)
2318 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2319 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2320 }
2321
2322 static void
2323 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2324 VkShaderStageFlags stages)
2325 {
2326 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2327 VK_PIPELINE_BIND_POINT_COMPUTE :
2328 VK_PIPELINE_BIND_POINT_GRAPHICS;
2329 struct radv_descriptor_state *descriptors_state =
2330 radv_get_descriptors_state(cmd_buffer, bind_point);
2331 struct radv_cmd_state *state = &cmd_buffer->state;
2332 bool flush_indirect_descriptors;
2333
2334 if (!descriptors_state->dirty)
2335 return;
2336
2337 if (descriptors_state->push_dirty)
2338 radv_flush_push_descriptors(cmd_buffer, bind_point);
2339
2340 flush_indirect_descriptors =
2341 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2342 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2343 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2344 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2345
2346 if (flush_indirect_descriptors)
2347 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2348
2349 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2350 cmd_buffer->cs,
2351 MAX_SETS * MESA_SHADER_STAGES * 4);
2352
2353 if (cmd_buffer->state.pipeline) {
2354 radv_foreach_stage(stage, stages) {
2355 if (!cmd_buffer->state.pipeline->shaders[stage])
2356 continue;
2357
2358 radv_emit_descriptor_pointers(cmd_buffer,
2359 cmd_buffer->state.pipeline,
2360 descriptors_state, stage);
2361 }
2362 }
2363
2364 if (cmd_buffer->state.compute_pipeline &&
2365 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2366 radv_emit_descriptor_pointers(cmd_buffer,
2367 cmd_buffer->state.compute_pipeline,
2368 descriptors_state,
2369 MESA_SHADER_COMPUTE);
2370 }
2371
2372 descriptors_state->dirty = 0;
2373 descriptors_state->push_dirty = false;
2374
2375 assert(cmd_buffer->cs->cdw <= cdw_max);
2376
2377 if (unlikely(cmd_buffer->device->trace_bo))
2378 radv_save_descriptors(cmd_buffer, bind_point);
2379 }
2380
2381 static void
2382 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2383 VkShaderStageFlags stages)
2384 {
2385 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2386 ? cmd_buffer->state.compute_pipeline
2387 : cmd_buffer->state.pipeline;
2388 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2389 VK_PIPELINE_BIND_POINT_COMPUTE :
2390 VK_PIPELINE_BIND_POINT_GRAPHICS;
2391 struct radv_descriptor_state *descriptors_state =
2392 radv_get_descriptors_state(cmd_buffer, bind_point);
2393 struct radv_pipeline_layout *layout = pipeline->layout;
2394 struct radv_shader_variant *shader, *prev_shader;
2395 bool need_push_constants = false;
2396 unsigned offset;
2397 void *ptr;
2398 uint64_t va;
2399
2400 stages &= cmd_buffer->push_constant_stages;
2401 if (!stages ||
2402 (!layout->push_constant_size && !layout->dynamic_offset_count))
2403 return;
2404
2405 radv_foreach_stage(stage, stages) {
2406 shader = radv_get_shader(pipeline, stage);
2407 if (!shader)
2408 continue;
2409
2410 need_push_constants |= shader->info.loads_push_constants;
2411 need_push_constants |= shader->info.loads_dynamic_offsets;
2412
2413 uint8_t base = shader->info.base_inline_push_consts;
2414 uint8_t count = shader->info.num_inline_push_consts;
2415
2416 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2417 AC_UD_INLINE_PUSH_CONSTANTS,
2418 count,
2419 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2420 }
2421
2422 if (need_push_constants) {
2423 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2424 16 * layout->dynamic_offset_count,
2425 256, &offset, &ptr))
2426 return;
2427
2428 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2429 memcpy((char*)ptr + layout->push_constant_size,
2430 descriptors_state->dynamic_buffers,
2431 16 * layout->dynamic_offset_count);
2432
2433 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2434 va += offset;
2435
2436 ASSERTED unsigned cdw_max =
2437 radeon_check_space(cmd_buffer->device->ws,
2438 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2439
2440 prev_shader = NULL;
2441 radv_foreach_stage(stage, stages) {
2442 shader = radv_get_shader(pipeline, stage);
2443
2444 /* Avoid redundantly emitting the address for merged stages. */
2445 if (shader && shader != prev_shader) {
2446 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2447 AC_UD_PUSH_CONSTANTS, va);
2448
2449 prev_shader = shader;
2450 }
2451 }
2452 assert(cmd_buffer->cs->cdw <= cdw_max);
2453 }
2454
2455 cmd_buffer->push_constant_stages &= ~stages;
2456 }
2457
2458 static void
2459 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2460 bool pipeline_is_dirty)
2461 {
2462 if ((pipeline_is_dirty ||
2463 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2464 cmd_buffer->state.pipeline->num_vertex_bindings &&
2465 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2466 unsigned vb_offset;
2467 void *vb_ptr;
2468 uint32_t i = 0;
2469 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2470 uint64_t va;
2471
2472 /* allocate some descriptor state for vertex buffers */
2473 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2474 &vb_offset, &vb_ptr))
2475 return;
2476
2477 for (i = 0; i < count; i++) {
2478 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2479 uint32_t offset;
2480 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2481 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2482 unsigned num_records;
2483
2484 if (!buffer)
2485 continue;
2486
2487 va = radv_buffer_get_va(buffer->bo);
2488
2489 offset = cmd_buffer->vertex_bindings[i].offset;
2490 va += offset + buffer->offset;
2491
2492 num_records = buffer->size - offset;
2493 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2494 num_records /= stride;
2495
2496 desc[0] = va;
2497 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2498 desc[2] = num_records;
2499 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2500 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2501 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2502 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2503
2504 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2505 /* OOB_SELECT chooses the out-of-bounds check:
2506 * - 1: index >= NUM_RECORDS (Structured)
2507 * - 3: offset >= NUM_RECORDS (Raw)
2508 */
2509 int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
2510
2511 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2512 S_008F0C_OOB_SELECT(oob_select) |
2513 S_008F0C_RESOURCE_LEVEL(1);
2514 } else {
2515 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2516 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2517 }
2518 }
2519
2520 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2521 va += vb_offset;
2522
2523 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2524 AC_UD_VS_VERTEX_BUFFERS, va);
2525
2526 cmd_buffer->state.vb_va = va;
2527 cmd_buffer->state.vb_size = count * 16;
2528 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2529 }
2530 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2531 }
2532
2533 static void
2534 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2535 {
2536 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2537 struct radv_userdata_info *loc;
2538 uint32_t base_reg;
2539
2540 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2541 if (!radv_get_shader(pipeline, stage))
2542 continue;
2543
2544 loc = radv_lookup_user_sgpr(pipeline, stage,
2545 AC_UD_STREAMOUT_BUFFERS);
2546 if (loc->sgpr_idx == -1)
2547 continue;
2548
2549 base_reg = pipeline->user_data_0[stage];
2550
2551 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2552 base_reg + loc->sgpr_idx * 4, va, false);
2553 }
2554
2555 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2556 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2557 if (loc->sgpr_idx != -1) {
2558 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2559
2560 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2561 base_reg + loc->sgpr_idx * 4, va, false);
2562 }
2563 }
2564 }
2565
2566 static void
2567 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2568 {
2569 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2570 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2571 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2572 unsigned so_offset;
2573 void *so_ptr;
2574 uint64_t va;
2575
2576 /* Allocate some descriptor state for streamout buffers. */
2577 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2578 MAX_SO_BUFFERS * 16, 256,
2579 &so_offset, &so_ptr))
2580 return;
2581
2582 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2583 struct radv_buffer *buffer = sb[i].buffer;
2584 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2585
2586 if (!(so->enabled_mask & (1 << i)))
2587 continue;
2588
2589 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2590
2591 va += sb[i].offset;
2592
2593 /* Set the descriptor.
2594 *
2595 * On GFX8, the format must be non-INVALID, otherwise
2596 * the buffer will be considered not bound and store
2597 * instructions will be no-ops.
2598 */
2599 uint32_t size = 0xffffffff;
2600
2601 /* Compute the correct buffer size for NGG streamout
2602 * because it's used to determine the max emit per
2603 * buffer.
2604 */
2605 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2606 size = buffer->size - sb[i].offset;
2607
2608 desc[0] = va;
2609 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2610 desc[2] = size;
2611 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2612 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2613 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2614 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2615
2616 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2617 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2618 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
2619 S_008F0C_RESOURCE_LEVEL(1);
2620 } else {
2621 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2622 }
2623 }
2624
2625 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2626 va += so_offset;
2627
2628 radv_emit_streamout_buffers(cmd_buffer, va);
2629 }
2630
2631 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2632 }
2633
2634 static void
2635 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)
2636 {
2637 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2638 struct radv_userdata_info *loc;
2639 uint32_t ngg_gs_state = 0;
2640 uint32_t base_reg;
2641
2642 if (!radv_pipeline_has_gs(pipeline) ||
2643 !radv_pipeline_has_ngg(pipeline))
2644 return;
2645
2646 /* By default NGG GS queries are disabled but they are enabled if the
2647 * command buffer has active GDS queries or if it's a secondary command
2648 * buffer that inherits the number of generated primitives.
2649 */
2650 if (cmd_buffer->state.active_pipeline_gds_queries ||
2651 (cmd_buffer->state.inherited_pipeline_statistics & VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT))
2652 ngg_gs_state = 1;
2653
2654 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2655 AC_UD_NGG_GS_STATE);
2656 base_reg = pipeline->user_data_0[MESA_SHADER_GEOMETRY];
2657 assert(loc->sgpr_idx != -1);
2658
2659 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
2660 ngg_gs_state);
2661 }
2662
2663 static void
2664 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2665 {
2666 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2667 radv_flush_streamout_descriptors(cmd_buffer);
2668 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2669 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2670 radv_flush_ngg_gs_state(cmd_buffer);
2671 }
2672
2673 struct radv_draw_info {
2674 /**
2675 * Number of vertices.
2676 */
2677 uint32_t count;
2678
2679 /**
2680 * Index of the first vertex.
2681 */
2682 int32_t vertex_offset;
2683
2684 /**
2685 * First instance id.
2686 */
2687 uint32_t first_instance;
2688
2689 /**
2690 * Number of instances.
2691 */
2692 uint32_t instance_count;
2693
2694 /**
2695 * First index (indexed draws only).
2696 */
2697 uint32_t first_index;
2698
2699 /**
2700 * Whether it's an indexed draw.
2701 */
2702 bool indexed;
2703
2704 /**
2705 * Indirect draw parameters resource.
2706 */
2707 struct radv_buffer *indirect;
2708 uint64_t indirect_offset;
2709 uint32_t stride;
2710
2711 /**
2712 * Draw count parameters resource.
2713 */
2714 struct radv_buffer *count_buffer;
2715 uint64_t count_buffer_offset;
2716
2717 /**
2718 * Stream output parameters resource.
2719 */
2720 struct radv_buffer *strmout_buffer;
2721 uint64_t strmout_buffer_offset;
2722 };
2723
2724 static uint32_t
2725 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2726 {
2727 switch (cmd_buffer->state.index_type) {
2728 case V_028A7C_VGT_INDEX_8:
2729 return 0xffu;
2730 case V_028A7C_VGT_INDEX_16:
2731 return 0xffffu;
2732 case V_028A7C_VGT_INDEX_32:
2733 return 0xffffffffu;
2734 default:
2735 unreachable("invalid index type");
2736 }
2737 }
2738
2739 static void
2740 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2741 bool instanced_draw, bool indirect_draw,
2742 bool count_from_stream_output,
2743 uint32_t draw_vertex_count)
2744 {
2745 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2746 struct radv_cmd_state *state = &cmd_buffer->state;
2747 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2748 unsigned ia_multi_vgt_param;
2749
2750 ia_multi_vgt_param =
2751 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2752 indirect_draw,
2753 count_from_stream_output,
2754 draw_vertex_count);
2755
2756 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2757 if (info->chip_class == GFX9) {
2758 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2759 cs,
2760 R_030960_IA_MULTI_VGT_PARAM,
2761 4, ia_multi_vgt_param);
2762 } else if (info->chip_class >= GFX7) {
2763 radeon_set_context_reg_idx(cs,
2764 R_028AA8_IA_MULTI_VGT_PARAM,
2765 1, ia_multi_vgt_param);
2766 } else {
2767 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2768 ia_multi_vgt_param);
2769 }
2770 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2771 }
2772 }
2773
2774 static void
2775 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2776 const struct radv_draw_info *draw_info)
2777 {
2778 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2779 struct radv_cmd_state *state = &cmd_buffer->state;
2780 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2781 int32_t primitive_reset_en;
2782
2783 /* Draw state. */
2784 if (info->chip_class < GFX10) {
2785 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2786 draw_info->indirect,
2787 !!draw_info->strmout_buffer,
2788 draw_info->indirect ? 0 : draw_info->count);
2789 }
2790
2791 /* Primitive restart. */
2792 primitive_reset_en =
2793 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2794
2795 if (primitive_reset_en != state->last_primitive_reset_en) {
2796 state->last_primitive_reset_en = primitive_reset_en;
2797 if (info->chip_class >= GFX9) {
2798 radeon_set_uconfig_reg(cs,
2799 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2800 primitive_reset_en);
2801 } else {
2802 radeon_set_context_reg(cs,
2803 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2804 primitive_reset_en);
2805 }
2806 }
2807
2808 if (primitive_reset_en) {
2809 uint32_t primitive_reset_index =
2810 radv_get_primitive_reset_index(cmd_buffer);
2811
2812 if (primitive_reset_index != state->last_primitive_reset_index) {
2813 radeon_set_context_reg(cs,
2814 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2815 primitive_reset_index);
2816 state->last_primitive_reset_index = primitive_reset_index;
2817 }
2818 }
2819
2820 if (draw_info->strmout_buffer) {
2821 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2822
2823 va += draw_info->strmout_buffer->offset +
2824 draw_info->strmout_buffer_offset;
2825
2826 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2827 draw_info->stride);
2828
2829 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2830 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2831 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2832 COPY_DATA_WR_CONFIRM);
2833 radeon_emit(cs, va);
2834 radeon_emit(cs, va >> 32);
2835 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2836 radeon_emit(cs, 0); /* unused */
2837
2838 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2839 }
2840 }
2841
2842 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2843 VkPipelineStageFlags src_stage_mask)
2844 {
2845 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2846 VK_PIPELINE_STAGE_TRANSFER_BIT |
2847 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2848 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2849 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2850 }
2851
2852 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2853 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2854 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2855 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2856 VK_PIPELINE_STAGE_TRANSFER_BIT |
2857 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2858 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2859 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2860 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2861 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2862 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2863 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2864 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2865 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2866 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2867 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2868 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2869 }
2870 }
2871
2872 static enum radv_cmd_flush_bits
2873 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2874 VkAccessFlags src_flags,
2875 struct radv_image *image)
2876 {
2877 bool flush_CB_meta = true, flush_DB_meta = true;
2878 enum radv_cmd_flush_bits flush_bits = 0;
2879 uint32_t b;
2880
2881 if (image) {
2882 if (!radv_image_has_CB_metadata(image))
2883 flush_CB_meta = false;
2884 if (!radv_image_has_htile(image))
2885 flush_DB_meta = false;
2886 }
2887
2888 for_each_bit(b, src_flags) {
2889 switch ((VkAccessFlagBits)(1 << b)) {
2890 case VK_ACCESS_SHADER_WRITE_BIT:
2891 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2892 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2893 flush_bits |= RADV_CMD_FLAG_WB_L2;
2894 break;
2895 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2896 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2897 if (flush_CB_meta)
2898 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2899 break;
2900 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2901 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2902 if (flush_DB_meta)
2903 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2904 break;
2905 case VK_ACCESS_TRANSFER_WRITE_BIT:
2906 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2907 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2908 RADV_CMD_FLAG_INV_L2;
2909
2910 if (flush_CB_meta)
2911 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2912 if (flush_DB_meta)
2913 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2914 break;
2915 case VK_ACCESS_MEMORY_WRITE_BIT:
2916 flush_bits |= RADV_CMD_FLAG_INV_L2 |
2917 RADV_CMD_FLAG_WB_L2 |
2918 RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2919 RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2920
2921 if (flush_CB_meta)
2922 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2923 if (flush_DB_meta)
2924 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2925 break;
2926 default:
2927 break;
2928 }
2929 }
2930 return flush_bits;
2931 }
2932
2933 static enum radv_cmd_flush_bits
2934 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2935 VkAccessFlags dst_flags,
2936 struct radv_image *image)
2937 {
2938 bool flush_CB_meta = true, flush_DB_meta = true;
2939 enum radv_cmd_flush_bits flush_bits = 0;
2940 bool flush_CB = true, flush_DB = true;
2941 bool image_is_coherent = false;
2942 uint32_t b;
2943
2944 if (image) {
2945 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2946 flush_CB = false;
2947 flush_DB = false;
2948 }
2949
2950 if (!radv_image_has_CB_metadata(image))
2951 flush_CB_meta = false;
2952 if (!radv_image_has_htile(image))
2953 flush_DB_meta = false;
2954
2955 /* TODO: implement shader coherent for GFX10 */
2956
2957 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2958 if (image->info.samples == 1 &&
2959 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2960 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2961 !vk_format_is_stencil(image->vk_format)) {
2962 /* Single-sample color and single-sample depth
2963 * (not stencil) are coherent with shaders on
2964 * GFX9.
2965 */
2966 image_is_coherent = true;
2967 }
2968 }
2969 }
2970
2971 for_each_bit(b, dst_flags) {
2972 switch ((VkAccessFlagBits)(1 << b)) {
2973 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2974 case VK_ACCESS_INDEX_READ_BIT:
2975 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2976 break;
2977 case VK_ACCESS_UNIFORM_READ_BIT:
2978 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2979 break;
2980 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2981 case VK_ACCESS_TRANSFER_READ_BIT:
2982 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2983 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2984 RADV_CMD_FLAG_INV_L2;
2985 break;
2986 case VK_ACCESS_SHADER_READ_BIT:
2987 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2988 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2989 * invalidate the scalar cache. */
2990 if (!cmd_buffer->device->physical_device->use_llvm)
2991 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2992
2993 if (!image_is_coherent)
2994 flush_bits |= RADV_CMD_FLAG_INV_L2;
2995 break;
2996 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2997 if (flush_CB)
2998 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2999 if (flush_CB_meta)
3000 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3001 break;
3002 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
3003 if (flush_DB)
3004 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3005 if (flush_DB_meta)
3006 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3007 break;
3008 case VK_ACCESS_MEMORY_READ_BIT:
3009 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
3010 RADV_CMD_FLAG_INV_SCACHE |
3011 RADV_CMD_FLAG_INV_L2;
3012 if (flush_CB)
3013 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
3014 if (flush_CB_meta)
3015 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3016 if (flush_DB)
3017 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
3018 if (flush_DB_meta)
3019 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3020 break;
3021 default:
3022 break;
3023 }
3024 }
3025 return flush_bits;
3026 }
3027
3028 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
3029 const struct radv_subpass_barrier *barrier)
3030 {
3031 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
3032 NULL);
3033 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
3034 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
3035 NULL);
3036 }
3037
3038 uint32_t
3039 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3040 {
3041 struct radv_cmd_state *state = &cmd_buffer->state;
3042 uint32_t subpass_id = state->subpass - state->pass->subpasses;
3043
3044 /* The id of this subpass shouldn't exceed the number of subpasses in
3045 * this render pass minus 1.
3046 */
3047 assert(subpass_id < state->pass->subpass_count);
3048 return subpass_id;
3049 }
3050
3051 static struct radv_sample_locations_state *
3052 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3053 uint32_t att_idx,
3054 bool begin_subpass)
3055 {
3056 struct radv_cmd_state *state = &cmd_buffer->state;
3057 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3058 struct radv_image_view *view = state->attachments[att_idx].iview;
3059
3060 if (view->image->info.samples == 1)
3061 return NULL;
3062
3063 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
3064 /* Return the initial sample locations if this is the initial
3065 * layout transition of the given subpass attachemnt.
3066 */
3067 if (state->attachments[att_idx].sample_location.count > 0)
3068 return &state->attachments[att_idx].sample_location;
3069 } else {
3070 /* Otherwise return the subpass sample locations if defined. */
3071 if (state->subpass_sample_locs) {
3072 /* Because the driver sets the current subpass before
3073 * initial layout transitions, we should use the sample
3074 * locations from the previous subpass to avoid an
3075 * off-by-one problem. Otherwise, use the sample
3076 * locations for the current subpass for final layout
3077 * transitions.
3078 */
3079 if (begin_subpass)
3080 subpass_id--;
3081
3082 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
3083 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
3084 return &state->subpass_sample_locs[i].sample_location;
3085 }
3086 }
3087 }
3088
3089 return NULL;
3090 }
3091
3092 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
3093 struct radv_subpass_attachment att,
3094 bool begin_subpass)
3095 {
3096 unsigned idx = att.attachment;
3097 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
3098 struct radv_sample_locations_state *sample_locs;
3099 VkImageSubresourceRange range;
3100 range.aspectMask = view->aspect_mask;
3101 range.baseMipLevel = view->base_mip;
3102 range.levelCount = 1;
3103 range.baseArrayLayer = view->base_layer;
3104 range.layerCount = cmd_buffer->state.framebuffer->layers;
3105
3106 if (cmd_buffer->state.subpass->view_mask) {
3107 /* If the current subpass uses multiview, the driver might have
3108 * performed a fast color/depth clear to the whole image
3109 * (including all layers). To make sure the driver will
3110 * decompress the image correctly (if needed), we have to
3111 * account for the "real" number of layers. If the view mask is
3112 * sparse, this will decompress more layers than needed.
3113 */
3114 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
3115 }
3116
3117 /* Get the subpass sample locations for the given attachment, if NULL
3118 * is returned the driver will use the default HW locations.
3119 */
3120 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
3121 begin_subpass);
3122
3123 /* Determine if the subpass uses separate depth/stencil layouts. */
3124 bool uses_separate_depth_stencil_layouts = false;
3125 if ((cmd_buffer->state.attachments[idx].current_layout !=
3126 cmd_buffer->state.attachments[idx].current_stencil_layout) ||
3127 (att.layout != att.stencil_layout)) {
3128 uses_separate_depth_stencil_layouts = true;
3129 }
3130
3131 /* For separate layouts, perform depth and stencil transitions
3132 * separately.
3133 */
3134 if (uses_separate_depth_stencil_layouts &&
3135 (range.aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT |
3136 VK_IMAGE_ASPECT_STENCIL_BIT))) {
3137 /* Depth-only transitions. */
3138 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3139 radv_handle_image_transition(cmd_buffer,
3140 view->image,
3141 cmd_buffer->state.attachments[idx].current_layout,
3142 cmd_buffer->state.attachments[idx].current_in_render_loop,
3143 att.layout, att.in_render_loop,
3144 0, 0, &range, sample_locs);
3145
3146 /* Stencil-only transitions. */
3147 range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT;
3148 radv_handle_image_transition(cmd_buffer,
3149 view->image,
3150 cmd_buffer->state.attachments[idx].current_stencil_layout,
3151 cmd_buffer->state.attachments[idx].current_in_render_loop,
3152 att.stencil_layout, att.in_render_loop,
3153 0, 0, &range, sample_locs);
3154 } else {
3155 radv_handle_image_transition(cmd_buffer,
3156 view->image,
3157 cmd_buffer->state.attachments[idx].current_layout,
3158 cmd_buffer->state.attachments[idx].current_in_render_loop,
3159 att.layout, att.in_render_loop,
3160 0, 0, &range, sample_locs);
3161 }
3162
3163 cmd_buffer->state.attachments[idx].current_layout = att.layout;
3164 cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;
3165 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
3166
3167
3168 }
3169
3170 void
3171 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3172 const struct radv_subpass *subpass)
3173 {
3174 cmd_buffer->state.subpass = subpass;
3175
3176 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3177 }
3178
3179 static VkResult
3180 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3181 struct radv_render_pass *pass,
3182 const VkRenderPassBeginInfo *info)
3183 {
3184 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3185 vk_find_struct_const(info->pNext,
3186 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3187 struct radv_cmd_state *state = &cmd_buffer->state;
3188
3189 if (!sample_locs) {
3190 state->subpass_sample_locs = NULL;
3191 return VK_SUCCESS;
3192 }
3193
3194 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3195 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3196 &sample_locs->pAttachmentInitialSampleLocations[i];
3197 uint32_t att_idx = att_sample_locs->attachmentIndex;
3198 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3199
3200 assert(vk_format_is_depth_or_stencil(image->vk_format));
3201
3202 /* From the Vulkan spec 1.1.108:
3203 *
3204 * "If the image referenced by the framebuffer attachment at
3205 * index attachmentIndex was not created with
3206 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3207 * then the values specified in sampleLocationsInfo are
3208 * ignored."
3209 */
3210 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3211 continue;
3212
3213 const VkSampleLocationsInfoEXT *sample_locs_info =
3214 &att_sample_locs->sampleLocationsInfo;
3215
3216 state->attachments[att_idx].sample_location.per_pixel =
3217 sample_locs_info->sampleLocationsPerPixel;
3218 state->attachments[att_idx].sample_location.grid_size =
3219 sample_locs_info->sampleLocationGridSize;
3220 state->attachments[att_idx].sample_location.count =
3221 sample_locs_info->sampleLocationsCount;
3222 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3223 sample_locs_info->pSampleLocations,
3224 sample_locs_info->sampleLocationsCount);
3225 }
3226
3227 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3228 sample_locs->postSubpassSampleLocationsCount *
3229 sizeof(state->subpass_sample_locs[0]),
3230 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3231 if (state->subpass_sample_locs == NULL) {
3232 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3233 return cmd_buffer->record_result;
3234 }
3235
3236 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3237
3238 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3239 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3240 &sample_locs->pPostSubpassSampleLocations[i];
3241 const VkSampleLocationsInfoEXT *sample_locs_info =
3242 &subpass_sample_locs_info->sampleLocationsInfo;
3243
3244 state->subpass_sample_locs[i].subpass_idx =
3245 subpass_sample_locs_info->subpassIndex;
3246 state->subpass_sample_locs[i].sample_location.per_pixel =
3247 sample_locs_info->sampleLocationsPerPixel;
3248 state->subpass_sample_locs[i].sample_location.grid_size =
3249 sample_locs_info->sampleLocationGridSize;
3250 state->subpass_sample_locs[i].sample_location.count =
3251 sample_locs_info->sampleLocationsCount;
3252 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3253 sample_locs_info->pSampleLocations,
3254 sample_locs_info->sampleLocationsCount);
3255 }
3256
3257 return VK_SUCCESS;
3258 }
3259
3260 static VkResult
3261 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3262 struct radv_render_pass *pass,
3263 const VkRenderPassBeginInfo *info)
3264 {
3265 struct radv_cmd_state *state = &cmd_buffer->state;
3266 const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
3267
3268 if (info) {
3269 attachment_info = vk_find_struct_const(info->pNext,
3270 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3271 }
3272
3273
3274 if (pass->attachment_count == 0) {
3275 state->attachments = NULL;
3276 return VK_SUCCESS;
3277 }
3278
3279 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3280 pass->attachment_count *
3281 sizeof(state->attachments[0]),
3282 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3283 if (state->attachments == NULL) {
3284 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3285 return cmd_buffer->record_result;
3286 }
3287
3288 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3289 struct radv_render_pass_attachment *att = &pass->attachments[i];
3290 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3291 VkImageAspectFlags clear_aspects = 0;
3292
3293 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3294 /* color attachment */
3295 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3296 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3297 }
3298 } else {
3299 /* depthstencil attachment */
3300 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3301 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3302 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3303 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3304 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3305 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3306 }
3307 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3308 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3309 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3310 }
3311 }
3312
3313 state->attachments[i].pending_clear_aspects = clear_aspects;
3314 state->attachments[i].cleared_views = 0;
3315 if (clear_aspects && info) {
3316 assert(info->clearValueCount > i);
3317 state->attachments[i].clear_value = info->pClearValues[i];
3318 }
3319
3320 state->attachments[i].current_layout = att->initial_layout;
3321 state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
3322 state->attachments[i].sample_location.count = 0;
3323
3324 struct radv_image_view *iview;
3325 if (attachment_info && attachment_info->attachmentCount > i) {
3326 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3327 } else {
3328 iview = state->framebuffer->attachments[i];
3329 }
3330
3331 state->attachments[i].iview = iview;
3332 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3333 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3334 } else {
3335 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3336 }
3337 }
3338
3339 return VK_SUCCESS;
3340 }
3341
3342 VkResult radv_AllocateCommandBuffers(
3343 VkDevice _device,
3344 const VkCommandBufferAllocateInfo *pAllocateInfo,
3345 VkCommandBuffer *pCommandBuffers)
3346 {
3347 RADV_FROM_HANDLE(radv_device, device, _device);
3348 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3349
3350 VkResult result = VK_SUCCESS;
3351 uint32_t i;
3352
3353 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3354
3355 if (!list_is_empty(&pool->free_cmd_buffers)) {
3356 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3357
3358 list_del(&cmd_buffer->pool_link);
3359 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3360
3361 result = radv_reset_cmd_buffer(cmd_buffer);
3362 cmd_buffer->level = pAllocateInfo->level;
3363
3364 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3365 } else {
3366 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3367 &pCommandBuffers[i]);
3368 }
3369 if (result != VK_SUCCESS)
3370 break;
3371 }
3372
3373 if (result != VK_SUCCESS) {
3374 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3375 i, pCommandBuffers);
3376
3377 /* From the Vulkan 1.0.66 spec:
3378 *
3379 * "vkAllocateCommandBuffers can be used to create multiple
3380 * command buffers. If the creation of any of those command
3381 * buffers fails, the implementation must destroy all
3382 * successfully created command buffer objects from this
3383 * command, set all entries of the pCommandBuffers array to
3384 * NULL and return the error."
3385 */
3386 memset(pCommandBuffers, 0,
3387 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3388 }
3389
3390 return result;
3391 }
3392
3393 void radv_FreeCommandBuffers(
3394 VkDevice device,
3395 VkCommandPool commandPool,
3396 uint32_t commandBufferCount,
3397 const VkCommandBuffer *pCommandBuffers)
3398 {
3399 for (uint32_t i = 0; i < commandBufferCount; i++) {
3400 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3401
3402 if (cmd_buffer) {
3403 if (cmd_buffer->pool) {
3404 list_del(&cmd_buffer->pool_link);
3405 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3406 } else
3407 radv_cmd_buffer_destroy(cmd_buffer);
3408
3409 }
3410 }
3411 }
3412
3413 VkResult radv_ResetCommandBuffer(
3414 VkCommandBuffer commandBuffer,
3415 VkCommandBufferResetFlags flags)
3416 {
3417 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3418 return radv_reset_cmd_buffer(cmd_buffer);
3419 }
3420
3421 VkResult radv_BeginCommandBuffer(
3422 VkCommandBuffer commandBuffer,
3423 const VkCommandBufferBeginInfo *pBeginInfo)
3424 {
3425 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3426 VkResult result = VK_SUCCESS;
3427
3428 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3429 /* If the command buffer has already been resetted with
3430 * vkResetCommandBuffer, no need to do it again.
3431 */
3432 result = radv_reset_cmd_buffer(cmd_buffer);
3433 if (result != VK_SUCCESS)
3434 return result;
3435 }
3436
3437 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3438 cmd_buffer->state.last_primitive_reset_en = -1;
3439 cmd_buffer->state.last_index_type = -1;
3440 cmd_buffer->state.last_num_instances = -1;
3441 cmd_buffer->state.last_vertex_offset = -1;
3442 cmd_buffer->state.last_first_instance = -1;
3443 cmd_buffer->state.predication_type = -1;
3444 cmd_buffer->state.last_sx_ps_downconvert = -1;
3445 cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
3446 cmd_buffer->state.last_sx_blend_opt_control = -1;
3447 cmd_buffer->usage_flags = pBeginInfo->flags;
3448
3449 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3450 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3451 assert(pBeginInfo->pInheritanceInfo);
3452 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3453 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3454
3455 struct radv_subpass *subpass =
3456 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3457
3458 if (cmd_buffer->state.framebuffer) {
3459 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3460 if (result != VK_SUCCESS)
3461 return result;
3462 }
3463
3464 cmd_buffer->state.inherited_pipeline_statistics =
3465 pBeginInfo->pInheritanceInfo->pipelineStatistics;
3466
3467 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3468 }
3469
3470 if (unlikely(cmd_buffer->device->trace_bo))
3471 radv_cmd_buffer_trace_emit(cmd_buffer);
3472
3473 radv_describe_begin_cmd_buffer(cmd_buffer);
3474
3475 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3476
3477 return result;
3478 }
3479
3480 void radv_CmdBindVertexBuffers(
3481 VkCommandBuffer commandBuffer,
3482 uint32_t firstBinding,
3483 uint32_t bindingCount,
3484 const VkBuffer* pBuffers,
3485 const VkDeviceSize* pOffsets)
3486 {
3487 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3488 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3489 bool changed = false;
3490
3491 /* We have to defer setting up vertex buffer since we need the buffer
3492 * stride from the pipeline. */
3493
3494 assert(firstBinding + bindingCount <= MAX_VBS);
3495 for (uint32_t i = 0; i < bindingCount; i++) {
3496 RADV_FROM_HANDLE(radv_buffer, buffer, pBuffers[i]);
3497 uint32_t idx = firstBinding + i;
3498
3499 if (!changed &&
3500 (vb[idx].buffer != buffer ||
3501 vb[idx].offset != pOffsets[i])) {
3502 changed = true;
3503 }
3504
3505 vb[idx].buffer = buffer;
3506 vb[idx].offset = pOffsets[i];
3507
3508 if (buffer) {
3509 radv_cs_add_buffer(cmd_buffer->device->ws,
3510 cmd_buffer->cs, vb[idx].buffer->bo);
3511 }
3512 }
3513
3514 if (!changed) {
3515 /* No state changes. */
3516 return;
3517 }
3518
3519 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3520 }
3521
3522 static uint32_t
3523 vk_to_index_type(VkIndexType type)
3524 {
3525 switch (type) {
3526 case VK_INDEX_TYPE_UINT8_EXT:
3527 return V_028A7C_VGT_INDEX_8;
3528 case VK_INDEX_TYPE_UINT16:
3529 return V_028A7C_VGT_INDEX_16;
3530 case VK_INDEX_TYPE_UINT32:
3531 return V_028A7C_VGT_INDEX_32;
3532 default:
3533 unreachable("invalid index type");
3534 }
3535 }
3536
3537 static uint32_t
3538 radv_get_vgt_index_size(uint32_t type)
3539 {
3540 switch (type) {
3541 case V_028A7C_VGT_INDEX_8:
3542 return 1;
3543 case V_028A7C_VGT_INDEX_16:
3544 return 2;
3545 case V_028A7C_VGT_INDEX_32:
3546 return 4;
3547 default:
3548 unreachable("invalid index type");
3549 }
3550 }
3551
3552 void radv_CmdBindIndexBuffer(
3553 VkCommandBuffer commandBuffer,
3554 VkBuffer buffer,
3555 VkDeviceSize offset,
3556 VkIndexType indexType)
3557 {
3558 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3559 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3560
3561 if (cmd_buffer->state.index_buffer == index_buffer &&
3562 cmd_buffer->state.index_offset == offset &&
3563 cmd_buffer->state.index_type == indexType) {
3564 /* No state changes. */
3565 return;
3566 }
3567
3568 cmd_buffer->state.index_buffer = index_buffer;
3569 cmd_buffer->state.index_offset = offset;
3570 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3571 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3572 cmd_buffer->state.index_va += index_buffer->offset + offset;
3573
3574 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3575 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3576 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3577 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3578 }
3579
3580
3581 static void
3582 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3583 VkPipelineBindPoint bind_point,
3584 struct radv_descriptor_set *set, unsigned idx)
3585 {
3586 struct radeon_winsys *ws = cmd_buffer->device->ws;
3587
3588 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3589
3590 assert(set);
3591 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3592
3593 if (!cmd_buffer->device->use_global_bo_list) {
3594 for (unsigned j = 0; j < set->buffer_count; ++j)
3595 if (set->descriptors[j])
3596 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3597 }
3598
3599 if(set->bo)
3600 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3601 }
3602
3603 void radv_CmdBindDescriptorSets(
3604 VkCommandBuffer commandBuffer,
3605 VkPipelineBindPoint pipelineBindPoint,
3606 VkPipelineLayout _layout,
3607 uint32_t firstSet,
3608 uint32_t descriptorSetCount,
3609 const VkDescriptorSet* pDescriptorSets,
3610 uint32_t dynamicOffsetCount,
3611 const uint32_t* pDynamicOffsets)
3612 {
3613 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3614 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3615 unsigned dyn_idx = 0;
3616
3617 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3618 struct radv_descriptor_state *descriptors_state =
3619 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3620
3621 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3622 unsigned idx = i + firstSet;
3623 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3624
3625 /* If the set is already bound we only need to update the
3626 * (potentially changed) dynamic offsets. */
3627 if (descriptors_state->sets[idx] != set ||
3628 !(descriptors_state->valid & (1u << idx))) {
3629 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3630 }
3631
3632 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3633 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3634 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3635 assert(dyn_idx < dynamicOffsetCount);
3636
3637 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3638 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3639 dst[0] = va;
3640 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3641 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3642 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3643 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3644 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3645 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3646
3647 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3648 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3649 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3650 S_008F0C_RESOURCE_LEVEL(1);
3651 } else {
3652 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3653 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3654 }
3655
3656 cmd_buffer->push_constant_stages |=
3657 set->layout->dynamic_shader_stages;
3658 }
3659 }
3660 }
3661
3662 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3663 struct radv_descriptor_set *set,
3664 struct radv_descriptor_set_layout *layout,
3665 VkPipelineBindPoint bind_point)
3666 {
3667 struct radv_descriptor_state *descriptors_state =
3668 radv_get_descriptors_state(cmd_buffer, bind_point);
3669 set->size = layout->size;
3670 set->layout = layout;
3671
3672 if (descriptors_state->push_set.capacity < set->size) {
3673 size_t new_size = MAX2(set->size, 1024);
3674 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3675 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3676
3677 free(set->mapped_ptr);
3678 set->mapped_ptr = malloc(new_size);
3679
3680 if (!set->mapped_ptr) {
3681 descriptors_state->push_set.capacity = 0;
3682 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3683 return false;
3684 }
3685
3686 descriptors_state->push_set.capacity = new_size;
3687 }
3688
3689 return true;
3690 }
3691
3692 void radv_meta_push_descriptor_set(
3693 struct radv_cmd_buffer* cmd_buffer,
3694 VkPipelineBindPoint pipelineBindPoint,
3695 VkPipelineLayout _layout,
3696 uint32_t set,
3697 uint32_t descriptorWriteCount,
3698 const VkWriteDescriptorSet* pDescriptorWrites)
3699 {
3700 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3701 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3702 unsigned bo_offset;
3703
3704 assert(set == 0);
3705 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3706
3707 push_set->size = layout->set[set].layout->size;
3708 push_set->layout = layout->set[set].layout;
3709
3710 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3711 &bo_offset,
3712 (void**) &push_set->mapped_ptr))
3713 return;
3714
3715 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3716 push_set->va += bo_offset;
3717
3718 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3719 radv_descriptor_set_to_handle(push_set),
3720 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3721
3722 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3723 }
3724
3725 void radv_CmdPushDescriptorSetKHR(
3726 VkCommandBuffer commandBuffer,
3727 VkPipelineBindPoint pipelineBindPoint,
3728 VkPipelineLayout _layout,
3729 uint32_t set,
3730 uint32_t descriptorWriteCount,
3731 const VkWriteDescriptorSet* pDescriptorWrites)
3732 {
3733 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3734 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3735 struct radv_descriptor_state *descriptors_state =
3736 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3737 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3738
3739 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3740
3741 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3742 layout->set[set].layout,
3743 pipelineBindPoint))
3744 return;
3745
3746 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3747 * because it is invalid, according to Vulkan spec.
3748 */
3749 for (int i = 0; i < descriptorWriteCount; i++) {
3750 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3751 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3752 }
3753
3754 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3755 radv_descriptor_set_to_handle(push_set),
3756 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3757
3758 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3759 descriptors_state->push_dirty = true;
3760 }
3761
3762 void radv_CmdPushDescriptorSetWithTemplateKHR(
3763 VkCommandBuffer commandBuffer,
3764 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3765 VkPipelineLayout _layout,
3766 uint32_t set,
3767 const void* pData)
3768 {
3769 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3770 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3771 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3772 struct radv_descriptor_state *descriptors_state =
3773 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3774 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3775
3776 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3777
3778 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3779 layout->set[set].layout,
3780 templ->bind_point))
3781 return;
3782
3783 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3784 descriptorUpdateTemplate, pData);
3785
3786 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3787 descriptors_state->push_dirty = true;
3788 }
3789
3790 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3791 VkPipelineLayout layout,
3792 VkShaderStageFlags stageFlags,
3793 uint32_t offset,
3794 uint32_t size,
3795 const void* pValues)
3796 {
3797 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3798 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3799 cmd_buffer->push_constant_stages |= stageFlags;
3800 }
3801
3802 VkResult radv_EndCommandBuffer(
3803 VkCommandBuffer commandBuffer)
3804 {
3805 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3806
3807 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3808 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3809 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3810
3811 /* Make sure to sync all pending active queries at the end of
3812 * command buffer.
3813 */
3814 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3815
3816 /* Since NGG streamout uses GDS, we need to make GDS idle when
3817 * we leave the IB, otherwise another process might overwrite
3818 * it while our shaders are busy.
3819 */
3820 if (cmd_buffer->gds_needed)
3821 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3822
3823 si_emit_cache_flush(cmd_buffer);
3824 }
3825
3826 /* Make sure CP DMA is idle at the end of IBs because the kernel
3827 * doesn't wait for it.
3828 */
3829 si_cp_dma_wait_for_idle(cmd_buffer);
3830
3831 radv_describe_end_cmd_buffer(cmd_buffer);
3832
3833 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3834 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3835
3836 VkResult result = cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs);
3837 if (result != VK_SUCCESS)
3838 return vk_error(cmd_buffer->device->instance, result);
3839
3840 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3841
3842 return cmd_buffer->record_result;
3843 }
3844
3845 static void
3846 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3847 {
3848 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3849
3850 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3851 return;
3852
3853 assert(!pipeline->ctx_cs.cdw);
3854
3855 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3856
3857 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3858 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3859
3860 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
3861 pipeline->scratch_bytes_per_wave);
3862 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
3863 pipeline->max_waves);
3864
3865 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3866 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3867
3868 if (unlikely(cmd_buffer->device->trace_bo))
3869 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3870 }
3871
3872 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3873 VkPipelineBindPoint bind_point)
3874 {
3875 struct radv_descriptor_state *descriptors_state =
3876 radv_get_descriptors_state(cmd_buffer, bind_point);
3877
3878 descriptors_state->dirty |= descriptors_state->valid;
3879 }
3880
3881 void radv_CmdBindPipeline(
3882 VkCommandBuffer commandBuffer,
3883 VkPipelineBindPoint pipelineBindPoint,
3884 VkPipeline _pipeline)
3885 {
3886 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3887 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3888
3889 switch (pipelineBindPoint) {
3890 case VK_PIPELINE_BIND_POINT_COMPUTE:
3891 if (cmd_buffer->state.compute_pipeline == pipeline)
3892 return;
3893 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3894
3895 cmd_buffer->state.compute_pipeline = pipeline;
3896 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3897 break;
3898 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3899 if (cmd_buffer->state.pipeline == pipeline)
3900 return;
3901 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3902
3903 cmd_buffer->state.pipeline = pipeline;
3904 if (!pipeline)
3905 break;
3906
3907 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3908 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3909
3910 /* the new vertex shader might not have the same user regs */
3911 cmd_buffer->state.last_first_instance = -1;
3912 cmd_buffer->state.last_vertex_offset = -1;
3913
3914 /* Prefetch all pipeline shaders at first draw time. */
3915 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3916
3917 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 &&
3918 cmd_buffer->state.emitted_pipeline &&
3919 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3920 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3921 /* Transitioning from NGG to legacy GS requires
3922 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3923 * at the beginning of IBs when legacy GS ring pointers
3924 * are set.
3925 */
3926 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3927 }
3928
3929 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3930 radv_bind_streamout_state(cmd_buffer, pipeline);
3931
3932 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3933 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3934 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3935 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3936
3937 if (radv_pipeline_has_tess(pipeline))
3938 cmd_buffer->tess_rings_needed = true;
3939 break;
3940 default:
3941 assert(!"invalid bind point");
3942 break;
3943 }
3944 }
3945
3946 void radv_CmdSetViewport(
3947 VkCommandBuffer commandBuffer,
3948 uint32_t firstViewport,
3949 uint32_t viewportCount,
3950 const VkViewport* pViewports)
3951 {
3952 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3953 struct radv_cmd_state *state = &cmd_buffer->state;
3954 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3955
3956 assert(firstViewport < MAX_VIEWPORTS);
3957 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3958
3959 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3960 pViewports, viewportCount * sizeof(*pViewports))) {
3961 return;
3962 }
3963
3964 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3965 viewportCount * sizeof(*pViewports));
3966
3967 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3968 }
3969
3970 void radv_CmdSetScissor(
3971 VkCommandBuffer commandBuffer,
3972 uint32_t firstScissor,
3973 uint32_t scissorCount,
3974 const VkRect2D* pScissors)
3975 {
3976 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3977 struct radv_cmd_state *state = &cmd_buffer->state;
3978 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3979
3980 assert(firstScissor < MAX_SCISSORS);
3981 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3982
3983 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3984 scissorCount * sizeof(*pScissors))) {
3985 return;
3986 }
3987
3988 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3989 scissorCount * sizeof(*pScissors));
3990
3991 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3992 }
3993
3994 void radv_CmdSetLineWidth(
3995 VkCommandBuffer commandBuffer,
3996 float lineWidth)
3997 {
3998 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3999
4000 if (cmd_buffer->state.dynamic.line_width == lineWidth)
4001 return;
4002
4003 cmd_buffer->state.dynamic.line_width = lineWidth;
4004 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
4005 }
4006
4007 void radv_CmdSetDepthBias(
4008 VkCommandBuffer commandBuffer,
4009 float depthBiasConstantFactor,
4010 float depthBiasClamp,
4011 float depthBiasSlopeFactor)
4012 {
4013 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4014 struct radv_cmd_state *state = &cmd_buffer->state;
4015
4016 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
4017 state->dynamic.depth_bias.clamp == depthBiasClamp &&
4018 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
4019 return;
4020 }
4021
4022 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
4023 state->dynamic.depth_bias.clamp = depthBiasClamp;
4024 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
4025
4026 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
4027 }
4028
4029 void radv_CmdSetBlendConstants(
4030 VkCommandBuffer commandBuffer,
4031 const float blendConstants[4])
4032 {
4033 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4034 struct radv_cmd_state *state = &cmd_buffer->state;
4035
4036 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
4037 return;
4038
4039 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
4040
4041 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
4042 }
4043
4044 void radv_CmdSetDepthBounds(
4045 VkCommandBuffer commandBuffer,
4046 float minDepthBounds,
4047 float maxDepthBounds)
4048 {
4049 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4050 struct radv_cmd_state *state = &cmd_buffer->state;
4051
4052 if (state->dynamic.depth_bounds.min == minDepthBounds &&
4053 state->dynamic.depth_bounds.max == maxDepthBounds) {
4054 return;
4055 }
4056
4057 state->dynamic.depth_bounds.min = minDepthBounds;
4058 state->dynamic.depth_bounds.max = maxDepthBounds;
4059
4060 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
4061 }
4062
4063 void radv_CmdSetStencilCompareMask(
4064 VkCommandBuffer commandBuffer,
4065 VkStencilFaceFlags faceMask,
4066 uint32_t compareMask)
4067 {
4068 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4069 struct radv_cmd_state *state = &cmd_buffer->state;
4070 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
4071 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
4072
4073 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4074 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4075 return;
4076 }
4077
4078 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4079 state->dynamic.stencil_compare_mask.front = compareMask;
4080 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4081 state->dynamic.stencil_compare_mask.back = compareMask;
4082
4083 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
4084 }
4085
4086 void radv_CmdSetStencilWriteMask(
4087 VkCommandBuffer commandBuffer,
4088 VkStencilFaceFlags faceMask,
4089 uint32_t writeMask)
4090 {
4091 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4092 struct radv_cmd_state *state = &cmd_buffer->state;
4093 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
4094 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
4095
4096 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4097 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4098 return;
4099 }
4100
4101 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4102 state->dynamic.stencil_write_mask.front = writeMask;
4103 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4104 state->dynamic.stencil_write_mask.back = writeMask;
4105
4106 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
4107 }
4108
4109 void radv_CmdSetStencilReference(
4110 VkCommandBuffer commandBuffer,
4111 VkStencilFaceFlags faceMask,
4112 uint32_t reference)
4113 {
4114 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4115 struct radv_cmd_state *state = &cmd_buffer->state;
4116 bool front_same = state->dynamic.stencil_reference.front == reference;
4117 bool back_same = state->dynamic.stencil_reference.back == reference;
4118
4119 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
4120 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
4121 return;
4122 }
4123
4124 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
4125 cmd_buffer->state.dynamic.stencil_reference.front = reference;
4126 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
4127 cmd_buffer->state.dynamic.stencil_reference.back = reference;
4128
4129 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
4130 }
4131
4132 void radv_CmdSetDiscardRectangleEXT(
4133 VkCommandBuffer commandBuffer,
4134 uint32_t firstDiscardRectangle,
4135 uint32_t discardRectangleCount,
4136 const VkRect2D* pDiscardRectangles)
4137 {
4138 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4139 struct radv_cmd_state *state = &cmd_buffer->state;
4140 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
4141
4142 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
4143 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
4144
4145 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
4146 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
4147 return;
4148 }
4149
4150 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
4151 pDiscardRectangles, discardRectangleCount);
4152
4153 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
4154 }
4155
4156 void radv_CmdSetSampleLocationsEXT(
4157 VkCommandBuffer commandBuffer,
4158 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
4159 {
4160 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4161 struct radv_cmd_state *state = &cmd_buffer->state;
4162
4163 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
4164
4165 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
4166 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
4167 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
4168 typed_memcpy(&state->dynamic.sample_location.locations[0],
4169 pSampleLocationsInfo->pSampleLocations,
4170 pSampleLocationsInfo->sampleLocationsCount);
4171
4172 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
4173 }
4174
4175 void radv_CmdSetLineStippleEXT(
4176 VkCommandBuffer commandBuffer,
4177 uint32_t lineStippleFactor,
4178 uint16_t lineStipplePattern)
4179 {
4180 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4181 struct radv_cmd_state *state = &cmd_buffer->state;
4182
4183 state->dynamic.line_stipple.factor = lineStippleFactor;
4184 state->dynamic.line_stipple.pattern = lineStipplePattern;
4185
4186 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
4187 }
4188
4189 void radv_CmdExecuteCommands(
4190 VkCommandBuffer commandBuffer,
4191 uint32_t commandBufferCount,
4192 const VkCommandBuffer* pCmdBuffers)
4193 {
4194 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4195
4196 assert(commandBufferCount > 0);
4197
4198 /* Emit pending flushes on primary prior to executing secondary */
4199 si_emit_cache_flush(primary);
4200
4201 for (uint32_t i = 0; i < commandBufferCount; i++) {
4202 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4203
4204 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4205 secondary->scratch_size_per_wave_needed);
4206 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4207 secondary->scratch_waves_wanted);
4208 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4209 secondary->compute_scratch_size_per_wave_needed);
4210 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4211 secondary->compute_scratch_waves_wanted);
4212
4213 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4214 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4215 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4216 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4217 if (secondary->tess_rings_needed)
4218 primary->tess_rings_needed = true;
4219 if (secondary->sample_positions_needed)
4220 primary->sample_positions_needed = true;
4221 if (secondary->gds_needed)
4222 primary->gds_needed = true;
4223
4224 if (!secondary->state.framebuffer &&
4225 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4226 /* Emit the framebuffer state from primary if secondary
4227 * has been recorded without a framebuffer, otherwise
4228 * fast color/depth clears can't work.
4229 */
4230 radv_emit_framebuffer_state(primary);
4231 }
4232
4233 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4234
4235
4236 /* When the secondary command buffer is compute only we don't
4237 * need to re-emit the current graphics pipeline.
4238 */
4239 if (secondary->state.emitted_pipeline) {
4240 primary->state.emitted_pipeline =
4241 secondary->state.emitted_pipeline;
4242 }
4243
4244 /* When the secondary command buffer is graphics only we don't
4245 * need to re-emit the current compute pipeline.
4246 */
4247 if (secondary->state.emitted_compute_pipeline) {
4248 primary->state.emitted_compute_pipeline =
4249 secondary->state.emitted_compute_pipeline;
4250 }
4251
4252 /* Only re-emit the draw packets when needed. */
4253 if (secondary->state.last_primitive_reset_en != -1) {
4254 primary->state.last_primitive_reset_en =
4255 secondary->state.last_primitive_reset_en;
4256 }
4257
4258 if (secondary->state.last_primitive_reset_index) {
4259 primary->state.last_primitive_reset_index =
4260 secondary->state.last_primitive_reset_index;
4261 }
4262
4263 if (secondary->state.last_ia_multi_vgt_param) {
4264 primary->state.last_ia_multi_vgt_param =
4265 secondary->state.last_ia_multi_vgt_param;
4266 }
4267
4268 primary->state.last_first_instance = secondary->state.last_first_instance;
4269 primary->state.last_num_instances = secondary->state.last_num_instances;
4270 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4271 primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
4272 primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
4273 primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
4274
4275 if (secondary->state.last_index_type != -1) {
4276 primary->state.last_index_type =
4277 secondary->state.last_index_type;
4278 }
4279 }
4280
4281 /* After executing commands from secondary buffers we have to dirty
4282 * some states.
4283 */
4284 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4285 RADV_CMD_DIRTY_INDEX_BUFFER |
4286 RADV_CMD_DIRTY_DYNAMIC_ALL;
4287 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4288 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4289 }
4290
4291 VkResult radv_CreateCommandPool(
4292 VkDevice _device,
4293 const VkCommandPoolCreateInfo* pCreateInfo,
4294 const VkAllocationCallbacks* pAllocator,
4295 VkCommandPool* pCmdPool)
4296 {
4297 RADV_FROM_HANDLE(radv_device, device, _device);
4298 struct radv_cmd_pool *pool;
4299
4300 pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8,
4301 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4302 if (pool == NULL)
4303 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4304
4305 vk_object_base_init(&device->vk, &pool->base,
4306 VK_OBJECT_TYPE_COMMAND_POOL);
4307
4308 if (pAllocator)
4309 pool->alloc = *pAllocator;
4310 else
4311 pool->alloc = device->vk.alloc;
4312
4313 list_inithead(&pool->cmd_buffers);
4314 list_inithead(&pool->free_cmd_buffers);
4315
4316 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4317
4318 *pCmdPool = radv_cmd_pool_to_handle(pool);
4319
4320 return VK_SUCCESS;
4321
4322 }
4323
4324 void radv_DestroyCommandPool(
4325 VkDevice _device,
4326 VkCommandPool commandPool,
4327 const VkAllocationCallbacks* pAllocator)
4328 {
4329 RADV_FROM_HANDLE(radv_device, device, _device);
4330 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4331
4332 if (!pool)
4333 return;
4334
4335 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4336 &pool->cmd_buffers, pool_link) {
4337 radv_cmd_buffer_destroy(cmd_buffer);
4338 }
4339
4340 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4341 &pool->free_cmd_buffers, pool_link) {
4342 radv_cmd_buffer_destroy(cmd_buffer);
4343 }
4344
4345 vk_object_base_finish(&pool->base);
4346 vk_free2(&device->vk.alloc, pAllocator, pool);
4347 }
4348
4349 VkResult radv_ResetCommandPool(
4350 VkDevice device,
4351 VkCommandPool commandPool,
4352 VkCommandPoolResetFlags flags)
4353 {
4354 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4355 VkResult result;
4356
4357 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4358 &pool->cmd_buffers, pool_link) {
4359 result = radv_reset_cmd_buffer(cmd_buffer);
4360 if (result != VK_SUCCESS)
4361 return result;
4362 }
4363
4364 return VK_SUCCESS;
4365 }
4366
4367 void radv_TrimCommandPool(
4368 VkDevice device,
4369 VkCommandPool commandPool,
4370 VkCommandPoolTrimFlags flags)
4371 {
4372 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4373
4374 if (!pool)
4375 return;
4376
4377 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4378 &pool->free_cmd_buffers, pool_link) {
4379 radv_cmd_buffer_destroy(cmd_buffer);
4380 }
4381 }
4382
4383 static void
4384 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4385 uint32_t subpass_id)
4386 {
4387 struct radv_cmd_state *state = &cmd_buffer->state;
4388 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4389
4390 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4391 cmd_buffer->cs, 4096);
4392
4393 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4394
4395 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4396
4397 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4398
4399 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4400 const uint32_t a = subpass->attachments[i].attachment;
4401 if (a == VK_ATTACHMENT_UNUSED)
4402 continue;
4403
4404 radv_handle_subpass_image_transition(cmd_buffer,
4405 subpass->attachments[i],
4406 true);
4407 }
4408
4409 radv_describe_barrier_end(cmd_buffer);
4410
4411 radv_cmd_buffer_clear_subpass(cmd_buffer);
4412
4413 assert(cmd_buffer->cs->cdw <= cdw_max);
4414 }
4415
4416 static void
4417 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4418 {
4419 struct radv_cmd_state *state = &cmd_buffer->state;
4420 const struct radv_subpass *subpass = state->subpass;
4421 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4422
4423 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4424
4425 radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
4426
4427 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4428 const uint32_t a = subpass->attachments[i].attachment;
4429 if (a == VK_ATTACHMENT_UNUSED)
4430 continue;
4431
4432 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4433 continue;
4434
4435 VkImageLayout layout = state->pass->attachments[a].final_layout;
4436 VkImageLayout stencil_layout = state->pass->attachments[a].stencil_final_layout;
4437 struct radv_subpass_attachment att = { a, layout, stencil_layout };
4438 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4439 }
4440
4441 radv_describe_barrier_end(cmd_buffer);
4442 }
4443
4444 void
4445 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
4446 const VkRenderPassBeginInfo *pRenderPassBegin)
4447 {
4448 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4449 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4450 VkResult result;
4451
4452 cmd_buffer->state.framebuffer = framebuffer;
4453 cmd_buffer->state.pass = pass;
4454 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4455
4456 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4457 if (result != VK_SUCCESS)
4458 return;
4459
4460 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4461 if (result != VK_SUCCESS)
4462 return;
4463 }
4464
4465 void radv_CmdBeginRenderPass(
4466 VkCommandBuffer commandBuffer,
4467 const VkRenderPassBeginInfo* pRenderPassBegin,
4468 VkSubpassContents contents)
4469 {
4470 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4471
4472 radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBegin);
4473
4474 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4475 }
4476
4477 void radv_CmdBeginRenderPass2(
4478 VkCommandBuffer commandBuffer,
4479 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4480 const VkSubpassBeginInfo* pSubpassBeginInfo)
4481 {
4482 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4483 pSubpassBeginInfo->contents);
4484 }
4485
4486 void radv_CmdNextSubpass(
4487 VkCommandBuffer commandBuffer,
4488 VkSubpassContents contents)
4489 {
4490 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4491
4492 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4493 radv_cmd_buffer_end_subpass(cmd_buffer);
4494 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4495 }
4496
4497 void radv_CmdNextSubpass2(
4498 VkCommandBuffer commandBuffer,
4499 const VkSubpassBeginInfo* pSubpassBeginInfo,
4500 const VkSubpassEndInfo* pSubpassEndInfo)
4501 {
4502 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4503 }
4504
4505 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4506 {
4507 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4508 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4509 if (!radv_get_shader(pipeline, stage))
4510 continue;
4511
4512 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4513 if (loc->sgpr_idx == -1)
4514 continue;
4515 uint32_t base_reg = pipeline->user_data_0[stage];
4516 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4517
4518 }
4519 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4520 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4521 if (loc->sgpr_idx != -1) {
4522 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4523 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4524 }
4525 }
4526 }
4527
4528 static void
4529 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4530 uint32_t vertex_count,
4531 bool use_opaque)
4532 {
4533 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4534 radeon_emit(cmd_buffer->cs, vertex_count);
4535 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4536 S_0287F0_USE_OPAQUE(use_opaque));
4537 }
4538
4539 static void
4540 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4541 uint64_t index_va,
4542 uint32_t index_count)
4543 {
4544 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4545 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4546 radeon_emit(cmd_buffer->cs, index_va);
4547 radeon_emit(cmd_buffer->cs, index_va >> 32);
4548 radeon_emit(cmd_buffer->cs, index_count);
4549 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4550 }
4551
4552 static void
4553 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4554 bool indexed,
4555 uint32_t draw_count,
4556 uint64_t count_va,
4557 uint32_t stride)
4558 {
4559 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4560 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4561 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4562 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4563 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4564 bool predicating = cmd_buffer->state.predicating;
4565 assert(base_reg);
4566
4567 /* just reset draw state for vertex data */
4568 cmd_buffer->state.last_first_instance = -1;
4569 cmd_buffer->state.last_num_instances = -1;
4570 cmd_buffer->state.last_vertex_offset = -1;
4571
4572 if (draw_count == 1 && !count_va && !draw_id_enable) {
4573 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4574 PKT3_DRAW_INDIRECT, 3, predicating));
4575 radeon_emit(cs, 0);
4576 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4577 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4578 radeon_emit(cs, di_src_sel);
4579 } else {
4580 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4581 PKT3_DRAW_INDIRECT_MULTI,
4582 8, predicating));
4583 radeon_emit(cs, 0);
4584 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4585 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4586 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4587 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4588 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4589 radeon_emit(cs, draw_count); /* count */
4590 radeon_emit(cs, count_va); /* count_addr */
4591 radeon_emit(cs, count_va >> 32);
4592 radeon_emit(cs, stride); /* stride */
4593 radeon_emit(cs, di_src_sel);
4594 }
4595 }
4596
4597 static void
4598 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4599 const struct radv_draw_info *info)
4600 {
4601 struct radv_cmd_state *state = &cmd_buffer->state;
4602 struct radeon_winsys *ws = cmd_buffer->device->ws;
4603 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4604
4605 if (info->indirect) {
4606 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4607 uint64_t count_va = 0;
4608
4609 va += info->indirect->offset + info->indirect_offset;
4610
4611 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4612
4613 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4614 radeon_emit(cs, 1);
4615 radeon_emit(cs, va);
4616 radeon_emit(cs, va >> 32);
4617
4618 if (info->count_buffer) {
4619 count_va = radv_buffer_get_va(info->count_buffer->bo);
4620 count_va += info->count_buffer->offset +
4621 info->count_buffer_offset;
4622
4623 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4624 }
4625
4626 if (!state->subpass->view_mask) {
4627 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4628 info->indexed,
4629 info->count,
4630 count_va,
4631 info->stride);
4632 } else {
4633 unsigned i;
4634 for_each_bit(i, state->subpass->view_mask) {
4635 radv_emit_view_index(cmd_buffer, i);
4636
4637 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4638 info->indexed,
4639 info->count,
4640 count_va,
4641 info->stride);
4642 }
4643 }
4644 } else {
4645 assert(state->pipeline->graphics.vtx_base_sgpr);
4646
4647 if (info->vertex_offset != state->last_vertex_offset ||
4648 info->first_instance != state->last_first_instance) {
4649 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4650 state->pipeline->graphics.vtx_emit_num);
4651
4652 radeon_emit(cs, info->vertex_offset);
4653 radeon_emit(cs, info->first_instance);
4654 if (state->pipeline->graphics.vtx_emit_num == 3)
4655 radeon_emit(cs, 0);
4656 state->last_first_instance = info->first_instance;
4657 state->last_vertex_offset = info->vertex_offset;
4658 }
4659
4660 if (state->last_num_instances != info->instance_count) {
4661 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4662 radeon_emit(cs, info->instance_count);
4663 state->last_num_instances = info->instance_count;
4664 }
4665
4666 if (info->indexed) {
4667 int index_size = radv_get_vgt_index_size(state->index_type);
4668 uint64_t index_va;
4669
4670 /* Skip draw calls with 0-sized index buffers. They
4671 * cause a hang on some chips, like Navi10-14.
4672 */
4673 if (!cmd_buffer->state.max_index_count)
4674 return;
4675
4676 index_va = state->index_va;
4677 index_va += info->first_index * index_size;
4678
4679 if (!state->subpass->view_mask) {
4680 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4681 index_va,
4682 info->count);
4683 } else {
4684 unsigned i;
4685 for_each_bit(i, state->subpass->view_mask) {
4686 radv_emit_view_index(cmd_buffer, i);
4687
4688 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4689 index_va,
4690 info->count);
4691 }
4692 }
4693 } else {
4694 if (!state->subpass->view_mask) {
4695 radv_cs_emit_draw_packet(cmd_buffer,
4696 info->count,
4697 !!info->strmout_buffer);
4698 } else {
4699 unsigned i;
4700 for_each_bit(i, state->subpass->view_mask) {
4701 radv_emit_view_index(cmd_buffer, i);
4702
4703 radv_cs_emit_draw_packet(cmd_buffer,
4704 info->count,
4705 !!info->strmout_buffer);
4706 }
4707 }
4708 }
4709 }
4710 }
4711
4712 /*
4713 * Vega and raven have a bug which triggers if there are multiple context
4714 * register contexts active at the same time with different scissor values.
4715 *
4716 * There are two possible workarounds:
4717 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4718 * there is only ever 1 active set of scissor values at the same time.
4719 *
4720 * 2) Whenever the hardware switches contexts we have to set the scissor
4721 * registers again even if it is a noop. That way the new context gets
4722 * the correct scissor values.
4723 *
4724 * This implements option 2. radv_need_late_scissor_emission needs to
4725 * return true on affected HW if radv_emit_all_graphics_states sets
4726 * any context registers.
4727 */
4728 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4729 const struct radv_draw_info *info)
4730 {
4731 struct radv_cmd_state *state = &cmd_buffer->state;
4732
4733 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4734 return false;
4735
4736 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4737 return true;
4738
4739 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4740
4741 /* Index, vertex and streamout buffers don't change context regs, and
4742 * pipeline is already handled.
4743 */
4744 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4745 RADV_CMD_DIRTY_VERTEX_BUFFER |
4746 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4747 RADV_CMD_DIRTY_PIPELINE);
4748
4749 if (cmd_buffer->state.dirty & used_states)
4750 return true;
4751
4752 uint32_t primitive_reset_index =
4753 radv_get_primitive_reset_index(cmd_buffer);
4754
4755 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4756 primitive_reset_index != state->last_primitive_reset_index)
4757 return true;
4758
4759 return false;
4760 }
4761
4762 static void
4763 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4764 const struct radv_draw_info *info)
4765 {
4766 bool late_scissor_emission;
4767
4768 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4769 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4770 radv_emit_rbplus_state(cmd_buffer);
4771
4772 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4773 radv_emit_graphics_pipeline(cmd_buffer);
4774
4775 /* This should be before the cmd_buffer->state.dirty is cleared
4776 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4777 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4778 late_scissor_emission =
4779 radv_need_late_scissor_emission(cmd_buffer, info);
4780
4781 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4782 radv_emit_framebuffer_state(cmd_buffer);
4783
4784 if (info->indexed) {
4785 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4786 radv_emit_index_buffer(cmd_buffer, info->indirect);
4787 } else {
4788 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4789 * so the state must be re-emitted before the next indexed
4790 * draw.
4791 */
4792 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4793 cmd_buffer->state.last_index_type = -1;
4794 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4795 }
4796 }
4797
4798 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4799
4800 radv_emit_draw_registers(cmd_buffer, info);
4801
4802 if (late_scissor_emission)
4803 radv_emit_scissor(cmd_buffer);
4804 }
4805
4806 static void
4807 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4808 const struct radv_draw_info *info)
4809 {
4810 struct radeon_info *rad_info =
4811 &cmd_buffer->device->physical_device->rad_info;
4812 bool has_prefetch =
4813 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4814 bool pipeline_is_dirty =
4815 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4816 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4817
4818 ASSERTED unsigned cdw_max =
4819 radeon_check_space(cmd_buffer->device->ws,
4820 cmd_buffer->cs, 4096);
4821
4822 if (likely(!info->indirect)) {
4823 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4824 * no workaround for indirect draws, but we can at least skip
4825 * direct draws.
4826 */
4827 if (unlikely(!info->instance_count))
4828 return;
4829
4830 /* Handle count == 0. */
4831 if (unlikely(!info->count && !info->strmout_buffer))
4832 return;
4833 }
4834
4835 radv_describe_draw(cmd_buffer);
4836
4837 /* Use optimal packet order based on whether we need to sync the
4838 * pipeline.
4839 */
4840 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4841 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4842 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4843 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4844 /* If we have to wait for idle, set all states first, so that
4845 * all SET packets are processed in parallel with previous draw
4846 * calls. Then upload descriptors, set shader pointers, and
4847 * draw, and prefetch at the end. This ensures that the time
4848 * the CUs are idle is very short. (there are only SET_SH
4849 * packets between the wait and the draw)
4850 */
4851 radv_emit_all_graphics_states(cmd_buffer, info);
4852 si_emit_cache_flush(cmd_buffer);
4853 /* <-- CUs are idle here --> */
4854
4855 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4856
4857 radv_emit_draw_packets(cmd_buffer, info);
4858 /* <-- CUs are busy here --> */
4859
4860 /* Start prefetches after the draw has been started. Both will
4861 * run in parallel, but starting the draw first is more
4862 * important.
4863 */
4864 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4865 radv_emit_prefetch_L2(cmd_buffer,
4866 cmd_buffer->state.pipeline, false);
4867 }
4868 } else {
4869 /* If we don't wait for idle, start prefetches first, then set
4870 * states, and draw at the end.
4871 */
4872 si_emit_cache_flush(cmd_buffer);
4873
4874 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4875 /* Only prefetch the vertex shader and VBO descriptors
4876 * in order to start the draw as soon as possible.
4877 */
4878 radv_emit_prefetch_L2(cmd_buffer,
4879 cmd_buffer->state.pipeline, true);
4880 }
4881
4882 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4883
4884 radv_emit_all_graphics_states(cmd_buffer, info);
4885 radv_emit_draw_packets(cmd_buffer, info);
4886
4887 /* Prefetch the remaining shaders after the draw has been
4888 * started.
4889 */
4890 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4891 radv_emit_prefetch_L2(cmd_buffer,
4892 cmd_buffer->state.pipeline, false);
4893 }
4894 }
4895
4896 /* Workaround for a VGT hang when streamout is enabled.
4897 * It must be done after drawing.
4898 */
4899 if (cmd_buffer->state.streamout.streamout_enabled &&
4900 (rad_info->family == CHIP_HAWAII ||
4901 rad_info->family == CHIP_TONGA ||
4902 rad_info->family == CHIP_FIJI)) {
4903 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4904 }
4905
4906 assert(cmd_buffer->cs->cdw <= cdw_max);
4907 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4908 }
4909
4910 void radv_CmdDraw(
4911 VkCommandBuffer commandBuffer,
4912 uint32_t vertexCount,
4913 uint32_t instanceCount,
4914 uint32_t firstVertex,
4915 uint32_t firstInstance)
4916 {
4917 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4918 struct radv_draw_info info = {};
4919
4920 info.count = vertexCount;
4921 info.instance_count = instanceCount;
4922 info.first_instance = firstInstance;
4923 info.vertex_offset = firstVertex;
4924
4925 radv_draw(cmd_buffer, &info);
4926 }
4927
4928 void radv_CmdDrawIndexed(
4929 VkCommandBuffer commandBuffer,
4930 uint32_t indexCount,
4931 uint32_t instanceCount,
4932 uint32_t firstIndex,
4933 int32_t vertexOffset,
4934 uint32_t firstInstance)
4935 {
4936 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4937 struct radv_draw_info info = {};
4938
4939 info.indexed = true;
4940 info.count = indexCount;
4941 info.instance_count = instanceCount;
4942 info.first_index = firstIndex;
4943 info.vertex_offset = vertexOffset;
4944 info.first_instance = firstInstance;
4945
4946 radv_draw(cmd_buffer, &info);
4947 }
4948
4949 void radv_CmdDrawIndirect(
4950 VkCommandBuffer commandBuffer,
4951 VkBuffer _buffer,
4952 VkDeviceSize offset,
4953 uint32_t drawCount,
4954 uint32_t stride)
4955 {
4956 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4957 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4958 struct radv_draw_info info = {};
4959
4960 info.count = drawCount;
4961 info.indirect = buffer;
4962 info.indirect_offset = offset;
4963 info.stride = stride;
4964
4965 radv_draw(cmd_buffer, &info);
4966 }
4967
4968 void radv_CmdDrawIndexedIndirect(
4969 VkCommandBuffer commandBuffer,
4970 VkBuffer _buffer,
4971 VkDeviceSize offset,
4972 uint32_t drawCount,
4973 uint32_t stride)
4974 {
4975 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4976 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4977 struct radv_draw_info info = {};
4978
4979 info.indexed = true;
4980 info.count = drawCount;
4981 info.indirect = buffer;
4982 info.indirect_offset = offset;
4983 info.stride = stride;
4984
4985 radv_draw(cmd_buffer, &info);
4986 }
4987
4988 void radv_CmdDrawIndirectCount(
4989 VkCommandBuffer commandBuffer,
4990 VkBuffer _buffer,
4991 VkDeviceSize offset,
4992 VkBuffer _countBuffer,
4993 VkDeviceSize countBufferOffset,
4994 uint32_t maxDrawCount,
4995 uint32_t stride)
4996 {
4997 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4998 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4999 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5000 struct radv_draw_info info = {};
5001
5002 info.count = maxDrawCount;
5003 info.indirect = buffer;
5004 info.indirect_offset = offset;
5005 info.count_buffer = count_buffer;
5006 info.count_buffer_offset = countBufferOffset;
5007 info.stride = stride;
5008
5009 radv_draw(cmd_buffer, &info);
5010 }
5011
5012 void radv_CmdDrawIndexedIndirectCount(
5013 VkCommandBuffer commandBuffer,
5014 VkBuffer _buffer,
5015 VkDeviceSize offset,
5016 VkBuffer _countBuffer,
5017 VkDeviceSize countBufferOffset,
5018 uint32_t maxDrawCount,
5019 uint32_t stride)
5020 {
5021 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5022 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5023 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
5024 struct radv_draw_info info = {};
5025
5026 info.indexed = true;
5027 info.count = maxDrawCount;
5028 info.indirect = buffer;
5029 info.indirect_offset = offset;
5030 info.count_buffer = count_buffer;
5031 info.count_buffer_offset = countBufferOffset;
5032 info.stride = stride;
5033
5034 radv_draw(cmd_buffer, &info);
5035 }
5036
5037 struct radv_dispatch_info {
5038 /**
5039 * Determine the layout of the grid (in block units) to be used.
5040 */
5041 uint32_t blocks[3];
5042
5043 /**
5044 * A starting offset for the grid. If unaligned is set, the offset
5045 * must still be aligned.
5046 */
5047 uint32_t offsets[3];
5048 /**
5049 * Whether it's an unaligned compute dispatch.
5050 */
5051 bool unaligned;
5052
5053 /**
5054 * Indirect compute parameters resource.
5055 */
5056 struct radv_buffer *indirect;
5057 uint64_t indirect_offset;
5058 };
5059
5060 static void
5061 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
5062 const struct radv_dispatch_info *info)
5063 {
5064 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5065 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5066 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
5067 struct radeon_winsys *ws = cmd_buffer->device->ws;
5068 bool predicating = cmd_buffer->state.predicating;
5069 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5070 struct radv_userdata_info *loc;
5071
5072 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
5073 AC_UD_CS_GRID_SIZE);
5074
5075 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
5076
5077 if (compute_shader->info.wave_size == 32) {
5078 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5079 dispatch_initiator |= S_00B800_CS_W32_EN(1);
5080 }
5081
5082 if (info->indirect) {
5083 uint64_t va = radv_buffer_get_va(info->indirect->bo);
5084
5085 va += info->indirect->offset + info->indirect_offset;
5086
5087 radv_cs_add_buffer(ws, cs, info->indirect->bo);
5088
5089 if (loc->sgpr_idx != -1) {
5090 for (unsigned i = 0; i < 3; ++i) {
5091 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5092 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5093 COPY_DATA_DST_SEL(COPY_DATA_REG));
5094 radeon_emit(cs, (va + 4 * i));
5095 radeon_emit(cs, (va + 4 * i) >> 32);
5096 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
5097 + loc->sgpr_idx * 4) >> 2) + i);
5098 radeon_emit(cs, 0);
5099 }
5100 }
5101
5102 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
5103 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
5104 PKT3_SHADER_TYPE_S(1));
5105 radeon_emit(cs, va);
5106 radeon_emit(cs, va >> 32);
5107 radeon_emit(cs, dispatch_initiator);
5108 } else {
5109 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
5110 PKT3_SHADER_TYPE_S(1));
5111 radeon_emit(cs, 1);
5112 radeon_emit(cs, va);
5113 radeon_emit(cs, va >> 32);
5114
5115 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
5116 PKT3_SHADER_TYPE_S(1));
5117 radeon_emit(cs, 0);
5118 radeon_emit(cs, dispatch_initiator);
5119 }
5120 } else {
5121 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
5122 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
5123
5124 if (info->unaligned) {
5125 unsigned *cs_block_size = compute_shader->info.cs.block_size;
5126 unsigned remainder[3];
5127
5128 /* If aligned, these should be an entire block size,
5129 * not 0.
5130 */
5131 remainder[0] = blocks[0] + cs_block_size[0] -
5132 align_u32_npot(blocks[0], cs_block_size[0]);
5133 remainder[1] = blocks[1] + cs_block_size[1] -
5134 align_u32_npot(blocks[1], cs_block_size[1]);
5135 remainder[2] = blocks[2] + cs_block_size[2] -
5136 align_u32_npot(blocks[2], cs_block_size[2]);
5137
5138 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
5139 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
5140 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
5141
5142 for(unsigned i = 0; i < 3; ++i) {
5143 assert(offsets[i] % cs_block_size[i] == 0);
5144 offsets[i] /= cs_block_size[i];
5145 }
5146
5147 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5148 radeon_emit(cs,
5149 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
5150 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
5151 radeon_emit(cs,
5152 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
5153 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
5154 radeon_emit(cs,
5155 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
5156 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
5157
5158 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
5159 }
5160
5161 if (loc->sgpr_idx != -1) {
5162 assert(loc->num_sgprs == 3);
5163
5164 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
5165 loc->sgpr_idx * 4, 3);
5166 radeon_emit(cs, blocks[0]);
5167 radeon_emit(cs, blocks[1]);
5168 radeon_emit(cs, blocks[2]);
5169 }
5170
5171 if (offsets[0] || offsets[1] || offsets[2]) {
5172 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
5173 radeon_emit(cs, offsets[0]);
5174 radeon_emit(cs, offsets[1]);
5175 radeon_emit(cs, offsets[2]);
5176
5177 /* The blocks in the packet are not counts but end values. */
5178 for (unsigned i = 0; i < 3; ++i)
5179 blocks[i] += offsets[i];
5180 } else {
5181 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
5182 }
5183
5184 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
5185 PKT3_SHADER_TYPE_S(1));
5186 radeon_emit(cs, blocks[0]);
5187 radeon_emit(cs, blocks[1]);
5188 radeon_emit(cs, blocks[2]);
5189 radeon_emit(cs, dispatch_initiator);
5190 }
5191
5192 assert(cmd_buffer->cs->cdw <= cdw_max);
5193 }
5194
5195 static void
5196 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
5197 {
5198 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5199 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
5200 }
5201
5202 static void
5203 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
5204 const struct radv_dispatch_info *info)
5205 {
5206 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
5207 bool has_prefetch =
5208 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
5209 bool pipeline_is_dirty = pipeline &&
5210 pipeline != cmd_buffer->state.emitted_compute_pipeline;
5211
5212 radv_describe_dispatch(cmd_buffer, 8, 8, 8);
5213
5214 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5215 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5216 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
5217 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5218 /* If we have to wait for idle, set all states first, so that
5219 * all SET packets are processed in parallel with previous draw
5220 * calls. Then upload descriptors, set shader pointers, and
5221 * dispatch, and prefetch at the end. This ensures that the
5222 * time the CUs are idle is very short. (there are only SET_SH
5223 * packets between the wait and the draw)
5224 */
5225 radv_emit_compute_pipeline(cmd_buffer);
5226 si_emit_cache_flush(cmd_buffer);
5227 /* <-- CUs are idle here --> */
5228
5229 radv_upload_compute_shader_descriptors(cmd_buffer);
5230
5231 radv_emit_dispatch_packets(cmd_buffer, info);
5232 /* <-- CUs are busy here --> */
5233
5234 /* Start prefetches after the dispatch has been started. Both
5235 * will run in parallel, but starting the dispatch first is
5236 * more important.
5237 */
5238 if (has_prefetch && pipeline_is_dirty) {
5239 radv_emit_shader_prefetch(cmd_buffer,
5240 pipeline->shaders[MESA_SHADER_COMPUTE]);
5241 }
5242 } else {
5243 /* If we don't wait for idle, start prefetches first, then set
5244 * states, and dispatch at the end.
5245 */
5246 si_emit_cache_flush(cmd_buffer);
5247
5248 if (has_prefetch && pipeline_is_dirty) {
5249 radv_emit_shader_prefetch(cmd_buffer,
5250 pipeline->shaders[MESA_SHADER_COMPUTE]);
5251 }
5252
5253 radv_upload_compute_shader_descriptors(cmd_buffer);
5254
5255 radv_emit_compute_pipeline(cmd_buffer);
5256 radv_emit_dispatch_packets(cmd_buffer, info);
5257 }
5258
5259 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5260 }
5261
5262 void radv_CmdDispatchBase(
5263 VkCommandBuffer commandBuffer,
5264 uint32_t base_x,
5265 uint32_t base_y,
5266 uint32_t base_z,
5267 uint32_t x,
5268 uint32_t y,
5269 uint32_t z)
5270 {
5271 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5272 struct radv_dispatch_info info = {};
5273
5274 info.blocks[0] = x;
5275 info.blocks[1] = y;
5276 info.blocks[2] = z;
5277
5278 info.offsets[0] = base_x;
5279 info.offsets[1] = base_y;
5280 info.offsets[2] = base_z;
5281 radv_dispatch(cmd_buffer, &info);
5282 }
5283
5284 void radv_CmdDispatch(
5285 VkCommandBuffer commandBuffer,
5286 uint32_t x,
5287 uint32_t y,
5288 uint32_t z)
5289 {
5290 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5291 }
5292
5293 void radv_CmdDispatchIndirect(
5294 VkCommandBuffer commandBuffer,
5295 VkBuffer _buffer,
5296 VkDeviceSize offset)
5297 {
5298 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5299 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5300 struct radv_dispatch_info info = {};
5301
5302 info.indirect = buffer;
5303 info.indirect_offset = offset;
5304
5305 radv_dispatch(cmd_buffer, &info);
5306 }
5307
5308 void radv_unaligned_dispatch(
5309 struct radv_cmd_buffer *cmd_buffer,
5310 uint32_t x,
5311 uint32_t y,
5312 uint32_t z)
5313 {
5314 struct radv_dispatch_info info = {};
5315
5316 info.blocks[0] = x;
5317 info.blocks[1] = y;
5318 info.blocks[2] = z;
5319 info.unaligned = 1;
5320
5321 radv_dispatch(cmd_buffer, &info);
5322 }
5323
5324 void
5325 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)
5326 {
5327 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5328 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5329
5330 cmd_buffer->state.pass = NULL;
5331 cmd_buffer->state.subpass = NULL;
5332 cmd_buffer->state.attachments = NULL;
5333 cmd_buffer->state.framebuffer = NULL;
5334 cmd_buffer->state.subpass_sample_locs = NULL;
5335 }
5336
5337 void radv_CmdEndRenderPass(
5338 VkCommandBuffer commandBuffer)
5339 {
5340 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5341
5342 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5343
5344 radv_cmd_buffer_end_subpass(cmd_buffer);
5345
5346 radv_cmd_buffer_end_render_pass(cmd_buffer);
5347 }
5348
5349 void radv_CmdEndRenderPass2(
5350 VkCommandBuffer commandBuffer,
5351 const VkSubpassEndInfo* pSubpassEndInfo)
5352 {
5353 radv_CmdEndRenderPass(commandBuffer);
5354 }
5355
5356 /*
5357 * For HTILE we have the following interesting clear words:
5358 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5359 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5360 * 0xfffffff0: Clear depth to 1.0
5361 * 0x00000000: Clear depth to 0.0
5362 */
5363 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5364 struct radv_image *image,
5365 const VkImageSubresourceRange *range)
5366 {
5367 assert(range->baseMipLevel == 0);
5368 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5369 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5370 struct radv_cmd_state *state = &cmd_buffer->state;
5371 uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5372 VkClearDepthStencilValue value = {};
5373 struct radv_barrier_data barrier = {};
5374
5375 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5376 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5377
5378 barrier.layout_transitions.init_mask_ram = 1;
5379 radv_describe_layout_transition(cmd_buffer, &barrier);
5380
5381 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
5382
5383 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5384
5385 if (vk_format_is_stencil(image->vk_format))
5386 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5387
5388 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5389
5390 if (radv_image_is_tc_compat_htile(image)) {
5391 /* Initialize the TC-compat metada value to 0 because by
5392 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5393 * need have to conditionally update its value when performing
5394 * a fast depth clear.
5395 */
5396 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5397 }
5398 }
5399
5400 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5401 struct radv_image *image,
5402 VkImageLayout src_layout,
5403 bool src_render_loop,
5404 VkImageLayout dst_layout,
5405 bool dst_render_loop,
5406 unsigned src_queue_mask,
5407 unsigned dst_queue_mask,
5408 const VkImageSubresourceRange *range,
5409 struct radv_sample_locations_state *sample_locs)
5410 {
5411 if (!radv_image_has_htile(image))
5412 return;
5413
5414 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5415 radv_initialize_htile(cmd_buffer, image, range);
5416 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5417 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5418 radv_initialize_htile(cmd_buffer, image, range);
5419 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5420 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5421 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5422 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5423
5424 radv_decompress_depth_stencil(cmd_buffer, image, range,
5425 sample_locs);
5426
5427 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5428 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5429 }
5430 }
5431
5432 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5433 struct radv_image *image,
5434 const VkImageSubresourceRange *range,
5435 uint32_t value)
5436 {
5437 struct radv_cmd_state *state = &cmd_buffer->state;
5438 struct radv_barrier_data barrier = {};
5439
5440 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5441 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5442
5443 barrier.layout_transitions.init_mask_ram = 1;
5444 radv_describe_layout_transition(cmd_buffer, &barrier);
5445
5446 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5447
5448 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5449 }
5450
5451 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5452 struct radv_image *image,
5453 const VkImageSubresourceRange *range)
5454 {
5455 struct radv_cmd_state *state = &cmd_buffer->state;
5456 static const uint32_t fmask_clear_values[4] = {
5457 0x00000000,
5458 0x02020202,
5459 0xE4E4E4E4,
5460 0x76543210
5461 };
5462 uint32_t log2_samples = util_logbase2(image->info.samples);
5463 uint32_t value = fmask_clear_values[log2_samples];
5464 struct radv_barrier_data barrier = {};
5465
5466 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5467 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5468
5469 barrier.layout_transitions.init_mask_ram = 1;
5470 radv_describe_layout_transition(cmd_buffer, &barrier);
5471
5472 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5473
5474 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5475 }
5476
5477 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5478 struct radv_image *image,
5479 const VkImageSubresourceRange *range, uint32_t value)
5480 {
5481 struct radv_cmd_state *state = &cmd_buffer->state;
5482 struct radv_barrier_data barrier = {};
5483 unsigned size = 0;
5484
5485 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5486 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5487
5488 barrier.layout_transitions.init_mask_ram = 1;
5489 radv_describe_layout_transition(cmd_buffer, &barrier);
5490
5491 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5492
5493 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5494 /* When DCC is enabled with mipmaps, some levels might not
5495 * support fast clears and we have to initialize them as "fully
5496 * expanded".
5497 */
5498 /* Compute the size of all fast clearable DCC levels. */
5499 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5500 struct legacy_surf_level *surf_level =
5501 &image->planes[0].surface.u.legacy.level[i];
5502 unsigned dcc_fast_clear_size =
5503 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5504
5505 if (!dcc_fast_clear_size)
5506 break;
5507
5508 size = surf_level->dcc_offset + dcc_fast_clear_size;
5509 }
5510
5511 /* Initialize the mipmap levels without DCC. */
5512 if (size != image->planes[0].surface.dcc_size) {
5513 state->flush_bits |=
5514 radv_fill_buffer(cmd_buffer, image->bo,
5515 image->offset + image->planes[0].surface.dcc_offset + size,
5516 image->planes[0].surface.dcc_size - size,
5517 0xffffffff);
5518 }
5519 }
5520
5521 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5522 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5523 }
5524
5525 /**
5526 * Initialize DCC/FMASK/CMASK metadata for a color image.
5527 */
5528 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5529 struct radv_image *image,
5530 VkImageLayout src_layout,
5531 bool src_render_loop,
5532 VkImageLayout dst_layout,
5533 bool dst_render_loop,
5534 unsigned src_queue_mask,
5535 unsigned dst_queue_mask,
5536 const VkImageSubresourceRange *range)
5537 {
5538 if (radv_image_has_cmask(image)) {
5539 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5540
5541 /* TODO: clarify this. */
5542 if (radv_image_has_fmask(image)) {
5543 value = 0xccccccccu;
5544 }
5545
5546 radv_initialise_cmask(cmd_buffer, image, range, value);
5547 }
5548
5549 if (radv_image_has_fmask(image)) {
5550 radv_initialize_fmask(cmd_buffer, image, range);
5551 }
5552
5553 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5554 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5555 bool need_decompress_pass = false;
5556
5557 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5558 dst_render_loop,
5559 dst_queue_mask)) {
5560 value = 0x20202020u;
5561 need_decompress_pass = true;
5562 }
5563
5564 radv_initialize_dcc(cmd_buffer, image, range, value);
5565
5566 radv_update_fce_metadata(cmd_buffer, image, range,
5567 need_decompress_pass);
5568 }
5569
5570 if (radv_image_has_cmask(image) ||
5571 radv_dcc_enabled(image, range->baseMipLevel)) {
5572 uint32_t color_values[2] = {};
5573 radv_set_color_clear_metadata(cmd_buffer, image, range,
5574 color_values);
5575 }
5576 }
5577
5578 /**
5579 * Handle color image transitions for DCC/FMASK/CMASK.
5580 */
5581 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5582 struct radv_image *image,
5583 VkImageLayout src_layout,
5584 bool src_render_loop,
5585 VkImageLayout dst_layout,
5586 bool dst_render_loop,
5587 unsigned src_queue_mask,
5588 unsigned dst_queue_mask,
5589 const VkImageSubresourceRange *range)
5590 {
5591 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5592 radv_init_color_image_metadata(cmd_buffer, image,
5593 src_layout, src_render_loop,
5594 dst_layout, dst_render_loop,
5595 src_queue_mask, dst_queue_mask,
5596 range);
5597 return;
5598 }
5599
5600 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5601 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5602 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5603 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5604 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5605 radv_decompress_dcc(cmd_buffer, image, range);
5606 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5607 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5608 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5609 }
5610 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5611 bool fce_eliminate = false, fmask_expand = false;
5612
5613 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5614 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5615 fce_eliminate = true;
5616 }
5617
5618 if (radv_image_has_fmask(image)) {
5619 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5620 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5621 /* A FMASK decompress is required before doing
5622 * a MSAA decompress using FMASK.
5623 */
5624 fmask_expand = true;
5625 }
5626 }
5627
5628 if (fce_eliminate || fmask_expand)
5629 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5630
5631 if (fmask_expand) {
5632 struct radv_barrier_data barrier = {};
5633 barrier.layout_transitions.fmask_color_expand = 1;
5634 radv_describe_layout_transition(cmd_buffer, &barrier);
5635
5636 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5637 }
5638 }
5639 }
5640
5641 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5642 struct radv_image *image,
5643 VkImageLayout src_layout,
5644 bool src_render_loop,
5645 VkImageLayout dst_layout,
5646 bool dst_render_loop,
5647 uint32_t src_family,
5648 uint32_t dst_family,
5649 const VkImageSubresourceRange *range,
5650 struct radv_sample_locations_state *sample_locs)
5651 {
5652 if (image->exclusive && src_family != dst_family) {
5653 /* This is an acquire or a release operation and there will be
5654 * a corresponding release/acquire. Do the transition in the
5655 * most flexible queue. */
5656
5657 assert(src_family == cmd_buffer->queue_family_index ||
5658 dst_family == cmd_buffer->queue_family_index);
5659
5660 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5661 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5662 return;
5663
5664 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5665 return;
5666
5667 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5668 (src_family == RADV_QUEUE_GENERAL ||
5669 dst_family == RADV_QUEUE_GENERAL))
5670 return;
5671 }
5672
5673 if (src_layout == dst_layout)
5674 return;
5675
5676 unsigned src_queue_mask =
5677 radv_image_queue_family_mask(image, src_family,
5678 cmd_buffer->queue_family_index);
5679 unsigned dst_queue_mask =
5680 radv_image_queue_family_mask(image, dst_family,
5681 cmd_buffer->queue_family_index);
5682
5683 if (vk_format_is_depth(image->vk_format)) {
5684 radv_handle_depth_image_transition(cmd_buffer, image,
5685 src_layout, src_render_loop,
5686 dst_layout, dst_render_loop,
5687 src_queue_mask, dst_queue_mask,
5688 range, sample_locs);
5689 } else {
5690 radv_handle_color_image_transition(cmd_buffer, image,
5691 src_layout, src_render_loop,
5692 dst_layout, dst_render_loop,
5693 src_queue_mask, dst_queue_mask,
5694 range);
5695 }
5696 }
5697
5698 struct radv_barrier_info {
5699 enum rgp_barrier_reason reason;
5700 uint32_t eventCount;
5701 const VkEvent *pEvents;
5702 VkPipelineStageFlags srcStageMask;
5703 VkPipelineStageFlags dstStageMask;
5704 };
5705
5706 static void
5707 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5708 uint32_t memoryBarrierCount,
5709 const VkMemoryBarrier *pMemoryBarriers,
5710 uint32_t bufferMemoryBarrierCount,
5711 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5712 uint32_t imageMemoryBarrierCount,
5713 const VkImageMemoryBarrier *pImageMemoryBarriers,
5714 const struct radv_barrier_info *info)
5715 {
5716 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5717 enum radv_cmd_flush_bits src_flush_bits = 0;
5718 enum radv_cmd_flush_bits dst_flush_bits = 0;
5719
5720 radv_describe_barrier_start(cmd_buffer, info->reason);
5721
5722 for (unsigned i = 0; i < info->eventCount; ++i) {
5723 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5724 uint64_t va = radv_buffer_get_va(event->bo);
5725
5726 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5727
5728 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5729
5730 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5731 assert(cmd_buffer->cs->cdw <= cdw_max);
5732 }
5733
5734 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5735 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5736 NULL);
5737 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5738 NULL);
5739 }
5740
5741 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5742 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5743 NULL);
5744 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5745 NULL);
5746 }
5747
5748 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5749 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5750
5751 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5752 image);
5753 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5754 image);
5755 }
5756
5757 /* The Vulkan spec 1.1.98 says:
5758 *
5759 * "An execution dependency with only
5760 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5761 * will only prevent that stage from executing in subsequently
5762 * submitted commands. As this stage does not perform any actual
5763 * execution, this is not observable - in effect, it does not delay
5764 * processing of subsequent commands. Similarly an execution dependency
5765 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5766 * will effectively not wait for any prior commands to complete."
5767 */
5768 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5769 radv_stage_flush(cmd_buffer, info->srcStageMask);
5770 cmd_buffer->state.flush_bits |= src_flush_bits;
5771
5772 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5773 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5774
5775 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5776 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5777 SAMPLE_LOCATIONS_INFO_EXT);
5778 struct radv_sample_locations_state sample_locations = {};
5779
5780 if (sample_locs_info) {
5781 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5782 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5783 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5784 sample_locations.count = sample_locs_info->sampleLocationsCount;
5785 typed_memcpy(&sample_locations.locations[0],
5786 sample_locs_info->pSampleLocations,
5787 sample_locs_info->sampleLocationsCount);
5788 }
5789
5790 radv_handle_image_transition(cmd_buffer, image,
5791 pImageMemoryBarriers[i].oldLayout,
5792 false, /* Outside of a renderpass we are never in a renderloop */
5793 pImageMemoryBarriers[i].newLayout,
5794 false, /* Outside of a renderpass we are never in a renderloop */
5795 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5796 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5797 &pImageMemoryBarriers[i].subresourceRange,
5798 sample_locs_info ? &sample_locations : NULL);
5799 }
5800
5801 /* Make sure CP DMA is idle because the driver might have performed a
5802 * DMA operation for copying or filling buffers/images.
5803 */
5804 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5805 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5806 si_cp_dma_wait_for_idle(cmd_buffer);
5807
5808 cmd_buffer->state.flush_bits |= dst_flush_bits;
5809
5810 radv_describe_barrier_end(cmd_buffer);
5811 }
5812
5813 void radv_CmdPipelineBarrier(
5814 VkCommandBuffer commandBuffer,
5815 VkPipelineStageFlags srcStageMask,
5816 VkPipelineStageFlags destStageMask,
5817 VkBool32 byRegion,
5818 uint32_t memoryBarrierCount,
5819 const VkMemoryBarrier* pMemoryBarriers,
5820 uint32_t bufferMemoryBarrierCount,
5821 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5822 uint32_t imageMemoryBarrierCount,
5823 const VkImageMemoryBarrier* pImageMemoryBarriers)
5824 {
5825 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5826 struct radv_barrier_info info;
5827
5828 info.reason = RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER;
5829 info.eventCount = 0;
5830 info.pEvents = NULL;
5831 info.srcStageMask = srcStageMask;
5832 info.dstStageMask = destStageMask;
5833
5834 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5835 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5836 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5837 }
5838
5839
5840 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5841 struct radv_event *event,
5842 VkPipelineStageFlags stageMask,
5843 unsigned value)
5844 {
5845 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5846 uint64_t va = radv_buffer_get_va(event->bo);
5847
5848 si_emit_cache_flush(cmd_buffer);
5849
5850 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5851
5852 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5853
5854 /* Flags that only require a top-of-pipe event. */
5855 VkPipelineStageFlags top_of_pipe_flags =
5856 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5857
5858 /* Flags that only require a post-index-fetch event. */
5859 VkPipelineStageFlags post_index_fetch_flags =
5860 top_of_pipe_flags |
5861 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5862 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5863
5864 /* Make sure CP DMA is idle because the driver might have performed a
5865 * DMA operation for copying or filling buffers/images.
5866 */
5867 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5868 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5869 si_cp_dma_wait_for_idle(cmd_buffer);
5870
5871 /* TODO: Emit EOS events for syncing PS/CS stages. */
5872
5873 if (!(stageMask & ~top_of_pipe_flags)) {
5874 /* Just need to sync the PFP engine. */
5875 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5876 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5877 S_370_WR_CONFIRM(1) |
5878 S_370_ENGINE_SEL(V_370_PFP));
5879 radeon_emit(cs, va);
5880 radeon_emit(cs, va >> 32);
5881 radeon_emit(cs, value);
5882 } else if (!(stageMask & ~post_index_fetch_flags)) {
5883 /* Sync ME because PFP reads index and indirect buffers. */
5884 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5885 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5886 S_370_WR_CONFIRM(1) |
5887 S_370_ENGINE_SEL(V_370_ME));
5888 radeon_emit(cs, va);
5889 radeon_emit(cs, va >> 32);
5890 radeon_emit(cs, value);
5891 } else {
5892 /* Otherwise, sync all prior GPU work using an EOP event. */
5893 si_cs_emit_write_event_eop(cs,
5894 cmd_buffer->device->physical_device->rad_info.chip_class,
5895 radv_cmd_buffer_uses_mec(cmd_buffer),
5896 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5897 EOP_DST_SEL_MEM,
5898 EOP_DATA_SEL_VALUE_32BIT, va, value,
5899 cmd_buffer->gfx9_eop_bug_va);
5900 }
5901
5902 assert(cmd_buffer->cs->cdw <= cdw_max);
5903 }
5904
5905 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5906 VkEvent _event,
5907 VkPipelineStageFlags stageMask)
5908 {
5909 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5910 RADV_FROM_HANDLE(radv_event, event, _event);
5911
5912 write_event(cmd_buffer, event, stageMask, 1);
5913 }
5914
5915 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5916 VkEvent _event,
5917 VkPipelineStageFlags stageMask)
5918 {
5919 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5920 RADV_FROM_HANDLE(radv_event, event, _event);
5921
5922 write_event(cmd_buffer, event, stageMask, 0);
5923 }
5924
5925 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5926 uint32_t eventCount,
5927 const VkEvent* pEvents,
5928 VkPipelineStageFlags srcStageMask,
5929 VkPipelineStageFlags dstStageMask,
5930 uint32_t memoryBarrierCount,
5931 const VkMemoryBarrier* pMemoryBarriers,
5932 uint32_t bufferMemoryBarrierCount,
5933 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5934 uint32_t imageMemoryBarrierCount,
5935 const VkImageMemoryBarrier* pImageMemoryBarriers)
5936 {
5937 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5938 struct radv_barrier_info info;
5939
5940 info.reason = RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS;
5941 info.eventCount = eventCount;
5942 info.pEvents = pEvents;
5943 info.srcStageMask = 0;
5944
5945 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5946 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5947 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5948 }
5949
5950
5951 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5952 uint32_t deviceMask)
5953 {
5954 /* No-op */
5955 }
5956
5957 /* VK_EXT_conditional_rendering */
5958 void radv_CmdBeginConditionalRenderingEXT(
5959 VkCommandBuffer commandBuffer,
5960 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5961 {
5962 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5963 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5964 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5965 bool draw_visible = true;
5966 uint64_t pred_value = 0;
5967 uint64_t va, new_va;
5968 unsigned pred_offset;
5969
5970 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5971
5972 /* By default, if the 32-bit value at offset in buffer memory is zero,
5973 * then the rendering commands are discarded, otherwise they are
5974 * executed as normal. If the inverted flag is set, all commands are
5975 * discarded if the value is non zero.
5976 */
5977 if (pConditionalRenderingBegin->flags &
5978 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5979 draw_visible = false;
5980 }
5981
5982 si_emit_cache_flush(cmd_buffer);
5983
5984 /* From the Vulkan spec 1.1.107:
5985 *
5986 * "If the 32-bit value at offset in buffer memory is zero, then the
5987 * rendering commands are discarded, otherwise they are executed as
5988 * normal. If the value of the predicate in buffer memory changes while
5989 * conditional rendering is active, the rendering commands may be
5990 * discarded in an implementation-dependent way. Some implementations
5991 * may latch the value of the predicate upon beginning conditional
5992 * rendering while others may read it before every rendering command."
5993 *
5994 * But, the AMD hardware treats the predicate as a 64-bit value which
5995 * means we need a workaround in the driver. Luckily, it's not required
5996 * to support if the value changes when predication is active.
5997 *
5998 * The workaround is as follows:
5999 * 1) allocate a 64-value in the upload BO and initialize it to 0
6000 * 2) copy the 32-bit predicate value to the upload BO
6001 * 3) use the new allocated VA address for predication
6002 *
6003 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
6004 * in ME (+ sync PFP) instead of PFP.
6005 */
6006 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
6007
6008 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
6009
6010 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6011 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
6012 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6013 COPY_DATA_WR_CONFIRM);
6014 radeon_emit(cs, va);
6015 radeon_emit(cs, va >> 32);
6016 radeon_emit(cs, new_va);
6017 radeon_emit(cs, new_va >> 32);
6018
6019 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
6020 radeon_emit(cs, 0);
6021
6022 /* Enable predication for this command buffer. */
6023 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
6024 cmd_buffer->state.predicating = true;
6025
6026 /* Store conditional rendering user info. */
6027 cmd_buffer->state.predication_type = draw_visible;
6028 cmd_buffer->state.predication_va = new_va;
6029 }
6030
6031 void radv_CmdEndConditionalRenderingEXT(
6032 VkCommandBuffer commandBuffer)
6033 {
6034 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6035
6036 /* Disable predication for this command buffer. */
6037 si_emit_set_predication_state(cmd_buffer, false, 0);
6038 cmd_buffer->state.predicating = false;
6039
6040 /* Reset conditional rendering user info. */
6041 cmd_buffer->state.predication_type = -1;
6042 cmd_buffer->state.predication_va = 0;
6043 }
6044
6045 /* VK_EXT_transform_feedback */
6046 void radv_CmdBindTransformFeedbackBuffersEXT(
6047 VkCommandBuffer commandBuffer,
6048 uint32_t firstBinding,
6049 uint32_t bindingCount,
6050 const VkBuffer* pBuffers,
6051 const VkDeviceSize* pOffsets,
6052 const VkDeviceSize* pSizes)
6053 {
6054 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6055 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6056 uint8_t enabled_mask = 0;
6057
6058 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
6059 for (uint32_t i = 0; i < bindingCount; i++) {
6060 uint32_t idx = firstBinding + i;
6061
6062 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
6063 sb[idx].offset = pOffsets[i];
6064
6065 if (!pSizes || pSizes[i] == VK_WHOLE_SIZE) {
6066 sb[idx].size = sb[idx].buffer->size - sb[idx].offset;
6067 } else {
6068 sb[idx].size = pSizes[i];
6069 }
6070
6071 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
6072 sb[idx].buffer->bo);
6073
6074 enabled_mask |= 1 << idx;
6075 }
6076
6077 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
6078
6079 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
6080 }
6081
6082 static void
6083 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
6084 {
6085 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6086 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6087
6088 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
6089 radeon_emit(cs,
6090 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
6091 S_028B94_RAST_STREAM(0) |
6092 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
6093 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
6094 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
6095 radeon_emit(cs, so->hw_enabled_mask &
6096 so->enabled_stream_buffers_mask);
6097
6098 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6099 }
6100
6101 static void
6102 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
6103 {
6104 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6105 bool old_streamout_enabled = so->streamout_enabled;
6106 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
6107
6108 so->streamout_enabled = enable;
6109
6110 so->hw_enabled_mask = so->enabled_mask |
6111 (so->enabled_mask << 4) |
6112 (so->enabled_mask << 8) |
6113 (so->enabled_mask << 12);
6114
6115 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
6116 ((old_streamout_enabled != so->streamout_enabled) ||
6117 (old_hw_enabled_mask != so->hw_enabled_mask)))
6118 radv_emit_streamout_enable(cmd_buffer);
6119
6120 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6121 cmd_buffer->gds_needed = true;
6122 cmd_buffer->gds_oa_needed = true;
6123 }
6124 }
6125
6126 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
6127 {
6128 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6129 unsigned reg_strmout_cntl;
6130
6131 /* The register is at different places on different ASICs. */
6132 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
6133 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
6134 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
6135 } else {
6136 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
6137 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
6138 }
6139
6140 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
6141 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
6142
6143 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
6144 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
6145 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
6146 radeon_emit(cs, 0);
6147 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6148 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6149 radeon_emit(cs, 4); /* poll interval */
6150 }
6151
6152 static void
6153 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6154 uint32_t firstCounterBuffer,
6155 uint32_t counterBufferCount,
6156 const VkBuffer *pCounterBuffers,
6157 const VkDeviceSize *pCounterBufferOffsets)
6158
6159 {
6160 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
6161 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6162 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6163 uint32_t i;
6164
6165 radv_flush_vgt_streamout(cmd_buffer);
6166
6167 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6168 for_each_bit(i, so->enabled_mask) {
6169 int32_t counter_buffer_idx = i - firstCounterBuffer;
6170 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6171 counter_buffer_idx = -1;
6172
6173 /* AMD GCN binds streamout buffers as shader resources.
6174 * VGT only counts primitives and tells the shader through
6175 * SGPRs what to do.
6176 */
6177 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
6178 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
6179 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
6180
6181 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6182
6183 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6184 /* The array of counter buffers is optional. */
6185 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6186 uint64_t va = radv_buffer_get_va(buffer->bo);
6187
6188 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6189
6190 /* Append */
6191 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6192 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6193 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6194 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
6195 radeon_emit(cs, 0); /* unused */
6196 radeon_emit(cs, 0); /* unused */
6197 radeon_emit(cs, va); /* src address lo */
6198 radeon_emit(cs, va >> 32); /* src address hi */
6199
6200 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6201 } else {
6202 /* Start from the beginning. */
6203 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6204 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6205 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6206 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
6207 radeon_emit(cs, 0); /* unused */
6208 radeon_emit(cs, 0); /* unused */
6209 radeon_emit(cs, 0); /* unused */
6210 radeon_emit(cs, 0); /* unused */
6211 }
6212 }
6213
6214 radv_set_streamout_enable(cmd_buffer, true);
6215 }
6216
6217 static void
6218 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
6219 uint32_t firstCounterBuffer,
6220 uint32_t counterBufferCount,
6221 const VkBuffer *pCounterBuffers,
6222 const VkDeviceSize *pCounterBufferOffsets)
6223 {
6224 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6225 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
6226 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6227 uint32_t i;
6228
6229 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6230 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6231
6232 /* Sync because the next streamout operation will overwrite GDS and we
6233 * have to make sure it's idle.
6234 * TODO: Improve by tracking if there is a streamout operation in
6235 * flight.
6236 */
6237 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
6238 si_emit_cache_flush(cmd_buffer);
6239
6240 for_each_bit(i, so->enabled_mask) {
6241 int32_t counter_buffer_idx = i - firstCounterBuffer;
6242 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6243 counter_buffer_idx = -1;
6244
6245 bool append = counter_buffer_idx >= 0 &&
6246 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
6247 uint64_t va = 0;
6248
6249 if (append) {
6250 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6251
6252 va += radv_buffer_get_va(buffer->bo);
6253 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6254
6255 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6256 }
6257
6258 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6259 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6260 S_411_DST_SEL(V_411_GDS) |
6261 S_411_CP_SYNC(i == last_target));
6262 radeon_emit(cs, va);
6263 radeon_emit(cs, va >> 32);
6264 radeon_emit(cs, 4 * i); /* destination in GDS */
6265 radeon_emit(cs, 0);
6266 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6267 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6268 }
6269
6270 radv_set_streamout_enable(cmd_buffer, true);
6271 }
6272
6273 void radv_CmdBeginTransformFeedbackEXT(
6274 VkCommandBuffer commandBuffer,
6275 uint32_t firstCounterBuffer,
6276 uint32_t counterBufferCount,
6277 const VkBuffer* pCounterBuffers,
6278 const VkDeviceSize* pCounterBufferOffsets)
6279 {
6280 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6281
6282 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6283 gfx10_emit_streamout_begin(cmd_buffer,
6284 firstCounterBuffer, counterBufferCount,
6285 pCounterBuffers, pCounterBufferOffsets);
6286 } else {
6287 radv_emit_streamout_begin(cmd_buffer,
6288 firstCounterBuffer, counterBufferCount,
6289 pCounterBuffers, pCounterBufferOffsets);
6290 }
6291 }
6292
6293 static void
6294 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6295 uint32_t firstCounterBuffer,
6296 uint32_t counterBufferCount,
6297 const VkBuffer *pCounterBuffers,
6298 const VkDeviceSize *pCounterBufferOffsets)
6299 {
6300 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6301 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6302 uint32_t i;
6303
6304 radv_flush_vgt_streamout(cmd_buffer);
6305
6306 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6307 for_each_bit(i, so->enabled_mask) {
6308 int32_t counter_buffer_idx = i - firstCounterBuffer;
6309 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6310 counter_buffer_idx = -1;
6311
6312 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6313 /* The array of counters buffer is optional. */
6314 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6315 uint64_t va = radv_buffer_get_va(buffer->bo);
6316
6317 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6318
6319 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6320 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6321 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6322 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6323 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6324 radeon_emit(cs, va); /* dst address lo */
6325 radeon_emit(cs, va >> 32); /* dst address hi */
6326 radeon_emit(cs, 0); /* unused */
6327 radeon_emit(cs, 0); /* unused */
6328
6329 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6330 }
6331
6332 /* Deactivate transform feedback by zeroing the buffer size.
6333 * The counters (primitives generated, primitives emitted) may
6334 * be enabled even if there is not buffer bound. This ensures
6335 * that the primitives-emitted query won't increment.
6336 */
6337 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6338
6339 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6340 }
6341
6342 radv_set_streamout_enable(cmd_buffer, false);
6343 }
6344
6345 static void
6346 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6347 uint32_t firstCounterBuffer,
6348 uint32_t counterBufferCount,
6349 const VkBuffer *pCounterBuffers,
6350 const VkDeviceSize *pCounterBufferOffsets)
6351 {
6352 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6353 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6354 uint32_t i;
6355
6356 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6357 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6358
6359 for_each_bit(i, so->enabled_mask) {
6360 int32_t counter_buffer_idx = i - firstCounterBuffer;
6361 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6362 counter_buffer_idx = -1;
6363
6364 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6365 /* The array of counters buffer is optional. */
6366 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6367 uint64_t va = radv_buffer_get_va(buffer->bo);
6368
6369 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6370
6371 si_cs_emit_write_event_eop(cs,
6372 cmd_buffer->device->physical_device->rad_info.chip_class,
6373 radv_cmd_buffer_uses_mec(cmd_buffer),
6374 V_028A90_PS_DONE, 0,
6375 EOP_DST_SEL_TC_L2,
6376 EOP_DATA_SEL_GDS,
6377 va, EOP_DATA_GDS(i, 1), 0);
6378
6379 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6380 }
6381 }
6382
6383 radv_set_streamout_enable(cmd_buffer, false);
6384 }
6385
6386 void radv_CmdEndTransformFeedbackEXT(
6387 VkCommandBuffer commandBuffer,
6388 uint32_t firstCounterBuffer,
6389 uint32_t counterBufferCount,
6390 const VkBuffer* pCounterBuffers,
6391 const VkDeviceSize* pCounterBufferOffsets)
6392 {
6393 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6394
6395 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6396 gfx10_emit_streamout_end(cmd_buffer,
6397 firstCounterBuffer, counterBufferCount,
6398 pCounterBuffers, pCounterBufferOffsets);
6399 } else {
6400 radv_emit_streamout_end(cmd_buffer,
6401 firstCounterBuffer, counterBufferCount,
6402 pCounterBuffers, pCounterBufferOffsets);
6403 }
6404 }
6405
6406 void radv_CmdDrawIndirectByteCountEXT(
6407 VkCommandBuffer commandBuffer,
6408 uint32_t instanceCount,
6409 uint32_t firstInstance,
6410 VkBuffer _counterBuffer,
6411 VkDeviceSize counterBufferOffset,
6412 uint32_t counterOffset,
6413 uint32_t vertexStride)
6414 {
6415 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6416 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6417 struct radv_draw_info info = {};
6418
6419 info.instance_count = instanceCount;
6420 info.first_instance = firstInstance;
6421 info.strmout_buffer = counterBuffer;
6422 info.strmout_buffer_offset = counterBufferOffset;
6423 info.stride = vertexStride;
6424
6425 radv_draw(cmd_buffer, &info);
6426 }
6427
6428 /* VK_AMD_buffer_marker */
6429 void radv_CmdWriteBufferMarkerAMD(
6430 VkCommandBuffer commandBuffer,
6431 VkPipelineStageFlagBits pipelineStage,
6432 VkBuffer dstBuffer,
6433 VkDeviceSize dstOffset,
6434 uint32_t marker)
6435 {
6436 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6437 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6438 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6439 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6440
6441 si_emit_cache_flush(cmd_buffer);
6442
6443 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
6444
6445 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6446 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6447 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6448 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6449 COPY_DATA_WR_CONFIRM);
6450 radeon_emit(cs, marker);
6451 radeon_emit(cs, 0);
6452 radeon_emit(cs, va);
6453 radeon_emit(cs, va >> 32);
6454 } else {
6455 si_cs_emit_write_event_eop(cs,
6456 cmd_buffer->device->physical_device->rad_info.chip_class,
6457 radv_cmd_buffer_uses_mec(cmd_buffer),
6458 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6459 EOP_DST_SEL_MEM,
6460 EOP_DATA_SEL_VALUE_32BIT,
6461 va, marker,
6462 cmd_buffer->gfx9_eop_bug_va);
6463 }
6464
6465 assert(cmd_buffer->cs->cdw <= cdw_max);
6466 }