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radv: Add LLVM version to the device name string
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
96 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
97 src->viewport.count * sizeof(VkViewport))) {
98 typed_memcpy(dest->viewport.viewports,
99 src->viewport.viewports,
100 src->viewport.count);
101 dest_mask |= 1 << VK_DYNAMIC_STATE_VIEWPORT;
102 }
103 }
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
106 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
107 src->scissor.count * sizeof(VkRect2D))) {
108 typed_memcpy(dest->scissor.scissors,
109 src->scissor.scissors, src->scissor.count);
110 dest_mask |= 1 << VK_DYNAMIC_STATE_SCISSOR;
111 }
112 }
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
115 if (dest->line_width != src->line_width) {
116 dest->line_width = src->line_width;
117 dest_mask |= 1 << VK_DYNAMIC_STATE_LINE_WIDTH;
118 }
119 }
120
121 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
122 if (memcmp(&dest->depth_bias, &src->depth_bias,
123 sizeof(src->depth_bias))) {
124 dest->depth_bias = src->depth_bias;
125 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS;
126 }
127 }
128
129 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
130 if (memcmp(&dest->blend_constants, &src->blend_constants,
131 sizeof(src->blend_constants))) {
132 typed_memcpy(dest->blend_constants,
133 src->blend_constants, 4);
134 dest_mask |= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS;
135 }
136 }
137
138 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
139 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
140 sizeof(src->depth_bounds))) {
141 dest->depth_bounds = src->depth_bounds;
142 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS;
143 }
144 }
145
146 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
147 if (memcmp(&dest->stencil_compare_mask,
148 &src->stencil_compare_mask,
149 sizeof(src->stencil_compare_mask))) {
150 dest->stencil_compare_mask = src->stencil_compare_mask;
151 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK;
152 }
153 }
154
155 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
156 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
157 sizeof(src->stencil_write_mask))) {
158 dest->stencil_write_mask = src->stencil_write_mask;
159 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK;
160 }
161 }
162
163 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
164 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
165 sizeof(src->stencil_reference))) {
166 dest->stencil_reference = src->stencil_reference;
167 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE;
168 }
169 }
170
171 cmd_buffer->state.dirty |= dest_mask;
172 }
173
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
175 {
176 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
177 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
178 }
179
180 enum ring_type radv_queue_family_to_ring(int f) {
181 switch (f) {
182 case RADV_QUEUE_GENERAL:
183 return RING_GFX;
184 case RADV_QUEUE_COMPUTE:
185 return RING_COMPUTE;
186 case RADV_QUEUE_TRANSFER:
187 return RING_DMA;
188 default:
189 unreachable("Unknown queue family");
190 }
191 }
192
193 static VkResult radv_create_cmd_buffer(
194 struct radv_device * device,
195 struct radv_cmd_pool * pool,
196 VkCommandBufferLevel level,
197 VkCommandBuffer* pCommandBuffer)
198 {
199 struct radv_cmd_buffer *cmd_buffer;
200 unsigned ring;
201 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
203 if (cmd_buffer == NULL)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
205
206 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
207 cmd_buffer->device = device;
208 cmd_buffer->pool = pool;
209 cmd_buffer->level = level;
210
211 if (pool) {
212 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
213 cmd_buffer->queue_family_index = pool->queue_family_index;
214
215 } else {
216 /* Init the pool_link so we can safefly call list_del when we destroy
217 * the command buffer
218 */
219 list_inithead(&cmd_buffer->pool_link);
220 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
221 }
222
223 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
224
225 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
226 if (!cmd_buffer->cs) {
227 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
228 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
229 }
230
231 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
232
233 list_inithead(&cmd_buffer->upload.list);
234
235 return VK_SUCCESS;
236 }
237
238 static void
239 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
240 {
241 list_del(&cmd_buffer->pool_link);
242
243 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
244 &cmd_buffer->upload.list, list) {
245 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
246 list_del(&up->list);
247 free(up);
248 }
249
250 if (cmd_buffer->upload.upload_bo)
251 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
252 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
253 free(cmd_buffer->push_descriptors.set.mapped_ptr);
254 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
255 }
256
257 static VkResult
258 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
259 {
260
261 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
262
263 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
264 &cmd_buffer->upload.list, list) {
265 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
266 list_del(&up->list);
267 free(up);
268 }
269
270 cmd_buffer->push_constant_stages = 0;
271 cmd_buffer->scratch_size_needed = 0;
272 cmd_buffer->compute_scratch_size_needed = 0;
273 cmd_buffer->esgs_ring_size_needed = 0;
274 cmd_buffer->gsvs_ring_size_needed = 0;
275 cmd_buffer->tess_rings_needed = false;
276 cmd_buffer->sample_positions_needed = false;
277
278 if (cmd_buffer->upload.upload_bo)
279 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
280 cmd_buffer->upload.upload_bo, 8);
281 cmd_buffer->upload.offset = 0;
282
283 cmd_buffer->record_result = VK_SUCCESS;
284
285 cmd_buffer->ring_offsets_idx = -1;
286
287 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
288 void *fence_ptr;
289 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
290 &cmd_buffer->gfx9_fence_offset,
291 &fence_ptr);
292 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
293 }
294
295 return cmd_buffer->record_result;
296 }
297
298 static bool
299 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
300 uint64_t min_needed)
301 {
302 uint64_t new_size;
303 struct radeon_winsys_bo *bo;
304 struct radv_cmd_buffer_upload *upload;
305 struct radv_device *device = cmd_buffer->device;
306
307 new_size = MAX2(min_needed, 16 * 1024);
308 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
309
310 bo = device->ws->buffer_create(device->ws,
311 new_size, 4096,
312 RADEON_DOMAIN_GTT,
313 RADEON_FLAG_CPU_ACCESS|
314 RADEON_FLAG_NO_INTERPROCESS_SHARING);
315
316 if (!bo) {
317 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
318 return false;
319 }
320
321 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
322 if (cmd_buffer->upload.upload_bo) {
323 upload = malloc(sizeof(*upload));
324
325 if (!upload) {
326 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
327 device->ws->buffer_destroy(bo);
328 return false;
329 }
330
331 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
332 list_add(&upload->list, &cmd_buffer->upload.list);
333 }
334
335 cmd_buffer->upload.upload_bo = bo;
336 cmd_buffer->upload.size = new_size;
337 cmd_buffer->upload.offset = 0;
338 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
339
340 if (!cmd_buffer->upload.map) {
341 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
342 return false;
343 }
344
345 return true;
346 }
347
348 bool
349 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
350 unsigned size,
351 unsigned alignment,
352 unsigned *out_offset,
353 void **ptr)
354 {
355 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
356 if (offset + size > cmd_buffer->upload.size) {
357 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
358 return false;
359 offset = 0;
360 }
361
362 *out_offset = offset;
363 *ptr = cmd_buffer->upload.map + offset;
364
365 cmd_buffer->upload.offset = offset + size;
366 return true;
367 }
368
369 bool
370 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
371 unsigned size, unsigned alignment,
372 const void *data, unsigned *out_offset)
373 {
374 uint8_t *ptr;
375
376 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
377 out_offset, (void **)&ptr))
378 return false;
379
380 if (ptr)
381 memcpy(ptr, data, size);
382
383 return true;
384 }
385
386 static void
387 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
388 unsigned count, const uint32_t *data)
389 {
390 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
391 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
392 S_370_WR_CONFIRM(1) |
393 S_370_ENGINE_SEL(V_370_ME));
394 radeon_emit(cs, va);
395 radeon_emit(cs, va >> 32);
396 radeon_emit_array(cs, data, count);
397 }
398
399 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
400 {
401 struct radv_device *device = cmd_buffer->device;
402 struct radeon_winsys_cs *cs = cmd_buffer->cs;
403 uint64_t va;
404
405 va = radv_buffer_get_va(device->trace_bo);
406 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
407 va += 4;
408
409 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
410
411 ++cmd_buffer->state.trace_id;
412 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
413 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
414 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
415 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
416 }
417
418 static void
419 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
420 {
421 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
422 enum radv_cmd_flush_bits flags;
423
424 /* Force wait for graphics/compute engines to be idle. */
425 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
426 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
427
428 si_cs_emit_cache_flush(cmd_buffer->cs, false,
429 cmd_buffer->device->physical_device->rad_info.chip_class,
430 NULL, 0,
431 radv_cmd_buffer_uses_mec(cmd_buffer),
432 flags);
433 }
434
435 if (unlikely(cmd_buffer->device->trace_bo))
436 radv_cmd_buffer_trace_emit(cmd_buffer);
437 }
438
439 static void
440 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
441 struct radv_pipeline *pipeline, enum ring_type ring)
442 {
443 struct radv_device *device = cmd_buffer->device;
444 struct radeon_winsys_cs *cs = cmd_buffer->cs;
445 uint32_t data[2];
446 uint64_t va;
447
448 va = radv_buffer_get_va(device->trace_bo);
449
450 switch (ring) {
451 case RING_GFX:
452 va += 8;
453 break;
454 case RING_COMPUTE:
455 va += 16;
456 break;
457 default:
458 assert(!"invalid ring type");
459 }
460
461 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
462 cmd_buffer->cs, 6);
463
464 data[0] = (uintptr_t)pipeline;
465 data[1] = (uintptr_t)pipeline >> 32;
466
467 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
468 radv_emit_write_data_packet(cs, va, 2, data);
469 }
470
471 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
472 struct radv_descriptor_set *set,
473 unsigned idx)
474 {
475 cmd_buffer->descriptors[idx] = set;
476 if (set)
477 cmd_buffer->state.valid_descriptors |= (1u << idx);
478 else
479 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
480 cmd_buffer->state.descriptors_dirty |= (1u << idx);
481
482 }
483
484 static void
485 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
486 {
487 struct radv_device *device = cmd_buffer->device;
488 struct radeon_winsys_cs *cs = cmd_buffer->cs;
489 uint32_t data[MAX_SETS * 2] = {};
490 uint64_t va;
491 unsigned i;
492 va = radv_buffer_get_va(device->trace_bo) + 24;
493
494 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
495 cmd_buffer->cs, 4 + MAX_SETS * 2);
496
497 for_each_bit(i, cmd_buffer->state.valid_descriptors) {
498 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
499 data[i * 2] = (uintptr_t)set;
500 data[i * 2 + 1] = (uintptr_t)set >> 32;
501 }
502
503 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
504 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
505 }
506
507 static void
508 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
509 struct radv_pipeline *pipeline)
510 {
511 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
512 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
513 8);
514 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
515 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
516
517 if (cmd_buffer->device->physical_device->has_rbplus) {
518
519 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
520 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
521
522 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
523 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
524 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
525 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
526 }
527 }
528
529 static void
530 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
531 struct radv_pipeline *pipeline)
532 {
533 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
534 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
535 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
536
537 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
538 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
539 }
540
541 struct ac_userdata_info *
542 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
543 gl_shader_stage stage,
544 int idx)
545 {
546 if (stage == MESA_SHADER_VERTEX) {
547 if (pipeline->shaders[MESA_SHADER_VERTEX])
548 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
549 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
550 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
551 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
552 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
553 } else if (stage == MESA_SHADER_TESS_EVAL) {
554 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
555 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
556 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
557 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
558 }
559 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
560 }
561
562 static void
563 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
564 struct radv_pipeline *pipeline,
565 gl_shader_stage stage,
566 int idx, uint64_t va)
567 {
568 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
569 uint32_t base_reg = pipeline->user_data_0[stage];
570 if (loc->sgpr_idx == -1)
571 return;
572 assert(loc->num_sgprs == 2);
573 assert(!loc->indirect);
574 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
575 radeon_emit(cmd_buffer->cs, va);
576 radeon_emit(cmd_buffer->cs, va >> 32);
577 }
578
579 static void
580 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
581 struct radv_pipeline *pipeline)
582 {
583 int num_samples = pipeline->graphics.ms.num_samples;
584 struct radv_multisample_state *ms = &pipeline->graphics.ms;
585 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
586
587 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
588 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
589 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
590
591 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
592 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
593
594 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
595 return;
596
597 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
598 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
599 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
600
601 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
602
603 /* GFX9: Flush DFSM when the AA mode changes. */
604 if (cmd_buffer->device->dfsm_allowed) {
605 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
606 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
607 }
608 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
609 uint32_t offset;
610 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
611 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
612 if (loc->sgpr_idx == -1)
613 return;
614 assert(loc->num_sgprs == 1);
615 assert(!loc->indirect);
616 switch (num_samples) {
617 default:
618 offset = 0;
619 break;
620 case 2:
621 offset = 1;
622 break;
623 case 4:
624 offset = 3;
625 break;
626 case 8:
627 offset = 7;
628 break;
629 case 16:
630 offset = 15;
631 break;
632 }
633
634 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
635 cmd_buffer->sample_positions_needed = true;
636 }
637 }
638
639 static void
640 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
641 struct radv_pipeline *pipeline)
642 {
643 struct radv_raster_state *raster = &pipeline->graphics.raster;
644
645 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
646 raster->pa_cl_clip_cntl);
647 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
648 raster->spi_interp_control);
649 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
650 raster->pa_su_vtx_cntl);
651 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
652 raster->pa_su_sc_mode_cntl);
653 }
654
655 static inline void
656 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
657 unsigned size)
658 {
659 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
660 si_cp_dma_prefetch(cmd_buffer, va, size);
661 }
662
663 static void
664 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
665 {
666 if (cmd_buffer->state.vb_prefetch_dirty) {
667 radv_emit_prefetch_TC_L2_async(cmd_buffer,
668 cmd_buffer->state.vb_va,
669 cmd_buffer->state.vb_size);
670 cmd_buffer->state.vb_prefetch_dirty = false;
671 }
672 }
673
674 static void
675 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
676 struct radv_shader_variant *shader)
677 {
678 struct radeon_winsys *ws = cmd_buffer->device->ws;
679 struct radeon_winsys_cs *cs = cmd_buffer->cs;
680 uint64_t va;
681
682 if (!shader)
683 return;
684
685 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
686
687 radv_cs_add_buffer(ws, cs, shader->bo, 8);
688 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
689 }
690
691 static void
692 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
693 struct radv_pipeline *pipeline)
694 {
695 radv_emit_shader_prefetch(cmd_buffer,
696 pipeline->shaders[MESA_SHADER_VERTEX]);
697 radv_emit_VBO_descriptors_prefetch(cmd_buffer);
698 radv_emit_shader_prefetch(cmd_buffer,
699 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
700 radv_emit_shader_prefetch(cmd_buffer,
701 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
702 radv_emit_shader_prefetch(cmd_buffer,
703 pipeline->shaders[MESA_SHADER_GEOMETRY]);
704 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
705 radv_emit_shader_prefetch(cmd_buffer,
706 pipeline->shaders[MESA_SHADER_FRAGMENT]);
707 }
708
709 static void
710 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
711 struct radv_pipeline *pipeline,
712 struct radv_shader_variant *shader)
713 {
714 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
715
716 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
717 pipeline->graphics.vs.spi_vs_out_config);
718
719 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
720 pipeline->graphics.vs.spi_shader_pos_format);
721
722 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
723 radeon_emit(cmd_buffer->cs, va >> 8);
724 radeon_emit(cmd_buffer->cs, va >> 40);
725 radeon_emit(cmd_buffer->cs, shader->rsrc1);
726 radeon_emit(cmd_buffer->cs, shader->rsrc2);
727
728 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
729 S_028818_VTX_W0_FMT(1) |
730 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
731 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
732 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
733
734
735 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
736 pipeline->graphics.vs.pa_cl_vs_out_cntl);
737
738 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
739 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
740 pipeline->graphics.vs.vgt_reuse_off);
741 }
742
743 static void
744 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
745 struct radv_pipeline *pipeline,
746 struct radv_shader_variant *shader)
747 {
748 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
749
750 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
751 radeon_emit(cmd_buffer->cs, va >> 8);
752 radeon_emit(cmd_buffer->cs, va >> 40);
753 radeon_emit(cmd_buffer->cs, shader->rsrc1);
754 radeon_emit(cmd_buffer->cs, shader->rsrc2);
755 }
756
757 static void
758 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
759 struct radv_shader_variant *shader)
760 {
761 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
762 uint32_t rsrc2 = shader->rsrc2;
763
764 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
765 radeon_emit(cmd_buffer->cs, va >> 8);
766 radeon_emit(cmd_buffer->cs, va >> 40);
767
768 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
769 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
770 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
771 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
772
773 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
774 radeon_emit(cmd_buffer->cs, shader->rsrc1);
775 radeon_emit(cmd_buffer->cs, rsrc2);
776 }
777
778 static void
779 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
780 struct radv_shader_variant *shader)
781 {
782 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
783
784 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
785 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
786 radeon_emit(cmd_buffer->cs, va >> 8);
787 radeon_emit(cmd_buffer->cs, va >> 40);
788
789 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
790 radeon_emit(cmd_buffer->cs, shader->rsrc1);
791 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
792 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
793 } else {
794 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
795 radeon_emit(cmd_buffer->cs, va >> 8);
796 radeon_emit(cmd_buffer->cs, va >> 40);
797 radeon_emit(cmd_buffer->cs, shader->rsrc1);
798 radeon_emit(cmd_buffer->cs, shader->rsrc2);
799 }
800 }
801
802 static void
803 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
804 struct radv_pipeline *pipeline)
805 {
806 struct radv_shader_variant *vs;
807
808 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
809
810 /* Skip shaders merged into HS/GS */
811 vs = pipeline->shaders[MESA_SHADER_VERTEX];
812 if (!vs)
813 return;
814
815 if (vs->info.vs.as_ls)
816 radv_emit_hw_ls(cmd_buffer, vs);
817 else if (vs->info.vs.as_es)
818 radv_emit_hw_es(cmd_buffer, pipeline, vs);
819 else
820 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
821 }
822
823
824 static void
825 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
826 struct radv_pipeline *pipeline)
827 {
828 if (!radv_pipeline_has_tess(pipeline))
829 return;
830
831 struct radv_shader_variant *tes, *tcs;
832
833 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
834 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
835
836 if (tes) {
837 if (tes->info.tes.as_es)
838 radv_emit_hw_es(cmd_buffer, pipeline, tes);
839 else
840 radv_emit_hw_vs(cmd_buffer, pipeline, tes);
841 }
842
843 radv_emit_hw_hs(cmd_buffer, tcs);
844
845 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
846 pipeline->graphics.tess.tf_param);
847
848 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
849 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
850 pipeline->graphics.tess.ls_hs_config);
851 else
852 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
853 pipeline->graphics.tess.ls_hs_config);
854
855 struct ac_userdata_info *loc;
856
857 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
858 if (loc->sgpr_idx != -1) {
859 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
860 assert(loc->num_sgprs == 4);
861 assert(!loc->indirect);
862 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
863 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
864 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
865 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
866 pipeline->graphics.tess.num_tcs_input_cp << 26);
867 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
868 }
869
870 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
871 if (loc->sgpr_idx != -1) {
872 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
873 assert(loc->num_sgprs == 1);
874 assert(!loc->indirect);
875
876 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
877 pipeline->graphics.tess.offchip_layout);
878 }
879
880 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
881 if (loc->sgpr_idx != -1) {
882 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
883 assert(loc->num_sgprs == 1);
884 assert(!loc->indirect);
885
886 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
887 pipeline->graphics.tess.tcs_in_layout);
888 }
889 }
890
891 static void
892 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
893 struct radv_pipeline *pipeline)
894 {
895 struct radv_shader_variant *gs;
896 uint64_t va;
897
898 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
899
900 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
901 if (!gs)
902 return;
903
904 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
905
906 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
907 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
908 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
909 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
910
911 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
912
913 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
914
915 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
916 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
917 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
918 radeon_emit(cmd_buffer->cs, 0);
919 radeon_emit(cmd_buffer->cs, 0);
920 radeon_emit(cmd_buffer->cs, 0);
921
922 uint32_t gs_num_invocations = gs->info.gs.invocations;
923 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
924 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
925 S_028B90_ENABLE(gs_num_invocations > 0));
926
927 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
928 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
929
930 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
931
932 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
933 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
934 radeon_emit(cmd_buffer->cs, va >> 8);
935 radeon_emit(cmd_buffer->cs, va >> 40);
936
937 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
938 radeon_emit(cmd_buffer->cs, gs->rsrc1);
939 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
940 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
941
942 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
943 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
944 } else {
945 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
946 radeon_emit(cmd_buffer->cs, va >> 8);
947 radeon_emit(cmd_buffer->cs, va >> 40);
948 radeon_emit(cmd_buffer->cs, gs->rsrc1);
949 radeon_emit(cmd_buffer->cs, gs->rsrc2);
950 }
951
952 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
953
954 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
955 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
956 if (loc->sgpr_idx != -1) {
957 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
958 uint32_t num_entries = 64;
959 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
960
961 if (is_vi)
962 num_entries *= stride;
963
964 stride = S_008F04_STRIDE(stride);
965 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
966 radeon_emit(cmd_buffer->cs, stride);
967 radeon_emit(cmd_buffer->cs, num_entries);
968 }
969 }
970
971 static void
972 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
973 struct radv_pipeline *pipeline)
974 {
975 struct radv_shader_variant *ps;
976 uint64_t va;
977 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
978 struct radv_blend_state *blend = &pipeline->graphics.blend;
979 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
980
981 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
982 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
983
984 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
985 radeon_emit(cmd_buffer->cs, va >> 8);
986 radeon_emit(cmd_buffer->cs, va >> 40);
987 radeon_emit(cmd_buffer->cs, ps->rsrc1);
988 radeon_emit(cmd_buffer->cs, ps->rsrc2);
989
990 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
991 pipeline->graphics.db_shader_control);
992
993 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
994 ps->config.spi_ps_input_ena);
995
996 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
997 ps->config.spi_ps_input_addr);
998
999 if (ps->info.info.ps.force_persample)
1000 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1001
1002 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
1003 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
1004
1005 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1006
1007 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
1008 pipeline->graphics.shader_z_format);
1009
1010 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1011
1012 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1013 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1014
1015 if (cmd_buffer->device->dfsm_allowed) {
1016 /* optimise this? */
1017 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1018 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1019 }
1020
1021 if (pipeline->graphics.ps_input_cntl_num) {
1022 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1023 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1024 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1025 }
1026 }
1027 }
1028
1029 static void
1030 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1031 struct radv_pipeline *pipeline)
1032 {
1033 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1034
1035 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1036 return;
1037
1038 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1039 pipeline->graphics.vtx_reuse_depth);
1040 }
1041
1042 static void
1043 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1044 {
1045 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1046
1047 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1048 return;
1049
1050 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1051 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1052 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1053 radv_update_multisample_state(cmd_buffer, pipeline);
1054 radv_emit_vertex_shader(cmd_buffer, pipeline);
1055 radv_emit_tess_shaders(cmd_buffer, pipeline);
1056 radv_emit_geometry_shader(cmd_buffer, pipeline);
1057 radv_emit_fragment_shader(cmd_buffer, pipeline);
1058 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1059
1060 cmd_buffer->scratch_size_needed =
1061 MAX2(cmd_buffer->scratch_size_needed,
1062 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1063
1064 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1065 S_0286E8_WAVES(pipeline->max_waves) |
1066 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1067
1068 if (!cmd_buffer->state.emitted_pipeline ||
1069 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1070 pipeline->graphics.can_use_guardband)
1071 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1072
1073 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1074
1075 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1076 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1077 } else {
1078 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1079 }
1080 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1081
1082 if (unlikely(cmd_buffer->device->trace_bo))
1083 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1084
1085 cmd_buffer->state.emitted_pipeline = pipeline;
1086
1087 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1088 }
1089
1090 static void
1091 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1092 {
1093 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1094 cmd_buffer->state.dynamic.viewport.viewports);
1095 }
1096
1097 static void
1098 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1099 {
1100 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1101
1102 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1103 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1104 si_emit_cache_flush(cmd_buffer);
1105 }
1106 si_write_scissors(cmd_buffer->cs, 0, count,
1107 cmd_buffer->state.dynamic.scissor.scissors,
1108 cmd_buffer->state.dynamic.viewport.viewports,
1109 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1110 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1111 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1112 }
1113
1114 static void
1115 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1116 {
1117 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1118
1119 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1120 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1121 }
1122
1123 static void
1124 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1125 {
1126 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1127
1128 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1129 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1130 }
1131
1132 static void
1133 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1134 {
1135 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1136
1137 radeon_set_context_reg_seq(cmd_buffer->cs,
1138 R_028430_DB_STENCILREFMASK, 2);
1139 radeon_emit(cmd_buffer->cs,
1140 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1141 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1142 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1143 S_028430_STENCILOPVAL(1));
1144 radeon_emit(cmd_buffer->cs,
1145 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1146 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1147 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1148 S_028434_STENCILOPVAL_BF(1));
1149 }
1150
1151 static void
1152 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1153 {
1154 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1155
1156 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1157 fui(d->depth_bounds.min));
1158 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1159 fui(d->depth_bounds.max));
1160 }
1161
1162 static void
1163 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1164 {
1165 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1166 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1167 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1168 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1169
1170 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1171 radeon_set_context_reg_seq(cmd_buffer->cs,
1172 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1173 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1174 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1175 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1176 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1177 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1178 }
1179 }
1180
1181 static void
1182 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1183 int index,
1184 struct radv_attachment_info *att)
1185 {
1186 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1187 struct radv_color_buffer_info *cb = &att->cb;
1188
1189 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1190 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1191 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1192 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1193 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1194 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1195 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1196 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1197 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1198 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1199 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1200 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1201 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1202
1203 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1204 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1205 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1206
1207 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1208 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1209 } else {
1210 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1211 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1212 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1213 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1214 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1215 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1216 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1217 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1218 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1219 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1220 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1221 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1222
1223 if (is_vi) { /* DCC BASE */
1224 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1225 }
1226 }
1227 }
1228
1229 static void
1230 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1231 struct radv_ds_buffer_info *ds,
1232 struct radv_image *image,
1233 VkImageLayout layout)
1234 {
1235 uint32_t db_z_info = ds->db_z_info;
1236 uint32_t db_stencil_info = ds->db_stencil_info;
1237
1238 if (!radv_layout_has_htile(image, layout,
1239 radv_image_queue_family_mask(image,
1240 cmd_buffer->queue_family_index,
1241 cmd_buffer->queue_family_index))) {
1242 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1243 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1244 }
1245
1246 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1247 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1248
1249
1250 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1251 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1252 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1253 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1254 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1255
1256 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1257 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1258 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1259 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1260 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1261 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1262 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1263 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1264 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1265 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1266 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1267
1268 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1269 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1270 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1271 } else {
1272 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1273
1274 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1275 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1276 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1277 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1278 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1279 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1280 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1281 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1282 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1283 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1284
1285 }
1286
1287 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1288 ds->pa_su_poly_offset_db_fmt_cntl);
1289 }
1290
1291 void
1292 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1293 struct radv_image *image,
1294 VkClearDepthStencilValue ds_clear_value,
1295 VkImageAspectFlags aspects)
1296 {
1297 uint64_t va = radv_buffer_get_va(image->bo);
1298 va += image->offset + image->clear_value_offset;
1299 unsigned reg_offset = 0, reg_count = 0;
1300
1301 if (!image->surface.htile_size)
1302 return;
1303
1304 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1305 ++reg_count;
1306 } else {
1307 ++reg_offset;
1308 va += 4;
1309 }
1310 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1311 ++reg_count;
1312
1313 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1314 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1315 S_370_WR_CONFIRM(1) |
1316 S_370_ENGINE_SEL(V_370_PFP));
1317 radeon_emit(cmd_buffer->cs, va);
1318 radeon_emit(cmd_buffer->cs, va >> 32);
1319 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1320 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1321 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1322 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1323
1324 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1325 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1326 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1327 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1328 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1329 }
1330
1331 static void
1332 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1333 struct radv_image *image)
1334 {
1335 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1336 uint64_t va = radv_buffer_get_va(image->bo);
1337 va += image->offset + image->clear_value_offset;
1338 unsigned reg_offset = 0, reg_count = 0;
1339
1340 if (!image->surface.htile_size)
1341 return;
1342
1343 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1344 ++reg_count;
1345 } else {
1346 ++reg_offset;
1347 va += 4;
1348 }
1349 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1350 ++reg_count;
1351
1352 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1353 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1354 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1355 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1356 radeon_emit(cmd_buffer->cs, va);
1357 radeon_emit(cmd_buffer->cs, va >> 32);
1358 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1359 radeon_emit(cmd_buffer->cs, 0);
1360
1361 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1362 radeon_emit(cmd_buffer->cs, 0);
1363 }
1364
1365 /*
1366 *with DCC some colors don't require CMASK elimiation before being
1367 * used as a texture. This sets a predicate value to determine if the
1368 * cmask eliminate is required.
1369 */
1370 void
1371 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1372 struct radv_image *image,
1373 bool value)
1374 {
1375 uint64_t pred_val = value;
1376 uint64_t va = radv_buffer_get_va(image->bo);
1377 va += image->offset + image->dcc_pred_offset;
1378
1379 if (!image->surface.dcc_size)
1380 return;
1381
1382 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1383 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1384 S_370_WR_CONFIRM(1) |
1385 S_370_ENGINE_SEL(V_370_PFP));
1386 radeon_emit(cmd_buffer->cs, va);
1387 radeon_emit(cmd_buffer->cs, va >> 32);
1388 radeon_emit(cmd_buffer->cs, pred_val);
1389 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1390 }
1391
1392 void
1393 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1394 struct radv_image *image,
1395 int idx,
1396 uint32_t color_values[2])
1397 {
1398 uint64_t va = radv_buffer_get_va(image->bo);
1399 va += image->offset + image->clear_value_offset;
1400
1401 if (!image->cmask.size && !image->surface.dcc_size)
1402 return;
1403
1404 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1405 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1406 S_370_WR_CONFIRM(1) |
1407 S_370_ENGINE_SEL(V_370_PFP));
1408 radeon_emit(cmd_buffer->cs, va);
1409 radeon_emit(cmd_buffer->cs, va >> 32);
1410 radeon_emit(cmd_buffer->cs, color_values[0]);
1411 radeon_emit(cmd_buffer->cs, color_values[1]);
1412
1413 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1414 radeon_emit(cmd_buffer->cs, color_values[0]);
1415 radeon_emit(cmd_buffer->cs, color_values[1]);
1416 }
1417
1418 static void
1419 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1420 struct radv_image *image,
1421 int idx)
1422 {
1423 uint64_t va = radv_buffer_get_va(image->bo);
1424 va += image->offset + image->clear_value_offset;
1425
1426 if (!image->cmask.size && !image->surface.dcc_size)
1427 return;
1428
1429 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1430
1431 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1432 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1433 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1434 COPY_DATA_COUNT_SEL);
1435 radeon_emit(cmd_buffer->cs, va);
1436 radeon_emit(cmd_buffer->cs, va >> 32);
1437 radeon_emit(cmd_buffer->cs, reg >> 2);
1438 radeon_emit(cmd_buffer->cs, 0);
1439
1440 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1441 radeon_emit(cmd_buffer->cs, 0);
1442 }
1443
1444 static void
1445 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1446 {
1447 int i;
1448 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1449 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1450
1451 /* this may happen for inherited secondary recording */
1452 if (!framebuffer)
1453 return;
1454
1455 for (i = 0; i < 8; ++i) {
1456 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1457 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1458 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1459 continue;
1460 }
1461
1462 int idx = subpass->color_attachments[i].attachment;
1463 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1464
1465 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1466
1467 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1468 radv_emit_fb_color_state(cmd_buffer, i, att);
1469
1470 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1471 }
1472
1473 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1474 int idx = subpass->depth_stencil_attachment.attachment;
1475 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1476 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1477 struct radv_image *image = att->attachment->image;
1478 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1479 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1480 cmd_buffer->queue_family_index,
1481 cmd_buffer->queue_family_index);
1482 /* We currently don't support writing decompressed HTILE */
1483 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1484 radv_layout_is_htile_compressed(image, layout, queue_mask));
1485
1486 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1487
1488 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1489 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1490 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1491 }
1492 radv_load_depth_clear_regs(cmd_buffer, image);
1493 } else {
1494 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1495 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1496 else
1497 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1498
1499 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1500 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1501 }
1502 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1503 S_028208_BR_X(framebuffer->width) |
1504 S_028208_BR_Y(framebuffer->height));
1505
1506 if (cmd_buffer->device->dfsm_allowed) {
1507 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1508 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1509 }
1510
1511 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1512 }
1513
1514 static void
1515 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1516 {
1517 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1518
1519 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1520 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1521 2, cmd_buffer->state.index_type);
1522 } else {
1523 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1524 radeon_emit(cs, cmd_buffer->state.index_type);
1525 }
1526
1527 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1528 radeon_emit(cs, cmd_buffer->state.index_va);
1529 radeon_emit(cs, cmd_buffer->state.index_va >> 32);
1530
1531 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1532 radeon_emit(cs, cmd_buffer->state.max_index_count);
1533
1534 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1535 }
1536
1537 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1538 {
1539 uint32_t db_count_control;
1540
1541 if(!cmd_buffer->state.active_occlusion_queries) {
1542 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1543 db_count_control = 0;
1544 } else {
1545 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1546 }
1547 } else {
1548 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1549 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1550 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1551 S_028004_ZPASS_ENABLE(1) |
1552 S_028004_SLICE_EVEN_ENABLE(1) |
1553 S_028004_SLICE_ODD_ENABLE(1);
1554 } else {
1555 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1556 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1557 }
1558 }
1559
1560 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1561 }
1562
1563 static void
1564 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1565 {
1566 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1567 return;
1568
1569 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1570 radv_emit_viewport(cmd_buffer);
1571
1572 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1573 radv_emit_scissor(cmd_buffer);
1574
1575 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1576 radv_emit_line_width(cmd_buffer);
1577
1578 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1579 radv_emit_blend_constants(cmd_buffer);
1580
1581 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1582 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1583 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1584 radv_emit_stencil(cmd_buffer);
1585
1586 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1587 radv_emit_depth_bounds(cmd_buffer);
1588
1589 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1590 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1591 radv_emit_depth_biais(cmd_buffer);
1592
1593 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1594 }
1595
1596 static void
1597 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1598 struct radv_pipeline *pipeline,
1599 int idx,
1600 uint64_t va,
1601 gl_shader_stage stage)
1602 {
1603 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1604 uint32_t base_reg = pipeline->user_data_0[stage];
1605
1606 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1607 return;
1608
1609 assert(!desc_set_loc->indirect);
1610 assert(desc_set_loc->num_sgprs == 2);
1611 radeon_set_sh_reg_seq(cmd_buffer->cs,
1612 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1613 radeon_emit(cmd_buffer->cs, va);
1614 radeon_emit(cmd_buffer->cs, va >> 32);
1615 }
1616
1617 static void
1618 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1619 VkShaderStageFlags stages,
1620 struct radv_descriptor_set *set,
1621 unsigned idx)
1622 {
1623 if (cmd_buffer->state.pipeline) {
1624 radv_foreach_stage(stage, stages) {
1625 if (cmd_buffer->state.pipeline->shaders[stage])
1626 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1627 idx, set->va,
1628 stage);
1629 }
1630 }
1631
1632 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1633 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1634 idx, set->va,
1635 MESA_SHADER_COMPUTE);
1636 }
1637
1638 static void
1639 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1640 {
1641 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1642 unsigned bo_offset;
1643
1644 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1645 set->mapped_ptr,
1646 &bo_offset))
1647 return;
1648
1649 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1650 set->va += bo_offset;
1651 }
1652
1653 static void
1654 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1655 {
1656 uint32_t size = MAX_SETS * 2 * 4;
1657 uint32_t offset;
1658 void *ptr;
1659
1660 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1661 256, &offset, &ptr))
1662 return;
1663
1664 for (unsigned i = 0; i < MAX_SETS; i++) {
1665 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1666 uint64_t set_va = 0;
1667 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1668 if (cmd_buffer->state.valid_descriptors & (1u << i))
1669 set_va = set->va;
1670 uptr[0] = set_va & 0xffffffff;
1671 uptr[1] = set_va >> 32;
1672 }
1673
1674 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1675 va += offset;
1676
1677 if (cmd_buffer->state.pipeline) {
1678 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1679 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1680 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1681
1682 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1683 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1684 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1685
1686 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1687 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1688 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1689
1690 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1691 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1692 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1693
1694 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1695 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1696 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1697 }
1698
1699 if (cmd_buffer->state.compute_pipeline)
1700 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1701 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1702 }
1703
1704 static void
1705 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1706 VkShaderStageFlags stages)
1707 {
1708 unsigned i;
1709
1710 if (!cmd_buffer->state.descriptors_dirty)
1711 return;
1712
1713 if (cmd_buffer->state.push_descriptors_dirty)
1714 radv_flush_push_descriptors(cmd_buffer);
1715
1716 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1717 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1718 radv_flush_indirect_descriptor_sets(cmd_buffer);
1719 }
1720
1721 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1722 cmd_buffer->cs,
1723 MAX_SETS * MESA_SHADER_STAGES * 4);
1724
1725 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1726 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1727 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1728 continue;
1729
1730 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1731 }
1732 cmd_buffer->state.descriptors_dirty = 0;
1733 cmd_buffer->state.push_descriptors_dirty = false;
1734
1735 if (unlikely(cmd_buffer->device->trace_bo))
1736 radv_save_descriptors(cmd_buffer);
1737
1738 assert(cmd_buffer->cs->cdw <= cdw_max);
1739 }
1740
1741 static void
1742 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1743 struct radv_pipeline *pipeline,
1744 VkShaderStageFlags stages)
1745 {
1746 struct radv_pipeline_layout *layout = pipeline->layout;
1747 unsigned offset;
1748 void *ptr;
1749 uint64_t va;
1750
1751 stages &= cmd_buffer->push_constant_stages;
1752 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1753 return;
1754
1755 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1756 16 * layout->dynamic_offset_count,
1757 256, &offset, &ptr))
1758 return;
1759
1760 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1761 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1762 16 * layout->dynamic_offset_count);
1763
1764 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1765 va += offset;
1766
1767 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1768 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1769
1770 radv_foreach_stage(stage, stages) {
1771 if (pipeline->shaders[stage]) {
1772 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1773 AC_UD_PUSH_CONSTANTS, va);
1774 }
1775 }
1776
1777 cmd_buffer->push_constant_stages &= ~stages;
1778 assert(cmd_buffer->cs->cdw <= cdw_max);
1779 }
1780
1781 static bool
1782 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1783 {
1784 if ((pipeline_is_dirty ||
1785 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1786 cmd_buffer->state.pipeline->vertex_elements.count &&
1787 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1788 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1789 unsigned vb_offset;
1790 void *vb_ptr;
1791 uint32_t i = 0;
1792 uint32_t count = velems->count;
1793 uint64_t va;
1794
1795 /* allocate some descriptor state for vertex buffers */
1796 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1797 &vb_offset, &vb_ptr))
1798 return false;
1799
1800 for (i = 0; i < count; i++) {
1801 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1802 uint32_t offset;
1803 int vb = velems->binding[i];
1804 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1805 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1806
1807 va = radv_buffer_get_va(buffer->bo);
1808
1809 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1810 va += offset + buffer->offset;
1811 desc[0] = va;
1812 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1813 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1814 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1815 else
1816 desc[2] = buffer->size - offset;
1817 desc[3] = velems->rsrc_word3[i];
1818 }
1819
1820 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1821 va += vb_offset;
1822
1823 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1824 AC_UD_VS_VERTEX_BUFFERS, va);
1825
1826 cmd_buffer->state.vb_va = va;
1827 cmd_buffer->state.vb_size = count * 16;
1828 cmd_buffer->state.vb_prefetch_dirty = true;
1829 }
1830 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1831
1832 return true;
1833 }
1834
1835 static bool
1836 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1837 {
1838 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1839 return false;
1840
1841 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1842 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1843 VK_SHADER_STAGE_ALL_GRAPHICS);
1844
1845 return true;
1846 }
1847
1848 static void
1849 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1850 bool instanced_draw, bool indirect_draw,
1851 uint32_t draw_vertex_count)
1852 {
1853 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1854 struct radv_cmd_state *state = &cmd_buffer->state;
1855 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1856 uint32_t ia_multi_vgt_param;
1857 int32_t primitive_reset_en;
1858
1859 /* Draw state. */
1860 ia_multi_vgt_param =
1861 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1862 indirect_draw, draw_vertex_count);
1863
1864 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1865 if (info->chip_class >= GFX9) {
1866 radeon_set_uconfig_reg_idx(cs,
1867 R_030960_IA_MULTI_VGT_PARAM,
1868 4, ia_multi_vgt_param);
1869 } else if (info->chip_class >= CIK) {
1870 radeon_set_context_reg_idx(cs,
1871 R_028AA8_IA_MULTI_VGT_PARAM,
1872 1, ia_multi_vgt_param);
1873 } else {
1874 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1875 ia_multi_vgt_param);
1876 }
1877 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1878 }
1879
1880 /* Primitive restart. */
1881 primitive_reset_en =
1882 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1883
1884 if (primitive_reset_en != state->last_primitive_reset_en) {
1885 state->last_primitive_reset_en = primitive_reset_en;
1886 if (info->chip_class >= GFX9) {
1887 radeon_set_uconfig_reg(cs,
1888 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1889 primitive_reset_en);
1890 } else {
1891 radeon_set_context_reg(cs,
1892 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1893 primitive_reset_en);
1894 }
1895 }
1896
1897 if (primitive_reset_en) {
1898 uint32_t primitive_reset_index =
1899 state->index_type ? 0xffffffffu : 0xffffu;
1900
1901 if (primitive_reset_index != state->last_primitive_reset_index) {
1902 radeon_set_context_reg(cs,
1903 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1904 primitive_reset_index);
1905 state->last_primitive_reset_index = primitive_reset_index;
1906 }
1907 }
1908 }
1909
1910 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1911 VkPipelineStageFlags src_stage_mask)
1912 {
1913 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1914 VK_PIPELINE_STAGE_TRANSFER_BIT |
1915 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1916 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1917 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1918 }
1919
1920 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1921 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1922 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1923 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1924 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1925 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1926 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1927 VK_PIPELINE_STAGE_TRANSFER_BIT |
1928 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1929 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1930 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1931 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1932 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1933 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1934 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1935 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1936 }
1937 }
1938
1939 static enum radv_cmd_flush_bits
1940 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1941 VkAccessFlags src_flags)
1942 {
1943 enum radv_cmd_flush_bits flush_bits = 0;
1944 uint32_t b;
1945 for_each_bit(b, src_flags) {
1946 switch ((VkAccessFlagBits)(1 << b)) {
1947 case VK_ACCESS_SHADER_WRITE_BIT:
1948 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1949 break;
1950 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1951 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1952 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1953 break;
1954 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1955 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1956 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1957 break;
1958 case VK_ACCESS_TRANSFER_WRITE_BIT:
1959 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1960 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1961 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1962 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1963 RADV_CMD_FLAG_INV_GLOBAL_L2;
1964 break;
1965 default:
1966 break;
1967 }
1968 }
1969 return flush_bits;
1970 }
1971
1972 static enum radv_cmd_flush_bits
1973 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1974 VkAccessFlags dst_flags,
1975 struct radv_image *image)
1976 {
1977 enum radv_cmd_flush_bits flush_bits = 0;
1978 uint32_t b;
1979 for_each_bit(b, dst_flags) {
1980 switch ((VkAccessFlagBits)(1 << b)) {
1981 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1982 case VK_ACCESS_INDEX_READ_BIT:
1983 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1984 break;
1985 case VK_ACCESS_UNIFORM_READ_BIT:
1986 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1987 break;
1988 case VK_ACCESS_SHADER_READ_BIT:
1989 case VK_ACCESS_TRANSFER_READ_BIT:
1990 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1991 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1992 RADV_CMD_FLAG_INV_GLOBAL_L2;
1993 break;
1994 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1995 /* TODO: change to image && when the image gets passed
1996 * through from the subpass. */
1997 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1998 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1999 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2000 break;
2001 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2002 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2003 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2004 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2005 break;
2006 default:
2007 break;
2008 }
2009 }
2010 return flush_bits;
2011 }
2012
2013 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2014 {
2015 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2016 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2017 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2018 NULL);
2019 }
2020
2021 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2022 VkAttachmentReference att)
2023 {
2024 unsigned idx = att.attachment;
2025 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2026 VkImageSubresourceRange range;
2027 range.aspectMask = 0;
2028 range.baseMipLevel = view->base_mip;
2029 range.levelCount = 1;
2030 range.baseArrayLayer = view->base_layer;
2031 range.layerCount = cmd_buffer->state.framebuffer->layers;
2032
2033 radv_handle_image_transition(cmd_buffer,
2034 view->image,
2035 cmd_buffer->state.attachments[idx].current_layout,
2036 att.layout, 0, 0, &range,
2037 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2038
2039 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2040
2041
2042 }
2043
2044 void
2045 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2046 const struct radv_subpass *subpass, bool transitions)
2047 {
2048 if (transitions) {
2049 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2050
2051 for (unsigned i = 0; i < subpass->color_count; ++i) {
2052 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2053 radv_handle_subpass_image_transition(cmd_buffer,
2054 subpass->color_attachments[i]);
2055 }
2056
2057 for (unsigned i = 0; i < subpass->input_count; ++i) {
2058 radv_handle_subpass_image_transition(cmd_buffer,
2059 subpass->input_attachments[i]);
2060 }
2061
2062 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2063 radv_handle_subpass_image_transition(cmd_buffer,
2064 subpass->depth_stencil_attachment);
2065 }
2066 }
2067
2068 cmd_buffer->state.subpass = subpass;
2069
2070 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2071 }
2072
2073 static VkResult
2074 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2075 struct radv_render_pass *pass,
2076 const VkRenderPassBeginInfo *info)
2077 {
2078 struct radv_cmd_state *state = &cmd_buffer->state;
2079
2080 if (pass->attachment_count == 0) {
2081 state->attachments = NULL;
2082 return VK_SUCCESS;
2083 }
2084
2085 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2086 pass->attachment_count *
2087 sizeof(state->attachments[0]),
2088 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2089 if (state->attachments == NULL) {
2090 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2091 return cmd_buffer->record_result;
2092 }
2093
2094 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2095 struct radv_render_pass_attachment *att = &pass->attachments[i];
2096 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2097 VkImageAspectFlags clear_aspects = 0;
2098
2099 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2100 /* color attachment */
2101 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2102 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2103 }
2104 } else {
2105 /* depthstencil attachment */
2106 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2107 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2108 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2109 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2110 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2111 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2112 }
2113 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2114 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2115 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2116 }
2117 }
2118
2119 state->attachments[i].pending_clear_aspects = clear_aspects;
2120 state->attachments[i].cleared_views = 0;
2121 if (clear_aspects && info) {
2122 assert(info->clearValueCount > i);
2123 state->attachments[i].clear_value = info->pClearValues[i];
2124 }
2125
2126 state->attachments[i].current_layout = att->initial_layout;
2127 }
2128
2129 return VK_SUCCESS;
2130 }
2131
2132 VkResult radv_AllocateCommandBuffers(
2133 VkDevice _device,
2134 const VkCommandBufferAllocateInfo *pAllocateInfo,
2135 VkCommandBuffer *pCommandBuffers)
2136 {
2137 RADV_FROM_HANDLE(radv_device, device, _device);
2138 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2139
2140 VkResult result = VK_SUCCESS;
2141 uint32_t i;
2142
2143 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2144
2145 if (!list_empty(&pool->free_cmd_buffers)) {
2146 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2147
2148 list_del(&cmd_buffer->pool_link);
2149 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2150
2151 result = radv_reset_cmd_buffer(cmd_buffer);
2152 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2153 cmd_buffer->level = pAllocateInfo->level;
2154
2155 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2156 } else {
2157 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2158 &pCommandBuffers[i]);
2159 }
2160 if (result != VK_SUCCESS)
2161 break;
2162 }
2163
2164 if (result != VK_SUCCESS) {
2165 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2166 i, pCommandBuffers);
2167
2168 /* From the Vulkan 1.0.66 spec:
2169 *
2170 * "vkAllocateCommandBuffers can be used to create multiple
2171 * command buffers. If the creation of any of those command
2172 * buffers fails, the implementation must destroy all
2173 * successfully created command buffer objects from this
2174 * command, set all entries of the pCommandBuffers array to
2175 * NULL and return the error."
2176 */
2177 memset(pCommandBuffers, 0,
2178 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2179 }
2180
2181 return result;
2182 }
2183
2184 void radv_FreeCommandBuffers(
2185 VkDevice device,
2186 VkCommandPool commandPool,
2187 uint32_t commandBufferCount,
2188 const VkCommandBuffer *pCommandBuffers)
2189 {
2190 for (uint32_t i = 0; i < commandBufferCount; i++) {
2191 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2192
2193 if (cmd_buffer) {
2194 if (cmd_buffer->pool) {
2195 list_del(&cmd_buffer->pool_link);
2196 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2197 } else
2198 radv_cmd_buffer_destroy(cmd_buffer);
2199
2200 }
2201 }
2202 }
2203
2204 VkResult radv_ResetCommandBuffer(
2205 VkCommandBuffer commandBuffer,
2206 VkCommandBufferResetFlags flags)
2207 {
2208 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2209 return radv_reset_cmd_buffer(cmd_buffer);
2210 }
2211
2212 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2213 {
2214 struct radv_device *device = cmd_buffer->device;
2215 if (device->gfx_init) {
2216 uint64_t va = radv_buffer_get_va(device->gfx_init);
2217 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2218 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2219 radeon_emit(cmd_buffer->cs, va);
2220 radeon_emit(cmd_buffer->cs, va >> 32);
2221 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2222 } else
2223 si_init_config(cmd_buffer);
2224 }
2225
2226 VkResult radv_BeginCommandBuffer(
2227 VkCommandBuffer commandBuffer,
2228 const VkCommandBufferBeginInfo *pBeginInfo)
2229 {
2230 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2231 VkResult result;
2232
2233 result = radv_reset_cmd_buffer(cmd_buffer);
2234 if (result != VK_SUCCESS)
2235 return result;
2236
2237 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2238 cmd_buffer->state.last_primitive_reset_en = -1;
2239 cmd_buffer->usage_flags = pBeginInfo->flags;
2240
2241 /* setup initial configuration into command buffer */
2242 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2243 switch (cmd_buffer->queue_family_index) {
2244 case RADV_QUEUE_GENERAL:
2245 emit_gfx_buffer_state(cmd_buffer);
2246 break;
2247 case RADV_QUEUE_COMPUTE:
2248 si_init_compute(cmd_buffer);
2249 break;
2250 case RADV_QUEUE_TRANSFER:
2251 default:
2252 break;
2253 }
2254 }
2255
2256 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2257 assert(pBeginInfo->pInheritanceInfo);
2258 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2259 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2260
2261 struct radv_subpass *subpass =
2262 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2263
2264 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2265 if (result != VK_SUCCESS)
2266 return result;
2267
2268 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2269 }
2270
2271 if (unlikely(cmd_buffer->device->trace_bo))
2272 radv_cmd_buffer_trace_emit(cmd_buffer);
2273
2274 return result;
2275 }
2276
2277 void radv_CmdBindVertexBuffers(
2278 VkCommandBuffer commandBuffer,
2279 uint32_t firstBinding,
2280 uint32_t bindingCount,
2281 const VkBuffer* pBuffers,
2282 const VkDeviceSize* pOffsets)
2283 {
2284 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2285 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2286 bool changed = false;
2287
2288 /* We have to defer setting up vertex buffer since we need the buffer
2289 * stride from the pipeline. */
2290
2291 assert(firstBinding + bindingCount <= MAX_VBS);
2292 for (uint32_t i = 0; i < bindingCount; i++) {
2293 uint32_t idx = firstBinding + i;
2294
2295 if (!changed &&
2296 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2297 vb[idx].offset != pOffsets[i])) {
2298 changed = true;
2299 }
2300
2301 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2302 vb[idx].offset = pOffsets[i];
2303
2304 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2305 vb[idx].buffer->bo, 8);
2306 }
2307
2308 if (!changed) {
2309 /* No state changes. */
2310 return;
2311 }
2312
2313 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2314 }
2315
2316 void radv_CmdBindIndexBuffer(
2317 VkCommandBuffer commandBuffer,
2318 VkBuffer buffer,
2319 VkDeviceSize offset,
2320 VkIndexType indexType)
2321 {
2322 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2323 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2324
2325 if (cmd_buffer->state.index_buffer == index_buffer &&
2326 cmd_buffer->state.index_offset == offset &&
2327 cmd_buffer->state.index_type == indexType) {
2328 /* No state changes. */
2329 return;
2330 }
2331
2332 cmd_buffer->state.index_buffer = index_buffer;
2333 cmd_buffer->state.index_offset = offset;
2334 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2335 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2336 cmd_buffer->state.index_va += index_buffer->offset + offset;
2337
2338 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2339 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2340 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2341 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2342 }
2343
2344
2345 static void
2346 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2347 struct radv_descriptor_set *set, unsigned idx)
2348 {
2349 struct radeon_winsys *ws = cmd_buffer->device->ws;
2350
2351 radv_set_descriptor_set(cmd_buffer, set, idx);
2352 if (!set)
2353 return;
2354
2355 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2356
2357 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2358 if (set->descriptors[j])
2359 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2360
2361 if(set->bo)
2362 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2363 }
2364
2365 void radv_CmdBindDescriptorSets(
2366 VkCommandBuffer commandBuffer,
2367 VkPipelineBindPoint pipelineBindPoint,
2368 VkPipelineLayout _layout,
2369 uint32_t firstSet,
2370 uint32_t descriptorSetCount,
2371 const VkDescriptorSet* pDescriptorSets,
2372 uint32_t dynamicOffsetCount,
2373 const uint32_t* pDynamicOffsets)
2374 {
2375 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2376 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2377 unsigned dyn_idx = 0;
2378
2379 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2380 unsigned idx = i + firstSet;
2381 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2382 radv_bind_descriptor_set(cmd_buffer, set, idx);
2383
2384 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2385 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2386 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2387 assert(dyn_idx < dynamicOffsetCount);
2388
2389 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2390 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2391 dst[0] = va;
2392 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2393 dst[2] = range->size;
2394 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2395 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2396 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2397 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2398 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2399 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2400 cmd_buffer->push_constant_stages |=
2401 set->layout->dynamic_shader_stages;
2402 }
2403 }
2404 }
2405
2406 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2407 struct radv_descriptor_set *set,
2408 struct radv_descriptor_set_layout *layout)
2409 {
2410 set->size = layout->size;
2411 set->layout = layout;
2412
2413 if (cmd_buffer->push_descriptors.capacity < set->size) {
2414 size_t new_size = MAX2(set->size, 1024);
2415 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2416 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2417
2418 free(set->mapped_ptr);
2419 set->mapped_ptr = malloc(new_size);
2420
2421 if (!set->mapped_ptr) {
2422 cmd_buffer->push_descriptors.capacity = 0;
2423 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2424 return false;
2425 }
2426
2427 cmd_buffer->push_descriptors.capacity = new_size;
2428 }
2429
2430 return true;
2431 }
2432
2433 void radv_meta_push_descriptor_set(
2434 struct radv_cmd_buffer* cmd_buffer,
2435 VkPipelineBindPoint pipelineBindPoint,
2436 VkPipelineLayout _layout,
2437 uint32_t set,
2438 uint32_t descriptorWriteCount,
2439 const VkWriteDescriptorSet* pDescriptorWrites)
2440 {
2441 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2442 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2443 unsigned bo_offset;
2444
2445 assert(set == 0);
2446 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2447
2448 push_set->size = layout->set[set].layout->size;
2449 push_set->layout = layout->set[set].layout;
2450
2451 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2452 &bo_offset,
2453 (void**) &push_set->mapped_ptr))
2454 return;
2455
2456 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2457 push_set->va += bo_offset;
2458
2459 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2460 radv_descriptor_set_to_handle(push_set),
2461 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2462
2463 radv_set_descriptor_set(cmd_buffer, push_set, set);
2464 }
2465
2466 void radv_CmdPushDescriptorSetKHR(
2467 VkCommandBuffer commandBuffer,
2468 VkPipelineBindPoint pipelineBindPoint,
2469 VkPipelineLayout _layout,
2470 uint32_t set,
2471 uint32_t descriptorWriteCount,
2472 const VkWriteDescriptorSet* pDescriptorWrites)
2473 {
2474 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2475 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2476 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2477
2478 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2479
2480 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2481 return;
2482
2483 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2484 radv_descriptor_set_to_handle(push_set),
2485 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2486
2487 radv_set_descriptor_set(cmd_buffer, push_set, set);
2488 cmd_buffer->state.push_descriptors_dirty = true;
2489 }
2490
2491 void radv_CmdPushDescriptorSetWithTemplateKHR(
2492 VkCommandBuffer commandBuffer,
2493 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2494 VkPipelineLayout _layout,
2495 uint32_t set,
2496 const void* pData)
2497 {
2498 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2499 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2500 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2501
2502 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2503
2504 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2505 return;
2506
2507 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2508 descriptorUpdateTemplate, pData);
2509
2510 radv_set_descriptor_set(cmd_buffer, push_set, set);
2511 cmd_buffer->state.push_descriptors_dirty = true;
2512 }
2513
2514 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2515 VkPipelineLayout layout,
2516 VkShaderStageFlags stageFlags,
2517 uint32_t offset,
2518 uint32_t size,
2519 const void* pValues)
2520 {
2521 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2522 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2523 cmd_buffer->push_constant_stages |= stageFlags;
2524 }
2525
2526 VkResult radv_EndCommandBuffer(
2527 VkCommandBuffer commandBuffer)
2528 {
2529 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2530
2531 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2532 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2533 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2534 si_emit_cache_flush(cmd_buffer);
2535 }
2536
2537 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2538
2539 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2540 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2541
2542 return cmd_buffer->record_result;
2543 }
2544
2545 static void
2546 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2547 {
2548 struct radv_shader_variant *compute_shader;
2549 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2550 uint64_t va;
2551
2552 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2553 return;
2554
2555 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2556
2557 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2558 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2559
2560 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2561 cmd_buffer->cs, 16);
2562
2563 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2564 radeon_emit(cmd_buffer->cs, va >> 8);
2565 radeon_emit(cmd_buffer->cs, va >> 40);
2566
2567 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2568 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2569 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2570
2571
2572 cmd_buffer->compute_scratch_size_needed =
2573 MAX2(cmd_buffer->compute_scratch_size_needed,
2574 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2575
2576 /* change these once we have scratch support */
2577 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2578 S_00B860_WAVES(pipeline->max_waves) |
2579 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2580
2581 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2582 radeon_emit(cmd_buffer->cs,
2583 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2584 radeon_emit(cmd_buffer->cs,
2585 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2586 radeon_emit(cmd_buffer->cs,
2587 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2588
2589 assert(cmd_buffer->cs->cdw <= cdw_max);
2590
2591 if (unlikely(cmd_buffer->device->trace_bo))
2592 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2593 }
2594
2595 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2596 {
2597 cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2598 }
2599
2600 void radv_CmdBindPipeline(
2601 VkCommandBuffer commandBuffer,
2602 VkPipelineBindPoint pipelineBindPoint,
2603 VkPipeline _pipeline)
2604 {
2605 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2606 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2607
2608 switch (pipelineBindPoint) {
2609 case VK_PIPELINE_BIND_POINT_COMPUTE:
2610 if (cmd_buffer->state.compute_pipeline == pipeline)
2611 return;
2612 radv_mark_descriptor_sets_dirty(cmd_buffer);
2613
2614 cmd_buffer->state.compute_pipeline = pipeline;
2615 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2616 break;
2617 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2618 if (cmd_buffer->state.pipeline == pipeline)
2619 return;
2620 radv_mark_descriptor_sets_dirty(cmd_buffer);
2621
2622 cmd_buffer->state.pipeline = pipeline;
2623 if (!pipeline)
2624 break;
2625
2626 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2627 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2628
2629 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2630
2631 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2632 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2633 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2634 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2635
2636 if (radv_pipeline_has_tess(pipeline))
2637 cmd_buffer->tess_rings_needed = true;
2638
2639 if (radv_pipeline_has_gs(pipeline)) {
2640 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2641 AC_UD_SCRATCH_RING_OFFSETS);
2642 if (cmd_buffer->ring_offsets_idx == -1)
2643 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2644 else if (loc->sgpr_idx != -1)
2645 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2646 }
2647 break;
2648 default:
2649 assert(!"invalid bind point");
2650 break;
2651 }
2652 }
2653
2654 void radv_CmdSetViewport(
2655 VkCommandBuffer commandBuffer,
2656 uint32_t firstViewport,
2657 uint32_t viewportCount,
2658 const VkViewport* pViewports)
2659 {
2660 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2661 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2662
2663 assert(firstViewport < MAX_VIEWPORTS);
2664 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2665
2666 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2667 pViewports, viewportCount * sizeof(*pViewports));
2668
2669 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2670 }
2671
2672 void radv_CmdSetScissor(
2673 VkCommandBuffer commandBuffer,
2674 uint32_t firstScissor,
2675 uint32_t scissorCount,
2676 const VkRect2D* pScissors)
2677 {
2678 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2679 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2680
2681 assert(firstScissor < MAX_SCISSORS);
2682 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2683
2684 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2685 pScissors, scissorCount * sizeof(*pScissors));
2686 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2687 }
2688
2689 void radv_CmdSetLineWidth(
2690 VkCommandBuffer commandBuffer,
2691 float lineWidth)
2692 {
2693 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2694 cmd_buffer->state.dynamic.line_width = lineWidth;
2695 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2696 }
2697
2698 void radv_CmdSetDepthBias(
2699 VkCommandBuffer commandBuffer,
2700 float depthBiasConstantFactor,
2701 float depthBiasClamp,
2702 float depthBiasSlopeFactor)
2703 {
2704 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2705
2706 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2707 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2708 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2709
2710 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2711 }
2712
2713 void radv_CmdSetBlendConstants(
2714 VkCommandBuffer commandBuffer,
2715 const float blendConstants[4])
2716 {
2717 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2718
2719 memcpy(cmd_buffer->state.dynamic.blend_constants,
2720 blendConstants, sizeof(float) * 4);
2721
2722 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2723 }
2724
2725 void radv_CmdSetDepthBounds(
2726 VkCommandBuffer commandBuffer,
2727 float minDepthBounds,
2728 float maxDepthBounds)
2729 {
2730 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2731
2732 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2733 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2734
2735 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2736 }
2737
2738 void radv_CmdSetStencilCompareMask(
2739 VkCommandBuffer commandBuffer,
2740 VkStencilFaceFlags faceMask,
2741 uint32_t compareMask)
2742 {
2743 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2744
2745 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2746 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2747 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2748 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2749
2750 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2751 }
2752
2753 void radv_CmdSetStencilWriteMask(
2754 VkCommandBuffer commandBuffer,
2755 VkStencilFaceFlags faceMask,
2756 uint32_t writeMask)
2757 {
2758 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2759
2760 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2761 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2762 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2763 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2764
2765 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2766 }
2767
2768 void radv_CmdSetStencilReference(
2769 VkCommandBuffer commandBuffer,
2770 VkStencilFaceFlags faceMask,
2771 uint32_t reference)
2772 {
2773 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2774
2775 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2776 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2777 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2778 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2779
2780 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2781 }
2782
2783 void radv_CmdExecuteCommands(
2784 VkCommandBuffer commandBuffer,
2785 uint32_t commandBufferCount,
2786 const VkCommandBuffer* pCmdBuffers)
2787 {
2788 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2789
2790 assert(commandBufferCount > 0);
2791
2792 /* Emit pending flushes on primary prior to executing secondary */
2793 si_emit_cache_flush(primary);
2794
2795 for (uint32_t i = 0; i < commandBufferCount; i++) {
2796 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2797
2798 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2799 secondary->scratch_size_needed);
2800 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2801 secondary->compute_scratch_size_needed);
2802
2803 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2804 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2805 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2806 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2807 if (secondary->tess_rings_needed)
2808 primary->tess_rings_needed = true;
2809 if (secondary->sample_positions_needed)
2810 primary->sample_positions_needed = true;
2811
2812 if (secondary->ring_offsets_idx != -1) {
2813 if (primary->ring_offsets_idx == -1)
2814 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2815 else
2816 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2817 }
2818 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2819
2820
2821 /* When the secondary command buffer is compute only we don't
2822 * need to re-emit the current graphics pipeline.
2823 */
2824 if (secondary->state.emitted_pipeline) {
2825 primary->state.emitted_pipeline =
2826 secondary->state.emitted_pipeline;
2827 }
2828
2829 /* When the secondary command buffer is graphics only we don't
2830 * need to re-emit the current compute pipeline.
2831 */
2832 if (secondary->state.emitted_compute_pipeline) {
2833 primary->state.emitted_compute_pipeline =
2834 secondary->state.emitted_compute_pipeline;
2835 }
2836
2837 /* Only re-emit the draw packets when needed. */
2838 if (secondary->state.last_primitive_reset_en != -1) {
2839 primary->state.last_primitive_reset_en =
2840 secondary->state.last_primitive_reset_en;
2841 }
2842
2843 if (secondary->state.last_primitive_reset_index) {
2844 primary->state.last_primitive_reset_index =
2845 secondary->state.last_primitive_reset_index;
2846 }
2847
2848 if (secondary->state.last_ia_multi_vgt_param) {
2849 primary->state.last_ia_multi_vgt_param =
2850 secondary->state.last_ia_multi_vgt_param;
2851 }
2852 }
2853
2854 /* After executing commands from secondary buffers we have to dirty
2855 * some states.
2856 */
2857 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2858 RADV_CMD_DIRTY_INDEX_BUFFER |
2859 RADV_CMD_DIRTY_DYNAMIC_ALL;
2860 radv_mark_descriptor_sets_dirty(primary);
2861 }
2862
2863 VkResult radv_CreateCommandPool(
2864 VkDevice _device,
2865 const VkCommandPoolCreateInfo* pCreateInfo,
2866 const VkAllocationCallbacks* pAllocator,
2867 VkCommandPool* pCmdPool)
2868 {
2869 RADV_FROM_HANDLE(radv_device, device, _device);
2870 struct radv_cmd_pool *pool;
2871
2872 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2873 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2874 if (pool == NULL)
2875 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2876
2877 if (pAllocator)
2878 pool->alloc = *pAllocator;
2879 else
2880 pool->alloc = device->alloc;
2881
2882 list_inithead(&pool->cmd_buffers);
2883 list_inithead(&pool->free_cmd_buffers);
2884
2885 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2886
2887 *pCmdPool = radv_cmd_pool_to_handle(pool);
2888
2889 return VK_SUCCESS;
2890
2891 }
2892
2893 void radv_DestroyCommandPool(
2894 VkDevice _device,
2895 VkCommandPool commandPool,
2896 const VkAllocationCallbacks* pAllocator)
2897 {
2898 RADV_FROM_HANDLE(radv_device, device, _device);
2899 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2900
2901 if (!pool)
2902 return;
2903
2904 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2905 &pool->cmd_buffers, pool_link) {
2906 radv_cmd_buffer_destroy(cmd_buffer);
2907 }
2908
2909 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2910 &pool->free_cmd_buffers, pool_link) {
2911 radv_cmd_buffer_destroy(cmd_buffer);
2912 }
2913
2914 vk_free2(&device->alloc, pAllocator, pool);
2915 }
2916
2917 VkResult radv_ResetCommandPool(
2918 VkDevice device,
2919 VkCommandPool commandPool,
2920 VkCommandPoolResetFlags flags)
2921 {
2922 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2923 VkResult result;
2924
2925 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2926 &pool->cmd_buffers, pool_link) {
2927 result = radv_reset_cmd_buffer(cmd_buffer);
2928 if (result != VK_SUCCESS)
2929 return result;
2930 }
2931
2932 return VK_SUCCESS;
2933 }
2934
2935 void radv_TrimCommandPoolKHR(
2936 VkDevice device,
2937 VkCommandPool commandPool,
2938 VkCommandPoolTrimFlagsKHR flags)
2939 {
2940 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2941
2942 if (!pool)
2943 return;
2944
2945 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2946 &pool->free_cmd_buffers, pool_link) {
2947 radv_cmd_buffer_destroy(cmd_buffer);
2948 }
2949 }
2950
2951 void radv_CmdBeginRenderPass(
2952 VkCommandBuffer commandBuffer,
2953 const VkRenderPassBeginInfo* pRenderPassBegin,
2954 VkSubpassContents contents)
2955 {
2956 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2957 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2958 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2959
2960 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2961 cmd_buffer->cs, 2048);
2962 MAYBE_UNUSED VkResult result;
2963
2964 cmd_buffer->state.framebuffer = framebuffer;
2965 cmd_buffer->state.pass = pass;
2966 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2967
2968 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2969 if (result != VK_SUCCESS)
2970 return;
2971
2972 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2973 assert(cmd_buffer->cs->cdw <= cdw_max);
2974
2975 radv_cmd_buffer_clear_subpass(cmd_buffer);
2976 }
2977
2978 void radv_CmdNextSubpass(
2979 VkCommandBuffer commandBuffer,
2980 VkSubpassContents contents)
2981 {
2982 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2983
2984 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2985
2986 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2987 2048);
2988
2989 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2990 radv_cmd_buffer_clear_subpass(cmd_buffer);
2991 }
2992
2993 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2994 {
2995 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2996 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2997 if (!pipeline->shaders[stage])
2998 continue;
2999 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3000 if (loc->sgpr_idx == -1)
3001 continue;
3002 uint32_t base_reg = pipeline->user_data_0[stage];
3003 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3004
3005 }
3006 if (pipeline->gs_copy_shader) {
3007 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3008 if (loc->sgpr_idx != -1) {
3009 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3010 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3011 }
3012 }
3013 }
3014
3015 static void
3016 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3017 uint32_t vertex_count)
3018 {
3019 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3020 radeon_emit(cmd_buffer->cs, vertex_count);
3021 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3022 S_0287F0_USE_OPAQUE(0));
3023 }
3024
3025 static void
3026 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3027 uint64_t index_va,
3028 uint32_t index_count)
3029 {
3030 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3031 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3032 radeon_emit(cmd_buffer->cs, index_va);
3033 radeon_emit(cmd_buffer->cs, index_va >> 32);
3034 radeon_emit(cmd_buffer->cs, index_count);
3035 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3036 }
3037
3038 static void
3039 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3040 bool indexed,
3041 uint32_t draw_count,
3042 uint64_t count_va,
3043 uint32_t stride)
3044 {
3045 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3046 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3047 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3048 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3049 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3050 assert(base_reg);
3051
3052 if (draw_count == 1 && !count_va && !draw_id_enable) {
3053 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3054 PKT3_DRAW_INDIRECT, 3, false));
3055 radeon_emit(cs, 0);
3056 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3057 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3058 radeon_emit(cs, di_src_sel);
3059 } else {
3060 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3061 PKT3_DRAW_INDIRECT_MULTI,
3062 8, false));
3063 radeon_emit(cs, 0);
3064 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3065 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3066 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3067 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3068 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3069 radeon_emit(cs, draw_count); /* count */
3070 radeon_emit(cs, count_va); /* count_addr */
3071 radeon_emit(cs, count_va >> 32);
3072 radeon_emit(cs, stride); /* stride */
3073 radeon_emit(cs, di_src_sel);
3074 }
3075 }
3076
3077 struct radv_draw_info {
3078 /**
3079 * Number of vertices.
3080 */
3081 uint32_t count;
3082
3083 /**
3084 * Index of the first vertex.
3085 */
3086 int32_t vertex_offset;
3087
3088 /**
3089 * First instance id.
3090 */
3091 uint32_t first_instance;
3092
3093 /**
3094 * Number of instances.
3095 */
3096 uint32_t instance_count;
3097
3098 /**
3099 * First index (indexed draws only).
3100 */
3101 uint32_t first_index;
3102
3103 /**
3104 * Whether it's an indexed draw.
3105 */
3106 bool indexed;
3107
3108 /**
3109 * Indirect draw parameters resource.
3110 */
3111 struct radv_buffer *indirect;
3112 uint64_t indirect_offset;
3113 uint32_t stride;
3114
3115 /**
3116 * Draw count parameters resource.
3117 */
3118 struct radv_buffer *count_buffer;
3119 uint64_t count_buffer_offset;
3120 };
3121
3122 static void
3123 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3124 const struct radv_draw_info *info)
3125 {
3126 struct radv_cmd_state *state = &cmd_buffer->state;
3127 struct radeon_winsys *ws = cmd_buffer->device->ws;
3128 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3129
3130 if (info->indirect) {
3131 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3132 uint64_t count_va = 0;
3133
3134 va += info->indirect->offset + info->indirect_offset;
3135
3136 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3137
3138 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3139 radeon_emit(cs, 1);
3140 radeon_emit(cs, va);
3141 radeon_emit(cs, va >> 32);
3142
3143 if (info->count_buffer) {
3144 count_va = radv_buffer_get_va(info->count_buffer->bo);
3145 count_va += info->count_buffer->offset +
3146 info->count_buffer_offset;
3147
3148 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3149 }
3150
3151 if (!state->subpass->view_mask) {
3152 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3153 info->indexed,
3154 info->count,
3155 count_va,
3156 info->stride);
3157 } else {
3158 unsigned i;
3159 for_each_bit(i, state->subpass->view_mask) {
3160 radv_emit_view_index(cmd_buffer, i);
3161
3162 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3163 info->indexed,
3164 info->count,
3165 count_va,
3166 info->stride);
3167 }
3168 }
3169 } else {
3170 assert(state->pipeline->graphics.vtx_base_sgpr);
3171 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3172 state->pipeline->graphics.vtx_emit_num);
3173 radeon_emit(cs, info->vertex_offset);
3174 radeon_emit(cs, info->first_instance);
3175 if (state->pipeline->graphics.vtx_emit_num == 3)
3176 radeon_emit(cs, 0);
3177
3178 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3179 radeon_emit(cs, info->instance_count);
3180
3181 if (info->indexed) {
3182 int index_size = state->index_type ? 4 : 2;
3183 uint64_t index_va;
3184
3185 index_va = state->index_va;
3186 index_va += info->first_index * index_size;
3187
3188 if (!state->subpass->view_mask) {
3189 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3190 index_va,
3191 info->count);
3192 } else {
3193 unsigned i;
3194 for_each_bit(i, state->subpass->view_mask) {
3195 radv_emit_view_index(cmd_buffer, i);
3196
3197 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3198 index_va,
3199 info->count);
3200 }
3201 }
3202 } else {
3203 if (!state->subpass->view_mask) {
3204 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3205 } else {
3206 unsigned i;
3207 for_each_bit(i, state->subpass->view_mask) {
3208 radv_emit_view_index(cmd_buffer, i);
3209
3210 radv_cs_emit_draw_packet(cmd_buffer,
3211 info->count);
3212 }
3213 }
3214 }
3215 }
3216 }
3217
3218 static void
3219 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3220 const struct radv_draw_info *info)
3221 {
3222 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3223 radv_emit_graphics_pipeline(cmd_buffer);
3224
3225 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3226 radv_emit_framebuffer_state(cmd_buffer);
3227
3228 if (info->indexed) {
3229 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3230 radv_emit_index_buffer(cmd_buffer);
3231 } else {
3232 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3233 * so the state must be re-emitted before the next indexed
3234 * draw.
3235 */
3236 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
3237 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3238 }
3239
3240 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3241
3242 radv_emit_draw_registers(cmd_buffer, info->indexed,
3243 info->instance_count > 1, info->indirect,
3244 info->indirect ? 0 : info->count);
3245 }
3246
3247 static void
3248 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3249 const struct radv_draw_info *info)
3250 {
3251 bool pipeline_is_dirty =
3252 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3253 cmd_buffer->state.pipeline &&
3254 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3255
3256 MAYBE_UNUSED unsigned cdw_max =
3257 radeon_check_space(cmd_buffer->device->ws,
3258 cmd_buffer->cs, 4096);
3259
3260 /* Use optimal packet order based on whether we need to sync the
3261 * pipeline.
3262 */
3263 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3264 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3265 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3266 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3267 /* If we have to wait for idle, set all states first, so that
3268 * all SET packets are processed in parallel with previous draw
3269 * calls. Then upload descriptors, set shader pointers, and
3270 * draw, and prefetch at the end. This ensures that the time
3271 * the CUs are idle is very short. (there are only SET_SH
3272 * packets between the wait and the draw)
3273 */
3274 radv_emit_all_graphics_states(cmd_buffer, info);
3275 si_emit_cache_flush(cmd_buffer);
3276 /* <-- CUs are idle here --> */
3277
3278 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3279 return;
3280
3281 radv_emit_draw_packets(cmd_buffer, info);
3282 /* <-- CUs are busy here --> */
3283
3284 /* Start prefetches after the draw has been started. Both will
3285 * run in parallel, but starting the draw first is more
3286 * important.
3287 */
3288 if (pipeline_is_dirty) {
3289 radv_emit_prefetch(cmd_buffer,
3290 cmd_buffer->state.pipeline);
3291 }
3292 } else {
3293 /* If we don't wait for idle, start prefetches first, then set
3294 * states, and draw at the end.
3295 */
3296 si_emit_cache_flush(cmd_buffer);
3297
3298 if (pipeline_is_dirty) {
3299 radv_emit_prefetch(cmd_buffer,
3300 cmd_buffer->state.pipeline);
3301 }
3302
3303 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3304 return;
3305
3306 radv_emit_all_graphics_states(cmd_buffer, info);
3307 radv_emit_draw_packets(cmd_buffer, info);
3308 }
3309
3310 assert(cmd_buffer->cs->cdw <= cdw_max);
3311 radv_cmd_buffer_after_draw(cmd_buffer);
3312 }
3313
3314 void radv_CmdDraw(
3315 VkCommandBuffer commandBuffer,
3316 uint32_t vertexCount,
3317 uint32_t instanceCount,
3318 uint32_t firstVertex,
3319 uint32_t firstInstance)
3320 {
3321 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3322 struct radv_draw_info info = {};
3323
3324 info.count = vertexCount;
3325 info.instance_count = instanceCount;
3326 info.first_instance = firstInstance;
3327 info.vertex_offset = firstVertex;
3328
3329 radv_draw(cmd_buffer, &info);
3330 }
3331
3332 void radv_CmdDrawIndexed(
3333 VkCommandBuffer commandBuffer,
3334 uint32_t indexCount,
3335 uint32_t instanceCount,
3336 uint32_t firstIndex,
3337 int32_t vertexOffset,
3338 uint32_t firstInstance)
3339 {
3340 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3341 struct radv_draw_info info = {};
3342
3343 info.indexed = true;
3344 info.count = indexCount;
3345 info.instance_count = instanceCount;
3346 info.first_index = firstIndex;
3347 info.vertex_offset = vertexOffset;
3348 info.first_instance = firstInstance;
3349
3350 radv_draw(cmd_buffer, &info);
3351 }
3352
3353 void radv_CmdDrawIndirect(
3354 VkCommandBuffer commandBuffer,
3355 VkBuffer _buffer,
3356 VkDeviceSize offset,
3357 uint32_t drawCount,
3358 uint32_t stride)
3359 {
3360 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3361 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3362 struct radv_draw_info info = {};
3363
3364 info.count = drawCount;
3365 info.indirect = buffer;
3366 info.indirect_offset = offset;
3367 info.stride = stride;
3368
3369 radv_draw(cmd_buffer, &info);
3370 }
3371
3372 void radv_CmdDrawIndexedIndirect(
3373 VkCommandBuffer commandBuffer,
3374 VkBuffer _buffer,
3375 VkDeviceSize offset,
3376 uint32_t drawCount,
3377 uint32_t stride)
3378 {
3379 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3380 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3381 struct radv_draw_info info = {};
3382
3383 info.indexed = true;
3384 info.count = drawCount;
3385 info.indirect = buffer;
3386 info.indirect_offset = offset;
3387 info.stride = stride;
3388
3389 radv_draw(cmd_buffer, &info);
3390 }
3391
3392 void radv_CmdDrawIndirectCountAMD(
3393 VkCommandBuffer commandBuffer,
3394 VkBuffer _buffer,
3395 VkDeviceSize offset,
3396 VkBuffer _countBuffer,
3397 VkDeviceSize countBufferOffset,
3398 uint32_t maxDrawCount,
3399 uint32_t stride)
3400 {
3401 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3402 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3403 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3404 struct radv_draw_info info = {};
3405
3406 info.count = maxDrawCount;
3407 info.indirect = buffer;
3408 info.indirect_offset = offset;
3409 info.count_buffer = count_buffer;
3410 info.count_buffer_offset = countBufferOffset;
3411 info.stride = stride;
3412
3413 radv_draw(cmd_buffer, &info);
3414 }
3415
3416 void radv_CmdDrawIndexedIndirectCountAMD(
3417 VkCommandBuffer commandBuffer,
3418 VkBuffer _buffer,
3419 VkDeviceSize offset,
3420 VkBuffer _countBuffer,
3421 VkDeviceSize countBufferOffset,
3422 uint32_t maxDrawCount,
3423 uint32_t stride)
3424 {
3425 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3426 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3427 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3428 struct radv_draw_info info = {};
3429
3430 info.indexed = true;
3431 info.count = maxDrawCount;
3432 info.indirect = buffer;
3433 info.indirect_offset = offset;
3434 info.count_buffer = count_buffer;
3435 info.count_buffer_offset = countBufferOffset;
3436 info.stride = stride;
3437
3438 radv_draw(cmd_buffer, &info);
3439 }
3440
3441 struct radv_dispatch_info {
3442 /**
3443 * Determine the layout of the grid (in block units) to be used.
3444 */
3445 uint32_t blocks[3];
3446
3447 /**
3448 * Whether it's an unaligned compute dispatch.
3449 */
3450 bool unaligned;
3451
3452 /**
3453 * Indirect compute parameters resource.
3454 */
3455 struct radv_buffer *indirect;
3456 uint64_t indirect_offset;
3457 };
3458
3459 static void
3460 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3461 const struct radv_dispatch_info *info)
3462 {
3463 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3464 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3465 struct radeon_winsys *ws = cmd_buffer->device->ws;
3466 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3467 struct ac_userdata_info *loc;
3468 unsigned dispatch_initiator;
3469 uint8_t grid_used;
3470
3471 grid_used = compute_shader->info.info.cs.grid_components_used;
3472
3473 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3474 AC_UD_CS_GRID_SIZE);
3475
3476 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3477
3478 dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3479 S_00B800_FORCE_START_AT_000(1);
3480
3481 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3482 /* If the KMD allows it (there is a KMD hw register for it),
3483 * allow launching waves out-of-order.
3484 */
3485 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3486 }
3487
3488 if (info->indirect) {
3489 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3490
3491 va += info->indirect->offset + info->indirect_offset;
3492
3493 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3494
3495 if (loc->sgpr_idx != -1) {
3496 for (unsigned i = 0; i < grid_used; ++i) {
3497 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3498 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3499 COPY_DATA_DST_SEL(COPY_DATA_REG));
3500 radeon_emit(cs, (va + 4 * i));
3501 radeon_emit(cs, (va + 4 * i) >> 32);
3502 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3503 + loc->sgpr_idx * 4) >> 2) + i);
3504 radeon_emit(cs, 0);
3505 }
3506 }
3507
3508 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3509 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3510 PKT3_SHADER_TYPE_S(1));
3511 radeon_emit(cs, va);
3512 radeon_emit(cs, va >> 32);
3513 radeon_emit(cs, dispatch_initiator);
3514 } else {
3515 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3516 PKT3_SHADER_TYPE_S(1));
3517 radeon_emit(cs, 1);
3518 radeon_emit(cs, va);
3519 radeon_emit(cs, va >> 32);
3520
3521 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3522 PKT3_SHADER_TYPE_S(1));
3523 radeon_emit(cs, 0);
3524 radeon_emit(cs, dispatch_initiator);
3525 }
3526 } else {
3527 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3528
3529 if (info->unaligned) {
3530 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3531 unsigned remainder[3];
3532
3533 /* If aligned, these should be an entire block size,
3534 * not 0.
3535 */
3536 remainder[0] = blocks[0] + cs_block_size[0] -
3537 align_u32_npot(blocks[0], cs_block_size[0]);
3538 remainder[1] = blocks[1] + cs_block_size[1] -
3539 align_u32_npot(blocks[1], cs_block_size[1]);
3540 remainder[2] = blocks[2] + cs_block_size[2] -
3541 align_u32_npot(blocks[2], cs_block_size[2]);
3542
3543 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3544 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3545 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3546
3547 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3548 radeon_emit(cs,
3549 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3550 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3551 radeon_emit(cs,
3552 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3553 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3554 radeon_emit(cs,
3555 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3556 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3557
3558 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3559 }
3560
3561 if (loc->sgpr_idx != -1) {
3562 assert(!loc->indirect);
3563 assert(loc->num_sgprs == grid_used);
3564
3565 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3566 loc->sgpr_idx * 4, grid_used);
3567 radeon_emit(cs, blocks[0]);
3568 if (grid_used > 1)
3569 radeon_emit(cs, blocks[1]);
3570 if (grid_used > 2)
3571 radeon_emit(cs, blocks[2]);
3572 }
3573
3574 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3575 PKT3_SHADER_TYPE_S(1));
3576 radeon_emit(cs, blocks[0]);
3577 radeon_emit(cs, blocks[1]);
3578 radeon_emit(cs, blocks[2]);
3579 radeon_emit(cs, dispatch_initiator);
3580 }
3581
3582 assert(cmd_buffer->cs->cdw <= cdw_max);
3583 }
3584
3585 static void
3586 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3587 {
3588 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3589 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3590 VK_SHADER_STAGE_COMPUTE_BIT);
3591 }
3592
3593 static void
3594 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3595 const struct radv_dispatch_info *info)
3596 {
3597 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3598 bool pipeline_is_dirty = pipeline &&
3599 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3600
3601 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3602 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3603 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3604 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3605 /* If we have to wait for idle, set all states first, so that
3606 * all SET packets are processed in parallel with previous draw
3607 * calls. Then upload descriptors, set shader pointers, and
3608 * dispatch, and prefetch at the end. This ensures that the
3609 * time the CUs are idle is very short. (there are only SET_SH
3610 * packets between the wait and the draw)
3611 */
3612 radv_emit_compute_pipeline(cmd_buffer);
3613 si_emit_cache_flush(cmd_buffer);
3614 /* <-- CUs are idle here --> */
3615
3616 radv_upload_compute_shader_descriptors(cmd_buffer);
3617
3618 radv_emit_dispatch_packets(cmd_buffer, info);
3619 /* <-- CUs are busy here --> */
3620
3621 /* Start prefetches after the dispatch has been started. Both
3622 * will run in parallel, but starting the dispatch first is
3623 * more important.
3624 */
3625 if (pipeline_is_dirty) {
3626 radv_emit_shader_prefetch(cmd_buffer,
3627 pipeline->shaders[MESA_SHADER_COMPUTE]);
3628 }
3629 } else {
3630 /* If we don't wait for idle, start prefetches first, then set
3631 * states, and dispatch at the end.
3632 */
3633 si_emit_cache_flush(cmd_buffer);
3634
3635 if (pipeline_is_dirty) {
3636 radv_emit_shader_prefetch(cmd_buffer,
3637 pipeline->shaders[MESA_SHADER_COMPUTE]);
3638 }
3639
3640 radv_upload_compute_shader_descriptors(cmd_buffer);
3641
3642 radv_emit_compute_pipeline(cmd_buffer);
3643 radv_emit_dispatch_packets(cmd_buffer, info);
3644 }
3645
3646 radv_cmd_buffer_after_draw(cmd_buffer);
3647 }
3648
3649 void radv_CmdDispatch(
3650 VkCommandBuffer commandBuffer,
3651 uint32_t x,
3652 uint32_t y,
3653 uint32_t z)
3654 {
3655 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3656 struct radv_dispatch_info info = {};
3657
3658 info.blocks[0] = x;
3659 info.blocks[1] = y;
3660 info.blocks[2] = z;
3661
3662 radv_dispatch(cmd_buffer, &info);
3663 }
3664
3665 void radv_CmdDispatchIndirect(
3666 VkCommandBuffer commandBuffer,
3667 VkBuffer _buffer,
3668 VkDeviceSize offset)
3669 {
3670 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3671 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3672 struct radv_dispatch_info info = {};
3673
3674 info.indirect = buffer;
3675 info.indirect_offset = offset;
3676
3677 radv_dispatch(cmd_buffer, &info);
3678 }
3679
3680 void radv_unaligned_dispatch(
3681 struct radv_cmd_buffer *cmd_buffer,
3682 uint32_t x,
3683 uint32_t y,
3684 uint32_t z)
3685 {
3686 struct radv_dispatch_info info = {};
3687
3688 info.blocks[0] = x;
3689 info.blocks[1] = y;
3690 info.blocks[2] = z;
3691 info.unaligned = 1;
3692
3693 radv_dispatch(cmd_buffer, &info);
3694 }
3695
3696 void radv_CmdEndRenderPass(
3697 VkCommandBuffer commandBuffer)
3698 {
3699 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3700
3701 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3702
3703 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3704
3705 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3706 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3707 radv_handle_subpass_image_transition(cmd_buffer,
3708 (VkAttachmentReference){i, layout});
3709 }
3710
3711 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3712
3713 cmd_buffer->state.pass = NULL;
3714 cmd_buffer->state.subpass = NULL;
3715 cmd_buffer->state.attachments = NULL;
3716 cmd_buffer->state.framebuffer = NULL;
3717 }
3718
3719 /*
3720 * For HTILE we have the following interesting clear words:
3721 * 0x0000030f: Uncompressed.
3722 * 0xfffffff0: Clear depth to 1.0
3723 * 0x00000000: Clear depth to 0.0
3724 */
3725 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3726 struct radv_image *image,
3727 const VkImageSubresourceRange *range,
3728 uint32_t clear_word)
3729 {
3730 assert(range->baseMipLevel == 0);
3731 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3732 unsigned layer_count = radv_get_layerCount(image, range);
3733 uint64_t size = image->surface.htile_slice_size * layer_count;
3734 uint64_t offset = image->offset + image->htile_offset +
3735 image->surface.htile_slice_size * range->baseArrayLayer;
3736 struct radv_cmd_state *state = &cmd_buffer->state;
3737
3738 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3739 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3740
3741 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3742 size, clear_word);
3743
3744 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3745 }
3746
3747 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3748 struct radv_image *image,
3749 VkImageLayout src_layout,
3750 VkImageLayout dst_layout,
3751 unsigned src_queue_mask,
3752 unsigned dst_queue_mask,
3753 const VkImageSubresourceRange *range,
3754 VkImageAspectFlags pending_clears)
3755 {
3756 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3757 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3758 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3759 cmd_buffer->state.render_area.extent.width == image->info.width &&
3760 cmd_buffer->state.render_area.extent.height == image->info.height) {
3761 /* The clear will initialize htile. */
3762 return;
3763 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3764 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3765 /* TODO: merge with the clear if applicable */
3766 radv_initialize_htile(cmd_buffer, image, range, 0);
3767 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3768 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3769 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3770 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3771 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3772 VkImageSubresourceRange local_range = *range;
3773 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3774 local_range.baseMipLevel = 0;
3775 local_range.levelCount = 1;
3776
3777 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3778 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3779
3780 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3781
3782 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3783 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3784 }
3785 }
3786
3787 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3788 struct radv_image *image, uint32_t value)
3789 {
3790 struct radv_cmd_state *state = &cmd_buffer->state;
3791
3792 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3793 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3794
3795 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3796 image->offset + image->cmask.offset,
3797 image->cmask.size, value);
3798
3799 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3800 }
3801
3802 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3803 struct radv_image *image,
3804 VkImageLayout src_layout,
3805 VkImageLayout dst_layout,
3806 unsigned src_queue_mask,
3807 unsigned dst_queue_mask,
3808 const VkImageSubresourceRange *range)
3809 {
3810 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3811 if (image->fmask.size)
3812 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3813 else
3814 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3815 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3816 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3817 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3818 }
3819 }
3820
3821 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3822 struct radv_image *image, uint32_t value)
3823 {
3824 struct radv_cmd_state *state = &cmd_buffer->state;
3825
3826 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3827 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3828
3829 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3830 image->offset + image->dcc_offset,
3831 image->surface.dcc_size, value);
3832
3833 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3834 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3835 }
3836
3837 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3838 struct radv_image *image,
3839 VkImageLayout src_layout,
3840 VkImageLayout dst_layout,
3841 unsigned src_queue_mask,
3842 unsigned dst_queue_mask,
3843 const VkImageSubresourceRange *range)
3844 {
3845 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3846 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3847 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3848 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3849 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3850 }
3851 }
3852
3853 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3854 struct radv_image *image,
3855 VkImageLayout src_layout,
3856 VkImageLayout dst_layout,
3857 uint32_t src_family,
3858 uint32_t dst_family,
3859 const VkImageSubresourceRange *range,
3860 VkImageAspectFlags pending_clears)
3861 {
3862 if (image->exclusive && src_family != dst_family) {
3863 /* This is an acquire or a release operation and there will be
3864 * a corresponding release/acquire. Do the transition in the
3865 * most flexible queue. */
3866
3867 assert(src_family == cmd_buffer->queue_family_index ||
3868 dst_family == cmd_buffer->queue_family_index);
3869
3870 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3871 return;
3872
3873 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3874 (src_family == RADV_QUEUE_GENERAL ||
3875 dst_family == RADV_QUEUE_GENERAL))
3876 return;
3877 }
3878
3879 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3880 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3881
3882 if (image->surface.htile_size)
3883 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3884 dst_layout, src_queue_mask,
3885 dst_queue_mask, range,
3886 pending_clears);
3887
3888 if (image->cmask.size || image->fmask.size)
3889 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3890 dst_layout, src_queue_mask,
3891 dst_queue_mask, range);
3892
3893 if (image->surface.dcc_size)
3894 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3895 dst_layout, src_queue_mask,
3896 dst_queue_mask, range);
3897 }
3898
3899 void radv_CmdPipelineBarrier(
3900 VkCommandBuffer commandBuffer,
3901 VkPipelineStageFlags srcStageMask,
3902 VkPipelineStageFlags destStageMask,
3903 VkBool32 byRegion,
3904 uint32_t memoryBarrierCount,
3905 const VkMemoryBarrier* pMemoryBarriers,
3906 uint32_t bufferMemoryBarrierCount,
3907 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3908 uint32_t imageMemoryBarrierCount,
3909 const VkImageMemoryBarrier* pImageMemoryBarriers)
3910 {
3911 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3912 enum radv_cmd_flush_bits src_flush_bits = 0;
3913 enum radv_cmd_flush_bits dst_flush_bits = 0;
3914
3915 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3916 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3917 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3918 NULL);
3919 }
3920
3921 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3922 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3923 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3924 NULL);
3925 }
3926
3927 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3928 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3929 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3930 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3931 image);
3932 }
3933
3934 radv_stage_flush(cmd_buffer, srcStageMask);
3935 cmd_buffer->state.flush_bits |= src_flush_bits;
3936
3937 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3938 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3939 radv_handle_image_transition(cmd_buffer, image,
3940 pImageMemoryBarriers[i].oldLayout,
3941 pImageMemoryBarriers[i].newLayout,
3942 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3943 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3944 &pImageMemoryBarriers[i].subresourceRange,
3945 0);
3946 }
3947
3948 cmd_buffer->state.flush_bits |= dst_flush_bits;
3949 }
3950
3951
3952 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3953 struct radv_event *event,
3954 VkPipelineStageFlags stageMask,
3955 unsigned value)
3956 {
3957 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3958 uint64_t va = radv_buffer_get_va(event->bo);
3959
3960 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3961
3962 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3963
3964 /* TODO: this is overkill. Probably should figure something out from
3965 * the stage mask. */
3966
3967 si_cs_emit_write_event_eop(cs,
3968 cmd_buffer->state.predicating,
3969 cmd_buffer->device->physical_device->rad_info.chip_class,
3970 false,
3971 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3972 1, va, 2, value);
3973
3974 assert(cmd_buffer->cs->cdw <= cdw_max);
3975 }
3976
3977 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3978 VkEvent _event,
3979 VkPipelineStageFlags stageMask)
3980 {
3981 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3982 RADV_FROM_HANDLE(radv_event, event, _event);
3983
3984 write_event(cmd_buffer, event, stageMask, 1);
3985 }
3986
3987 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3988 VkEvent _event,
3989 VkPipelineStageFlags stageMask)
3990 {
3991 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3992 RADV_FROM_HANDLE(radv_event, event, _event);
3993
3994 write_event(cmd_buffer, event, stageMask, 0);
3995 }
3996
3997 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3998 uint32_t eventCount,
3999 const VkEvent* pEvents,
4000 VkPipelineStageFlags srcStageMask,
4001 VkPipelineStageFlags dstStageMask,
4002 uint32_t memoryBarrierCount,
4003 const VkMemoryBarrier* pMemoryBarriers,
4004 uint32_t bufferMemoryBarrierCount,
4005 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4006 uint32_t imageMemoryBarrierCount,
4007 const VkImageMemoryBarrier* pImageMemoryBarriers)
4008 {
4009 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4010 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4011
4012 for (unsigned i = 0; i < eventCount; ++i) {
4013 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4014 uint64_t va = radv_buffer_get_va(event->bo);
4015
4016 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4017
4018 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4019
4020 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4021 assert(cmd_buffer->cs->cdw <= cdw_max);
4022 }
4023
4024
4025 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4026 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4027
4028 radv_handle_image_transition(cmd_buffer, image,
4029 pImageMemoryBarriers[i].oldLayout,
4030 pImageMemoryBarriers[i].newLayout,
4031 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4032 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4033 &pImageMemoryBarriers[i].subresourceRange,
4034 0);
4035 }
4036
4037 /* TODO: figure out how to do memory barriers without waiting */
4038 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4039 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4040 RADV_CMD_FLAG_INV_VMEM_L1 |
4041 RADV_CMD_FLAG_INV_SMEM_L1;
4042 }