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radv: add some misc gfx9 pieces.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "gfx9d.h"
33 #include "vk_format.h"
34 #include "radv_meta.h"
35
36 #include "ac_debug.h"
37
38 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
39 struct radv_image *image,
40 VkImageLayout src_layout,
41 VkImageLayout dst_layout,
42 uint32_t src_family,
43 uint32_t dst_family,
44 const VkImageSubresourceRange *range,
45 VkImageAspectFlags pending_clears);
46
47 const struct radv_dynamic_state default_dynamic_state = {
48 .viewport = {
49 .count = 0,
50 },
51 .scissor = {
52 .count = 0,
53 },
54 .line_width = 1.0f,
55 .depth_bias = {
56 .bias = 0.0f,
57 .clamp = 0.0f,
58 .slope = 0.0f,
59 },
60 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
61 .depth_bounds = {
62 .min = 0.0f,
63 .max = 1.0f,
64 },
65 .stencil_compare_mask = {
66 .front = ~0u,
67 .back = ~0u,
68 },
69 .stencil_write_mask = {
70 .front = ~0u,
71 .back = ~0u,
72 },
73 .stencil_reference = {
74 .front = 0u,
75 .back = 0u,
76 },
77 };
78
79 void
80 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
81 const struct radv_dynamic_state *src,
82 uint32_t copy_mask)
83 {
84 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
85 dest->viewport.count = src->viewport.count;
86 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
87 src->viewport.count);
88 }
89
90 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
91 dest->scissor.count = src->scissor.count;
92 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
93 src->scissor.count);
94 }
95
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
97 dest->line_width = src->line_width;
98
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
100 dest->depth_bias = src->depth_bias;
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
103 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
106 dest->depth_bounds = src->depth_bounds;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
109 dest->stencil_compare_mask = src->stencil_compare_mask;
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
112 dest->stencil_write_mask = src->stencil_write_mask;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
115 dest->stencil_reference = src->stencil_reference;
116 }
117
118 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
119 {
120 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
121 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
122 }
123
124 enum ring_type radv_queue_family_to_ring(int f) {
125 switch (f) {
126 case RADV_QUEUE_GENERAL:
127 return RING_GFX;
128 case RADV_QUEUE_COMPUTE:
129 return RING_COMPUTE;
130 case RADV_QUEUE_TRANSFER:
131 return RING_DMA;
132 default:
133 unreachable("Unknown queue family");
134 }
135 }
136
137 static VkResult radv_create_cmd_buffer(
138 struct radv_device * device,
139 struct radv_cmd_pool * pool,
140 VkCommandBufferLevel level,
141 VkCommandBuffer* pCommandBuffer)
142 {
143 struct radv_cmd_buffer *cmd_buffer;
144 VkResult result;
145 unsigned ring;
146 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
147 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
148 if (cmd_buffer == NULL)
149 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
150
151 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
152 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
153 cmd_buffer->device = device;
154 cmd_buffer->pool = pool;
155 cmd_buffer->level = level;
156
157 if (pool) {
158 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
159 cmd_buffer->queue_family_index = pool->queue_family_index;
160
161 } else {
162 /* Init the pool_link so we can safefly call list_del when we destroy
163 * the command buffer
164 */
165 list_inithead(&cmd_buffer->pool_link);
166 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
167 }
168
169 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
170
171 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
172 if (!cmd_buffer->cs) {
173 result = VK_ERROR_OUT_OF_HOST_MEMORY;
174 goto fail;
175 }
176
177 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
178
179 cmd_buffer->upload.offset = 0;
180 cmd_buffer->upload.size = 0;
181 list_inithead(&cmd_buffer->upload.list);
182
183 return VK_SUCCESS;
184
185 fail:
186 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
187
188 return result;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
211 {
212
213 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
214
215 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
216 &cmd_buffer->upload.list, list) {
217 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
218 list_del(&up->list);
219 free(up);
220 }
221
222 cmd_buffer->scratch_size_needed = 0;
223 cmd_buffer->compute_scratch_size_needed = 0;
224 cmd_buffer->esgs_ring_size_needed = 0;
225 cmd_buffer->gsvs_ring_size_needed = 0;
226 cmd_buffer->tess_rings_needed = false;
227 cmd_buffer->sample_positions_needed = false;
228
229 if (cmd_buffer->upload.upload_bo)
230 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
231 cmd_buffer->upload.upload_bo, 8);
232 cmd_buffer->upload.offset = 0;
233
234 cmd_buffer->record_fail = false;
235
236 cmd_buffer->ring_offsets_idx = -1;
237 }
238
239 static bool
240 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
241 uint64_t min_needed)
242 {
243 uint64_t new_size;
244 struct radeon_winsys_bo *bo;
245 struct radv_cmd_buffer_upload *upload;
246 struct radv_device *device = cmd_buffer->device;
247
248 new_size = MAX2(min_needed, 16 * 1024);
249 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
250
251 bo = device->ws->buffer_create(device->ws,
252 new_size, 4096,
253 RADEON_DOMAIN_GTT,
254 RADEON_FLAG_CPU_ACCESS);
255
256 if (!bo) {
257 cmd_buffer->record_fail = true;
258 return false;
259 }
260
261 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
262 if (cmd_buffer->upload.upload_bo) {
263 upload = malloc(sizeof(*upload));
264
265 if (!upload) {
266 cmd_buffer->record_fail = true;
267 device->ws->buffer_destroy(bo);
268 return false;
269 }
270
271 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
272 list_add(&upload->list, &cmd_buffer->upload.list);
273 }
274
275 cmd_buffer->upload.upload_bo = bo;
276 cmd_buffer->upload.size = new_size;
277 cmd_buffer->upload.offset = 0;
278 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
279
280 if (!cmd_buffer->upload.map) {
281 cmd_buffer->record_fail = true;
282 return false;
283 }
284
285 return true;
286 }
287
288 bool
289 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
290 unsigned size,
291 unsigned alignment,
292 unsigned *out_offset,
293 void **ptr)
294 {
295 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
296 if (offset + size > cmd_buffer->upload.size) {
297 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
298 return false;
299 offset = 0;
300 }
301
302 *out_offset = offset;
303 *ptr = cmd_buffer->upload.map + offset;
304
305 cmd_buffer->upload.offset = offset + size;
306 return true;
307 }
308
309 bool
310 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
311 unsigned size, unsigned alignment,
312 const void *data, unsigned *out_offset)
313 {
314 uint8_t *ptr;
315
316 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
317 out_offset, (void **)&ptr))
318 return false;
319
320 if (ptr)
321 memcpy(ptr, data, size);
322
323 return true;
324 }
325
326 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
327 {
328 struct radv_device *device = cmd_buffer->device;
329 struct radeon_winsys_cs *cs = cmd_buffer->cs;
330 uint64_t va;
331
332 if (!device->trace_bo)
333 return;
334
335 va = device->ws->buffer_get_va(device->trace_bo);
336
337 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
338
339 ++cmd_buffer->state.trace_id;
340 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
341 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
342 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
343 S_370_WR_CONFIRM(1) |
344 S_370_ENGINE_SEL(V_370_ME));
345 radeon_emit(cs, va);
346 radeon_emit(cs, va >> 32);
347 radeon_emit(cs, cmd_buffer->state.trace_id);
348 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
349 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
350 }
351
352 static void
353 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
354 struct radv_pipeline *pipeline)
355 {
356 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
357 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
358 8);
359 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
360 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
361 }
362
363 static void
364 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
365 struct radv_pipeline *pipeline)
366 {
367 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
368 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
369 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
370
371 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
372 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
373 }
374
375 /* 12.4 fixed-point */
376 static unsigned radv_pack_float_12p4(float x)
377 {
378 return x <= 0 ? 0 :
379 x >= 4096 ? 0xffff : x * 16;
380 }
381
382 static uint32_t
383 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
384 {
385 switch (stage) {
386 case MESA_SHADER_FRAGMENT:
387 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
388 case MESA_SHADER_VERTEX:
389 if (has_tess)
390 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
391 else
392 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
393 case MESA_SHADER_GEOMETRY:
394 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
395 case MESA_SHADER_COMPUTE:
396 return R_00B900_COMPUTE_USER_DATA_0;
397 case MESA_SHADER_TESS_CTRL:
398 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
399 case MESA_SHADER_TESS_EVAL:
400 if (has_gs)
401 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
402 else
403 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
404 default:
405 unreachable("unknown shader");
406 }
407 }
408
409 static struct ac_userdata_info *
410 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
411 gl_shader_stage stage,
412 int idx)
413 {
414 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
415 }
416
417 static void
418 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
419 struct radv_pipeline *pipeline,
420 gl_shader_stage stage,
421 int idx, uint64_t va)
422 {
423 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
424 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
425 if (loc->sgpr_idx == -1)
426 return;
427 assert(loc->num_sgprs == 2);
428 assert(!loc->indirect);
429 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
430 radeon_emit(cmd_buffer->cs, va);
431 radeon_emit(cmd_buffer->cs, va >> 32);
432 }
433
434 static void
435 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
436 struct radv_pipeline *pipeline)
437 {
438 int num_samples = pipeline->graphics.ms.num_samples;
439 struct radv_multisample_state *ms = &pipeline->graphics.ms;
440 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
441
442 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
443 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
444 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
445
446 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
447 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
448
449 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
450 return;
451
452 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
453 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
454 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
455
456 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
457
458 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
459 uint32_t offset;
460 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
461 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
462 if (loc->sgpr_idx == -1)
463 return;
464 assert(loc->num_sgprs == 1);
465 assert(!loc->indirect);
466 switch (num_samples) {
467 default:
468 offset = 0;
469 break;
470 case 2:
471 offset = 1;
472 break;
473 case 4:
474 offset = 3;
475 break;
476 case 8:
477 offset = 7;
478 break;
479 case 16:
480 offset = 15;
481 break;
482 }
483
484 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
485 cmd_buffer->sample_positions_needed = true;
486 }
487 }
488
489 static void
490 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
491 struct radv_pipeline *pipeline)
492 {
493 struct radv_raster_state *raster = &pipeline->graphics.raster;
494
495 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
496 raster->pa_cl_clip_cntl);
497
498 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
499 raster->spi_interp_control);
500
501 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
502 unsigned tmp = (unsigned)(1.0 * 8.0);
503 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
504 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
505 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
506
507 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
508 raster->pa_su_vtx_cntl);
509
510 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
511 raster->pa_su_sc_mode_cntl);
512 }
513
514 static void
515 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
516 struct radv_pipeline *pipeline,
517 struct radv_shader_variant *shader,
518 struct ac_vs_output_info *outinfo)
519 {
520 struct radeon_winsys *ws = cmd_buffer->device->ws;
521 uint64_t va = ws->buffer_get_va(shader->bo);
522 unsigned export_count;
523
524 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
525 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
526
527 export_count = MAX2(1, outinfo->param_exports);
528 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
529 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
530
531 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
532 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
533 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
534 V_02870C_SPI_SHADER_4COMP :
535 V_02870C_SPI_SHADER_NONE) |
536 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
537 V_02870C_SPI_SHADER_4COMP :
538 V_02870C_SPI_SHADER_NONE) |
539 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
540 V_02870C_SPI_SHADER_4COMP :
541 V_02870C_SPI_SHADER_NONE));
542
543
544 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
545 radeon_emit(cmd_buffer->cs, va >> 8);
546 radeon_emit(cmd_buffer->cs, va >> 40);
547 radeon_emit(cmd_buffer->cs, shader->rsrc1);
548 radeon_emit(cmd_buffer->cs, shader->rsrc2);
549
550 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
551 S_028818_VTX_W0_FMT(1) |
552 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
553 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
554 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
555
556
557 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
558 pipeline->graphics.pa_cl_vs_out_cntl);
559
560 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
561 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
562 }
563
564 static void
565 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
566 struct radv_shader_variant *shader,
567 struct ac_es_output_info *outinfo)
568 {
569 struct radeon_winsys *ws = cmd_buffer->device->ws;
570 uint64_t va = ws->buffer_get_va(shader->bo);
571
572 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
573 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
574
575 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
576 outinfo->esgs_itemsize / 4);
577 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
578 radeon_emit(cmd_buffer->cs, va >> 8);
579 radeon_emit(cmd_buffer->cs, va >> 40);
580 radeon_emit(cmd_buffer->cs, shader->rsrc1);
581 radeon_emit(cmd_buffer->cs, shader->rsrc2);
582 }
583
584 static void
585 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
586 struct radv_shader_variant *shader)
587 {
588 struct radeon_winsys *ws = cmd_buffer->device->ws;
589 uint64_t va = ws->buffer_get_va(shader->bo);
590 uint32_t rsrc2 = shader->rsrc2;
591
592 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
593 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
594
595 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
596 radeon_emit(cmd_buffer->cs, va >> 8);
597 radeon_emit(cmd_buffer->cs, va >> 40);
598
599 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
600 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
601 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
602 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
603
604 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
605 radeon_emit(cmd_buffer->cs, shader->rsrc1);
606 radeon_emit(cmd_buffer->cs, rsrc2);
607 }
608
609 static void
610 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
611 struct radv_shader_variant *shader)
612 {
613 struct radeon_winsys *ws = cmd_buffer->device->ws;
614 uint64_t va = ws->buffer_get_va(shader->bo);
615
616 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
617 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
618
619 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
620 radeon_emit(cmd_buffer->cs, va >> 8);
621 radeon_emit(cmd_buffer->cs, va >> 40);
622 radeon_emit(cmd_buffer->cs, shader->rsrc1);
623 radeon_emit(cmd_buffer->cs, shader->rsrc2);
624 }
625
626 static void
627 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
628 struct radv_pipeline *pipeline)
629 {
630 struct radv_shader_variant *vs;
631
632 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
633
634 vs = pipeline->shaders[MESA_SHADER_VERTEX];
635
636 if (vs->info.vs.as_ls)
637 radv_emit_hw_ls(cmd_buffer, vs);
638 else if (vs->info.vs.as_es)
639 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
640 else
641 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
642
643 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
644 }
645
646
647 static void
648 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
649 struct radv_pipeline *pipeline)
650 {
651 if (!radv_pipeline_has_tess(pipeline))
652 return;
653
654 struct radv_shader_variant *tes, *tcs;
655
656 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
657 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
658
659 if (tes->info.tes.as_es)
660 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
661 else
662 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
663
664 radv_emit_hw_hs(cmd_buffer, tcs);
665
666 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
667 pipeline->graphics.tess.tf_param);
668
669 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
670 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
671 pipeline->graphics.tess.ls_hs_config);
672 else
673 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
674 pipeline->graphics.tess.ls_hs_config);
675
676 struct ac_userdata_info *loc;
677
678 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
679 if (loc->sgpr_idx != -1) {
680 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
681 assert(loc->num_sgprs == 4);
682 assert(!loc->indirect);
683 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
684 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
685 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
686 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
687 pipeline->graphics.tess.num_tcs_input_cp << 26);
688 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
689 }
690
691 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
692 if (loc->sgpr_idx != -1) {
693 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
694 assert(loc->num_sgprs == 1);
695 assert(!loc->indirect);
696
697 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
698 pipeline->graphics.tess.offchip_layout);
699 }
700
701 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
702 if (loc->sgpr_idx != -1) {
703 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
704 assert(loc->num_sgprs == 1);
705 assert(!loc->indirect);
706
707 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
708 pipeline->graphics.tess.tcs_in_layout);
709 }
710 }
711
712 static void
713 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
714 struct radv_pipeline *pipeline)
715 {
716 struct radeon_winsys *ws = cmd_buffer->device->ws;
717 struct radv_shader_variant *gs;
718 uint64_t va;
719
720 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
721
722 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
723 if (!gs)
724 return;
725
726 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
727
728 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
729 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
730 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
731 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
732
733 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
734
735 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
736
737 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
738 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
739 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
740 radeon_emit(cmd_buffer->cs, 0);
741 radeon_emit(cmd_buffer->cs, 0);
742 radeon_emit(cmd_buffer->cs, 0);
743
744 uint32_t gs_num_invocations = gs->info.gs.invocations;
745 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
746 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
747 S_028B90_ENABLE(gs_num_invocations > 0));
748
749 va = ws->buffer_get_va(gs->bo);
750 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
751 si_cp_dma_prefetch(cmd_buffer, va, gs->code_size);
752 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
753 radeon_emit(cmd_buffer->cs, va >> 8);
754 radeon_emit(cmd_buffer->cs, va >> 40);
755 radeon_emit(cmd_buffer->cs, gs->rsrc1);
756 radeon_emit(cmd_buffer->cs, gs->rsrc2);
757
758 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
759
760 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
761 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
762 if (loc->sgpr_idx != -1) {
763 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
764 uint32_t num_entries = 64;
765 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
766
767 if (is_vi)
768 num_entries *= stride;
769
770 stride = S_008F04_STRIDE(stride);
771 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
772 radeon_emit(cmd_buffer->cs, stride);
773 radeon_emit(cmd_buffer->cs, num_entries);
774 }
775 }
776
777 static void
778 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
779 struct radv_pipeline *pipeline)
780 {
781 struct radeon_winsys *ws = cmd_buffer->device->ws;
782 struct radv_shader_variant *ps;
783 uint64_t va;
784 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
785 struct radv_blend_state *blend = &pipeline->graphics.blend;
786 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
787
788 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
789
790 va = ws->buffer_get_va(ps->bo);
791 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
792 si_cp_dma_prefetch(cmd_buffer, va, ps->code_size);
793
794 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
795 radeon_emit(cmd_buffer->cs, va >> 8);
796 radeon_emit(cmd_buffer->cs, va >> 40);
797 radeon_emit(cmd_buffer->cs, ps->rsrc1);
798 radeon_emit(cmd_buffer->cs, ps->rsrc2);
799
800 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
801 pipeline->graphics.db_shader_control);
802
803 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
804 ps->config.spi_ps_input_ena);
805
806 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
807 ps->config.spi_ps_input_addr);
808
809 if (ps->info.fs.force_persample)
810 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
811
812 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
813 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
814
815 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
816
817 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
818 pipeline->graphics.shader_z_format);
819
820 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
821
822 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
823 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
824
825 if (pipeline->graphics.ps_input_cntl_num) {
826 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
827 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
828 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
829 }
830 }
831 }
832
833 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
834 struct radv_pipeline *pipeline)
835 {
836 uint32_t vtx_reuse_depth = 30;
837 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
838 return;
839
840 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
841 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
842 vtx_reuse_depth = 14;
843 }
844 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
845 vtx_reuse_depth);
846 }
847
848 static void
849 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
850 struct radv_pipeline *pipeline)
851 {
852 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
853 return;
854
855 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
856 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
857 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
858 radv_update_multisample_state(cmd_buffer, pipeline);
859 radv_emit_vertex_shader(cmd_buffer, pipeline);
860 radv_emit_tess_shaders(cmd_buffer, pipeline);
861 radv_emit_geometry_shader(cmd_buffer, pipeline);
862 radv_emit_fragment_shader(cmd_buffer, pipeline);
863 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
864
865 cmd_buffer->scratch_size_needed =
866 MAX2(cmd_buffer->scratch_size_needed,
867 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
868
869 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
870 S_0286E8_WAVES(pipeline->max_waves) |
871 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
872
873 if (!cmd_buffer->state.emitted_pipeline ||
874 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
875 pipeline->graphics.can_use_guardband)
876 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
877 cmd_buffer->state.emitted_pipeline = pipeline;
878 }
879
880 static void
881 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
882 {
883 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
884 cmd_buffer->state.dynamic.viewport.viewports);
885 }
886
887 static void
888 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
889 {
890 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
891 si_write_scissors(cmd_buffer->cs, 0, count,
892 cmd_buffer->state.dynamic.scissor.scissors,
893 cmd_buffer->state.dynamic.viewport.viewports,
894 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
895 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
896 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
897 }
898
899 static void
900 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
901 int index,
902 struct radv_color_buffer_info *cb)
903 {
904 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
905 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
906 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
907 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
908 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
909 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
910 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
911 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
912 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
913 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
914 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
915 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
916 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
917
918 if (is_vi) { /* DCC BASE */
919 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
920 }
921 }
922
923 static void
924 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
925 struct radv_ds_buffer_info *ds,
926 struct radv_image *image,
927 VkImageLayout layout)
928 {
929 uint32_t db_z_info = ds->db_z_info;
930 uint32_t db_stencil_info = ds->db_stencil_info;
931
932 if (!radv_layout_has_htile(image, layout,
933 radv_image_queue_family_mask(image,
934 cmd_buffer->queue_family_index,
935 cmd_buffer->queue_family_index))) {
936 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
937 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
938 }
939
940 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
941 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
942
943 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
944 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
945 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
946 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
947 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
948 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
949 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
950 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
951 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
952 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
953
954 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
955 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
956 ds->pa_su_poly_offset_db_fmt_cntl);
957 }
958
959 void
960 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
961 struct radv_image *image,
962 VkClearDepthStencilValue ds_clear_value,
963 VkImageAspectFlags aspects)
964 {
965 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
966 va += image->offset + image->clear_value_offset;
967 unsigned reg_offset = 0, reg_count = 0;
968
969 if (!image->surface.htile_size || !aspects)
970 return;
971
972 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
973 ++reg_count;
974 } else {
975 ++reg_offset;
976 va += 4;
977 }
978 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
979 ++reg_count;
980
981 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
982
983 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
984 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
985 S_370_WR_CONFIRM(1) |
986 S_370_ENGINE_SEL(V_370_PFP));
987 radeon_emit(cmd_buffer->cs, va);
988 radeon_emit(cmd_buffer->cs, va >> 32);
989 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
990 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
991 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
992 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
993
994 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
995 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
996 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
997 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
998 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
999 }
1000
1001 static void
1002 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1003 struct radv_image *image)
1004 {
1005 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1006 va += image->offset + image->clear_value_offset;
1007
1008 if (!image->surface.htile_size)
1009 return;
1010
1011 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1012
1013 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1014 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1015 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1016 COPY_DATA_COUNT_SEL);
1017 radeon_emit(cmd_buffer->cs, va);
1018 radeon_emit(cmd_buffer->cs, va >> 32);
1019 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1020 radeon_emit(cmd_buffer->cs, 0);
1021
1022 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1023 radeon_emit(cmd_buffer->cs, 0);
1024 }
1025
1026 void
1027 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1028 struct radv_image *image,
1029 int idx,
1030 uint32_t color_values[2])
1031 {
1032 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1033 va += image->offset + image->clear_value_offset;
1034
1035 if (!image->cmask.size && !image->surface.dcc_size)
1036 return;
1037
1038 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1039
1040 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1041 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1042 S_370_WR_CONFIRM(1) |
1043 S_370_ENGINE_SEL(V_370_PFP));
1044 radeon_emit(cmd_buffer->cs, va);
1045 radeon_emit(cmd_buffer->cs, va >> 32);
1046 radeon_emit(cmd_buffer->cs, color_values[0]);
1047 radeon_emit(cmd_buffer->cs, color_values[1]);
1048
1049 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1050 radeon_emit(cmd_buffer->cs, color_values[0]);
1051 radeon_emit(cmd_buffer->cs, color_values[1]);
1052 }
1053
1054 static void
1055 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1056 struct radv_image *image,
1057 int idx)
1058 {
1059 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1060 va += image->offset + image->clear_value_offset;
1061
1062 if (!image->cmask.size && !image->surface.dcc_size)
1063 return;
1064
1065 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1066 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1067
1068 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1069 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1070 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1071 COPY_DATA_COUNT_SEL);
1072 radeon_emit(cmd_buffer->cs, va);
1073 radeon_emit(cmd_buffer->cs, va >> 32);
1074 radeon_emit(cmd_buffer->cs, reg >> 2);
1075 radeon_emit(cmd_buffer->cs, 0);
1076
1077 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1078 radeon_emit(cmd_buffer->cs, 0);
1079 }
1080
1081 void
1082 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1083 {
1084 int i;
1085 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1086 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1087
1088 for (i = 0; i < subpass->color_count; ++i) {
1089 int idx = subpass->color_attachments[i].attachment;
1090 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1091
1092 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1093
1094 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1095 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1096
1097 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1098 }
1099
1100 for (i = subpass->color_count; i < 8; i++)
1101 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1102 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1103
1104 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1105 int idx = subpass->depth_stencil_attachment.attachment;
1106 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1107 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1108 struct radv_image *image = att->attachment->image;
1109 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1110 uint32_t queue_mask = radv_image_queue_family_mask(image,
1111 cmd_buffer->queue_family_index,
1112 cmd_buffer->queue_family_index);
1113 /* We currently don't support writing decompressed HTILE */
1114 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1115 radv_layout_is_htile_compressed(image, layout, queue_mask));
1116
1117 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1118
1119 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1120 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1121 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1122 }
1123 radv_load_depth_clear_regs(cmd_buffer, image);
1124 } else {
1125 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1126 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1127 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1128 }
1129 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1130 S_028208_BR_X(framebuffer->width) |
1131 S_028208_BR_Y(framebuffer->height));
1132 }
1133
1134 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1135 {
1136 uint32_t db_count_control;
1137
1138 if(!cmd_buffer->state.active_occlusion_queries) {
1139 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1140 db_count_control = 0;
1141 } else {
1142 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1143 }
1144 } else {
1145 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1146 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1147 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1148 S_028004_ZPASS_ENABLE(1) |
1149 S_028004_SLICE_EVEN_ENABLE(1) |
1150 S_028004_SLICE_ODD_ENABLE(1);
1151 } else {
1152 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1153 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1154 }
1155 }
1156
1157 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1158 }
1159
1160 static void
1161 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1162 {
1163 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1164
1165 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1166 return;
1167
1168 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1169 radv_emit_viewport(cmd_buffer);
1170
1171 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1172 radv_emit_scissor(cmd_buffer);
1173
1174 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1175 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1176 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1177 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1178 }
1179
1180 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1181 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1182 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1183 }
1184
1185 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1186 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1187 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1188 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1189 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1190 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1191 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1192 S_028430_STENCILOPVAL(1));
1193 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1194 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1195 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1196 S_028434_STENCILOPVAL_BF(1));
1197 }
1198
1199 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1200 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1201 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1202 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1203 }
1204
1205 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1206 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1207 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1208 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1209 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1210
1211 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1212 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1213 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1214 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1215 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1216 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1217 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1218 }
1219 }
1220
1221 cmd_buffer->state.dirty = 0;
1222 }
1223
1224 static void
1225 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1226 struct radv_pipeline *pipeline,
1227 int idx,
1228 uint64_t va,
1229 gl_shader_stage stage)
1230 {
1231 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1232 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1233
1234 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1235 return;
1236
1237 assert(!desc_set_loc->indirect);
1238 assert(desc_set_loc->num_sgprs == 2);
1239 radeon_set_sh_reg_seq(cmd_buffer->cs,
1240 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1241 radeon_emit(cmd_buffer->cs, va);
1242 radeon_emit(cmd_buffer->cs, va >> 32);
1243 }
1244
1245 static void
1246 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1247 VkShaderStageFlags stages,
1248 struct radv_descriptor_set *set,
1249 unsigned idx)
1250 {
1251 if (cmd_buffer->state.pipeline) {
1252 radv_foreach_stage(stage, stages) {
1253 if (cmd_buffer->state.pipeline->shaders[stage])
1254 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1255 idx, set->va,
1256 stage);
1257 }
1258 }
1259
1260 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1261 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1262 idx, set->va,
1263 MESA_SHADER_COMPUTE);
1264 }
1265
1266 static void
1267 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1268 {
1269 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1270 uint32_t *ptr = NULL;
1271 unsigned bo_offset;
1272
1273 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1274 &bo_offset,
1275 (void**) &ptr))
1276 return;
1277
1278 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1279 set->va += bo_offset;
1280
1281 memcpy(ptr, set->mapped_ptr, set->size);
1282 }
1283
1284 static void
1285 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1286 {
1287 uint32_t size = MAX_SETS * 2 * 4;
1288 uint32_t offset;
1289 void *ptr;
1290
1291 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1292 256, &offset, &ptr))
1293 return;
1294
1295 for (unsigned i = 0; i < MAX_SETS; i++) {
1296 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1297 uint64_t set_va = 0;
1298 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1299 if (set)
1300 set_va = set->va;
1301 uptr[0] = set_va & 0xffffffff;
1302 uptr[1] = set_va >> 32;
1303 }
1304
1305 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1306 va += offset;
1307
1308 if (cmd_buffer->state.pipeline) {
1309 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1310 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1311 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1312
1313 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1314 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1315 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1316
1317 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1318 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1319 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1320
1321 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1322 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1323 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1324
1325 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1326 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1327 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1328 }
1329
1330 if (cmd_buffer->state.compute_pipeline)
1331 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1332 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1333 }
1334
1335 static void
1336 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1337 VkShaderStageFlags stages)
1338 {
1339 unsigned i;
1340
1341 if (!cmd_buffer->state.descriptors_dirty)
1342 return;
1343
1344 if (cmd_buffer->state.push_descriptors_dirty)
1345 radv_flush_push_descriptors(cmd_buffer);
1346
1347 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1348 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1349 radv_flush_indirect_descriptor_sets(cmd_buffer);
1350 }
1351
1352 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1353 cmd_buffer->cs,
1354 MAX_SETS * MESA_SHADER_STAGES * 4);
1355
1356 for (i = 0; i < MAX_SETS; i++) {
1357 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1358 continue;
1359 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1360 if (!set)
1361 continue;
1362
1363 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1364 }
1365 cmd_buffer->state.descriptors_dirty = 0;
1366 cmd_buffer->state.push_descriptors_dirty = false;
1367 assert(cmd_buffer->cs->cdw <= cdw_max);
1368 }
1369
1370 static void
1371 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1372 struct radv_pipeline *pipeline,
1373 VkShaderStageFlags stages)
1374 {
1375 struct radv_pipeline_layout *layout = pipeline->layout;
1376 unsigned offset;
1377 void *ptr;
1378 uint64_t va;
1379
1380 stages &= cmd_buffer->push_constant_stages;
1381 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1382 return;
1383
1384 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1385 16 * layout->dynamic_offset_count,
1386 256, &offset, &ptr))
1387 return;
1388
1389 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1390 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1391 16 * layout->dynamic_offset_count);
1392
1393 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1394 va += offset;
1395
1396 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1397 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1398
1399 radv_foreach_stage(stage, stages) {
1400 if (pipeline->shaders[stage]) {
1401 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1402 AC_UD_PUSH_CONSTANTS, va);
1403 }
1404 }
1405
1406 cmd_buffer->push_constant_stages &= ~stages;
1407 assert(cmd_buffer->cs->cdw <= cdw_max);
1408 }
1409
1410 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1411 bool indexed_draw)
1412 {
1413 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1414
1415 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1416 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1417 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1418 primitive_reset_en);
1419 }
1420
1421 if (primitive_reset_en) {
1422 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1423
1424 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1425 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1426 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1427 primitive_reset_index);
1428 }
1429 }
1430 }
1431
1432 static void
1433 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1434 bool indexed_draw, bool instanced_draw,
1435 bool indirect_draw,
1436 uint32_t draw_vertex_count)
1437 {
1438 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1439 struct radv_device *device = cmd_buffer->device;
1440 uint32_t ia_multi_vgt_param;
1441
1442 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1443 cmd_buffer->cs, 4096);
1444
1445 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1446 cmd_buffer->state.pipeline->num_vertex_attribs &&
1447 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1448 unsigned vb_offset;
1449 void *vb_ptr;
1450 uint32_t i = 0;
1451 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1452 uint64_t va;
1453
1454 /* allocate some descriptor state for vertex buffers */
1455 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1456 &vb_offset, &vb_ptr);
1457
1458 for (i = 0; i < num_attribs; i++) {
1459 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1460 uint32_t offset;
1461 int vb = cmd_buffer->state.pipeline->va_binding[i];
1462 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1463 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1464
1465 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1466 va = device->ws->buffer_get_va(buffer->bo);
1467
1468 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1469 va += offset + buffer->offset;
1470 desc[0] = va;
1471 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1472 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1473 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1474 else
1475 desc[2] = buffer->size - offset;
1476 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1477 }
1478
1479 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1480 va += vb_offset;
1481
1482 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1483 AC_UD_VS_VERTEX_BUFFERS, va);
1484 }
1485
1486 cmd_buffer->state.vertex_descriptors_dirty = false;
1487 cmd_buffer->state.vb_dirty = 0;
1488 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1489 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1490
1491 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1492 radv_emit_framebuffer_state(cmd_buffer);
1493
1494 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1495 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1496 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1497 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1498 else
1499 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1500 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1501 }
1502
1503 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1504 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1505
1506 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1507 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1508 } else {
1509 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1510 }
1511 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1512 }
1513
1514 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1515
1516 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1517
1518 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1519 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1520 VK_SHADER_STAGE_ALL_GRAPHICS);
1521
1522 assert(cmd_buffer->cs->cdw <= cdw_max);
1523
1524 si_emit_cache_flush(cmd_buffer);
1525 }
1526
1527 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1528 VkPipelineStageFlags src_stage_mask)
1529 {
1530 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1531 VK_PIPELINE_STAGE_TRANSFER_BIT |
1532 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1533 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1534 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1535 }
1536
1537 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1538 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1539 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1540 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1541 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1542 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1543 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1544 VK_PIPELINE_STAGE_TRANSFER_BIT |
1545 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1546 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1547 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1548 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1549 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1550 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1551 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1552 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1553 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1554 }
1555 }
1556
1557 static enum radv_cmd_flush_bits
1558 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1559 VkAccessFlags src_flags)
1560 {
1561 enum radv_cmd_flush_bits flush_bits = 0;
1562 uint32_t b;
1563 for_each_bit(b, src_flags) {
1564 switch ((VkAccessFlagBits)(1 << b)) {
1565 case VK_ACCESS_SHADER_WRITE_BIT:
1566 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1567 break;
1568 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1569 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1570 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1571 break;
1572 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1573 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1574 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1575 break;
1576 case VK_ACCESS_TRANSFER_WRITE_BIT:
1577 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1578 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1579 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1580 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1581 RADV_CMD_FLAG_INV_GLOBAL_L2;
1582 break;
1583 default:
1584 break;
1585 }
1586 }
1587 return flush_bits;
1588 }
1589
1590 static enum radv_cmd_flush_bits
1591 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1592 VkAccessFlags dst_flags,
1593 struct radv_image *image)
1594 {
1595 enum radv_cmd_flush_bits flush_bits = 0;
1596 uint32_t b;
1597 for_each_bit(b, dst_flags) {
1598 switch ((VkAccessFlagBits)(1 << b)) {
1599 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1600 case VK_ACCESS_INDEX_READ_BIT:
1601 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1602 break;
1603 case VK_ACCESS_UNIFORM_READ_BIT:
1604 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1605 break;
1606 case VK_ACCESS_SHADER_READ_BIT:
1607 case VK_ACCESS_TRANSFER_READ_BIT:
1608 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1609 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1610 RADV_CMD_FLAG_INV_GLOBAL_L2;
1611 break;
1612 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1613 /* TODO: change to image && when the image gets passed
1614 * through from the subpass. */
1615 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1616 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1617 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1618 break;
1619 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1620 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1621 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1622 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1623 break;
1624 default:
1625 break;
1626 }
1627 }
1628 return flush_bits;
1629 }
1630
1631 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1632 {
1633 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1634 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1635 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1636 NULL);
1637 }
1638
1639 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1640 VkAttachmentReference att)
1641 {
1642 unsigned idx = att.attachment;
1643 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1644 VkImageSubresourceRange range;
1645 range.aspectMask = 0;
1646 range.baseMipLevel = view->base_mip;
1647 range.levelCount = 1;
1648 range.baseArrayLayer = view->base_layer;
1649 range.layerCount = cmd_buffer->state.framebuffer->layers;
1650
1651 radv_handle_image_transition(cmd_buffer,
1652 view->image,
1653 cmd_buffer->state.attachments[idx].current_layout,
1654 att.layout, 0, 0, &range,
1655 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1656
1657 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1658
1659
1660 }
1661
1662 void
1663 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1664 const struct radv_subpass *subpass, bool transitions)
1665 {
1666 if (transitions) {
1667 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1668
1669 for (unsigned i = 0; i < subpass->color_count; ++i) {
1670 radv_handle_subpass_image_transition(cmd_buffer,
1671 subpass->color_attachments[i]);
1672 }
1673
1674 for (unsigned i = 0; i < subpass->input_count; ++i) {
1675 radv_handle_subpass_image_transition(cmd_buffer,
1676 subpass->input_attachments[i]);
1677 }
1678
1679 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1680 radv_handle_subpass_image_transition(cmd_buffer,
1681 subpass->depth_stencil_attachment);
1682 }
1683 }
1684
1685 cmd_buffer->state.subpass = subpass;
1686
1687 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1688 }
1689
1690 static void
1691 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1692 struct radv_render_pass *pass,
1693 const VkRenderPassBeginInfo *info)
1694 {
1695 struct radv_cmd_state *state = &cmd_buffer->state;
1696
1697 if (pass->attachment_count == 0) {
1698 state->attachments = NULL;
1699 return;
1700 }
1701
1702 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1703 pass->attachment_count *
1704 sizeof(state->attachments[0]),
1705 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1706 if (state->attachments == NULL) {
1707 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1708 abort();
1709 }
1710
1711 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1712 struct radv_render_pass_attachment *att = &pass->attachments[i];
1713 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1714 VkImageAspectFlags clear_aspects = 0;
1715
1716 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1717 /* color attachment */
1718 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1719 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1720 }
1721 } else {
1722 /* depthstencil attachment */
1723 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1724 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1725 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1726 }
1727 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1728 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1729 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1730 }
1731 }
1732
1733 state->attachments[i].pending_clear_aspects = clear_aspects;
1734 if (clear_aspects && info) {
1735 assert(info->clearValueCount > i);
1736 state->attachments[i].clear_value = info->pClearValues[i];
1737 }
1738
1739 state->attachments[i].current_layout = att->initial_layout;
1740 }
1741 }
1742
1743 VkResult radv_AllocateCommandBuffers(
1744 VkDevice _device,
1745 const VkCommandBufferAllocateInfo *pAllocateInfo,
1746 VkCommandBuffer *pCommandBuffers)
1747 {
1748 RADV_FROM_HANDLE(radv_device, device, _device);
1749 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1750
1751 VkResult result = VK_SUCCESS;
1752 uint32_t i;
1753
1754 memset(pCommandBuffers, 0,
1755 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1756
1757 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1758
1759 if (!list_empty(&pool->free_cmd_buffers)) {
1760 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1761
1762 list_del(&cmd_buffer->pool_link);
1763 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1764
1765 radv_reset_cmd_buffer(cmd_buffer);
1766 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1767 cmd_buffer->level = pAllocateInfo->level;
1768
1769 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1770 result = VK_SUCCESS;
1771 } else {
1772 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1773 &pCommandBuffers[i]);
1774 }
1775 if (result != VK_SUCCESS)
1776 break;
1777 }
1778
1779 if (result != VK_SUCCESS)
1780 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1781 i, pCommandBuffers);
1782
1783 return result;
1784 }
1785
1786 void radv_FreeCommandBuffers(
1787 VkDevice device,
1788 VkCommandPool commandPool,
1789 uint32_t commandBufferCount,
1790 const VkCommandBuffer *pCommandBuffers)
1791 {
1792 for (uint32_t i = 0; i < commandBufferCount; i++) {
1793 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1794
1795 if (cmd_buffer) {
1796 if (cmd_buffer->pool) {
1797 list_del(&cmd_buffer->pool_link);
1798 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1799 } else
1800 radv_cmd_buffer_destroy(cmd_buffer);
1801
1802 }
1803 }
1804 }
1805
1806 VkResult radv_ResetCommandBuffer(
1807 VkCommandBuffer commandBuffer,
1808 VkCommandBufferResetFlags flags)
1809 {
1810 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1811 radv_reset_cmd_buffer(cmd_buffer);
1812 return VK_SUCCESS;
1813 }
1814
1815 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1816 {
1817 struct radv_device *device = cmd_buffer->device;
1818 if (device->gfx_init) {
1819 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1820 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1821 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1822 radeon_emit(cmd_buffer->cs, va);
1823 radeon_emit(cmd_buffer->cs, (va >> 32) & 0xffff);
1824 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1825 } else
1826 si_init_config(cmd_buffer);
1827 }
1828
1829 VkResult radv_BeginCommandBuffer(
1830 VkCommandBuffer commandBuffer,
1831 const VkCommandBufferBeginInfo *pBeginInfo)
1832 {
1833 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1834 radv_reset_cmd_buffer(cmd_buffer);
1835
1836 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1837 cmd_buffer->state.last_primitive_reset_en = -1;
1838
1839 /* setup initial configuration into command buffer */
1840 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1841 switch (cmd_buffer->queue_family_index) {
1842 case RADV_QUEUE_GENERAL:
1843 emit_gfx_buffer_state(cmd_buffer);
1844 radv_set_db_count_control(cmd_buffer);
1845 break;
1846 case RADV_QUEUE_COMPUTE:
1847 si_init_compute(cmd_buffer);
1848 break;
1849 case RADV_QUEUE_TRANSFER:
1850 default:
1851 break;
1852 }
1853 }
1854
1855 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1856 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1857 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1858
1859 struct radv_subpass *subpass =
1860 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1861
1862 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1863 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1864 }
1865
1866 radv_cmd_buffer_trace_emit(cmd_buffer);
1867 return VK_SUCCESS;
1868 }
1869
1870 void radv_CmdBindVertexBuffers(
1871 VkCommandBuffer commandBuffer,
1872 uint32_t firstBinding,
1873 uint32_t bindingCount,
1874 const VkBuffer* pBuffers,
1875 const VkDeviceSize* pOffsets)
1876 {
1877 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1878 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1879
1880 /* We have to defer setting up vertex buffer since we need the buffer
1881 * stride from the pipeline. */
1882
1883 assert(firstBinding + bindingCount < MAX_VBS);
1884 for (uint32_t i = 0; i < bindingCount; i++) {
1885 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1886 vb[firstBinding + i].offset = pOffsets[i];
1887 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1888 }
1889 }
1890
1891 void radv_CmdBindIndexBuffer(
1892 VkCommandBuffer commandBuffer,
1893 VkBuffer buffer,
1894 VkDeviceSize offset,
1895 VkIndexType indexType)
1896 {
1897 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1898
1899 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1900 cmd_buffer->state.index_offset = offset;
1901 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1902 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1903 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1904 }
1905
1906
1907 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1908 struct radv_descriptor_set *set,
1909 unsigned idx)
1910 {
1911 struct radeon_winsys *ws = cmd_buffer->device->ws;
1912
1913 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
1914
1915 cmd_buffer->state.descriptors[idx] = set;
1916 cmd_buffer->state.descriptors_dirty |= (1u << idx);
1917 if (!set)
1918 return;
1919
1920 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1921 if (set->descriptors[j])
1922 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1923
1924 if(set->bo)
1925 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1926 }
1927
1928 void radv_CmdBindDescriptorSets(
1929 VkCommandBuffer commandBuffer,
1930 VkPipelineBindPoint pipelineBindPoint,
1931 VkPipelineLayout _layout,
1932 uint32_t firstSet,
1933 uint32_t descriptorSetCount,
1934 const VkDescriptorSet* pDescriptorSets,
1935 uint32_t dynamicOffsetCount,
1936 const uint32_t* pDynamicOffsets)
1937 {
1938 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1939 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1940 unsigned dyn_idx = 0;
1941
1942 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1943 unsigned idx = i + firstSet;
1944 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1945 radv_bind_descriptor_set(cmd_buffer, set, idx);
1946
1947 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1948 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1949 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1950 assert(dyn_idx < dynamicOffsetCount);
1951
1952 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1953 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1954 dst[0] = va;
1955 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1956 dst[2] = range->size;
1957 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1958 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1959 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1960 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1961 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1962 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1963 cmd_buffer->push_constant_stages |=
1964 set->layout->dynamic_shader_stages;
1965 }
1966 }
1967 }
1968
1969 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1970 struct radv_descriptor_set *set,
1971 struct radv_descriptor_set_layout *layout)
1972 {
1973 set->size = layout->size;
1974 set->layout = layout;
1975
1976 if (cmd_buffer->push_descriptors.capacity < set->size) {
1977 size_t new_size = MAX2(set->size, 1024);
1978 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
1979 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
1980
1981 free(set->mapped_ptr);
1982 set->mapped_ptr = malloc(new_size);
1983
1984 if (!set->mapped_ptr) {
1985 cmd_buffer->push_descriptors.capacity = 0;
1986 cmd_buffer->record_fail = true;
1987 return false;
1988 }
1989
1990 cmd_buffer->push_descriptors.capacity = new_size;
1991 }
1992
1993 return true;
1994 }
1995
1996 void radv_meta_push_descriptor_set(
1997 struct radv_cmd_buffer* cmd_buffer,
1998 VkPipelineBindPoint pipelineBindPoint,
1999 VkPipelineLayout _layout,
2000 uint32_t set,
2001 uint32_t descriptorWriteCount,
2002 const VkWriteDescriptorSet* pDescriptorWrites)
2003 {
2004 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2005 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2006 unsigned bo_offset;
2007
2008 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2009
2010 push_set->size = layout->set[set].layout->size;
2011 push_set->layout = layout->set[set].layout;
2012
2013 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2014 &bo_offset,
2015 (void**) &push_set->mapped_ptr))
2016 return;
2017
2018 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2019 push_set->va += bo_offset;
2020
2021 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2022 radv_descriptor_set_to_handle(push_set),
2023 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2024
2025 cmd_buffer->state.descriptors[set] = push_set;
2026 cmd_buffer->state.descriptors_dirty |= (1u << set);
2027 }
2028
2029 void radv_CmdPushDescriptorSetKHR(
2030 VkCommandBuffer commandBuffer,
2031 VkPipelineBindPoint pipelineBindPoint,
2032 VkPipelineLayout _layout,
2033 uint32_t set,
2034 uint32_t descriptorWriteCount,
2035 const VkWriteDescriptorSet* pDescriptorWrites)
2036 {
2037 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2038 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2039 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2040
2041 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2042
2043 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2044 return;
2045
2046 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2047 radv_descriptor_set_to_handle(push_set),
2048 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2049
2050 cmd_buffer->state.descriptors[set] = push_set;
2051 cmd_buffer->state.descriptors_dirty |= (1u << set);
2052 cmd_buffer->state.push_descriptors_dirty = true;
2053 }
2054
2055 void radv_CmdPushDescriptorSetWithTemplateKHR(
2056 VkCommandBuffer commandBuffer,
2057 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2058 VkPipelineLayout _layout,
2059 uint32_t set,
2060 const void* pData)
2061 {
2062 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2063 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2064 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2065
2066 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2067
2068 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2069 return;
2070
2071 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2072 descriptorUpdateTemplate, pData);
2073
2074 cmd_buffer->state.descriptors[set] = push_set;
2075 cmd_buffer->state.descriptors_dirty |= (1u << set);
2076 cmd_buffer->state.push_descriptors_dirty = true;
2077 }
2078
2079 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2080 VkPipelineLayout layout,
2081 VkShaderStageFlags stageFlags,
2082 uint32_t offset,
2083 uint32_t size,
2084 const void* pValues)
2085 {
2086 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2087 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2088 cmd_buffer->push_constant_stages |= stageFlags;
2089 }
2090
2091 VkResult radv_EndCommandBuffer(
2092 VkCommandBuffer commandBuffer)
2093 {
2094 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2095
2096 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
2097 si_emit_cache_flush(cmd_buffer);
2098
2099 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
2100 cmd_buffer->record_fail)
2101 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2102 return VK_SUCCESS;
2103 }
2104
2105 static void
2106 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2107 {
2108 struct radeon_winsys *ws = cmd_buffer->device->ws;
2109 struct radv_shader_variant *compute_shader;
2110 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2111 uint64_t va;
2112
2113 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2114 return;
2115
2116 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2117
2118 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2119 va = ws->buffer_get_va(compute_shader->bo);
2120
2121 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2122 si_cp_dma_prefetch(cmd_buffer, va, compute_shader->code_size);
2123
2124 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2125 cmd_buffer->cs, 16);
2126
2127 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2128 radeon_emit(cmd_buffer->cs, va >> 8);
2129 radeon_emit(cmd_buffer->cs, va >> 40);
2130
2131 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2132 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2133 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2134
2135
2136 cmd_buffer->compute_scratch_size_needed =
2137 MAX2(cmd_buffer->compute_scratch_size_needed,
2138 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2139
2140 /* change these once we have scratch support */
2141 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2142 S_00B860_WAVES(pipeline->max_waves) |
2143 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2144
2145 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2146 radeon_emit(cmd_buffer->cs,
2147 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2148 radeon_emit(cmd_buffer->cs,
2149 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2150 radeon_emit(cmd_buffer->cs,
2151 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2152
2153 assert(cmd_buffer->cs->cdw <= cdw_max);
2154 }
2155
2156 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2157 {
2158 for (unsigned i = 0; i < MAX_SETS; i++) {
2159 if (cmd_buffer->state.descriptors[i])
2160 cmd_buffer->state.descriptors_dirty |= (1u << i);
2161 }
2162 }
2163
2164 void radv_CmdBindPipeline(
2165 VkCommandBuffer commandBuffer,
2166 VkPipelineBindPoint pipelineBindPoint,
2167 VkPipeline _pipeline)
2168 {
2169 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2170 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2171
2172 radv_mark_descriptor_sets_dirty(cmd_buffer);
2173
2174 switch (pipelineBindPoint) {
2175 case VK_PIPELINE_BIND_POINT_COMPUTE:
2176 cmd_buffer->state.compute_pipeline = pipeline;
2177 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2178 break;
2179 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2180 cmd_buffer->state.pipeline = pipeline;
2181 if (!pipeline)
2182 break;
2183
2184 cmd_buffer->state.vertex_descriptors_dirty = true;
2185 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2186 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2187
2188 /* Apply the dynamic state from the pipeline */
2189 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2190 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2191 &pipeline->dynamic_state,
2192 pipeline->dynamic_state_mask);
2193
2194 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2195 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2196 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2197 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2198
2199 if (radv_pipeline_has_tess(pipeline))
2200 cmd_buffer->tess_rings_needed = true;
2201
2202 if (radv_pipeline_has_gs(pipeline)) {
2203 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2204 AC_UD_SCRATCH_RING_OFFSETS);
2205 if (cmd_buffer->ring_offsets_idx == -1)
2206 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2207 else if (loc->sgpr_idx != -1)
2208 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2209 }
2210 break;
2211 default:
2212 assert(!"invalid bind point");
2213 break;
2214 }
2215 }
2216
2217 void radv_CmdSetViewport(
2218 VkCommandBuffer commandBuffer,
2219 uint32_t firstViewport,
2220 uint32_t viewportCount,
2221 const VkViewport* pViewports)
2222 {
2223 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2224
2225 const uint32_t total_count = firstViewport + viewportCount;
2226 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2227 cmd_buffer->state.dynamic.viewport.count = total_count;
2228
2229 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2230 pViewports, viewportCount * sizeof(*pViewports));
2231
2232 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2233 }
2234
2235 void radv_CmdSetScissor(
2236 VkCommandBuffer commandBuffer,
2237 uint32_t firstScissor,
2238 uint32_t scissorCount,
2239 const VkRect2D* pScissors)
2240 {
2241 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2242
2243 const uint32_t total_count = firstScissor + scissorCount;
2244 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2245 cmd_buffer->state.dynamic.scissor.count = total_count;
2246
2247 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2248 pScissors, scissorCount * sizeof(*pScissors));
2249 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2250 }
2251
2252 void radv_CmdSetLineWidth(
2253 VkCommandBuffer commandBuffer,
2254 float lineWidth)
2255 {
2256 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2257 cmd_buffer->state.dynamic.line_width = lineWidth;
2258 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2259 }
2260
2261 void radv_CmdSetDepthBias(
2262 VkCommandBuffer commandBuffer,
2263 float depthBiasConstantFactor,
2264 float depthBiasClamp,
2265 float depthBiasSlopeFactor)
2266 {
2267 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2268
2269 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2270 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2271 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2272
2273 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2274 }
2275
2276 void radv_CmdSetBlendConstants(
2277 VkCommandBuffer commandBuffer,
2278 const float blendConstants[4])
2279 {
2280 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2281
2282 memcpy(cmd_buffer->state.dynamic.blend_constants,
2283 blendConstants, sizeof(float) * 4);
2284
2285 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2286 }
2287
2288 void radv_CmdSetDepthBounds(
2289 VkCommandBuffer commandBuffer,
2290 float minDepthBounds,
2291 float maxDepthBounds)
2292 {
2293 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2294
2295 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2296 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2297
2298 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2299 }
2300
2301 void radv_CmdSetStencilCompareMask(
2302 VkCommandBuffer commandBuffer,
2303 VkStencilFaceFlags faceMask,
2304 uint32_t compareMask)
2305 {
2306 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2307
2308 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2309 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2310 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2311 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2312
2313 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2314 }
2315
2316 void radv_CmdSetStencilWriteMask(
2317 VkCommandBuffer commandBuffer,
2318 VkStencilFaceFlags faceMask,
2319 uint32_t writeMask)
2320 {
2321 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2322
2323 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2324 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2325 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2326 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2327
2328 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2329 }
2330
2331 void radv_CmdSetStencilReference(
2332 VkCommandBuffer commandBuffer,
2333 VkStencilFaceFlags faceMask,
2334 uint32_t reference)
2335 {
2336 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2337
2338 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2339 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2340 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2341 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2342
2343 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2344 }
2345
2346 void radv_CmdExecuteCommands(
2347 VkCommandBuffer commandBuffer,
2348 uint32_t commandBufferCount,
2349 const VkCommandBuffer* pCmdBuffers)
2350 {
2351 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2352
2353 /* Emit pending flushes on primary prior to executing secondary */
2354 si_emit_cache_flush(primary);
2355
2356 for (uint32_t i = 0; i < commandBufferCount; i++) {
2357 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2358
2359 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2360 secondary->scratch_size_needed);
2361 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2362 secondary->compute_scratch_size_needed);
2363
2364 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2365 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2366 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2367 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2368 if (secondary->tess_rings_needed)
2369 primary->tess_rings_needed = true;
2370 if (secondary->sample_positions_needed)
2371 primary->sample_positions_needed = true;
2372
2373 if (secondary->ring_offsets_idx != -1) {
2374 if (primary->ring_offsets_idx == -1)
2375 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2376 else
2377 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2378 }
2379 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2380 }
2381
2382 /* if we execute secondary we need to re-emit out pipelines */
2383 if (commandBufferCount) {
2384 primary->state.emitted_pipeline = NULL;
2385 primary->state.emitted_compute_pipeline = NULL;
2386 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2387 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2388 primary->state.last_primitive_reset_en = -1;
2389 primary->state.last_primitive_reset_index = 0;
2390 radv_mark_descriptor_sets_dirty(primary);
2391 }
2392 }
2393
2394 VkResult radv_CreateCommandPool(
2395 VkDevice _device,
2396 const VkCommandPoolCreateInfo* pCreateInfo,
2397 const VkAllocationCallbacks* pAllocator,
2398 VkCommandPool* pCmdPool)
2399 {
2400 RADV_FROM_HANDLE(radv_device, device, _device);
2401 struct radv_cmd_pool *pool;
2402
2403 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2404 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2405 if (pool == NULL)
2406 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2407
2408 if (pAllocator)
2409 pool->alloc = *pAllocator;
2410 else
2411 pool->alloc = device->alloc;
2412
2413 list_inithead(&pool->cmd_buffers);
2414 list_inithead(&pool->free_cmd_buffers);
2415
2416 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2417
2418 *pCmdPool = radv_cmd_pool_to_handle(pool);
2419
2420 return VK_SUCCESS;
2421
2422 }
2423
2424 void radv_DestroyCommandPool(
2425 VkDevice _device,
2426 VkCommandPool commandPool,
2427 const VkAllocationCallbacks* pAllocator)
2428 {
2429 RADV_FROM_HANDLE(radv_device, device, _device);
2430 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2431
2432 if (!pool)
2433 return;
2434
2435 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2436 &pool->cmd_buffers, pool_link) {
2437 radv_cmd_buffer_destroy(cmd_buffer);
2438 }
2439
2440 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2441 &pool->free_cmd_buffers, pool_link) {
2442 radv_cmd_buffer_destroy(cmd_buffer);
2443 }
2444
2445 vk_free2(&device->alloc, pAllocator, pool);
2446 }
2447
2448 VkResult radv_ResetCommandPool(
2449 VkDevice device,
2450 VkCommandPool commandPool,
2451 VkCommandPoolResetFlags flags)
2452 {
2453 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2454
2455 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2456 &pool->cmd_buffers, pool_link) {
2457 radv_reset_cmd_buffer(cmd_buffer);
2458 }
2459
2460 return VK_SUCCESS;
2461 }
2462
2463 void radv_TrimCommandPoolKHR(
2464 VkDevice device,
2465 VkCommandPool commandPool,
2466 VkCommandPoolTrimFlagsKHR flags)
2467 {
2468 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2469
2470 if (!pool)
2471 return;
2472
2473 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2474 &pool->free_cmd_buffers, pool_link) {
2475 radv_cmd_buffer_destroy(cmd_buffer);
2476 }
2477 }
2478
2479 void radv_CmdBeginRenderPass(
2480 VkCommandBuffer commandBuffer,
2481 const VkRenderPassBeginInfo* pRenderPassBegin,
2482 VkSubpassContents contents)
2483 {
2484 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2485 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2486 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2487
2488 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2489 cmd_buffer->cs, 2048);
2490
2491 cmd_buffer->state.framebuffer = framebuffer;
2492 cmd_buffer->state.pass = pass;
2493 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2494 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2495
2496 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2497 assert(cmd_buffer->cs->cdw <= cdw_max);
2498
2499 radv_cmd_buffer_clear_subpass(cmd_buffer);
2500 }
2501
2502 void radv_CmdNextSubpass(
2503 VkCommandBuffer commandBuffer,
2504 VkSubpassContents contents)
2505 {
2506 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2507
2508 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2509
2510 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2511 2048);
2512
2513 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2514 radv_cmd_buffer_clear_subpass(cmd_buffer);
2515 }
2516
2517 void radv_CmdDraw(
2518 VkCommandBuffer commandBuffer,
2519 uint32_t vertexCount,
2520 uint32_t instanceCount,
2521 uint32_t firstVertex,
2522 uint32_t firstInstance)
2523 {
2524 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2525
2526 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2527
2528 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2529
2530 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2531 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2532 if (loc->sgpr_idx != -1) {
2533 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2534 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2535 int vs_num = 2;
2536 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2537 vs_num = 3;
2538
2539 assert (loc->num_sgprs == vs_num);
2540 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
2541 radeon_emit(cmd_buffer->cs, firstVertex);
2542 radeon_emit(cmd_buffer->cs, firstInstance);
2543 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2544 radeon_emit(cmd_buffer->cs, 0);
2545 }
2546 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2547 radeon_emit(cmd_buffer->cs, instanceCount);
2548
2549 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2550 radeon_emit(cmd_buffer->cs, vertexCount);
2551 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2552 S_0287F0_USE_OPAQUE(0));
2553
2554 assert(cmd_buffer->cs->cdw <= cdw_max);
2555
2556 radv_cmd_buffer_trace_emit(cmd_buffer);
2557 }
2558
2559 void radv_CmdDrawIndexed(
2560 VkCommandBuffer commandBuffer,
2561 uint32_t indexCount,
2562 uint32_t instanceCount,
2563 uint32_t firstIndex,
2564 int32_t vertexOffset,
2565 uint32_t firstInstance)
2566 {
2567 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2568 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2569 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2570 uint64_t index_va;
2571
2572 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2573
2574 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2575
2576 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2577 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2578
2579 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2580 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2581 if (loc->sgpr_idx != -1) {
2582 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2583 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2584 int vs_num = 2;
2585 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2586 vs_num = 3;
2587
2588 assert (loc->num_sgprs == vs_num);
2589 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
2590 radeon_emit(cmd_buffer->cs, vertexOffset);
2591 radeon_emit(cmd_buffer->cs, firstInstance);
2592 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2593 radeon_emit(cmd_buffer->cs, 0);
2594 }
2595 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2596 radeon_emit(cmd_buffer->cs, instanceCount);
2597
2598 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2599 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2600 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2601 radeon_emit(cmd_buffer->cs, index_max_size);
2602 radeon_emit(cmd_buffer->cs, index_va);
2603 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2604 radeon_emit(cmd_buffer->cs, indexCount);
2605 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2606
2607 assert(cmd_buffer->cs->cdw <= cdw_max);
2608 radv_cmd_buffer_trace_emit(cmd_buffer);
2609 }
2610
2611 static void
2612 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2613 VkBuffer _buffer,
2614 VkDeviceSize offset,
2615 VkBuffer _count_buffer,
2616 VkDeviceSize count_offset,
2617 uint32_t draw_count,
2618 uint32_t stride,
2619 bool indexed)
2620 {
2621 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2622 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2623 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2624 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2625 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2626 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2627 indirect_va += offset + buffer->offset;
2628 uint64_t count_va = 0;
2629
2630 if (count_buffer) {
2631 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2632 count_va += count_offset + count_buffer->offset;
2633 }
2634
2635 if (!draw_count)
2636 return;
2637
2638 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2639
2640 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2641 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2642 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2643 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2644 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2645 assert(loc->sgpr_idx != -1);
2646 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2647 radeon_emit(cs, 1);
2648 radeon_emit(cs, indirect_va);
2649 radeon_emit(cs, indirect_va >> 32);
2650
2651 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2652 PKT3_DRAW_INDIRECT_MULTI,
2653 8, false));
2654 radeon_emit(cs, 0);
2655 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2656 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2657 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2658 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2659 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2660 radeon_emit(cs, draw_count); /* count */
2661 radeon_emit(cs, count_va); /* count_addr */
2662 radeon_emit(cs, count_va >> 32);
2663 radeon_emit(cs, stride); /* stride */
2664 radeon_emit(cs, di_src_sel);
2665 radv_cmd_buffer_trace_emit(cmd_buffer);
2666 }
2667
2668 static void
2669 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2670 VkBuffer buffer,
2671 VkDeviceSize offset,
2672 VkBuffer countBuffer,
2673 VkDeviceSize countBufferOffset,
2674 uint32_t maxDrawCount,
2675 uint32_t stride)
2676 {
2677 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2678 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2679
2680 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2681 cmd_buffer->cs, 14);
2682
2683 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2684 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2685
2686 assert(cmd_buffer->cs->cdw <= cdw_max);
2687 }
2688
2689 static void
2690 radv_cmd_draw_indexed_indirect_count(
2691 VkCommandBuffer commandBuffer,
2692 VkBuffer buffer,
2693 VkDeviceSize offset,
2694 VkBuffer countBuffer,
2695 VkDeviceSize countBufferOffset,
2696 uint32_t maxDrawCount,
2697 uint32_t stride)
2698 {
2699 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2700 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2701 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2702 uint64_t index_va;
2703 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2704
2705 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2706 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2707
2708 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2709
2710 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2711 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2712
2713 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2714 radeon_emit(cmd_buffer->cs, index_va);
2715 radeon_emit(cmd_buffer->cs, index_va >> 32);
2716
2717 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2718 radeon_emit(cmd_buffer->cs, index_max_size);
2719
2720 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2721 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2722
2723 assert(cmd_buffer->cs->cdw <= cdw_max);
2724 }
2725
2726 void radv_CmdDrawIndirect(
2727 VkCommandBuffer commandBuffer,
2728 VkBuffer buffer,
2729 VkDeviceSize offset,
2730 uint32_t drawCount,
2731 uint32_t stride)
2732 {
2733 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2734 VK_NULL_HANDLE, 0, drawCount, stride);
2735 }
2736
2737 void radv_CmdDrawIndexedIndirect(
2738 VkCommandBuffer commandBuffer,
2739 VkBuffer buffer,
2740 VkDeviceSize offset,
2741 uint32_t drawCount,
2742 uint32_t stride)
2743 {
2744 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2745 VK_NULL_HANDLE, 0, drawCount, stride);
2746 }
2747
2748 void radv_CmdDrawIndirectCountAMD(
2749 VkCommandBuffer commandBuffer,
2750 VkBuffer buffer,
2751 VkDeviceSize offset,
2752 VkBuffer countBuffer,
2753 VkDeviceSize countBufferOffset,
2754 uint32_t maxDrawCount,
2755 uint32_t stride)
2756 {
2757 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2758 countBuffer, countBufferOffset,
2759 maxDrawCount, stride);
2760 }
2761
2762 void radv_CmdDrawIndexedIndirectCountAMD(
2763 VkCommandBuffer commandBuffer,
2764 VkBuffer buffer,
2765 VkDeviceSize offset,
2766 VkBuffer countBuffer,
2767 VkDeviceSize countBufferOffset,
2768 uint32_t maxDrawCount,
2769 uint32_t stride)
2770 {
2771 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2772 countBuffer, countBufferOffset,
2773 maxDrawCount, stride);
2774 }
2775
2776 static void
2777 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2778 {
2779 radv_emit_compute_pipeline(cmd_buffer);
2780 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
2781 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2782 VK_SHADER_STAGE_COMPUTE_BIT);
2783 si_emit_cache_flush(cmd_buffer);
2784 }
2785
2786 void radv_CmdDispatch(
2787 VkCommandBuffer commandBuffer,
2788 uint32_t x,
2789 uint32_t y,
2790 uint32_t z)
2791 {
2792 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2793
2794 radv_flush_compute_state(cmd_buffer);
2795
2796 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2797
2798 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2799 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2800 if (loc->sgpr_idx != -1) {
2801 assert(!loc->indirect);
2802 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2803 assert(loc->num_sgprs == grid_used);
2804 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2805 radeon_emit(cmd_buffer->cs, x);
2806 if (grid_used > 1)
2807 radeon_emit(cmd_buffer->cs, y);
2808 if (grid_used > 2)
2809 radeon_emit(cmd_buffer->cs, z);
2810 }
2811
2812 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2813 PKT3_SHADER_TYPE_S(1));
2814 radeon_emit(cmd_buffer->cs, x);
2815 radeon_emit(cmd_buffer->cs, y);
2816 radeon_emit(cmd_buffer->cs, z);
2817 radeon_emit(cmd_buffer->cs, 1);
2818
2819 assert(cmd_buffer->cs->cdw <= cdw_max);
2820 radv_cmd_buffer_trace_emit(cmd_buffer);
2821 }
2822
2823 void radv_CmdDispatchIndirect(
2824 VkCommandBuffer commandBuffer,
2825 VkBuffer _buffer,
2826 VkDeviceSize offset)
2827 {
2828 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2829 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2830 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2831 va += buffer->offset + offset;
2832
2833 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2834
2835 radv_flush_compute_state(cmd_buffer);
2836
2837 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2838 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2839 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2840 if (loc->sgpr_idx != -1) {
2841 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2842 for (unsigned i = 0; i < grid_used; ++i) {
2843 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2844 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2845 COPY_DATA_DST_SEL(COPY_DATA_REG));
2846 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2847 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2848 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2849 radeon_emit(cmd_buffer->cs, 0);
2850 }
2851 }
2852
2853 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2854 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2855 PKT3_SHADER_TYPE_S(1));
2856 radeon_emit(cmd_buffer->cs, va);
2857 radeon_emit(cmd_buffer->cs, va >> 32);
2858 radeon_emit(cmd_buffer->cs, 1);
2859 } else {
2860 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2861 PKT3_SHADER_TYPE_S(1));
2862 radeon_emit(cmd_buffer->cs, 1);
2863 radeon_emit(cmd_buffer->cs, va);
2864 radeon_emit(cmd_buffer->cs, va >> 32);
2865
2866 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2867 PKT3_SHADER_TYPE_S(1));
2868 radeon_emit(cmd_buffer->cs, 0);
2869 radeon_emit(cmd_buffer->cs, 1);
2870 }
2871
2872 assert(cmd_buffer->cs->cdw <= cdw_max);
2873 radv_cmd_buffer_trace_emit(cmd_buffer);
2874 }
2875
2876 void radv_unaligned_dispatch(
2877 struct radv_cmd_buffer *cmd_buffer,
2878 uint32_t x,
2879 uint32_t y,
2880 uint32_t z)
2881 {
2882 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2883 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2884 uint32_t blocks[3], remainder[3];
2885
2886 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2887 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2888 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2889
2890 /* If aligned, these should be an entire block size, not 0 */
2891 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2892 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2893 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2894
2895 radv_flush_compute_state(cmd_buffer);
2896
2897 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2898
2899 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2900 radeon_emit(cmd_buffer->cs,
2901 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2902 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2903 radeon_emit(cmd_buffer->cs,
2904 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2905 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2906 radeon_emit(cmd_buffer->cs,
2907 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2908 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2909
2910 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2911 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2912 if (loc->sgpr_idx != -1) {
2913 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2914 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2915 radeon_emit(cmd_buffer->cs, blocks[0]);
2916 if (grid_used > 1)
2917 radeon_emit(cmd_buffer->cs, blocks[1]);
2918 if (grid_used > 2)
2919 radeon_emit(cmd_buffer->cs, blocks[2]);
2920 }
2921 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2922 PKT3_SHADER_TYPE_S(1));
2923 radeon_emit(cmd_buffer->cs, blocks[0]);
2924 radeon_emit(cmd_buffer->cs, blocks[1]);
2925 radeon_emit(cmd_buffer->cs, blocks[2]);
2926 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2927 S_00B800_PARTIAL_TG_EN(1));
2928
2929 assert(cmd_buffer->cs->cdw <= cdw_max);
2930 radv_cmd_buffer_trace_emit(cmd_buffer);
2931 }
2932
2933 void radv_CmdEndRenderPass(
2934 VkCommandBuffer commandBuffer)
2935 {
2936 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2937
2938 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2939
2940 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2941
2942 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2943 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2944 radv_handle_subpass_image_transition(cmd_buffer,
2945 (VkAttachmentReference){i, layout});
2946 }
2947
2948 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2949
2950 cmd_buffer->state.pass = NULL;
2951 cmd_buffer->state.subpass = NULL;
2952 cmd_buffer->state.attachments = NULL;
2953 cmd_buffer->state.framebuffer = NULL;
2954 }
2955
2956 /*
2957 * For HTILE we have the following interesting clear words:
2958 * 0x0000030f: Uncompressed.
2959 * 0xfffffff0: Clear depth to 1.0
2960 * 0x00000000: Clear depth to 0.0
2961 */
2962 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2963 struct radv_image *image,
2964 const VkImageSubresourceRange *range,
2965 uint32_t clear_word)
2966 {
2967 assert(range->baseMipLevel == 0);
2968 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
2969 unsigned layer_count = radv_get_layerCount(image, range);
2970 uint64_t size = image->surface.htile_slice_size * layer_count;
2971 uint64_t offset = image->offset + image->htile_offset +
2972 image->surface.htile_slice_size * range->baseArrayLayer;
2973
2974 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2975 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2976
2977 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
2978
2979 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2980 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2981 RADV_CMD_FLAG_INV_VMEM_L1 |
2982 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2983 }
2984
2985 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2986 struct radv_image *image,
2987 VkImageLayout src_layout,
2988 VkImageLayout dst_layout,
2989 unsigned src_queue_mask,
2990 unsigned dst_queue_mask,
2991 const VkImageSubresourceRange *range,
2992 VkImageAspectFlags pending_clears)
2993 {
2994 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2995 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2996 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2997 cmd_buffer->state.render_area.extent.width == image->info.width &&
2998 cmd_buffer->state.render_area.extent.height == image->info.height) {
2999 /* The clear will initialize htile. */
3000 return;
3001 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3002 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3003 /* TODO: merge with the clear if applicable */
3004 radv_initialize_htile(cmd_buffer, image, range, 0);
3005 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3006 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3007 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3008 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3009 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3010 VkImageSubresourceRange local_range = *range;
3011 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3012 local_range.baseMipLevel = 0;
3013 local_range.levelCount = 1;
3014
3015 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3016 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3017
3018 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3019
3020 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3021 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3022 }
3023 }
3024
3025 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3026 struct radv_image *image, uint32_t value)
3027 {
3028 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3029 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3030
3031 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3032 image->cmask.size, value);
3033
3034 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3035 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3036 RADV_CMD_FLAG_INV_VMEM_L1 |
3037 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3038 }
3039
3040 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3041 struct radv_image *image,
3042 VkImageLayout src_layout,
3043 VkImageLayout dst_layout,
3044 unsigned src_queue_mask,
3045 unsigned dst_queue_mask,
3046 const VkImageSubresourceRange *range,
3047 VkImageAspectFlags pending_clears)
3048 {
3049 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3050 if (image->fmask.size)
3051 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3052 else
3053 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3054 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3055 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3056 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3057 }
3058 }
3059
3060 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3061 struct radv_image *image, uint32_t value)
3062 {
3063
3064 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3065 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3066
3067 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3068 image->surface.dcc_size, value);
3069
3070 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3071 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3072 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3073 RADV_CMD_FLAG_INV_VMEM_L1 |
3074 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3075 }
3076
3077 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3078 struct radv_image *image,
3079 VkImageLayout src_layout,
3080 VkImageLayout dst_layout,
3081 unsigned src_queue_mask,
3082 unsigned dst_queue_mask,
3083 const VkImageSubresourceRange *range,
3084 VkImageAspectFlags pending_clears)
3085 {
3086 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3087 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3088 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3089 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3090 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3091 }
3092 }
3093
3094 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3095 struct radv_image *image,
3096 VkImageLayout src_layout,
3097 VkImageLayout dst_layout,
3098 uint32_t src_family,
3099 uint32_t dst_family,
3100 const VkImageSubresourceRange *range,
3101 VkImageAspectFlags pending_clears)
3102 {
3103 if (image->exclusive && src_family != dst_family) {
3104 /* This is an acquire or a release operation and there will be
3105 * a corresponding release/acquire. Do the transition in the
3106 * most flexible queue. */
3107
3108 assert(src_family == cmd_buffer->queue_family_index ||
3109 dst_family == cmd_buffer->queue_family_index);
3110
3111 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3112 return;
3113
3114 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3115 (src_family == RADV_QUEUE_GENERAL ||
3116 dst_family == RADV_QUEUE_GENERAL))
3117 return;
3118 }
3119
3120 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3121 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3122
3123 if (image->surface.htile_size)
3124 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3125 dst_layout, src_queue_mask,
3126 dst_queue_mask, range,
3127 pending_clears);
3128
3129 if (image->cmask.size)
3130 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3131 dst_layout, src_queue_mask,
3132 dst_queue_mask, range,
3133 pending_clears);
3134
3135 if (image->surface.dcc_size)
3136 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3137 dst_layout, src_queue_mask,
3138 dst_queue_mask, range,
3139 pending_clears);
3140 }
3141
3142 void radv_CmdPipelineBarrier(
3143 VkCommandBuffer commandBuffer,
3144 VkPipelineStageFlags srcStageMask,
3145 VkPipelineStageFlags destStageMask,
3146 VkBool32 byRegion,
3147 uint32_t memoryBarrierCount,
3148 const VkMemoryBarrier* pMemoryBarriers,
3149 uint32_t bufferMemoryBarrierCount,
3150 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3151 uint32_t imageMemoryBarrierCount,
3152 const VkImageMemoryBarrier* pImageMemoryBarriers)
3153 {
3154 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3155 enum radv_cmd_flush_bits src_flush_bits = 0;
3156 enum radv_cmd_flush_bits dst_flush_bits = 0;
3157
3158 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3159 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3160 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3161 NULL);
3162 }
3163
3164 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3165 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3166 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3167 NULL);
3168 }
3169
3170 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3171 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3172 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3173 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3174 image);
3175 }
3176
3177 radv_stage_flush(cmd_buffer, srcStageMask);
3178 cmd_buffer->state.flush_bits |= src_flush_bits;
3179
3180 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3181 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3182 radv_handle_image_transition(cmd_buffer, image,
3183 pImageMemoryBarriers[i].oldLayout,
3184 pImageMemoryBarriers[i].newLayout,
3185 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3186 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3187 &pImageMemoryBarriers[i].subresourceRange,
3188 0);
3189 }
3190
3191 cmd_buffer->state.flush_bits |= dst_flush_bits;
3192 }
3193
3194
3195 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3196 struct radv_event *event,
3197 VkPipelineStageFlags stageMask,
3198 unsigned value)
3199 {
3200 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3201 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3202
3203 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3204
3205 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3206
3207 /* TODO: this is overkill. Probably should figure something out from
3208 * the stage mask. */
3209
3210 si_cs_emit_write_event_eop(cs,
3211 cmd_buffer->device->physical_device->rad_info.chip_class == CIK,
3212 false,
3213 EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
3214 1, va, 2, value);
3215
3216 assert(cmd_buffer->cs->cdw <= cdw_max);
3217 }
3218
3219 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3220 VkEvent _event,
3221 VkPipelineStageFlags stageMask)
3222 {
3223 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3224 RADV_FROM_HANDLE(radv_event, event, _event);
3225
3226 write_event(cmd_buffer, event, stageMask, 1);
3227 }
3228
3229 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3230 VkEvent _event,
3231 VkPipelineStageFlags stageMask)
3232 {
3233 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3234 RADV_FROM_HANDLE(radv_event, event, _event);
3235
3236 write_event(cmd_buffer, event, stageMask, 0);
3237 }
3238
3239 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3240 uint32_t eventCount,
3241 const VkEvent* pEvents,
3242 VkPipelineStageFlags srcStageMask,
3243 VkPipelineStageFlags dstStageMask,
3244 uint32_t memoryBarrierCount,
3245 const VkMemoryBarrier* pMemoryBarriers,
3246 uint32_t bufferMemoryBarrierCount,
3247 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3248 uint32_t imageMemoryBarrierCount,
3249 const VkImageMemoryBarrier* pImageMemoryBarriers)
3250 {
3251 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3252 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3253
3254 for (unsigned i = 0; i < eventCount; ++i) {
3255 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3256 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3257
3258 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3259
3260 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3261
3262 si_emit_wait_fence(cs, va, 1, 0xffffffff);
3263 assert(cmd_buffer->cs->cdw <= cdw_max);
3264 }
3265
3266
3267 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3268 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3269
3270 radv_handle_image_transition(cmd_buffer, image,
3271 pImageMemoryBarriers[i].oldLayout,
3272 pImageMemoryBarriers[i].newLayout,
3273 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3274 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3275 &pImageMemoryBarriers[i].subresourceRange,
3276 0);
3277 }
3278
3279 /* TODO: figure out how to do memory barriers without waiting */
3280 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3281 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3282 RADV_CMD_FLAG_INV_VMEM_L1 |
3283 RADV_CMD_FLAG_INV_SMEM_L1;
3284 }