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radv: Specify semantics of HTILE layout helpers.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 uint32_t src_family,
42 uint32_t dst_family,
43 const VkImageSubresourceRange *range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static void
191 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
192 {
193 list_del(&cmd_buffer->pool_link);
194
195 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
196 &cmd_buffer->upload.list, list) {
197 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
198 list_del(&up->list);
199 free(up);
200 }
201
202 if (cmd_buffer->upload.upload_bo)
203 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
204 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
205 free(cmd_buffer->push_descriptors.set.mapped_ptr);
206 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
207 }
208
209 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
210 {
211
212 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
213
214 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
215 &cmd_buffer->upload.list, list) {
216 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
217 list_del(&up->list);
218 free(up);
219 }
220
221 cmd_buffer->scratch_size_needed = 0;
222 cmd_buffer->compute_scratch_size_needed = 0;
223 cmd_buffer->esgs_ring_size_needed = 0;
224 cmd_buffer->gsvs_ring_size_needed = 0;
225 cmd_buffer->tess_rings_needed = false;
226 cmd_buffer->sample_positions_needed = false;
227
228 if (cmd_buffer->upload.upload_bo)
229 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
230 cmd_buffer->upload.upload_bo, 8);
231 cmd_buffer->upload.offset = 0;
232
233 cmd_buffer->record_fail = false;
234
235 cmd_buffer->ring_offsets_idx = -1;
236 }
237
238 static bool
239 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
240 uint64_t min_needed)
241 {
242 uint64_t new_size;
243 struct radeon_winsys_bo *bo;
244 struct radv_cmd_buffer_upload *upload;
245 struct radv_device *device = cmd_buffer->device;
246
247 new_size = MAX2(min_needed, 16 * 1024);
248 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
249
250 bo = device->ws->buffer_create(device->ws,
251 new_size, 4096,
252 RADEON_DOMAIN_GTT,
253 RADEON_FLAG_CPU_ACCESS);
254
255 if (!bo) {
256 cmd_buffer->record_fail = true;
257 return false;
258 }
259
260 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
261 if (cmd_buffer->upload.upload_bo) {
262 upload = malloc(sizeof(*upload));
263
264 if (!upload) {
265 cmd_buffer->record_fail = true;
266 device->ws->buffer_destroy(bo);
267 return false;
268 }
269
270 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
271 list_add(&upload->list, &cmd_buffer->upload.list);
272 }
273
274 cmd_buffer->upload.upload_bo = bo;
275 cmd_buffer->upload.size = new_size;
276 cmd_buffer->upload.offset = 0;
277 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
278
279 if (!cmd_buffer->upload.map) {
280 cmd_buffer->record_fail = true;
281 return false;
282 }
283
284 return true;
285 }
286
287 bool
288 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
289 unsigned size,
290 unsigned alignment,
291 unsigned *out_offset,
292 void **ptr)
293 {
294 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
295 if (offset + size > cmd_buffer->upload.size) {
296 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
297 return false;
298 offset = 0;
299 }
300
301 *out_offset = offset;
302 *ptr = cmd_buffer->upload.map + offset;
303
304 cmd_buffer->upload.offset = offset + size;
305 return true;
306 }
307
308 bool
309 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
310 unsigned size, unsigned alignment,
311 const void *data, unsigned *out_offset)
312 {
313 uint8_t *ptr;
314
315 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
316 out_offset, (void **)&ptr))
317 return false;
318
319 if (ptr)
320 memcpy(ptr, data, size);
321
322 return true;
323 }
324
325 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
326 {
327 struct radv_device *device = cmd_buffer->device;
328 struct radeon_winsys_cs *cs = cmd_buffer->cs;
329 uint64_t va;
330
331 if (!device->trace_bo)
332 return;
333
334 va = device->ws->buffer_get_va(device->trace_bo);
335
336 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
337
338 ++cmd_buffer->state.trace_id;
339 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
340 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
341 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
342 S_370_WR_CONFIRM(1) |
343 S_370_ENGINE_SEL(V_370_ME));
344 radeon_emit(cs, va);
345 radeon_emit(cs, va >> 32);
346 radeon_emit(cs, cmd_buffer->state.trace_id);
347 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
348 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
349 }
350
351 static void
352 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
353 struct radv_pipeline *pipeline)
354 {
355 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
356 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
357 8);
358 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
359 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
360 }
361
362 static void
363 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
364 struct radv_pipeline *pipeline)
365 {
366 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
367 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
369
370 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
371 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
372 }
373
374 /* 12.4 fixed-point */
375 static unsigned radv_pack_float_12p4(float x)
376 {
377 return x <= 0 ? 0 :
378 x >= 4096 ? 0xffff : x * 16;
379 }
380
381 static uint32_t
382 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
383 {
384 switch (stage) {
385 case MESA_SHADER_FRAGMENT:
386 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
387 case MESA_SHADER_VERTEX:
388 if (has_tess)
389 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
390 else
391 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
392 case MESA_SHADER_GEOMETRY:
393 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
394 case MESA_SHADER_COMPUTE:
395 return R_00B900_COMPUTE_USER_DATA_0;
396 case MESA_SHADER_TESS_CTRL:
397 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
398 case MESA_SHADER_TESS_EVAL:
399 if (has_gs)
400 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
401 else
402 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
403 default:
404 unreachable("unknown shader");
405 }
406 }
407
408 static struct ac_userdata_info *
409 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
410 gl_shader_stage stage,
411 int idx)
412 {
413 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
414 }
415
416 static void
417 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
418 struct radv_pipeline *pipeline,
419 gl_shader_stage stage,
420 int idx, uint64_t va)
421 {
422 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
423 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
424 if (loc->sgpr_idx == -1)
425 return;
426 assert(loc->num_sgprs == 2);
427 assert(!loc->indirect);
428 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
429 radeon_emit(cmd_buffer->cs, va);
430 radeon_emit(cmd_buffer->cs, va >> 32);
431 }
432
433 static void
434 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
435 struct radv_pipeline *pipeline)
436 {
437 int num_samples = pipeline->graphics.ms.num_samples;
438 struct radv_multisample_state *ms = &pipeline->graphics.ms;
439 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
440
441 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
442 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
443 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
444
445 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
446 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
447
448 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
449 return;
450
451 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
452 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
453 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
454
455 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
456
457 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
458 uint32_t offset;
459 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
460 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
461 if (loc->sgpr_idx == -1)
462 return;
463 assert(loc->num_sgprs == 1);
464 assert(!loc->indirect);
465 switch (num_samples) {
466 default:
467 offset = 0;
468 break;
469 case 2:
470 offset = 1;
471 break;
472 case 4:
473 offset = 3;
474 break;
475 case 8:
476 offset = 7;
477 break;
478 case 16:
479 offset = 15;
480 break;
481 }
482
483 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
484 cmd_buffer->sample_positions_needed = true;
485 }
486 }
487
488 static void
489 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
490 struct radv_pipeline *pipeline)
491 {
492 struct radv_raster_state *raster = &pipeline->graphics.raster;
493
494 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
495 raster->pa_cl_clip_cntl);
496
497 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
498 raster->spi_interp_control);
499
500 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
501 unsigned tmp = (unsigned)(1.0 * 8.0);
502 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
503 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
504 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
505
506 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
507 raster->pa_su_vtx_cntl);
508
509 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
510 raster->pa_su_sc_mode_cntl);
511 }
512
513 static void
514 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
515 struct radv_pipeline *pipeline,
516 struct radv_shader_variant *shader,
517 struct ac_vs_output_info *outinfo)
518 {
519 struct radeon_winsys *ws = cmd_buffer->device->ws;
520 uint64_t va = ws->buffer_get_va(shader->bo);
521 unsigned export_count;
522
523 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
524 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
525
526 export_count = MAX2(1, outinfo->param_exports);
527 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
528 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
529
530 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
531 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
532 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
533 V_02870C_SPI_SHADER_4COMP :
534 V_02870C_SPI_SHADER_NONE) |
535 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
536 V_02870C_SPI_SHADER_4COMP :
537 V_02870C_SPI_SHADER_NONE) |
538 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
539 V_02870C_SPI_SHADER_4COMP :
540 V_02870C_SPI_SHADER_NONE));
541
542
543 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
544 radeon_emit(cmd_buffer->cs, va >> 8);
545 radeon_emit(cmd_buffer->cs, va >> 40);
546 radeon_emit(cmd_buffer->cs, shader->rsrc1);
547 radeon_emit(cmd_buffer->cs, shader->rsrc2);
548
549 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
550 S_028818_VTX_W0_FMT(1) |
551 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
552 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
553 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
554
555
556 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
557 pipeline->graphics.pa_cl_vs_out_cntl);
558
559 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
560 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
561 }
562
563 static void
564 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
565 struct radv_shader_variant *shader,
566 struct ac_es_output_info *outinfo)
567 {
568 struct radeon_winsys *ws = cmd_buffer->device->ws;
569 uint64_t va = ws->buffer_get_va(shader->bo);
570
571 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
572 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
573
574 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
575 outinfo->esgs_itemsize / 4);
576 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
577 radeon_emit(cmd_buffer->cs, va >> 8);
578 radeon_emit(cmd_buffer->cs, va >> 40);
579 radeon_emit(cmd_buffer->cs, shader->rsrc1);
580 radeon_emit(cmd_buffer->cs, shader->rsrc2);
581 }
582
583 static void
584 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
585 struct radv_shader_variant *shader)
586 {
587 struct radeon_winsys *ws = cmd_buffer->device->ws;
588 uint64_t va = ws->buffer_get_va(shader->bo);
589 uint32_t rsrc2 = shader->rsrc2;
590
591 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
592 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
593
594 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
595 radeon_emit(cmd_buffer->cs, va >> 8);
596 radeon_emit(cmd_buffer->cs, va >> 40);
597
598 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
599 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
600 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
601 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
602
603 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
604 radeon_emit(cmd_buffer->cs, shader->rsrc1);
605 radeon_emit(cmd_buffer->cs, rsrc2);
606 }
607
608 static void
609 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
610 struct radv_shader_variant *shader)
611 {
612 struct radeon_winsys *ws = cmd_buffer->device->ws;
613 uint64_t va = ws->buffer_get_va(shader->bo);
614
615 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
616 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
617
618 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
619 radeon_emit(cmd_buffer->cs, va >> 8);
620 radeon_emit(cmd_buffer->cs, va >> 40);
621 radeon_emit(cmd_buffer->cs, shader->rsrc1);
622 radeon_emit(cmd_buffer->cs, shader->rsrc2);
623 }
624
625 static void
626 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
627 struct radv_pipeline *pipeline)
628 {
629 struct radv_shader_variant *vs;
630
631 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
632
633 vs = pipeline->shaders[MESA_SHADER_VERTEX];
634
635 if (vs->info.vs.as_ls)
636 radv_emit_hw_ls(cmd_buffer, vs);
637 else if (vs->info.vs.as_es)
638 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
639 else
640 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
641
642 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
643 }
644
645
646 static void
647 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
648 struct radv_pipeline *pipeline)
649 {
650 if (!radv_pipeline_has_tess(pipeline))
651 return;
652
653 struct radv_shader_variant *tes, *tcs;
654
655 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
656 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
657
658 if (tes->info.tes.as_es)
659 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
660 else
661 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
662
663 radv_emit_hw_hs(cmd_buffer, tcs);
664
665 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
666 pipeline->graphics.tess.tf_param);
667
668 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
669 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
670 pipeline->graphics.tess.ls_hs_config);
671 else
672 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
673 pipeline->graphics.tess.ls_hs_config);
674
675 struct ac_userdata_info *loc;
676
677 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
678 if (loc->sgpr_idx != -1) {
679 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
680 assert(loc->num_sgprs == 4);
681 assert(!loc->indirect);
682 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
683 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
684 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
685 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
686 pipeline->graphics.tess.num_tcs_input_cp << 26);
687 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
688 }
689
690 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
691 if (loc->sgpr_idx != -1) {
692 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
693 assert(loc->num_sgprs == 1);
694 assert(!loc->indirect);
695
696 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
697 pipeline->graphics.tess.offchip_layout);
698 }
699
700 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
701 if (loc->sgpr_idx != -1) {
702 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
703 assert(loc->num_sgprs == 1);
704 assert(!loc->indirect);
705
706 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
707 pipeline->graphics.tess.tcs_in_layout);
708 }
709 }
710
711 static void
712 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
713 struct radv_pipeline *pipeline)
714 {
715 struct radeon_winsys *ws = cmd_buffer->device->ws;
716 struct radv_shader_variant *gs;
717 uint64_t va;
718
719 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
720
721 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
722 if (!gs)
723 return;
724
725 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
726
727 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
728 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
729 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
730 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
731
732 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
733
734 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
735
736 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
737 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
738 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
739 radeon_emit(cmd_buffer->cs, 0);
740 radeon_emit(cmd_buffer->cs, 0);
741 radeon_emit(cmd_buffer->cs, 0);
742
743 uint32_t gs_num_invocations = gs->info.gs.invocations;
744 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
745 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
746 S_028B90_ENABLE(gs_num_invocations > 0));
747
748 va = ws->buffer_get_va(gs->bo);
749 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
750 si_cp_dma_prefetch(cmd_buffer, va, gs->code_size);
751 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
752 radeon_emit(cmd_buffer->cs, va >> 8);
753 radeon_emit(cmd_buffer->cs, va >> 40);
754 radeon_emit(cmd_buffer->cs, gs->rsrc1);
755 radeon_emit(cmd_buffer->cs, gs->rsrc2);
756
757 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
758
759 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
760 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
761 if (loc->sgpr_idx != -1) {
762 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
763 uint32_t num_entries = 64;
764 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
765
766 if (is_vi)
767 num_entries *= stride;
768
769 stride = S_008F04_STRIDE(stride);
770 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
771 radeon_emit(cmd_buffer->cs, stride);
772 radeon_emit(cmd_buffer->cs, num_entries);
773 }
774 }
775
776 static void
777 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
778 struct radv_pipeline *pipeline)
779 {
780 struct radeon_winsys *ws = cmd_buffer->device->ws;
781 struct radv_shader_variant *ps;
782 uint64_t va;
783 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
784 struct radv_blend_state *blend = &pipeline->graphics.blend;
785 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
786
787 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
788
789 va = ws->buffer_get_va(ps->bo);
790 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
791 si_cp_dma_prefetch(cmd_buffer, va, ps->code_size);
792
793 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
794 radeon_emit(cmd_buffer->cs, va >> 8);
795 radeon_emit(cmd_buffer->cs, va >> 40);
796 radeon_emit(cmd_buffer->cs, ps->rsrc1);
797 radeon_emit(cmd_buffer->cs, ps->rsrc2);
798
799 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
800 pipeline->graphics.db_shader_control);
801
802 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
803 ps->config.spi_ps_input_ena);
804
805 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
806 ps->config.spi_ps_input_addr);
807
808 if (ps->info.fs.force_persample)
809 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
810
811 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
812 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
813
814 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
815
816 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
817 pipeline->graphics.shader_z_format);
818
819 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
820
821 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
822 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
823
824 if (pipeline->graphics.ps_input_cntl_num) {
825 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
826 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
827 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
828 }
829 }
830 }
831
832 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
833 struct radv_pipeline *pipeline)
834 {
835 uint32_t vtx_reuse_depth = 30;
836 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
837 return;
838
839 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
840 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
841 vtx_reuse_depth = 14;
842 }
843 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
844 vtx_reuse_depth);
845 }
846
847 static void
848 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
849 struct radv_pipeline *pipeline)
850 {
851 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
852 return;
853
854 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
855 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
856 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
857 radv_update_multisample_state(cmd_buffer, pipeline);
858 radv_emit_vertex_shader(cmd_buffer, pipeline);
859 radv_emit_tess_shaders(cmd_buffer, pipeline);
860 radv_emit_geometry_shader(cmd_buffer, pipeline);
861 radv_emit_fragment_shader(cmd_buffer, pipeline);
862 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
863
864 cmd_buffer->scratch_size_needed =
865 MAX2(cmd_buffer->scratch_size_needed,
866 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
867
868 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
869 S_0286E8_WAVES(pipeline->max_waves) |
870 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
871
872 if (!cmd_buffer->state.emitted_pipeline ||
873 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
874 pipeline->graphics.can_use_guardband)
875 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
876 cmd_buffer->state.emitted_pipeline = pipeline;
877 }
878
879 static void
880 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
881 {
882 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
883 cmd_buffer->state.dynamic.viewport.viewports);
884 }
885
886 static void
887 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
888 {
889 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
890 si_write_scissors(cmd_buffer->cs, 0, count,
891 cmd_buffer->state.dynamic.scissor.scissors,
892 cmd_buffer->state.dynamic.viewport.viewports,
893 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
894 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
895 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
896 }
897
898 static void
899 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
900 int index,
901 struct radv_color_buffer_info *cb)
902 {
903 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
904 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
905 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
906 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
907 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
908 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
909 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
910 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
911 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
912 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
913 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
914 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
915 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
916
917 if (is_vi) { /* DCC BASE */
918 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
919 }
920 }
921
922 static void
923 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
924 struct radv_ds_buffer_info *ds,
925 struct radv_image *image,
926 VkImageLayout layout)
927 {
928 uint32_t db_z_info = ds->db_z_info;
929 uint32_t db_stencil_info = ds->db_stencil_info;
930
931 if (!radv_layout_has_htile(image, layout)) {
932 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
933 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
934 }
935
936 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
937 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
938
939 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
940 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
941 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
942 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
943 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
944 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
945 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
946 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
947 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
948 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
949
950 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
951 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
952 ds->pa_su_poly_offset_db_fmt_cntl);
953 }
954
955 void
956 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
957 struct radv_image *image,
958 VkClearDepthStencilValue ds_clear_value,
959 VkImageAspectFlags aspects)
960 {
961 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
962 va += image->offset + image->clear_value_offset;
963 unsigned reg_offset = 0, reg_count = 0;
964
965 if (!image->surface.htile_size || !aspects)
966 return;
967
968 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
969 ++reg_count;
970 } else {
971 ++reg_offset;
972 va += 4;
973 }
974 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
975 ++reg_count;
976
977 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
978
979 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
980 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
981 S_370_WR_CONFIRM(1) |
982 S_370_ENGINE_SEL(V_370_PFP));
983 radeon_emit(cmd_buffer->cs, va);
984 radeon_emit(cmd_buffer->cs, va >> 32);
985 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
986 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
987 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
988 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
989
990 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
991 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
992 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
993 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
994 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
995 }
996
997 static void
998 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
999 struct radv_image *image)
1000 {
1001 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1002 va += image->offset + image->clear_value_offset;
1003
1004 if (!image->surface.htile_size)
1005 return;
1006
1007 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1008
1009 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1010 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1011 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1012 COPY_DATA_COUNT_SEL);
1013 radeon_emit(cmd_buffer->cs, va);
1014 radeon_emit(cmd_buffer->cs, va >> 32);
1015 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1016 radeon_emit(cmd_buffer->cs, 0);
1017
1018 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1019 radeon_emit(cmd_buffer->cs, 0);
1020 }
1021
1022 void
1023 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1024 struct radv_image *image,
1025 int idx,
1026 uint32_t color_values[2])
1027 {
1028 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1029 va += image->offset + image->clear_value_offset;
1030
1031 if (!image->cmask.size && !image->surface.dcc_size)
1032 return;
1033
1034 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1035
1036 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1037 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1038 S_370_WR_CONFIRM(1) |
1039 S_370_ENGINE_SEL(V_370_PFP));
1040 radeon_emit(cmd_buffer->cs, va);
1041 radeon_emit(cmd_buffer->cs, va >> 32);
1042 radeon_emit(cmd_buffer->cs, color_values[0]);
1043 radeon_emit(cmd_buffer->cs, color_values[1]);
1044
1045 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1046 radeon_emit(cmd_buffer->cs, color_values[0]);
1047 radeon_emit(cmd_buffer->cs, color_values[1]);
1048 }
1049
1050 static void
1051 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1052 struct radv_image *image,
1053 int idx)
1054 {
1055 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1056 va += image->offset + image->clear_value_offset;
1057
1058 if (!image->cmask.size && !image->surface.dcc_size)
1059 return;
1060
1061 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1062 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1063
1064 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1065 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1066 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1067 COPY_DATA_COUNT_SEL);
1068 radeon_emit(cmd_buffer->cs, va);
1069 radeon_emit(cmd_buffer->cs, va >> 32);
1070 radeon_emit(cmd_buffer->cs, reg >> 2);
1071 radeon_emit(cmd_buffer->cs, 0);
1072
1073 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1074 radeon_emit(cmd_buffer->cs, 0);
1075 }
1076
1077 void
1078 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1079 {
1080 int i;
1081 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1082 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1083
1084 for (i = 0; i < subpass->color_count; ++i) {
1085 int idx = subpass->color_attachments[i].attachment;
1086 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1087
1088 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1089
1090 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1091 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1092
1093 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1094 }
1095
1096 for (i = subpass->color_count; i < 8; i++)
1097 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1098 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1099
1100 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1101 int idx = subpass->depth_stencil_attachment.attachment;
1102 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1103 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1104 struct radv_image *image = att->attachment->image;
1105 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1106
1107 /* We currently don't support writing decompressed HTILE */
1108 assert(radv_layout_has_htile(image, layout) ==
1109 radv_layout_is_htile_compressed(image, layout));
1110
1111 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1112
1113 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1114 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1115 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1116 }
1117 radv_load_depth_clear_regs(cmd_buffer, image);
1118 } else {
1119 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1120 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1121 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1122 }
1123 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1124 S_028208_BR_X(framebuffer->width) |
1125 S_028208_BR_Y(framebuffer->height));
1126 }
1127
1128 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1129 {
1130 uint32_t db_count_control;
1131
1132 if(!cmd_buffer->state.active_occlusion_queries) {
1133 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1134 db_count_control = 0;
1135 } else {
1136 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1137 }
1138 } else {
1139 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1140 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1141 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1142 S_028004_ZPASS_ENABLE(1) |
1143 S_028004_SLICE_EVEN_ENABLE(1) |
1144 S_028004_SLICE_ODD_ENABLE(1);
1145 } else {
1146 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1147 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1148 }
1149 }
1150
1151 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1152 }
1153
1154 static void
1155 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1156 {
1157 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1158
1159 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1160 return;
1161
1162 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1163 radv_emit_viewport(cmd_buffer);
1164
1165 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1166 radv_emit_scissor(cmd_buffer);
1167
1168 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1169 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1170 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1171 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1172 }
1173
1174 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1175 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1176 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1177 }
1178
1179 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1180 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1181 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1182 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1183 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1184 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1185 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1186 S_028430_STENCILOPVAL(1));
1187 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1188 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1189 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1190 S_028434_STENCILOPVAL_BF(1));
1191 }
1192
1193 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1194 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1195 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1196 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1197 }
1198
1199 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1200 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1201 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1202 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1203 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1204
1205 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1206 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1207 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1208 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1209 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1210 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1211 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1212 }
1213 }
1214
1215 cmd_buffer->state.dirty = 0;
1216 }
1217
1218 static void
1219 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1220 struct radv_pipeline *pipeline,
1221 int idx,
1222 uint64_t va,
1223 gl_shader_stage stage)
1224 {
1225 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1226 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1227
1228 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1229 return;
1230
1231 assert(!desc_set_loc->indirect);
1232 assert(desc_set_loc->num_sgprs == 2);
1233 radeon_set_sh_reg_seq(cmd_buffer->cs,
1234 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1235 radeon_emit(cmd_buffer->cs, va);
1236 radeon_emit(cmd_buffer->cs, va >> 32);
1237 }
1238
1239 static void
1240 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1241 struct radv_pipeline *pipeline,
1242 VkShaderStageFlags stages,
1243 struct radv_descriptor_set *set,
1244 unsigned idx)
1245 {
1246 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1247 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1248 idx, set->va,
1249 MESA_SHADER_FRAGMENT);
1250
1251 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1252 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1253 idx, set->va,
1254 MESA_SHADER_VERTEX);
1255
1256 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1257 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1258 idx, set->va,
1259 MESA_SHADER_GEOMETRY);
1260
1261 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1262 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1263 idx, set->va,
1264 MESA_SHADER_TESS_CTRL);
1265
1266 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1267 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1268 idx, set->va,
1269 MESA_SHADER_TESS_EVAL);
1270
1271 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1272 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1273 idx, set->va,
1274 MESA_SHADER_COMPUTE);
1275 }
1276
1277 static void
1278 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1279 {
1280 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1281 uint32_t *ptr = NULL;
1282 unsigned bo_offset;
1283
1284 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1285 &bo_offset,
1286 (void**) &ptr))
1287 return;
1288
1289 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1290 set->va += bo_offset;
1291
1292 memcpy(ptr, set->mapped_ptr, set->size);
1293 }
1294
1295 static void
1296 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1297 struct radv_pipeline *pipeline)
1298 {
1299 uint32_t size = MAX_SETS * 2 * 4;
1300 uint32_t offset;
1301 void *ptr;
1302
1303 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1304 256, &offset, &ptr))
1305 return;
1306
1307 for (unsigned i = 0; i < MAX_SETS; i++) {
1308 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1309 uint64_t set_va = 0;
1310 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1311 if (set)
1312 set_va = set->va;
1313 uptr[0] = set_va & 0xffffffff;
1314 uptr[1] = set_va >> 32;
1315 }
1316
1317 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1318 va += offset;
1319
1320 if (pipeline->shaders[MESA_SHADER_VERTEX])
1321 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1322 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1323
1324 if (pipeline->shaders[MESA_SHADER_FRAGMENT])
1325 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1326 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1327
1328 if (radv_pipeline_has_gs(pipeline))
1329 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1330 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1331
1332 if (radv_pipeline_has_tess(pipeline))
1333 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL,
1334 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1335
1336 if (radv_pipeline_has_tess(pipeline))
1337 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL,
1338 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1339
1340 if (pipeline->shaders[MESA_SHADER_COMPUTE])
1341 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1342 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1343 }
1344
1345 static void
1346 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1347 struct radv_pipeline *pipeline,
1348 VkShaderStageFlags stages)
1349 {
1350 unsigned i;
1351
1352 if (!cmd_buffer->state.descriptors_dirty)
1353 return;
1354
1355 if (cmd_buffer->state.push_descriptors_dirty)
1356 radv_flush_push_descriptors(cmd_buffer);
1357
1358 if (pipeline->need_indirect_descriptor_sets) {
1359 radv_flush_indirect_descriptor_sets(cmd_buffer, pipeline);
1360 }
1361
1362 for (i = 0; i < MAX_SETS; i++) {
1363 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1364 continue;
1365 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1366 if (!set)
1367 continue;
1368
1369 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1370 }
1371 cmd_buffer->state.descriptors_dirty = 0;
1372 cmd_buffer->state.push_descriptors_dirty = false;
1373 }
1374
1375 static void
1376 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1377 struct radv_pipeline *pipeline,
1378 VkShaderStageFlags stages)
1379 {
1380 struct radv_pipeline_layout *layout = pipeline->layout;
1381 unsigned offset;
1382 void *ptr;
1383 uint64_t va;
1384
1385 stages &= cmd_buffer->push_constant_stages;
1386 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1387 return;
1388
1389 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1390 16 * layout->dynamic_offset_count,
1391 256, &offset, &ptr))
1392 return;
1393
1394 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1395 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1396 16 * layout->dynamic_offset_count);
1397
1398 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1399 va += offset;
1400
1401 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1402 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1403 AC_UD_PUSH_CONSTANTS, va);
1404
1405 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1406 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1407 AC_UD_PUSH_CONSTANTS, va);
1408
1409 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1410 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1411 AC_UD_PUSH_CONSTANTS, va);
1412
1413 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1414 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL,
1415 AC_UD_PUSH_CONSTANTS, va);
1416
1417 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1418 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL,
1419 AC_UD_PUSH_CONSTANTS, va);
1420
1421 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1422 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1423 AC_UD_PUSH_CONSTANTS, va);
1424
1425 cmd_buffer->push_constant_stages &= ~stages;
1426 }
1427
1428 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1429 bool indexed_draw)
1430 {
1431 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1432
1433 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1434 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1435 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1436 primitive_reset_en);
1437 }
1438
1439 if (primitive_reset_en) {
1440 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1441
1442 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1443 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1444 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1445 primitive_reset_index);
1446 }
1447 }
1448 }
1449
1450 static void
1451 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1452 bool indexed_draw, bool instanced_draw,
1453 bool indirect_draw,
1454 uint32_t draw_vertex_count)
1455 {
1456 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1457 struct radv_device *device = cmd_buffer->device;
1458 uint32_t ia_multi_vgt_param;
1459
1460 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1461 cmd_buffer->cs, 4096);
1462
1463 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1464 cmd_buffer->state.pipeline->num_vertex_attribs &&
1465 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1466 unsigned vb_offset;
1467 void *vb_ptr;
1468 uint32_t i = 0;
1469 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1470 uint64_t va;
1471
1472 /* allocate some descriptor state for vertex buffers */
1473 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1474 &vb_offset, &vb_ptr);
1475
1476 for (i = 0; i < num_attribs; i++) {
1477 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1478 uint32_t offset;
1479 int vb = cmd_buffer->state.pipeline->va_binding[i];
1480 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1481 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1482
1483 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1484 va = device->ws->buffer_get_va(buffer->bo);
1485
1486 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1487 va += offset + buffer->offset;
1488 desc[0] = va;
1489 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1490 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1491 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1492 else
1493 desc[2] = buffer->size - offset;
1494 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1495 }
1496
1497 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1498 va += vb_offset;
1499
1500 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1501 AC_UD_VS_VERTEX_BUFFERS, va);
1502 }
1503
1504 cmd_buffer->state.vertex_descriptors_dirty = false;
1505 cmd_buffer->state.vb_dirty = 0;
1506 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1507 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1508
1509 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1510 radv_emit_framebuffer_state(cmd_buffer);
1511
1512 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1513 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1514 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1515 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1516 else
1517 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1518 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1519 }
1520
1521 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1522 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1523
1524 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1525 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1526 } else {
1527 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1528 }
1529 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1530 }
1531
1532 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1533
1534 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1535
1536 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1537 VK_SHADER_STAGE_ALL_GRAPHICS);
1538 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1539 VK_SHADER_STAGE_ALL_GRAPHICS);
1540
1541 assert(cmd_buffer->cs->cdw <= cdw_max);
1542
1543 si_emit_cache_flush(cmd_buffer);
1544 }
1545
1546 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1547 VkPipelineStageFlags src_stage_mask)
1548 {
1549 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1550 VK_PIPELINE_STAGE_TRANSFER_BIT |
1551 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1552 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1553 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1554 }
1555
1556 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1557 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1558 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1559 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1560 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1561 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1562 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1563 VK_PIPELINE_STAGE_TRANSFER_BIT |
1564 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1565 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1566 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1567 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1568 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1569 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1570 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1571 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1572 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1573 }
1574 }
1575
1576 static enum radv_cmd_flush_bits
1577 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1578 VkAccessFlags src_flags)
1579 {
1580 enum radv_cmd_flush_bits flush_bits = 0;
1581 uint32_t b;
1582 for_each_bit(b, src_flags) {
1583 switch ((VkAccessFlagBits)(1 << b)) {
1584 case VK_ACCESS_SHADER_WRITE_BIT:
1585 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1586 break;
1587 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1588 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1589 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1590 break;
1591 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1592 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1593 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1594 break;
1595 case VK_ACCESS_TRANSFER_WRITE_BIT:
1596 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1597 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1598 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1599 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1600 RADV_CMD_FLAG_INV_GLOBAL_L2;
1601 break;
1602 default:
1603 break;
1604 }
1605 }
1606 return flush_bits;
1607 }
1608
1609 static enum radv_cmd_flush_bits
1610 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1611 VkAccessFlags dst_flags,
1612 struct radv_image *image)
1613 {
1614 enum radv_cmd_flush_bits flush_bits = 0;
1615 uint32_t b;
1616 for_each_bit(b, dst_flags) {
1617 switch ((VkAccessFlagBits)(1 << b)) {
1618 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1619 case VK_ACCESS_INDEX_READ_BIT:
1620 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1621 break;
1622 case VK_ACCESS_UNIFORM_READ_BIT:
1623 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1624 break;
1625 case VK_ACCESS_SHADER_READ_BIT:
1626 case VK_ACCESS_TRANSFER_READ_BIT:
1627 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1628 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1629 RADV_CMD_FLAG_INV_GLOBAL_L2;
1630 break;
1631 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1632 /* TODO: change to image && when the image gets passed
1633 * through from the subpass. */
1634 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1635 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1636 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1637 break;
1638 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1639 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1640 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1641 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1642 break;
1643 default:
1644 break;
1645 }
1646 }
1647 return flush_bits;
1648 }
1649
1650 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1651 {
1652 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1653 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1654 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1655 NULL);
1656 }
1657
1658 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1659 VkAttachmentReference att)
1660 {
1661 unsigned idx = att.attachment;
1662 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1663 VkImageSubresourceRange range;
1664 range.aspectMask = 0;
1665 range.baseMipLevel = view->base_mip;
1666 range.levelCount = 1;
1667 range.baseArrayLayer = view->base_layer;
1668 range.layerCount = cmd_buffer->state.framebuffer->layers;
1669
1670 radv_handle_image_transition(cmd_buffer,
1671 view->image,
1672 cmd_buffer->state.attachments[idx].current_layout,
1673 att.layout, 0, 0, &range,
1674 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1675
1676 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1677
1678
1679 }
1680
1681 void
1682 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1683 const struct radv_subpass *subpass, bool transitions)
1684 {
1685 if (transitions) {
1686 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1687
1688 for (unsigned i = 0; i < subpass->color_count; ++i) {
1689 radv_handle_subpass_image_transition(cmd_buffer,
1690 subpass->color_attachments[i]);
1691 }
1692
1693 for (unsigned i = 0; i < subpass->input_count; ++i) {
1694 radv_handle_subpass_image_transition(cmd_buffer,
1695 subpass->input_attachments[i]);
1696 }
1697
1698 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1699 radv_handle_subpass_image_transition(cmd_buffer,
1700 subpass->depth_stencil_attachment);
1701 }
1702 }
1703
1704 cmd_buffer->state.subpass = subpass;
1705
1706 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1707 }
1708
1709 static void
1710 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1711 struct radv_render_pass *pass,
1712 const VkRenderPassBeginInfo *info)
1713 {
1714 struct radv_cmd_state *state = &cmd_buffer->state;
1715
1716 if (pass->attachment_count == 0) {
1717 state->attachments = NULL;
1718 return;
1719 }
1720
1721 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1722 pass->attachment_count *
1723 sizeof(state->attachments[0]),
1724 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1725 if (state->attachments == NULL) {
1726 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1727 abort();
1728 }
1729
1730 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1731 struct radv_render_pass_attachment *att = &pass->attachments[i];
1732 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1733 VkImageAspectFlags clear_aspects = 0;
1734
1735 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1736 /* color attachment */
1737 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1738 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1739 }
1740 } else {
1741 /* depthstencil attachment */
1742 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1743 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1744 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1745 }
1746 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1747 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1748 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1749 }
1750 }
1751
1752 state->attachments[i].pending_clear_aspects = clear_aspects;
1753 if (clear_aspects && info) {
1754 assert(info->clearValueCount > i);
1755 state->attachments[i].clear_value = info->pClearValues[i];
1756 }
1757
1758 state->attachments[i].current_layout = att->initial_layout;
1759 }
1760 }
1761
1762 VkResult radv_AllocateCommandBuffers(
1763 VkDevice _device,
1764 const VkCommandBufferAllocateInfo *pAllocateInfo,
1765 VkCommandBuffer *pCommandBuffers)
1766 {
1767 RADV_FROM_HANDLE(radv_device, device, _device);
1768 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1769
1770 VkResult result = VK_SUCCESS;
1771 uint32_t i;
1772
1773 memset(pCommandBuffers, 0,
1774 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1775
1776 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1777
1778 if (!list_empty(&pool->free_cmd_buffers)) {
1779 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1780
1781 list_del(&cmd_buffer->pool_link);
1782 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1783
1784 radv_reset_cmd_buffer(cmd_buffer);
1785 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1786 cmd_buffer->level = pAllocateInfo->level;
1787
1788 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1789 result = VK_SUCCESS;
1790 } else {
1791 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1792 &pCommandBuffers[i]);
1793 }
1794 if (result != VK_SUCCESS)
1795 break;
1796 }
1797
1798 if (result != VK_SUCCESS)
1799 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1800 i, pCommandBuffers);
1801
1802 return result;
1803 }
1804
1805 void radv_FreeCommandBuffers(
1806 VkDevice device,
1807 VkCommandPool commandPool,
1808 uint32_t commandBufferCount,
1809 const VkCommandBuffer *pCommandBuffers)
1810 {
1811 for (uint32_t i = 0; i < commandBufferCount; i++) {
1812 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1813
1814 if (cmd_buffer) {
1815 if (cmd_buffer->pool) {
1816 list_del(&cmd_buffer->pool_link);
1817 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1818 } else
1819 radv_cmd_buffer_destroy(cmd_buffer);
1820
1821 }
1822 }
1823 }
1824
1825 VkResult radv_ResetCommandBuffer(
1826 VkCommandBuffer commandBuffer,
1827 VkCommandBufferResetFlags flags)
1828 {
1829 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1830 radv_reset_cmd_buffer(cmd_buffer);
1831 return VK_SUCCESS;
1832 }
1833
1834 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1835 {
1836 struct radv_device *device = cmd_buffer->device;
1837 if (device->gfx_init) {
1838 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1839 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1840 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1841 radeon_emit(cmd_buffer->cs, va);
1842 radeon_emit(cmd_buffer->cs, (va >> 32) & 0xffff);
1843 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1844 } else
1845 si_init_config(cmd_buffer);
1846 }
1847
1848 VkResult radv_BeginCommandBuffer(
1849 VkCommandBuffer commandBuffer,
1850 const VkCommandBufferBeginInfo *pBeginInfo)
1851 {
1852 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1853 radv_reset_cmd_buffer(cmd_buffer);
1854
1855 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1856 cmd_buffer->state.last_primitive_reset_en = -1;
1857
1858 /* setup initial configuration into command buffer */
1859 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1860 switch (cmd_buffer->queue_family_index) {
1861 case RADV_QUEUE_GENERAL:
1862 emit_gfx_buffer_state(cmd_buffer);
1863 radv_set_db_count_control(cmd_buffer);
1864 break;
1865 case RADV_QUEUE_COMPUTE:
1866 si_init_compute(cmd_buffer);
1867 break;
1868 case RADV_QUEUE_TRANSFER:
1869 default:
1870 break;
1871 }
1872 }
1873
1874 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1875 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1876 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1877
1878 struct radv_subpass *subpass =
1879 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1880
1881 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1882 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1883 }
1884
1885 radv_cmd_buffer_trace_emit(cmd_buffer);
1886 return VK_SUCCESS;
1887 }
1888
1889 void radv_CmdBindVertexBuffers(
1890 VkCommandBuffer commandBuffer,
1891 uint32_t firstBinding,
1892 uint32_t bindingCount,
1893 const VkBuffer* pBuffers,
1894 const VkDeviceSize* pOffsets)
1895 {
1896 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1897 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1898
1899 /* We have to defer setting up vertex buffer since we need the buffer
1900 * stride from the pipeline. */
1901
1902 assert(firstBinding + bindingCount < MAX_VBS);
1903 for (uint32_t i = 0; i < bindingCount; i++) {
1904 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1905 vb[firstBinding + i].offset = pOffsets[i];
1906 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1907 }
1908 }
1909
1910 void radv_CmdBindIndexBuffer(
1911 VkCommandBuffer commandBuffer,
1912 VkBuffer buffer,
1913 VkDeviceSize offset,
1914 VkIndexType indexType)
1915 {
1916 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1917
1918 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1919 cmd_buffer->state.index_offset = offset;
1920 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1921 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1922 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1923 }
1924
1925
1926 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1927 struct radv_descriptor_set *set,
1928 unsigned idx)
1929 {
1930 struct radeon_winsys *ws = cmd_buffer->device->ws;
1931
1932 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
1933
1934 cmd_buffer->state.descriptors[idx] = set;
1935 cmd_buffer->state.descriptors_dirty |= (1u << idx);
1936 if (!set)
1937 return;
1938
1939 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1940 if (set->descriptors[j])
1941 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1942
1943 if(set->bo)
1944 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1945 }
1946
1947 void radv_CmdBindDescriptorSets(
1948 VkCommandBuffer commandBuffer,
1949 VkPipelineBindPoint pipelineBindPoint,
1950 VkPipelineLayout _layout,
1951 uint32_t firstSet,
1952 uint32_t descriptorSetCount,
1953 const VkDescriptorSet* pDescriptorSets,
1954 uint32_t dynamicOffsetCount,
1955 const uint32_t* pDynamicOffsets)
1956 {
1957 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1958 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1959 unsigned dyn_idx = 0;
1960
1961 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1962 unsigned idx = i + firstSet;
1963 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1964 radv_bind_descriptor_set(cmd_buffer, set, idx);
1965
1966 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1967 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1968 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1969 assert(dyn_idx < dynamicOffsetCount);
1970
1971 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1972 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1973 dst[0] = va;
1974 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1975 dst[2] = range->size;
1976 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1977 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1978 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1979 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1980 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1981 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1982 cmd_buffer->push_constant_stages |=
1983 set->layout->dynamic_shader_stages;
1984 }
1985 }
1986 }
1987
1988 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1989 struct radv_descriptor_set *set,
1990 struct radv_descriptor_set_layout *layout)
1991 {
1992 set->size = layout->size;
1993 set->layout = layout;
1994
1995 if (cmd_buffer->push_descriptors.capacity < set->size) {
1996 size_t new_size = MAX2(set->size, 1024);
1997 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
1998 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
1999
2000 free(set->mapped_ptr);
2001 set->mapped_ptr = malloc(new_size);
2002
2003 if (!set->mapped_ptr) {
2004 cmd_buffer->push_descriptors.capacity = 0;
2005 cmd_buffer->record_fail = true;
2006 return false;
2007 }
2008
2009 cmd_buffer->push_descriptors.capacity = new_size;
2010 }
2011
2012 return true;
2013 }
2014
2015 void radv_meta_push_descriptor_set(
2016 struct radv_cmd_buffer* cmd_buffer,
2017 VkPipelineBindPoint pipelineBindPoint,
2018 VkPipelineLayout _layout,
2019 uint32_t set,
2020 uint32_t descriptorWriteCount,
2021 const VkWriteDescriptorSet* pDescriptorWrites)
2022 {
2023 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2024 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2025 unsigned bo_offset;
2026
2027 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2028
2029 push_set->size = layout->set[set].layout->size;
2030 push_set->layout = layout->set[set].layout;
2031
2032 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2033 &bo_offset,
2034 (void**) &push_set->mapped_ptr))
2035 return;
2036
2037 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2038 push_set->va += bo_offset;
2039
2040 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2041 radv_descriptor_set_to_handle(push_set),
2042 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2043
2044 cmd_buffer->state.descriptors[set] = push_set;
2045 cmd_buffer->state.descriptors_dirty |= (1u << set);
2046 }
2047
2048 void radv_CmdPushDescriptorSetKHR(
2049 VkCommandBuffer commandBuffer,
2050 VkPipelineBindPoint pipelineBindPoint,
2051 VkPipelineLayout _layout,
2052 uint32_t set,
2053 uint32_t descriptorWriteCount,
2054 const VkWriteDescriptorSet* pDescriptorWrites)
2055 {
2056 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2057 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2058 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2059
2060 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2061
2062 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2063 return;
2064
2065 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2066 radv_descriptor_set_to_handle(push_set),
2067 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2068
2069 cmd_buffer->state.descriptors[set] = push_set;
2070 cmd_buffer->state.descriptors_dirty |= (1u << set);
2071 cmd_buffer->state.push_descriptors_dirty = true;
2072 }
2073
2074 void radv_CmdPushDescriptorSetWithTemplateKHR(
2075 VkCommandBuffer commandBuffer,
2076 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2077 VkPipelineLayout _layout,
2078 uint32_t set,
2079 const void* pData)
2080 {
2081 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2082 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2083 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2084
2085 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2086
2087 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2088 return;
2089
2090 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2091 descriptorUpdateTemplate, pData);
2092
2093 cmd_buffer->state.descriptors[set] = push_set;
2094 cmd_buffer->state.descriptors_dirty |= (1u << set);
2095 cmd_buffer->state.push_descriptors_dirty = true;
2096 }
2097
2098 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2099 VkPipelineLayout layout,
2100 VkShaderStageFlags stageFlags,
2101 uint32_t offset,
2102 uint32_t size,
2103 const void* pValues)
2104 {
2105 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2106 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2107 cmd_buffer->push_constant_stages |= stageFlags;
2108 }
2109
2110 VkResult radv_EndCommandBuffer(
2111 VkCommandBuffer commandBuffer)
2112 {
2113 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2114
2115 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
2116 si_emit_cache_flush(cmd_buffer);
2117
2118 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
2119 cmd_buffer->record_fail)
2120 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2121 return VK_SUCCESS;
2122 }
2123
2124 static void
2125 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2126 {
2127 struct radeon_winsys *ws = cmd_buffer->device->ws;
2128 struct radv_shader_variant *compute_shader;
2129 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2130 uint64_t va;
2131
2132 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2133 return;
2134
2135 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2136
2137 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2138 va = ws->buffer_get_va(compute_shader->bo);
2139
2140 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2141 si_cp_dma_prefetch(cmd_buffer, va, compute_shader->code_size);
2142
2143 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2144 cmd_buffer->cs, 16);
2145
2146 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2147 radeon_emit(cmd_buffer->cs, va >> 8);
2148 radeon_emit(cmd_buffer->cs, va >> 40);
2149
2150 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2151 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2152 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2153
2154
2155 cmd_buffer->compute_scratch_size_needed =
2156 MAX2(cmd_buffer->compute_scratch_size_needed,
2157 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2158
2159 /* change these once we have scratch support */
2160 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2161 S_00B860_WAVES(pipeline->max_waves) |
2162 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2163
2164 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2165 radeon_emit(cmd_buffer->cs,
2166 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2167 radeon_emit(cmd_buffer->cs,
2168 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2169 radeon_emit(cmd_buffer->cs,
2170 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2171
2172 assert(cmd_buffer->cs->cdw <= cdw_max);
2173 }
2174
2175
2176 void radv_CmdBindPipeline(
2177 VkCommandBuffer commandBuffer,
2178 VkPipelineBindPoint pipelineBindPoint,
2179 VkPipeline _pipeline)
2180 {
2181 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2182 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2183
2184 for (unsigned i = 0; i < MAX_SETS; i++) {
2185 if (cmd_buffer->state.descriptors[i])
2186 cmd_buffer->state.descriptors_dirty |= (1u << i);
2187 }
2188
2189 switch (pipelineBindPoint) {
2190 case VK_PIPELINE_BIND_POINT_COMPUTE:
2191 cmd_buffer->state.compute_pipeline = pipeline;
2192 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2193 break;
2194 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2195 cmd_buffer->state.pipeline = pipeline;
2196 cmd_buffer->state.vertex_descriptors_dirty = true;
2197 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2198 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2199
2200 /* Apply the dynamic state from the pipeline */
2201 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2202 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2203 &pipeline->dynamic_state,
2204 pipeline->dynamic_state_mask);
2205
2206 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2207 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2208 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2209 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2210
2211 if (radv_pipeline_has_tess(pipeline))
2212 cmd_buffer->tess_rings_needed = true;
2213
2214 if (radv_pipeline_has_gs(pipeline)) {
2215 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2216 AC_UD_SCRATCH_RING_OFFSETS);
2217 if (cmd_buffer->ring_offsets_idx == -1)
2218 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2219 else if (loc->sgpr_idx != -1)
2220 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2221 }
2222 break;
2223 default:
2224 assert(!"invalid bind point");
2225 break;
2226 }
2227 }
2228
2229 void radv_CmdSetViewport(
2230 VkCommandBuffer commandBuffer,
2231 uint32_t firstViewport,
2232 uint32_t viewportCount,
2233 const VkViewport* pViewports)
2234 {
2235 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2236
2237 const uint32_t total_count = firstViewport + viewportCount;
2238 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2239 cmd_buffer->state.dynamic.viewport.count = total_count;
2240
2241 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2242 pViewports, viewportCount * sizeof(*pViewports));
2243
2244 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2245 }
2246
2247 void radv_CmdSetScissor(
2248 VkCommandBuffer commandBuffer,
2249 uint32_t firstScissor,
2250 uint32_t scissorCount,
2251 const VkRect2D* pScissors)
2252 {
2253 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2254
2255 const uint32_t total_count = firstScissor + scissorCount;
2256 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2257 cmd_buffer->state.dynamic.scissor.count = total_count;
2258
2259 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2260 pScissors, scissorCount * sizeof(*pScissors));
2261 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2262 }
2263
2264 void radv_CmdSetLineWidth(
2265 VkCommandBuffer commandBuffer,
2266 float lineWidth)
2267 {
2268 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2269 cmd_buffer->state.dynamic.line_width = lineWidth;
2270 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2271 }
2272
2273 void radv_CmdSetDepthBias(
2274 VkCommandBuffer commandBuffer,
2275 float depthBiasConstantFactor,
2276 float depthBiasClamp,
2277 float depthBiasSlopeFactor)
2278 {
2279 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2280
2281 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2282 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2283 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2284
2285 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2286 }
2287
2288 void radv_CmdSetBlendConstants(
2289 VkCommandBuffer commandBuffer,
2290 const float blendConstants[4])
2291 {
2292 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2293
2294 memcpy(cmd_buffer->state.dynamic.blend_constants,
2295 blendConstants, sizeof(float) * 4);
2296
2297 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2298 }
2299
2300 void radv_CmdSetDepthBounds(
2301 VkCommandBuffer commandBuffer,
2302 float minDepthBounds,
2303 float maxDepthBounds)
2304 {
2305 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2306
2307 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2308 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2309
2310 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2311 }
2312
2313 void radv_CmdSetStencilCompareMask(
2314 VkCommandBuffer commandBuffer,
2315 VkStencilFaceFlags faceMask,
2316 uint32_t compareMask)
2317 {
2318 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2319
2320 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2321 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2322 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2323 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2324
2325 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2326 }
2327
2328 void radv_CmdSetStencilWriteMask(
2329 VkCommandBuffer commandBuffer,
2330 VkStencilFaceFlags faceMask,
2331 uint32_t writeMask)
2332 {
2333 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2334
2335 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2336 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2337 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2338 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2339
2340 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2341 }
2342
2343 void radv_CmdSetStencilReference(
2344 VkCommandBuffer commandBuffer,
2345 VkStencilFaceFlags faceMask,
2346 uint32_t reference)
2347 {
2348 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2349
2350 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2351 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2352 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2353 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2354
2355 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2356 }
2357
2358
2359 void radv_CmdExecuteCommands(
2360 VkCommandBuffer commandBuffer,
2361 uint32_t commandBufferCount,
2362 const VkCommandBuffer* pCmdBuffers)
2363 {
2364 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2365
2366 /* Emit pending flushes on primary prior to executing secondary */
2367 si_emit_cache_flush(primary);
2368
2369 for (uint32_t i = 0; i < commandBufferCount; i++) {
2370 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2371
2372 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2373 secondary->scratch_size_needed);
2374 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2375 secondary->compute_scratch_size_needed);
2376
2377 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2378 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2379 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2380 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2381 if (secondary->tess_rings_needed)
2382 primary->tess_rings_needed = true;
2383 if (secondary->sample_positions_needed)
2384 primary->sample_positions_needed = true;
2385
2386 if (secondary->ring_offsets_idx != -1) {
2387 if (primary->ring_offsets_idx == -1)
2388 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2389 else
2390 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2391 }
2392 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2393 }
2394
2395 /* if we execute secondary we need to re-emit out pipelines */
2396 if (commandBufferCount) {
2397 primary->state.emitted_pipeline = NULL;
2398 primary->state.emitted_compute_pipeline = NULL;
2399 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2400 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2401 primary->state.last_primitive_reset_en = -1;
2402 primary->state.last_primitive_reset_index = 0;
2403 }
2404 }
2405
2406 VkResult radv_CreateCommandPool(
2407 VkDevice _device,
2408 const VkCommandPoolCreateInfo* pCreateInfo,
2409 const VkAllocationCallbacks* pAllocator,
2410 VkCommandPool* pCmdPool)
2411 {
2412 RADV_FROM_HANDLE(radv_device, device, _device);
2413 struct radv_cmd_pool *pool;
2414
2415 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2416 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2417 if (pool == NULL)
2418 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2419
2420 if (pAllocator)
2421 pool->alloc = *pAllocator;
2422 else
2423 pool->alloc = device->alloc;
2424
2425 list_inithead(&pool->cmd_buffers);
2426 list_inithead(&pool->free_cmd_buffers);
2427
2428 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2429
2430 *pCmdPool = radv_cmd_pool_to_handle(pool);
2431
2432 return VK_SUCCESS;
2433
2434 }
2435
2436 void radv_DestroyCommandPool(
2437 VkDevice _device,
2438 VkCommandPool commandPool,
2439 const VkAllocationCallbacks* pAllocator)
2440 {
2441 RADV_FROM_HANDLE(radv_device, device, _device);
2442 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2443
2444 if (!pool)
2445 return;
2446
2447 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2448 &pool->cmd_buffers, pool_link) {
2449 radv_cmd_buffer_destroy(cmd_buffer);
2450 }
2451
2452 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2453 &pool->free_cmd_buffers, pool_link) {
2454 radv_cmd_buffer_destroy(cmd_buffer);
2455 }
2456
2457 vk_free2(&device->alloc, pAllocator, pool);
2458 }
2459
2460 VkResult radv_ResetCommandPool(
2461 VkDevice device,
2462 VkCommandPool commandPool,
2463 VkCommandPoolResetFlags flags)
2464 {
2465 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2466
2467 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2468 &pool->cmd_buffers, pool_link) {
2469 radv_reset_cmd_buffer(cmd_buffer);
2470 }
2471
2472 return VK_SUCCESS;
2473 }
2474
2475 void radv_TrimCommandPoolKHR(
2476 VkDevice device,
2477 VkCommandPool commandPool,
2478 VkCommandPoolTrimFlagsKHR flags)
2479 {
2480 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2481
2482 if (!pool)
2483 return;
2484
2485 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2486 &pool->free_cmd_buffers, pool_link) {
2487 radv_cmd_buffer_destroy(cmd_buffer);
2488 }
2489 }
2490
2491 void radv_CmdBeginRenderPass(
2492 VkCommandBuffer commandBuffer,
2493 const VkRenderPassBeginInfo* pRenderPassBegin,
2494 VkSubpassContents contents)
2495 {
2496 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2497 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2498 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2499
2500 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2501 cmd_buffer->cs, 2048);
2502
2503 cmd_buffer->state.framebuffer = framebuffer;
2504 cmd_buffer->state.pass = pass;
2505 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2506 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2507
2508 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2509 assert(cmd_buffer->cs->cdw <= cdw_max);
2510
2511 radv_cmd_buffer_clear_subpass(cmd_buffer);
2512 }
2513
2514 void radv_CmdNextSubpass(
2515 VkCommandBuffer commandBuffer,
2516 VkSubpassContents contents)
2517 {
2518 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2519
2520 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2521
2522 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2523 2048);
2524
2525 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2526 radv_cmd_buffer_clear_subpass(cmd_buffer);
2527 }
2528
2529 void radv_CmdDraw(
2530 VkCommandBuffer commandBuffer,
2531 uint32_t vertexCount,
2532 uint32_t instanceCount,
2533 uint32_t firstVertex,
2534 uint32_t firstInstance)
2535 {
2536 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2537
2538 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2539
2540 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2541
2542 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2543 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2544 if (loc->sgpr_idx != -1) {
2545 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2546 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2547 int vs_num = 2;
2548 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2549 vs_num = 3;
2550
2551 assert (loc->num_sgprs == vs_num);
2552 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
2553 radeon_emit(cmd_buffer->cs, firstVertex);
2554 radeon_emit(cmd_buffer->cs, firstInstance);
2555 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2556 radeon_emit(cmd_buffer->cs, 0);
2557 }
2558 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2559 radeon_emit(cmd_buffer->cs, instanceCount);
2560
2561 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2562 radeon_emit(cmd_buffer->cs, vertexCount);
2563 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2564 S_0287F0_USE_OPAQUE(0));
2565
2566 assert(cmd_buffer->cs->cdw <= cdw_max);
2567
2568 radv_cmd_buffer_trace_emit(cmd_buffer);
2569 }
2570
2571 void radv_CmdDrawIndexed(
2572 VkCommandBuffer commandBuffer,
2573 uint32_t indexCount,
2574 uint32_t instanceCount,
2575 uint32_t firstIndex,
2576 int32_t vertexOffset,
2577 uint32_t firstInstance)
2578 {
2579 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2580 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2581 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2582 uint64_t index_va;
2583
2584 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2585
2586 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2587
2588 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2589 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2590
2591 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2592 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2593 if (loc->sgpr_idx != -1) {
2594 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2595 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2596 int vs_num = 2;
2597 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2598 vs_num = 3;
2599
2600 assert (loc->num_sgprs == vs_num);
2601 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
2602 radeon_emit(cmd_buffer->cs, vertexOffset);
2603 radeon_emit(cmd_buffer->cs, firstInstance);
2604 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2605 radeon_emit(cmd_buffer->cs, 0);
2606 }
2607 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2608 radeon_emit(cmd_buffer->cs, instanceCount);
2609
2610 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2611 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2612 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2613 radeon_emit(cmd_buffer->cs, index_max_size);
2614 radeon_emit(cmd_buffer->cs, index_va);
2615 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2616 radeon_emit(cmd_buffer->cs, indexCount);
2617 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2618
2619 assert(cmd_buffer->cs->cdw <= cdw_max);
2620 radv_cmd_buffer_trace_emit(cmd_buffer);
2621 }
2622
2623 static void
2624 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2625 VkBuffer _buffer,
2626 VkDeviceSize offset,
2627 VkBuffer _count_buffer,
2628 VkDeviceSize count_offset,
2629 uint32_t draw_count,
2630 uint32_t stride,
2631 bool indexed)
2632 {
2633 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2634 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2635 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2636 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2637 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2638 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2639 indirect_va += offset + buffer->offset;
2640 uint64_t count_va = 0;
2641
2642 if (count_buffer) {
2643 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2644 count_va += count_offset + count_buffer->offset;
2645 }
2646
2647 if (!draw_count)
2648 return;
2649
2650 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2651
2652 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2653 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2654 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2655 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2656 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2657 assert(loc->sgpr_idx != -1);
2658 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2659 radeon_emit(cs, 1);
2660 radeon_emit(cs, indirect_va);
2661 radeon_emit(cs, indirect_va >> 32);
2662
2663 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2664 PKT3_DRAW_INDIRECT_MULTI,
2665 8, false));
2666 radeon_emit(cs, 0);
2667 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2668 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2669 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2670 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2671 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2672 radeon_emit(cs, draw_count); /* count */
2673 radeon_emit(cs, count_va); /* count_addr */
2674 radeon_emit(cs, count_va >> 32);
2675 radeon_emit(cs, stride); /* stride */
2676 radeon_emit(cs, di_src_sel);
2677 radv_cmd_buffer_trace_emit(cmd_buffer);
2678 }
2679
2680 static void
2681 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2682 VkBuffer buffer,
2683 VkDeviceSize offset,
2684 VkBuffer countBuffer,
2685 VkDeviceSize countBufferOffset,
2686 uint32_t maxDrawCount,
2687 uint32_t stride)
2688 {
2689 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2690 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2691
2692 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2693 cmd_buffer->cs, 14);
2694
2695 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2696 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2697
2698 assert(cmd_buffer->cs->cdw <= cdw_max);
2699 }
2700
2701 static void
2702 radv_cmd_draw_indexed_indirect_count(
2703 VkCommandBuffer commandBuffer,
2704 VkBuffer buffer,
2705 VkDeviceSize offset,
2706 VkBuffer countBuffer,
2707 VkDeviceSize countBufferOffset,
2708 uint32_t maxDrawCount,
2709 uint32_t stride)
2710 {
2711 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2712 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2713 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2714 uint64_t index_va;
2715 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2716
2717 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2718 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2719
2720 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2721
2722 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2723 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2724
2725 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2726 radeon_emit(cmd_buffer->cs, index_va);
2727 radeon_emit(cmd_buffer->cs, index_va >> 32);
2728
2729 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2730 radeon_emit(cmd_buffer->cs, index_max_size);
2731
2732 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2733 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2734
2735 assert(cmd_buffer->cs->cdw <= cdw_max);
2736 }
2737
2738 void radv_CmdDrawIndirect(
2739 VkCommandBuffer commandBuffer,
2740 VkBuffer buffer,
2741 VkDeviceSize offset,
2742 uint32_t drawCount,
2743 uint32_t stride)
2744 {
2745 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2746 VK_NULL_HANDLE, 0, drawCount, stride);
2747 }
2748
2749 void radv_CmdDrawIndexedIndirect(
2750 VkCommandBuffer commandBuffer,
2751 VkBuffer buffer,
2752 VkDeviceSize offset,
2753 uint32_t drawCount,
2754 uint32_t stride)
2755 {
2756 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2757 VK_NULL_HANDLE, 0, drawCount, stride);
2758 }
2759
2760 void radv_CmdDrawIndirectCountAMD(
2761 VkCommandBuffer commandBuffer,
2762 VkBuffer buffer,
2763 VkDeviceSize offset,
2764 VkBuffer countBuffer,
2765 VkDeviceSize countBufferOffset,
2766 uint32_t maxDrawCount,
2767 uint32_t stride)
2768 {
2769 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2770 countBuffer, countBufferOffset,
2771 maxDrawCount, stride);
2772 }
2773
2774 void radv_CmdDrawIndexedIndirectCountAMD(
2775 VkCommandBuffer commandBuffer,
2776 VkBuffer buffer,
2777 VkDeviceSize offset,
2778 VkBuffer countBuffer,
2779 VkDeviceSize countBufferOffset,
2780 uint32_t maxDrawCount,
2781 uint32_t stride)
2782 {
2783 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2784 countBuffer, countBufferOffset,
2785 maxDrawCount, stride);
2786 }
2787
2788 static void
2789 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2790 {
2791 radv_emit_compute_pipeline(cmd_buffer);
2792 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2793 VK_SHADER_STAGE_COMPUTE_BIT);
2794 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2795 VK_SHADER_STAGE_COMPUTE_BIT);
2796 si_emit_cache_flush(cmd_buffer);
2797 }
2798
2799 void radv_CmdDispatch(
2800 VkCommandBuffer commandBuffer,
2801 uint32_t x,
2802 uint32_t y,
2803 uint32_t z)
2804 {
2805 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2806
2807 radv_flush_compute_state(cmd_buffer);
2808
2809 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2810
2811 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2812 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2813 if (loc->sgpr_idx != -1) {
2814 assert(!loc->indirect);
2815 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2816 assert(loc->num_sgprs == grid_used);
2817 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2818 radeon_emit(cmd_buffer->cs, x);
2819 if (grid_used > 1)
2820 radeon_emit(cmd_buffer->cs, y);
2821 if (grid_used > 2)
2822 radeon_emit(cmd_buffer->cs, z);
2823 }
2824
2825 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2826 PKT3_SHADER_TYPE_S(1));
2827 radeon_emit(cmd_buffer->cs, x);
2828 radeon_emit(cmd_buffer->cs, y);
2829 radeon_emit(cmd_buffer->cs, z);
2830 radeon_emit(cmd_buffer->cs, 1);
2831
2832 assert(cmd_buffer->cs->cdw <= cdw_max);
2833 radv_cmd_buffer_trace_emit(cmd_buffer);
2834 }
2835
2836 void radv_CmdDispatchIndirect(
2837 VkCommandBuffer commandBuffer,
2838 VkBuffer _buffer,
2839 VkDeviceSize offset)
2840 {
2841 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2842 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2843 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2844 va += buffer->offset + offset;
2845
2846 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2847
2848 radv_flush_compute_state(cmd_buffer);
2849
2850 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2851 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2852 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2853 if (loc->sgpr_idx != -1) {
2854 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2855 for (unsigned i = 0; i < grid_used; ++i) {
2856 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2857 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2858 COPY_DATA_DST_SEL(COPY_DATA_REG));
2859 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2860 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2861 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2862 radeon_emit(cmd_buffer->cs, 0);
2863 }
2864 }
2865
2866 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2867 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2868 PKT3_SHADER_TYPE_S(1));
2869 radeon_emit(cmd_buffer->cs, va);
2870 radeon_emit(cmd_buffer->cs, va >> 32);
2871 radeon_emit(cmd_buffer->cs, 1);
2872 } else {
2873 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2874 PKT3_SHADER_TYPE_S(1));
2875 radeon_emit(cmd_buffer->cs, 1);
2876 radeon_emit(cmd_buffer->cs, va);
2877 radeon_emit(cmd_buffer->cs, va >> 32);
2878
2879 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2880 PKT3_SHADER_TYPE_S(1));
2881 radeon_emit(cmd_buffer->cs, 0);
2882 radeon_emit(cmd_buffer->cs, 1);
2883 }
2884
2885 assert(cmd_buffer->cs->cdw <= cdw_max);
2886 radv_cmd_buffer_trace_emit(cmd_buffer);
2887 }
2888
2889 void radv_unaligned_dispatch(
2890 struct radv_cmd_buffer *cmd_buffer,
2891 uint32_t x,
2892 uint32_t y,
2893 uint32_t z)
2894 {
2895 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2896 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2897 uint32_t blocks[3], remainder[3];
2898
2899 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2900 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2901 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2902
2903 /* If aligned, these should be an entire block size, not 0 */
2904 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2905 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2906 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2907
2908 radv_flush_compute_state(cmd_buffer);
2909
2910 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2911
2912 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2913 radeon_emit(cmd_buffer->cs,
2914 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2915 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2916 radeon_emit(cmd_buffer->cs,
2917 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2918 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2919 radeon_emit(cmd_buffer->cs,
2920 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2921 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2922
2923 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2924 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2925 if (loc->sgpr_idx != -1) {
2926 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2927 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2928 radeon_emit(cmd_buffer->cs, blocks[0]);
2929 if (grid_used > 1)
2930 radeon_emit(cmd_buffer->cs, blocks[1]);
2931 if (grid_used > 2)
2932 radeon_emit(cmd_buffer->cs, blocks[2]);
2933 }
2934 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2935 PKT3_SHADER_TYPE_S(1));
2936 radeon_emit(cmd_buffer->cs, blocks[0]);
2937 radeon_emit(cmd_buffer->cs, blocks[1]);
2938 radeon_emit(cmd_buffer->cs, blocks[2]);
2939 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2940 S_00B800_PARTIAL_TG_EN(1));
2941
2942 assert(cmd_buffer->cs->cdw <= cdw_max);
2943 radv_cmd_buffer_trace_emit(cmd_buffer);
2944 }
2945
2946 void radv_CmdEndRenderPass(
2947 VkCommandBuffer commandBuffer)
2948 {
2949 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2950
2951 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2952
2953 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2954
2955 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2956 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2957 radv_handle_subpass_image_transition(cmd_buffer,
2958 (VkAttachmentReference){i, layout});
2959 }
2960
2961 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2962
2963 cmd_buffer->state.pass = NULL;
2964 cmd_buffer->state.subpass = NULL;
2965 cmd_buffer->state.attachments = NULL;
2966 cmd_buffer->state.framebuffer = NULL;
2967 }
2968
2969
2970 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2971 struct radv_image *image,
2972 const VkImageSubresourceRange *range)
2973 {
2974 assert(range->baseMipLevel == 0);
2975 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
2976 unsigned layer_count = radv_get_layerCount(image, range);
2977 uint64_t size = image->surface.htile_slice_size * layer_count;
2978 uint64_t offset = image->offset + image->htile_offset +
2979 image->surface.htile_slice_size * range->baseArrayLayer;
2980
2981 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2982 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2983
2984 radv_fill_buffer(cmd_buffer, image->bo, offset, size, 0xffffffff);
2985
2986 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2987 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2988 RADV_CMD_FLAG_INV_VMEM_L1 |
2989 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2990 }
2991
2992 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2993 struct radv_image *image,
2994 VkImageLayout src_layout,
2995 VkImageLayout dst_layout,
2996 const VkImageSubresourceRange *range,
2997 VkImageAspectFlags pending_clears)
2998 {
2999 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3000 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3001 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3002 cmd_buffer->state.render_area.extent.width == image->info.width &&
3003 cmd_buffer->state.render_area.extent.height == image->info.height) {
3004 /* The clear will initialize htile. */
3005 return;
3006 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3007 radv_layout_has_htile(image, dst_layout)) {
3008 /* TODO: merge with the clear if applicable */
3009 radv_initialize_htile(cmd_buffer, image, range);
3010 } else if (radv_layout_is_htile_compressed(image, src_layout) &&
3011 !radv_layout_is_htile_compressed(image, dst_layout)) {
3012 VkImageSubresourceRange local_range = *range;
3013 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3014 local_range.baseMipLevel = 0;
3015 local_range.levelCount = 1;
3016
3017 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3018 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3019
3020 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3021
3022 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3023 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3024 }
3025 }
3026
3027 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3028 struct radv_image *image, uint32_t value)
3029 {
3030 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3031 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3032
3033 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3034 image->cmask.size, value);
3035
3036 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3037 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3038 RADV_CMD_FLAG_INV_VMEM_L1 |
3039 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3040 }
3041
3042 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3043 struct radv_image *image,
3044 VkImageLayout src_layout,
3045 VkImageLayout dst_layout,
3046 unsigned src_queue_mask,
3047 unsigned dst_queue_mask,
3048 const VkImageSubresourceRange *range,
3049 VkImageAspectFlags pending_clears)
3050 {
3051 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3052 if (image->fmask.size)
3053 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3054 else
3055 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3056 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3057 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3058 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3059 }
3060 }
3061
3062 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3063 struct radv_image *image, uint32_t value)
3064 {
3065
3066 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3067 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3068
3069 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3070 image->surface.dcc_size, value);
3071
3072 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3073 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3074 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3075 RADV_CMD_FLAG_INV_VMEM_L1 |
3076 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3077 }
3078
3079 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3080 struct radv_image *image,
3081 VkImageLayout src_layout,
3082 VkImageLayout dst_layout,
3083 unsigned src_queue_mask,
3084 unsigned dst_queue_mask,
3085 const VkImageSubresourceRange *range,
3086 VkImageAspectFlags pending_clears)
3087 {
3088 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3089 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3090 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3091 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3092 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3093 }
3094 }
3095
3096 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3097 struct radv_image *image,
3098 VkImageLayout src_layout,
3099 VkImageLayout dst_layout,
3100 uint32_t src_family,
3101 uint32_t dst_family,
3102 const VkImageSubresourceRange *range,
3103 VkImageAspectFlags pending_clears)
3104 {
3105 if (image->exclusive && src_family != dst_family) {
3106 /* This is an acquire or a release operation and there will be
3107 * a corresponding release/acquire. Do the transition in the
3108 * most flexible queue. */
3109
3110 assert(src_family == cmd_buffer->queue_family_index ||
3111 dst_family == cmd_buffer->queue_family_index);
3112
3113 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3114 return;
3115
3116 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3117 (src_family == RADV_QUEUE_GENERAL ||
3118 dst_family == RADV_QUEUE_GENERAL))
3119 return;
3120 }
3121
3122 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3123 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3124
3125 if (image->surface.htile_size)
3126 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3127 dst_layout, range, pending_clears);
3128
3129 if (image->cmask.size)
3130 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3131 dst_layout, src_queue_mask,
3132 dst_queue_mask, range,
3133 pending_clears);
3134
3135 if (image->surface.dcc_size)
3136 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3137 dst_layout, src_queue_mask,
3138 dst_queue_mask, range,
3139 pending_clears);
3140 }
3141
3142 void radv_CmdPipelineBarrier(
3143 VkCommandBuffer commandBuffer,
3144 VkPipelineStageFlags srcStageMask,
3145 VkPipelineStageFlags destStageMask,
3146 VkBool32 byRegion,
3147 uint32_t memoryBarrierCount,
3148 const VkMemoryBarrier* pMemoryBarriers,
3149 uint32_t bufferMemoryBarrierCount,
3150 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3151 uint32_t imageMemoryBarrierCount,
3152 const VkImageMemoryBarrier* pImageMemoryBarriers)
3153 {
3154 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3155 enum radv_cmd_flush_bits src_flush_bits = 0;
3156 enum radv_cmd_flush_bits dst_flush_bits = 0;
3157
3158 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3159 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3160 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3161 NULL);
3162 }
3163
3164 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3165 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3166 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3167 NULL);
3168 }
3169
3170 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3171 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3172 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3173 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3174 image);
3175 }
3176
3177 radv_stage_flush(cmd_buffer, srcStageMask);
3178 cmd_buffer->state.flush_bits |= src_flush_bits;
3179
3180 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3181 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3182 radv_handle_image_transition(cmd_buffer, image,
3183 pImageMemoryBarriers[i].oldLayout,
3184 pImageMemoryBarriers[i].newLayout,
3185 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3186 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3187 &pImageMemoryBarriers[i].subresourceRange,
3188 0);
3189 }
3190
3191 cmd_buffer->state.flush_bits |= dst_flush_bits;
3192 }
3193
3194
3195 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3196 struct radv_event *event,
3197 VkPipelineStageFlags stageMask,
3198 unsigned value)
3199 {
3200 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3201 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3202
3203 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3204
3205 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
3206
3207 /* TODO: this is overkill. Probably should figure something out from
3208 * the stage mask. */
3209
3210 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
3211 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
3212 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
3213 EVENT_INDEX(5));
3214 radeon_emit(cs, va);
3215 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
3216 radeon_emit(cs, 2);
3217 radeon_emit(cs, 0);
3218 }
3219
3220 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
3221 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
3222 EVENT_INDEX(5));
3223 radeon_emit(cs, va);
3224 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
3225 radeon_emit(cs, value);
3226 radeon_emit(cs, 0);
3227
3228 assert(cmd_buffer->cs->cdw <= cdw_max);
3229 }
3230
3231 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3232 VkEvent _event,
3233 VkPipelineStageFlags stageMask)
3234 {
3235 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3236 RADV_FROM_HANDLE(radv_event, event, _event);
3237
3238 write_event(cmd_buffer, event, stageMask, 1);
3239 }
3240
3241 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3242 VkEvent _event,
3243 VkPipelineStageFlags stageMask)
3244 {
3245 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3246 RADV_FROM_HANDLE(radv_event, event, _event);
3247
3248 write_event(cmd_buffer, event, stageMask, 0);
3249 }
3250
3251 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3252 uint32_t eventCount,
3253 const VkEvent* pEvents,
3254 VkPipelineStageFlags srcStageMask,
3255 VkPipelineStageFlags dstStageMask,
3256 uint32_t memoryBarrierCount,
3257 const VkMemoryBarrier* pMemoryBarriers,
3258 uint32_t bufferMemoryBarrierCount,
3259 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3260 uint32_t imageMemoryBarrierCount,
3261 const VkImageMemoryBarrier* pImageMemoryBarriers)
3262 {
3263 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3264 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3265
3266 for (unsigned i = 0; i < eventCount; ++i) {
3267 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3268 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3269
3270 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3271
3272 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3273
3274 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
3275 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
3276 radeon_emit(cs, va);
3277 radeon_emit(cs, va >> 32);
3278 radeon_emit(cs, 1); /* reference value */
3279 radeon_emit(cs, 0xffffffff); /* mask */
3280 radeon_emit(cs, 4); /* poll interval */
3281
3282 assert(cmd_buffer->cs->cdw <= cdw_max);
3283 }
3284
3285
3286 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3287 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3288
3289 radv_handle_image_transition(cmd_buffer, image,
3290 pImageMemoryBarriers[i].oldLayout,
3291 pImageMemoryBarriers[i].newLayout,
3292 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3293 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3294 &pImageMemoryBarriers[i].subresourceRange,
3295 0);
3296 }
3297
3298 /* TODO: figure out how to do memory barriers without waiting */
3299 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3300 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3301 RADV_CMD_FLAG_INV_VMEM_L1 |
3302 RADV_CMD_FLAG_INV_SMEM_L1;
3303 }