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radv: Prevent Coverity warning
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 int src_family,
42 int dst_family,
43 VkImageSubresourceRange range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static bool
191 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
192 uint64_t min_needed)
193 {
194 uint64_t new_size;
195 struct radeon_winsys_bo *bo;
196 struct radv_cmd_buffer_upload *upload;
197 struct radv_device *device = cmd_buffer->device;
198
199 new_size = MAX2(min_needed, 16 * 1024);
200 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
201
202 bo = device->ws->buffer_create(device->ws,
203 new_size, 4096,
204 RADEON_DOMAIN_GTT,
205 RADEON_FLAG_CPU_ACCESS);
206
207 if (!bo) {
208 cmd_buffer->record_fail = true;
209 return false;
210 }
211
212 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
213 if (cmd_buffer->upload.upload_bo) {
214 upload = malloc(sizeof(*upload));
215
216 if (!upload) {
217 cmd_buffer->record_fail = true;
218 device->ws->buffer_destroy(bo);
219 return false;
220 }
221
222 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
223 list_add(&upload->list, &cmd_buffer->upload.list);
224 }
225
226 cmd_buffer->upload.upload_bo = bo;
227 cmd_buffer->upload.size = new_size;
228 cmd_buffer->upload.offset = 0;
229 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
230
231 if (!cmd_buffer->upload.map) {
232 cmd_buffer->record_fail = true;
233 return false;
234 }
235
236 return true;
237 }
238
239 bool
240 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
241 unsigned size,
242 unsigned alignment,
243 unsigned *out_offset,
244 void **ptr)
245 {
246 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
247 if (offset + size > cmd_buffer->upload.size) {
248 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
249 return false;
250 offset = 0;
251 }
252
253 *out_offset = offset;
254 *ptr = cmd_buffer->upload.map + offset;
255
256 cmd_buffer->upload.offset = offset + size;
257 return true;
258 }
259
260 bool
261 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
262 unsigned size, unsigned alignment,
263 const void *data, unsigned *out_offset)
264 {
265 uint8_t *ptr;
266
267 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
268 out_offset, (void **)&ptr))
269 return false;
270
271 if (ptr)
272 memcpy(ptr, data, size);
273
274 return true;
275 }
276
277 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
278 {
279 struct radv_device *device = cmd_buffer->device;
280 struct radeon_winsys_cs *cs = cmd_buffer->cs;
281 uint64_t va;
282
283 if (!device->trace_bo)
284 return;
285
286 va = device->ws->buffer_get_va(device->trace_bo);
287
288 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
289
290 ++cmd_buffer->state.trace_id;
291 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
292 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
293 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
294 S_370_WR_CONFIRM(1) |
295 S_370_ENGINE_SEL(V_370_ME));
296 radeon_emit(cs, va);
297 radeon_emit(cs, va >> 32);
298 radeon_emit(cs, cmd_buffer->state.trace_id);
299 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
300 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
301 }
302
303 static void
304 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
305 struct radv_pipeline *pipeline)
306 {
307 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
308 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
309 8);
310 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
311 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
312 }
313
314 static void
315 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
316 struct radv_pipeline *pipeline)
317 {
318 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
319 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
320 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
321
322 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
323 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
324 }
325
326 /* 12.4 fixed-point */
327 static unsigned radv_pack_float_12p4(float x)
328 {
329 return x <= 0 ? 0 :
330 x >= 4096 ? 0xffff : x * 16;
331 }
332
333 static uint32_t
334 shader_stage_to_user_data_0(gl_shader_stage stage)
335 {
336 switch (stage) {
337 case MESA_SHADER_FRAGMENT:
338 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
339 case MESA_SHADER_VERTEX:
340 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
341 case MESA_SHADER_COMPUTE:
342 return R_00B900_COMPUTE_USER_DATA_0;
343 default:
344 unreachable("unknown shader");
345 }
346 }
347
348 static struct ac_userdata_info *
349 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
350 gl_shader_stage stage,
351 int idx)
352 {
353 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
354 }
355
356 static void
357 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
358 struct radv_pipeline *pipeline,
359 gl_shader_stage stage,
360 int idx, uint64_t va)
361 {
362 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
363 uint32_t base_reg = shader_stage_to_user_data_0(stage);
364 if (loc->sgpr_idx == -1)
365 return;
366 assert(loc->num_sgprs == 2);
367 assert(!loc->indirect);
368 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
369 radeon_emit(cmd_buffer->cs, va);
370 radeon_emit(cmd_buffer->cs, va >> 32);
371 }
372
373 static void
374 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
375 struct radv_pipeline *pipeline)
376 {
377 int num_samples = pipeline->graphics.ms.num_samples;
378 struct radv_multisample_state *ms = &pipeline->graphics.ms;
379 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
380
381 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
382 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
383 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
384
385 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
386 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
387
388 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
389 return;
390
391 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
392 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
393 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
394
395 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
396
397 uint32_t samples_offset;
398 void *samples_ptr;
399 void *src;
400 radv_cmd_buffer_upload_alloc(cmd_buffer, num_samples * 4 * 2, 256, &samples_offset,
401 &samples_ptr);
402 switch (num_samples) {
403 case 1:
404 src = cmd_buffer->device->sample_locations_1x;
405 break;
406 case 2:
407 src = cmd_buffer->device->sample_locations_2x;
408 break;
409 case 4:
410 src = cmd_buffer->device->sample_locations_4x;
411 break;
412 case 8:
413 src = cmd_buffer->device->sample_locations_8x;
414 break;
415 case 16:
416 src = cmd_buffer->device->sample_locations_16x;
417 break;
418 default:
419 unreachable("unknown number of samples");
420 }
421 memcpy(samples_ptr, src, num_samples * 4 * 2);
422
423 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
424 va += samples_offset;
425
426 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
427 AC_UD_PS_SAMPLE_POS, va);
428 }
429
430 static void
431 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
432 struct radv_pipeline *pipeline)
433 {
434 struct radv_raster_state *raster = &pipeline->graphics.raster;
435
436 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
437 raster->pa_cl_clip_cntl);
438
439 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
440 raster->spi_interp_control);
441
442 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
443 unsigned tmp = (unsigned)(1.0 * 8.0);
444 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
445 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
446 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
447
448 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
449 raster->pa_su_vtx_cntl);
450
451 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
452 raster->pa_su_sc_mode_cntl);
453 }
454
455 static void
456 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
457 struct radv_pipeline *pipeline)
458 {
459 struct radeon_winsys *ws = cmd_buffer->device->ws;
460 struct radv_shader_variant *vs;
461 uint64_t va;
462 unsigned export_count;
463 unsigned clip_dist_mask, cull_dist_mask, total_mask;
464
465 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
466
467 vs = pipeline->shaders[MESA_SHADER_VERTEX];
468 va = ws->buffer_get_va(vs->bo);
469 ws->cs_add_buffer(cmd_buffer->cs, vs->bo, 8);
470
471 clip_dist_mask = vs->info.vs.clip_dist_mask;
472 cull_dist_mask = vs->info.vs.cull_dist_mask;
473 total_mask = clip_dist_mask | cull_dist_mask;
474 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, 0);
475 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
476
477 export_count = MAX2(1, vs->info.vs.param_exports);
478 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
479 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
480 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
481 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
482 S_02870C_POS1_EXPORT_FORMAT(vs->info.vs.pos_exports > 1 ?
483 V_02870C_SPI_SHADER_4COMP :
484 V_02870C_SPI_SHADER_NONE) |
485 S_02870C_POS2_EXPORT_FORMAT(vs->info.vs.pos_exports > 2 ?
486 V_02870C_SPI_SHADER_4COMP :
487 V_02870C_SPI_SHADER_NONE) |
488 S_02870C_POS3_EXPORT_FORMAT(vs->info.vs.pos_exports > 3 ?
489 V_02870C_SPI_SHADER_4COMP :
490 V_02870C_SPI_SHADER_NONE));
491
492 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
493 radeon_emit(cmd_buffer->cs, va >> 8);
494 radeon_emit(cmd_buffer->cs, va >> 40);
495 radeon_emit(cmd_buffer->cs, vs->rsrc1);
496 radeon_emit(cmd_buffer->cs, vs->rsrc2);
497
498 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
499 S_028818_VTX_W0_FMT(1) |
500 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
501 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
502 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
503
504 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
505 S_02881C_USE_VTX_POINT_SIZE(vs->info.vs.writes_pointsize) |
506 S_02881C_USE_VTX_RENDER_TARGET_INDX(vs->info.vs.writes_layer) |
507 S_02881C_USE_VTX_VIEWPORT_INDX(vs->info.vs.writes_viewport_index) |
508 S_02881C_VS_OUT_MISC_VEC_ENA(vs->info.vs.writes_pointsize ||
509 vs->info.vs.writes_layer ||
510 vs->info.vs.writes_viewport_index) |
511 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
512 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
513 pipeline->graphics.raster.pa_cl_vs_out_cntl |
514 cull_dist_mask << 8 |
515 clip_dist_mask);
516
517 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
518 S_028AB4_REUSE_OFF(vs->info.vs.writes_viewport_index));
519 }
520
521
522
523 static void
524 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
525 struct radv_pipeline *pipeline)
526 {
527 struct radeon_winsys *ws = cmd_buffer->device->ws;
528 struct radv_shader_variant *ps, *vs;
529 uint64_t va;
530 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
531 struct radv_blend_state *blend = &pipeline->graphics.blend;
532 unsigned ps_offset = 0;
533 unsigned z_order;
534 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
535
536 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
537 vs = pipeline->shaders[MESA_SHADER_VERTEX];
538 va = ws->buffer_get_va(ps->bo);
539 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
540
541 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
542 radeon_emit(cmd_buffer->cs, va >> 8);
543 radeon_emit(cmd_buffer->cs, va >> 40);
544 radeon_emit(cmd_buffer->cs, ps->rsrc1);
545 radeon_emit(cmd_buffer->cs, ps->rsrc2);
546
547 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
548 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
549 else
550 z_order = V_02880C_LATE_Z;
551
552
553 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
554 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
555 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
556 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
557 S_02880C_Z_ORDER(z_order) |
558 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
559 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
560 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory));
561
562 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
563 ps->config.spi_ps_input_ena);
564
565 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
566 ps->config.spi_ps_input_addr);
567
568 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(0);
569 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
570 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
571
572 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
573
574 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
575 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
576 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
577 V_028710_SPI_SHADER_ZERO);
578
579 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
580
581 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
582 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
583
584 if (ps->info.fs.has_pcoord) {
585 unsigned val;
586 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
587 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
588 ps_offset = 1;
589 }
590
591 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
592 unsigned vs_offset, flat_shade;
593 unsigned val;
594
595 if (!(ps->info.fs.input_mask & (1u << i)))
596 continue;
597
598
599 if (!(vs->info.vs.export_mask & (1u << i))) {
600 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset,
601 S_028644_OFFSET(0x20));
602 ++ps_offset;
603 continue;
604 }
605
606 vs_offset = util_bitcount(vs->info.vs.export_mask & ((1u << i) - 1));
607 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
608
609 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
610 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
611 ++ps_offset;
612 }
613 }
614
615 static void
616 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
617 struct radv_pipeline *pipeline)
618 {
619 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
620 return;
621
622 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
623 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
624 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
625 radv_update_multisample_state(cmd_buffer, pipeline);
626 radv_emit_vertex_shader(cmd_buffer, pipeline);
627 radv_emit_fragment_shader(cmd_buffer, pipeline);
628
629 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
630 pipeline->graphics.prim_restart_enable);
631
632 cmd_buffer->scratch_size_needed =
633 MAX2(cmd_buffer->scratch_size_needed,
634 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
635
636 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
637 S_0286E8_WAVES(pipeline->max_waves) |
638 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
639 cmd_buffer->state.emitted_pipeline = pipeline;
640 }
641
642 static void
643 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
644 {
645 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
646 cmd_buffer->state.dynamic.viewport.viewports);
647 }
648
649 static void
650 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
651 {
652 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
653 si_write_scissors(cmd_buffer->cs, 0, count,
654 cmd_buffer->state.dynamic.scissor.scissors);
655 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
656 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
657 }
658
659 static void
660 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
661 int index,
662 struct radv_color_buffer_info *cb)
663 {
664 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
665 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
666 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
667 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
668 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
669 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
670 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
671 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
672 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
673 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
674 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
675 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
676 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
677
678 if (is_vi) { /* DCC BASE */
679 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
680 }
681 }
682
683 static void
684 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
685 struct radv_ds_buffer_info *ds,
686 struct radv_image *image,
687 VkImageLayout layout)
688 {
689 uint32_t db_z_info = ds->db_z_info;
690
691 if (!radv_layout_has_htile(image, layout))
692 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
693
694 if (!radv_layout_can_expclear(image, layout))
695 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
696
697 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
698 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
699
700 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
701 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
702 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
703 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
704 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
705 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
706 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
707 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
708 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
709 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
710
711 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
712 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
713 ds->pa_su_poly_offset_db_fmt_cntl);
714 }
715
716 /*
717 * To hw resolve multisample images both src and dst need to have the same
718 * micro tiling mode. However we don't always know in advance when creating
719 * the images. This function gets called if we have a resolve attachment,
720 * and tests if the attachment image has the same tiling mode, then it
721 * checks if the generated framebuffer data has the same tiling mode, and
722 * updates it if not.
723 */
724 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
725 struct radv_attachment_info *att,
726 uint32_t micro_tile_mode)
727 {
728 struct radv_image *image = att->attachment->image;
729 uint32_t tile_mode_index;
730 if (image->surface.nsamples <= 1)
731 return;
732
733 if (image->surface.micro_tile_mode != micro_tile_mode) {
734 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
735 }
736
737 if (att->cb.micro_tile_mode != micro_tile_mode) {
738 tile_mode_index = image->surface.tiling_index[0];
739
740 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
741 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
742 att->cb.micro_tile_mode = micro_tile_mode;
743 }
744 }
745
746 void
747 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
748 struct radv_image *image,
749 VkClearDepthStencilValue ds_clear_value,
750 VkImageAspectFlags aspects)
751 {
752 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
753 va += image->offset + image->clear_value_offset;
754 unsigned reg_offset = 0, reg_count = 0;
755
756 if (!image->htile.size || !aspects)
757 return;
758
759 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
760 ++reg_count;
761 } else {
762 ++reg_offset;
763 va += 4;
764 }
765 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
766 ++reg_count;
767
768 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
769
770 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
771 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
772 S_370_WR_CONFIRM(1) |
773 S_370_ENGINE_SEL(V_370_PFP));
774 radeon_emit(cmd_buffer->cs, va);
775 radeon_emit(cmd_buffer->cs, va >> 32);
776 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
777 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
778 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
779 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
780
781 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
782 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
783 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
784 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
785 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
786 }
787
788 static void
789 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
790 struct radv_image *image)
791 {
792 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
793 va += image->offset + image->clear_value_offset;
794
795 if (!image->htile.size)
796 return;
797
798 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
799
800 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
801 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
802 COPY_DATA_DST_SEL(COPY_DATA_REG) |
803 COPY_DATA_COUNT_SEL);
804 radeon_emit(cmd_buffer->cs, va);
805 radeon_emit(cmd_buffer->cs, va >> 32);
806 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
807 radeon_emit(cmd_buffer->cs, 0);
808
809 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
810 radeon_emit(cmd_buffer->cs, 0);
811 }
812
813 void
814 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
815 struct radv_image *image,
816 int idx,
817 uint32_t color_values[2])
818 {
819 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
820 va += image->offset + image->clear_value_offset;
821
822 if (!image->cmask.size && !image->surface.dcc_size)
823 return;
824
825 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
826
827 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
828 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
829 S_370_WR_CONFIRM(1) |
830 S_370_ENGINE_SEL(V_370_PFP));
831 radeon_emit(cmd_buffer->cs, va);
832 radeon_emit(cmd_buffer->cs, va >> 32);
833 radeon_emit(cmd_buffer->cs, color_values[0]);
834 radeon_emit(cmd_buffer->cs, color_values[1]);
835
836 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
837 radeon_emit(cmd_buffer->cs, color_values[0]);
838 radeon_emit(cmd_buffer->cs, color_values[1]);
839 }
840
841 static void
842 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
843 struct radv_image *image,
844 int idx)
845 {
846 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
847 va += image->offset + image->clear_value_offset;
848
849 if (!image->cmask.size && !image->surface.dcc_size)
850 return;
851
852 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
853 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
854
855 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
856 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
857 COPY_DATA_DST_SEL(COPY_DATA_REG) |
858 COPY_DATA_COUNT_SEL);
859 radeon_emit(cmd_buffer->cs, va);
860 radeon_emit(cmd_buffer->cs, va >> 32);
861 radeon_emit(cmd_buffer->cs, reg >> 2);
862 radeon_emit(cmd_buffer->cs, 0);
863
864 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
865 radeon_emit(cmd_buffer->cs, 0);
866 }
867
868 void
869 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
870 {
871 int i;
872 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
873 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
874 int dst_resolve_micro_tile_mode = -1;
875
876 if (subpass->has_resolve) {
877 uint32_t a = subpass->resolve_attachments[0].attachment;
878 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
879 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
880 }
881 for (i = 0; i < subpass->color_count; ++i) {
882 int idx = subpass->color_attachments[i].attachment;
883 struct radv_attachment_info *att = &framebuffer->attachments[idx];
884
885 if (dst_resolve_micro_tile_mode != -1) {
886 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
887 att, dst_resolve_micro_tile_mode);
888 }
889 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
890
891 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
892 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
893
894 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
895 }
896
897 for (i = subpass->color_count; i < 8; i++)
898 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
899 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
900
901 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
902 int idx = subpass->depth_stencil_attachment.attachment;
903 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
904 struct radv_attachment_info *att = &framebuffer->attachments[idx];
905 struct radv_image *image = att->attachment->image;
906 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
907
908 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
909
910 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
911 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
912 cmd_buffer->state.offset_scale = att->ds.offset_scale;
913 }
914 radv_load_depth_clear_regs(cmd_buffer, image);
915 } else {
916 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
917 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
918 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
919 }
920 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
921 S_028208_BR_X(framebuffer->width) |
922 S_028208_BR_Y(framebuffer->height));
923 }
924
925 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
926 {
927 uint32_t db_count_control;
928
929 if(!cmd_buffer->state.active_occlusion_queries) {
930 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
931 db_count_control = 0;
932 } else {
933 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
934 }
935 } else {
936 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
937 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
938 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
939 S_028004_ZPASS_ENABLE(1) |
940 S_028004_SLICE_EVEN_ENABLE(1) |
941 S_028004_SLICE_ODD_ENABLE(1);
942 } else {
943 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
944 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
945 }
946 }
947
948 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
949 }
950
951 static void
952 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
953 {
954 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
955
956 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
957 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
958 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
959 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
960 }
961
962 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
963 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
964 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
965 }
966
967 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
968 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
969 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
970 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
971 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
972 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
973 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
974 S_028430_STENCILOPVAL(1));
975 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
976 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
977 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
978 S_028434_STENCILOPVAL_BF(1));
979 }
980
981 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
982 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
983 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
984 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
985 }
986
987 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
988 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
989 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
990 unsigned slope = fui(d->depth_bias.slope * 16.0f);
991 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
992
993 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
994 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
995 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
996 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
997 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
998 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
999 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1000 }
1001 }
1002
1003 cmd_buffer->state.dirty = 0;
1004 }
1005
1006 static void
1007 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1008 struct radv_pipeline *pipeline,
1009 int idx,
1010 uint64_t va,
1011 gl_shader_stage stage)
1012 {
1013 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1014 uint32_t base_reg = shader_stage_to_user_data_0(stage);
1015
1016 if (desc_set_loc->sgpr_idx == -1)
1017 return;
1018
1019 assert(!desc_set_loc->indirect);
1020 assert(desc_set_loc->num_sgprs == 2);
1021 radeon_set_sh_reg_seq(cmd_buffer->cs,
1022 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1023 radeon_emit(cmd_buffer->cs, va);
1024 radeon_emit(cmd_buffer->cs, va >> 32);
1025 }
1026
1027 static void
1028 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1029 struct radv_pipeline *pipeline,
1030 VkShaderStageFlags stages,
1031 struct radv_descriptor_set *set,
1032 unsigned idx)
1033 {
1034 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1035 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1036 idx, set->va,
1037 MESA_SHADER_FRAGMENT);
1038
1039 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1040 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1041 idx, set->va,
1042 MESA_SHADER_VERTEX);
1043
1044 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1045 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1046 idx, set->va,
1047 MESA_SHADER_COMPUTE);
1048 }
1049
1050 static void
1051 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1052 struct radv_pipeline *pipeline,
1053 VkShaderStageFlags stages)
1054 {
1055 unsigned i;
1056 if (!cmd_buffer->state.descriptors_dirty)
1057 return;
1058
1059 for (i = 0; i < MAX_SETS; i++) {
1060 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1061 continue;
1062 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1063 if (!set)
1064 continue;
1065
1066 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1067 }
1068 cmd_buffer->state.descriptors_dirty = 0;
1069 }
1070
1071 static void
1072 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1073 struct radv_pipeline *pipeline,
1074 VkShaderStageFlags stages)
1075 {
1076 struct radv_pipeline_layout *layout = pipeline->layout;
1077 unsigned offset;
1078 void *ptr;
1079 uint64_t va;
1080
1081 stages &= cmd_buffer->push_constant_stages;
1082 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1083 return;
1084
1085 radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1086 16 * layout->dynamic_offset_count,
1087 256, &offset, &ptr);
1088
1089 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1090 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1091 16 * layout->dynamic_offset_count);
1092
1093 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1094 va += offset;
1095
1096 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1097 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1098 AC_UD_PUSH_CONSTANTS, va);
1099
1100 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1101 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1102 AC_UD_PUSH_CONSTANTS, va);
1103
1104 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1105 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1106 AC_UD_PUSH_CONSTANTS, va);
1107
1108 cmd_buffer->push_constant_stages &= ~stages;
1109 }
1110
1111 static void
1112 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer)
1113 {
1114 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1115 struct radv_device *device = cmd_buffer->device;
1116 uint32_t ia_multi_vgt_param;
1117 uint32_t ls_hs_config = 0;
1118
1119 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1120 cmd_buffer->cs, 4096);
1121
1122 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1123 cmd_buffer->state.pipeline->num_vertex_attribs) {
1124 unsigned vb_offset;
1125 void *vb_ptr;
1126 uint32_t i = 0;
1127 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1128 uint64_t va;
1129
1130 /* allocate some descriptor state for vertex buffers */
1131 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1132 &vb_offset, &vb_ptr);
1133
1134 for (i = 0; i < num_attribs; i++) {
1135 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1136 uint32_t offset;
1137 int vb = cmd_buffer->state.pipeline->va_binding[i];
1138 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1139 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1140
1141 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1142 va = device->ws->buffer_get_va(buffer->bo);
1143
1144 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1145 va += offset + buffer->offset;
1146 desc[0] = va;
1147 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1148 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1149 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1150 else
1151 desc[2] = buffer->size - offset;
1152 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1153 }
1154
1155 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1156 va += vb_offset;
1157
1158 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1159 AC_UD_VS_VERTEX_BUFFERS, va);
1160 }
1161
1162 cmd_buffer->state.vertex_descriptors_dirty = false;
1163 cmd_buffer->state.vb_dirty = 0;
1164 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1165 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1166
1167 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1168 radv_emit_framebuffer_state(cmd_buffer);
1169
1170 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1171 radv_emit_viewport(cmd_buffer);
1172
1173 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR))
1174 radv_emit_scissor(cmd_buffer);
1175
1176 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1177 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, 0);
1178 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer);
1179
1180 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1181 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1182 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
1183 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1184 } else {
1185 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1186 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1187 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
1188 }
1189 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1190 }
1191
1192 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1193
1194 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1195 VK_SHADER_STAGE_ALL_GRAPHICS);
1196 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1197 VK_SHADER_STAGE_ALL_GRAPHICS);
1198
1199 assert(cmd_buffer->cs->cdw <= cdw_max);
1200
1201 si_emit_cache_flush(cmd_buffer);
1202 }
1203
1204 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1205 VkPipelineStageFlags src_stage_mask)
1206 {
1207 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1208 VK_PIPELINE_STAGE_TRANSFER_BIT |
1209 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1210 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1211 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1212 }
1213
1214 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1215 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1216 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1217 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1218 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1219 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1220 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1221 VK_PIPELINE_STAGE_TRANSFER_BIT |
1222 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1223 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1224 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1225 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1226 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1227 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1228 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1229 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1230 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1231 }
1232 }
1233
1234 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1235 {
1236 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1237
1238 /* TODO: actual cache flushes */
1239 }
1240
1241 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1242 VkAttachmentReference att)
1243 {
1244 unsigned idx = att.attachment;
1245 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1246 VkImageSubresourceRange range;
1247 range.aspectMask = 0;
1248 range.baseMipLevel = view->base_mip;
1249 range.levelCount = 1;
1250 range.baseArrayLayer = view->base_layer;
1251 range.layerCount = cmd_buffer->state.framebuffer->layers;
1252
1253 radv_handle_image_transition(cmd_buffer,
1254 view->image,
1255 cmd_buffer->state.attachments[idx].current_layout,
1256 att.layout, 0, 0, range,
1257 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1258
1259 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1260
1261
1262 }
1263
1264 void
1265 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1266 const struct radv_subpass *subpass, bool transitions)
1267 {
1268 if (transitions) {
1269 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1270
1271 for (unsigned i = 0; i < subpass->color_count; ++i) {
1272 radv_handle_subpass_image_transition(cmd_buffer,
1273 subpass->color_attachments[i]);
1274 }
1275
1276 for (unsigned i = 0; i < subpass->input_count; ++i) {
1277 radv_handle_subpass_image_transition(cmd_buffer,
1278 subpass->input_attachments[i]);
1279 }
1280
1281 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1282 radv_handle_subpass_image_transition(cmd_buffer,
1283 subpass->depth_stencil_attachment);
1284 }
1285 }
1286
1287 cmd_buffer->state.subpass = subpass;
1288
1289 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1290 }
1291
1292 static void
1293 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1294 struct radv_render_pass *pass,
1295 const VkRenderPassBeginInfo *info)
1296 {
1297 struct radv_cmd_state *state = &cmd_buffer->state;
1298
1299 if (pass->attachment_count == 0) {
1300 state->attachments = NULL;
1301 return;
1302 }
1303
1304 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1305 pass->attachment_count *
1306 sizeof(state->attachments[0]),
1307 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1308 if (state->attachments == NULL) {
1309 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1310 abort();
1311 }
1312
1313 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1314 struct radv_render_pass_attachment *att = &pass->attachments[i];
1315 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1316 VkImageAspectFlags clear_aspects = 0;
1317
1318 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1319 /* color attachment */
1320 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1321 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1322 }
1323 } else {
1324 /* depthstencil attachment */
1325 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1326 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1327 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1328 }
1329 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1330 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1331 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1332 }
1333 }
1334
1335 state->attachments[i].pending_clear_aspects = clear_aspects;
1336 if (clear_aspects && info) {
1337 assert(info->clearValueCount > i);
1338 state->attachments[i].clear_value = info->pClearValues[i];
1339 }
1340
1341 state->attachments[i].current_layout = att->initial_layout;
1342 }
1343 }
1344
1345 VkResult radv_AllocateCommandBuffers(
1346 VkDevice _device,
1347 const VkCommandBufferAllocateInfo *pAllocateInfo,
1348 VkCommandBuffer *pCommandBuffers)
1349 {
1350 RADV_FROM_HANDLE(radv_device, device, _device);
1351 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1352
1353 VkResult result = VK_SUCCESS;
1354 uint32_t i;
1355
1356 memset(pCommandBuffers, 0,
1357 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1358
1359 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1360 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1361 &pCommandBuffers[i]);
1362 if (result != VK_SUCCESS)
1363 break;
1364 }
1365
1366 if (result != VK_SUCCESS)
1367 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1368 i, pCommandBuffers);
1369
1370 return result;
1371 }
1372
1373 static void
1374 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
1375 {
1376 list_del(&cmd_buffer->pool_link);
1377
1378 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1379 &cmd_buffer->upload.list, list) {
1380 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1381 list_del(&up->list);
1382 free(up);
1383 }
1384
1385 if (cmd_buffer->upload.upload_bo)
1386 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
1387 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
1388 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1389 }
1390
1391 void radv_FreeCommandBuffers(
1392 VkDevice device,
1393 VkCommandPool commandPool,
1394 uint32_t commandBufferCount,
1395 const VkCommandBuffer *pCommandBuffers)
1396 {
1397 for (uint32_t i = 0; i < commandBufferCount; i++) {
1398 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1399
1400 if (cmd_buffer)
1401 radv_cmd_buffer_destroy(cmd_buffer);
1402 }
1403 }
1404
1405 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
1406 {
1407
1408 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
1409
1410 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1411 &cmd_buffer->upload.list, list) {
1412 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1413 list_del(&up->list);
1414 free(up);
1415 }
1416
1417 cmd_buffer->scratch_size_needed = 0;
1418 cmd_buffer->compute_scratch_size_needed = 0;
1419 if (cmd_buffer->upload.upload_bo)
1420 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
1421 cmd_buffer->upload.upload_bo, 8);
1422 cmd_buffer->upload.offset = 0;
1423
1424 cmd_buffer->record_fail = false;
1425 }
1426
1427 VkResult radv_ResetCommandBuffer(
1428 VkCommandBuffer commandBuffer,
1429 VkCommandBufferResetFlags flags)
1430 {
1431 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1432 radv_reset_cmd_buffer(cmd_buffer);
1433 return VK_SUCCESS;
1434 }
1435
1436 VkResult radv_BeginCommandBuffer(
1437 VkCommandBuffer commandBuffer,
1438 const VkCommandBufferBeginInfo *pBeginInfo)
1439 {
1440 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1441 radv_reset_cmd_buffer(cmd_buffer);
1442
1443 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1444
1445 /* setup initial configuration into command buffer */
1446 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1447 switch (cmd_buffer->queue_family_index) {
1448 case RADV_QUEUE_GENERAL:
1449 /* Flush read caches at the beginning of CS not flushed by the kernel. */
1450 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_ICACHE |
1451 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1452 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1453 RADV_CMD_FLAG_INV_VMEM_L1 |
1454 RADV_CMD_FLAG_INV_SMEM_L1 |
1455 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
1456 RADV_CMD_FLAG_INV_GLOBAL_L2;
1457 si_init_config(cmd_buffer->device->physical_device, cmd_buffer);
1458 radv_set_db_count_control(cmd_buffer);
1459 si_emit_cache_flush(cmd_buffer);
1460 break;
1461 case RADV_QUEUE_COMPUTE:
1462 cmd_buffer->state.flush_bits = RADV_CMD_FLAG_INV_ICACHE |
1463 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1464 RADV_CMD_FLAG_INV_VMEM_L1 |
1465 RADV_CMD_FLAG_INV_SMEM_L1 |
1466 RADV_CMD_FLAG_INV_GLOBAL_L2;
1467 si_init_compute(cmd_buffer->device->physical_device, cmd_buffer);
1468 si_emit_cache_flush(cmd_buffer);
1469 break;
1470 case RADV_QUEUE_TRANSFER:
1471 default:
1472 break;
1473 }
1474 }
1475
1476 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1477 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1478 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1479
1480 struct radv_subpass *subpass =
1481 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1482
1483 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1484 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1485 }
1486
1487 return VK_SUCCESS;
1488 }
1489
1490 void radv_CmdBindVertexBuffers(
1491 VkCommandBuffer commandBuffer,
1492 uint32_t firstBinding,
1493 uint32_t bindingCount,
1494 const VkBuffer* pBuffers,
1495 const VkDeviceSize* pOffsets)
1496 {
1497 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1498 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1499
1500 /* We have to defer setting up vertex buffer since we need the buffer
1501 * stride from the pipeline. */
1502
1503 assert(firstBinding + bindingCount < MAX_VBS);
1504 for (uint32_t i = 0; i < bindingCount; i++) {
1505 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1506 vb[firstBinding + i].offset = pOffsets[i];
1507 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1508 }
1509 }
1510
1511 void radv_CmdBindIndexBuffer(
1512 VkCommandBuffer commandBuffer,
1513 VkBuffer buffer,
1514 VkDeviceSize offset,
1515 VkIndexType indexType)
1516 {
1517 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1518
1519 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1520 cmd_buffer->state.index_offset = offset;
1521 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1522 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1523 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1524 }
1525
1526
1527 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1528 struct radv_descriptor_set *set,
1529 unsigned idx)
1530 {
1531 struct radeon_winsys *ws = cmd_buffer->device->ws;
1532
1533 cmd_buffer->state.descriptors[idx] = set;
1534 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1535 if (!set)
1536 return;
1537
1538 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1539 if (set->descriptors[j])
1540 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1541
1542 if(set->bo)
1543 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1544 }
1545
1546 void radv_CmdBindDescriptorSets(
1547 VkCommandBuffer commandBuffer,
1548 VkPipelineBindPoint pipelineBindPoint,
1549 VkPipelineLayout _layout,
1550 uint32_t firstSet,
1551 uint32_t descriptorSetCount,
1552 const VkDescriptorSet* pDescriptorSets,
1553 uint32_t dynamicOffsetCount,
1554 const uint32_t* pDynamicOffsets)
1555 {
1556 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1557 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1558 unsigned dyn_idx = 0;
1559
1560 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1561 cmd_buffer->cs, MAX_SETS * 4 * 6);
1562
1563 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1564 unsigned idx = i + firstSet;
1565 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1566 radv_bind_descriptor_set(cmd_buffer, set, idx);
1567
1568 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1569 unsigned idx = j + layout->set[i].dynamic_offset_start;
1570 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1571 assert(dyn_idx < dynamicOffsetCount);
1572
1573 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1574 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1575 dst[0] = va;
1576 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1577 dst[2] = range->size;
1578 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1579 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1580 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1581 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1582 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1583 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1584 cmd_buffer->push_constant_stages |=
1585 set->layout->dynamic_shader_stages;
1586 }
1587 }
1588
1589 assert(cmd_buffer->cs->cdw <= cdw_max);
1590 }
1591
1592 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1593 VkPipelineLayout layout,
1594 VkShaderStageFlags stageFlags,
1595 uint32_t offset,
1596 uint32_t size,
1597 const void* pValues)
1598 {
1599 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1600 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1601 cmd_buffer->push_constant_stages |= stageFlags;
1602 }
1603
1604 VkResult radv_EndCommandBuffer(
1605 VkCommandBuffer commandBuffer)
1606 {
1607 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1608
1609 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
1610 si_emit_cache_flush(cmd_buffer);
1611 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1612 cmd_buffer->record_fail)
1613 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1614 return VK_SUCCESS;
1615 }
1616
1617 static void
1618 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1619 {
1620 struct radeon_winsys *ws = cmd_buffer->device->ws;
1621 struct radv_shader_variant *compute_shader;
1622 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1623 uint64_t va;
1624
1625 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1626 return;
1627
1628 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1629
1630 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1631 va = ws->buffer_get_va(compute_shader->bo);
1632
1633 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1634
1635 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1636 cmd_buffer->cs, 16);
1637
1638 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1639 radeon_emit(cmd_buffer->cs, va >> 8);
1640 radeon_emit(cmd_buffer->cs, va >> 40);
1641
1642 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1643 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1644 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1645
1646
1647 cmd_buffer->compute_scratch_size_needed =
1648 MAX2(cmd_buffer->compute_scratch_size_needed,
1649 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1650
1651 /* change these once we have scratch support */
1652 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1653 S_00B860_WAVES(pipeline->max_waves) |
1654 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1655
1656 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1657 radeon_emit(cmd_buffer->cs,
1658 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1659 radeon_emit(cmd_buffer->cs,
1660 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1661 radeon_emit(cmd_buffer->cs,
1662 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1663
1664 assert(cmd_buffer->cs->cdw <= cdw_max);
1665 }
1666
1667
1668 void radv_CmdBindPipeline(
1669 VkCommandBuffer commandBuffer,
1670 VkPipelineBindPoint pipelineBindPoint,
1671 VkPipeline _pipeline)
1672 {
1673 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1674 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1675
1676 for (unsigned i = 0; i < MAX_SETS; i++) {
1677 if (cmd_buffer->state.descriptors[i])
1678 cmd_buffer->state.descriptors_dirty |= (1 << i);
1679 }
1680
1681 switch (pipelineBindPoint) {
1682 case VK_PIPELINE_BIND_POINT_COMPUTE:
1683 cmd_buffer->state.compute_pipeline = pipeline;
1684 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
1685 break;
1686 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1687 cmd_buffer->state.pipeline = pipeline;
1688 cmd_buffer->state.vertex_descriptors_dirty = true;
1689 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1690 cmd_buffer->push_constant_stages |= pipeline->active_stages;
1691
1692 /* Apply the dynamic state from the pipeline */
1693 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
1694 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
1695 &pipeline->dynamic_state,
1696 pipeline->dynamic_state_mask);
1697 break;
1698 default:
1699 assert(!"invalid bind point");
1700 break;
1701 }
1702 }
1703
1704 void radv_CmdSetViewport(
1705 VkCommandBuffer commandBuffer,
1706 uint32_t firstViewport,
1707 uint32_t viewportCount,
1708 const VkViewport* pViewports)
1709 {
1710 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1711
1712 const uint32_t total_count = firstViewport + viewportCount;
1713 if (cmd_buffer->state.dynamic.viewport.count < total_count)
1714 cmd_buffer->state.dynamic.viewport.count = total_count;
1715
1716 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
1717 pViewports, viewportCount * sizeof(*pViewports));
1718
1719 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
1720 }
1721
1722 void radv_CmdSetScissor(
1723 VkCommandBuffer commandBuffer,
1724 uint32_t firstScissor,
1725 uint32_t scissorCount,
1726 const VkRect2D* pScissors)
1727 {
1728 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1729
1730 const uint32_t total_count = firstScissor + scissorCount;
1731 if (cmd_buffer->state.dynamic.scissor.count < total_count)
1732 cmd_buffer->state.dynamic.scissor.count = total_count;
1733
1734 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
1735 pScissors, scissorCount * sizeof(*pScissors));
1736 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1737 }
1738
1739 void radv_CmdSetLineWidth(
1740 VkCommandBuffer commandBuffer,
1741 float lineWidth)
1742 {
1743 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1744 cmd_buffer->state.dynamic.line_width = lineWidth;
1745 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1746 }
1747
1748 void radv_CmdSetDepthBias(
1749 VkCommandBuffer commandBuffer,
1750 float depthBiasConstantFactor,
1751 float depthBiasClamp,
1752 float depthBiasSlopeFactor)
1753 {
1754 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1755
1756 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
1757 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
1758 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
1759
1760 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1761 }
1762
1763 void radv_CmdSetBlendConstants(
1764 VkCommandBuffer commandBuffer,
1765 const float blendConstants[4])
1766 {
1767 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1768
1769 memcpy(cmd_buffer->state.dynamic.blend_constants,
1770 blendConstants, sizeof(float) * 4);
1771
1772 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
1773 }
1774
1775 void radv_CmdSetDepthBounds(
1776 VkCommandBuffer commandBuffer,
1777 float minDepthBounds,
1778 float maxDepthBounds)
1779 {
1780 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1781
1782 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
1783 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
1784
1785 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
1786 }
1787
1788 void radv_CmdSetStencilCompareMask(
1789 VkCommandBuffer commandBuffer,
1790 VkStencilFaceFlags faceMask,
1791 uint32_t compareMask)
1792 {
1793 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1794
1795 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1796 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
1797 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1798 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
1799
1800 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1801 }
1802
1803 void radv_CmdSetStencilWriteMask(
1804 VkCommandBuffer commandBuffer,
1805 VkStencilFaceFlags faceMask,
1806 uint32_t writeMask)
1807 {
1808 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1809
1810 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1811 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
1812 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1813 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
1814
1815 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1816 }
1817
1818 void radv_CmdSetStencilReference(
1819 VkCommandBuffer commandBuffer,
1820 VkStencilFaceFlags faceMask,
1821 uint32_t reference)
1822 {
1823 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1824
1825 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1826 cmd_buffer->state.dynamic.stencil_reference.front = reference;
1827 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1828 cmd_buffer->state.dynamic.stencil_reference.back = reference;
1829
1830 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1831 }
1832
1833
1834 void radv_CmdExecuteCommands(
1835 VkCommandBuffer commandBuffer,
1836 uint32_t commandBufferCount,
1837 const VkCommandBuffer* pCmdBuffers)
1838 {
1839 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
1840
1841 for (uint32_t i = 0; i < commandBufferCount; i++) {
1842 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
1843
1844 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
1845 secondary->scratch_size_needed);
1846 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
1847 secondary->compute_scratch_size_needed);
1848
1849 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
1850 }
1851
1852 /* if we execute secondary we need to re-emit out pipelines */
1853 if (commandBufferCount) {
1854 primary->state.emitted_pipeline = NULL;
1855 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1856 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
1857 }
1858 }
1859
1860 VkResult radv_CreateCommandPool(
1861 VkDevice _device,
1862 const VkCommandPoolCreateInfo* pCreateInfo,
1863 const VkAllocationCallbacks* pAllocator,
1864 VkCommandPool* pCmdPool)
1865 {
1866 RADV_FROM_HANDLE(radv_device, device, _device);
1867 struct radv_cmd_pool *pool;
1868
1869 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
1870 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1871 if (pool == NULL)
1872 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1873
1874 if (pAllocator)
1875 pool->alloc = *pAllocator;
1876 else
1877 pool->alloc = device->alloc;
1878
1879 list_inithead(&pool->cmd_buffers);
1880
1881 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
1882
1883 *pCmdPool = radv_cmd_pool_to_handle(pool);
1884
1885 return VK_SUCCESS;
1886
1887 }
1888
1889 void radv_DestroyCommandPool(
1890 VkDevice _device,
1891 VkCommandPool commandPool,
1892 const VkAllocationCallbacks* pAllocator)
1893 {
1894 RADV_FROM_HANDLE(radv_device, device, _device);
1895 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
1896
1897 if (!pool)
1898 return;
1899
1900 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
1901 &pool->cmd_buffers, pool_link) {
1902 radv_cmd_buffer_destroy(cmd_buffer);
1903 }
1904
1905 vk_free2(&device->alloc, pAllocator, pool);
1906 }
1907
1908 VkResult radv_ResetCommandPool(
1909 VkDevice device,
1910 VkCommandPool commandPool,
1911 VkCommandPoolResetFlags flags)
1912 {
1913 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
1914
1915 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
1916 &pool->cmd_buffers, pool_link) {
1917 radv_reset_cmd_buffer(cmd_buffer);
1918 }
1919
1920 return VK_SUCCESS;
1921 }
1922
1923 void radv_TrimCommandPoolKHR(
1924 VkDevice device,
1925 VkCommandPool commandPool,
1926 VkCommandPoolTrimFlagsKHR flags)
1927 {
1928 }
1929
1930 void radv_CmdBeginRenderPass(
1931 VkCommandBuffer commandBuffer,
1932 const VkRenderPassBeginInfo* pRenderPassBegin,
1933 VkSubpassContents contents)
1934 {
1935 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1936 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
1937 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
1938
1939 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1940 cmd_buffer->cs, 2048);
1941
1942 cmd_buffer->state.framebuffer = framebuffer;
1943 cmd_buffer->state.pass = pass;
1944 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
1945 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
1946
1947 si_emit_cache_flush(cmd_buffer);
1948
1949 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
1950 assert(cmd_buffer->cs->cdw <= cdw_max);
1951
1952 radv_cmd_buffer_clear_subpass(cmd_buffer);
1953 }
1954
1955 void radv_CmdNextSubpass(
1956 VkCommandBuffer commandBuffer,
1957 VkSubpassContents contents)
1958 {
1959 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1960
1961 si_emit_cache_flush(cmd_buffer);
1962 radv_cmd_buffer_resolve_subpass(cmd_buffer);
1963
1964 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
1965 2048);
1966
1967 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
1968 radv_cmd_buffer_clear_subpass(cmd_buffer);
1969 }
1970
1971 void radv_CmdDraw(
1972 VkCommandBuffer commandBuffer,
1973 uint32_t vertexCount,
1974 uint32_t instanceCount,
1975 uint32_t firstVertex,
1976 uint32_t firstInstance)
1977 {
1978 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1979 radv_cmd_buffer_flush_state(cmd_buffer);
1980
1981 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1982
1983 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1984 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
1985 if (loc->sgpr_idx != -1) {
1986 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4, 2);
1987 radeon_emit(cmd_buffer->cs, firstVertex);
1988 radeon_emit(cmd_buffer->cs, firstInstance);
1989 }
1990 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
1991 radeon_emit(cmd_buffer->cs, instanceCount);
1992
1993 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
1994 radeon_emit(cmd_buffer->cs, vertexCount);
1995 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1996 S_0287F0_USE_OPAQUE(0));
1997
1998 assert(cmd_buffer->cs->cdw <= cdw_max);
1999
2000 radv_cmd_buffer_trace_emit(cmd_buffer);
2001 }
2002
2003 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2004 {
2005 uint32_t primitive_reset_index = cmd_buffer->state.last_primitive_reset_index ? 0xffffffffu : 0xffffu;
2006
2007 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
2008 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
2009 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
2010 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2011 primitive_reset_index);
2012 }
2013 }
2014
2015 void radv_CmdDrawIndexed(
2016 VkCommandBuffer commandBuffer,
2017 uint32_t indexCount,
2018 uint32_t instanceCount,
2019 uint32_t firstIndex,
2020 int32_t vertexOffset,
2021 uint32_t firstInstance)
2022 {
2023 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2024 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2025 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2026 uint64_t index_va;
2027
2028 radv_cmd_buffer_flush_state(cmd_buffer);
2029 radv_emit_primitive_reset_index(cmd_buffer);
2030
2031 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 14);
2032
2033 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2034 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2035
2036 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2037 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2038 if (loc->sgpr_idx != -1) {
2039 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4, 2);
2040 radeon_emit(cmd_buffer->cs, vertexOffset);
2041 radeon_emit(cmd_buffer->cs, firstInstance);
2042 }
2043 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2044 radeon_emit(cmd_buffer->cs, instanceCount);
2045
2046 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2047 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2048 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2049 radeon_emit(cmd_buffer->cs, index_max_size);
2050 radeon_emit(cmd_buffer->cs, index_va);
2051 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2052 radeon_emit(cmd_buffer->cs, indexCount);
2053 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2054
2055 assert(cmd_buffer->cs->cdw <= cdw_max);
2056 radv_cmd_buffer_trace_emit(cmd_buffer);
2057 }
2058
2059 static void
2060 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2061 VkBuffer _buffer,
2062 VkDeviceSize offset,
2063 VkBuffer _count_buffer,
2064 VkDeviceSize count_offset,
2065 uint32_t draw_count,
2066 uint32_t stride,
2067 bool indexed)
2068 {
2069 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2070 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2071 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2072 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2073 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2074 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2075 indirect_va += offset + buffer->offset;
2076 uint64_t count_va = 0;
2077
2078 if (count_buffer) {
2079 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2080 count_va += count_offset + count_buffer->offset;
2081 }
2082
2083 if (!draw_count)
2084 return;
2085
2086 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2087
2088 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2089 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2090 assert(loc->sgpr_idx != -1);
2091 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2092 radeon_emit(cs, 1);
2093 radeon_emit(cs, indirect_va);
2094 radeon_emit(cs, indirect_va >> 32);
2095
2096 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2097 PKT3_DRAW_INDIRECT_MULTI,
2098 8, false));
2099 radeon_emit(cs, 0);
2100 radeon_emit(cs, ((R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2101 radeon_emit(cs, ((R_00B130_SPI_SHADER_USER_DATA_VS_0 + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2102 radeon_emit(cs, S_2C3_COUNT_INDIRECT_ENABLE(!!count_va)); /* draw_index and count_indirect enable */
2103 radeon_emit(cs, draw_count); /* count */
2104 radeon_emit(cs, count_va); /* count_addr */
2105 radeon_emit(cs, count_va >> 32);
2106 radeon_emit(cs, stride); /* stride */
2107 radeon_emit(cs, di_src_sel);
2108 radv_cmd_buffer_trace_emit(cmd_buffer);
2109 }
2110
2111 static void
2112 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2113 VkBuffer buffer,
2114 VkDeviceSize offset,
2115 VkBuffer countBuffer,
2116 VkDeviceSize countBufferOffset,
2117 uint32_t maxDrawCount,
2118 uint32_t stride)
2119 {
2120 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2121 radv_cmd_buffer_flush_state(cmd_buffer);
2122
2123 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2124 cmd_buffer->cs, 14);
2125
2126 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2127 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2128
2129 assert(cmd_buffer->cs->cdw <= cdw_max);
2130 }
2131
2132 static void
2133 radv_cmd_draw_indexed_indirect_count(
2134 VkCommandBuffer commandBuffer,
2135 VkBuffer buffer,
2136 VkDeviceSize offset,
2137 VkBuffer countBuffer,
2138 VkDeviceSize countBufferOffset,
2139 uint32_t maxDrawCount,
2140 uint32_t stride)
2141 {
2142 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2143 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2144 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2145 uint64_t index_va;
2146 radv_cmd_buffer_flush_state(cmd_buffer);
2147 radv_emit_primitive_reset_index(cmd_buffer);
2148
2149 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2150 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2151
2152 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2153
2154 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2155 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2156
2157 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2158 radeon_emit(cmd_buffer->cs, index_va);
2159 radeon_emit(cmd_buffer->cs, index_va >> 32);
2160
2161 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2162 radeon_emit(cmd_buffer->cs, index_max_size);
2163
2164 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2165 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2166
2167 assert(cmd_buffer->cs->cdw <= cdw_max);
2168 }
2169
2170 void radv_CmdDrawIndirect(
2171 VkCommandBuffer commandBuffer,
2172 VkBuffer buffer,
2173 VkDeviceSize offset,
2174 uint32_t drawCount,
2175 uint32_t stride)
2176 {
2177 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2178 VK_NULL_HANDLE, 0, drawCount, stride);
2179 }
2180
2181 void radv_CmdDrawIndexedIndirect(
2182 VkCommandBuffer commandBuffer,
2183 VkBuffer buffer,
2184 VkDeviceSize offset,
2185 uint32_t drawCount,
2186 uint32_t stride)
2187 {
2188 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2189 VK_NULL_HANDLE, 0, drawCount, stride);
2190 }
2191
2192 void radv_CmdDrawIndirectCountAMD(
2193 VkCommandBuffer commandBuffer,
2194 VkBuffer buffer,
2195 VkDeviceSize offset,
2196 VkBuffer countBuffer,
2197 VkDeviceSize countBufferOffset,
2198 uint32_t maxDrawCount,
2199 uint32_t stride)
2200 {
2201 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2202 countBuffer, countBufferOffset,
2203 maxDrawCount, stride);
2204 }
2205
2206 void radv_CmdDrawIndexedIndirectCountAMD(
2207 VkCommandBuffer commandBuffer,
2208 VkBuffer buffer,
2209 VkDeviceSize offset,
2210 VkBuffer countBuffer,
2211 VkDeviceSize countBufferOffset,
2212 uint32_t maxDrawCount,
2213 uint32_t stride)
2214 {
2215 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2216 countBuffer, countBufferOffset,
2217 maxDrawCount, stride);
2218 }
2219
2220 static void
2221 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2222 {
2223 radv_emit_compute_pipeline(cmd_buffer);
2224 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2225 VK_SHADER_STAGE_COMPUTE_BIT);
2226 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2227 VK_SHADER_STAGE_COMPUTE_BIT);
2228 si_emit_cache_flush(cmd_buffer);
2229 }
2230
2231 void radv_CmdDispatch(
2232 VkCommandBuffer commandBuffer,
2233 uint32_t x,
2234 uint32_t y,
2235 uint32_t z)
2236 {
2237 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2238
2239 radv_flush_compute_state(cmd_buffer);
2240
2241 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2242
2243 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2244 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2245 if (loc->sgpr_idx != -1) {
2246 assert(!loc->indirect);
2247 assert(loc->num_sgprs == 3);
2248 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2249 radeon_emit(cmd_buffer->cs, x);
2250 radeon_emit(cmd_buffer->cs, y);
2251 radeon_emit(cmd_buffer->cs, z);
2252 }
2253
2254 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2255 PKT3_SHADER_TYPE_S(1));
2256 radeon_emit(cmd_buffer->cs, x);
2257 radeon_emit(cmd_buffer->cs, y);
2258 radeon_emit(cmd_buffer->cs, z);
2259 radeon_emit(cmd_buffer->cs, 1);
2260
2261 assert(cmd_buffer->cs->cdw <= cdw_max);
2262 radv_cmd_buffer_trace_emit(cmd_buffer);
2263 }
2264
2265 void radv_CmdDispatchIndirect(
2266 VkCommandBuffer commandBuffer,
2267 VkBuffer _buffer,
2268 VkDeviceSize offset)
2269 {
2270 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2271 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2272 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2273 va += buffer->offset + offset;
2274
2275 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2276
2277 radv_flush_compute_state(cmd_buffer);
2278
2279 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2280 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2281 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2282 if (loc->sgpr_idx != -1) {
2283 for (unsigned i = 0; i < 3; ++i) {
2284 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2285 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2286 COPY_DATA_DST_SEL(COPY_DATA_REG));
2287 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2288 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2289 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2290 radeon_emit(cmd_buffer->cs, 0);
2291 }
2292 }
2293
2294 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2295 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2296 PKT3_SHADER_TYPE_S(1));
2297 radeon_emit(cmd_buffer->cs, va);
2298 radeon_emit(cmd_buffer->cs, va >> 32);
2299 radeon_emit(cmd_buffer->cs, 1);
2300 } else {
2301 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2302 PKT3_SHADER_TYPE_S(1));
2303 radeon_emit(cmd_buffer->cs, 1);
2304 radeon_emit(cmd_buffer->cs, va);
2305 radeon_emit(cmd_buffer->cs, va >> 32);
2306
2307 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2308 PKT3_SHADER_TYPE_S(1));
2309 radeon_emit(cmd_buffer->cs, 0);
2310 radeon_emit(cmd_buffer->cs, 1);
2311 }
2312
2313 assert(cmd_buffer->cs->cdw <= cdw_max);
2314 radv_cmd_buffer_trace_emit(cmd_buffer);
2315 }
2316
2317 void radv_unaligned_dispatch(
2318 struct radv_cmd_buffer *cmd_buffer,
2319 uint32_t x,
2320 uint32_t y,
2321 uint32_t z)
2322 {
2323 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2324 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2325 uint32_t blocks[3], remainder[3];
2326
2327 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2328 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2329 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2330
2331 /* If aligned, these should be an entire block size, not 0 */
2332 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2333 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2334 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2335
2336 radv_flush_compute_state(cmd_buffer);
2337
2338 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2339
2340 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2341 radeon_emit(cmd_buffer->cs,
2342 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2343 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2344 radeon_emit(cmd_buffer->cs,
2345 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2346 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2347 radeon_emit(cmd_buffer->cs,
2348 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2349 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2350
2351 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2352 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2353 if (loc->sgpr_idx != -1) {
2354 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2355 radeon_emit(cmd_buffer->cs, blocks[0]);
2356 radeon_emit(cmd_buffer->cs, blocks[1]);
2357 radeon_emit(cmd_buffer->cs, blocks[2]);
2358 }
2359 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2360 PKT3_SHADER_TYPE_S(1));
2361 radeon_emit(cmd_buffer->cs, blocks[0]);
2362 radeon_emit(cmd_buffer->cs, blocks[1]);
2363 radeon_emit(cmd_buffer->cs, blocks[2]);
2364 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2365 S_00B800_PARTIAL_TG_EN(1));
2366
2367 assert(cmd_buffer->cs->cdw <= cdw_max);
2368 radv_cmd_buffer_trace_emit(cmd_buffer);
2369 }
2370
2371 void radv_CmdEndRenderPass(
2372 VkCommandBuffer commandBuffer)
2373 {
2374 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2375
2376 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2377
2378 si_emit_cache_flush(cmd_buffer);
2379 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2380
2381 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2382 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2383 radv_handle_subpass_image_transition(cmd_buffer,
2384 (VkAttachmentReference){i, layout});
2385 }
2386
2387 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2388
2389 cmd_buffer->state.pass = NULL;
2390 cmd_buffer->state.subpass = NULL;
2391 cmd_buffer->state.attachments = NULL;
2392 cmd_buffer->state.framebuffer = NULL;
2393 }
2394
2395
2396 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2397 struct radv_image *image)
2398 {
2399
2400 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2401 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2402
2403 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->htile.offset,
2404 image->htile.size, 0xffffffff);
2405
2406 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2407 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2408 RADV_CMD_FLAG_INV_VMEM_L1 |
2409 RADV_CMD_FLAG_INV_GLOBAL_L2;
2410 }
2411
2412 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2413 struct radv_image *image,
2414 VkImageLayout src_layout,
2415 VkImageLayout dst_layout,
2416 VkImageSubresourceRange range,
2417 VkImageAspectFlags pending_clears)
2418 {
2419 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2420 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2421 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2422 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2423 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2424 /* The clear will initialize htile. */
2425 return;
2426 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2427 radv_layout_has_htile(image, dst_layout)) {
2428 /* TODO: merge with the clear if applicable */
2429 radv_initialize_htile(cmd_buffer, image);
2430 } else if (!radv_layout_has_htile(image, src_layout) &&
2431 radv_layout_has_htile(image, dst_layout)) {
2432 radv_initialize_htile(cmd_buffer, image);
2433 } else if ((radv_layout_has_htile(image, src_layout) &&
2434 !radv_layout_has_htile(image, dst_layout)) ||
2435 (radv_layout_is_htile_compressed(image, src_layout) &&
2436 !radv_layout_is_htile_compressed(image, dst_layout))) {
2437
2438 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2439 range.baseMipLevel = 0;
2440 range.levelCount = 1;
2441
2442 radv_decompress_depth_image_inplace(cmd_buffer, image, &range);
2443 }
2444 }
2445
2446 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2447 struct radv_image *image, uint32_t value)
2448 {
2449 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2450 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2451
2452 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2453 image->cmask.size, value);
2454
2455 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2456 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2457 RADV_CMD_FLAG_INV_VMEM_L1 |
2458 RADV_CMD_FLAG_INV_GLOBAL_L2;
2459 }
2460
2461 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2462 struct radv_image *image,
2463 VkImageLayout src_layout,
2464 VkImageLayout dst_layout,
2465 unsigned src_queue_mask,
2466 unsigned dst_queue_mask,
2467 VkImageSubresourceRange range,
2468 VkImageAspectFlags pending_clears)
2469 {
2470 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2471 if (image->fmask.size)
2472 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2473 else
2474 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2475 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2476 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2477 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2478 }
2479 }
2480
2481 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2482 struct radv_image *image, uint32_t value)
2483 {
2484
2485 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2486 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2487
2488 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2489 image->surface.dcc_size, value);
2490
2491 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2492 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2493 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2494 RADV_CMD_FLAG_INV_VMEM_L1 |
2495 RADV_CMD_FLAG_INV_GLOBAL_L2;
2496 }
2497
2498 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2499 struct radv_image *image,
2500 VkImageLayout src_layout,
2501 VkImageLayout dst_layout,
2502 unsigned src_queue_mask,
2503 unsigned dst_queue_mask,
2504 VkImageSubresourceRange range,
2505 VkImageAspectFlags pending_clears)
2506 {
2507 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2508 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2509 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2510 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2511 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2512 }
2513 }
2514
2515 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2516 struct radv_image *image,
2517 VkImageLayout src_layout,
2518 VkImageLayout dst_layout,
2519 int src_family,
2520 int dst_family,
2521 VkImageSubresourceRange range,
2522 VkImageAspectFlags pending_clears)
2523 {
2524 if (image->exclusive && src_family != dst_family) {
2525 /* This is an acquire or a release operation and there will be
2526 * a corresponding release/acquire. Do the transition in the
2527 * most flexible queue. */
2528
2529 assert(src_family == cmd_buffer->queue_family_index ||
2530 dst_family == cmd_buffer->queue_family_index);
2531
2532 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
2533 return;
2534
2535 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
2536 (src_family == RADV_QUEUE_GENERAL ||
2537 dst_family == RADV_QUEUE_GENERAL))
2538 return;
2539 }
2540
2541 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family);
2542 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family);
2543
2544 if (image->htile.size)
2545 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2546 dst_layout, range, pending_clears);
2547
2548 if (image->cmask.size)
2549 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2550 dst_layout, src_queue_mask,
2551 dst_queue_mask, range,
2552 pending_clears);
2553
2554 if (image->surface.dcc_size)
2555 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2556 dst_layout, src_queue_mask,
2557 dst_queue_mask, range,
2558 pending_clears);
2559 }
2560
2561 void radv_CmdPipelineBarrier(
2562 VkCommandBuffer commandBuffer,
2563 VkPipelineStageFlags srcStageMask,
2564 VkPipelineStageFlags destStageMask,
2565 VkBool32 byRegion,
2566 uint32_t memoryBarrierCount,
2567 const VkMemoryBarrier* pMemoryBarriers,
2568 uint32_t bufferMemoryBarrierCount,
2569 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2570 uint32_t imageMemoryBarrierCount,
2571 const VkImageMemoryBarrier* pImageMemoryBarriers)
2572 {
2573 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2574 VkAccessFlags src_flags = 0;
2575 VkAccessFlags dst_flags = 0;
2576 uint32_t b;
2577 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2578 src_flags |= pMemoryBarriers[i].srcAccessMask;
2579 dst_flags |= pMemoryBarriers[i].dstAccessMask;
2580 }
2581
2582 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2583 src_flags |= pBufferMemoryBarriers[i].srcAccessMask;
2584 dst_flags |= pBufferMemoryBarriers[i].dstAccessMask;
2585 }
2586
2587 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2588 src_flags |= pImageMemoryBarriers[i].srcAccessMask;
2589 dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
2590 }
2591
2592 enum radv_cmd_flush_bits flush_bits = 0;
2593 for_each_bit(b, src_flags) {
2594 switch ((VkAccessFlagBits)(1 << b)) {
2595 case VK_ACCESS_SHADER_WRITE_BIT:
2596 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2597 break;
2598 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2599 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2600 break;
2601 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2602 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2603 break;
2604 case VK_ACCESS_TRANSFER_WRITE_BIT:
2605 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2606 break;
2607 default:
2608 break;
2609 }
2610 }
2611 cmd_buffer->state.flush_bits |= flush_bits;
2612
2613 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2614 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2615 radv_handle_image_transition(cmd_buffer, image,
2616 pImageMemoryBarriers[i].oldLayout,
2617 pImageMemoryBarriers[i].newLayout,
2618 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2619 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2620 pImageMemoryBarriers[i].subresourceRange,
2621 0);
2622 }
2623
2624 flush_bits = 0;
2625
2626 for_each_bit(b, dst_flags) {
2627 switch ((VkAccessFlagBits)(1 << b)) {
2628 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2629 case VK_ACCESS_INDEX_READ_BIT:
2630 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2631 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2632 break;
2633 case VK_ACCESS_UNIFORM_READ_BIT:
2634 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2635 break;
2636 case VK_ACCESS_SHADER_READ_BIT:
2637 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2638 break;
2639 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2640 case VK_ACCESS_TRANSFER_READ_BIT:
2641 case VK_ACCESS_TRANSFER_WRITE_BIT:
2642 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2643 flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER | RADV_CMD_FLAG_INV_GLOBAL_L2;
2644 default:
2645 break;
2646 }
2647 }
2648
2649 flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2650 RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2651
2652 cmd_buffer->state.flush_bits |= flush_bits;
2653 }
2654
2655
2656 static void write_event(struct radv_cmd_buffer *cmd_buffer,
2657 struct radv_event *event,
2658 VkPipelineStageFlags stageMask,
2659 unsigned value)
2660 {
2661 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2662 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2663
2664 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2665
2666 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
2667
2668 /* TODO: this is overkill. Probably should figure something out from
2669 * the stage mask. */
2670
2671 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
2672 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2673 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2674 EVENT_INDEX(5));
2675 radeon_emit(cs, va);
2676 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2677 radeon_emit(cs, 2);
2678 radeon_emit(cs, 0);
2679 }
2680
2681 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2682 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2683 EVENT_INDEX(5));
2684 radeon_emit(cs, va);
2685 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2686 radeon_emit(cs, value);
2687 radeon_emit(cs, 0);
2688
2689 assert(cmd_buffer->cs->cdw <= cdw_max);
2690 }
2691
2692 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
2693 VkEvent _event,
2694 VkPipelineStageFlags stageMask)
2695 {
2696 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2697 RADV_FROM_HANDLE(radv_event, event, _event);
2698
2699 write_event(cmd_buffer, event, stageMask, 1);
2700 }
2701
2702 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
2703 VkEvent _event,
2704 VkPipelineStageFlags stageMask)
2705 {
2706 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2707 RADV_FROM_HANDLE(radv_event, event, _event);
2708
2709 write_event(cmd_buffer, event, stageMask, 0);
2710 }
2711
2712 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
2713 uint32_t eventCount,
2714 const VkEvent* pEvents,
2715 VkPipelineStageFlags srcStageMask,
2716 VkPipelineStageFlags dstStageMask,
2717 uint32_t memoryBarrierCount,
2718 const VkMemoryBarrier* pMemoryBarriers,
2719 uint32_t bufferMemoryBarrierCount,
2720 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2721 uint32_t imageMemoryBarrierCount,
2722 const VkImageMemoryBarrier* pImageMemoryBarriers)
2723 {
2724 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2725 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2726
2727 for (unsigned i = 0; i < eventCount; ++i) {
2728 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
2729 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2730
2731 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2732
2733 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
2734
2735 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
2736 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
2737 radeon_emit(cs, va);
2738 radeon_emit(cs, va >> 32);
2739 radeon_emit(cs, 1); /* reference value */
2740 radeon_emit(cs, 0xffffffff); /* mask */
2741 radeon_emit(cs, 4); /* poll interval */
2742
2743 assert(cmd_buffer->cs->cdw <= cdw_max);
2744 }
2745
2746
2747 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2748 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2749
2750 radv_handle_image_transition(cmd_buffer, image,
2751 pImageMemoryBarriers[i].oldLayout,
2752 pImageMemoryBarriers[i].newLayout,
2753 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2754 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2755 pImageMemoryBarriers[i].subresourceRange,
2756 0);
2757 }
2758
2759 /* TODO: figure out how to do memory barriers without waiting */
2760 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
2761 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2762 RADV_CMD_FLAG_INV_VMEM_L1 |
2763 RADV_CMD_FLAG_INV_SMEM_L1;
2764 }