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radv/gfx10: implement a bug workaround for NGG -> legacy transitions
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 struct radv_sample_locations_state *sample_locs);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109 dest->sample_location.count = src->sample_location.count;
110
111 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
112 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
113 src->viewport.count * sizeof(VkViewport))) {
114 typed_memcpy(dest->viewport.viewports,
115 src->viewport.viewports,
116 src->viewport.count);
117 dest_mask |= RADV_DYNAMIC_VIEWPORT;
118 }
119 }
120
121 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
122 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
123 src->scissor.count * sizeof(VkRect2D))) {
124 typed_memcpy(dest->scissor.scissors,
125 src->scissor.scissors, src->scissor.count);
126 dest_mask |= RADV_DYNAMIC_SCISSOR;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
131 if (dest->line_width != src->line_width) {
132 dest->line_width = src->line_width;
133 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
134 }
135 }
136
137 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
138 if (memcmp(&dest->depth_bias, &src->depth_bias,
139 sizeof(src->depth_bias))) {
140 dest->depth_bias = src->depth_bias;
141 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
142 }
143 }
144
145 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
146 if (memcmp(&dest->blend_constants, &src->blend_constants,
147 sizeof(src->blend_constants))) {
148 typed_memcpy(dest->blend_constants,
149 src->blend_constants, 4);
150 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
151 }
152 }
153
154 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
155 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
156 sizeof(src->depth_bounds))) {
157 dest->depth_bounds = src->depth_bounds;
158 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
159 }
160 }
161
162 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
163 if (memcmp(&dest->stencil_compare_mask,
164 &src->stencil_compare_mask,
165 sizeof(src->stencil_compare_mask))) {
166 dest->stencil_compare_mask = src->stencil_compare_mask;
167 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
168 }
169 }
170
171 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
172 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
173 sizeof(src->stencil_write_mask))) {
174 dest->stencil_write_mask = src->stencil_write_mask;
175 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
176 }
177 }
178
179 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
180 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
181 sizeof(src->stencil_reference))) {
182 dest->stencil_reference = src->stencil_reference;
183 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
184 }
185 }
186
187 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
188 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
189 src->discard_rectangle.count * sizeof(VkRect2D))) {
190 typed_memcpy(dest->discard_rectangle.rectangles,
191 src->discard_rectangle.rectangles,
192 src->discard_rectangle.count);
193 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
194 }
195 }
196
197 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
198 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
199 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
200 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
201 memcmp(&dest->sample_location.locations,
202 &src->sample_location.locations,
203 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
204 dest->sample_location.per_pixel = src->sample_location.per_pixel;
205 dest->sample_location.grid_size = src->sample_location.grid_size;
206 typed_memcpy(dest->sample_location.locations,
207 src->sample_location.locations,
208 src->sample_location.count);
209 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
210 }
211 }
212
213 cmd_buffer->state.dirty |= dest_mask;
214 }
215
216 static void
217 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
218 struct radv_pipeline *pipeline)
219 {
220 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
221 struct radv_shader_info *info;
222
223 if (!pipeline->streamout_shader)
224 return;
225
226 info = &pipeline->streamout_shader->info.info;
227 for (int i = 0; i < MAX_SO_BUFFERS; i++)
228 so->stride_in_dw[i] = info->so.strides[i];
229
230 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
231 }
232
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
234 {
235 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
236 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
237 }
238
239 enum ring_type radv_queue_family_to_ring(int f) {
240 switch (f) {
241 case RADV_QUEUE_GENERAL:
242 return RING_GFX;
243 case RADV_QUEUE_COMPUTE:
244 return RING_COMPUTE;
245 case RADV_QUEUE_TRANSFER:
246 return RING_DMA;
247 default:
248 unreachable("Unknown queue family");
249 }
250 }
251
252 static VkResult radv_create_cmd_buffer(
253 struct radv_device * device,
254 struct radv_cmd_pool * pool,
255 VkCommandBufferLevel level,
256 VkCommandBuffer* pCommandBuffer)
257 {
258 struct radv_cmd_buffer *cmd_buffer;
259 unsigned ring;
260 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
262 if (cmd_buffer == NULL)
263 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 cmd_buffer->device = device;
267 cmd_buffer->pool = pool;
268 cmd_buffer->level = level;
269
270 if (pool) {
271 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
272 cmd_buffer->queue_family_index = pool->queue_family_index;
273
274 } else {
275 /* Init the pool_link so we can safely call list_del when we destroy
276 * the command buffer
277 */
278 list_inithead(&cmd_buffer->pool_link);
279 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
280 }
281
282 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
283
284 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
285 if (!cmd_buffer->cs) {
286 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
287 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
288 }
289
290 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
291
292 list_inithead(&cmd_buffer->upload.list);
293
294 return VK_SUCCESS;
295 }
296
297 static void
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
299 {
300 list_del(&cmd_buffer->pool_link);
301
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
303 &cmd_buffer->upload.list, list) {
304 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
305 list_del(&up->list);
306 free(up);
307 }
308
309 if (cmd_buffer->upload.upload_bo)
310 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
311 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
314 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
315
316 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
317 }
318
319 static VkResult
320 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
321 {
322 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
323
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
325 &cmd_buffer->upload.list, list) {
326 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
327 list_del(&up->list);
328 free(up);
329 }
330
331 cmd_buffer->push_constant_stages = 0;
332 cmd_buffer->scratch_size_needed = 0;
333 cmd_buffer->compute_scratch_size_needed = 0;
334 cmd_buffer->esgs_ring_size_needed = 0;
335 cmd_buffer->gsvs_ring_size_needed = 0;
336 cmd_buffer->tess_rings_needed = false;
337 cmd_buffer->sample_positions_needed = false;
338
339 if (cmd_buffer->upload.upload_bo)
340 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
341 cmd_buffer->upload.upload_bo);
342 cmd_buffer->upload.offset = 0;
343
344 cmd_buffer->record_result = VK_SUCCESS;
345
346 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
347
348 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
349 cmd_buffer->descriptors[i].dirty = 0;
350 cmd_buffer->descriptors[i].valid = 0;
351 cmd_buffer->descriptors[i].push_dirty = false;
352 }
353
354 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
355 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
356 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
357 unsigned fence_offset, eop_bug_offset;
358 void *fence_ptr;
359
360 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
361 &fence_ptr);
362
363 cmd_buffer->gfx9_fence_va =
364 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
365 cmd_buffer->gfx9_fence_va += fence_offset;
366
367 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
368 /* Allocate a buffer for the EOP bug on GFX9. */
369 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
370 &eop_bug_offset, &fence_ptr);
371 cmd_buffer->gfx9_eop_bug_va =
372 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
373 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
374 }
375 }
376
377 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
378
379 return cmd_buffer->record_result;
380 }
381
382 static bool
383 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
384 uint64_t min_needed)
385 {
386 uint64_t new_size;
387 struct radeon_winsys_bo *bo;
388 struct radv_cmd_buffer_upload *upload;
389 struct radv_device *device = cmd_buffer->device;
390
391 new_size = MAX2(min_needed, 16 * 1024);
392 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
393
394 bo = device->ws->buffer_create(device->ws,
395 new_size, 4096,
396 RADEON_DOMAIN_GTT,
397 RADEON_FLAG_CPU_ACCESS|
398 RADEON_FLAG_NO_INTERPROCESS_SHARING |
399 RADEON_FLAG_32BIT,
400 RADV_BO_PRIORITY_UPLOAD_BUFFER);
401
402 if (!bo) {
403 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
404 return false;
405 }
406
407 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
408 if (cmd_buffer->upload.upload_bo) {
409 upload = malloc(sizeof(*upload));
410
411 if (!upload) {
412 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
413 device->ws->buffer_destroy(bo);
414 return false;
415 }
416
417 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
418 list_add(&upload->list, &cmd_buffer->upload.list);
419 }
420
421 cmd_buffer->upload.upload_bo = bo;
422 cmd_buffer->upload.size = new_size;
423 cmd_buffer->upload.offset = 0;
424 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
425
426 if (!cmd_buffer->upload.map) {
427 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
428 return false;
429 }
430
431 return true;
432 }
433
434 bool
435 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
436 unsigned size,
437 unsigned alignment,
438 unsigned *out_offset,
439 void **ptr)
440 {
441 assert(util_is_power_of_two_nonzero(alignment));
442
443 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
444 if (offset + size > cmd_buffer->upload.size) {
445 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
446 return false;
447 offset = 0;
448 }
449
450 *out_offset = offset;
451 *ptr = cmd_buffer->upload.map + offset;
452
453 cmd_buffer->upload.offset = offset + size;
454 return true;
455 }
456
457 bool
458 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
459 unsigned size, unsigned alignment,
460 const void *data, unsigned *out_offset)
461 {
462 uint8_t *ptr;
463
464 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
465 out_offset, (void **)&ptr))
466 return false;
467
468 if (ptr)
469 memcpy(ptr, data, size);
470
471 return true;
472 }
473
474 static void
475 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
476 unsigned count, const uint32_t *data)
477 {
478 struct radeon_cmdbuf *cs = cmd_buffer->cs;
479
480 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
481
482 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
483 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
484 S_370_WR_CONFIRM(1) |
485 S_370_ENGINE_SEL(V_370_ME));
486 radeon_emit(cs, va);
487 radeon_emit(cs, va >> 32);
488 radeon_emit_array(cs, data, count);
489 }
490
491 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
492 {
493 struct radv_device *device = cmd_buffer->device;
494 struct radeon_cmdbuf *cs = cmd_buffer->cs;
495 uint64_t va;
496
497 va = radv_buffer_get_va(device->trace_bo);
498 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
499 va += 4;
500
501 ++cmd_buffer->state.trace_id;
502 radv_emit_write_data_packet(cmd_buffer, va, 1,
503 &cmd_buffer->state.trace_id);
504
505 radeon_check_space(cmd_buffer->device->ws, cs, 2);
506
507 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
508 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
509 }
510
511 static void
512 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
513 enum radv_cmd_flush_bits flags)
514 {
515 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
516 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
517 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
518
519 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
520
521 /* Force wait for graphics or compute engines to be idle. */
522 si_cs_emit_cache_flush(cmd_buffer->cs,
523 cmd_buffer->device->physical_device->rad_info.chip_class,
524 &cmd_buffer->gfx9_fence_idx,
525 cmd_buffer->gfx9_fence_va,
526 radv_cmd_buffer_uses_mec(cmd_buffer),
527 flags, cmd_buffer->gfx9_eop_bug_va);
528 }
529
530 if (unlikely(cmd_buffer->device->trace_bo))
531 radv_cmd_buffer_trace_emit(cmd_buffer);
532 }
533
534 static void
535 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
536 struct radv_pipeline *pipeline, enum ring_type ring)
537 {
538 struct radv_device *device = cmd_buffer->device;
539 uint32_t data[2];
540 uint64_t va;
541
542 va = radv_buffer_get_va(device->trace_bo);
543
544 switch (ring) {
545 case RING_GFX:
546 va += 8;
547 break;
548 case RING_COMPUTE:
549 va += 16;
550 break;
551 default:
552 assert(!"invalid ring type");
553 }
554
555 data[0] = (uintptr_t)pipeline;
556 data[1] = (uintptr_t)pipeline >> 32;
557
558 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
559 }
560
561 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
562 VkPipelineBindPoint bind_point,
563 struct radv_descriptor_set *set,
564 unsigned idx)
565 {
566 struct radv_descriptor_state *descriptors_state =
567 radv_get_descriptors_state(cmd_buffer, bind_point);
568
569 descriptors_state->sets[idx] = set;
570
571 descriptors_state->valid |= (1u << idx); /* active descriptors */
572 descriptors_state->dirty |= (1u << idx);
573 }
574
575 static void
576 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
577 VkPipelineBindPoint bind_point)
578 {
579 struct radv_descriptor_state *descriptors_state =
580 radv_get_descriptors_state(cmd_buffer, bind_point);
581 struct radv_device *device = cmd_buffer->device;
582 uint32_t data[MAX_SETS * 2] = {};
583 uint64_t va;
584 unsigned i;
585 va = radv_buffer_get_va(device->trace_bo) + 24;
586
587 for_each_bit(i, descriptors_state->valid) {
588 struct radv_descriptor_set *set = descriptors_state->sets[i];
589 data[i * 2] = (uint64_t)(uintptr_t)set;
590 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
591 }
592
593 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
594 }
595
596 struct radv_userdata_info *
597 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
598 gl_shader_stage stage,
599 int idx)
600 {
601 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
602 return &shader->info.user_sgprs_locs.shader_data[idx];
603 }
604
605 static void
606 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
607 struct radv_pipeline *pipeline,
608 gl_shader_stage stage,
609 int idx, uint64_t va)
610 {
611 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
612 uint32_t base_reg = pipeline->user_data_0[stage];
613 if (loc->sgpr_idx == -1)
614 return;
615
616 assert(loc->num_sgprs == 1);
617
618 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
619 base_reg + loc->sgpr_idx * 4, va, false);
620 }
621
622 static void
623 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
624 struct radv_pipeline *pipeline,
625 struct radv_descriptor_state *descriptors_state,
626 gl_shader_stage stage)
627 {
628 struct radv_device *device = cmd_buffer->device;
629 struct radeon_cmdbuf *cs = cmd_buffer->cs;
630 uint32_t sh_base = pipeline->user_data_0[stage];
631 struct radv_userdata_locations *locs =
632 &pipeline->shaders[stage]->info.user_sgprs_locs;
633 unsigned mask = locs->descriptor_sets_enabled;
634
635 mask &= descriptors_state->dirty & descriptors_state->valid;
636
637 while (mask) {
638 int start, count;
639
640 u_bit_scan_consecutive_range(&mask, &start, &count);
641
642 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
643 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
644
645 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
646 for (int i = 0; i < count; i++) {
647 struct radv_descriptor_set *set =
648 descriptors_state->sets[start + i];
649
650 radv_emit_shader_pointer_body(device, cs, set->va, true);
651 }
652 }
653 }
654
655 /**
656 * Convert the user sample locations to hardware sample locations (the values
657 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
658 */
659 static void
660 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
661 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
662 {
663 uint32_t x_offset = x % state->grid_size.width;
664 uint32_t y_offset = y % state->grid_size.height;
665 uint32_t num_samples = (uint32_t)state->per_pixel;
666 VkSampleLocationEXT *user_locs;
667 uint32_t pixel_offset;
668
669 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
670
671 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
672 user_locs = &state->locations[pixel_offset];
673
674 for (uint32_t i = 0; i < num_samples; i++) {
675 float shifted_pos_x = user_locs[i].x - 0.5;
676 float shifted_pos_y = user_locs[i].y - 0.5;
677
678 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
679 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
680
681 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
682 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
683 }
684 }
685
686 /**
687 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
688 * locations.
689 */
690 static void
691 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
692 uint32_t *sample_locs_pixel)
693 {
694 for (uint32_t i = 0; i < num_samples; i++) {
695 uint32_t sample_reg_idx = i / 4;
696 uint32_t sample_loc_idx = i % 4;
697 int32_t pos_x = sample_locs[i].x;
698 int32_t pos_y = sample_locs[i].y;
699
700 uint32_t shift_x = 8 * sample_loc_idx;
701 uint32_t shift_y = shift_x + 4;
702
703 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
704 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
705 }
706 }
707
708 /**
709 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
710 * sample locations.
711 */
712 static uint64_t
713 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
714 VkOffset2D *sample_locs,
715 uint32_t num_samples)
716 {
717 uint32_t centroid_priorities[num_samples];
718 uint32_t sample_mask = num_samples - 1;
719 uint32_t distances[num_samples];
720 uint64_t centroid_priority = 0;
721
722 /* Compute the distances from center for each sample. */
723 for (int i = 0; i < num_samples; i++) {
724 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
725 (sample_locs[i].y * sample_locs[i].y);
726 }
727
728 /* Compute the centroid priorities by looking at the distances array. */
729 for (int i = 0; i < num_samples; i++) {
730 uint32_t min_idx = 0;
731
732 for (int j = 1; j < num_samples; j++) {
733 if (distances[j] < distances[min_idx])
734 min_idx = j;
735 }
736
737 centroid_priorities[i] = min_idx;
738 distances[min_idx] = 0xffffffff;
739 }
740
741 /* Compute the final centroid priority. */
742 for (int i = 0; i < 8; i++) {
743 centroid_priority |=
744 centroid_priorities[i & sample_mask] << (i * 4);
745 }
746
747 return centroid_priority << 32 | centroid_priority;
748 }
749
750 /**
751 * Emit the sample locations that are specified with VK_EXT_sample_locations.
752 */
753 static void
754 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
755 {
756 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
757 struct radv_multisample_state *ms = &pipeline->graphics.ms;
758 struct radv_sample_locations_state *sample_location =
759 &cmd_buffer->state.dynamic.sample_location;
760 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
761 struct radeon_cmdbuf *cs = cmd_buffer->cs;
762 uint32_t sample_locs_pixel[4][2] = {};
763 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
764 uint32_t max_sample_dist = 0;
765 uint64_t centroid_priority;
766
767 if (!cmd_buffer->state.dynamic.sample_location.count)
768 return;
769
770 /* Convert the user sample locations to hardware sample locations. */
771 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
772 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
773 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
774 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
775
776 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
777 for (uint32_t i = 0; i < 4; i++) {
778 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
779 sample_locs_pixel[i]);
780 }
781
782 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
783 centroid_priority =
784 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
785 num_samples);
786
787 /* Compute the maximum sample distance from the specified locations. */
788 for (uint32_t i = 0; i < num_samples; i++) {
789 VkOffset2D offset = sample_locs[0][i];
790 max_sample_dist = MAX2(max_sample_dist,
791 MAX2(abs(offset.x), abs(offset.y)));
792 }
793
794 /* Emit the specified user sample locations. */
795 switch (num_samples) {
796 case 2:
797 case 4:
798 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
799 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
800 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
801 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
802 break;
803 case 8:
804 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
805 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
806 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
807 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
808 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
809 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
810 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
811 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
812 break;
813 default:
814 unreachable("invalid number of samples");
815 }
816
817 /* Emit the maximum sample distance and the centroid priority. */
818 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
819
820 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
821 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
822
823 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
824 radeon_emit(cs, pa_sc_aa_config);
825
826 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
827 radeon_emit(cs, centroid_priority);
828 radeon_emit(cs, centroid_priority >> 32);
829
830 /* GFX9: Flush DFSM when the AA mode changes. */
831 if (cmd_buffer->device->dfsm_allowed) {
832 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
833 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
834 }
835
836 cmd_buffer->state.context_roll_without_scissor_emitted = true;
837 }
838
839 static void
840 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
841 struct radv_pipeline *pipeline,
842 gl_shader_stage stage,
843 int idx, int count, uint32_t *values)
844 {
845 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
846 uint32_t base_reg = pipeline->user_data_0[stage];
847 if (loc->sgpr_idx == -1)
848 return;
849
850 assert(loc->num_sgprs == count);
851
852 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
853 radeon_emit_array(cmd_buffer->cs, values, count);
854 }
855
856 static void
857 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
858 struct radv_pipeline *pipeline)
859 {
860 int num_samples = pipeline->graphics.ms.num_samples;
861 struct radv_multisample_state *ms = &pipeline->graphics.ms;
862 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
863
864 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
865 cmd_buffer->sample_positions_needed = true;
866
867 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
868 return;
869
870 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
871 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
872 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
873
874 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
875
876 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
877
878 /* GFX9: Flush DFSM when the AA mode changes. */
879 if (cmd_buffer->device->dfsm_allowed) {
880 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
881 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
882 }
883
884 cmd_buffer->state.context_roll_without_scissor_emitted = true;
885 }
886
887 static void
888 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
889 struct radv_pipeline *pipeline)
890 {
891 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
892
893
894 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
895 return;
896
897 if (old_pipeline &&
898 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
899 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
900 return;
901
902 bool binning_flush = false;
903 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
904 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
905 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
906 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
907 binning_flush = !old_pipeline ||
908 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
909 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
910 }
911
912 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
913 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
914 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
915
916 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
917 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
918 pipeline->graphics.binning.db_dfsm_control);
919 } else {
920 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
921 pipeline->graphics.binning.db_dfsm_control);
922 }
923
924 cmd_buffer->state.context_roll_without_scissor_emitted = true;
925 }
926
927
928 static void
929 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
930 struct radv_shader_variant *shader)
931 {
932 uint64_t va;
933
934 if (!shader)
935 return;
936
937 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
938
939 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
940 }
941
942 static void
943 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
944 struct radv_pipeline *pipeline,
945 bool vertex_stage_only)
946 {
947 struct radv_cmd_state *state = &cmd_buffer->state;
948 uint32_t mask = state->prefetch_L2_mask;
949
950 if (vertex_stage_only) {
951 /* Fast prefetch path for starting draws as soon as possible.
952 */
953 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
954 RADV_PREFETCH_VBO_DESCRIPTORS);
955 }
956
957 if (mask & RADV_PREFETCH_VS)
958 radv_emit_shader_prefetch(cmd_buffer,
959 pipeline->shaders[MESA_SHADER_VERTEX]);
960
961 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
962 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
963
964 if (mask & RADV_PREFETCH_TCS)
965 radv_emit_shader_prefetch(cmd_buffer,
966 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
967
968 if (mask & RADV_PREFETCH_TES)
969 radv_emit_shader_prefetch(cmd_buffer,
970 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
971
972 if (mask & RADV_PREFETCH_GS) {
973 radv_emit_shader_prefetch(cmd_buffer,
974 pipeline->shaders[MESA_SHADER_GEOMETRY]);
975 if (radv_pipeline_has_gs_copy_shader(pipeline))
976 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
977 }
978
979 if (mask & RADV_PREFETCH_PS)
980 radv_emit_shader_prefetch(cmd_buffer,
981 pipeline->shaders[MESA_SHADER_FRAGMENT]);
982
983 state->prefetch_L2_mask &= ~mask;
984 }
985
986 static void
987 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
988 {
989 if (!cmd_buffer->device->physical_device->rbplus_allowed)
990 return;
991
992 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
993 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
994 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
995
996 unsigned sx_ps_downconvert = 0;
997 unsigned sx_blend_opt_epsilon = 0;
998 unsigned sx_blend_opt_control = 0;
999
1000 for (unsigned i = 0; i < subpass->color_count; ++i) {
1001 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1002 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1003 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1004 continue;
1005 }
1006
1007 int idx = subpass->color_attachments[i].attachment;
1008 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
1009
1010 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1011 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1012 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1013 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1014
1015 bool has_alpha, has_rgb;
1016
1017 /* Set if RGB and A are present. */
1018 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1019
1020 if (format == V_028C70_COLOR_8 ||
1021 format == V_028C70_COLOR_16 ||
1022 format == V_028C70_COLOR_32)
1023 has_rgb = !has_alpha;
1024 else
1025 has_rgb = true;
1026
1027 /* Check the colormask and export format. */
1028 if (!(colormask & 0x7))
1029 has_rgb = false;
1030 if (!(colormask & 0x8))
1031 has_alpha = false;
1032
1033 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1034 has_rgb = false;
1035 has_alpha = false;
1036 }
1037
1038 /* Disable value checking for disabled channels. */
1039 if (!has_rgb)
1040 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1041 if (!has_alpha)
1042 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1043
1044 /* Enable down-conversion for 32bpp and smaller formats. */
1045 switch (format) {
1046 case V_028C70_COLOR_8:
1047 case V_028C70_COLOR_8_8:
1048 case V_028C70_COLOR_8_8_8_8:
1049 /* For 1 and 2-channel formats, use the superset thereof. */
1050 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1051 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1052 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1053 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1054 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1055 }
1056 break;
1057
1058 case V_028C70_COLOR_5_6_5:
1059 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1060 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1061 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1062 }
1063 break;
1064
1065 case V_028C70_COLOR_1_5_5_5:
1066 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1067 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1068 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1069 }
1070 break;
1071
1072 case V_028C70_COLOR_4_4_4_4:
1073 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1074 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1075 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1076 }
1077 break;
1078
1079 case V_028C70_COLOR_32:
1080 if (swap == V_028C70_SWAP_STD &&
1081 spi_format == V_028714_SPI_SHADER_32_R)
1082 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1083 else if (swap == V_028C70_SWAP_ALT_REV &&
1084 spi_format == V_028714_SPI_SHADER_32_AR)
1085 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1086 break;
1087
1088 case V_028C70_COLOR_16:
1089 case V_028C70_COLOR_16_16:
1090 /* For 1-channel formats, use the superset thereof. */
1091 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1092 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1093 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1094 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1095 if (swap == V_028C70_SWAP_STD ||
1096 swap == V_028C70_SWAP_STD_REV)
1097 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1098 else
1099 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1100 }
1101 break;
1102
1103 case V_028C70_COLOR_10_11_11:
1104 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1105 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1106 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1107 }
1108 break;
1109
1110 case V_028C70_COLOR_2_10_10_10:
1111 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1112 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1113 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1114 }
1115 break;
1116 }
1117 }
1118
1119 for (unsigned i = subpass->color_count; i < 8; ++i) {
1120 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1121 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1122 }
1123 /* TODO: avoid redundantly setting context registers */
1124 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1125 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1126 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1127 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1128
1129 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1130 }
1131
1132 static void
1133 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1134 {
1135 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1136
1137 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1138 return;
1139
1140 radv_update_multisample_state(cmd_buffer, pipeline);
1141 radv_update_binning_state(cmd_buffer, pipeline);
1142
1143 cmd_buffer->scratch_size_needed =
1144 MAX2(cmd_buffer->scratch_size_needed,
1145 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1146
1147 if (!cmd_buffer->state.emitted_pipeline ||
1148 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1149 pipeline->graphics.can_use_guardband)
1150 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1151
1152 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1153
1154 if (!cmd_buffer->state.emitted_pipeline ||
1155 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1156 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1157 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1158 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1159 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1160 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1161 }
1162
1163 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1164 if (!pipeline->shaders[i])
1165 continue;
1166
1167 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1168 pipeline->shaders[i]->bo);
1169 }
1170
1171 if (radv_pipeline_has_gs_copy_shader(pipeline))
1172 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1173 pipeline->gs_copy_shader->bo);
1174
1175 if (unlikely(cmd_buffer->device->trace_bo))
1176 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1177
1178 cmd_buffer->state.emitted_pipeline = pipeline;
1179
1180 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1181 }
1182
1183 static void
1184 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1185 {
1186 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1187 cmd_buffer->state.dynamic.viewport.viewports);
1188 }
1189
1190 static void
1191 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1192 {
1193 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1194
1195 si_write_scissors(cmd_buffer->cs, 0, count,
1196 cmd_buffer->state.dynamic.scissor.scissors,
1197 cmd_buffer->state.dynamic.viewport.viewports,
1198 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1199
1200 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1201 }
1202
1203 static void
1204 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1205 {
1206 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1207 return;
1208
1209 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1210 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1211 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1212 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1213 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1214 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1215 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1216 }
1217 }
1218
1219 static void
1220 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1221 {
1222 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1223
1224 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1225 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1226 }
1227
1228 static void
1229 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1230 {
1231 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1232
1233 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1234 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1235 }
1236
1237 static void
1238 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1239 {
1240 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1241
1242 radeon_set_context_reg_seq(cmd_buffer->cs,
1243 R_028430_DB_STENCILREFMASK, 2);
1244 radeon_emit(cmd_buffer->cs,
1245 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1246 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1247 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1248 S_028430_STENCILOPVAL(1));
1249 radeon_emit(cmd_buffer->cs,
1250 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1251 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1252 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1253 S_028434_STENCILOPVAL_BF(1));
1254 }
1255
1256 static void
1257 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1258 {
1259 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1260
1261 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1262 fui(d->depth_bounds.min));
1263 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1264 fui(d->depth_bounds.max));
1265 }
1266
1267 static void
1268 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1269 {
1270 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1271 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1272 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1273
1274
1275 radeon_set_context_reg_seq(cmd_buffer->cs,
1276 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1277 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1278 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1279 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1280 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1281 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1282 }
1283
1284 static void
1285 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1286 int index,
1287 struct radv_attachment_info *att,
1288 struct radv_image_view *iview,
1289 VkImageLayout layout)
1290 {
1291 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1292 struct radv_color_buffer_info *cb = &att->cb;
1293 uint32_t cb_color_info = cb->cb_color_info;
1294 struct radv_image *image = iview->image;
1295
1296 if (!radv_layout_dcc_compressed(image, layout,
1297 radv_image_queue_family_mask(image,
1298 cmd_buffer->queue_family_index,
1299 cmd_buffer->queue_family_index))) {
1300 cb_color_info &= C_028C70_DCC_ENABLE;
1301 }
1302
1303 if (radv_image_is_tc_compat_cmask(image) &&
1304 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1305 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1306 /* If this bit is set, the FMASK decompression operation
1307 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1308 */
1309 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1310 }
1311
1312 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1313 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1314 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1315 radeon_emit(cmd_buffer->cs, 0);
1316 radeon_emit(cmd_buffer->cs, 0);
1317 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1318 radeon_emit(cmd_buffer->cs, cb_color_info);
1319 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1320 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1321 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1322 radeon_emit(cmd_buffer->cs, 0);
1323 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1324 radeon_emit(cmd_buffer->cs, 0);
1325
1326 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1327 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1328
1329 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1330 cb->cb_color_base >> 32);
1331 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1332 cb->cb_color_cmask >> 32);
1333 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1334 cb->cb_color_fmask >> 32);
1335 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1336 cb->cb_dcc_base >> 32);
1337 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1338 cb->cb_color_attrib2);
1339 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1340 cb->cb_color_attrib3);
1341 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1342 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1343 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1344 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1345 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1346 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1347 radeon_emit(cmd_buffer->cs, cb_color_info);
1348 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1349 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1350 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1351 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1352 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1353 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1354
1355 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1356 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1357 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1358
1359 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1360 cb->cb_mrt_epitch);
1361 } else {
1362 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1363 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1364 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1365 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1366 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1367 radeon_emit(cmd_buffer->cs, cb_color_info);
1368 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1369 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1370 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1371 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1372 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1373 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1374
1375 if (is_vi) { /* DCC BASE */
1376 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1377 }
1378 }
1379
1380 if (radv_dcc_enabled(image, iview->base_mip)) {
1381 /* Drawing with DCC enabled also compresses colorbuffers. */
1382 VkImageSubresourceRange range = {
1383 .aspectMask = iview->aspect_mask,
1384 .baseMipLevel = iview->base_mip,
1385 .levelCount = iview->level_count,
1386 .baseArrayLayer = iview->base_layer,
1387 .layerCount = iview->layer_count,
1388 };
1389
1390 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1391 }
1392 }
1393
1394 static void
1395 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1396 struct radv_ds_buffer_info *ds,
1397 struct radv_image *image, VkImageLayout layout,
1398 bool requires_cond_exec)
1399 {
1400 uint32_t db_z_info = ds->db_z_info;
1401 uint32_t db_z_info_reg;
1402
1403 if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug ||
1404 !radv_image_is_tc_compat_htile(image))
1405 return;
1406
1407 if (!radv_layout_has_htile(image, layout,
1408 radv_image_queue_family_mask(image,
1409 cmd_buffer->queue_family_index,
1410 cmd_buffer->queue_family_index))) {
1411 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1412 }
1413
1414 db_z_info &= C_028040_ZRANGE_PRECISION;
1415
1416 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1417 db_z_info_reg = R_028038_DB_Z_INFO;
1418 } else {
1419 db_z_info_reg = R_028040_DB_Z_INFO;
1420 }
1421
1422 /* When we don't know the last fast clear value we need to emit a
1423 * conditional packet that will eventually skip the following
1424 * SET_CONTEXT_REG packet.
1425 */
1426 if (requires_cond_exec) {
1427 uint64_t va = radv_buffer_get_va(image->bo);
1428 va += image->offset + image->tc_compat_zrange_offset;
1429
1430 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1431 radeon_emit(cmd_buffer->cs, va);
1432 radeon_emit(cmd_buffer->cs, va >> 32);
1433 radeon_emit(cmd_buffer->cs, 0);
1434 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1435 }
1436
1437 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1438 }
1439
1440 static void
1441 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1442 struct radv_ds_buffer_info *ds,
1443 struct radv_image *image,
1444 VkImageLayout layout)
1445 {
1446 uint32_t db_z_info = ds->db_z_info;
1447 uint32_t db_stencil_info = ds->db_stencil_info;
1448
1449 if (!radv_layout_has_htile(image, layout,
1450 radv_image_queue_family_mask(image,
1451 cmd_buffer->queue_family_index,
1452 cmd_buffer->queue_family_index))) {
1453 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1454 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1455 }
1456
1457 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1458 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1459
1460 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1461 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1462 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1463
1464 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1465 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1466 radeon_emit(cmd_buffer->cs, db_z_info);
1467 radeon_emit(cmd_buffer->cs, db_stencil_info);
1468 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1469 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1470 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1471 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1472
1473 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1474 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1475 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1476 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1477 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1478 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1479 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1480 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1481 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1482 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1483 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1484
1485 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1486 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1487 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1488 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1489 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1490 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1491 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1492 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1493 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1494 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1495 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1496
1497 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1498 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1499 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1500 } else {
1501 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1502
1503 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1504 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1505 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1506 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1507 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1508 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1509 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1510 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1511 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1512 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1513
1514 }
1515
1516 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1517 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1518
1519 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1520 ds->pa_su_poly_offset_db_fmt_cntl);
1521 }
1522
1523 /**
1524 * Update the fast clear depth/stencil values if the image is bound as a
1525 * depth/stencil buffer.
1526 */
1527 static void
1528 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1529 struct radv_image *image,
1530 VkClearDepthStencilValue ds_clear_value,
1531 VkImageAspectFlags aspects)
1532 {
1533 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1534 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1535 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1536 struct radv_attachment_info *att;
1537 uint32_t att_idx;
1538
1539 if (!framebuffer || !subpass)
1540 return;
1541
1542 if (!subpass->depth_stencil_attachment)
1543 return;
1544
1545 att_idx = subpass->depth_stencil_attachment->attachment;
1546 att = &framebuffer->attachments[att_idx];
1547 if (att->attachment->image != image)
1548 return;
1549
1550 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1551 radeon_emit(cs, ds_clear_value.stencil);
1552 radeon_emit(cs, fui(ds_clear_value.depth));
1553
1554 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1555 * only needed when clearing Z to 0.0.
1556 */
1557 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1558 ds_clear_value.depth == 0.0) {
1559 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1560
1561 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1562 layout, false);
1563 }
1564
1565 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1566 }
1567
1568 /**
1569 * Set the clear depth/stencil values to the image's metadata.
1570 */
1571 static void
1572 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1573 struct radv_image *image,
1574 VkClearDepthStencilValue ds_clear_value,
1575 VkImageAspectFlags aspects)
1576 {
1577 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1578 uint64_t va = radv_buffer_get_va(image->bo);
1579 unsigned reg_offset = 0, reg_count = 0;
1580
1581 va += image->offset + image->clear_value_offset;
1582
1583 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1584 ++reg_count;
1585 } else {
1586 ++reg_offset;
1587 va += 4;
1588 }
1589 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1590 ++reg_count;
1591
1592 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1593 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1594 S_370_WR_CONFIRM(1) |
1595 S_370_ENGINE_SEL(V_370_PFP));
1596 radeon_emit(cs, va);
1597 radeon_emit(cs, va >> 32);
1598 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1599 radeon_emit(cs, ds_clear_value.stencil);
1600 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1601 radeon_emit(cs, fui(ds_clear_value.depth));
1602 }
1603
1604 /**
1605 * Update the TC-compat metadata value for this image.
1606 */
1607 static void
1608 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1609 struct radv_image *image,
1610 uint32_t value)
1611 {
1612 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1613 uint64_t va = radv_buffer_get_va(image->bo);
1614
1615 if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug)
1616 return;
1617
1618 va += image->offset + image->tc_compat_zrange_offset;
1619
1620 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1621 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1622 S_370_WR_CONFIRM(1) |
1623 S_370_ENGINE_SEL(V_370_PFP));
1624 radeon_emit(cs, va);
1625 radeon_emit(cs, va >> 32);
1626 radeon_emit(cs, value);
1627 }
1628
1629 static void
1630 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1631 struct radv_image *image,
1632 VkClearDepthStencilValue ds_clear_value)
1633 {
1634 uint32_t cond_val;
1635
1636 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1637 * depth clear value is 0.0f.
1638 */
1639 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1640
1641 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1642 }
1643
1644 /**
1645 * Update the clear depth/stencil values for this image.
1646 */
1647 void
1648 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1649 struct radv_image *image,
1650 VkClearDepthStencilValue ds_clear_value,
1651 VkImageAspectFlags aspects)
1652 {
1653 assert(radv_image_has_htile(image));
1654
1655 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1656
1657 if (radv_image_is_tc_compat_htile(image) &&
1658 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1659 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1660 ds_clear_value);
1661 }
1662
1663 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1664 aspects);
1665 }
1666
1667 /**
1668 * Load the clear depth/stencil values from the image's metadata.
1669 */
1670 static void
1671 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1672 struct radv_image *image)
1673 {
1674 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1675 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1676 uint64_t va = radv_buffer_get_va(image->bo);
1677 unsigned reg_offset = 0, reg_count = 0;
1678
1679 va += image->offset + image->clear_value_offset;
1680
1681 if (!radv_image_has_htile(image))
1682 return;
1683
1684 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1685 ++reg_count;
1686 } else {
1687 ++reg_offset;
1688 va += 4;
1689 }
1690 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1691 ++reg_count;
1692
1693 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1694
1695 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1696 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1697 radeon_emit(cs, va);
1698 radeon_emit(cs, va >> 32);
1699 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1700 radeon_emit(cs, reg_count);
1701 } else {
1702 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1703 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1704 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1705 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1706 radeon_emit(cs, va);
1707 radeon_emit(cs, va >> 32);
1708 radeon_emit(cs, reg >> 2);
1709 radeon_emit(cs, 0);
1710
1711 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1712 radeon_emit(cs, 0);
1713 }
1714 }
1715
1716 /*
1717 * With DCC some colors don't require CMASK elimination before being
1718 * used as a texture. This sets a predicate value to determine if the
1719 * cmask eliminate is required.
1720 */
1721 void
1722 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1723 struct radv_image *image,
1724 const VkImageSubresourceRange *range, bool value)
1725 {
1726 uint64_t pred_val = value;
1727 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1728 uint32_t level_count = radv_get_levelCount(image, range);
1729 uint32_t count = 2 * level_count;
1730
1731 assert(radv_dcc_enabled(image, range->baseMipLevel));
1732
1733 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1734 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1735 S_370_WR_CONFIRM(1) |
1736 S_370_ENGINE_SEL(V_370_PFP));
1737 radeon_emit(cmd_buffer->cs, va);
1738 radeon_emit(cmd_buffer->cs, va >> 32);
1739
1740 for (uint32_t l = 0; l < level_count; l++) {
1741 radeon_emit(cmd_buffer->cs, pred_val);
1742 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1743 }
1744 }
1745
1746 /**
1747 * Update the DCC predicate to reflect the compression state.
1748 */
1749 void
1750 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1751 struct radv_image *image,
1752 const VkImageSubresourceRange *range, bool value)
1753 {
1754 uint64_t pred_val = value;
1755 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1756 uint32_t level_count = radv_get_levelCount(image, range);
1757 uint32_t count = 2 * level_count;
1758
1759 assert(radv_dcc_enabled(image, range->baseMipLevel));
1760
1761 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1762 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1763 S_370_WR_CONFIRM(1) |
1764 S_370_ENGINE_SEL(V_370_PFP));
1765 radeon_emit(cmd_buffer->cs, va);
1766 radeon_emit(cmd_buffer->cs, va >> 32);
1767
1768 for (uint32_t l = 0; l < level_count; l++) {
1769 radeon_emit(cmd_buffer->cs, pred_val);
1770 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1771 }
1772 }
1773
1774 /**
1775 * Update the fast clear color values if the image is bound as a color buffer.
1776 */
1777 static void
1778 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1779 struct radv_image *image,
1780 int cb_idx,
1781 uint32_t color_values[2])
1782 {
1783 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1784 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1785 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1786 struct radv_attachment_info *att;
1787 uint32_t att_idx;
1788
1789 if (!framebuffer || !subpass)
1790 return;
1791
1792 att_idx = subpass->color_attachments[cb_idx].attachment;
1793 if (att_idx == VK_ATTACHMENT_UNUSED)
1794 return;
1795
1796 att = &framebuffer->attachments[att_idx];
1797 if (att->attachment->image != image)
1798 return;
1799
1800 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1801 radeon_emit(cs, color_values[0]);
1802 radeon_emit(cs, color_values[1]);
1803
1804 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1805 }
1806
1807 /**
1808 * Set the clear color values to the image's metadata.
1809 */
1810 static void
1811 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1812 struct radv_image *image,
1813 const VkImageSubresourceRange *range,
1814 uint32_t color_values[2])
1815 {
1816 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1817 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1818 uint32_t level_count = radv_get_levelCount(image, range);
1819 uint32_t count = 2 * level_count;
1820
1821 assert(radv_image_has_cmask(image) ||
1822 radv_dcc_enabled(image, range->baseMipLevel));
1823
1824 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1825 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1826 S_370_WR_CONFIRM(1) |
1827 S_370_ENGINE_SEL(V_370_PFP));
1828 radeon_emit(cs, va);
1829 radeon_emit(cs, va >> 32);
1830
1831 for (uint32_t l = 0; l < level_count; l++) {
1832 radeon_emit(cs, color_values[0]);
1833 radeon_emit(cs, color_values[1]);
1834 }
1835 }
1836
1837 /**
1838 * Update the clear color values for this image.
1839 */
1840 void
1841 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1842 const struct radv_image_view *iview,
1843 int cb_idx,
1844 uint32_t color_values[2])
1845 {
1846 struct radv_image *image = iview->image;
1847 VkImageSubresourceRange range = {
1848 .aspectMask = iview->aspect_mask,
1849 .baseMipLevel = iview->base_mip,
1850 .levelCount = iview->level_count,
1851 .baseArrayLayer = iview->base_layer,
1852 .layerCount = iview->layer_count,
1853 };
1854
1855 assert(radv_image_has_cmask(image) ||
1856 radv_dcc_enabled(image, iview->base_mip));
1857
1858 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1859
1860 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1861 color_values);
1862 }
1863
1864 /**
1865 * Load the clear color values from the image's metadata.
1866 */
1867 static void
1868 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1869 struct radv_image_view *iview,
1870 int cb_idx)
1871 {
1872 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1873 struct radv_image *image = iview->image;
1874 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1875
1876 if (!radv_image_has_cmask(image) &&
1877 !radv_dcc_enabled(image, iview->base_mip))
1878 return;
1879
1880 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1881
1882 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1883 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1884 radeon_emit(cs, va);
1885 radeon_emit(cs, va >> 32);
1886 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1887 radeon_emit(cs, 2);
1888 } else {
1889 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1890 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1891 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1892 COPY_DATA_COUNT_SEL);
1893 radeon_emit(cs, va);
1894 radeon_emit(cs, va >> 32);
1895 radeon_emit(cs, reg >> 2);
1896 radeon_emit(cs, 0);
1897
1898 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1899 radeon_emit(cs, 0);
1900 }
1901 }
1902
1903 static void
1904 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1905 {
1906 int i;
1907 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1908 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1909
1910 /* this may happen for inherited secondary recording */
1911 if (!framebuffer)
1912 return;
1913
1914 for (i = 0; i < 8; ++i) {
1915 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1916 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1917 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1918 continue;
1919 }
1920
1921 int idx = subpass->color_attachments[i].attachment;
1922 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1923 struct radv_image_view *iview = att->attachment;
1924 VkImageLayout layout = subpass->color_attachments[i].layout;
1925
1926 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1927
1928 assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1929 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1930 radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
1931
1932 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1933 }
1934
1935 if (subpass->depth_stencil_attachment) {
1936 int idx = subpass->depth_stencil_attachment->attachment;
1937 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1938 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1939 struct radv_image *image = att->attachment->image;
1940 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1941 ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
1942 cmd_buffer->queue_family_index,
1943 cmd_buffer->queue_family_index);
1944 /* We currently don't support writing decompressed HTILE */
1945 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1946 radv_layout_is_htile_compressed(image, layout, queue_mask));
1947
1948 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1949
1950 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1951 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1952 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1953 }
1954 radv_load_ds_clear_metadata(cmd_buffer, image);
1955 } else {
1956 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
1957 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1958 else
1959 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1960
1961 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1962 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1963 }
1964 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1965 S_028208_BR_X(framebuffer->width) |
1966 S_028208_BR_Y(framebuffer->height));
1967
1968 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
1969 bool disable_constant_encode =
1970 cmd_buffer->device->physical_device->has_dcc_constant_encode;
1971 enum chip_class chip_class =
1972 cmd_buffer->device->physical_device->rad_info.chip_class;
1973 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
1974
1975 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1976 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
1977 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
1978 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
1979 }
1980
1981 if (cmd_buffer->device->pbb_allowed) {
1982 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1983 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1984 }
1985
1986 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1987 }
1988
1989 static void
1990 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1991 {
1992 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1993 struct radv_cmd_state *state = &cmd_buffer->state;
1994
1995 if (state->index_type != state->last_index_type) {
1996 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1997 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1998 cs, R_03090C_VGT_INDEX_TYPE,
1999 2, state->index_type);
2000 } else {
2001 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2002 radeon_emit(cs, state->index_type);
2003 }
2004
2005 state->last_index_type = state->index_type;
2006 }
2007
2008 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2009 radeon_emit(cs, state->index_va);
2010 radeon_emit(cs, state->index_va >> 32);
2011
2012 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2013 radeon_emit(cs, state->max_index_count);
2014
2015 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2016 }
2017
2018 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2019 {
2020 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2021 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2022 uint32_t pa_sc_mode_cntl_1 =
2023 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2024 uint32_t db_count_control;
2025
2026 if(!cmd_buffer->state.active_occlusion_queries) {
2027 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2028 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2029 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2030 has_perfect_queries) {
2031 /* Re-enable out-of-order rasterization if the
2032 * bound pipeline supports it and if it's has
2033 * been disabled before starting any perfect
2034 * occlusion queries.
2035 */
2036 radeon_set_context_reg(cmd_buffer->cs,
2037 R_028A4C_PA_SC_MODE_CNTL_1,
2038 pa_sc_mode_cntl_1);
2039 }
2040 }
2041 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2042 } else {
2043 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2044 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2045 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2046
2047 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2048 db_count_control =
2049 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2050 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2051 S_028004_SAMPLE_RATE(sample_rate) |
2052 S_028004_ZPASS_ENABLE(1) |
2053 S_028004_SLICE_EVEN_ENABLE(1) |
2054 S_028004_SLICE_ODD_ENABLE(1);
2055
2056 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2057 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2058 has_perfect_queries) {
2059 /* If the bound pipeline has enabled
2060 * out-of-order rasterization, we should
2061 * disable it before starting any perfect
2062 * occlusion queries.
2063 */
2064 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2065
2066 radeon_set_context_reg(cmd_buffer->cs,
2067 R_028A4C_PA_SC_MODE_CNTL_1,
2068 pa_sc_mode_cntl_1);
2069 }
2070 } else {
2071 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2072 S_028004_SAMPLE_RATE(sample_rate);
2073 }
2074 }
2075
2076 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2077
2078 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2079 }
2080
2081 static void
2082 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2083 {
2084 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2085
2086 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2087 radv_emit_viewport(cmd_buffer);
2088
2089 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2090 !cmd_buffer->device->physical_device->has_scissor_bug)
2091 radv_emit_scissor(cmd_buffer);
2092
2093 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2094 radv_emit_line_width(cmd_buffer);
2095
2096 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2097 radv_emit_blend_constants(cmd_buffer);
2098
2099 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2100 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2101 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2102 radv_emit_stencil(cmd_buffer);
2103
2104 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2105 radv_emit_depth_bounds(cmd_buffer);
2106
2107 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2108 radv_emit_depth_bias(cmd_buffer);
2109
2110 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2111 radv_emit_discard_rectangle(cmd_buffer);
2112
2113 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2114 radv_emit_sample_locations(cmd_buffer);
2115
2116 cmd_buffer->state.dirty &= ~states;
2117 }
2118
2119 static void
2120 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2121 VkPipelineBindPoint bind_point)
2122 {
2123 struct radv_descriptor_state *descriptors_state =
2124 radv_get_descriptors_state(cmd_buffer, bind_point);
2125 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2126 unsigned bo_offset;
2127
2128 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2129 set->mapped_ptr,
2130 &bo_offset))
2131 return;
2132
2133 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2134 set->va += bo_offset;
2135 }
2136
2137 static void
2138 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2139 VkPipelineBindPoint bind_point)
2140 {
2141 struct radv_descriptor_state *descriptors_state =
2142 radv_get_descriptors_state(cmd_buffer, bind_point);
2143 uint32_t size = MAX_SETS * 4;
2144 uint32_t offset;
2145 void *ptr;
2146
2147 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2148 256, &offset, &ptr))
2149 return;
2150
2151 for (unsigned i = 0; i < MAX_SETS; i++) {
2152 uint32_t *uptr = ((uint32_t *)ptr) + i;
2153 uint64_t set_va = 0;
2154 struct radv_descriptor_set *set = descriptors_state->sets[i];
2155 if (descriptors_state->valid & (1u << i))
2156 set_va = set->va;
2157 uptr[0] = set_va & 0xffffffff;
2158 }
2159
2160 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2161 va += offset;
2162
2163 if (cmd_buffer->state.pipeline) {
2164 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2165 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2166 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2167
2168 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2169 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2170 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2171
2172 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2173 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2174 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2175
2176 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2177 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2178 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2179
2180 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2181 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2182 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2183 }
2184
2185 if (cmd_buffer->state.compute_pipeline)
2186 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2187 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2188 }
2189
2190 static void
2191 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2192 VkShaderStageFlags stages)
2193 {
2194 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2195 VK_PIPELINE_BIND_POINT_COMPUTE :
2196 VK_PIPELINE_BIND_POINT_GRAPHICS;
2197 struct radv_descriptor_state *descriptors_state =
2198 radv_get_descriptors_state(cmd_buffer, bind_point);
2199 struct radv_cmd_state *state = &cmd_buffer->state;
2200 bool flush_indirect_descriptors;
2201
2202 if (!descriptors_state->dirty)
2203 return;
2204
2205 if (descriptors_state->push_dirty)
2206 radv_flush_push_descriptors(cmd_buffer, bind_point);
2207
2208 flush_indirect_descriptors =
2209 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2210 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2211 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2212 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2213
2214 if (flush_indirect_descriptors)
2215 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2216
2217 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2218 cmd_buffer->cs,
2219 MAX_SETS * MESA_SHADER_STAGES * 4);
2220
2221 if (cmd_buffer->state.pipeline) {
2222 radv_foreach_stage(stage, stages) {
2223 if (!cmd_buffer->state.pipeline->shaders[stage])
2224 continue;
2225
2226 radv_emit_descriptor_pointers(cmd_buffer,
2227 cmd_buffer->state.pipeline,
2228 descriptors_state, stage);
2229 }
2230 }
2231
2232 if (cmd_buffer->state.compute_pipeline &&
2233 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2234 radv_emit_descriptor_pointers(cmd_buffer,
2235 cmd_buffer->state.compute_pipeline,
2236 descriptors_state,
2237 MESA_SHADER_COMPUTE);
2238 }
2239
2240 descriptors_state->dirty = 0;
2241 descriptors_state->push_dirty = false;
2242
2243 assert(cmd_buffer->cs->cdw <= cdw_max);
2244
2245 if (unlikely(cmd_buffer->device->trace_bo))
2246 radv_save_descriptors(cmd_buffer, bind_point);
2247 }
2248
2249 static void
2250 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2251 VkShaderStageFlags stages)
2252 {
2253 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2254 ? cmd_buffer->state.compute_pipeline
2255 : cmd_buffer->state.pipeline;
2256 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2257 VK_PIPELINE_BIND_POINT_COMPUTE :
2258 VK_PIPELINE_BIND_POINT_GRAPHICS;
2259 struct radv_descriptor_state *descriptors_state =
2260 radv_get_descriptors_state(cmd_buffer, bind_point);
2261 struct radv_pipeline_layout *layout = pipeline->layout;
2262 struct radv_shader_variant *shader, *prev_shader;
2263 bool need_push_constants = false;
2264 unsigned offset;
2265 void *ptr;
2266 uint64_t va;
2267
2268 stages &= cmd_buffer->push_constant_stages;
2269 if (!stages ||
2270 (!layout->push_constant_size && !layout->dynamic_offset_count))
2271 return;
2272
2273 radv_foreach_stage(stage, stages) {
2274 if (!pipeline->shaders[stage])
2275 continue;
2276
2277 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
2278 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
2279
2280 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
2281 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
2282
2283 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2284 AC_UD_INLINE_PUSH_CONSTANTS,
2285 count,
2286 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2287 }
2288
2289 if (need_push_constants) {
2290 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2291 16 * layout->dynamic_offset_count,
2292 256, &offset, &ptr))
2293 return;
2294
2295 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2296 memcpy((char*)ptr + layout->push_constant_size,
2297 descriptors_state->dynamic_buffers,
2298 16 * layout->dynamic_offset_count);
2299
2300 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2301 va += offset;
2302
2303 ASSERTED unsigned cdw_max =
2304 radeon_check_space(cmd_buffer->device->ws,
2305 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2306
2307 prev_shader = NULL;
2308 radv_foreach_stage(stage, stages) {
2309 shader = radv_get_shader(pipeline, stage);
2310
2311 /* Avoid redundantly emitting the address for merged stages. */
2312 if (shader && shader != prev_shader) {
2313 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2314 AC_UD_PUSH_CONSTANTS, va);
2315
2316 prev_shader = shader;
2317 }
2318 }
2319 assert(cmd_buffer->cs->cdw <= cdw_max);
2320 }
2321
2322 cmd_buffer->push_constant_stages &= ~stages;
2323 }
2324
2325 static void
2326 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2327 bool pipeline_is_dirty)
2328 {
2329 if ((pipeline_is_dirty ||
2330 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2331 cmd_buffer->state.pipeline->num_vertex_bindings &&
2332 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
2333 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2334 unsigned vb_offset;
2335 void *vb_ptr;
2336 uint32_t i = 0;
2337 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2338 uint64_t va;
2339
2340 /* allocate some descriptor state for vertex buffers */
2341 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2342 &vb_offset, &vb_ptr))
2343 return;
2344
2345 for (i = 0; i < count; i++) {
2346 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2347 uint32_t offset;
2348 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2349 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2350
2351 if (!buffer)
2352 continue;
2353
2354 va = radv_buffer_get_va(buffer->bo);
2355
2356 offset = cmd_buffer->vertex_bindings[i].offset;
2357 va += offset + buffer->offset;
2358 desc[0] = va;
2359 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2360 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2361 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2362 else
2363 desc[2] = buffer->size - offset;
2364 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2365 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2366 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2367 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2368
2369 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2370 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2371 S_008F0C_OOB_SELECT(1) |
2372 S_008F0C_RESOURCE_LEVEL(1);
2373 } else {
2374 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2375 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2376 }
2377 }
2378
2379 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2380 va += vb_offset;
2381
2382 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2383 AC_UD_VS_VERTEX_BUFFERS, va);
2384
2385 cmd_buffer->state.vb_va = va;
2386 cmd_buffer->state.vb_size = count * 16;
2387 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2388 }
2389 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2390 }
2391
2392 static void
2393 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2394 {
2395 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2396 struct radv_userdata_info *loc;
2397 uint32_t base_reg;
2398
2399 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2400 if (!radv_get_shader(pipeline, stage))
2401 continue;
2402
2403 loc = radv_lookup_user_sgpr(pipeline, stage,
2404 AC_UD_STREAMOUT_BUFFERS);
2405 if (loc->sgpr_idx == -1)
2406 continue;
2407
2408 base_reg = pipeline->user_data_0[stage];
2409
2410 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2411 base_reg + loc->sgpr_idx * 4, va, false);
2412 }
2413
2414 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2415 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2416 if (loc->sgpr_idx != -1) {
2417 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2418
2419 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2420 base_reg + loc->sgpr_idx * 4, va, false);
2421 }
2422 }
2423 }
2424
2425 static void
2426 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2427 {
2428 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2429 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2430 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2431 unsigned so_offset;
2432 void *so_ptr;
2433 uint64_t va;
2434
2435 /* Allocate some descriptor state for streamout buffers. */
2436 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2437 MAX_SO_BUFFERS * 16, 256,
2438 &so_offset, &so_ptr))
2439 return;
2440
2441 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2442 struct radv_buffer *buffer = sb[i].buffer;
2443 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2444
2445 if (!(so->enabled_mask & (1 << i)))
2446 continue;
2447
2448 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2449
2450 va += sb[i].offset;
2451
2452 /* Set the descriptor.
2453 *
2454 * On GFX8, the format must be non-INVALID, otherwise
2455 * the buffer will be considered not bound and store
2456 * instructions will be no-ops.
2457 */
2458 desc[0] = va;
2459 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2460 desc[2] = 0xffffffff;
2461 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2462 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2463 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2464 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2465
2466 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2467 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2468 S_008F0C_OOB_SELECT(3) |
2469 S_008F0C_RESOURCE_LEVEL(1);
2470 } else {
2471 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2472 }
2473 }
2474
2475 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2476 va += so_offset;
2477
2478 radv_emit_streamout_buffers(cmd_buffer, va);
2479 }
2480
2481 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2482 }
2483
2484 static void
2485 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2486 {
2487 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2488 radv_flush_streamout_descriptors(cmd_buffer);
2489 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2490 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2491 }
2492
2493 struct radv_draw_info {
2494 /**
2495 * Number of vertices.
2496 */
2497 uint32_t count;
2498
2499 /**
2500 * Index of the first vertex.
2501 */
2502 int32_t vertex_offset;
2503
2504 /**
2505 * First instance id.
2506 */
2507 uint32_t first_instance;
2508
2509 /**
2510 * Number of instances.
2511 */
2512 uint32_t instance_count;
2513
2514 /**
2515 * First index (indexed draws only).
2516 */
2517 uint32_t first_index;
2518
2519 /**
2520 * Whether it's an indexed draw.
2521 */
2522 bool indexed;
2523
2524 /**
2525 * Indirect draw parameters resource.
2526 */
2527 struct radv_buffer *indirect;
2528 uint64_t indirect_offset;
2529 uint32_t stride;
2530
2531 /**
2532 * Draw count parameters resource.
2533 */
2534 struct radv_buffer *count_buffer;
2535 uint64_t count_buffer_offset;
2536
2537 /**
2538 * Stream output parameters resource.
2539 */
2540 struct radv_buffer *strmout_buffer;
2541 uint64_t strmout_buffer_offset;
2542 };
2543
2544 static uint32_t
2545 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2546 {
2547 switch (cmd_buffer->state.index_type) {
2548 case V_028A7C_VGT_INDEX_8:
2549 return 0xffu;
2550 case V_028A7C_VGT_INDEX_16:
2551 return 0xffffu;
2552 case V_028A7C_VGT_INDEX_32:
2553 return 0xffffffffu;
2554 default:
2555 unreachable("invalid index type");
2556 }
2557 }
2558
2559 static void
2560 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2561 bool instanced_draw, bool indirect_draw,
2562 bool count_from_stream_output,
2563 uint32_t draw_vertex_count)
2564 {
2565 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2566 struct radv_cmd_state *state = &cmd_buffer->state;
2567 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2568 unsigned ia_multi_vgt_param;
2569
2570 ia_multi_vgt_param =
2571 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2572 indirect_draw,
2573 count_from_stream_output,
2574 draw_vertex_count);
2575
2576 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2577 if (info->chip_class == GFX9) {
2578 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2579 cs,
2580 R_030960_IA_MULTI_VGT_PARAM,
2581 4, ia_multi_vgt_param);
2582 } else if (info->chip_class >= GFX7) {
2583 radeon_set_context_reg_idx(cs,
2584 R_028AA8_IA_MULTI_VGT_PARAM,
2585 1, ia_multi_vgt_param);
2586 } else {
2587 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2588 ia_multi_vgt_param);
2589 }
2590 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2591 }
2592 }
2593
2594 static void
2595 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2596 const struct radv_draw_info *draw_info)
2597 {
2598 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2599 struct radv_cmd_state *state = &cmd_buffer->state;
2600 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2601 int32_t primitive_reset_en;
2602
2603 /* Draw state. */
2604 if (info->chip_class < GFX10) {
2605 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2606 draw_info->indirect,
2607 !!draw_info->strmout_buffer,
2608 draw_info->indirect ? 0 : draw_info->count);
2609 }
2610
2611 /* Primitive restart. */
2612 primitive_reset_en =
2613 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2614
2615 if (primitive_reset_en != state->last_primitive_reset_en) {
2616 state->last_primitive_reset_en = primitive_reset_en;
2617 if (info->chip_class >= GFX9) {
2618 radeon_set_uconfig_reg(cs,
2619 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2620 primitive_reset_en);
2621 } else {
2622 radeon_set_context_reg(cs,
2623 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2624 primitive_reset_en);
2625 }
2626 }
2627
2628 if (primitive_reset_en) {
2629 uint32_t primitive_reset_index =
2630 radv_get_primitive_reset_index(cmd_buffer);
2631
2632 if (primitive_reset_index != state->last_primitive_reset_index) {
2633 radeon_set_context_reg(cs,
2634 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2635 primitive_reset_index);
2636 state->last_primitive_reset_index = primitive_reset_index;
2637 }
2638 }
2639
2640 if (draw_info->strmout_buffer) {
2641 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2642
2643 va += draw_info->strmout_buffer->offset +
2644 draw_info->strmout_buffer_offset;
2645
2646 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2647 draw_info->stride);
2648
2649 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2650 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2651 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2652 COPY_DATA_WR_CONFIRM);
2653 radeon_emit(cs, va);
2654 radeon_emit(cs, va >> 32);
2655 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2656 radeon_emit(cs, 0); /* unused */
2657
2658 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2659 }
2660 }
2661
2662 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2663 VkPipelineStageFlags src_stage_mask)
2664 {
2665 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2666 VK_PIPELINE_STAGE_TRANSFER_BIT |
2667 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2668 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2669 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2670 }
2671
2672 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2673 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2674 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2675 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2676 VK_PIPELINE_STAGE_TRANSFER_BIT |
2677 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2678 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2679 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2680 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2681 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2682 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2683 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2684 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2685 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2686 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2687 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2688 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2689 }
2690 }
2691
2692 static enum radv_cmd_flush_bits
2693 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2694 VkAccessFlags src_flags,
2695 struct radv_image *image)
2696 {
2697 bool flush_CB_meta = true, flush_DB_meta = true;
2698 enum radv_cmd_flush_bits flush_bits = 0;
2699 uint32_t b;
2700
2701 if (image) {
2702 if (!radv_image_has_CB_metadata(image))
2703 flush_CB_meta = false;
2704 if (!radv_image_has_htile(image))
2705 flush_DB_meta = false;
2706 }
2707
2708 for_each_bit(b, src_flags) {
2709 switch ((VkAccessFlagBits)(1 << b)) {
2710 case VK_ACCESS_SHADER_WRITE_BIT:
2711 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2712 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2713 flush_bits |= RADV_CMD_FLAG_WB_L2;
2714 break;
2715 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2716 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2717 if (flush_CB_meta)
2718 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2719 break;
2720 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2721 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2722 if (flush_DB_meta)
2723 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2724 break;
2725 case VK_ACCESS_TRANSFER_WRITE_BIT:
2726 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2727 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2728 RADV_CMD_FLAG_INV_L2;
2729
2730 if (flush_CB_meta)
2731 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2732 if (flush_DB_meta)
2733 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2734 break;
2735 default:
2736 break;
2737 }
2738 }
2739 return flush_bits;
2740 }
2741
2742 static enum radv_cmd_flush_bits
2743 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2744 VkAccessFlags dst_flags,
2745 struct radv_image *image)
2746 {
2747 bool flush_CB_meta = true, flush_DB_meta = true;
2748 enum radv_cmd_flush_bits flush_bits = 0;
2749 bool flush_CB = true, flush_DB = true;
2750 bool image_is_coherent = false;
2751 uint32_t b;
2752
2753 if (image) {
2754 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2755 flush_CB = false;
2756 flush_DB = false;
2757 }
2758
2759 if (!radv_image_has_CB_metadata(image))
2760 flush_CB_meta = false;
2761 if (!radv_image_has_htile(image))
2762 flush_DB_meta = false;
2763
2764 /* TODO: implement shader coherent for GFX10 */
2765
2766 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2767 if (image->info.samples == 1 &&
2768 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2769 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2770 !vk_format_is_stencil(image->vk_format)) {
2771 /* Single-sample color and single-sample depth
2772 * (not stencil) are coherent with shaders on
2773 * GFX9.
2774 */
2775 image_is_coherent = true;
2776 }
2777 }
2778 }
2779
2780 for_each_bit(b, dst_flags) {
2781 switch ((VkAccessFlagBits)(1 << b)) {
2782 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2783 case VK_ACCESS_INDEX_READ_BIT:
2784 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2785 break;
2786 case VK_ACCESS_UNIFORM_READ_BIT:
2787 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2788 break;
2789 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2790 case VK_ACCESS_TRANSFER_READ_BIT:
2791 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2792 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2793 RADV_CMD_FLAG_INV_L2;
2794 break;
2795 case VK_ACCESS_SHADER_READ_BIT:
2796 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2797
2798 if (!image_is_coherent)
2799 flush_bits |= RADV_CMD_FLAG_INV_L2;
2800 break;
2801 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2802 if (flush_CB)
2803 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2804 if (flush_CB_meta)
2805 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2806 break;
2807 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2808 if (flush_DB)
2809 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2810 if (flush_DB_meta)
2811 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2812 break;
2813 default:
2814 break;
2815 }
2816 }
2817 return flush_bits;
2818 }
2819
2820 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2821 const struct radv_subpass_barrier *barrier)
2822 {
2823 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2824 NULL);
2825 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2826 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2827 NULL);
2828 }
2829
2830 uint32_t
2831 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2832 {
2833 struct radv_cmd_state *state = &cmd_buffer->state;
2834 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2835
2836 /* The id of this subpass shouldn't exceed the number of subpasses in
2837 * this render pass minus 1.
2838 */
2839 assert(subpass_id < state->pass->subpass_count);
2840 return subpass_id;
2841 }
2842
2843 static struct radv_sample_locations_state *
2844 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2845 uint32_t att_idx,
2846 bool begin_subpass)
2847 {
2848 struct radv_cmd_state *state = &cmd_buffer->state;
2849 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2850 struct radv_image_view *view = state->framebuffer->attachments[att_idx].attachment;
2851
2852 if (view->image->info.samples == 1)
2853 return NULL;
2854
2855 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2856 /* Return the initial sample locations if this is the initial
2857 * layout transition of the given subpass attachemnt.
2858 */
2859 if (state->attachments[att_idx].sample_location.count > 0)
2860 return &state->attachments[att_idx].sample_location;
2861 } else {
2862 /* Otherwise return the subpass sample locations if defined. */
2863 if (state->subpass_sample_locs) {
2864 /* Because the driver sets the current subpass before
2865 * initial layout transitions, we should use the sample
2866 * locations from the previous subpass to avoid an
2867 * off-by-one problem. Otherwise, use the sample
2868 * locations for the current subpass for final layout
2869 * transitions.
2870 */
2871 if (begin_subpass)
2872 subpass_id--;
2873
2874 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2875 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2876 return &state->subpass_sample_locs[i].sample_location;
2877 }
2878 }
2879 }
2880
2881 return NULL;
2882 }
2883
2884 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2885 struct radv_subpass_attachment att,
2886 bool begin_subpass)
2887 {
2888 unsigned idx = att.attachment;
2889 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2890 struct radv_sample_locations_state *sample_locs;
2891 VkImageSubresourceRange range;
2892 range.aspectMask = 0;
2893 range.baseMipLevel = view->base_mip;
2894 range.levelCount = 1;
2895 range.baseArrayLayer = view->base_layer;
2896 range.layerCount = cmd_buffer->state.framebuffer->layers;
2897
2898 if (cmd_buffer->state.subpass->view_mask) {
2899 /* If the current subpass uses multiview, the driver might have
2900 * performed a fast color/depth clear to the whole image
2901 * (including all layers). To make sure the driver will
2902 * decompress the image correctly (if needed), we have to
2903 * account for the "real" number of layers. If the view mask is
2904 * sparse, this will decompress more layers than needed.
2905 */
2906 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2907 }
2908
2909 /* Get the subpass sample locations for the given attachment, if NULL
2910 * is returned the driver will use the default HW locations.
2911 */
2912 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2913 begin_subpass);
2914
2915 radv_handle_image_transition(cmd_buffer,
2916 view->image,
2917 cmd_buffer->state.attachments[idx].current_layout,
2918 att.layout, 0, 0, &range, sample_locs);
2919
2920 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2921
2922
2923 }
2924
2925 void
2926 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2927 const struct radv_subpass *subpass)
2928 {
2929 cmd_buffer->state.subpass = subpass;
2930
2931 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2932 }
2933
2934 static VkResult
2935 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2936 struct radv_render_pass *pass,
2937 const VkRenderPassBeginInfo *info)
2938 {
2939 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2940 vk_find_struct_const(info->pNext,
2941 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
2942 struct radv_cmd_state *state = &cmd_buffer->state;
2943 struct radv_framebuffer *framebuffer = state->framebuffer;
2944
2945 if (!sample_locs) {
2946 state->subpass_sample_locs = NULL;
2947 return VK_SUCCESS;
2948 }
2949
2950 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
2951 const VkAttachmentSampleLocationsEXT *att_sample_locs =
2952 &sample_locs->pAttachmentInitialSampleLocations[i];
2953 uint32_t att_idx = att_sample_locs->attachmentIndex;
2954 struct radv_attachment_info *att = &framebuffer->attachments[att_idx];
2955 struct radv_image *image = att->attachment->image;
2956
2957 assert(vk_format_is_depth_or_stencil(image->vk_format));
2958
2959 /* From the Vulkan spec 1.1.108:
2960 *
2961 * "If the image referenced by the framebuffer attachment at
2962 * index attachmentIndex was not created with
2963 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2964 * then the values specified in sampleLocationsInfo are
2965 * ignored."
2966 */
2967 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
2968 continue;
2969
2970 const VkSampleLocationsInfoEXT *sample_locs_info =
2971 &att_sample_locs->sampleLocationsInfo;
2972
2973 state->attachments[att_idx].sample_location.per_pixel =
2974 sample_locs_info->sampleLocationsPerPixel;
2975 state->attachments[att_idx].sample_location.grid_size =
2976 sample_locs_info->sampleLocationGridSize;
2977 state->attachments[att_idx].sample_location.count =
2978 sample_locs_info->sampleLocationsCount;
2979 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
2980 sample_locs_info->pSampleLocations,
2981 sample_locs_info->sampleLocationsCount);
2982 }
2983
2984 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
2985 sample_locs->postSubpassSampleLocationsCount *
2986 sizeof(state->subpass_sample_locs[0]),
2987 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2988 if (state->subpass_sample_locs == NULL) {
2989 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2990 return cmd_buffer->record_result;
2991 }
2992
2993 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
2994
2995 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
2996 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
2997 &sample_locs->pPostSubpassSampleLocations[i];
2998 const VkSampleLocationsInfoEXT *sample_locs_info =
2999 &subpass_sample_locs_info->sampleLocationsInfo;
3000
3001 state->subpass_sample_locs[i].subpass_idx =
3002 subpass_sample_locs_info->subpassIndex;
3003 state->subpass_sample_locs[i].sample_location.per_pixel =
3004 sample_locs_info->sampleLocationsPerPixel;
3005 state->subpass_sample_locs[i].sample_location.grid_size =
3006 sample_locs_info->sampleLocationGridSize;
3007 state->subpass_sample_locs[i].sample_location.count =
3008 sample_locs_info->sampleLocationsCount;
3009 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3010 sample_locs_info->pSampleLocations,
3011 sample_locs_info->sampleLocationsCount);
3012 }
3013
3014 return VK_SUCCESS;
3015 }
3016
3017 static VkResult
3018 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3019 struct radv_render_pass *pass,
3020 const VkRenderPassBeginInfo *info)
3021 {
3022 struct radv_cmd_state *state = &cmd_buffer->state;
3023
3024 if (pass->attachment_count == 0) {
3025 state->attachments = NULL;
3026 return VK_SUCCESS;
3027 }
3028
3029 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3030 pass->attachment_count *
3031 sizeof(state->attachments[0]),
3032 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3033 if (state->attachments == NULL) {
3034 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3035 return cmd_buffer->record_result;
3036 }
3037
3038 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3039 struct radv_render_pass_attachment *att = &pass->attachments[i];
3040 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3041 VkImageAspectFlags clear_aspects = 0;
3042
3043 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3044 /* color attachment */
3045 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3046 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3047 }
3048 } else {
3049 /* depthstencil attachment */
3050 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3051 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3052 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3053 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3054 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3055 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3056 }
3057 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3058 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3059 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3060 }
3061 }
3062
3063 state->attachments[i].pending_clear_aspects = clear_aspects;
3064 state->attachments[i].cleared_views = 0;
3065 if (clear_aspects && info) {
3066 assert(info->clearValueCount > i);
3067 state->attachments[i].clear_value = info->pClearValues[i];
3068 }
3069
3070 state->attachments[i].current_layout = att->initial_layout;
3071 state->attachments[i].sample_location.count = 0;
3072 }
3073
3074 return VK_SUCCESS;
3075 }
3076
3077 VkResult radv_AllocateCommandBuffers(
3078 VkDevice _device,
3079 const VkCommandBufferAllocateInfo *pAllocateInfo,
3080 VkCommandBuffer *pCommandBuffers)
3081 {
3082 RADV_FROM_HANDLE(radv_device, device, _device);
3083 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3084
3085 VkResult result = VK_SUCCESS;
3086 uint32_t i;
3087
3088 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3089
3090 if (!list_empty(&pool->free_cmd_buffers)) {
3091 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3092
3093 list_del(&cmd_buffer->pool_link);
3094 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3095
3096 result = radv_reset_cmd_buffer(cmd_buffer);
3097 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3098 cmd_buffer->level = pAllocateInfo->level;
3099
3100 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3101 } else {
3102 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3103 &pCommandBuffers[i]);
3104 }
3105 if (result != VK_SUCCESS)
3106 break;
3107 }
3108
3109 if (result != VK_SUCCESS) {
3110 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3111 i, pCommandBuffers);
3112
3113 /* From the Vulkan 1.0.66 spec:
3114 *
3115 * "vkAllocateCommandBuffers can be used to create multiple
3116 * command buffers. If the creation of any of those command
3117 * buffers fails, the implementation must destroy all
3118 * successfully created command buffer objects from this
3119 * command, set all entries of the pCommandBuffers array to
3120 * NULL and return the error."
3121 */
3122 memset(pCommandBuffers, 0,
3123 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3124 }
3125
3126 return result;
3127 }
3128
3129 void radv_FreeCommandBuffers(
3130 VkDevice device,
3131 VkCommandPool commandPool,
3132 uint32_t commandBufferCount,
3133 const VkCommandBuffer *pCommandBuffers)
3134 {
3135 for (uint32_t i = 0; i < commandBufferCount; i++) {
3136 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3137
3138 if (cmd_buffer) {
3139 if (cmd_buffer->pool) {
3140 list_del(&cmd_buffer->pool_link);
3141 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3142 } else
3143 radv_cmd_buffer_destroy(cmd_buffer);
3144
3145 }
3146 }
3147 }
3148
3149 VkResult radv_ResetCommandBuffer(
3150 VkCommandBuffer commandBuffer,
3151 VkCommandBufferResetFlags flags)
3152 {
3153 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3154 return radv_reset_cmd_buffer(cmd_buffer);
3155 }
3156
3157 VkResult radv_BeginCommandBuffer(
3158 VkCommandBuffer commandBuffer,
3159 const VkCommandBufferBeginInfo *pBeginInfo)
3160 {
3161 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3162 VkResult result = VK_SUCCESS;
3163
3164 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3165 /* If the command buffer has already been resetted with
3166 * vkResetCommandBuffer, no need to do it again.
3167 */
3168 result = radv_reset_cmd_buffer(cmd_buffer);
3169 if (result != VK_SUCCESS)
3170 return result;
3171 }
3172
3173 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3174 cmd_buffer->state.last_primitive_reset_en = -1;
3175 cmd_buffer->state.last_index_type = -1;
3176 cmd_buffer->state.last_num_instances = -1;
3177 cmd_buffer->state.last_vertex_offset = -1;
3178 cmd_buffer->state.last_first_instance = -1;
3179 cmd_buffer->state.predication_type = -1;
3180 cmd_buffer->usage_flags = pBeginInfo->flags;
3181
3182 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3183 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3184 assert(pBeginInfo->pInheritanceInfo);
3185 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3186 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3187
3188 struct radv_subpass *subpass =
3189 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3190
3191 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3192 if (result != VK_SUCCESS)
3193 return result;
3194
3195 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3196 }
3197
3198 if (unlikely(cmd_buffer->device->trace_bo)) {
3199 struct radv_device *device = cmd_buffer->device;
3200
3201 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3202 device->trace_bo);
3203
3204 radv_cmd_buffer_trace_emit(cmd_buffer);
3205 }
3206
3207 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3208
3209 return result;
3210 }
3211
3212 void radv_CmdBindVertexBuffers(
3213 VkCommandBuffer commandBuffer,
3214 uint32_t firstBinding,
3215 uint32_t bindingCount,
3216 const VkBuffer* pBuffers,
3217 const VkDeviceSize* pOffsets)
3218 {
3219 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3220 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3221 bool changed = false;
3222
3223 /* We have to defer setting up vertex buffer since we need the buffer
3224 * stride from the pipeline. */
3225
3226 assert(firstBinding + bindingCount <= MAX_VBS);
3227 for (uint32_t i = 0; i < bindingCount; i++) {
3228 uint32_t idx = firstBinding + i;
3229
3230 if (!changed &&
3231 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3232 vb[idx].offset != pOffsets[i])) {
3233 changed = true;
3234 }
3235
3236 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3237 vb[idx].offset = pOffsets[i];
3238
3239 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3240 vb[idx].buffer->bo);
3241 }
3242
3243 if (!changed) {
3244 /* No state changes. */
3245 return;
3246 }
3247
3248 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3249 }
3250
3251 static uint32_t
3252 vk_to_index_type(VkIndexType type)
3253 {
3254 switch (type) {
3255 case VK_INDEX_TYPE_UINT8_EXT:
3256 return V_028A7C_VGT_INDEX_8;
3257 case VK_INDEX_TYPE_UINT16:
3258 return V_028A7C_VGT_INDEX_16;
3259 case VK_INDEX_TYPE_UINT32:
3260 return V_028A7C_VGT_INDEX_32;
3261 default:
3262 unreachable("invalid index type");
3263 }
3264 }
3265
3266 static uint32_t
3267 radv_get_vgt_index_size(uint32_t type)
3268 {
3269 switch (type) {
3270 case V_028A7C_VGT_INDEX_8:
3271 return 1;
3272 case V_028A7C_VGT_INDEX_16:
3273 return 2;
3274 case V_028A7C_VGT_INDEX_32:
3275 return 4;
3276 default:
3277 unreachable("invalid index type");
3278 }
3279 }
3280
3281 void radv_CmdBindIndexBuffer(
3282 VkCommandBuffer commandBuffer,
3283 VkBuffer buffer,
3284 VkDeviceSize offset,
3285 VkIndexType indexType)
3286 {
3287 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3288 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3289
3290 if (cmd_buffer->state.index_buffer == index_buffer &&
3291 cmd_buffer->state.index_offset == offset &&
3292 cmd_buffer->state.index_type == indexType) {
3293 /* No state changes. */
3294 return;
3295 }
3296
3297 cmd_buffer->state.index_buffer = index_buffer;
3298 cmd_buffer->state.index_offset = offset;
3299 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3300 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3301 cmd_buffer->state.index_va += index_buffer->offset + offset;
3302
3303 int index_size = radv_get_vgt_index_size(indexType);
3304 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3305 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3306 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3307 }
3308
3309
3310 static void
3311 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3312 VkPipelineBindPoint bind_point,
3313 struct radv_descriptor_set *set, unsigned idx)
3314 {
3315 struct radeon_winsys *ws = cmd_buffer->device->ws;
3316
3317 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3318
3319 assert(set);
3320 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3321
3322 if (!cmd_buffer->device->use_global_bo_list) {
3323 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3324 if (set->descriptors[j])
3325 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3326 }
3327
3328 if(set->bo)
3329 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3330 }
3331
3332 void radv_CmdBindDescriptorSets(
3333 VkCommandBuffer commandBuffer,
3334 VkPipelineBindPoint pipelineBindPoint,
3335 VkPipelineLayout _layout,
3336 uint32_t firstSet,
3337 uint32_t descriptorSetCount,
3338 const VkDescriptorSet* pDescriptorSets,
3339 uint32_t dynamicOffsetCount,
3340 const uint32_t* pDynamicOffsets)
3341 {
3342 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3343 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3344 unsigned dyn_idx = 0;
3345
3346 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3347 struct radv_descriptor_state *descriptors_state =
3348 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3349
3350 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3351 unsigned idx = i + firstSet;
3352 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3353 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3354
3355 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3356 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3357 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3358 assert(dyn_idx < dynamicOffsetCount);
3359
3360 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3361 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3362 dst[0] = va;
3363 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3364 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3365 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3366 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3367 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3368 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3369
3370 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3371 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3372 S_008F0C_OOB_SELECT(3) |
3373 S_008F0C_RESOURCE_LEVEL(1);
3374 } else {
3375 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3376 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3377 }
3378
3379 cmd_buffer->push_constant_stages |=
3380 set->layout->dynamic_shader_stages;
3381 }
3382 }
3383 }
3384
3385 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3386 struct radv_descriptor_set *set,
3387 struct radv_descriptor_set_layout *layout,
3388 VkPipelineBindPoint bind_point)
3389 {
3390 struct radv_descriptor_state *descriptors_state =
3391 radv_get_descriptors_state(cmd_buffer, bind_point);
3392 set->size = layout->size;
3393 set->layout = layout;
3394
3395 if (descriptors_state->push_set.capacity < set->size) {
3396 size_t new_size = MAX2(set->size, 1024);
3397 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3398 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3399
3400 free(set->mapped_ptr);
3401 set->mapped_ptr = malloc(new_size);
3402
3403 if (!set->mapped_ptr) {
3404 descriptors_state->push_set.capacity = 0;
3405 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3406 return false;
3407 }
3408
3409 descriptors_state->push_set.capacity = new_size;
3410 }
3411
3412 return true;
3413 }
3414
3415 void radv_meta_push_descriptor_set(
3416 struct radv_cmd_buffer* cmd_buffer,
3417 VkPipelineBindPoint pipelineBindPoint,
3418 VkPipelineLayout _layout,
3419 uint32_t set,
3420 uint32_t descriptorWriteCount,
3421 const VkWriteDescriptorSet* pDescriptorWrites)
3422 {
3423 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3424 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3425 unsigned bo_offset;
3426
3427 assert(set == 0);
3428 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3429
3430 push_set->size = layout->set[set].layout->size;
3431 push_set->layout = layout->set[set].layout;
3432
3433 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3434 &bo_offset,
3435 (void**) &push_set->mapped_ptr))
3436 return;
3437
3438 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3439 push_set->va += bo_offset;
3440
3441 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3442 radv_descriptor_set_to_handle(push_set),
3443 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3444
3445 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3446 }
3447
3448 void radv_CmdPushDescriptorSetKHR(
3449 VkCommandBuffer commandBuffer,
3450 VkPipelineBindPoint pipelineBindPoint,
3451 VkPipelineLayout _layout,
3452 uint32_t set,
3453 uint32_t descriptorWriteCount,
3454 const VkWriteDescriptorSet* pDescriptorWrites)
3455 {
3456 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3457 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3458 struct radv_descriptor_state *descriptors_state =
3459 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3460 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3461
3462 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3463
3464 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3465 layout->set[set].layout,
3466 pipelineBindPoint))
3467 return;
3468
3469 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3470 * because it is invalid, according to Vulkan spec.
3471 */
3472 for (int i = 0; i < descriptorWriteCount; i++) {
3473 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3474 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3475 }
3476
3477 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3478 radv_descriptor_set_to_handle(push_set),
3479 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3480
3481 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3482 descriptors_state->push_dirty = true;
3483 }
3484
3485 void radv_CmdPushDescriptorSetWithTemplateKHR(
3486 VkCommandBuffer commandBuffer,
3487 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3488 VkPipelineLayout _layout,
3489 uint32_t set,
3490 const void* pData)
3491 {
3492 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3493 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3494 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3495 struct radv_descriptor_state *descriptors_state =
3496 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3497 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3498
3499 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3500
3501 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3502 layout->set[set].layout,
3503 templ->bind_point))
3504 return;
3505
3506 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3507 descriptorUpdateTemplate, pData);
3508
3509 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3510 descriptors_state->push_dirty = true;
3511 }
3512
3513 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3514 VkPipelineLayout layout,
3515 VkShaderStageFlags stageFlags,
3516 uint32_t offset,
3517 uint32_t size,
3518 const void* pValues)
3519 {
3520 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3521 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3522 cmd_buffer->push_constant_stages |= stageFlags;
3523 }
3524
3525 VkResult radv_EndCommandBuffer(
3526 VkCommandBuffer commandBuffer)
3527 {
3528 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3529
3530 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3531 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3532 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3533
3534 /* Make sure to sync all pending active queries at the end of
3535 * command buffer.
3536 */
3537 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3538
3539 si_emit_cache_flush(cmd_buffer);
3540 }
3541
3542 /* Make sure CP DMA is idle at the end of IBs because the kernel
3543 * doesn't wait for it.
3544 */
3545 si_cp_dma_wait_for_idle(cmd_buffer);
3546
3547 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3548 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3549
3550 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3551 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3552
3553 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3554
3555 return cmd_buffer->record_result;
3556 }
3557
3558 static void
3559 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3560 {
3561 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3562
3563 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3564 return;
3565
3566 assert(!pipeline->ctx_cs.cdw);
3567
3568 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3569
3570 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3571 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3572
3573 cmd_buffer->compute_scratch_size_needed =
3574 MAX2(cmd_buffer->compute_scratch_size_needed,
3575 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3576
3577 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3578 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3579
3580 if (unlikely(cmd_buffer->device->trace_bo))
3581 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3582 }
3583
3584 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3585 VkPipelineBindPoint bind_point)
3586 {
3587 struct radv_descriptor_state *descriptors_state =
3588 radv_get_descriptors_state(cmd_buffer, bind_point);
3589
3590 descriptors_state->dirty |= descriptors_state->valid;
3591 }
3592
3593 void radv_CmdBindPipeline(
3594 VkCommandBuffer commandBuffer,
3595 VkPipelineBindPoint pipelineBindPoint,
3596 VkPipeline _pipeline)
3597 {
3598 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3599 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3600
3601 switch (pipelineBindPoint) {
3602 case VK_PIPELINE_BIND_POINT_COMPUTE:
3603 if (cmd_buffer->state.compute_pipeline == pipeline)
3604 return;
3605 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3606
3607 cmd_buffer->state.compute_pipeline = pipeline;
3608 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3609 break;
3610 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3611 if (cmd_buffer->state.pipeline == pipeline)
3612 return;
3613 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3614
3615 cmd_buffer->state.pipeline = pipeline;
3616 if (!pipeline)
3617 break;
3618
3619 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3620 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3621
3622 /* the new vertex shader might not have the same user regs */
3623 cmd_buffer->state.last_first_instance = -1;
3624 cmd_buffer->state.last_vertex_offset = -1;
3625
3626 /* Prefetch all pipeline shaders at first draw time. */
3627 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3628
3629 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3630 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3631 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3632 cmd_buffer->state.emitted_pipeline &&
3633 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3634 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3635 /* Transitioning from NGG to legacy GS requires
3636 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3637 * at the beginning of IBs when legacy GS ring pointers
3638 * are set.
3639 */
3640 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3641 }
3642
3643 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3644 radv_bind_streamout_state(cmd_buffer, pipeline);
3645
3646 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3647 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3648 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3649 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3650
3651 if (radv_pipeline_has_tess(pipeline))
3652 cmd_buffer->tess_rings_needed = true;
3653 break;
3654 default:
3655 assert(!"invalid bind point");
3656 break;
3657 }
3658 }
3659
3660 void radv_CmdSetViewport(
3661 VkCommandBuffer commandBuffer,
3662 uint32_t firstViewport,
3663 uint32_t viewportCount,
3664 const VkViewport* pViewports)
3665 {
3666 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3667 struct radv_cmd_state *state = &cmd_buffer->state;
3668 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3669
3670 assert(firstViewport < MAX_VIEWPORTS);
3671 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3672
3673 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3674 pViewports, viewportCount * sizeof(*pViewports))) {
3675 return;
3676 }
3677
3678 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3679 viewportCount * sizeof(*pViewports));
3680
3681 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3682 }
3683
3684 void radv_CmdSetScissor(
3685 VkCommandBuffer commandBuffer,
3686 uint32_t firstScissor,
3687 uint32_t scissorCount,
3688 const VkRect2D* pScissors)
3689 {
3690 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3691 struct radv_cmd_state *state = &cmd_buffer->state;
3692 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3693
3694 assert(firstScissor < MAX_SCISSORS);
3695 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3696
3697 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3698 scissorCount * sizeof(*pScissors))) {
3699 return;
3700 }
3701
3702 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3703 scissorCount * sizeof(*pScissors));
3704
3705 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3706 }
3707
3708 void radv_CmdSetLineWidth(
3709 VkCommandBuffer commandBuffer,
3710 float lineWidth)
3711 {
3712 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3713
3714 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3715 return;
3716
3717 cmd_buffer->state.dynamic.line_width = lineWidth;
3718 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3719 }
3720
3721 void radv_CmdSetDepthBias(
3722 VkCommandBuffer commandBuffer,
3723 float depthBiasConstantFactor,
3724 float depthBiasClamp,
3725 float depthBiasSlopeFactor)
3726 {
3727 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3728 struct radv_cmd_state *state = &cmd_buffer->state;
3729
3730 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3731 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3732 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3733 return;
3734 }
3735
3736 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3737 state->dynamic.depth_bias.clamp = depthBiasClamp;
3738 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3739
3740 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3741 }
3742
3743 void radv_CmdSetBlendConstants(
3744 VkCommandBuffer commandBuffer,
3745 const float blendConstants[4])
3746 {
3747 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3748 struct radv_cmd_state *state = &cmd_buffer->state;
3749
3750 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3751 return;
3752
3753 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3754
3755 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3756 }
3757
3758 void radv_CmdSetDepthBounds(
3759 VkCommandBuffer commandBuffer,
3760 float minDepthBounds,
3761 float maxDepthBounds)
3762 {
3763 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3764 struct radv_cmd_state *state = &cmd_buffer->state;
3765
3766 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3767 state->dynamic.depth_bounds.max == maxDepthBounds) {
3768 return;
3769 }
3770
3771 state->dynamic.depth_bounds.min = minDepthBounds;
3772 state->dynamic.depth_bounds.max = maxDepthBounds;
3773
3774 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3775 }
3776
3777 void radv_CmdSetStencilCompareMask(
3778 VkCommandBuffer commandBuffer,
3779 VkStencilFaceFlags faceMask,
3780 uint32_t compareMask)
3781 {
3782 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3783 struct radv_cmd_state *state = &cmd_buffer->state;
3784 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3785 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3786
3787 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3788 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3789 return;
3790 }
3791
3792 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3793 state->dynamic.stencil_compare_mask.front = compareMask;
3794 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3795 state->dynamic.stencil_compare_mask.back = compareMask;
3796
3797 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3798 }
3799
3800 void radv_CmdSetStencilWriteMask(
3801 VkCommandBuffer commandBuffer,
3802 VkStencilFaceFlags faceMask,
3803 uint32_t writeMask)
3804 {
3805 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3806 struct radv_cmd_state *state = &cmd_buffer->state;
3807 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3808 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3809
3810 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3811 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3812 return;
3813 }
3814
3815 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3816 state->dynamic.stencil_write_mask.front = writeMask;
3817 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3818 state->dynamic.stencil_write_mask.back = writeMask;
3819
3820 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3821 }
3822
3823 void radv_CmdSetStencilReference(
3824 VkCommandBuffer commandBuffer,
3825 VkStencilFaceFlags faceMask,
3826 uint32_t reference)
3827 {
3828 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3829 struct radv_cmd_state *state = &cmd_buffer->state;
3830 bool front_same = state->dynamic.stencil_reference.front == reference;
3831 bool back_same = state->dynamic.stencil_reference.back == reference;
3832
3833 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3834 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3835 return;
3836 }
3837
3838 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3839 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3840 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3841 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3842
3843 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3844 }
3845
3846 void radv_CmdSetDiscardRectangleEXT(
3847 VkCommandBuffer commandBuffer,
3848 uint32_t firstDiscardRectangle,
3849 uint32_t discardRectangleCount,
3850 const VkRect2D* pDiscardRectangles)
3851 {
3852 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3853 struct radv_cmd_state *state = &cmd_buffer->state;
3854 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3855
3856 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3857 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3858
3859 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3860 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3861 return;
3862 }
3863
3864 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3865 pDiscardRectangles, discardRectangleCount);
3866
3867 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3868 }
3869
3870 void radv_CmdSetSampleLocationsEXT(
3871 VkCommandBuffer commandBuffer,
3872 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3873 {
3874 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3875 struct radv_cmd_state *state = &cmd_buffer->state;
3876
3877 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3878
3879 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3880 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3881 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3882 typed_memcpy(&state->dynamic.sample_location.locations[0],
3883 pSampleLocationsInfo->pSampleLocations,
3884 pSampleLocationsInfo->sampleLocationsCount);
3885
3886 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3887 }
3888
3889 void radv_CmdExecuteCommands(
3890 VkCommandBuffer commandBuffer,
3891 uint32_t commandBufferCount,
3892 const VkCommandBuffer* pCmdBuffers)
3893 {
3894 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3895
3896 assert(commandBufferCount > 0);
3897
3898 /* Emit pending flushes on primary prior to executing secondary */
3899 si_emit_cache_flush(primary);
3900
3901 for (uint32_t i = 0; i < commandBufferCount; i++) {
3902 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3903
3904 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3905 secondary->scratch_size_needed);
3906 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3907 secondary->compute_scratch_size_needed);
3908
3909 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3910 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3911 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3912 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3913 if (secondary->tess_rings_needed)
3914 primary->tess_rings_needed = true;
3915 if (secondary->sample_positions_needed)
3916 primary->sample_positions_needed = true;
3917
3918 if (!secondary->state.framebuffer &&
3919 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
3920 /* Emit the framebuffer state from primary if secondary
3921 * has been recorded without a framebuffer, otherwise
3922 * fast color/depth clears can't work.
3923 */
3924 radv_emit_framebuffer_state(primary);
3925 }
3926
3927 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3928
3929
3930 /* When the secondary command buffer is compute only we don't
3931 * need to re-emit the current graphics pipeline.
3932 */
3933 if (secondary->state.emitted_pipeline) {
3934 primary->state.emitted_pipeline =
3935 secondary->state.emitted_pipeline;
3936 }
3937
3938 /* When the secondary command buffer is graphics only we don't
3939 * need to re-emit the current compute pipeline.
3940 */
3941 if (secondary->state.emitted_compute_pipeline) {
3942 primary->state.emitted_compute_pipeline =
3943 secondary->state.emitted_compute_pipeline;
3944 }
3945
3946 /* Only re-emit the draw packets when needed. */
3947 if (secondary->state.last_primitive_reset_en != -1) {
3948 primary->state.last_primitive_reset_en =
3949 secondary->state.last_primitive_reset_en;
3950 }
3951
3952 if (secondary->state.last_primitive_reset_index) {
3953 primary->state.last_primitive_reset_index =
3954 secondary->state.last_primitive_reset_index;
3955 }
3956
3957 if (secondary->state.last_ia_multi_vgt_param) {
3958 primary->state.last_ia_multi_vgt_param =
3959 secondary->state.last_ia_multi_vgt_param;
3960 }
3961
3962 primary->state.last_first_instance = secondary->state.last_first_instance;
3963 primary->state.last_num_instances = secondary->state.last_num_instances;
3964 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3965
3966 if (secondary->state.last_index_type != -1) {
3967 primary->state.last_index_type =
3968 secondary->state.last_index_type;
3969 }
3970 }
3971
3972 /* After executing commands from secondary buffers we have to dirty
3973 * some states.
3974 */
3975 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3976 RADV_CMD_DIRTY_INDEX_BUFFER |
3977 RADV_CMD_DIRTY_DYNAMIC_ALL;
3978 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3979 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3980 }
3981
3982 VkResult radv_CreateCommandPool(
3983 VkDevice _device,
3984 const VkCommandPoolCreateInfo* pCreateInfo,
3985 const VkAllocationCallbacks* pAllocator,
3986 VkCommandPool* pCmdPool)
3987 {
3988 RADV_FROM_HANDLE(radv_device, device, _device);
3989 struct radv_cmd_pool *pool;
3990
3991 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3992 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3993 if (pool == NULL)
3994 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3995
3996 if (pAllocator)
3997 pool->alloc = *pAllocator;
3998 else
3999 pool->alloc = device->alloc;
4000
4001 list_inithead(&pool->cmd_buffers);
4002 list_inithead(&pool->free_cmd_buffers);
4003
4004 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4005
4006 *pCmdPool = radv_cmd_pool_to_handle(pool);
4007
4008 return VK_SUCCESS;
4009
4010 }
4011
4012 void radv_DestroyCommandPool(
4013 VkDevice _device,
4014 VkCommandPool commandPool,
4015 const VkAllocationCallbacks* pAllocator)
4016 {
4017 RADV_FROM_HANDLE(radv_device, device, _device);
4018 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4019
4020 if (!pool)
4021 return;
4022
4023 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4024 &pool->cmd_buffers, pool_link) {
4025 radv_cmd_buffer_destroy(cmd_buffer);
4026 }
4027
4028 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4029 &pool->free_cmd_buffers, pool_link) {
4030 radv_cmd_buffer_destroy(cmd_buffer);
4031 }
4032
4033 vk_free2(&device->alloc, pAllocator, pool);
4034 }
4035
4036 VkResult radv_ResetCommandPool(
4037 VkDevice device,
4038 VkCommandPool commandPool,
4039 VkCommandPoolResetFlags flags)
4040 {
4041 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4042 VkResult result;
4043
4044 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4045 &pool->cmd_buffers, pool_link) {
4046 result = radv_reset_cmd_buffer(cmd_buffer);
4047 if (result != VK_SUCCESS)
4048 return result;
4049 }
4050
4051 return VK_SUCCESS;
4052 }
4053
4054 void radv_TrimCommandPool(
4055 VkDevice device,
4056 VkCommandPool commandPool,
4057 VkCommandPoolTrimFlags flags)
4058 {
4059 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4060
4061 if (!pool)
4062 return;
4063
4064 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4065 &pool->free_cmd_buffers, pool_link) {
4066 radv_cmd_buffer_destroy(cmd_buffer);
4067 }
4068 }
4069
4070 static void
4071 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4072 uint32_t subpass_id)
4073 {
4074 struct radv_cmd_state *state = &cmd_buffer->state;
4075 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4076
4077 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4078 cmd_buffer->cs, 4096);
4079
4080 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4081
4082 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4083
4084 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4085 const uint32_t a = subpass->attachments[i].attachment;
4086 if (a == VK_ATTACHMENT_UNUSED)
4087 continue;
4088
4089 radv_handle_subpass_image_transition(cmd_buffer,
4090 subpass->attachments[i],
4091 true);
4092 }
4093
4094 radv_cmd_buffer_clear_subpass(cmd_buffer);
4095
4096 assert(cmd_buffer->cs->cdw <= cdw_max);
4097 }
4098
4099 static void
4100 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4101 {
4102 struct radv_cmd_state *state = &cmd_buffer->state;
4103 const struct radv_subpass *subpass = state->subpass;
4104 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4105
4106 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4107
4108 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4109 const uint32_t a = subpass->attachments[i].attachment;
4110 if (a == VK_ATTACHMENT_UNUSED)
4111 continue;
4112
4113 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4114 continue;
4115
4116 VkImageLayout layout = state->pass->attachments[a].final_layout;
4117 struct radv_subpass_attachment att = { a, layout };
4118 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4119 }
4120 }
4121
4122 void radv_CmdBeginRenderPass(
4123 VkCommandBuffer commandBuffer,
4124 const VkRenderPassBeginInfo* pRenderPassBegin,
4125 VkSubpassContents contents)
4126 {
4127 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4128 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4129 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4130 VkResult result;
4131
4132 cmd_buffer->state.framebuffer = framebuffer;
4133 cmd_buffer->state.pass = pass;
4134 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4135
4136 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4137 if (result != VK_SUCCESS)
4138 return;
4139
4140 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4141 if (result != VK_SUCCESS)
4142 return;
4143
4144 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4145 }
4146
4147 void radv_CmdBeginRenderPass2KHR(
4148 VkCommandBuffer commandBuffer,
4149 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4150 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4151 {
4152 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4153 pSubpassBeginInfo->contents);
4154 }
4155
4156 void radv_CmdNextSubpass(
4157 VkCommandBuffer commandBuffer,
4158 VkSubpassContents contents)
4159 {
4160 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4161
4162 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4163 radv_cmd_buffer_end_subpass(cmd_buffer);
4164 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4165 }
4166
4167 void radv_CmdNextSubpass2KHR(
4168 VkCommandBuffer commandBuffer,
4169 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4170 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4171 {
4172 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4173 }
4174
4175 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4176 {
4177 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4178 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4179 if (!radv_get_shader(pipeline, stage))
4180 continue;
4181
4182 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4183 if (loc->sgpr_idx == -1)
4184 continue;
4185 uint32_t base_reg = pipeline->user_data_0[stage];
4186 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4187
4188 }
4189 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4190 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4191 if (loc->sgpr_idx != -1) {
4192 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4193 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4194 }
4195 }
4196 }
4197
4198 static void
4199 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4200 uint32_t vertex_count,
4201 bool use_opaque)
4202 {
4203 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4204 radeon_emit(cmd_buffer->cs, vertex_count);
4205 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4206 S_0287F0_USE_OPAQUE(use_opaque));
4207 }
4208
4209 static void
4210 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4211 uint64_t index_va,
4212 uint32_t index_count)
4213 {
4214 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4215 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4216 radeon_emit(cmd_buffer->cs, index_va);
4217 radeon_emit(cmd_buffer->cs, index_va >> 32);
4218 radeon_emit(cmd_buffer->cs, index_count);
4219 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4220 }
4221
4222 static void
4223 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4224 bool indexed,
4225 uint32_t draw_count,
4226 uint64_t count_va,
4227 uint32_t stride)
4228 {
4229 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4230 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4231 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4232 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
4233 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4234 bool predicating = cmd_buffer->state.predicating;
4235 assert(base_reg);
4236
4237 /* just reset draw state for vertex data */
4238 cmd_buffer->state.last_first_instance = -1;
4239 cmd_buffer->state.last_num_instances = -1;
4240 cmd_buffer->state.last_vertex_offset = -1;
4241
4242 if (draw_count == 1 && !count_va && !draw_id_enable) {
4243 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4244 PKT3_DRAW_INDIRECT, 3, predicating));
4245 radeon_emit(cs, 0);
4246 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4247 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4248 radeon_emit(cs, di_src_sel);
4249 } else {
4250 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4251 PKT3_DRAW_INDIRECT_MULTI,
4252 8, predicating));
4253 radeon_emit(cs, 0);
4254 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4255 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4256 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4257 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4258 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4259 radeon_emit(cs, draw_count); /* count */
4260 radeon_emit(cs, count_va); /* count_addr */
4261 radeon_emit(cs, count_va >> 32);
4262 radeon_emit(cs, stride); /* stride */
4263 radeon_emit(cs, di_src_sel);
4264 }
4265 }
4266
4267 static void
4268 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4269 const struct radv_draw_info *info)
4270 {
4271 struct radv_cmd_state *state = &cmd_buffer->state;
4272 struct radeon_winsys *ws = cmd_buffer->device->ws;
4273 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4274
4275 if (info->indirect) {
4276 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4277 uint64_t count_va = 0;
4278
4279 va += info->indirect->offset + info->indirect_offset;
4280
4281 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4282
4283 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4284 radeon_emit(cs, 1);
4285 radeon_emit(cs, va);
4286 radeon_emit(cs, va >> 32);
4287
4288 if (info->count_buffer) {
4289 count_va = radv_buffer_get_va(info->count_buffer->bo);
4290 count_va += info->count_buffer->offset +
4291 info->count_buffer_offset;
4292
4293 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4294 }
4295
4296 if (!state->subpass->view_mask) {
4297 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4298 info->indexed,
4299 info->count,
4300 count_va,
4301 info->stride);
4302 } else {
4303 unsigned i;
4304 for_each_bit(i, state->subpass->view_mask) {
4305 radv_emit_view_index(cmd_buffer, i);
4306
4307 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4308 info->indexed,
4309 info->count,
4310 count_va,
4311 info->stride);
4312 }
4313 }
4314 } else {
4315 assert(state->pipeline->graphics.vtx_base_sgpr);
4316
4317 if (info->vertex_offset != state->last_vertex_offset ||
4318 info->first_instance != state->last_first_instance) {
4319 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4320 state->pipeline->graphics.vtx_emit_num);
4321
4322 radeon_emit(cs, info->vertex_offset);
4323 radeon_emit(cs, info->first_instance);
4324 if (state->pipeline->graphics.vtx_emit_num == 3)
4325 radeon_emit(cs, 0);
4326 state->last_first_instance = info->first_instance;
4327 state->last_vertex_offset = info->vertex_offset;
4328 }
4329
4330 if (state->last_num_instances != info->instance_count) {
4331 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4332 radeon_emit(cs, info->instance_count);
4333 state->last_num_instances = info->instance_count;
4334 }
4335
4336 if (info->indexed) {
4337 int index_size = radv_get_vgt_index_size(state->index_type);
4338 uint64_t index_va;
4339
4340 /* Skip draw calls with 0-sized index buffers. They
4341 * cause a hang on some chips, like Navi10-14.
4342 */
4343 if (!cmd_buffer->state.max_index_count)
4344 return;
4345
4346 index_va = state->index_va;
4347 index_va += info->first_index * index_size;
4348
4349 if (!state->subpass->view_mask) {
4350 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4351 index_va,
4352 info->count);
4353 } else {
4354 unsigned i;
4355 for_each_bit(i, state->subpass->view_mask) {
4356 radv_emit_view_index(cmd_buffer, i);
4357
4358 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4359 index_va,
4360 info->count);
4361 }
4362 }
4363 } else {
4364 if (!state->subpass->view_mask) {
4365 radv_cs_emit_draw_packet(cmd_buffer,
4366 info->count,
4367 !!info->strmout_buffer);
4368 } else {
4369 unsigned i;
4370 for_each_bit(i, state->subpass->view_mask) {
4371 radv_emit_view_index(cmd_buffer, i);
4372
4373 radv_cs_emit_draw_packet(cmd_buffer,
4374 info->count,
4375 !!info->strmout_buffer);
4376 }
4377 }
4378 }
4379 }
4380 }
4381
4382 /*
4383 * Vega and raven have a bug which triggers if there are multiple context
4384 * register contexts active at the same time with different scissor values.
4385 *
4386 * There are two possible workarounds:
4387 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4388 * there is only ever 1 active set of scissor values at the same time.
4389 *
4390 * 2) Whenever the hardware switches contexts we have to set the scissor
4391 * registers again even if it is a noop. That way the new context gets
4392 * the correct scissor values.
4393 *
4394 * This implements option 2. radv_need_late_scissor_emission needs to
4395 * return true on affected HW if radv_emit_all_graphics_states sets
4396 * any context registers.
4397 */
4398 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4399 const struct radv_draw_info *info)
4400 {
4401 struct radv_cmd_state *state = &cmd_buffer->state;
4402
4403 if (!cmd_buffer->device->physical_device->has_scissor_bug)
4404 return false;
4405
4406 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4407 return true;
4408
4409 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4410
4411 /* Index, vertex and streamout buffers don't change context regs, and
4412 * pipeline is already handled.
4413 */
4414 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4415 RADV_CMD_DIRTY_VERTEX_BUFFER |
4416 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4417 RADV_CMD_DIRTY_PIPELINE);
4418
4419 if (cmd_buffer->state.dirty & used_states)
4420 return true;
4421
4422 uint32_t primitive_reset_index =
4423 radv_get_primitive_reset_index(cmd_buffer);
4424
4425 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4426 primitive_reset_index != state->last_primitive_reset_index)
4427 return true;
4428
4429 return false;
4430 }
4431
4432 static void
4433 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4434 const struct radv_draw_info *info)
4435 {
4436 bool late_scissor_emission;
4437
4438 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4439 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4440 radv_emit_rbplus_state(cmd_buffer);
4441
4442 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4443 radv_emit_graphics_pipeline(cmd_buffer);
4444
4445 /* This should be before the cmd_buffer->state.dirty is cleared
4446 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4447 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4448 late_scissor_emission =
4449 radv_need_late_scissor_emission(cmd_buffer, info);
4450
4451 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4452 radv_emit_framebuffer_state(cmd_buffer);
4453
4454 if (info->indexed) {
4455 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4456 radv_emit_index_buffer(cmd_buffer);
4457 } else {
4458 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4459 * so the state must be re-emitted before the next indexed
4460 * draw.
4461 */
4462 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4463 cmd_buffer->state.last_index_type = -1;
4464 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4465 }
4466 }
4467
4468 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4469
4470 radv_emit_draw_registers(cmd_buffer, info);
4471
4472 if (late_scissor_emission)
4473 radv_emit_scissor(cmd_buffer);
4474 }
4475
4476 static void
4477 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4478 const struct radv_draw_info *info)
4479 {
4480 struct radeon_info *rad_info =
4481 &cmd_buffer->device->physical_device->rad_info;
4482 bool has_prefetch =
4483 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4484 bool pipeline_is_dirty =
4485 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4486 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4487
4488 ASSERTED unsigned cdw_max =
4489 radeon_check_space(cmd_buffer->device->ws,
4490 cmd_buffer->cs, 4096);
4491
4492 if (likely(!info->indirect)) {
4493 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4494 * no workaround for indirect draws, but we can at least skip
4495 * direct draws.
4496 */
4497 if (unlikely(!info->instance_count))
4498 return;
4499
4500 /* Handle count == 0. */
4501 if (unlikely(!info->count && !info->strmout_buffer))
4502 return;
4503 }
4504
4505 /* Use optimal packet order based on whether we need to sync the
4506 * pipeline.
4507 */
4508 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4509 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4510 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4511 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4512 /* If we have to wait for idle, set all states first, so that
4513 * all SET packets are processed in parallel with previous draw
4514 * calls. Then upload descriptors, set shader pointers, and
4515 * draw, and prefetch at the end. This ensures that the time
4516 * the CUs are idle is very short. (there are only SET_SH
4517 * packets between the wait and the draw)
4518 */
4519 radv_emit_all_graphics_states(cmd_buffer, info);
4520 si_emit_cache_flush(cmd_buffer);
4521 /* <-- CUs are idle here --> */
4522
4523 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4524
4525 radv_emit_draw_packets(cmd_buffer, info);
4526 /* <-- CUs are busy here --> */
4527
4528 /* Start prefetches after the draw has been started. Both will
4529 * run in parallel, but starting the draw first is more
4530 * important.
4531 */
4532 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4533 radv_emit_prefetch_L2(cmd_buffer,
4534 cmd_buffer->state.pipeline, false);
4535 }
4536 } else {
4537 /* If we don't wait for idle, start prefetches first, then set
4538 * states, and draw at the end.
4539 */
4540 si_emit_cache_flush(cmd_buffer);
4541
4542 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4543 /* Only prefetch the vertex shader and VBO descriptors
4544 * in order to start the draw as soon as possible.
4545 */
4546 radv_emit_prefetch_L2(cmd_buffer,
4547 cmd_buffer->state.pipeline, true);
4548 }
4549
4550 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4551
4552 radv_emit_all_graphics_states(cmd_buffer, info);
4553 radv_emit_draw_packets(cmd_buffer, info);
4554
4555 /* Prefetch the remaining shaders after the draw has been
4556 * started.
4557 */
4558 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4559 radv_emit_prefetch_L2(cmd_buffer,
4560 cmd_buffer->state.pipeline, false);
4561 }
4562 }
4563
4564 /* Workaround for a VGT hang when streamout is enabled.
4565 * It must be done after drawing.
4566 */
4567 if (cmd_buffer->state.streamout.streamout_enabled &&
4568 (rad_info->family == CHIP_HAWAII ||
4569 rad_info->family == CHIP_TONGA ||
4570 rad_info->family == CHIP_FIJI)) {
4571 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4572 }
4573
4574 assert(cmd_buffer->cs->cdw <= cdw_max);
4575 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4576 }
4577
4578 void radv_CmdDraw(
4579 VkCommandBuffer commandBuffer,
4580 uint32_t vertexCount,
4581 uint32_t instanceCount,
4582 uint32_t firstVertex,
4583 uint32_t firstInstance)
4584 {
4585 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4586 struct radv_draw_info info = {};
4587
4588 info.count = vertexCount;
4589 info.instance_count = instanceCount;
4590 info.first_instance = firstInstance;
4591 info.vertex_offset = firstVertex;
4592
4593 radv_draw(cmd_buffer, &info);
4594 }
4595
4596 void radv_CmdDrawIndexed(
4597 VkCommandBuffer commandBuffer,
4598 uint32_t indexCount,
4599 uint32_t instanceCount,
4600 uint32_t firstIndex,
4601 int32_t vertexOffset,
4602 uint32_t firstInstance)
4603 {
4604 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4605 struct radv_draw_info info = {};
4606
4607 info.indexed = true;
4608 info.count = indexCount;
4609 info.instance_count = instanceCount;
4610 info.first_index = firstIndex;
4611 info.vertex_offset = vertexOffset;
4612 info.first_instance = firstInstance;
4613
4614 radv_draw(cmd_buffer, &info);
4615 }
4616
4617 void radv_CmdDrawIndirect(
4618 VkCommandBuffer commandBuffer,
4619 VkBuffer _buffer,
4620 VkDeviceSize offset,
4621 uint32_t drawCount,
4622 uint32_t stride)
4623 {
4624 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4625 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4626 struct radv_draw_info info = {};
4627
4628 info.count = drawCount;
4629 info.indirect = buffer;
4630 info.indirect_offset = offset;
4631 info.stride = stride;
4632
4633 radv_draw(cmd_buffer, &info);
4634 }
4635
4636 void radv_CmdDrawIndexedIndirect(
4637 VkCommandBuffer commandBuffer,
4638 VkBuffer _buffer,
4639 VkDeviceSize offset,
4640 uint32_t drawCount,
4641 uint32_t stride)
4642 {
4643 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4644 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4645 struct radv_draw_info info = {};
4646
4647 info.indexed = true;
4648 info.count = drawCount;
4649 info.indirect = buffer;
4650 info.indirect_offset = offset;
4651 info.stride = stride;
4652
4653 radv_draw(cmd_buffer, &info);
4654 }
4655
4656 void radv_CmdDrawIndirectCountKHR(
4657 VkCommandBuffer commandBuffer,
4658 VkBuffer _buffer,
4659 VkDeviceSize offset,
4660 VkBuffer _countBuffer,
4661 VkDeviceSize countBufferOffset,
4662 uint32_t maxDrawCount,
4663 uint32_t stride)
4664 {
4665 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4666 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4667 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4668 struct radv_draw_info info = {};
4669
4670 info.count = maxDrawCount;
4671 info.indirect = buffer;
4672 info.indirect_offset = offset;
4673 info.count_buffer = count_buffer;
4674 info.count_buffer_offset = countBufferOffset;
4675 info.stride = stride;
4676
4677 radv_draw(cmd_buffer, &info);
4678 }
4679
4680 void radv_CmdDrawIndexedIndirectCountKHR(
4681 VkCommandBuffer commandBuffer,
4682 VkBuffer _buffer,
4683 VkDeviceSize offset,
4684 VkBuffer _countBuffer,
4685 VkDeviceSize countBufferOffset,
4686 uint32_t maxDrawCount,
4687 uint32_t stride)
4688 {
4689 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4690 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4691 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4692 struct radv_draw_info info = {};
4693
4694 info.indexed = true;
4695 info.count = maxDrawCount;
4696 info.indirect = buffer;
4697 info.indirect_offset = offset;
4698 info.count_buffer = count_buffer;
4699 info.count_buffer_offset = countBufferOffset;
4700 info.stride = stride;
4701
4702 radv_draw(cmd_buffer, &info);
4703 }
4704
4705 struct radv_dispatch_info {
4706 /**
4707 * Determine the layout of the grid (in block units) to be used.
4708 */
4709 uint32_t blocks[3];
4710
4711 /**
4712 * A starting offset for the grid. If unaligned is set, the offset
4713 * must still be aligned.
4714 */
4715 uint32_t offsets[3];
4716 /**
4717 * Whether it's an unaligned compute dispatch.
4718 */
4719 bool unaligned;
4720
4721 /**
4722 * Indirect compute parameters resource.
4723 */
4724 struct radv_buffer *indirect;
4725 uint64_t indirect_offset;
4726 };
4727
4728 static void
4729 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4730 const struct radv_dispatch_info *info)
4731 {
4732 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4733 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4734 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4735 struct radeon_winsys *ws = cmd_buffer->device->ws;
4736 bool predicating = cmd_buffer->state.predicating;
4737 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4738 struct radv_userdata_info *loc;
4739
4740 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4741 AC_UD_CS_GRID_SIZE);
4742
4743 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4744
4745 if (info->indirect) {
4746 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4747
4748 va += info->indirect->offset + info->indirect_offset;
4749
4750 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4751
4752 if (loc->sgpr_idx != -1) {
4753 for (unsigned i = 0; i < 3; ++i) {
4754 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4755 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4756 COPY_DATA_DST_SEL(COPY_DATA_REG));
4757 radeon_emit(cs, (va + 4 * i));
4758 radeon_emit(cs, (va + 4 * i) >> 32);
4759 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4760 + loc->sgpr_idx * 4) >> 2) + i);
4761 radeon_emit(cs, 0);
4762 }
4763 }
4764
4765 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4766 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4767 PKT3_SHADER_TYPE_S(1));
4768 radeon_emit(cs, va);
4769 radeon_emit(cs, va >> 32);
4770 radeon_emit(cs, dispatch_initiator);
4771 } else {
4772 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4773 PKT3_SHADER_TYPE_S(1));
4774 radeon_emit(cs, 1);
4775 radeon_emit(cs, va);
4776 radeon_emit(cs, va >> 32);
4777
4778 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4779 PKT3_SHADER_TYPE_S(1));
4780 radeon_emit(cs, 0);
4781 radeon_emit(cs, dispatch_initiator);
4782 }
4783 } else {
4784 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4785 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4786
4787 if (info->unaligned) {
4788 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4789 unsigned remainder[3];
4790
4791 /* If aligned, these should be an entire block size,
4792 * not 0.
4793 */
4794 remainder[0] = blocks[0] + cs_block_size[0] -
4795 align_u32_npot(blocks[0], cs_block_size[0]);
4796 remainder[1] = blocks[1] + cs_block_size[1] -
4797 align_u32_npot(blocks[1], cs_block_size[1]);
4798 remainder[2] = blocks[2] + cs_block_size[2] -
4799 align_u32_npot(blocks[2], cs_block_size[2]);
4800
4801 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4802 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4803 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4804
4805 for(unsigned i = 0; i < 3; ++i) {
4806 assert(offsets[i] % cs_block_size[i] == 0);
4807 offsets[i] /= cs_block_size[i];
4808 }
4809
4810 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4811 radeon_emit(cs,
4812 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4813 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4814 radeon_emit(cs,
4815 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4816 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4817 radeon_emit(cs,
4818 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4819 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4820
4821 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4822 }
4823
4824 if (loc->sgpr_idx != -1) {
4825 assert(loc->num_sgprs == 3);
4826
4827 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4828 loc->sgpr_idx * 4, 3);
4829 radeon_emit(cs, blocks[0]);
4830 radeon_emit(cs, blocks[1]);
4831 radeon_emit(cs, blocks[2]);
4832 }
4833
4834 if (offsets[0] || offsets[1] || offsets[2]) {
4835 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4836 radeon_emit(cs, offsets[0]);
4837 radeon_emit(cs, offsets[1]);
4838 radeon_emit(cs, offsets[2]);
4839
4840 /* The blocks in the packet are not counts but end values. */
4841 for (unsigned i = 0; i < 3; ++i)
4842 blocks[i] += offsets[i];
4843 } else {
4844 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4845 }
4846
4847 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4848 PKT3_SHADER_TYPE_S(1));
4849 radeon_emit(cs, blocks[0]);
4850 radeon_emit(cs, blocks[1]);
4851 radeon_emit(cs, blocks[2]);
4852 radeon_emit(cs, dispatch_initiator);
4853 }
4854
4855 assert(cmd_buffer->cs->cdw <= cdw_max);
4856 }
4857
4858 static void
4859 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4860 {
4861 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4862 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4863 }
4864
4865 static void
4866 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4867 const struct radv_dispatch_info *info)
4868 {
4869 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4870 bool has_prefetch =
4871 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4872 bool pipeline_is_dirty = pipeline &&
4873 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4874
4875 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4876 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4877 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4878 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4879 /* If we have to wait for idle, set all states first, so that
4880 * all SET packets are processed in parallel with previous draw
4881 * calls. Then upload descriptors, set shader pointers, and
4882 * dispatch, and prefetch at the end. This ensures that the
4883 * time the CUs are idle is very short. (there are only SET_SH
4884 * packets between the wait and the draw)
4885 */
4886 radv_emit_compute_pipeline(cmd_buffer);
4887 si_emit_cache_flush(cmd_buffer);
4888 /* <-- CUs are idle here --> */
4889
4890 radv_upload_compute_shader_descriptors(cmd_buffer);
4891
4892 radv_emit_dispatch_packets(cmd_buffer, info);
4893 /* <-- CUs are busy here --> */
4894
4895 /* Start prefetches after the dispatch has been started. Both
4896 * will run in parallel, but starting the dispatch first is
4897 * more important.
4898 */
4899 if (has_prefetch && pipeline_is_dirty) {
4900 radv_emit_shader_prefetch(cmd_buffer,
4901 pipeline->shaders[MESA_SHADER_COMPUTE]);
4902 }
4903 } else {
4904 /* If we don't wait for idle, start prefetches first, then set
4905 * states, and dispatch at the end.
4906 */
4907 si_emit_cache_flush(cmd_buffer);
4908
4909 if (has_prefetch && pipeline_is_dirty) {
4910 radv_emit_shader_prefetch(cmd_buffer,
4911 pipeline->shaders[MESA_SHADER_COMPUTE]);
4912 }
4913
4914 radv_upload_compute_shader_descriptors(cmd_buffer);
4915
4916 radv_emit_compute_pipeline(cmd_buffer);
4917 radv_emit_dispatch_packets(cmd_buffer, info);
4918 }
4919
4920 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4921 }
4922
4923 void radv_CmdDispatchBase(
4924 VkCommandBuffer commandBuffer,
4925 uint32_t base_x,
4926 uint32_t base_y,
4927 uint32_t base_z,
4928 uint32_t x,
4929 uint32_t y,
4930 uint32_t z)
4931 {
4932 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4933 struct radv_dispatch_info info = {};
4934
4935 info.blocks[0] = x;
4936 info.blocks[1] = y;
4937 info.blocks[2] = z;
4938
4939 info.offsets[0] = base_x;
4940 info.offsets[1] = base_y;
4941 info.offsets[2] = base_z;
4942 radv_dispatch(cmd_buffer, &info);
4943 }
4944
4945 void radv_CmdDispatch(
4946 VkCommandBuffer commandBuffer,
4947 uint32_t x,
4948 uint32_t y,
4949 uint32_t z)
4950 {
4951 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4952 }
4953
4954 void radv_CmdDispatchIndirect(
4955 VkCommandBuffer commandBuffer,
4956 VkBuffer _buffer,
4957 VkDeviceSize offset)
4958 {
4959 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4960 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4961 struct radv_dispatch_info info = {};
4962
4963 info.indirect = buffer;
4964 info.indirect_offset = offset;
4965
4966 radv_dispatch(cmd_buffer, &info);
4967 }
4968
4969 void radv_unaligned_dispatch(
4970 struct radv_cmd_buffer *cmd_buffer,
4971 uint32_t x,
4972 uint32_t y,
4973 uint32_t z)
4974 {
4975 struct radv_dispatch_info info = {};
4976
4977 info.blocks[0] = x;
4978 info.blocks[1] = y;
4979 info.blocks[2] = z;
4980 info.unaligned = 1;
4981
4982 radv_dispatch(cmd_buffer, &info);
4983 }
4984
4985 void radv_CmdEndRenderPass(
4986 VkCommandBuffer commandBuffer)
4987 {
4988 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4989
4990 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4991
4992 radv_cmd_buffer_end_subpass(cmd_buffer);
4993
4994 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4995 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4996
4997 cmd_buffer->state.pass = NULL;
4998 cmd_buffer->state.subpass = NULL;
4999 cmd_buffer->state.attachments = NULL;
5000 cmd_buffer->state.framebuffer = NULL;
5001 cmd_buffer->state.subpass_sample_locs = NULL;
5002 }
5003
5004 void radv_CmdEndRenderPass2KHR(
5005 VkCommandBuffer commandBuffer,
5006 const VkSubpassEndInfoKHR* pSubpassEndInfo)
5007 {
5008 radv_CmdEndRenderPass(commandBuffer);
5009 }
5010
5011 /*
5012 * For HTILE we have the following interesting clear words:
5013 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5014 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5015 * 0xfffffff0: Clear depth to 1.0
5016 * 0x00000000: Clear depth to 0.0
5017 */
5018 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5019 struct radv_image *image,
5020 const VkImageSubresourceRange *range,
5021 uint32_t clear_word)
5022 {
5023 assert(range->baseMipLevel == 0);
5024 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5025 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5026 struct radv_cmd_state *state = &cmd_buffer->state;
5027 VkClearDepthStencilValue value = {};
5028
5029 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5030 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5031
5032 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
5033
5034 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5035
5036 if (vk_format_is_stencil(image->vk_format))
5037 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5038
5039 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
5040
5041 if (radv_image_is_tc_compat_htile(image)) {
5042 /* Initialize the TC-compat metada value to 0 because by
5043 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5044 * need have to conditionally update its value when performing
5045 * a fast depth clear.
5046 */
5047 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
5048 }
5049 }
5050
5051 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5052 struct radv_image *image,
5053 VkImageLayout src_layout,
5054 VkImageLayout dst_layout,
5055 unsigned src_queue_mask,
5056 unsigned dst_queue_mask,
5057 const VkImageSubresourceRange *range,
5058 struct radv_sample_locations_state *sample_locs)
5059 {
5060 if (!radv_image_has_htile(image))
5061 return;
5062
5063 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5064 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5065
5066 if (radv_layout_is_htile_compressed(image, dst_layout,
5067 dst_queue_mask)) {
5068 clear_value = 0;
5069 }
5070
5071 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5072 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
5073 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
5074 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5075 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5076 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
5077 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
5078 VkImageSubresourceRange local_range = *range;
5079 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
5080 local_range.baseMipLevel = 0;
5081 local_range.levelCount = 1;
5082
5083 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5084 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5085
5086 radv_decompress_depth_image_inplace(cmd_buffer, image,
5087 &local_range, sample_locs);
5088
5089 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5090 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5091 }
5092 }
5093
5094 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5095 struct radv_image *image,
5096 const VkImageSubresourceRange *range,
5097 uint32_t value)
5098 {
5099 struct radv_cmd_state *state = &cmd_buffer->state;
5100
5101 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5102 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5103
5104 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5105
5106 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5107 }
5108
5109 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5110 struct radv_image *image,
5111 const VkImageSubresourceRange *range)
5112 {
5113 struct radv_cmd_state *state = &cmd_buffer->state;
5114 static const uint32_t fmask_clear_values[4] = {
5115 0x00000000,
5116 0x02020202,
5117 0xE4E4E4E4,
5118 0x76543210
5119 };
5120 uint32_t log2_samples = util_logbase2(image->info.samples);
5121 uint32_t value = fmask_clear_values[log2_samples];
5122
5123 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5124 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5125
5126 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5127
5128 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5129 }
5130
5131 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5132 struct radv_image *image,
5133 const VkImageSubresourceRange *range, uint32_t value)
5134 {
5135 struct radv_cmd_state *state = &cmd_buffer->state;
5136 unsigned size = 0;
5137
5138 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5139 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5140
5141 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5142
5143 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5144 /* When DCC is enabled with mipmaps, some levels might not
5145 * support fast clears and we have to initialize them as "fully
5146 * expanded".
5147 */
5148 /* Compute the size of all fast clearable DCC levels. */
5149 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5150 struct legacy_surf_level *surf_level =
5151 &image->planes[0].surface.u.legacy.level[i];
5152 unsigned dcc_fast_clear_size =
5153 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5154
5155 if (!dcc_fast_clear_size)
5156 break;
5157
5158 size = surf_level->dcc_offset + dcc_fast_clear_size;
5159 }
5160
5161 /* Initialize the mipmap levels without DCC. */
5162 if (size != image->planes[0].surface.dcc_size) {
5163 state->flush_bits |=
5164 radv_fill_buffer(cmd_buffer, image->bo,
5165 image->offset + image->dcc_offset + size,
5166 image->planes[0].surface.dcc_size - size,
5167 0xffffffff);
5168 }
5169 }
5170
5171 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5172 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5173 }
5174
5175 /**
5176 * Initialize DCC/FMASK/CMASK metadata for a color image.
5177 */
5178 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5179 struct radv_image *image,
5180 VkImageLayout src_layout,
5181 VkImageLayout dst_layout,
5182 unsigned src_queue_mask,
5183 unsigned dst_queue_mask,
5184 const VkImageSubresourceRange *range)
5185 {
5186 if (radv_image_has_cmask(image)) {
5187 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5188
5189 /* TODO: clarify this. */
5190 if (radv_image_has_fmask(image)) {
5191 value = 0xccccccccu;
5192 }
5193
5194 radv_initialise_cmask(cmd_buffer, image, range, value);
5195 }
5196
5197 if (radv_image_has_fmask(image)) {
5198 radv_initialize_fmask(cmd_buffer, image, range);
5199 }
5200
5201 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5202 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5203 bool need_decompress_pass = false;
5204
5205 if (radv_layout_dcc_compressed(image, dst_layout,
5206 dst_queue_mask)) {
5207 value = 0x20202020u;
5208 need_decompress_pass = true;
5209 }
5210
5211 radv_initialize_dcc(cmd_buffer, image, range, value);
5212
5213 radv_update_fce_metadata(cmd_buffer, image, range,
5214 need_decompress_pass);
5215 }
5216
5217 if (radv_image_has_cmask(image) ||
5218 radv_dcc_enabled(image, range->baseMipLevel)) {
5219 uint32_t color_values[2] = {};
5220 radv_set_color_clear_metadata(cmd_buffer, image, range,
5221 color_values);
5222 }
5223 }
5224
5225 /**
5226 * Handle color image transitions for DCC/FMASK/CMASK.
5227 */
5228 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5229 struct radv_image *image,
5230 VkImageLayout src_layout,
5231 VkImageLayout dst_layout,
5232 unsigned src_queue_mask,
5233 unsigned dst_queue_mask,
5234 const VkImageSubresourceRange *range)
5235 {
5236 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5237 radv_init_color_image_metadata(cmd_buffer, image,
5238 src_layout, dst_layout,
5239 src_queue_mask, dst_queue_mask,
5240 range);
5241 return;
5242 }
5243
5244 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5245 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5246 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5247 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
5248 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
5249 radv_decompress_dcc(cmd_buffer, image, range);
5250 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5251 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5252 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5253 }
5254 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5255 bool fce_eliminate = false, fmask_expand = false;
5256
5257 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5258 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5259 fce_eliminate = true;
5260 }
5261
5262 if (radv_image_has_fmask(image)) {
5263 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5264 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5265 /* A FMASK decompress is required before doing
5266 * a MSAA decompress using FMASK.
5267 */
5268 fmask_expand = true;
5269 }
5270 }
5271
5272 if (fce_eliminate || fmask_expand)
5273 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5274
5275 if (fmask_expand)
5276 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5277 }
5278 }
5279
5280 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5281 struct radv_image *image,
5282 VkImageLayout src_layout,
5283 VkImageLayout dst_layout,
5284 uint32_t src_family,
5285 uint32_t dst_family,
5286 const VkImageSubresourceRange *range,
5287 struct radv_sample_locations_state *sample_locs)
5288 {
5289 if (image->exclusive && src_family != dst_family) {
5290 /* This is an acquire or a release operation and there will be
5291 * a corresponding release/acquire. Do the transition in the
5292 * most flexible queue. */
5293
5294 assert(src_family == cmd_buffer->queue_family_index ||
5295 dst_family == cmd_buffer->queue_family_index);
5296
5297 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5298 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5299 return;
5300
5301 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5302 return;
5303
5304 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5305 (src_family == RADV_QUEUE_GENERAL ||
5306 dst_family == RADV_QUEUE_GENERAL))
5307 return;
5308 }
5309
5310 if (src_layout == dst_layout)
5311 return;
5312
5313 unsigned src_queue_mask =
5314 radv_image_queue_family_mask(image, src_family,
5315 cmd_buffer->queue_family_index);
5316 unsigned dst_queue_mask =
5317 radv_image_queue_family_mask(image, dst_family,
5318 cmd_buffer->queue_family_index);
5319
5320 if (vk_format_is_depth(image->vk_format)) {
5321 radv_handle_depth_image_transition(cmd_buffer, image,
5322 src_layout, dst_layout,
5323 src_queue_mask, dst_queue_mask,
5324 range, sample_locs);
5325 } else {
5326 radv_handle_color_image_transition(cmd_buffer, image,
5327 src_layout, dst_layout,
5328 src_queue_mask, dst_queue_mask,
5329 range);
5330 }
5331 }
5332
5333 struct radv_barrier_info {
5334 uint32_t eventCount;
5335 const VkEvent *pEvents;
5336 VkPipelineStageFlags srcStageMask;
5337 VkPipelineStageFlags dstStageMask;
5338 };
5339
5340 static void
5341 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5342 uint32_t memoryBarrierCount,
5343 const VkMemoryBarrier *pMemoryBarriers,
5344 uint32_t bufferMemoryBarrierCount,
5345 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5346 uint32_t imageMemoryBarrierCount,
5347 const VkImageMemoryBarrier *pImageMemoryBarriers,
5348 const struct radv_barrier_info *info)
5349 {
5350 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5351 enum radv_cmd_flush_bits src_flush_bits = 0;
5352 enum radv_cmd_flush_bits dst_flush_bits = 0;
5353
5354 for (unsigned i = 0; i < info->eventCount; ++i) {
5355 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5356 uint64_t va = radv_buffer_get_va(event->bo);
5357
5358 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5359
5360 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5361
5362 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5363 assert(cmd_buffer->cs->cdw <= cdw_max);
5364 }
5365
5366 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5367 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5368 NULL);
5369 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5370 NULL);
5371 }
5372
5373 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5374 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5375 NULL);
5376 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5377 NULL);
5378 }
5379
5380 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5381 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5382
5383 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5384 image);
5385 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5386 image);
5387 }
5388
5389 /* The Vulkan spec 1.1.98 says:
5390 *
5391 * "An execution dependency with only
5392 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5393 * will only prevent that stage from executing in subsequently
5394 * submitted commands. As this stage does not perform any actual
5395 * execution, this is not observable - in effect, it does not delay
5396 * processing of subsequent commands. Similarly an execution dependency
5397 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5398 * will effectively not wait for any prior commands to complete."
5399 */
5400 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5401 radv_stage_flush(cmd_buffer, info->srcStageMask);
5402 cmd_buffer->state.flush_bits |= src_flush_bits;
5403
5404 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5405 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5406
5407 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5408 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5409 SAMPLE_LOCATIONS_INFO_EXT);
5410 struct radv_sample_locations_state sample_locations = {};
5411
5412 if (sample_locs_info) {
5413 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5414 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5415 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5416 sample_locations.count = sample_locs_info->sampleLocationsCount;
5417 typed_memcpy(&sample_locations.locations[0],
5418 sample_locs_info->pSampleLocations,
5419 sample_locs_info->sampleLocationsCount);
5420 }
5421
5422 radv_handle_image_transition(cmd_buffer, image,
5423 pImageMemoryBarriers[i].oldLayout,
5424 pImageMemoryBarriers[i].newLayout,
5425 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5426 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5427 &pImageMemoryBarriers[i].subresourceRange,
5428 sample_locs_info ? &sample_locations : NULL);
5429 }
5430
5431 /* Make sure CP DMA is idle because the driver might have performed a
5432 * DMA operation for copying or filling buffers/images.
5433 */
5434 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5435 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5436 si_cp_dma_wait_for_idle(cmd_buffer);
5437
5438 cmd_buffer->state.flush_bits |= dst_flush_bits;
5439 }
5440
5441 void radv_CmdPipelineBarrier(
5442 VkCommandBuffer commandBuffer,
5443 VkPipelineStageFlags srcStageMask,
5444 VkPipelineStageFlags destStageMask,
5445 VkBool32 byRegion,
5446 uint32_t memoryBarrierCount,
5447 const VkMemoryBarrier* pMemoryBarriers,
5448 uint32_t bufferMemoryBarrierCount,
5449 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5450 uint32_t imageMemoryBarrierCount,
5451 const VkImageMemoryBarrier* pImageMemoryBarriers)
5452 {
5453 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5454 struct radv_barrier_info info;
5455
5456 info.eventCount = 0;
5457 info.pEvents = NULL;
5458 info.srcStageMask = srcStageMask;
5459 info.dstStageMask = destStageMask;
5460
5461 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5462 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5463 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5464 }
5465
5466
5467 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5468 struct radv_event *event,
5469 VkPipelineStageFlags stageMask,
5470 unsigned value)
5471 {
5472 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5473 uint64_t va = radv_buffer_get_va(event->bo);
5474
5475 si_emit_cache_flush(cmd_buffer);
5476
5477 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5478
5479 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5480
5481 /* Flags that only require a top-of-pipe event. */
5482 VkPipelineStageFlags top_of_pipe_flags =
5483 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5484
5485 /* Flags that only require a post-index-fetch event. */
5486 VkPipelineStageFlags post_index_fetch_flags =
5487 top_of_pipe_flags |
5488 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5489 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5490
5491 /* Make sure CP DMA is idle because the driver might have performed a
5492 * DMA operation for copying or filling buffers/images.
5493 */
5494 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5495 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5496 si_cp_dma_wait_for_idle(cmd_buffer);
5497
5498 /* TODO: Emit EOS events for syncing PS/CS stages. */
5499
5500 if (!(stageMask & ~top_of_pipe_flags)) {
5501 /* Just need to sync the PFP engine. */
5502 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5503 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5504 S_370_WR_CONFIRM(1) |
5505 S_370_ENGINE_SEL(V_370_PFP));
5506 radeon_emit(cs, va);
5507 radeon_emit(cs, va >> 32);
5508 radeon_emit(cs, value);
5509 } else if (!(stageMask & ~post_index_fetch_flags)) {
5510 /* Sync ME because PFP reads index and indirect buffers. */
5511 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5512 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5513 S_370_WR_CONFIRM(1) |
5514 S_370_ENGINE_SEL(V_370_ME));
5515 radeon_emit(cs, va);
5516 radeon_emit(cs, va >> 32);
5517 radeon_emit(cs, value);
5518 } else {
5519 /* Otherwise, sync all prior GPU work using an EOP event. */
5520 si_cs_emit_write_event_eop(cs,
5521 cmd_buffer->device->physical_device->rad_info.chip_class,
5522 radv_cmd_buffer_uses_mec(cmd_buffer),
5523 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5524 EOP_DST_SEL_MEM,
5525 EOP_DATA_SEL_VALUE_32BIT, va, value,
5526 cmd_buffer->gfx9_eop_bug_va);
5527 }
5528
5529 assert(cmd_buffer->cs->cdw <= cdw_max);
5530 }
5531
5532 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5533 VkEvent _event,
5534 VkPipelineStageFlags stageMask)
5535 {
5536 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5537 RADV_FROM_HANDLE(radv_event, event, _event);
5538
5539 write_event(cmd_buffer, event, stageMask, 1);
5540 }
5541
5542 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5543 VkEvent _event,
5544 VkPipelineStageFlags stageMask)
5545 {
5546 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5547 RADV_FROM_HANDLE(radv_event, event, _event);
5548
5549 write_event(cmd_buffer, event, stageMask, 0);
5550 }
5551
5552 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5553 uint32_t eventCount,
5554 const VkEvent* pEvents,
5555 VkPipelineStageFlags srcStageMask,
5556 VkPipelineStageFlags dstStageMask,
5557 uint32_t memoryBarrierCount,
5558 const VkMemoryBarrier* pMemoryBarriers,
5559 uint32_t bufferMemoryBarrierCount,
5560 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5561 uint32_t imageMemoryBarrierCount,
5562 const VkImageMemoryBarrier* pImageMemoryBarriers)
5563 {
5564 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5565 struct radv_barrier_info info;
5566
5567 info.eventCount = eventCount;
5568 info.pEvents = pEvents;
5569 info.srcStageMask = 0;
5570
5571 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5572 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5573 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5574 }
5575
5576
5577 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5578 uint32_t deviceMask)
5579 {
5580 /* No-op */
5581 }
5582
5583 /* VK_EXT_conditional_rendering */
5584 void radv_CmdBeginConditionalRenderingEXT(
5585 VkCommandBuffer commandBuffer,
5586 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5587 {
5588 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5589 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5590 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5591 bool draw_visible = true;
5592 uint64_t pred_value = 0;
5593 uint64_t va, new_va;
5594 unsigned pred_offset;
5595
5596 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5597
5598 /* By default, if the 32-bit value at offset in buffer memory is zero,
5599 * then the rendering commands are discarded, otherwise they are
5600 * executed as normal. If the inverted flag is set, all commands are
5601 * discarded if the value is non zero.
5602 */
5603 if (pConditionalRenderingBegin->flags &
5604 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5605 draw_visible = false;
5606 }
5607
5608 si_emit_cache_flush(cmd_buffer);
5609
5610 /* From the Vulkan spec 1.1.107:
5611 *
5612 * "If the 32-bit value at offset in buffer memory is zero, then the
5613 * rendering commands are discarded, otherwise they are executed as
5614 * normal. If the value of the predicate in buffer memory changes while
5615 * conditional rendering is active, the rendering commands may be
5616 * discarded in an implementation-dependent way. Some implementations
5617 * may latch the value of the predicate upon beginning conditional
5618 * rendering while others may read it before every rendering command."
5619 *
5620 * But, the AMD hardware treats the predicate as a 64-bit value which
5621 * means we need a workaround in the driver. Luckily, it's not required
5622 * to support if the value changes when predication is active.
5623 *
5624 * The workaround is as follows:
5625 * 1) allocate a 64-value in the upload BO and initialize it to 0
5626 * 2) copy the 32-bit predicate value to the upload BO
5627 * 3) use the new allocated VA address for predication
5628 *
5629 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5630 * in ME (+ sync PFP) instead of PFP.
5631 */
5632 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5633
5634 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5635
5636 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5637 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5638 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5639 COPY_DATA_WR_CONFIRM);
5640 radeon_emit(cs, va);
5641 radeon_emit(cs, va >> 32);
5642 radeon_emit(cs, new_va);
5643 radeon_emit(cs, new_va >> 32);
5644
5645 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5646 radeon_emit(cs, 0);
5647
5648 /* Enable predication for this command buffer. */
5649 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5650 cmd_buffer->state.predicating = true;
5651
5652 /* Store conditional rendering user info. */
5653 cmd_buffer->state.predication_type = draw_visible;
5654 cmd_buffer->state.predication_va = new_va;
5655 }
5656
5657 void radv_CmdEndConditionalRenderingEXT(
5658 VkCommandBuffer commandBuffer)
5659 {
5660 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5661
5662 /* Disable predication for this command buffer. */
5663 si_emit_set_predication_state(cmd_buffer, false, 0);
5664 cmd_buffer->state.predicating = false;
5665
5666 /* Reset conditional rendering user info. */
5667 cmd_buffer->state.predication_type = -1;
5668 cmd_buffer->state.predication_va = 0;
5669 }
5670
5671 /* VK_EXT_transform_feedback */
5672 void radv_CmdBindTransformFeedbackBuffersEXT(
5673 VkCommandBuffer commandBuffer,
5674 uint32_t firstBinding,
5675 uint32_t bindingCount,
5676 const VkBuffer* pBuffers,
5677 const VkDeviceSize* pOffsets,
5678 const VkDeviceSize* pSizes)
5679 {
5680 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5681 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5682 uint8_t enabled_mask = 0;
5683
5684 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5685 for (uint32_t i = 0; i < bindingCount; i++) {
5686 uint32_t idx = firstBinding + i;
5687
5688 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5689 sb[idx].offset = pOffsets[i];
5690 sb[idx].size = pSizes[i];
5691
5692 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5693 sb[idx].buffer->bo);
5694
5695 enabled_mask |= 1 << idx;
5696 }
5697
5698 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5699
5700 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5701 }
5702
5703 static void
5704 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5705 {
5706 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5707 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5708
5709 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5710 radeon_emit(cs,
5711 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5712 S_028B94_RAST_STREAM(0) |
5713 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5714 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5715 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5716 radeon_emit(cs, so->hw_enabled_mask &
5717 so->enabled_stream_buffers_mask);
5718
5719 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5720 }
5721
5722 static void
5723 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5724 {
5725 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5726 bool old_streamout_enabled = so->streamout_enabled;
5727 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5728
5729 so->streamout_enabled = enable;
5730
5731 so->hw_enabled_mask = so->enabled_mask |
5732 (so->enabled_mask << 4) |
5733 (so->enabled_mask << 8) |
5734 (so->enabled_mask << 12);
5735
5736 if ((old_streamout_enabled != so->streamout_enabled) ||
5737 (old_hw_enabled_mask != so->hw_enabled_mask))
5738 radv_emit_streamout_enable(cmd_buffer);
5739 }
5740
5741 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5742 {
5743 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5744 unsigned reg_strmout_cntl;
5745
5746 /* The register is at different places on different ASICs. */
5747 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5748 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5749 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5750 } else {
5751 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5752 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5753 }
5754
5755 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5756 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5757
5758 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5759 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5760 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5761 radeon_emit(cs, 0);
5762 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5763 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5764 radeon_emit(cs, 4); /* poll interval */
5765 }
5766
5767 static void
5768 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5769 uint32_t firstCounterBuffer,
5770 uint32_t counterBufferCount,
5771 const VkBuffer *pCounterBuffers,
5772 const VkDeviceSize *pCounterBufferOffsets)
5773
5774 {
5775 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5776 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5777 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5778 uint32_t i;
5779
5780 radv_flush_vgt_streamout(cmd_buffer);
5781
5782 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5783 for_each_bit(i, so->enabled_mask) {
5784 int32_t counter_buffer_idx = i - firstCounterBuffer;
5785 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5786 counter_buffer_idx = -1;
5787
5788 /* AMD GCN binds streamout buffers as shader resources.
5789 * VGT only counts primitives and tells the shader through
5790 * SGPRs what to do.
5791 */
5792 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5793 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5794 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5795
5796 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5797
5798 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5799 /* The array of counter buffers is optional. */
5800 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5801 uint64_t va = radv_buffer_get_va(buffer->bo);
5802
5803 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5804
5805 /* Append */
5806 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5807 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5808 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5809 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5810 radeon_emit(cs, 0); /* unused */
5811 radeon_emit(cs, 0); /* unused */
5812 radeon_emit(cs, va); /* src address lo */
5813 radeon_emit(cs, va >> 32); /* src address hi */
5814
5815 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5816 } else {
5817 /* Start from the beginning. */
5818 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5819 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5820 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5821 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5822 radeon_emit(cs, 0); /* unused */
5823 radeon_emit(cs, 0); /* unused */
5824 radeon_emit(cs, 0); /* unused */
5825 radeon_emit(cs, 0); /* unused */
5826 }
5827 }
5828
5829 radv_set_streamout_enable(cmd_buffer, true);
5830 }
5831
5832 void radv_CmdBeginTransformFeedbackEXT(
5833 VkCommandBuffer commandBuffer,
5834 uint32_t firstCounterBuffer,
5835 uint32_t counterBufferCount,
5836 const VkBuffer* pCounterBuffers,
5837 const VkDeviceSize* pCounterBufferOffsets)
5838 {
5839 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5840
5841 radv_emit_streamout_begin(cmd_buffer,
5842 firstCounterBuffer, counterBufferCount,
5843 pCounterBuffers, pCounterBufferOffsets);
5844 }
5845
5846 static void
5847 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
5848 uint32_t firstCounterBuffer,
5849 uint32_t counterBufferCount,
5850 const VkBuffer *pCounterBuffers,
5851 const VkDeviceSize *pCounterBufferOffsets)
5852 {
5853 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5854 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5855 uint32_t i;
5856
5857 radv_flush_vgt_streamout(cmd_buffer);
5858
5859 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5860 for_each_bit(i, so->enabled_mask) {
5861 int32_t counter_buffer_idx = i - firstCounterBuffer;
5862 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5863 counter_buffer_idx = -1;
5864
5865 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5866 /* The array of counters buffer is optional. */
5867 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5868 uint64_t va = radv_buffer_get_va(buffer->bo);
5869
5870 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5871
5872 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5873 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5874 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5875 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5876 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5877 radeon_emit(cs, va); /* dst address lo */
5878 radeon_emit(cs, va >> 32); /* dst address hi */
5879 radeon_emit(cs, 0); /* unused */
5880 radeon_emit(cs, 0); /* unused */
5881
5882 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5883 }
5884
5885 /* Deactivate transform feedback by zeroing the buffer size.
5886 * The counters (primitives generated, primitives emitted) may
5887 * be enabled even if there is not buffer bound. This ensures
5888 * that the primitives-emitted query won't increment.
5889 */
5890 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5891
5892 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5893 }
5894
5895 radv_set_streamout_enable(cmd_buffer, false);
5896 }
5897
5898 void radv_CmdEndTransformFeedbackEXT(
5899 VkCommandBuffer commandBuffer,
5900 uint32_t firstCounterBuffer,
5901 uint32_t counterBufferCount,
5902 const VkBuffer* pCounterBuffers,
5903 const VkDeviceSize* pCounterBufferOffsets)
5904 {
5905 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5906
5907 radv_emit_streamout_end(cmd_buffer,
5908 firstCounterBuffer, counterBufferCount,
5909 pCounterBuffers, pCounterBufferOffsets);
5910 }
5911
5912 void radv_CmdDrawIndirectByteCountEXT(
5913 VkCommandBuffer commandBuffer,
5914 uint32_t instanceCount,
5915 uint32_t firstInstance,
5916 VkBuffer _counterBuffer,
5917 VkDeviceSize counterBufferOffset,
5918 uint32_t counterOffset,
5919 uint32_t vertexStride)
5920 {
5921 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5922 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5923 struct radv_draw_info info = {};
5924
5925 info.instance_count = instanceCount;
5926 info.first_instance = firstInstance;
5927 info.strmout_buffer = counterBuffer;
5928 info.strmout_buffer_offset = counterBufferOffset;
5929 info.stride = vertexStride;
5930
5931 radv_draw(cmd_buffer, &info);
5932 }
5933
5934 /* VK_AMD_buffer_marker */
5935 void radv_CmdWriteBufferMarkerAMD(
5936 VkCommandBuffer commandBuffer,
5937 VkPipelineStageFlagBits pipelineStage,
5938 VkBuffer dstBuffer,
5939 VkDeviceSize dstOffset,
5940 uint32_t marker)
5941 {
5942 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5943 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
5944 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5945 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
5946
5947 si_emit_cache_flush(cmd_buffer);
5948
5949 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
5950 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5951 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
5952 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5953 COPY_DATA_WR_CONFIRM);
5954 radeon_emit(cs, marker);
5955 radeon_emit(cs, 0);
5956 radeon_emit(cs, va);
5957 radeon_emit(cs, va >> 32);
5958 } else {
5959 si_cs_emit_write_event_eop(cs,
5960 cmd_buffer->device->physical_device->rad_info.chip_class,
5961 radv_cmd_buffer_uses_mec(cmd_buffer),
5962 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5963 EOP_DST_SEL_MEM,
5964 EOP_DATA_SEL_VALUE_32BIT,
5965 va, marker,
5966 cmd_buffer->gfx9_eop_bug_va);
5967 }
5968 }