projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: overhaul fragment shader sample positions.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 uint32_t src_family,
42 uint32_t dst_family,
43 const VkImageSubresourceRange *range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static void
191 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
192 {
193 list_del(&cmd_buffer->pool_link);
194
195 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
196 &cmd_buffer->upload.list, list) {
197 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
198 list_del(&up->list);
199 free(up);
200 }
201
202 if (cmd_buffer->upload.upload_bo)
203 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
204 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
205 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
206 }
207
208 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
209 {
210
211 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
212
213 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
214 &cmd_buffer->upload.list, list) {
215 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
216 list_del(&up->list);
217 free(up);
218 }
219
220 cmd_buffer->scratch_size_needed = 0;
221 cmd_buffer->compute_scratch_size_needed = 0;
222 cmd_buffer->esgs_ring_size_needed = 0;
223 cmd_buffer->gsvs_ring_size_needed = 0;
224 cmd_buffer->tess_rings_needed = false;
225 cmd_buffer->sample_positions_needed = false;
226
227 if (cmd_buffer->upload.upload_bo)
228 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
229 cmd_buffer->upload.upload_bo, 8);
230 cmd_buffer->upload.offset = 0;
231
232 cmd_buffer->record_fail = false;
233
234 cmd_buffer->ring_offsets_idx = -1;
235 }
236
237 static bool
238 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
239 uint64_t min_needed)
240 {
241 uint64_t new_size;
242 struct radeon_winsys_bo *bo;
243 struct radv_cmd_buffer_upload *upload;
244 struct radv_device *device = cmd_buffer->device;
245
246 new_size = MAX2(min_needed, 16 * 1024);
247 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
248
249 bo = device->ws->buffer_create(device->ws,
250 new_size, 4096,
251 RADEON_DOMAIN_GTT,
252 RADEON_FLAG_CPU_ACCESS);
253
254 if (!bo) {
255 cmd_buffer->record_fail = true;
256 return false;
257 }
258
259 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
260 if (cmd_buffer->upload.upload_bo) {
261 upload = malloc(sizeof(*upload));
262
263 if (!upload) {
264 cmd_buffer->record_fail = true;
265 device->ws->buffer_destroy(bo);
266 return false;
267 }
268
269 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
270 list_add(&upload->list, &cmd_buffer->upload.list);
271 }
272
273 cmd_buffer->upload.upload_bo = bo;
274 cmd_buffer->upload.size = new_size;
275 cmd_buffer->upload.offset = 0;
276 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
277
278 if (!cmd_buffer->upload.map) {
279 cmd_buffer->record_fail = true;
280 return false;
281 }
282
283 return true;
284 }
285
286 bool
287 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
288 unsigned size,
289 unsigned alignment,
290 unsigned *out_offset,
291 void **ptr)
292 {
293 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
294 if (offset + size > cmd_buffer->upload.size) {
295 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
296 return false;
297 offset = 0;
298 }
299
300 *out_offset = offset;
301 *ptr = cmd_buffer->upload.map + offset;
302
303 cmd_buffer->upload.offset = offset + size;
304 return true;
305 }
306
307 bool
308 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
309 unsigned size, unsigned alignment,
310 const void *data, unsigned *out_offset)
311 {
312 uint8_t *ptr;
313
314 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
315 out_offset, (void **)&ptr))
316 return false;
317
318 if (ptr)
319 memcpy(ptr, data, size);
320
321 return true;
322 }
323
324 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
325 {
326 struct radv_device *device = cmd_buffer->device;
327 struct radeon_winsys_cs *cs = cmd_buffer->cs;
328 uint64_t va;
329
330 if (!device->trace_bo)
331 return;
332
333 va = device->ws->buffer_get_va(device->trace_bo);
334
335 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
336
337 ++cmd_buffer->state.trace_id;
338 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
339 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
340 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
341 S_370_WR_CONFIRM(1) |
342 S_370_ENGINE_SEL(V_370_ME));
343 radeon_emit(cs, va);
344 radeon_emit(cs, va >> 32);
345 radeon_emit(cs, cmd_buffer->state.trace_id);
346 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
347 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
348 }
349
350 static void
351 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
352 struct radv_pipeline *pipeline)
353 {
354 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
355 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
356 8);
357 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
358 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
359 }
360
361 static void
362 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
363 struct radv_pipeline *pipeline)
364 {
365 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
366 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
367 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
368
369 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
370 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
371 }
372
373 /* 12.4 fixed-point */
374 static unsigned radv_pack_float_12p4(float x)
375 {
376 return x <= 0 ? 0 :
377 x >= 4096 ? 0xffff : x * 16;
378 }
379
380 static uint32_t
381 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
382 {
383 switch (stage) {
384 case MESA_SHADER_FRAGMENT:
385 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
386 case MESA_SHADER_VERTEX:
387 if (has_tess)
388 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
389 else
390 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
391 case MESA_SHADER_GEOMETRY:
392 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
393 case MESA_SHADER_COMPUTE:
394 return R_00B900_COMPUTE_USER_DATA_0;
395 case MESA_SHADER_TESS_CTRL:
396 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
397 case MESA_SHADER_TESS_EVAL:
398 if (has_gs)
399 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
400 else
401 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
402 default:
403 unreachable("unknown shader");
404 }
405 }
406
407 static struct ac_userdata_info *
408 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
409 gl_shader_stage stage,
410 int idx)
411 {
412 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
413 }
414
415 static void
416 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
417 struct radv_pipeline *pipeline,
418 gl_shader_stage stage,
419 int idx, uint64_t va)
420 {
421 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
422 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
423 if (loc->sgpr_idx == -1)
424 return;
425 assert(loc->num_sgprs == 2);
426 assert(!loc->indirect);
427 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
428 radeon_emit(cmd_buffer->cs, va);
429 radeon_emit(cmd_buffer->cs, va >> 32);
430 }
431
432 static void
433 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
434 struct radv_pipeline *pipeline)
435 {
436 int num_samples = pipeline->graphics.ms.num_samples;
437 struct radv_multisample_state *ms = &pipeline->graphics.ms;
438 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
439
440 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
441 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
442 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
443
444 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
445 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
446
447 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
448 return;
449
450 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
451 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
452 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
453
454 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
455
456 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.uses_sample_positions) {
457 uint32_t offset;
458 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
459 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
460 if (loc->sgpr_idx == -1)
461 return;
462 assert(loc->num_sgprs == 1);
463 assert(!loc->indirect);
464 switch (num_samples) {
465 default:
466 offset = 0;
467 break;
468 case 2:
469 offset = 1;
470 break;
471 case 4:
472 offset = 3;
473 break;
474 case 8:
475 offset = 7;
476 break;
477 case 16:
478 offset = 15;
479 break;
480 }
481
482 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
483 cmd_buffer->sample_positions_needed = true;
484 }
485 }
486
487 static void
488 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
489 struct radv_pipeline *pipeline)
490 {
491 struct radv_raster_state *raster = &pipeline->graphics.raster;
492
493 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
494 raster->pa_cl_clip_cntl);
495
496 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
497 raster->spi_interp_control);
498
499 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
500 unsigned tmp = (unsigned)(1.0 * 8.0);
501 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
502 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
503 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
504
505 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
506 raster->pa_su_vtx_cntl);
507
508 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
509 raster->pa_su_sc_mode_cntl);
510 }
511
512 static void
513 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
514 struct radv_pipeline *pipeline,
515 struct radv_shader_variant *shader,
516 struct ac_vs_output_info *outinfo)
517 {
518 struct radeon_winsys *ws = cmd_buffer->device->ws;
519 uint64_t va = ws->buffer_get_va(shader->bo);
520 unsigned export_count;
521
522 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
523
524 export_count = MAX2(1, outinfo->param_exports);
525 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
526 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
527
528 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
529 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
530 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
531 V_02870C_SPI_SHADER_4COMP :
532 V_02870C_SPI_SHADER_NONE) |
533 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
534 V_02870C_SPI_SHADER_4COMP :
535 V_02870C_SPI_SHADER_NONE) |
536 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
537 V_02870C_SPI_SHADER_4COMP :
538 V_02870C_SPI_SHADER_NONE));
539
540
541 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
542 radeon_emit(cmd_buffer->cs, va >> 8);
543 radeon_emit(cmd_buffer->cs, va >> 40);
544 radeon_emit(cmd_buffer->cs, shader->rsrc1);
545 radeon_emit(cmd_buffer->cs, shader->rsrc2);
546
547 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
548 S_028818_VTX_W0_FMT(1) |
549 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
550 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
551 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
552
553
554 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
555 pipeline->graphics.pa_cl_vs_out_cntl);
556
557 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
558 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
559 }
560
561 static void
562 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
563 struct radv_shader_variant *shader,
564 struct ac_es_output_info *outinfo)
565 {
566 struct radeon_winsys *ws = cmd_buffer->device->ws;
567 uint64_t va = ws->buffer_get_va(shader->bo);
568
569 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
570
571 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
572 outinfo->esgs_itemsize / 4);
573 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
574 radeon_emit(cmd_buffer->cs, va >> 8);
575 radeon_emit(cmd_buffer->cs, va >> 40);
576 radeon_emit(cmd_buffer->cs, shader->rsrc1);
577 radeon_emit(cmd_buffer->cs, shader->rsrc2);
578 }
579
580 static void
581 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
582 struct radv_shader_variant *shader)
583 {
584 struct radeon_winsys *ws = cmd_buffer->device->ws;
585 uint64_t va = ws->buffer_get_va(shader->bo);
586 uint32_t rsrc2 = shader->rsrc2;
587
588 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
589
590 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
591 radeon_emit(cmd_buffer->cs, va >> 8);
592 radeon_emit(cmd_buffer->cs, va >> 40);
593
594 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
595 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
596 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
597 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
598
599 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
600 radeon_emit(cmd_buffer->cs, shader->rsrc1);
601 radeon_emit(cmd_buffer->cs, rsrc2);
602 }
603
604 static void
605 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
606 struct radv_shader_variant *shader)
607 {
608 struct radeon_winsys *ws = cmd_buffer->device->ws;
609 uint64_t va = ws->buffer_get_va(shader->bo);
610
611 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
612
613 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
614 radeon_emit(cmd_buffer->cs, va >> 8);
615 radeon_emit(cmd_buffer->cs, va >> 40);
616 radeon_emit(cmd_buffer->cs, shader->rsrc1);
617 radeon_emit(cmd_buffer->cs, shader->rsrc2);
618 }
619
620 static void
621 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
622 struct radv_pipeline *pipeline)
623 {
624 struct radv_shader_variant *vs;
625
626 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
627
628 vs = pipeline->shaders[MESA_SHADER_VERTEX];
629
630 if (vs->info.vs.as_ls)
631 radv_emit_hw_ls(cmd_buffer, vs);
632 else if (vs->info.vs.as_es)
633 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
634 else
635 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
636
637 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
638 }
639
640
641 static void
642 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
643 struct radv_pipeline *pipeline)
644 {
645 if (!radv_pipeline_has_tess(pipeline))
646 return;
647
648 struct radv_shader_variant *tes, *tcs;
649
650 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
651 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
652
653 if (tes->info.tes.as_es)
654 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
655 else
656 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
657
658 radv_emit_hw_hs(cmd_buffer, tcs);
659
660 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
661 pipeline->graphics.tess.tf_param);
662
663 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
664 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
665 pipeline->graphics.tess.ls_hs_config);
666 else
667 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
668 pipeline->graphics.tess.ls_hs_config);
669
670 struct ac_userdata_info *loc;
671
672 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
673 if (loc->sgpr_idx != -1) {
674 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
675 assert(loc->num_sgprs == 4);
676 assert(!loc->indirect);
677 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
678 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
679 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
680 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
681 pipeline->graphics.tess.num_tcs_input_cp << 26);
682 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
683 }
684
685 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
686 if (loc->sgpr_idx != -1) {
687 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
688 assert(loc->num_sgprs == 1);
689 assert(!loc->indirect);
690
691 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
692 pipeline->graphics.tess.offchip_layout);
693 }
694
695 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
696 if (loc->sgpr_idx != -1) {
697 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
698 assert(loc->num_sgprs == 1);
699 assert(!loc->indirect);
700
701 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
702 pipeline->graphics.tess.tcs_in_layout);
703 }
704 }
705
706 static void
707 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
708 struct radv_pipeline *pipeline)
709 {
710 struct radeon_winsys *ws = cmd_buffer->device->ws;
711 struct radv_shader_variant *gs;
712 uint64_t va;
713
714 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
715
716 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
717 if (!gs)
718 return;
719
720 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
721
722 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
723 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
724 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
725 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
726
727 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
728
729 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
730
731 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
732 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
733 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
734 radeon_emit(cmd_buffer->cs, 0);
735 radeon_emit(cmd_buffer->cs, 0);
736 radeon_emit(cmd_buffer->cs, 0);
737
738 uint32_t gs_num_invocations = gs->info.gs.invocations;
739 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
740 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
741 S_028B90_ENABLE(gs_num_invocations > 0));
742
743 va = ws->buffer_get_va(gs->bo);
744 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
745 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
746 radeon_emit(cmd_buffer->cs, va >> 8);
747 radeon_emit(cmd_buffer->cs, va >> 40);
748 radeon_emit(cmd_buffer->cs, gs->rsrc1);
749 radeon_emit(cmd_buffer->cs, gs->rsrc2);
750
751 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
752
753 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
754 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
755 if (loc->sgpr_idx != -1) {
756 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
757 uint32_t num_entries = 64;
758 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
759
760 if (is_vi)
761 num_entries *= stride;
762
763 stride = S_008F04_STRIDE(stride);
764 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
765 radeon_emit(cmd_buffer->cs, stride);
766 radeon_emit(cmd_buffer->cs, num_entries);
767 }
768 }
769
770 static void
771 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
772 struct radv_pipeline *pipeline)
773 {
774 struct radeon_winsys *ws = cmd_buffer->device->ws;
775 struct radv_shader_variant *ps;
776 uint64_t va;
777 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
778 struct radv_blend_state *blend = &pipeline->graphics.blend;
779 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
780
781 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
782
783 va = ws->buffer_get_va(ps->bo);
784 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
785
786 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
787 radeon_emit(cmd_buffer->cs, va >> 8);
788 radeon_emit(cmd_buffer->cs, va >> 40);
789 radeon_emit(cmd_buffer->cs, ps->rsrc1);
790 radeon_emit(cmd_buffer->cs, ps->rsrc2);
791
792 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
793 pipeline->graphics.db_shader_control);
794
795 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
796 ps->config.spi_ps_input_ena);
797
798 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
799 ps->config.spi_ps_input_addr);
800
801 if (ps->info.fs.force_persample)
802 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
803
804 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
805 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
806
807 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
808
809 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
810 pipeline->graphics.shader_z_format);
811
812 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
813
814 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
815 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
816
817 if (pipeline->graphics.ps_input_cntl_num) {
818 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
819 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
820 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
821 }
822 }
823 }
824
825 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
826 struct radv_pipeline *pipeline)
827 {
828 uint32_t vtx_reuse_depth = 30;
829 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
830 return;
831
832 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
833 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
834 vtx_reuse_depth = 14;
835 }
836 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
837 vtx_reuse_depth);
838 }
839
840 static void
841 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
842 struct radv_pipeline *pipeline)
843 {
844 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
845 return;
846
847 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
848 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
849 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
850 radv_update_multisample_state(cmd_buffer, pipeline);
851 radv_emit_vertex_shader(cmd_buffer, pipeline);
852 radv_emit_tess_shaders(cmd_buffer, pipeline);
853 radv_emit_geometry_shader(cmd_buffer, pipeline);
854 radv_emit_fragment_shader(cmd_buffer, pipeline);
855 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
856
857 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
858 pipeline->graphics.prim_restart_enable);
859
860 cmd_buffer->scratch_size_needed =
861 MAX2(cmd_buffer->scratch_size_needed,
862 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
863
864 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
865 S_0286E8_WAVES(pipeline->max_waves) |
866 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
867
868 if (!cmd_buffer->state.emitted_pipeline ||
869 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
870 pipeline->graphics.can_use_guardband)
871 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
872 cmd_buffer->state.emitted_pipeline = pipeline;
873 }
874
875 static void
876 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
877 {
878 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
879 cmd_buffer->state.dynamic.viewport.viewports);
880 }
881
882 static void
883 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
884 {
885 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
886 si_write_scissors(cmd_buffer->cs, 0, count,
887 cmd_buffer->state.dynamic.scissor.scissors,
888 cmd_buffer->state.dynamic.viewport.viewports,
889 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
890 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
891 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
892 }
893
894 static void
895 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
896 int index,
897 struct radv_color_buffer_info *cb)
898 {
899 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
900 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
901 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
902 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
903 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
904 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
905 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
906 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
907 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
908 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
909 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
910 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
911 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
912
913 if (is_vi) { /* DCC BASE */
914 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
915 }
916 }
917
918 static void
919 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
920 struct radv_ds_buffer_info *ds,
921 struct radv_image *image,
922 VkImageLayout layout)
923 {
924 uint32_t db_z_info = ds->db_z_info;
925
926 if (!radv_layout_has_htile(image, layout))
927 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
928
929 if (!radv_layout_can_expclear(image, layout))
930 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
931
932 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
933 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
934
935 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
936 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
937 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
938 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
939 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
940 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
941 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
942 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
943 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
944 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
945
946 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
947 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
948 ds->pa_su_poly_offset_db_fmt_cntl);
949 }
950
951 /*
952 * To hw resolve multisample images both src and dst need to have the same
953 * micro tiling mode. However we don't always know in advance when creating
954 * the images. This function gets called if we have a resolve attachment,
955 * and tests if the attachment image has the same tiling mode, then it
956 * checks if the generated framebuffer data has the same tiling mode, and
957 * updates it if not.
958 */
959 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
960 struct radv_attachment_info *att,
961 uint32_t micro_tile_mode)
962 {
963 struct radv_image *image = att->attachment->image;
964 uint32_t tile_mode_index;
965 if (image->surface.nsamples <= 1)
966 return;
967
968 if (image->surface.micro_tile_mode != micro_tile_mode) {
969 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
970 }
971
972 if (att->cb.micro_tile_mode != micro_tile_mode) {
973 tile_mode_index = image->surface.tiling_index[0];
974
975 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
976 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
977 att->cb.micro_tile_mode = micro_tile_mode;
978 }
979 }
980
981 void
982 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
983 struct radv_image *image,
984 VkClearDepthStencilValue ds_clear_value,
985 VkImageAspectFlags aspects)
986 {
987 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
988 va += image->offset + image->clear_value_offset;
989 unsigned reg_offset = 0, reg_count = 0;
990
991 if (!image->surface.htile_size || !aspects)
992 return;
993
994 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
995 ++reg_count;
996 } else {
997 ++reg_offset;
998 va += 4;
999 }
1000 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1001 ++reg_count;
1002
1003 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1004
1005 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1006 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1007 S_370_WR_CONFIRM(1) |
1008 S_370_ENGINE_SEL(V_370_PFP));
1009 radeon_emit(cmd_buffer->cs, va);
1010 radeon_emit(cmd_buffer->cs, va >> 32);
1011 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1012 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1013 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1014 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1015
1016 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1017 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1018 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1019 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1020 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1021 }
1022
1023 static void
1024 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1025 struct radv_image *image)
1026 {
1027 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1028 va += image->offset + image->clear_value_offset;
1029
1030 if (!image->surface.htile_size)
1031 return;
1032
1033 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1034
1035 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1036 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1037 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1038 COPY_DATA_COUNT_SEL);
1039 radeon_emit(cmd_buffer->cs, va);
1040 radeon_emit(cmd_buffer->cs, va >> 32);
1041 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1042 radeon_emit(cmd_buffer->cs, 0);
1043
1044 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1045 radeon_emit(cmd_buffer->cs, 0);
1046 }
1047
1048 void
1049 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1050 struct radv_image *image,
1051 int idx,
1052 uint32_t color_values[2])
1053 {
1054 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1055 va += image->offset + image->clear_value_offset;
1056
1057 if (!image->cmask.size && !image->surface.dcc_size)
1058 return;
1059
1060 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1061
1062 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1063 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1064 S_370_WR_CONFIRM(1) |
1065 S_370_ENGINE_SEL(V_370_PFP));
1066 radeon_emit(cmd_buffer->cs, va);
1067 radeon_emit(cmd_buffer->cs, va >> 32);
1068 radeon_emit(cmd_buffer->cs, color_values[0]);
1069 radeon_emit(cmd_buffer->cs, color_values[1]);
1070
1071 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1072 radeon_emit(cmd_buffer->cs, color_values[0]);
1073 radeon_emit(cmd_buffer->cs, color_values[1]);
1074 }
1075
1076 static void
1077 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1078 struct radv_image *image,
1079 int idx)
1080 {
1081 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1082 va += image->offset + image->clear_value_offset;
1083
1084 if (!image->cmask.size && !image->surface.dcc_size)
1085 return;
1086
1087 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1088 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1089
1090 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1091 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1092 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1093 COPY_DATA_COUNT_SEL);
1094 radeon_emit(cmd_buffer->cs, va);
1095 radeon_emit(cmd_buffer->cs, va >> 32);
1096 radeon_emit(cmd_buffer->cs, reg >> 2);
1097 radeon_emit(cmd_buffer->cs, 0);
1098
1099 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1100 radeon_emit(cmd_buffer->cs, 0);
1101 }
1102
1103 void
1104 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1105 {
1106 int i;
1107 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1108 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1109 int dst_resolve_micro_tile_mode = -1;
1110
1111 if (subpass->has_resolve) {
1112 uint32_t a = subpass->resolve_attachments[0].attachment;
1113 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
1114 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
1115 }
1116 for (i = 0; i < subpass->color_count; ++i) {
1117 int idx = subpass->color_attachments[i].attachment;
1118 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1119
1120 if (dst_resolve_micro_tile_mode != -1) {
1121 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
1122 att, dst_resolve_micro_tile_mode);
1123 }
1124 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1125
1126 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1127 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1128
1129 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1130 }
1131
1132 for (i = subpass->color_count; i < 8; i++)
1133 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1134 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1135
1136 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1137 int idx = subpass->depth_stencil_attachment.attachment;
1138 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1139 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1140 struct radv_image *image = att->attachment->image;
1141 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1142
1143 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1144
1145 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1146 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1147 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1148 }
1149 radv_load_depth_clear_regs(cmd_buffer, image);
1150 } else {
1151 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1152 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1153 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1154 }
1155 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1156 S_028208_BR_X(framebuffer->width) |
1157 S_028208_BR_Y(framebuffer->height));
1158 }
1159
1160 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1161 {
1162 uint32_t db_count_control;
1163
1164 if(!cmd_buffer->state.active_occlusion_queries) {
1165 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1166 db_count_control = 0;
1167 } else {
1168 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1169 }
1170 } else {
1171 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1172 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1173 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1174 S_028004_ZPASS_ENABLE(1) |
1175 S_028004_SLICE_EVEN_ENABLE(1) |
1176 S_028004_SLICE_ODD_ENABLE(1);
1177 } else {
1178 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1179 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1180 }
1181 }
1182
1183 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1184 }
1185
1186 static void
1187 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1188 {
1189 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1190
1191 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1192 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1193 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1194 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1195 }
1196
1197 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1198 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1199 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1200 }
1201
1202 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1203 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1204 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1205 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1206 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1207 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1208 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1209 S_028430_STENCILOPVAL(1));
1210 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1211 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1212 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1213 S_028434_STENCILOPVAL_BF(1));
1214 }
1215
1216 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1217 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1218 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1219 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1220 }
1221
1222 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1223 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1224 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1225 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1226 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1227
1228 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1229 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1230 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1231 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1232 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1233 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1234 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1235 }
1236 }
1237
1238 cmd_buffer->state.dirty = 0;
1239 }
1240
1241 static void
1242 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1243 struct radv_pipeline *pipeline,
1244 int idx,
1245 uint64_t va,
1246 gl_shader_stage stage)
1247 {
1248 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1249 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1250
1251 if (desc_set_loc->sgpr_idx == -1)
1252 return;
1253
1254 assert(!desc_set_loc->indirect);
1255 assert(desc_set_loc->num_sgprs == 2);
1256 radeon_set_sh_reg_seq(cmd_buffer->cs,
1257 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1258 radeon_emit(cmd_buffer->cs, va);
1259 radeon_emit(cmd_buffer->cs, va >> 32);
1260 }
1261
1262 static void
1263 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1264 struct radv_pipeline *pipeline,
1265 VkShaderStageFlags stages,
1266 struct radv_descriptor_set *set,
1267 unsigned idx)
1268 {
1269 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1270 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1271 idx, set->va,
1272 MESA_SHADER_FRAGMENT);
1273
1274 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1275 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1276 idx, set->va,
1277 MESA_SHADER_VERTEX);
1278
1279 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1280 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1281 idx, set->va,
1282 MESA_SHADER_GEOMETRY);
1283
1284 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1285 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1286 idx, set->va,
1287 MESA_SHADER_TESS_CTRL);
1288
1289 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1290 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1291 idx, set->va,
1292 MESA_SHADER_TESS_EVAL);
1293
1294 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1295 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1296 idx, set->va,
1297 MESA_SHADER_COMPUTE);
1298 }
1299
1300 static void
1301 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1302 struct radv_pipeline *pipeline,
1303 VkShaderStageFlags stages)
1304 {
1305 unsigned i;
1306 if (!cmd_buffer->state.descriptors_dirty)
1307 return;
1308
1309 for (i = 0; i < MAX_SETS; i++) {
1310 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1311 continue;
1312 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1313 if (!set)
1314 continue;
1315
1316 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1317 }
1318 cmd_buffer->state.descriptors_dirty = 0;
1319 }
1320
1321 static void
1322 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1323 struct radv_pipeline *pipeline,
1324 VkShaderStageFlags stages)
1325 {
1326 struct radv_pipeline_layout *layout = pipeline->layout;
1327 unsigned offset;
1328 void *ptr;
1329 uint64_t va;
1330
1331 stages &= cmd_buffer->push_constant_stages;
1332 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1333 return;
1334
1335 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1336 16 * layout->dynamic_offset_count,
1337 256, &offset, &ptr))
1338 return;
1339
1340 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1341 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1342 16 * layout->dynamic_offset_count);
1343
1344 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1345 va += offset;
1346
1347 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1348 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1349 AC_UD_PUSH_CONSTANTS, va);
1350
1351 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1352 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1353 AC_UD_PUSH_CONSTANTS, va);
1354
1355 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1356 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1357 AC_UD_PUSH_CONSTANTS, va);
1358
1359 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1360 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL,
1361 AC_UD_PUSH_CONSTANTS, va);
1362
1363 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1364 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL,
1365 AC_UD_PUSH_CONSTANTS, va);
1366
1367 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1368 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1369 AC_UD_PUSH_CONSTANTS, va);
1370
1371 cmd_buffer->push_constant_stages &= ~stages;
1372 }
1373
1374 static void
1375 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1376 bool instanced_draw, bool indirect_draw,
1377 uint32_t draw_vertex_count)
1378 {
1379 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1380 struct radv_device *device = cmd_buffer->device;
1381 uint32_t ia_multi_vgt_param;
1382
1383 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1384 cmd_buffer->cs, 4096);
1385
1386 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1387 cmd_buffer->state.pipeline->num_vertex_attribs) {
1388 unsigned vb_offset;
1389 void *vb_ptr;
1390 uint32_t i = 0;
1391 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1392 uint64_t va;
1393
1394 /* allocate some descriptor state for vertex buffers */
1395 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1396 &vb_offset, &vb_ptr);
1397
1398 for (i = 0; i < num_attribs; i++) {
1399 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1400 uint32_t offset;
1401 int vb = cmd_buffer->state.pipeline->va_binding[i];
1402 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1403 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1404
1405 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1406 va = device->ws->buffer_get_va(buffer->bo);
1407
1408 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1409 va += offset + buffer->offset;
1410 desc[0] = va;
1411 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1412 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1413 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1414 else
1415 desc[2] = buffer->size - offset;
1416 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1417 }
1418
1419 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1420 va += vb_offset;
1421
1422 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1423 AC_UD_VS_VERTEX_BUFFERS, va);
1424 }
1425
1426 cmd_buffer->state.vertex_descriptors_dirty = false;
1427 cmd_buffer->state.vb_dirty = 0;
1428 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1429 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1430
1431 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1432 radv_emit_framebuffer_state(cmd_buffer);
1433
1434 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1435 radv_emit_viewport(cmd_buffer);
1436
1437 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1438 radv_emit_scissor(cmd_buffer);
1439
1440 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1441 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1442 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1443 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1444 else
1445 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1446 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1447 }
1448
1449 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1450 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1451
1452 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1453 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1454 } else {
1455 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1456 }
1457 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1458 }
1459
1460 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1461
1462 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1463 VK_SHADER_STAGE_ALL_GRAPHICS);
1464 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1465 VK_SHADER_STAGE_ALL_GRAPHICS);
1466
1467 assert(cmd_buffer->cs->cdw <= cdw_max);
1468
1469 si_emit_cache_flush(cmd_buffer);
1470 }
1471
1472 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1473 VkPipelineStageFlags src_stage_mask)
1474 {
1475 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1476 VK_PIPELINE_STAGE_TRANSFER_BIT |
1477 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1478 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1479 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1480 }
1481
1482 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1483 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1484 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1485 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1486 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1487 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1488 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1489 VK_PIPELINE_STAGE_TRANSFER_BIT |
1490 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1491 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1492 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1493 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1494 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1495 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1496 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1497 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1498 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1499 }
1500 }
1501
1502 static enum radv_cmd_flush_bits
1503 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1504 VkAccessFlags src_flags)
1505 {
1506 enum radv_cmd_flush_bits flush_bits = 0;
1507 uint32_t b;
1508 for_each_bit(b, src_flags) {
1509 switch ((VkAccessFlagBits)(1 << b)) {
1510 case VK_ACCESS_SHADER_WRITE_BIT:
1511 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1512 break;
1513 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1514 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1515 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1516 break;
1517 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1518 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1519 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1520 break;
1521 case VK_ACCESS_TRANSFER_WRITE_BIT:
1522 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1523 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1524 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1525 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1526 RADV_CMD_FLAG_INV_GLOBAL_L2;
1527 break;
1528 default:
1529 break;
1530 }
1531 }
1532 return flush_bits;
1533 }
1534
1535 static enum radv_cmd_flush_bits
1536 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1537 VkAccessFlags dst_flags,
1538 struct radv_image *image)
1539 {
1540 enum radv_cmd_flush_bits flush_bits = 0;
1541 uint32_t b;
1542 for_each_bit(b, dst_flags) {
1543 switch ((VkAccessFlagBits)(1 << b)) {
1544 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1545 case VK_ACCESS_INDEX_READ_BIT:
1546 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1547 break;
1548 case VK_ACCESS_UNIFORM_READ_BIT:
1549 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1550 break;
1551 case VK_ACCESS_SHADER_READ_BIT:
1552 case VK_ACCESS_TRANSFER_READ_BIT:
1553 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1554 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1555 RADV_CMD_FLAG_INV_GLOBAL_L2;
1556 break;
1557 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1558 /* TODO: change to image && when the image gets passed
1559 * through from the subpass. */
1560 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1561 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1562 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1563 break;
1564 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1565 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1566 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1567 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1568 break;
1569 default:
1570 break;
1571 }
1572 }
1573 return flush_bits;
1574 }
1575
1576 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1577 {
1578 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1579 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1580 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1581 NULL);
1582 }
1583
1584 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1585 VkAttachmentReference att)
1586 {
1587 unsigned idx = att.attachment;
1588 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1589 VkImageSubresourceRange range;
1590 range.aspectMask = 0;
1591 range.baseMipLevel = view->base_mip;
1592 range.levelCount = 1;
1593 range.baseArrayLayer = view->base_layer;
1594 range.layerCount = cmd_buffer->state.framebuffer->layers;
1595
1596 radv_handle_image_transition(cmd_buffer,
1597 view->image,
1598 cmd_buffer->state.attachments[idx].current_layout,
1599 att.layout, 0, 0, &range,
1600 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1601
1602 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1603
1604
1605 }
1606
1607 void
1608 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1609 const struct radv_subpass *subpass, bool transitions)
1610 {
1611 if (transitions) {
1612 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1613
1614 for (unsigned i = 0; i < subpass->color_count; ++i) {
1615 radv_handle_subpass_image_transition(cmd_buffer,
1616 subpass->color_attachments[i]);
1617 }
1618
1619 for (unsigned i = 0; i < subpass->input_count; ++i) {
1620 radv_handle_subpass_image_transition(cmd_buffer,
1621 subpass->input_attachments[i]);
1622 }
1623
1624 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1625 radv_handle_subpass_image_transition(cmd_buffer,
1626 subpass->depth_stencil_attachment);
1627 }
1628 }
1629
1630 cmd_buffer->state.subpass = subpass;
1631
1632 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1633 }
1634
1635 static void
1636 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1637 struct radv_render_pass *pass,
1638 const VkRenderPassBeginInfo *info)
1639 {
1640 struct radv_cmd_state *state = &cmd_buffer->state;
1641
1642 if (pass->attachment_count == 0) {
1643 state->attachments = NULL;
1644 return;
1645 }
1646
1647 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1648 pass->attachment_count *
1649 sizeof(state->attachments[0]),
1650 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1651 if (state->attachments == NULL) {
1652 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1653 abort();
1654 }
1655
1656 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1657 struct radv_render_pass_attachment *att = &pass->attachments[i];
1658 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1659 VkImageAspectFlags clear_aspects = 0;
1660
1661 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1662 /* color attachment */
1663 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1664 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1665 }
1666 } else {
1667 /* depthstencil attachment */
1668 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1669 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1670 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1671 }
1672 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1673 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1674 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1675 }
1676 }
1677
1678 state->attachments[i].pending_clear_aspects = clear_aspects;
1679 if (clear_aspects && info) {
1680 assert(info->clearValueCount > i);
1681 state->attachments[i].clear_value = info->pClearValues[i];
1682 }
1683
1684 state->attachments[i].current_layout = att->initial_layout;
1685 }
1686 }
1687
1688 VkResult radv_AllocateCommandBuffers(
1689 VkDevice _device,
1690 const VkCommandBufferAllocateInfo *pAllocateInfo,
1691 VkCommandBuffer *pCommandBuffers)
1692 {
1693 RADV_FROM_HANDLE(radv_device, device, _device);
1694 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1695
1696 VkResult result = VK_SUCCESS;
1697 uint32_t i;
1698
1699 memset(pCommandBuffers, 0,
1700 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1701
1702 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1703
1704 if (!list_empty(&pool->free_cmd_buffers)) {
1705 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1706
1707 list_del(&cmd_buffer->pool_link);
1708 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1709
1710 radv_reset_cmd_buffer(cmd_buffer);
1711 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1712 cmd_buffer->level = pAllocateInfo->level;
1713
1714 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1715 result = VK_SUCCESS;
1716 } else {
1717 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1718 &pCommandBuffers[i]);
1719 }
1720 if (result != VK_SUCCESS)
1721 break;
1722 }
1723
1724 if (result != VK_SUCCESS)
1725 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1726 i, pCommandBuffers);
1727
1728 return result;
1729 }
1730
1731 void radv_FreeCommandBuffers(
1732 VkDevice device,
1733 VkCommandPool commandPool,
1734 uint32_t commandBufferCount,
1735 const VkCommandBuffer *pCommandBuffers)
1736 {
1737 for (uint32_t i = 0; i < commandBufferCount; i++) {
1738 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1739
1740 if (cmd_buffer) {
1741 if (cmd_buffer->pool) {
1742 list_del(&cmd_buffer->pool_link);
1743 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1744 } else
1745 radv_cmd_buffer_destroy(cmd_buffer);
1746
1747 }
1748 }
1749 }
1750
1751 VkResult radv_ResetCommandBuffer(
1752 VkCommandBuffer commandBuffer,
1753 VkCommandBufferResetFlags flags)
1754 {
1755 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1756 radv_reset_cmd_buffer(cmd_buffer);
1757 return VK_SUCCESS;
1758 }
1759
1760 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1761 {
1762 struct radv_device *device = cmd_buffer->device;
1763 if (device->gfx_init) {
1764 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1765 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1766 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1767 radeon_emit(cmd_buffer->cs, va);
1768 radeon_emit(cmd_buffer->cs, (va >> 32) & 0xffff);
1769 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1770 } else
1771 si_init_config(cmd_buffer);
1772 }
1773
1774 VkResult radv_BeginCommandBuffer(
1775 VkCommandBuffer commandBuffer,
1776 const VkCommandBufferBeginInfo *pBeginInfo)
1777 {
1778 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1779 radv_reset_cmd_buffer(cmd_buffer);
1780
1781 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1782
1783 /* setup initial configuration into command buffer */
1784 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1785 switch (cmd_buffer->queue_family_index) {
1786 case RADV_QUEUE_GENERAL:
1787 emit_gfx_buffer_state(cmd_buffer);
1788 radv_set_db_count_control(cmd_buffer);
1789 break;
1790 case RADV_QUEUE_COMPUTE:
1791 si_init_compute(cmd_buffer);
1792 break;
1793 case RADV_QUEUE_TRANSFER:
1794 default:
1795 break;
1796 }
1797 }
1798
1799 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1800 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1801 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1802
1803 struct radv_subpass *subpass =
1804 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1805
1806 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1807 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1808 }
1809
1810 return VK_SUCCESS;
1811 }
1812
1813 void radv_CmdBindVertexBuffers(
1814 VkCommandBuffer commandBuffer,
1815 uint32_t firstBinding,
1816 uint32_t bindingCount,
1817 const VkBuffer* pBuffers,
1818 const VkDeviceSize* pOffsets)
1819 {
1820 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1821 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1822
1823 /* We have to defer setting up vertex buffer since we need the buffer
1824 * stride from the pipeline. */
1825
1826 assert(firstBinding + bindingCount < MAX_VBS);
1827 for (uint32_t i = 0; i < bindingCount; i++) {
1828 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1829 vb[firstBinding + i].offset = pOffsets[i];
1830 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1831 }
1832 }
1833
1834 void radv_CmdBindIndexBuffer(
1835 VkCommandBuffer commandBuffer,
1836 VkBuffer buffer,
1837 VkDeviceSize offset,
1838 VkIndexType indexType)
1839 {
1840 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1841
1842 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1843 cmd_buffer->state.index_offset = offset;
1844 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1845 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1846 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1847 }
1848
1849
1850 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1851 struct radv_descriptor_set *set,
1852 unsigned idx)
1853 {
1854 struct radeon_winsys *ws = cmd_buffer->device->ws;
1855
1856 cmd_buffer->state.descriptors[idx] = set;
1857 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1858 if (!set)
1859 return;
1860
1861 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1862 if (set->descriptors[j])
1863 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1864
1865 if(set->bo)
1866 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1867 }
1868
1869 void radv_CmdBindDescriptorSets(
1870 VkCommandBuffer commandBuffer,
1871 VkPipelineBindPoint pipelineBindPoint,
1872 VkPipelineLayout _layout,
1873 uint32_t firstSet,
1874 uint32_t descriptorSetCount,
1875 const VkDescriptorSet* pDescriptorSets,
1876 uint32_t dynamicOffsetCount,
1877 const uint32_t* pDynamicOffsets)
1878 {
1879 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1880 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1881 unsigned dyn_idx = 0;
1882
1883 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1884 cmd_buffer->cs, MAX_SETS * 4 * 6);
1885
1886 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1887 unsigned idx = i + firstSet;
1888 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1889 radv_bind_descriptor_set(cmd_buffer, set, idx);
1890
1891 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1892 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1893 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1894 assert(dyn_idx < dynamicOffsetCount);
1895
1896 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1897 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1898 dst[0] = va;
1899 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1900 dst[2] = range->size;
1901 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1902 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1903 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1904 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1905 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1906 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1907 cmd_buffer->push_constant_stages |=
1908 set->layout->dynamic_shader_stages;
1909 }
1910 }
1911
1912 assert(cmd_buffer->cs->cdw <= cdw_max);
1913 }
1914
1915 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1916 VkPipelineLayout layout,
1917 VkShaderStageFlags stageFlags,
1918 uint32_t offset,
1919 uint32_t size,
1920 const void* pValues)
1921 {
1922 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1923 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1924 cmd_buffer->push_constant_stages |= stageFlags;
1925 }
1926
1927 VkResult radv_EndCommandBuffer(
1928 VkCommandBuffer commandBuffer)
1929 {
1930 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1931
1932 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
1933 si_emit_cache_flush(cmd_buffer);
1934
1935 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1936 cmd_buffer->record_fail)
1937 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1938 return VK_SUCCESS;
1939 }
1940
1941 static void
1942 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1943 {
1944 struct radeon_winsys *ws = cmd_buffer->device->ws;
1945 struct radv_shader_variant *compute_shader;
1946 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1947 uint64_t va;
1948
1949 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1950 return;
1951
1952 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1953
1954 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1955 va = ws->buffer_get_va(compute_shader->bo);
1956
1957 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1958
1959 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1960 cmd_buffer->cs, 16);
1961
1962 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1963 radeon_emit(cmd_buffer->cs, va >> 8);
1964 radeon_emit(cmd_buffer->cs, va >> 40);
1965
1966 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1967 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1968 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1969
1970
1971 cmd_buffer->compute_scratch_size_needed =
1972 MAX2(cmd_buffer->compute_scratch_size_needed,
1973 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1974
1975 /* change these once we have scratch support */
1976 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1977 S_00B860_WAVES(pipeline->max_waves) |
1978 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1979
1980 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1981 radeon_emit(cmd_buffer->cs,
1982 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1983 radeon_emit(cmd_buffer->cs,
1984 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1985 radeon_emit(cmd_buffer->cs,
1986 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1987
1988 assert(cmd_buffer->cs->cdw <= cdw_max);
1989 }
1990
1991
1992 void radv_CmdBindPipeline(
1993 VkCommandBuffer commandBuffer,
1994 VkPipelineBindPoint pipelineBindPoint,
1995 VkPipeline _pipeline)
1996 {
1997 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1998 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1999
2000 for (unsigned i = 0; i < MAX_SETS; i++) {
2001 if (cmd_buffer->state.descriptors[i])
2002 cmd_buffer->state.descriptors_dirty |= (1 << i);
2003 }
2004
2005 switch (pipelineBindPoint) {
2006 case VK_PIPELINE_BIND_POINT_COMPUTE:
2007 cmd_buffer->state.compute_pipeline = pipeline;
2008 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2009 break;
2010 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2011 cmd_buffer->state.pipeline = pipeline;
2012 cmd_buffer->state.vertex_descriptors_dirty = true;
2013 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2014 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2015
2016 /* Apply the dynamic state from the pipeline */
2017 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2018 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2019 &pipeline->dynamic_state,
2020 pipeline->dynamic_state_mask);
2021
2022 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2023 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2024 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2025 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2026
2027 if (radv_pipeline_has_tess(pipeline))
2028 cmd_buffer->tess_rings_needed = true;
2029
2030 if (radv_pipeline_has_gs(pipeline)) {
2031 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2032 AC_UD_SCRATCH_RING_OFFSETS);
2033 if (cmd_buffer->ring_offsets_idx == -1)
2034 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2035 else if (loc->sgpr_idx != -1)
2036 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2037 }
2038 break;
2039 default:
2040 assert(!"invalid bind point");
2041 break;
2042 }
2043 }
2044
2045 void radv_CmdSetViewport(
2046 VkCommandBuffer commandBuffer,
2047 uint32_t firstViewport,
2048 uint32_t viewportCount,
2049 const VkViewport* pViewports)
2050 {
2051 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2052
2053 const uint32_t total_count = firstViewport + viewportCount;
2054 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2055 cmd_buffer->state.dynamic.viewport.count = total_count;
2056
2057 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2058 pViewports, viewportCount * sizeof(*pViewports));
2059
2060 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2061 }
2062
2063 void radv_CmdSetScissor(
2064 VkCommandBuffer commandBuffer,
2065 uint32_t firstScissor,
2066 uint32_t scissorCount,
2067 const VkRect2D* pScissors)
2068 {
2069 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2070
2071 const uint32_t total_count = firstScissor + scissorCount;
2072 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2073 cmd_buffer->state.dynamic.scissor.count = total_count;
2074
2075 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2076 pScissors, scissorCount * sizeof(*pScissors));
2077 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2078 }
2079
2080 void radv_CmdSetLineWidth(
2081 VkCommandBuffer commandBuffer,
2082 float lineWidth)
2083 {
2084 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2085 cmd_buffer->state.dynamic.line_width = lineWidth;
2086 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2087 }
2088
2089 void radv_CmdSetDepthBias(
2090 VkCommandBuffer commandBuffer,
2091 float depthBiasConstantFactor,
2092 float depthBiasClamp,
2093 float depthBiasSlopeFactor)
2094 {
2095 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2096
2097 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2098 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2099 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2100
2101 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2102 }
2103
2104 void radv_CmdSetBlendConstants(
2105 VkCommandBuffer commandBuffer,
2106 const float blendConstants[4])
2107 {
2108 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2109
2110 memcpy(cmd_buffer->state.dynamic.blend_constants,
2111 blendConstants, sizeof(float) * 4);
2112
2113 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2114 }
2115
2116 void radv_CmdSetDepthBounds(
2117 VkCommandBuffer commandBuffer,
2118 float minDepthBounds,
2119 float maxDepthBounds)
2120 {
2121 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2122
2123 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2124 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2125
2126 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2127 }
2128
2129 void radv_CmdSetStencilCompareMask(
2130 VkCommandBuffer commandBuffer,
2131 VkStencilFaceFlags faceMask,
2132 uint32_t compareMask)
2133 {
2134 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2135
2136 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2137 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2138 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2139 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2140
2141 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2142 }
2143
2144 void radv_CmdSetStencilWriteMask(
2145 VkCommandBuffer commandBuffer,
2146 VkStencilFaceFlags faceMask,
2147 uint32_t writeMask)
2148 {
2149 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2150
2151 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2152 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2153 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2154 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2155
2156 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2157 }
2158
2159 void radv_CmdSetStencilReference(
2160 VkCommandBuffer commandBuffer,
2161 VkStencilFaceFlags faceMask,
2162 uint32_t reference)
2163 {
2164 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2165
2166 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2167 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2168 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2169 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2170
2171 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2172 }
2173
2174
2175 void radv_CmdExecuteCommands(
2176 VkCommandBuffer commandBuffer,
2177 uint32_t commandBufferCount,
2178 const VkCommandBuffer* pCmdBuffers)
2179 {
2180 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2181
2182 /* Emit pending flushes on primary prior to executing secondary */
2183 si_emit_cache_flush(primary);
2184
2185 for (uint32_t i = 0; i < commandBufferCount; i++) {
2186 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2187
2188 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2189 secondary->scratch_size_needed);
2190 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2191 secondary->compute_scratch_size_needed);
2192
2193 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2194 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2195 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2196 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2197 if (secondary->tess_rings_needed)
2198 primary->tess_rings_needed = true;
2199 if (secondary->sample_positions_needed)
2200 primary->sample_positions_needed = true;
2201
2202 if (secondary->ring_offsets_idx != -1) {
2203 if (primary->ring_offsets_idx == -1)
2204 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2205 else
2206 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2207 }
2208 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2209 }
2210
2211 /* if we execute secondary we need to re-emit out pipelines */
2212 if (commandBufferCount) {
2213 primary->state.emitted_pipeline = NULL;
2214 primary->state.emitted_compute_pipeline = NULL;
2215 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2216 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2217 }
2218 }
2219
2220 VkResult radv_CreateCommandPool(
2221 VkDevice _device,
2222 const VkCommandPoolCreateInfo* pCreateInfo,
2223 const VkAllocationCallbacks* pAllocator,
2224 VkCommandPool* pCmdPool)
2225 {
2226 RADV_FROM_HANDLE(radv_device, device, _device);
2227 struct radv_cmd_pool *pool;
2228
2229 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2230 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2231 if (pool == NULL)
2232 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2233
2234 if (pAllocator)
2235 pool->alloc = *pAllocator;
2236 else
2237 pool->alloc = device->alloc;
2238
2239 list_inithead(&pool->cmd_buffers);
2240 list_inithead(&pool->free_cmd_buffers);
2241
2242 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2243
2244 *pCmdPool = radv_cmd_pool_to_handle(pool);
2245
2246 return VK_SUCCESS;
2247
2248 }
2249
2250 void radv_DestroyCommandPool(
2251 VkDevice _device,
2252 VkCommandPool commandPool,
2253 const VkAllocationCallbacks* pAllocator)
2254 {
2255 RADV_FROM_HANDLE(radv_device, device, _device);
2256 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2257
2258 if (!pool)
2259 return;
2260
2261 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2262 &pool->cmd_buffers, pool_link) {
2263 radv_cmd_buffer_destroy(cmd_buffer);
2264 }
2265
2266 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2267 &pool->free_cmd_buffers, pool_link) {
2268 radv_cmd_buffer_destroy(cmd_buffer);
2269 }
2270
2271 vk_free2(&device->alloc, pAllocator, pool);
2272 }
2273
2274 VkResult radv_ResetCommandPool(
2275 VkDevice device,
2276 VkCommandPool commandPool,
2277 VkCommandPoolResetFlags flags)
2278 {
2279 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2280
2281 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2282 &pool->cmd_buffers, pool_link) {
2283 radv_reset_cmd_buffer(cmd_buffer);
2284 }
2285
2286 return VK_SUCCESS;
2287 }
2288
2289 void radv_TrimCommandPoolKHR(
2290 VkDevice device,
2291 VkCommandPool commandPool,
2292 VkCommandPoolTrimFlagsKHR flags)
2293 {
2294 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2295
2296 if (!pool)
2297 return;
2298
2299 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2300 &pool->free_cmd_buffers, pool_link) {
2301 radv_cmd_buffer_destroy(cmd_buffer);
2302 }
2303 }
2304
2305 void radv_CmdBeginRenderPass(
2306 VkCommandBuffer commandBuffer,
2307 const VkRenderPassBeginInfo* pRenderPassBegin,
2308 VkSubpassContents contents)
2309 {
2310 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2311 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2312 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2313
2314 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2315 cmd_buffer->cs, 2048);
2316
2317 cmd_buffer->state.framebuffer = framebuffer;
2318 cmd_buffer->state.pass = pass;
2319 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2320 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2321
2322 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2323 assert(cmd_buffer->cs->cdw <= cdw_max);
2324
2325 radv_cmd_buffer_clear_subpass(cmd_buffer);
2326 }
2327
2328 void radv_CmdNextSubpass(
2329 VkCommandBuffer commandBuffer,
2330 VkSubpassContents contents)
2331 {
2332 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2333
2334 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2335
2336 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2337 2048);
2338
2339 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2340 radv_cmd_buffer_clear_subpass(cmd_buffer);
2341 }
2342
2343 void radv_CmdDraw(
2344 VkCommandBuffer commandBuffer,
2345 uint32_t vertexCount,
2346 uint32_t instanceCount,
2347 uint32_t firstVertex,
2348 uint32_t firstInstance)
2349 {
2350 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2351
2352 radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, vertexCount);
2353
2354 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2355
2356 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2357 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2358 if (loc->sgpr_idx != -1) {
2359 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2360 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2361 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2362 radeon_emit(cmd_buffer->cs, firstVertex);
2363 radeon_emit(cmd_buffer->cs, firstInstance);
2364 radeon_emit(cmd_buffer->cs, 0);
2365 }
2366 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2367 radeon_emit(cmd_buffer->cs, instanceCount);
2368
2369 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2370 radeon_emit(cmd_buffer->cs, vertexCount);
2371 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2372 S_0287F0_USE_OPAQUE(0));
2373
2374 assert(cmd_buffer->cs->cdw <= cdw_max);
2375
2376 radv_cmd_buffer_trace_emit(cmd_buffer);
2377 }
2378
2379 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2380 {
2381 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
2382
2383 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
2384 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
2385 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
2386 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2387 primitive_reset_index);
2388 }
2389 }
2390
2391 void radv_CmdDrawIndexed(
2392 VkCommandBuffer commandBuffer,
2393 uint32_t indexCount,
2394 uint32_t instanceCount,
2395 uint32_t firstIndex,
2396 int32_t vertexOffset,
2397 uint32_t firstInstance)
2398 {
2399 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2400 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2401 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2402 uint64_t index_va;
2403
2404 radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, indexCount);
2405 radv_emit_primitive_reset_index(cmd_buffer);
2406
2407 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2408
2409 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2410 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2411
2412 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2413 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2414 if (loc->sgpr_idx != -1) {
2415 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2416 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2417 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2418 radeon_emit(cmd_buffer->cs, vertexOffset);
2419 radeon_emit(cmd_buffer->cs, firstInstance);
2420 radeon_emit(cmd_buffer->cs, 0);
2421 }
2422 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2423 radeon_emit(cmd_buffer->cs, instanceCount);
2424
2425 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2426 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2427 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2428 radeon_emit(cmd_buffer->cs, index_max_size);
2429 radeon_emit(cmd_buffer->cs, index_va);
2430 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2431 radeon_emit(cmd_buffer->cs, indexCount);
2432 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2433
2434 assert(cmd_buffer->cs->cdw <= cdw_max);
2435 radv_cmd_buffer_trace_emit(cmd_buffer);
2436 }
2437
2438 static void
2439 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2440 VkBuffer _buffer,
2441 VkDeviceSize offset,
2442 VkBuffer _count_buffer,
2443 VkDeviceSize count_offset,
2444 uint32_t draw_count,
2445 uint32_t stride,
2446 bool indexed)
2447 {
2448 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2449 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2450 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2451 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2452 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2453 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2454 indirect_va += offset + buffer->offset;
2455 uint64_t count_va = 0;
2456
2457 if (count_buffer) {
2458 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2459 count_va += count_offset + count_buffer->offset;
2460 }
2461
2462 if (!draw_count)
2463 return;
2464
2465 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2466
2467 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2468 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2469 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2470 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2471 assert(loc->sgpr_idx != -1);
2472 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2473 radeon_emit(cs, 1);
2474 radeon_emit(cs, indirect_va);
2475 radeon_emit(cs, indirect_va >> 32);
2476
2477 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2478 PKT3_DRAW_INDIRECT_MULTI,
2479 8, false));
2480 radeon_emit(cs, 0);
2481 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2482 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2483 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2484 S_2C3_DRAW_INDEX_ENABLE(1) |
2485 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2486 radeon_emit(cs, draw_count); /* count */
2487 radeon_emit(cs, count_va); /* count_addr */
2488 radeon_emit(cs, count_va >> 32);
2489 radeon_emit(cs, stride); /* stride */
2490 radeon_emit(cs, di_src_sel);
2491 radv_cmd_buffer_trace_emit(cmd_buffer);
2492 }
2493
2494 static void
2495 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2496 VkBuffer buffer,
2497 VkDeviceSize offset,
2498 VkBuffer countBuffer,
2499 VkDeviceSize countBufferOffset,
2500 uint32_t maxDrawCount,
2501 uint32_t stride)
2502 {
2503 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2504 radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0);
2505
2506 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2507 cmd_buffer->cs, 14);
2508
2509 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2510 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2511
2512 assert(cmd_buffer->cs->cdw <= cdw_max);
2513 }
2514
2515 static void
2516 radv_cmd_draw_indexed_indirect_count(
2517 VkCommandBuffer commandBuffer,
2518 VkBuffer buffer,
2519 VkDeviceSize offset,
2520 VkBuffer countBuffer,
2521 VkDeviceSize countBufferOffset,
2522 uint32_t maxDrawCount,
2523 uint32_t stride)
2524 {
2525 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2526 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2527 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2528 uint64_t index_va;
2529 radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0);
2530 radv_emit_primitive_reset_index(cmd_buffer);
2531
2532 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2533 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2534
2535 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2536
2537 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2538 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2539
2540 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2541 radeon_emit(cmd_buffer->cs, index_va);
2542 radeon_emit(cmd_buffer->cs, index_va >> 32);
2543
2544 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2545 radeon_emit(cmd_buffer->cs, index_max_size);
2546
2547 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2548 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2549
2550 assert(cmd_buffer->cs->cdw <= cdw_max);
2551 }
2552
2553 void radv_CmdDrawIndirect(
2554 VkCommandBuffer commandBuffer,
2555 VkBuffer buffer,
2556 VkDeviceSize offset,
2557 uint32_t drawCount,
2558 uint32_t stride)
2559 {
2560 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2561 VK_NULL_HANDLE, 0, drawCount, stride);
2562 }
2563
2564 void radv_CmdDrawIndexedIndirect(
2565 VkCommandBuffer commandBuffer,
2566 VkBuffer buffer,
2567 VkDeviceSize offset,
2568 uint32_t drawCount,
2569 uint32_t stride)
2570 {
2571 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2572 VK_NULL_HANDLE, 0, drawCount, stride);
2573 }
2574
2575 void radv_CmdDrawIndirectCountAMD(
2576 VkCommandBuffer commandBuffer,
2577 VkBuffer buffer,
2578 VkDeviceSize offset,
2579 VkBuffer countBuffer,
2580 VkDeviceSize countBufferOffset,
2581 uint32_t maxDrawCount,
2582 uint32_t stride)
2583 {
2584 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2585 countBuffer, countBufferOffset,
2586 maxDrawCount, stride);
2587 }
2588
2589 void radv_CmdDrawIndexedIndirectCountAMD(
2590 VkCommandBuffer commandBuffer,
2591 VkBuffer buffer,
2592 VkDeviceSize offset,
2593 VkBuffer countBuffer,
2594 VkDeviceSize countBufferOffset,
2595 uint32_t maxDrawCount,
2596 uint32_t stride)
2597 {
2598 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2599 countBuffer, countBufferOffset,
2600 maxDrawCount, stride);
2601 }
2602
2603 static void
2604 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2605 {
2606 radv_emit_compute_pipeline(cmd_buffer);
2607 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2608 VK_SHADER_STAGE_COMPUTE_BIT);
2609 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2610 VK_SHADER_STAGE_COMPUTE_BIT);
2611 si_emit_cache_flush(cmd_buffer);
2612 }
2613
2614 void radv_CmdDispatch(
2615 VkCommandBuffer commandBuffer,
2616 uint32_t x,
2617 uint32_t y,
2618 uint32_t z)
2619 {
2620 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2621
2622 radv_flush_compute_state(cmd_buffer);
2623
2624 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2625
2626 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2627 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2628 if (loc->sgpr_idx != -1) {
2629 assert(!loc->indirect);
2630 assert(loc->num_sgprs == 3);
2631 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2632 radeon_emit(cmd_buffer->cs, x);
2633 radeon_emit(cmd_buffer->cs, y);
2634 radeon_emit(cmd_buffer->cs, z);
2635 }
2636
2637 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2638 PKT3_SHADER_TYPE_S(1));
2639 radeon_emit(cmd_buffer->cs, x);
2640 radeon_emit(cmd_buffer->cs, y);
2641 radeon_emit(cmd_buffer->cs, z);
2642 radeon_emit(cmd_buffer->cs, 1);
2643
2644 assert(cmd_buffer->cs->cdw <= cdw_max);
2645 radv_cmd_buffer_trace_emit(cmd_buffer);
2646 }
2647
2648 void radv_CmdDispatchIndirect(
2649 VkCommandBuffer commandBuffer,
2650 VkBuffer _buffer,
2651 VkDeviceSize offset)
2652 {
2653 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2654 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2655 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2656 va += buffer->offset + offset;
2657
2658 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2659
2660 radv_flush_compute_state(cmd_buffer);
2661
2662 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2663 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2664 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2665 if (loc->sgpr_idx != -1) {
2666 for (unsigned i = 0; i < 3; ++i) {
2667 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2668 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2669 COPY_DATA_DST_SEL(COPY_DATA_REG));
2670 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2671 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2672 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2673 radeon_emit(cmd_buffer->cs, 0);
2674 }
2675 }
2676
2677 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2678 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2679 PKT3_SHADER_TYPE_S(1));
2680 radeon_emit(cmd_buffer->cs, va);
2681 radeon_emit(cmd_buffer->cs, va >> 32);
2682 radeon_emit(cmd_buffer->cs, 1);
2683 } else {
2684 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2685 PKT3_SHADER_TYPE_S(1));
2686 radeon_emit(cmd_buffer->cs, 1);
2687 radeon_emit(cmd_buffer->cs, va);
2688 radeon_emit(cmd_buffer->cs, va >> 32);
2689
2690 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2691 PKT3_SHADER_TYPE_S(1));
2692 radeon_emit(cmd_buffer->cs, 0);
2693 radeon_emit(cmd_buffer->cs, 1);
2694 }
2695
2696 assert(cmd_buffer->cs->cdw <= cdw_max);
2697 radv_cmd_buffer_trace_emit(cmd_buffer);
2698 }
2699
2700 void radv_unaligned_dispatch(
2701 struct radv_cmd_buffer *cmd_buffer,
2702 uint32_t x,
2703 uint32_t y,
2704 uint32_t z)
2705 {
2706 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2707 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2708 uint32_t blocks[3], remainder[3];
2709
2710 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2711 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2712 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2713
2714 /* If aligned, these should be an entire block size, not 0 */
2715 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2716 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2717 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2718
2719 radv_flush_compute_state(cmd_buffer);
2720
2721 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2722
2723 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2724 radeon_emit(cmd_buffer->cs,
2725 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2726 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2727 radeon_emit(cmd_buffer->cs,
2728 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2729 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2730 radeon_emit(cmd_buffer->cs,
2731 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2732 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2733
2734 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2735 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2736 if (loc->sgpr_idx != -1) {
2737 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2738 radeon_emit(cmd_buffer->cs, blocks[0]);
2739 radeon_emit(cmd_buffer->cs, blocks[1]);
2740 radeon_emit(cmd_buffer->cs, blocks[2]);
2741 }
2742 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2743 PKT3_SHADER_TYPE_S(1));
2744 radeon_emit(cmd_buffer->cs, blocks[0]);
2745 radeon_emit(cmd_buffer->cs, blocks[1]);
2746 radeon_emit(cmd_buffer->cs, blocks[2]);
2747 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2748 S_00B800_PARTIAL_TG_EN(1));
2749
2750 assert(cmd_buffer->cs->cdw <= cdw_max);
2751 radv_cmd_buffer_trace_emit(cmd_buffer);
2752 }
2753
2754 void radv_CmdEndRenderPass(
2755 VkCommandBuffer commandBuffer)
2756 {
2757 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2758
2759 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2760
2761 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2762
2763 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2764 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2765 radv_handle_subpass_image_transition(cmd_buffer,
2766 (VkAttachmentReference){i, layout});
2767 }
2768
2769 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2770
2771 cmd_buffer->state.pass = NULL;
2772 cmd_buffer->state.subpass = NULL;
2773 cmd_buffer->state.attachments = NULL;
2774 cmd_buffer->state.framebuffer = NULL;
2775 }
2776
2777
2778 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2779 struct radv_image *image,
2780 const VkImageSubresourceRange *range)
2781 {
2782 assert(range->baseMipLevel == 0);
2783 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
2784 unsigned layer_count = radv_get_layerCount(image, range);
2785 uint64_t size = image->surface.htile_slice_size * layer_count;
2786 uint64_t offset = image->offset + image->htile_offset +
2787 image->surface.htile_slice_size * range->baseArrayLayer;
2788
2789 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2790 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2791
2792 radv_fill_buffer(cmd_buffer, image->bo, offset, size, 0xffffffff);
2793
2794 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2795 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2796 RADV_CMD_FLAG_INV_VMEM_L1 |
2797 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2798 }
2799
2800 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2801 struct radv_image *image,
2802 VkImageLayout src_layout,
2803 VkImageLayout dst_layout,
2804 const VkImageSubresourceRange *range,
2805 VkImageAspectFlags pending_clears)
2806 {
2807 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2808 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2809 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2810 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2811 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2812 /* The clear will initialize htile. */
2813 return;
2814 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2815 radv_layout_has_htile(image, dst_layout)) {
2816 /* TODO: merge with the clear if applicable */
2817 radv_initialize_htile(cmd_buffer, image, range);
2818 } else if (!radv_layout_has_htile(image, src_layout) &&
2819 radv_layout_has_htile(image, dst_layout)) {
2820 radv_initialize_htile(cmd_buffer, image, range);
2821 } else if ((radv_layout_has_htile(image, src_layout) &&
2822 !radv_layout_has_htile(image, dst_layout)) ||
2823 (radv_layout_is_htile_compressed(image, src_layout) &&
2824 !radv_layout_is_htile_compressed(image, dst_layout))) {
2825 VkImageSubresourceRange local_range = *range;
2826 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2827 local_range.baseMipLevel = 0;
2828 local_range.levelCount = 1;
2829
2830 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2831 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2832
2833 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
2834
2835 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2836 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2837 }
2838 }
2839
2840 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2841 struct radv_image *image, uint32_t value)
2842 {
2843 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2844 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2845
2846 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2847 image->cmask.size, value);
2848
2849 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2850 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2851 RADV_CMD_FLAG_INV_VMEM_L1 |
2852 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2853 }
2854
2855 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2856 struct radv_image *image,
2857 VkImageLayout src_layout,
2858 VkImageLayout dst_layout,
2859 unsigned src_queue_mask,
2860 unsigned dst_queue_mask,
2861 const VkImageSubresourceRange *range,
2862 VkImageAspectFlags pending_clears)
2863 {
2864 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2865 if (image->fmask.size)
2866 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2867 else
2868 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2869 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2870 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2871 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
2872 }
2873 }
2874
2875 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2876 struct radv_image *image, uint32_t value)
2877 {
2878
2879 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2880 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2881
2882 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2883 image->surface.dcc_size, value);
2884
2885 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2886 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2887 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2888 RADV_CMD_FLAG_INV_VMEM_L1 |
2889 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2890 }
2891
2892 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2893 struct radv_image *image,
2894 VkImageLayout src_layout,
2895 VkImageLayout dst_layout,
2896 unsigned src_queue_mask,
2897 unsigned dst_queue_mask,
2898 const VkImageSubresourceRange *range,
2899 VkImageAspectFlags pending_clears)
2900 {
2901 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2902 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2903 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2904 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2905 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
2906 }
2907 }
2908
2909 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2910 struct radv_image *image,
2911 VkImageLayout src_layout,
2912 VkImageLayout dst_layout,
2913 uint32_t src_family,
2914 uint32_t dst_family,
2915 const VkImageSubresourceRange *range,
2916 VkImageAspectFlags pending_clears)
2917 {
2918 if (image->exclusive && src_family != dst_family) {
2919 /* This is an acquire or a release operation and there will be
2920 * a corresponding release/acquire. Do the transition in the
2921 * most flexible queue. */
2922
2923 assert(src_family == cmd_buffer->queue_family_index ||
2924 dst_family == cmd_buffer->queue_family_index);
2925
2926 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
2927 return;
2928
2929 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
2930 (src_family == RADV_QUEUE_GENERAL ||
2931 dst_family == RADV_QUEUE_GENERAL))
2932 return;
2933 }
2934
2935 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
2936 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
2937
2938 if (image->surface.htile_size)
2939 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2940 dst_layout, range, pending_clears);
2941
2942 if (image->cmask.size)
2943 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2944 dst_layout, src_queue_mask,
2945 dst_queue_mask, range,
2946 pending_clears);
2947
2948 if (image->surface.dcc_size)
2949 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2950 dst_layout, src_queue_mask,
2951 dst_queue_mask, range,
2952 pending_clears);
2953 }
2954
2955 void radv_CmdPipelineBarrier(
2956 VkCommandBuffer commandBuffer,
2957 VkPipelineStageFlags srcStageMask,
2958 VkPipelineStageFlags destStageMask,
2959 VkBool32 byRegion,
2960 uint32_t memoryBarrierCount,
2961 const VkMemoryBarrier* pMemoryBarriers,
2962 uint32_t bufferMemoryBarrierCount,
2963 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2964 uint32_t imageMemoryBarrierCount,
2965 const VkImageMemoryBarrier* pImageMemoryBarriers)
2966 {
2967 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2968 enum radv_cmd_flush_bits src_flush_bits = 0;
2969 enum radv_cmd_flush_bits dst_flush_bits = 0;
2970
2971 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2972 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
2973 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
2974 NULL);
2975 }
2976
2977 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2978 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
2979 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
2980 NULL);
2981 }
2982
2983 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2984 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2985 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
2986 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
2987 image);
2988 }
2989
2990 radv_stage_flush(cmd_buffer, srcStageMask);
2991 cmd_buffer->state.flush_bits |= src_flush_bits;
2992
2993 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2994 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2995 radv_handle_image_transition(cmd_buffer, image,
2996 pImageMemoryBarriers[i].oldLayout,
2997 pImageMemoryBarriers[i].newLayout,
2998 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2999 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3000 &pImageMemoryBarriers[i].subresourceRange,
3001 0);
3002 }
3003
3004 cmd_buffer->state.flush_bits |= dst_flush_bits;
3005 }
3006
3007
3008 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3009 struct radv_event *event,
3010 VkPipelineStageFlags stageMask,
3011 unsigned value)
3012 {
3013 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3014 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3015
3016 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3017
3018 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
3019
3020 /* TODO: this is overkill. Probably should figure something out from
3021 * the stage mask. */
3022
3023 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
3024 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
3025 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
3026 EVENT_INDEX(5));
3027 radeon_emit(cs, va);
3028 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
3029 radeon_emit(cs, 2);
3030 radeon_emit(cs, 0);
3031 }
3032
3033 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
3034 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
3035 EVENT_INDEX(5));
3036 radeon_emit(cs, va);
3037 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
3038 radeon_emit(cs, value);
3039 radeon_emit(cs, 0);
3040
3041 assert(cmd_buffer->cs->cdw <= cdw_max);
3042 }
3043
3044 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3045 VkEvent _event,
3046 VkPipelineStageFlags stageMask)
3047 {
3048 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3049 RADV_FROM_HANDLE(radv_event, event, _event);
3050
3051 write_event(cmd_buffer, event, stageMask, 1);
3052 }
3053
3054 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3055 VkEvent _event,
3056 VkPipelineStageFlags stageMask)
3057 {
3058 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3059 RADV_FROM_HANDLE(radv_event, event, _event);
3060
3061 write_event(cmd_buffer, event, stageMask, 0);
3062 }
3063
3064 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3065 uint32_t eventCount,
3066 const VkEvent* pEvents,
3067 VkPipelineStageFlags srcStageMask,
3068 VkPipelineStageFlags dstStageMask,
3069 uint32_t memoryBarrierCount,
3070 const VkMemoryBarrier* pMemoryBarriers,
3071 uint32_t bufferMemoryBarrierCount,
3072 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3073 uint32_t imageMemoryBarrierCount,
3074 const VkImageMemoryBarrier* pImageMemoryBarriers)
3075 {
3076 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3077 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3078
3079 for (unsigned i = 0; i < eventCount; ++i) {
3080 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3081 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3082
3083 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3084
3085 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3086
3087 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
3088 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
3089 radeon_emit(cs, va);
3090 radeon_emit(cs, va >> 32);
3091 radeon_emit(cs, 1); /* reference value */
3092 radeon_emit(cs, 0xffffffff); /* mask */
3093 radeon_emit(cs, 4); /* poll interval */
3094
3095 assert(cmd_buffer->cs->cdw <= cdw_max);
3096 }
3097
3098
3099 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3100 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3101
3102 radv_handle_image_transition(cmd_buffer, image,
3103 pImageMemoryBarriers[i].oldLayout,
3104 pImageMemoryBarriers[i].newLayout,
3105 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3106 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3107 &pImageMemoryBarriers[i].subresourceRange,
3108 0);
3109 }
3110
3111 /* TODO: figure out how to do memory barriers without waiting */
3112 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3113 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3114 RADV_CMD_FLAG_INV_VMEM_L1 |
3115 RADV_CMD_FLAG_INV_SMEM_L1;
3116 }