2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
40 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
41 struct radv_image
*image
,
42 VkImageLayout src_layout
,
43 VkImageLayout dst_layout
,
46 const VkImageSubresourceRange
*range
,
47 VkImageAspectFlags pending_clears
);
49 const struct radv_dynamic_state default_dynamic_state
= {
62 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
67 .stencil_compare_mask
= {
71 .stencil_write_mask
= {
75 .stencil_reference
= {
82 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
83 const struct radv_dynamic_state
*src
)
85 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
86 uint32_t copy_mask
= src
->mask
;
87 uint32_t dest_mask
= 0;
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
92 dest
->viewport
.count
= src
->viewport
.count
;
93 dest
->scissor
.count
= src
->scissor
.count
;
95 if (copy_mask
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
96 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
97 src
->viewport
.count
* sizeof(VkViewport
))) {
98 typed_memcpy(dest
->viewport
.viewports
,
99 src
->viewport
.viewports
,
100 src
->viewport
.count
);
101 dest_mask
|= 1 << VK_DYNAMIC_STATE_VIEWPORT
;
105 if (copy_mask
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
106 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
107 src
->scissor
.count
* sizeof(VkRect2D
))) {
108 typed_memcpy(dest
->scissor
.scissors
,
109 src
->scissor
.scissors
, src
->scissor
.count
);
110 dest_mask
|= 1 << VK_DYNAMIC_STATE_SCISSOR
;
114 if (copy_mask
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
115 if (dest
->line_width
!= src
->line_width
) {
116 dest
->line_width
= src
->line_width
;
117 dest_mask
|= 1 << VK_DYNAMIC_STATE_LINE_WIDTH
;
121 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
122 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
123 sizeof(src
->depth_bias
))) {
124 dest
->depth_bias
= src
->depth_bias
;
125 dest_mask
|= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS
;
129 if (copy_mask
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
)) {
130 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
131 sizeof(src
->blend_constants
))) {
132 typed_memcpy(dest
->blend_constants
,
133 src
->blend_constants
, 4);
134 dest_mask
|= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
;
138 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
139 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
140 sizeof(src
->depth_bounds
))) {
141 dest
->depth_bounds
= src
->depth_bounds
;
142 dest_mask
|= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
;
146 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
147 if (memcmp(&dest
->stencil_compare_mask
,
148 &src
->stencil_compare_mask
,
149 sizeof(src
->stencil_compare_mask
))) {
150 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
151 dest_mask
|= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
;
155 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
156 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
157 sizeof(src
->stencil_write_mask
))) {
158 dest
->stencil_write_mask
= src
->stencil_write_mask
;
159 dest_mask
|= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
;
163 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
164 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
165 sizeof(src
->stencil_reference
))) {
166 dest
->stencil_reference
= src
->stencil_reference
;
167 dest_mask
|= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
;
171 cmd_buffer
->state
.dirty
|= dest_mask
;
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
176 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
177 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
180 enum ring_type
radv_queue_family_to_ring(int f
) {
182 case RADV_QUEUE_GENERAL
:
184 case RADV_QUEUE_COMPUTE
:
186 case RADV_QUEUE_TRANSFER
:
189 unreachable("Unknown queue family");
193 static VkResult
radv_create_cmd_buffer(
194 struct radv_device
* device
,
195 struct radv_cmd_pool
* pool
,
196 VkCommandBufferLevel level
,
197 VkCommandBuffer
* pCommandBuffer
)
199 struct radv_cmd_buffer
*cmd_buffer
;
201 cmd_buffer
= vk_alloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
203 if (cmd_buffer
== NULL
)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
206 memset(cmd_buffer
, 0, sizeof(*cmd_buffer
));
207 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
208 cmd_buffer
->device
= device
;
209 cmd_buffer
->pool
= pool
;
210 cmd_buffer
->level
= level
;
213 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
214 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
217 /* Init the pool_link so we can safefly call list_del when we destroy
220 list_inithead(&cmd_buffer
->pool_link
);
221 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
224 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
226 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
227 if (!cmd_buffer
->cs
) {
228 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
229 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
232 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
234 cmd_buffer
->upload
.offset
= 0;
235 cmd_buffer
->upload
.size
= 0;
236 list_inithead(&cmd_buffer
->upload
.list
);
242 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
244 list_del(&cmd_buffer
->pool_link
);
246 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
247 &cmd_buffer
->upload
.list
, list
) {
248 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
253 if (cmd_buffer
->upload
.upload_bo
)
254 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
255 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
256 free(cmd_buffer
->push_descriptors
.set
.mapped_ptr
);
257 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
261 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
264 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
266 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
267 &cmd_buffer
->upload
.list
, list
) {
268 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
273 cmd_buffer
->push_constant_stages
= 0;
274 cmd_buffer
->scratch_size_needed
= 0;
275 cmd_buffer
->compute_scratch_size_needed
= 0;
276 cmd_buffer
->esgs_ring_size_needed
= 0;
277 cmd_buffer
->gsvs_ring_size_needed
= 0;
278 cmd_buffer
->tess_rings_needed
= false;
279 cmd_buffer
->sample_positions_needed
= false;
281 if (cmd_buffer
->upload
.upload_bo
)
282 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
,
283 cmd_buffer
->upload
.upload_bo
, 8);
284 cmd_buffer
->upload
.offset
= 0;
286 cmd_buffer
->record_result
= VK_SUCCESS
;
288 cmd_buffer
->ring_offsets_idx
= -1;
290 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
292 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 0,
293 &cmd_buffer
->gfx9_fence_offset
,
295 cmd_buffer
->gfx9_fence_bo
= cmd_buffer
->upload
.upload_bo
;
298 return cmd_buffer
->record_result
;
302 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
306 struct radeon_winsys_bo
*bo
;
307 struct radv_cmd_buffer_upload
*upload
;
308 struct radv_device
*device
= cmd_buffer
->device
;
310 new_size
= MAX2(min_needed
, 16 * 1024);
311 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
313 bo
= device
->ws
->buffer_create(device
->ws
,
316 RADEON_FLAG_CPU_ACCESS
|
317 RADEON_FLAG_NO_INTERPROCESS_SHARING
);
320 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
324 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, bo
, 8);
325 if (cmd_buffer
->upload
.upload_bo
) {
326 upload
= malloc(sizeof(*upload
));
329 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
330 device
->ws
->buffer_destroy(bo
);
334 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
335 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
338 cmd_buffer
->upload
.upload_bo
= bo
;
339 cmd_buffer
->upload
.size
= new_size
;
340 cmd_buffer
->upload
.offset
= 0;
341 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
343 if (!cmd_buffer
->upload
.map
) {
344 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
352 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
355 unsigned *out_offset
,
358 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
359 if (offset
+ size
> cmd_buffer
->upload
.size
) {
360 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
365 *out_offset
= offset
;
366 *ptr
= cmd_buffer
->upload
.map
+ offset
;
368 cmd_buffer
->upload
.offset
= offset
+ size
;
373 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
374 unsigned size
, unsigned alignment
,
375 const void *data
, unsigned *out_offset
)
379 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
380 out_offset
, (void **)&ptr
))
384 memcpy(ptr
, data
, size
);
390 radv_emit_write_data_packet(struct radeon_winsys_cs
*cs
, uint64_t va
,
391 unsigned count
, const uint32_t *data
)
393 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
394 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
395 S_370_WR_CONFIRM(1) |
396 S_370_ENGINE_SEL(V_370_ME
));
398 radeon_emit(cs
, va
>> 32);
399 radeon_emit_array(cs
, data
, count
);
402 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
404 struct radv_device
*device
= cmd_buffer
->device
;
405 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
408 if (!device
->trace_bo
)
411 va
= radv_buffer_get_va(device
->trace_bo
);
412 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
415 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 7);
417 ++cmd_buffer
->state
.trace_id
;
418 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
419 radv_emit_write_data_packet(cs
, va
, 1, &cmd_buffer
->state
.trace_id
);
420 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
421 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
425 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
)
427 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
428 enum radv_cmd_flush_bits flags
;
430 /* Force wait for graphics/compute engines to be idle. */
431 flags
= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
432 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
434 si_cs_emit_cache_flush(cmd_buffer
->cs
, false,
435 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
437 radv_cmd_buffer_uses_mec(cmd_buffer
),
441 radv_cmd_buffer_trace_emit(cmd_buffer
);
445 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
446 struct radv_pipeline
*pipeline
, enum ring_type ring
)
448 struct radv_device
*device
= cmd_buffer
->device
;
449 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
453 if (!device
->trace_bo
)
456 va
= radv_buffer_get_va(device
->trace_bo
);
466 assert(!"invalid ring type");
469 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
472 data
[0] = (uintptr_t)pipeline
;
473 data
[1] = (uintptr_t)pipeline
>> 32;
475 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
476 radv_emit_write_data_packet(cs
, va
, 2, data
);
480 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
482 struct radv_device
*device
= cmd_buffer
->device
;
483 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
484 uint32_t data
[MAX_SETS
* 2] = {};
487 if (!device
->trace_bo
)
490 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
492 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
493 cmd_buffer
->cs
, 4 + MAX_SETS
* 2);
495 for (int i
= 0; i
< MAX_SETS
; i
++) {
496 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
500 data
[i
* 2] = (uintptr_t)set
;
501 data
[i
* 2 + 1] = (uintptr_t)set
>> 32;
504 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
505 radv_emit_write_data_packet(cs
, va
, MAX_SETS
* 2, data
);
509 radv_emit_graphics_blend_state(struct radv_cmd_buffer
*cmd_buffer
,
510 struct radv_pipeline
*pipeline
)
512 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028780_CB_BLEND0_CONTROL
, 8);
513 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.cb_blend_control
,
515 radeon_set_context_reg(cmd_buffer
->cs
, R_028808_CB_COLOR_CONTROL
, pipeline
->graphics
.blend
.cb_color_control
);
516 radeon_set_context_reg(cmd_buffer
->cs
, R_028B70_DB_ALPHA_TO_MASK
, pipeline
->graphics
.blend
.db_alpha_to_mask
);
518 if (cmd_buffer
->device
->physical_device
->has_rbplus
) {
520 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
521 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.sx_mrt_blend_opt
, 8);
523 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
524 radeon_emit(cmd_buffer
->cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
525 radeon_emit(cmd_buffer
->cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
526 radeon_emit(cmd_buffer
->cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
531 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer
*cmd_buffer
,
532 struct radv_pipeline
*pipeline
)
534 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
535 radeon_set_context_reg(cmd_buffer
->cs
, R_028800_DB_DEPTH_CONTROL
, ds
->db_depth_control
);
536 radeon_set_context_reg(cmd_buffer
->cs
, R_02842C_DB_STENCIL_CONTROL
, ds
->db_stencil_control
);
538 radeon_set_context_reg(cmd_buffer
->cs
, R_028000_DB_RENDER_CONTROL
, ds
->db_render_control
);
539 radeon_set_context_reg(cmd_buffer
->cs
, R_028010_DB_RENDER_OVERRIDE2
, ds
->db_render_override2
);
542 struct ac_userdata_info
*
543 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
544 gl_shader_stage stage
,
547 if (stage
== MESA_SHADER_VERTEX
) {
548 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
549 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.user_sgprs_locs
.shader_data
[idx
];
550 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
551 return &pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.user_sgprs_locs
.shader_data
[idx
];
552 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
553 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.user_sgprs_locs
.shader_data
[idx
];
554 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
555 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
556 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.user_sgprs_locs
.shader_data
[idx
];
557 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
558 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.user_sgprs_locs
.shader_data
[idx
];
560 return &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.shader_data
[idx
];
564 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
565 struct radv_pipeline
*pipeline
,
566 gl_shader_stage stage
,
567 int idx
, uint64_t va
)
569 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
570 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
571 if (loc
->sgpr_idx
== -1)
573 assert(loc
->num_sgprs
== 2);
574 assert(!loc
->indirect
);
575 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 2);
576 radeon_emit(cmd_buffer
->cs
, va
);
577 radeon_emit(cmd_buffer
->cs
, va
>> 32);
581 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
582 struct radv_pipeline
*pipeline
)
584 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
585 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
586 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
588 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
589 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[0]);
590 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[1]);
592 radeon_set_context_reg(cmd_buffer
->cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
593 radeon_set_context_reg(cmd_buffer
->cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
595 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
598 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
599 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
600 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
602 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
604 /* GFX9: Flush DFSM when the AA mode changes. */
605 if (cmd_buffer
->device
->dfsm_allowed
) {
606 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
607 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
609 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
) {
611 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_FRAGMENT
, AC_UD_PS_SAMPLE_POS_OFFSET
);
612 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
613 if (loc
->sgpr_idx
== -1)
615 assert(loc
->num_sgprs
== 1);
616 assert(!loc
->indirect
);
617 switch (num_samples
) {
635 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, offset
);
636 cmd_buffer
->sample_positions_needed
= true;
641 radv_emit_graphics_raster_state(struct radv_cmd_buffer
*cmd_buffer
,
642 struct radv_pipeline
*pipeline
)
644 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
646 radeon_set_context_reg(cmd_buffer
->cs
, R_028810_PA_CL_CLIP_CNTL
,
647 raster
->pa_cl_clip_cntl
);
648 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
649 raster
->spi_interp_control
);
650 radeon_set_context_reg(cmd_buffer
->cs
, R_028BE4_PA_SU_VTX_CNTL
,
651 raster
->pa_su_vtx_cntl
);
652 radeon_set_context_reg(cmd_buffer
->cs
, R_028814_PA_SU_SC_MODE_CNTL
,
653 raster
->pa_su_sc_mode_cntl
);
657 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
658 struct radv_shader_variant
*shader
)
660 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
661 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
667 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
669 ws
->cs_add_buffer(cs
, shader
->bo
, 8);
670 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
671 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
675 radv_emit_shaders_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
676 struct radv_pipeline
*pipeline
)
678 radv_emit_shader_prefetch(cmd_buffer
,
679 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
680 radv_emit_shader_prefetch(cmd_buffer
,
681 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
682 radv_emit_shader_prefetch(cmd_buffer
,
683 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
684 radv_emit_shader_prefetch(cmd_buffer
,
685 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
686 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
687 radv_emit_shader_prefetch(cmd_buffer
,
688 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
692 radv_emit_hw_vs(struct radv_cmd_buffer
*cmd_buffer
,
693 struct radv_pipeline
*pipeline
,
694 struct radv_shader_variant
*shader
,
695 struct ac_vs_output_info
*outinfo
)
697 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
698 unsigned export_count
;
700 export_count
= MAX2(1, outinfo
->param_exports
);
701 radeon_set_context_reg(cmd_buffer
->cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
702 S_0286C4_VS_EXPORT_COUNT(export_count
- 1));
704 radeon_set_context_reg(cmd_buffer
->cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
705 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
706 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
707 V_02870C_SPI_SHADER_4COMP
:
708 V_02870C_SPI_SHADER_NONE
) |
709 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
710 V_02870C_SPI_SHADER_4COMP
:
711 V_02870C_SPI_SHADER_NONE
) |
712 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
713 V_02870C_SPI_SHADER_4COMP
:
714 V_02870C_SPI_SHADER_NONE
));
717 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
718 radeon_emit(cmd_buffer
->cs
, va
>> 8);
719 radeon_emit(cmd_buffer
->cs
, va
>> 40);
720 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
721 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
723 radeon_set_context_reg(cmd_buffer
->cs
, R_028818_PA_CL_VTE_CNTL
,
724 S_028818_VTX_W0_FMT(1) |
725 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
726 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
727 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
730 radeon_set_context_reg(cmd_buffer
->cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
731 pipeline
->graphics
.pa_cl_vs_out_cntl
);
733 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= VI
)
734 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB4_VGT_REUSE_OFF
,
735 S_028AB4_REUSE_OFF(outinfo
->writes_viewport_index
));
739 radv_emit_hw_es(struct radv_cmd_buffer
*cmd_buffer
,
740 struct radv_shader_variant
*shader
,
741 struct ac_es_output_info
*outinfo
)
743 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
745 radeon_set_context_reg(cmd_buffer
->cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
746 outinfo
->esgs_itemsize
/ 4);
747 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
748 radeon_emit(cmd_buffer
->cs
, va
>> 8);
749 radeon_emit(cmd_buffer
->cs
, va
>> 40);
750 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
751 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
755 radv_emit_hw_ls(struct radv_cmd_buffer
*cmd_buffer
,
756 struct radv_shader_variant
*shader
)
758 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
759 uint32_t rsrc2
= shader
->rsrc2
;
761 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
762 radeon_emit(cmd_buffer
->cs
, va
>> 8);
763 radeon_emit(cmd_buffer
->cs
, va
>> 40);
765 rsrc2
|= S_00B52C_LDS_SIZE(cmd_buffer
->state
.pipeline
->graphics
.tess
.lds_size
);
766 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== CIK
&&
767 cmd_buffer
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
768 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
770 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
771 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
772 radeon_emit(cmd_buffer
->cs
, rsrc2
);
776 radv_emit_hw_hs(struct radv_cmd_buffer
*cmd_buffer
,
777 struct radv_shader_variant
*shader
)
779 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
781 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
782 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
783 radeon_emit(cmd_buffer
->cs
, va
>> 8);
784 radeon_emit(cmd_buffer
->cs
, va
>> 40);
786 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
787 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
788 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
|
789 S_00B42C_LDS_SIZE(cmd_buffer
->state
.pipeline
->graphics
.tess
.lds_size
));
791 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
792 radeon_emit(cmd_buffer
->cs
, va
>> 8);
793 radeon_emit(cmd_buffer
->cs
, va
>> 40);
794 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
795 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
800 radv_emit_vertex_shader(struct radv_cmd_buffer
*cmd_buffer
,
801 struct radv_pipeline
*pipeline
)
803 struct radv_shader_variant
*vs
;
805 radeon_set_context_reg(cmd_buffer
->cs
, R_028A84_VGT_PRIMITIVEID_EN
, pipeline
->graphics
.vgt_primitiveid_en
);
807 /* Skip shaders merged into HS/GS */
808 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
812 if (vs
->info
.vs
.as_ls
)
813 radv_emit_hw_ls(cmd_buffer
, vs
);
814 else if (vs
->info
.vs
.as_es
)
815 radv_emit_hw_es(cmd_buffer
, vs
, &vs
->info
.vs
.es_info
);
817 radv_emit_hw_vs(cmd_buffer
, pipeline
, vs
, &vs
->info
.vs
.outinfo
);
822 radv_emit_tess_shaders(struct radv_cmd_buffer
*cmd_buffer
,
823 struct radv_pipeline
*pipeline
)
825 if (!radv_pipeline_has_tess(pipeline
))
828 struct radv_shader_variant
*tes
, *tcs
;
830 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
831 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
834 if (tes
->info
.tes
.as_es
)
835 radv_emit_hw_es(cmd_buffer
, tes
, &tes
->info
.tes
.es_info
);
837 radv_emit_hw_vs(cmd_buffer
, pipeline
, tes
, &tes
->info
.tes
.outinfo
);
840 radv_emit_hw_hs(cmd_buffer
, tcs
);
842 radeon_set_context_reg(cmd_buffer
->cs
, R_028B6C_VGT_TF_PARAM
,
843 pipeline
->graphics
.tess
.tf_param
);
845 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
846 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
847 pipeline
->graphics
.tess
.ls_hs_config
);
849 radeon_set_context_reg(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
,
850 pipeline
->graphics
.tess
.ls_hs_config
);
852 struct ac_userdata_info
*loc
;
854 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_CTRL
, AC_UD_TCS_OFFCHIP_LAYOUT
);
855 if (loc
->sgpr_idx
!= -1) {
856 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
857 assert(loc
->num_sgprs
== 4);
858 assert(!loc
->indirect
);
859 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 4);
860 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.offchip_layout
);
861 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_offsets
);
862 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_layout
|
863 pipeline
->graphics
.tess
.num_tcs_input_cp
<< 26);
864 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_in_layout
);
867 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_EVAL
, AC_UD_TES_OFFCHIP_LAYOUT
);
868 if (loc
->sgpr_idx
!= -1) {
869 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
870 assert(loc
->num_sgprs
== 1);
871 assert(!loc
->indirect
);
873 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
874 pipeline
->graphics
.tess
.offchip_layout
);
877 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
, AC_UD_VS_LS_TCS_IN_LAYOUT
);
878 if (loc
->sgpr_idx
!= -1) {
879 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
880 assert(loc
->num_sgprs
== 1);
881 assert(!loc
->indirect
);
883 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
884 pipeline
->graphics
.tess
.tcs_in_layout
);
889 radv_emit_geometry_shader(struct radv_cmd_buffer
*cmd_buffer
,
890 struct radv_pipeline
*pipeline
)
892 struct radv_shader_variant
*gs
;
895 radeon_set_context_reg(cmd_buffer
->cs
, R_028A40_VGT_GS_MODE
, pipeline
->graphics
.vgt_gs_mode
);
897 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
901 uint32_t gsvs_itemsize
= gs
->info
.gs
.max_gsvs_emit_size
>> 2;
903 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
904 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
905 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
906 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
908 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
);
910 radeon_set_context_reg(cmd_buffer
->cs
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs
->info
.gs
.vertices_out
);
912 uint32_t gs_vert_itemsize
= gs
->info
.gs
.gsvs_vertex_size
;
913 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
914 radeon_emit(cmd_buffer
->cs
, gs_vert_itemsize
>> 2);
915 radeon_emit(cmd_buffer
->cs
, 0);
916 radeon_emit(cmd_buffer
->cs
, 0);
917 radeon_emit(cmd_buffer
->cs
, 0);
919 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
920 radeon_set_context_reg(cmd_buffer
->cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
921 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
922 S_028B90_ENABLE(gs_num_invocations
> 0));
924 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
926 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
927 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
928 radeon_emit(cmd_buffer
->cs
, va
>> 8);
929 radeon_emit(cmd_buffer
->cs
, va
>> 40);
931 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
932 radeon_emit(cmd_buffer
->cs
, gs
->rsrc1
);
933 radeon_emit(cmd_buffer
->cs
, gs
->rsrc2
|
934 S_00B22C_LDS_SIZE(pipeline
->graphics
.gs
.lds_size
));
936 radeon_set_context_reg(cmd_buffer
->cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, pipeline
->graphics
.gs
.vgt_gs_onchip_cntl
);
937 radeon_set_context_reg(cmd_buffer
->cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, pipeline
->graphics
.gs
.vgt_gs_max_prims_per_subgroup
);
938 radeon_set_context_reg(cmd_buffer
->cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
, pipeline
->graphics
.gs
.vgt_esgs_ring_itemsize
);
940 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
941 radeon_emit(cmd_buffer
->cs
, va
>> 8);
942 radeon_emit(cmd_buffer
->cs
, va
>> 40);
943 radeon_emit(cmd_buffer
->cs
, gs
->rsrc1
);
944 radeon_emit(cmd_buffer
->cs
, gs
->rsrc2
);
947 radv_emit_hw_vs(cmd_buffer
, pipeline
, pipeline
->gs_copy_shader
, &pipeline
->gs_copy_shader
->info
.vs
.outinfo
);
949 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
950 AC_UD_GS_VS_RING_STRIDE_ENTRIES
);
951 if (loc
->sgpr_idx
!= -1) {
952 uint32_t stride
= gs
->info
.gs
.max_gsvs_emit_size
;
953 uint32_t num_entries
= 64;
954 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
957 num_entries
*= stride
;
959 stride
= S_008F04_STRIDE(stride
);
960 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
+ loc
->sgpr_idx
* 4, 2);
961 radeon_emit(cmd_buffer
->cs
, stride
);
962 radeon_emit(cmd_buffer
->cs
, num_entries
);
967 radv_emit_fragment_shader(struct radv_cmd_buffer
*cmd_buffer
,
968 struct radv_pipeline
*pipeline
)
970 struct radv_shader_variant
*ps
;
972 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
973 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
974 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
976 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
977 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
979 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
980 radeon_emit(cmd_buffer
->cs
, va
>> 8);
981 radeon_emit(cmd_buffer
->cs
, va
>> 40);
982 radeon_emit(cmd_buffer
->cs
, ps
->rsrc1
);
983 radeon_emit(cmd_buffer
->cs
, ps
->rsrc2
);
985 radeon_set_context_reg(cmd_buffer
->cs
, R_02880C_DB_SHADER_CONTROL
,
986 pipeline
->graphics
.db_shader_control
);
988 radeon_set_context_reg(cmd_buffer
->cs
, R_0286CC_SPI_PS_INPUT_ENA
,
989 ps
->config
.spi_ps_input_ena
);
991 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
992 ps
->config
.spi_ps_input_addr
);
994 if (ps
->info
.info
.ps
.force_persample
)
995 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
997 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D8_SPI_PS_IN_CONTROL
,
998 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
1000 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
1002 radeon_set_context_reg(cmd_buffer
->cs
, R_028710_SPI_SHADER_Z_FORMAT
,
1003 pipeline
->graphics
.shader_z_format
);
1005 radeon_set_context_reg(cmd_buffer
->cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
1007 radeon_set_context_reg(cmd_buffer
->cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
1008 radeon_set_context_reg(cmd_buffer
->cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
1010 if (cmd_buffer
->device
->dfsm_allowed
) {
1011 /* optimise this? */
1012 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1013 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
1016 if (pipeline
->graphics
.ps_input_cntl_num
) {
1017 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028644_SPI_PS_INPUT_CNTL_0
, pipeline
->graphics
.ps_input_cntl_num
);
1018 for (unsigned i
= 0; i
< pipeline
->graphics
.ps_input_cntl_num
; i
++) {
1019 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.ps_input_cntl
[i
]);
1025 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer
*cmd_buffer
,
1026 struct radv_pipeline
*pipeline
)
1028 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1030 if (cmd_buffer
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
)
1033 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1034 pipeline
->graphics
.vtx_reuse_depth
);
1038 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1040 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1042 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
1045 radv_emit_graphics_depth_stencil_state(cmd_buffer
, pipeline
);
1046 radv_emit_graphics_blend_state(cmd_buffer
, pipeline
);
1047 radv_emit_graphics_raster_state(cmd_buffer
, pipeline
);
1048 radv_update_multisample_state(cmd_buffer
, pipeline
);
1049 radv_emit_vertex_shader(cmd_buffer
, pipeline
);
1050 radv_emit_tess_shaders(cmd_buffer
, pipeline
);
1051 radv_emit_geometry_shader(cmd_buffer
, pipeline
);
1052 radv_emit_fragment_shader(cmd_buffer
, pipeline
);
1053 radv_emit_vgt_vertex_reuse(cmd_buffer
, pipeline
);
1055 cmd_buffer
->scratch_size_needed
=
1056 MAX2(cmd_buffer
->scratch_size_needed
,
1057 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
1059 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E8_SPI_TMPRING_SIZE
,
1060 S_0286E8_WAVES(pipeline
->max_waves
) |
1061 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
1063 if (!cmd_buffer
->state
.emitted_pipeline
||
1064 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1065 pipeline
->graphics
.can_use_guardband
)
1066 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1068 radeon_set_context_reg(cmd_buffer
->cs
, R_028B54_VGT_SHADER_STAGES_EN
, pipeline
->graphics
.vgt_shader_stages_en
);
1070 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1071 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, pipeline
->graphics
.prim
);
1073 radeon_set_config_reg(cmd_buffer
->cs
, R_008958_VGT_PRIMITIVE_TYPE
, pipeline
->graphics
.prim
);
1075 radeon_set_context_reg(cmd_buffer
->cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, pipeline
->graphics
.gs_out
);
1077 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1079 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1081 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1085 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1087 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1088 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1092 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1094 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1096 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1097 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1098 si_emit_cache_flush(cmd_buffer
);
1100 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1101 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1102 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1103 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1104 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
,
1105 cmd_buffer
->state
.pipeline
->graphics
.ms
.pa_sc_mode_cntl_0
| S_028A48_VPORT_SCISSOR_ENABLE(count
? 1 : 0));
1109 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1111 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1113 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1114 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1118 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1120 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1122 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1123 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1127 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1129 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1131 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1132 R_028430_DB_STENCILREFMASK
, 2);
1133 radeon_emit(cmd_buffer
->cs
,
1134 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1135 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1136 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1137 S_028430_STENCILOPVAL(1));
1138 radeon_emit(cmd_buffer
->cs
,
1139 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1140 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1141 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1142 S_028434_STENCILOPVAL_BF(1));
1146 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1148 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1150 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1151 fui(d
->depth_bounds
.min
));
1152 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1153 fui(d
->depth_bounds
.max
));
1157 radv_emit_depth_biais(struct radv_cmd_buffer
*cmd_buffer
)
1159 struct radv_raster_state
*raster
= &cmd_buffer
->state
.pipeline
->graphics
.raster
;
1160 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1161 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1162 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1164 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster
->pa_su_sc_mode_cntl
)) {
1165 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1166 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1167 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1168 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1169 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1170 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1171 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1176 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1178 struct radv_color_buffer_info
*cb
)
1180 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
1182 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1183 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1184 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1185 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
>> 32);
1186 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1187 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1188 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
1189 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1190 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1191 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1192 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
>> 32);
1193 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1194 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
>> 32);
1196 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1197 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1198 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
>> 32);
1200 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1203 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1204 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1205 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1206 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1207 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1208 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
1209 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1210 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1211 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1212 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1213 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1214 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1216 if (is_vi
) { /* DCC BASE */
1217 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1223 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1224 struct radv_ds_buffer_info
*ds
,
1225 struct radv_image
*image
,
1226 VkImageLayout layout
)
1228 uint32_t db_z_info
= ds
->db_z_info
;
1229 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1231 if (!radv_layout_has_htile(image
, layout
,
1232 radv_image_queue_family_mask(image
,
1233 cmd_buffer
->queue_family_index
,
1234 cmd_buffer
->queue_family_index
))) {
1235 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1236 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1239 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1240 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1243 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1244 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1245 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1246 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1247 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1249 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1250 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1251 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1252 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1253 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32); /* DB_Z_READ_BASE_HI */
1254 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1255 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
1256 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1257 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
>> 32); /* DB_Z_WRITE_BASE_HI */
1258 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1259 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
1261 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1262 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1263 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1265 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1267 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1268 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1269 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1270 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1271 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1272 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1273 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1274 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1275 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1276 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1280 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1281 ds
->pa_su_poly_offset_db_fmt_cntl
);
1285 radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1286 struct radv_image
*image
,
1287 VkClearDepthStencilValue ds_clear_value
,
1288 VkImageAspectFlags aspects
)
1290 uint64_t va
= radv_buffer_get_va(image
->bo
);
1291 va
+= image
->offset
+ image
->clear_value_offset
;
1292 unsigned reg_offset
= 0, reg_count
= 0;
1294 if (!image
->surface
.htile_size
|| !aspects
)
1297 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1303 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1306 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1308 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
1309 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1310 S_370_WR_CONFIRM(1) |
1311 S_370_ENGINE_SEL(V_370_PFP
));
1312 radeon_emit(cmd_buffer
->cs
, va
);
1313 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1314 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1315 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
);
1316 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1317 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
));
1319 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
, reg_count
);
1320 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1321 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
); /* R_028028_DB_STENCIL_CLEAR */
1322 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1323 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
)); /* R_02802C_DB_DEPTH_CLEAR */
1327 radv_load_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1328 struct radv_image
*image
)
1330 uint64_t va
= radv_buffer_get_va(image
->bo
);
1331 va
+= image
->offset
+ image
->clear_value_offset
;
1333 if (!image
->surface
.htile_size
)
1336 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1338 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1339 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1340 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1341 COPY_DATA_COUNT_SEL
);
1342 radeon_emit(cmd_buffer
->cs
, va
);
1343 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1344 radeon_emit(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
>> 2);
1345 radeon_emit(cmd_buffer
->cs
, 0);
1347 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1348 radeon_emit(cmd_buffer
->cs
, 0);
1352 *with DCC some colors don't require CMASK elimiation before being
1353 * used as a texture. This sets a predicate value to determine if the
1354 * cmask eliminate is required.
1357 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1358 struct radv_image
*image
,
1361 uint64_t pred_val
= value
;
1362 uint64_t va
= radv_buffer_get_va(image
->bo
);
1363 va
+= image
->offset
+ image
->dcc_pred_offset
;
1365 if (!image
->surface
.dcc_size
)
1368 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1370 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1371 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1372 S_370_WR_CONFIRM(1) |
1373 S_370_ENGINE_SEL(V_370_PFP
));
1374 radeon_emit(cmd_buffer
->cs
, va
);
1375 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1376 radeon_emit(cmd_buffer
->cs
, pred_val
);
1377 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1381 radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1382 struct radv_image
*image
,
1384 uint32_t color_values
[2])
1386 uint64_t va
= radv_buffer_get_va(image
->bo
);
1387 va
+= image
->offset
+ image
->clear_value_offset
;
1389 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1392 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1394 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1395 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1396 S_370_WR_CONFIRM(1) |
1397 S_370_ENGINE_SEL(V_370_PFP
));
1398 radeon_emit(cmd_buffer
->cs
, va
);
1399 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1400 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1401 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1403 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c, 2);
1404 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1405 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1409 radv_load_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1410 struct radv_image
*image
,
1413 uint64_t va
= radv_buffer_get_va(image
->bo
);
1414 va
+= image
->offset
+ image
->clear_value_offset
;
1416 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1419 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c;
1420 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1422 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1423 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1424 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1425 COPY_DATA_COUNT_SEL
);
1426 radeon_emit(cmd_buffer
->cs
, va
);
1427 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1428 radeon_emit(cmd_buffer
->cs
, reg
>> 2);
1429 radeon_emit(cmd_buffer
->cs
, 0);
1431 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1432 radeon_emit(cmd_buffer
->cs
, 0);
1436 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1439 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1440 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1442 /* this may happen for inherited secondary recording */
1446 for (i
= 0; i
< 8; ++i
) {
1447 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1448 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1449 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1453 int idx
= subpass
->color_attachments
[i
].attachment
;
1454 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1456 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1458 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
1459 radv_emit_fb_color_state(cmd_buffer
, i
, &att
->cb
);
1461 radv_load_color_clear_regs(cmd_buffer
, att
->attachment
->image
, i
);
1464 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1465 int idx
= subpass
->depth_stencil_attachment
.attachment
;
1466 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1467 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1468 struct radv_image
*image
= att
->attachment
->image
;
1469 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1470 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1471 cmd_buffer
->queue_family_index
,
1472 cmd_buffer
->queue_family_index
);
1473 /* We currently don't support writing decompressed HTILE */
1474 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1475 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1477 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1479 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1480 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1481 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1483 radv_load_depth_clear_regs(cmd_buffer
, image
);
1485 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1486 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1488 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1490 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1491 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1493 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1494 S_028208_BR_X(framebuffer
->width
) |
1495 S_028208_BR_Y(framebuffer
->height
));
1497 if (cmd_buffer
->device
->dfsm_allowed
) {
1498 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1499 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1502 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
1506 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1508 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1510 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1511 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
1512 2, cmd_buffer
->state
.index_type
);
1514 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1515 radeon_emit(cs
, cmd_buffer
->state
.index_type
);
1518 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
1519 radeon_emit(cs
, cmd_buffer
->state
.index_va
);
1520 radeon_emit(cs
, cmd_buffer
->state
.index_va
>> 32);
1522 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1523 radeon_emit(cs
, cmd_buffer
->state
.max_index_count
);
1525 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
1528 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1530 uint32_t db_count_control
;
1532 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1533 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1534 db_count_control
= 0;
1536 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1539 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1540 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1541 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1542 S_028004_ZPASS_ENABLE(1) |
1543 S_028004_SLICE_EVEN_ENABLE(1) |
1544 S_028004_SLICE_ODD_ENABLE(1);
1546 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1547 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1551 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1555 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1557 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer
->state
.pipeline
->graphics
.raster
.pa_cl_clip_cntl
))
1560 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1561 radv_emit_viewport(cmd_buffer
);
1563 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1564 radv_emit_scissor(cmd_buffer
);
1566 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
1567 radv_emit_line_width(cmd_buffer
);
1569 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1570 radv_emit_blend_constants(cmd_buffer
);
1572 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1573 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1574 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
1575 radv_emit_stencil(cmd_buffer
);
1577 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
1578 radv_emit_depth_bounds(cmd_buffer
);
1580 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
1581 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
))
1582 radv_emit_depth_biais(cmd_buffer
);
1584 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
1588 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1589 struct radv_pipeline
*pipeline
,
1592 gl_shader_stage stage
)
1594 struct ac_userdata_info
*desc_set_loc
= &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.descriptor_sets
[idx
];
1595 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
1597 if (desc_set_loc
->sgpr_idx
== -1 || desc_set_loc
->indirect
)
1600 assert(!desc_set_loc
->indirect
);
1601 assert(desc_set_loc
->num_sgprs
== 2);
1602 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
1603 base_reg
+ desc_set_loc
->sgpr_idx
* 4, 2);
1604 radeon_emit(cmd_buffer
->cs
, va
);
1605 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1609 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1610 VkShaderStageFlags stages
,
1611 struct radv_descriptor_set
*set
,
1614 if (cmd_buffer
->state
.pipeline
) {
1615 radv_foreach_stage(stage
, stages
) {
1616 if (cmd_buffer
->state
.pipeline
->shaders
[stage
])
1617 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1623 if (cmd_buffer
->state
.compute_pipeline
&& (stages
& VK_SHADER_STAGE_COMPUTE_BIT
))
1624 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
1626 MESA_SHADER_COMPUTE
);
1630 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
1632 struct radv_descriptor_set
*set
= &cmd_buffer
->push_descriptors
.set
;
1635 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
1640 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1641 set
->va
+= bo_offset
;
1645 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
)
1647 uint32_t size
= MAX_SETS
* 2 * 4;
1651 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1652 256, &offset
, &ptr
))
1655 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1656 uint32_t *uptr
= ((uint32_t *)ptr
) + i
* 2;
1657 uint64_t set_va
= 0;
1658 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
1661 uptr
[0] = set_va
& 0xffffffff;
1662 uptr
[1] = set_va
>> 32;
1665 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1668 if (cmd_buffer
->state
.pipeline
) {
1669 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1670 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1671 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1673 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1674 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1675 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1677 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1678 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1679 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1681 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1682 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1683 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1685 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1686 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1687 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1690 if (cmd_buffer
->state
.compute_pipeline
)
1691 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1692 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1696 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1697 VkShaderStageFlags stages
)
1701 if (!cmd_buffer
->state
.descriptors_dirty
)
1704 if (cmd_buffer
->state
.push_descriptors_dirty
)
1705 radv_flush_push_descriptors(cmd_buffer
);
1707 if ((cmd_buffer
->state
.pipeline
&& cmd_buffer
->state
.pipeline
->need_indirect_descriptor_sets
) ||
1708 (cmd_buffer
->state
.compute_pipeline
&& cmd_buffer
->state
.compute_pipeline
->need_indirect_descriptor_sets
)) {
1709 radv_flush_indirect_descriptor_sets(cmd_buffer
);
1712 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1714 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1716 for_each_bit(i
, cmd_buffer
->state
.descriptors_dirty
) {
1717 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
1721 radv_emit_descriptor_set_userdata(cmd_buffer
, stages
, set
, i
);
1723 cmd_buffer
->state
.descriptors_dirty
= 0;
1724 cmd_buffer
->state
.push_descriptors_dirty
= false;
1726 radv_save_descriptors(cmd_buffer
);
1728 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1732 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1733 struct radv_pipeline
*pipeline
,
1734 VkShaderStageFlags stages
)
1736 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1741 stages
&= cmd_buffer
->push_constant_stages
;
1742 if (!stages
|| !layout
|| (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1745 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1746 16 * layout
->dynamic_offset_count
,
1747 256, &offset
, &ptr
))
1750 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1751 memcpy((char*)ptr
+ layout
->push_constant_size
, cmd_buffer
->dynamic_buffers
,
1752 16 * layout
->dynamic_offset_count
);
1754 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1757 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1758 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1760 radv_foreach_stage(stage
, stages
) {
1761 if (pipeline
->shaders
[stage
]) {
1762 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1763 AC_UD_PUSH_CONSTANTS
, va
);
1767 cmd_buffer
->push_constant_stages
&= ~stages
;
1768 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1772 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
1774 struct radv_device
*device
= cmd_buffer
->device
;
1776 if ((pipeline_is_dirty
|| cmd_buffer
->state
.vb_dirty
) &&
1777 cmd_buffer
->state
.pipeline
->vertex_elements
.count
&&
1778 radv_get_vertex_shader(cmd_buffer
->state
.pipeline
)->info
.info
.vs
.has_vertex_buffers
) {
1779 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
1783 uint32_t count
= velems
->count
;
1786 /* allocate some descriptor state for vertex buffers */
1787 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
1788 &vb_offset
, &vb_ptr
))
1791 for (i
= 0; i
< count
; i
++) {
1792 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
1794 int vb
= velems
->binding
[i
];
1795 struct radv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1796 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
1798 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, buffer
->bo
, 8);
1799 va
= radv_buffer_get_va(buffer
->bo
);
1801 offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
+ velems
->offset
[i
];
1802 va
+= offset
+ buffer
->offset
;
1804 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
1805 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= CIK
&& stride
)
1806 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
1808 desc
[2] = buffer
->size
- offset
;
1809 desc
[3] = velems
->rsrc_word3
[i
];
1812 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1815 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1816 AC_UD_VS_VERTEX_BUFFERS
, va
);
1818 cmd_buffer
->state
.vb_dirty
= false;
1824 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
1826 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
))
1829 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
1830 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1831 VK_SHADER_STAGE_ALL_GRAPHICS
);
1837 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
, bool indexed_draw
,
1838 bool instanced_draw
, bool indirect_draw
,
1839 uint32_t draw_vertex_count
)
1841 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
1842 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1843 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1844 uint32_t ia_multi_vgt_param
;
1845 int32_t primitive_reset_en
;
1848 ia_multi_vgt_param
=
1849 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
1850 indirect_draw
, draw_vertex_count
);
1852 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
1853 if (info
->chip_class
>= GFX9
) {
1854 radeon_set_uconfig_reg_idx(cs
,
1855 R_030960_IA_MULTI_VGT_PARAM
,
1856 4, ia_multi_vgt_param
);
1857 } else if (info
->chip_class
>= CIK
) {
1858 radeon_set_context_reg_idx(cs
,
1859 R_028AA8_IA_MULTI_VGT_PARAM
,
1860 1, ia_multi_vgt_param
);
1862 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
1863 ia_multi_vgt_param
);
1865 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
1868 /* Primitive restart. */
1869 primitive_reset_en
=
1870 indexed_draw
&& state
->pipeline
->graphics
.prim_restart_enable
;
1872 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
1873 state
->last_primitive_reset_en
= primitive_reset_en
;
1874 if (info
->chip_class
>= GFX9
) {
1875 radeon_set_uconfig_reg(cs
,
1876 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
1877 primitive_reset_en
);
1879 radeon_set_context_reg(cs
,
1880 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
1881 primitive_reset_en
);
1885 if (primitive_reset_en
) {
1886 uint32_t primitive_reset_index
=
1887 state
->index_type
? 0xffffffffu
: 0xffffu
;
1889 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
1890 radeon_set_context_reg(cs
,
1891 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
1892 primitive_reset_index
);
1893 state
->last_primitive_reset_index
= primitive_reset_index
;
1898 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
1899 VkPipelineStageFlags src_stage_mask
)
1901 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
1902 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1903 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1904 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1905 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
1908 if (src_stage_mask
& (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
1909 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
1910 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
1911 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
1912 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
1913 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
1914 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
1915 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1916 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1917 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
1918 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1919 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1920 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
1921 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
1922 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
)) {
1923 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
1927 static enum radv_cmd_flush_bits
1928 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1929 VkAccessFlags src_flags
)
1931 enum radv_cmd_flush_bits flush_bits
= 0;
1933 for_each_bit(b
, src_flags
) {
1934 switch ((VkAccessFlagBits
)(1 << b
)) {
1935 case VK_ACCESS_SHADER_WRITE_BIT
:
1936 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
1938 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1939 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1940 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1942 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1943 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1944 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1946 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1947 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1948 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1949 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1950 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
1951 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1960 static enum radv_cmd_flush_bits
1961 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1962 VkAccessFlags dst_flags
,
1963 struct radv_image
*image
)
1965 enum radv_cmd_flush_bits flush_bits
= 0;
1967 for_each_bit(b
, dst_flags
) {
1968 switch ((VkAccessFlagBits
)(1 << b
)) {
1969 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1970 case VK_ACCESS_INDEX_READ_BIT
:
1971 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1973 case VK_ACCESS_UNIFORM_READ_BIT
:
1974 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
1976 case VK_ACCESS_SHADER_READ_BIT
:
1977 case VK_ACCESS_TRANSFER_READ_BIT
:
1978 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1979 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
1980 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1982 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
1983 /* TODO: change to image && when the image gets passed
1984 * through from the subpass. */
1985 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
1986 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1987 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1989 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
1990 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
1991 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1992 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2001 static void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
, const struct radv_subpass_barrier
*barrier
)
2003 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
);
2004 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2005 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2009 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2010 VkAttachmentReference att
)
2012 unsigned idx
= att
.attachment
;
2013 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
2014 VkImageSubresourceRange range
;
2015 range
.aspectMask
= 0;
2016 range
.baseMipLevel
= view
->base_mip
;
2017 range
.levelCount
= 1;
2018 range
.baseArrayLayer
= view
->base_layer
;
2019 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2021 radv_handle_image_transition(cmd_buffer
,
2023 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2024 att
.layout
, 0, 0, &range
,
2025 cmd_buffer
->state
.attachments
[idx
].pending_clear_aspects
);
2027 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2033 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2034 const struct radv_subpass
*subpass
, bool transitions
)
2037 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
2039 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
2040 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
2041 radv_handle_subpass_image_transition(cmd_buffer
,
2042 subpass
->color_attachments
[i
]);
2045 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
2046 radv_handle_subpass_image_transition(cmd_buffer
,
2047 subpass
->input_attachments
[i
]);
2050 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
2051 radv_handle_subpass_image_transition(cmd_buffer
,
2052 subpass
->depth_stencil_attachment
);
2056 cmd_buffer
->state
.subpass
= subpass
;
2058 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2062 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
2063 struct radv_render_pass
*pass
,
2064 const VkRenderPassBeginInfo
*info
)
2066 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2068 if (pass
->attachment_count
== 0) {
2069 state
->attachments
= NULL
;
2073 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2074 pass
->attachment_count
*
2075 sizeof(state
->attachments
[0]),
2076 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2077 if (state
->attachments
== NULL
) {
2078 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2079 return cmd_buffer
->record_result
;
2082 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
2083 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
2084 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
2085 VkImageAspectFlags clear_aspects
= 0;
2087 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2088 /* color attachment */
2089 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2090 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
2093 /* depthstencil attachment */
2094 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2095 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2096 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
2097 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2098 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
2099 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2101 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2102 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2103 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2107 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
2108 state
->attachments
[i
].cleared_views
= 0;
2109 if (clear_aspects
&& info
) {
2110 assert(info
->clearValueCount
> i
);
2111 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
2114 state
->attachments
[i
].current_layout
= att
->initial_layout
;
2120 VkResult
radv_AllocateCommandBuffers(
2122 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
2123 VkCommandBuffer
*pCommandBuffers
)
2125 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2126 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
2128 VkResult result
= VK_SUCCESS
;
2131 memset(pCommandBuffers
, 0,
2132 sizeof(*pCommandBuffers
)*pAllocateInfo
->commandBufferCount
);
2134 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
2136 if (!list_empty(&pool
->free_cmd_buffers
)) {
2137 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
2139 list_del(&cmd_buffer
->pool_link
);
2140 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
2142 result
= radv_reset_cmd_buffer(cmd_buffer
);
2143 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2144 cmd_buffer
->level
= pAllocateInfo
->level
;
2146 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
2148 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
2149 &pCommandBuffers
[i
]);
2151 if (result
!= VK_SUCCESS
)
2155 if (result
!= VK_SUCCESS
)
2156 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
2157 i
, pCommandBuffers
);
2162 void radv_FreeCommandBuffers(
2164 VkCommandPool commandPool
,
2165 uint32_t commandBufferCount
,
2166 const VkCommandBuffer
*pCommandBuffers
)
2168 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2169 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
2172 if (cmd_buffer
->pool
) {
2173 list_del(&cmd_buffer
->pool_link
);
2174 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
2176 radv_cmd_buffer_destroy(cmd_buffer
);
2182 VkResult
radv_ResetCommandBuffer(
2183 VkCommandBuffer commandBuffer
,
2184 VkCommandBufferResetFlags flags
)
2186 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2187 return radv_reset_cmd_buffer(cmd_buffer
);
2190 static void emit_gfx_buffer_state(struct radv_cmd_buffer
*cmd_buffer
)
2192 struct radv_device
*device
= cmd_buffer
->device
;
2193 if (device
->gfx_init
) {
2194 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2195 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, device
->gfx_init
, 8);
2196 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2197 radeon_emit(cmd_buffer
->cs
, va
);
2198 radeon_emit(cmd_buffer
->cs
, va
>> 32);
2199 radeon_emit(cmd_buffer
->cs
, device
->gfx_init_size_dw
& 0xffff);
2201 si_init_config(cmd_buffer
);
2204 VkResult
radv_BeginCommandBuffer(
2205 VkCommandBuffer commandBuffer
,
2206 const VkCommandBufferBeginInfo
*pBeginInfo
)
2208 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2211 result
= radv_reset_cmd_buffer(cmd_buffer
);
2212 if (result
!= VK_SUCCESS
)
2215 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
2216 cmd_buffer
->state
.last_primitive_reset_en
= -1;
2217 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
2219 /* setup initial configuration into command buffer */
2220 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
2221 switch (cmd_buffer
->queue_family_index
) {
2222 case RADV_QUEUE_GENERAL
:
2223 emit_gfx_buffer_state(cmd_buffer
);
2225 case RADV_QUEUE_COMPUTE
:
2226 si_init_compute(cmd_buffer
);
2228 case RADV_QUEUE_TRANSFER
:
2234 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2235 assert(pBeginInfo
->pInheritanceInfo
);
2236 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
2237 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
2239 struct radv_subpass
*subpass
=
2240 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
2242 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
2243 if (result
!= VK_SUCCESS
)
2246 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
2249 radv_cmd_buffer_trace_emit(cmd_buffer
);
2253 void radv_CmdBindVertexBuffers(
2254 VkCommandBuffer commandBuffer
,
2255 uint32_t firstBinding
,
2256 uint32_t bindingCount
,
2257 const VkBuffer
* pBuffers
,
2258 const VkDeviceSize
* pOffsets
)
2260 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2261 struct radv_vertex_binding
*vb
= cmd_buffer
->state
.vertex_bindings
;
2263 /* We have to defer setting up vertex buffer since we need the buffer
2264 * stride from the pipeline. */
2266 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
2267 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2268 vb
[firstBinding
+ i
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2269 vb
[firstBinding
+ i
].offset
= pOffsets
[i
];
2272 cmd_buffer
->state
.vb_dirty
= true;
2275 void radv_CmdBindIndexBuffer(
2276 VkCommandBuffer commandBuffer
,
2278 VkDeviceSize offset
,
2279 VkIndexType indexType
)
2281 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2282 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2284 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
2285 cmd_buffer
->state
.index_offset
== offset
&&
2286 cmd_buffer
->state
.index_type
== indexType
) {
2287 /* No state changes. */
2291 cmd_buffer
->state
.index_buffer
= index_buffer
;
2292 cmd_buffer
->state
.index_offset
= offset
;
2293 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2294 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
2295 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2297 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2298 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2299 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2300 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, index_buffer
->bo
, 8);
2304 void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2305 struct radv_descriptor_set
*set
,
2308 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2310 cmd_buffer
->state
.descriptors
[idx
] = set
;
2311 cmd_buffer
->state
.descriptors_dirty
|= (1u << idx
);
2315 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2317 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2318 if (set
->descriptors
[j
])
2319 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->descriptors
[j
], 7);
2322 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->bo
, 8);
2325 void radv_CmdBindDescriptorSets(
2326 VkCommandBuffer commandBuffer
,
2327 VkPipelineBindPoint pipelineBindPoint
,
2328 VkPipelineLayout _layout
,
2330 uint32_t descriptorSetCount
,
2331 const VkDescriptorSet
* pDescriptorSets
,
2332 uint32_t dynamicOffsetCount
,
2333 const uint32_t* pDynamicOffsets
)
2335 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2336 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2337 unsigned dyn_idx
= 0;
2339 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2340 unsigned idx
= i
+ firstSet
;
2341 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2342 radv_bind_descriptor_set(cmd_buffer
, set
, idx
);
2344 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2345 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2346 uint32_t *dst
= cmd_buffer
->dynamic_buffers
+ idx
* 4;
2347 assert(dyn_idx
< dynamicOffsetCount
);
2349 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2350 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2352 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2353 dst
[2] = range
->size
;
2354 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2355 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2356 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2357 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2358 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2359 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2360 cmd_buffer
->push_constant_stages
|=
2361 set
->layout
->dynamic_shader_stages
;
2366 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2367 struct radv_descriptor_set
*set
,
2368 struct radv_descriptor_set_layout
*layout
)
2370 set
->size
= layout
->size
;
2371 set
->layout
= layout
;
2373 if (cmd_buffer
->push_descriptors
.capacity
< set
->size
) {
2374 size_t new_size
= MAX2(set
->size
, 1024);
2375 new_size
= MAX2(new_size
, 2 * cmd_buffer
->push_descriptors
.capacity
);
2376 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2378 free(set
->mapped_ptr
);
2379 set
->mapped_ptr
= malloc(new_size
);
2381 if (!set
->mapped_ptr
) {
2382 cmd_buffer
->push_descriptors
.capacity
= 0;
2383 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2387 cmd_buffer
->push_descriptors
.capacity
= new_size
;
2393 void radv_meta_push_descriptor_set(
2394 struct radv_cmd_buffer
* cmd_buffer
,
2395 VkPipelineBindPoint pipelineBindPoint
,
2396 VkPipelineLayout _layout
,
2398 uint32_t descriptorWriteCount
,
2399 const VkWriteDescriptorSet
* pDescriptorWrites
)
2401 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2402 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2406 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2408 push_set
->size
= layout
->set
[set
].layout
->size
;
2409 push_set
->layout
= layout
->set
[set
].layout
;
2411 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2413 (void**) &push_set
->mapped_ptr
))
2416 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2417 push_set
->va
+= bo_offset
;
2419 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2420 radv_descriptor_set_to_handle(push_set
),
2421 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2423 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2424 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2427 void radv_CmdPushDescriptorSetKHR(
2428 VkCommandBuffer commandBuffer
,
2429 VkPipelineBindPoint pipelineBindPoint
,
2430 VkPipelineLayout _layout
,
2432 uint32_t descriptorWriteCount
,
2433 const VkWriteDescriptorSet
* pDescriptorWrites
)
2435 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2436 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2437 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2439 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2441 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2444 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2445 radv_descriptor_set_to_handle(push_set
),
2446 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2448 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2449 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2450 cmd_buffer
->state
.push_descriptors_dirty
= true;
2453 void radv_CmdPushDescriptorSetWithTemplateKHR(
2454 VkCommandBuffer commandBuffer
,
2455 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
2456 VkPipelineLayout _layout
,
2460 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2461 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2462 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2464 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2466 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2469 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2470 descriptorUpdateTemplate
, pData
);
2472 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2473 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2474 cmd_buffer
->state
.push_descriptors_dirty
= true;
2477 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2478 VkPipelineLayout layout
,
2479 VkShaderStageFlags stageFlags
,
2482 const void* pValues
)
2484 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2485 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2486 cmd_buffer
->push_constant_stages
|= stageFlags
;
2489 VkResult
radv_EndCommandBuffer(
2490 VkCommandBuffer commandBuffer
)
2492 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2494 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
2495 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== SI
)
2496 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2497 si_emit_cache_flush(cmd_buffer
);
2500 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
2501 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2503 return cmd_buffer
->record_result
;
2507 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2509 struct radv_shader_variant
*compute_shader
;
2510 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2513 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2516 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2518 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
2519 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
2521 radv_emit_shader_prefetch(cmd_buffer
, compute_shader
);
2523 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2524 cmd_buffer
->cs
, 16);
2526 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
2527 radeon_emit(cmd_buffer
->cs
, va
>> 8);
2528 radeon_emit(cmd_buffer
->cs
, va
>> 40);
2530 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
2531 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc1
);
2532 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc2
);
2535 cmd_buffer
->compute_scratch_size_needed
=
2536 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2537 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2539 /* change these once we have scratch support */
2540 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
2541 S_00B860_WAVES(pipeline
->max_waves
) |
2542 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
2544 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
2545 radeon_emit(cmd_buffer
->cs
,
2546 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
2547 radeon_emit(cmd_buffer
->cs
,
2548 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
2549 radeon_emit(cmd_buffer
->cs
,
2550 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
2552 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2553 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
2556 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
)
2558 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2559 if (cmd_buffer
->state
.descriptors
[i
])
2560 cmd_buffer
->state
.descriptors_dirty
|= (1u << i
);
2564 void radv_CmdBindPipeline(
2565 VkCommandBuffer commandBuffer
,
2566 VkPipelineBindPoint pipelineBindPoint
,
2567 VkPipeline _pipeline
)
2569 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2570 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
2572 switch (pipelineBindPoint
) {
2573 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2574 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
2576 radv_mark_descriptor_sets_dirty(cmd_buffer
);
2578 cmd_buffer
->state
.compute_pipeline
= pipeline
;
2579 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2581 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2582 if (cmd_buffer
->state
.pipeline
== pipeline
)
2584 radv_mark_descriptor_sets_dirty(cmd_buffer
);
2586 cmd_buffer
->state
.pipeline
= pipeline
;
2590 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2591 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
2593 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
2595 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
2596 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
2597 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
2598 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
2600 if (radv_pipeline_has_tess(pipeline
))
2601 cmd_buffer
->tess_rings_needed
= true;
2603 if (radv_pipeline_has_gs(pipeline
)) {
2604 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2605 AC_UD_SCRATCH_RING_OFFSETS
);
2606 if (cmd_buffer
->ring_offsets_idx
== -1)
2607 cmd_buffer
->ring_offsets_idx
= loc
->sgpr_idx
;
2608 else if (loc
->sgpr_idx
!= -1)
2609 assert(loc
->sgpr_idx
== cmd_buffer
->ring_offsets_idx
);
2613 assert(!"invalid bind point");
2618 void radv_CmdSetViewport(
2619 VkCommandBuffer commandBuffer
,
2620 uint32_t firstViewport
,
2621 uint32_t viewportCount
,
2622 const VkViewport
* pViewports
)
2624 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2625 MAYBE_UNUSED
const uint32_t total_count
= firstViewport
+ viewportCount
;
2627 assert(firstViewport
< MAX_VIEWPORTS
);
2628 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
2630 memcpy(cmd_buffer
->state
.dynamic
.viewport
.viewports
+ firstViewport
,
2631 pViewports
, viewportCount
* sizeof(*pViewports
));
2633 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2636 void radv_CmdSetScissor(
2637 VkCommandBuffer commandBuffer
,
2638 uint32_t firstScissor
,
2639 uint32_t scissorCount
,
2640 const VkRect2D
* pScissors
)
2642 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2643 MAYBE_UNUSED
const uint32_t total_count
= firstScissor
+ scissorCount
;
2645 assert(firstScissor
< MAX_SCISSORS
);
2646 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
2648 memcpy(cmd_buffer
->state
.dynamic
.scissor
.scissors
+ firstScissor
,
2649 pScissors
, scissorCount
* sizeof(*pScissors
));
2650 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2653 void radv_CmdSetLineWidth(
2654 VkCommandBuffer commandBuffer
,
2657 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2658 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
2659 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2662 void radv_CmdSetDepthBias(
2663 VkCommandBuffer commandBuffer
,
2664 float depthBiasConstantFactor
,
2665 float depthBiasClamp
,
2666 float depthBiasSlopeFactor
)
2668 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2670 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
2671 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
2672 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
2674 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2677 void radv_CmdSetBlendConstants(
2678 VkCommandBuffer commandBuffer
,
2679 const float blendConstants
[4])
2681 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2683 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
2684 blendConstants
, sizeof(float) * 4);
2686 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2689 void radv_CmdSetDepthBounds(
2690 VkCommandBuffer commandBuffer
,
2691 float minDepthBounds
,
2692 float maxDepthBounds
)
2694 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2696 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
2697 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
2699 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2702 void radv_CmdSetStencilCompareMask(
2703 VkCommandBuffer commandBuffer
,
2704 VkStencilFaceFlags faceMask
,
2705 uint32_t compareMask
)
2707 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2709 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2710 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2711 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2712 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2714 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2717 void radv_CmdSetStencilWriteMask(
2718 VkCommandBuffer commandBuffer
,
2719 VkStencilFaceFlags faceMask
,
2722 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2724 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2725 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2726 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2727 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2729 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2732 void radv_CmdSetStencilReference(
2733 VkCommandBuffer commandBuffer
,
2734 VkStencilFaceFlags faceMask
,
2737 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2739 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2740 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
2741 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2742 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
2744 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2747 void radv_CmdExecuteCommands(
2748 VkCommandBuffer commandBuffer
,
2749 uint32_t commandBufferCount
,
2750 const VkCommandBuffer
* pCmdBuffers
)
2752 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
2754 assert(commandBufferCount
> 0);
2756 /* Emit pending flushes on primary prior to executing secondary */
2757 si_emit_cache_flush(primary
);
2759 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2760 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2762 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
2763 secondary
->scratch_size_needed
);
2764 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
2765 secondary
->compute_scratch_size_needed
);
2767 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
2768 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
2769 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
2770 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
2771 if (secondary
->tess_rings_needed
)
2772 primary
->tess_rings_needed
= true;
2773 if (secondary
->sample_positions_needed
)
2774 primary
->sample_positions_needed
= true;
2776 if (secondary
->ring_offsets_idx
!= -1) {
2777 if (primary
->ring_offsets_idx
== -1)
2778 primary
->ring_offsets_idx
= secondary
->ring_offsets_idx
;
2780 assert(secondary
->ring_offsets_idx
== primary
->ring_offsets_idx
);
2782 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
2785 /* When the secondary command buffer is compute only we don't
2786 * need to re-emit the current graphics pipeline.
2788 if (secondary
->state
.emitted_pipeline
) {
2789 primary
->state
.emitted_pipeline
=
2790 secondary
->state
.emitted_pipeline
;
2793 /* When the secondary command buffer is graphics only we don't
2794 * need to re-emit the current compute pipeline.
2796 if (secondary
->state
.emitted_compute_pipeline
) {
2797 primary
->state
.emitted_compute_pipeline
=
2798 secondary
->state
.emitted_compute_pipeline
;
2801 /* Only re-emit the draw packets when needed. */
2802 if (secondary
->state
.last_primitive_reset_en
!= -1) {
2803 primary
->state
.last_primitive_reset_en
=
2804 secondary
->state
.last_primitive_reset_en
;
2807 if (secondary
->state
.last_primitive_reset_index
) {
2808 primary
->state
.last_primitive_reset_index
=
2809 secondary
->state
.last_primitive_reset_index
;
2812 if (secondary
->state
.last_ia_multi_vgt_param
) {
2813 primary
->state
.last_ia_multi_vgt_param
=
2814 secondary
->state
.last_ia_multi_vgt_param
;
2818 /* After executing commands from secondary buffers we have to dirty
2821 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
2822 RADV_CMD_DIRTY_INDEX_BUFFER
|
2823 RADV_CMD_DIRTY_DYNAMIC_ALL
;
2824 radv_mark_descriptor_sets_dirty(primary
);
2827 VkResult
radv_CreateCommandPool(
2829 const VkCommandPoolCreateInfo
* pCreateInfo
,
2830 const VkAllocationCallbacks
* pAllocator
,
2831 VkCommandPool
* pCmdPool
)
2833 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2834 struct radv_cmd_pool
*pool
;
2836 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2837 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2839 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2842 pool
->alloc
= *pAllocator
;
2844 pool
->alloc
= device
->alloc
;
2846 list_inithead(&pool
->cmd_buffers
);
2847 list_inithead(&pool
->free_cmd_buffers
);
2849 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2851 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
2857 void radv_DestroyCommandPool(
2859 VkCommandPool commandPool
,
2860 const VkAllocationCallbacks
* pAllocator
)
2862 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2863 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2868 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2869 &pool
->cmd_buffers
, pool_link
) {
2870 radv_cmd_buffer_destroy(cmd_buffer
);
2873 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2874 &pool
->free_cmd_buffers
, pool_link
) {
2875 radv_cmd_buffer_destroy(cmd_buffer
);
2878 vk_free2(&device
->alloc
, pAllocator
, pool
);
2881 VkResult
radv_ResetCommandPool(
2883 VkCommandPool commandPool
,
2884 VkCommandPoolResetFlags flags
)
2886 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2889 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
2890 &pool
->cmd_buffers
, pool_link
) {
2891 result
= radv_reset_cmd_buffer(cmd_buffer
);
2892 if (result
!= VK_SUCCESS
)
2899 void radv_TrimCommandPoolKHR(
2901 VkCommandPool commandPool
,
2902 VkCommandPoolTrimFlagsKHR flags
)
2904 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2909 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2910 &pool
->free_cmd_buffers
, pool_link
) {
2911 radv_cmd_buffer_destroy(cmd_buffer
);
2915 void radv_CmdBeginRenderPass(
2916 VkCommandBuffer commandBuffer
,
2917 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2918 VkSubpassContents contents
)
2920 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2921 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2922 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2924 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2925 cmd_buffer
->cs
, 2048);
2926 MAYBE_UNUSED VkResult result
;
2928 cmd_buffer
->state
.framebuffer
= framebuffer
;
2929 cmd_buffer
->state
.pass
= pass
;
2930 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2932 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
2933 if (result
!= VK_SUCCESS
)
2936 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
2937 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2939 radv_cmd_buffer_clear_subpass(cmd_buffer
);
2942 void radv_CmdNextSubpass(
2943 VkCommandBuffer commandBuffer
,
2944 VkSubpassContents contents
)
2946 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2948 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
2950 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2953 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
2954 radv_cmd_buffer_clear_subpass(cmd_buffer
);
2957 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
2959 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2960 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2961 if (!pipeline
->shaders
[stage
])
2963 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
2964 if (loc
->sgpr_idx
== -1)
2966 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, cmd_buffer
->device
->physical_device
->rad_info
.chip_class
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
2967 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
2970 if (pipeline
->gs_copy_shader
) {
2971 struct ac_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
2972 if (loc
->sgpr_idx
!= -1) {
2973 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2974 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
2980 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
2981 uint32_t vertex_count
)
2983 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
2984 radeon_emit(cmd_buffer
->cs
, vertex_count
);
2985 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
2986 S_0287F0_USE_OPAQUE(0));
2990 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
2992 uint32_t index_count
)
2994 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, false));
2995 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
2996 radeon_emit(cmd_buffer
->cs
, index_va
);
2997 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
2998 radeon_emit(cmd_buffer
->cs
, index_count
);
2999 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
3003 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3005 uint32_t draw_count
,
3009 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3010 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
3011 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
3012 bool draw_id_enable
= radv_get_vertex_shader(cmd_buffer
->state
.pipeline
)->info
.info
.vs
.needs_draw_id
;
3013 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
3016 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
3017 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
3018 PKT3_DRAW_INDIRECT
, 3, false));
3020 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3021 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3022 radeon_emit(cs
, di_src_sel
);
3024 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
3025 PKT3_DRAW_INDIRECT_MULTI
,
3028 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3029 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3030 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
3031 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
3032 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
3033 radeon_emit(cs
, draw_count
); /* count */
3034 radeon_emit(cs
, count_va
); /* count_addr */
3035 radeon_emit(cs
, count_va
>> 32);
3036 radeon_emit(cs
, stride
); /* stride */
3037 radeon_emit(cs
, di_src_sel
);
3041 struct radv_draw_info
{
3043 * Number of vertices.
3048 * Index of the first vertex.
3050 int32_t vertex_offset
;
3053 * First instance id.
3055 uint32_t first_instance
;
3058 * Number of instances.
3060 uint32_t instance_count
;
3063 * First index (indexed draws only).
3065 uint32_t first_index
;
3068 * Whether it's an indexed draw.
3073 * Indirect draw parameters resource.
3075 struct radv_buffer
*indirect
;
3076 uint64_t indirect_offset
;
3080 * Draw count parameters resource.
3082 struct radv_buffer
*count_buffer
;
3083 uint64_t count_buffer_offset
;
3087 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
3088 const struct radv_draw_info
*info
)
3090 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3091 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3092 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3094 if (info
->indirect
) {
3095 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3096 uint64_t count_va
= 0;
3098 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3100 ws
->cs_add_buffer(cs
, info
->indirect
->bo
, 8);
3102 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
3104 radeon_emit(cs
, va
);
3105 radeon_emit(cs
, va
>> 32);
3107 if (info
->count_buffer
) {
3108 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
3109 count_va
+= info
->count_buffer
->offset
+
3110 info
->count_buffer_offset
;
3112 ws
->cs_add_buffer(cs
, info
->count_buffer
->bo
, 8);
3115 if (!state
->subpass
->view_mask
) {
3116 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3123 for_each_bit(i
, state
->subpass
->view_mask
) {
3124 radv_emit_view_index(cmd_buffer
, i
);
3126 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3134 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
3135 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
3136 state
->pipeline
->graphics
.vtx_emit_num
);
3137 radeon_emit(cs
, info
->vertex_offset
);
3138 radeon_emit(cs
, info
->first_instance
);
3139 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
3142 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, state
->predicating
));
3143 radeon_emit(cs
, info
->instance_count
);
3145 if (info
->indexed
) {
3146 int index_size
= state
->index_type
? 4 : 2;
3149 index_va
= state
->index_va
;
3150 index_va
+= info
->first_index
* index_size
;
3152 if (!state
->subpass
->view_mask
) {
3153 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3158 for_each_bit(i
, state
->subpass
->view_mask
) {
3159 radv_emit_view_index(cmd_buffer
, i
);
3161 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3167 if (!state
->subpass
->view_mask
) {
3168 radv_cs_emit_draw_packet(cmd_buffer
, info
->count
);
3171 for_each_bit(i
, state
->subpass
->view_mask
) {
3172 radv_emit_view_index(cmd_buffer
, i
);
3174 radv_cs_emit_draw_packet(cmd_buffer
,
3183 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
3184 const struct radv_draw_info
*info
)
3186 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
3187 radv_emit_graphics_pipeline(cmd_buffer
);
3189 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
3190 radv_emit_framebuffer_state(cmd_buffer
);
3192 if (info
->indexed
) {
3193 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
3194 radv_emit_index_buffer(cmd_buffer
);
3196 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3197 * so the state must be re-emitted before the next indexed
3200 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
3201 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3204 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
3206 radv_emit_draw_registers(cmd_buffer
, info
->indexed
,
3207 info
->instance_count
> 1, info
->indirect
,
3208 info
->indirect
? 0 : info
->count
);
3212 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
3213 const struct radv_draw_info
*info
)
3215 bool pipeline_is_dirty
=
3216 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
3217 cmd_buffer
->state
.pipeline
&&
3218 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
3220 MAYBE_UNUSED
unsigned cdw_max
=
3221 radeon_check_space(cmd_buffer
->device
->ws
,
3222 cmd_buffer
->cs
, 4096);
3224 /* Use optimal packet order based on whether we need to sync the
3227 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3228 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3229 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
3230 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
3231 /* If we have to wait for idle, set all states first, so that
3232 * all SET packets are processed in parallel with previous draw
3233 * calls. Then upload descriptors, set shader pointers, and
3234 * draw, and prefetch at the end. This ensures that the time
3235 * the CUs are idle is very short. (there are only SET_SH
3236 * packets between the wait and the draw)
3238 radv_emit_all_graphics_states(cmd_buffer
, info
);
3239 si_emit_cache_flush(cmd_buffer
);
3240 /* <-- CUs are idle here --> */
3242 if (!radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
))
3245 radv_emit_draw_packets(cmd_buffer
, info
);
3246 /* <-- CUs are busy here --> */
3248 /* Start prefetches after the draw has been started. Both will
3249 * run in parallel, but starting the draw first is more
3252 if (pipeline_is_dirty
) {
3253 radv_emit_shaders_prefetch(cmd_buffer
,
3254 cmd_buffer
->state
.pipeline
);
3257 /* If we don't wait for idle, start prefetches first, then set
3258 * states, and draw at the end.
3260 si_emit_cache_flush(cmd_buffer
);
3262 if (pipeline_is_dirty
) {
3263 radv_emit_shaders_prefetch(cmd_buffer
,
3264 cmd_buffer
->state
.pipeline
);
3267 if (!radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
))
3270 radv_emit_all_graphics_states(cmd_buffer
, info
);
3271 radv_emit_draw_packets(cmd_buffer
, info
);
3274 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3275 radv_cmd_buffer_after_draw(cmd_buffer
);
3279 VkCommandBuffer commandBuffer
,
3280 uint32_t vertexCount
,
3281 uint32_t instanceCount
,
3282 uint32_t firstVertex
,
3283 uint32_t firstInstance
)
3285 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3286 struct radv_draw_info info
= {};
3288 info
.count
= vertexCount
;
3289 info
.instance_count
= instanceCount
;
3290 info
.first_instance
= firstInstance
;
3291 info
.vertex_offset
= firstVertex
;
3293 radv_draw(cmd_buffer
, &info
);
3296 void radv_CmdDrawIndexed(
3297 VkCommandBuffer commandBuffer
,
3298 uint32_t indexCount
,
3299 uint32_t instanceCount
,
3300 uint32_t firstIndex
,
3301 int32_t vertexOffset
,
3302 uint32_t firstInstance
)
3304 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3305 struct radv_draw_info info
= {};
3307 info
.indexed
= true;
3308 info
.count
= indexCount
;
3309 info
.instance_count
= instanceCount
;
3310 info
.first_index
= firstIndex
;
3311 info
.vertex_offset
= vertexOffset
;
3312 info
.first_instance
= firstInstance
;
3314 radv_draw(cmd_buffer
, &info
);
3317 void radv_CmdDrawIndirect(
3318 VkCommandBuffer commandBuffer
,
3320 VkDeviceSize offset
,
3324 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3325 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3326 struct radv_draw_info info
= {};
3328 info
.count
= drawCount
;
3329 info
.indirect
= buffer
;
3330 info
.indirect_offset
= offset
;
3331 info
.stride
= stride
;
3333 radv_draw(cmd_buffer
, &info
);
3336 void radv_CmdDrawIndexedIndirect(
3337 VkCommandBuffer commandBuffer
,
3339 VkDeviceSize offset
,
3343 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3344 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3345 struct radv_draw_info info
= {};
3347 info
.indexed
= true;
3348 info
.count
= drawCount
;
3349 info
.indirect
= buffer
;
3350 info
.indirect_offset
= offset
;
3351 info
.stride
= stride
;
3353 radv_draw(cmd_buffer
, &info
);
3356 void radv_CmdDrawIndirectCountAMD(
3357 VkCommandBuffer commandBuffer
,
3359 VkDeviceSize offset
,
3360 VkBuffer _countBuffer
,
3361 VkDeviceSize countBufferOffset
,
3362 uint32_t maxDrawCount
,
3365 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3366 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3367 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3368 struct radv_draw_info info
= {};
3370 info
.count
= maxDrawCount
;
3371 info
.indirect
= buffer
;
3372 info
.indirect_offset
= offset
;
3373 info
.count_buffer
= count_buffer
;
3374 info
.count_buffer_offset
= countBufferOffset
;
3375 info
.stride
= stride
;
3377 radv_draw(cmd_buffer
, &info
);
3380 void radv_CmdDrawIndexedIndirectCountAMD(
3381 VkCommandBuffer commandBuffer
,
3383 VkDeviceSize offset
,
3384 VkBuffer _countBuffer
,
3385 VkDeviceSize countBufferOffset
,
3386 uint32_t maxDrawCount
,
3389 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3390 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3391 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3392 struct radv_draw_info info
= {};
3394 info
.indexed
= true;
3395 info
.count
= maxDrawCount
;
3396 info
.indirect
= buffer
;
3397 info
.indirect_offset
= offset
;
3398 info
.count_buffer
= count_buffer
;
3399 info
.count_buffer_offset
= countBufferOffset
;
3400 info
.stride
= stride
;
3402 radv_draw(cmd_buffer
, &info
);
3405 struct radv_dispatch_info
{
3407 * Determine the layout of the grid (in block units) to be used.
3412 * Whether it's an unaligned compute dispatch.
3417 * Indirect compute parameters resource.
3419 struct radv_buffer
*indirect
;
3420 uint64_t indirect_offset
;
3424 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
3425 const struct radv_dispatch_info
*info
)
3427 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3428 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3429 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3430 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3431 struct ac_userdata_info
*loc
;
3432 unsigned dispatch_initiator
;
3435 grid_used
= compute_shader
->info
.info
.cs
.grid_components_used
;
3437 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
3438 AC_UD_CS_GRID_SIZE
);
3440 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
3442 dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1) |
3443 S_00B800_FORCE_START_AT_000(1);
3445 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3446 /* If the KMD allows it (there is a KMD hw register for it),
3447 * allow launching waves out-of-order.
3449 dispatch_initiator
|= S_00B800_ORDER_MODE(1);
3452 if (info
->indirect
) {
3453 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3455 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3457 ws
->cs_add_buffer(cs
, info
->indirect
->bo
, 8);
3459 if (loc
->sgpr_idx
!= -1) {
3460 for (unsigned i
= 0; i
< grid_used
; ++i
) {
3461 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3462 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
3463 COPY_DATA_DST_SEL(COPY_DATA_REG
));
3464 radeon_emit(cs
, (va
+ 4 * i
));
3465 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
3466 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
3467 + loc
->sgpr_idx
* 4) >> 2) + i
);
3472 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
3473 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, 0) |
3474 PKT3_SHADER_TYPE_S(1));
3475 radeon_emit(cs
, va
);
3476 radeon_emit(cs
, va
>> 32);
3477 radeon_emit(cs
, dispatch_initiator
);
3479 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
3480 PKT3_SHADER_TYPE_S(1));
3482 radeon_emit(cs
, va
);
3483 radeon_emit(cs
, va
>> 32);
3485 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, 0) |
3486 PKT3_SHADER_TYPE_S(1));
3488 radeon_emit(cs
, dispatch_initiator
);
3491 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
3493 if (info
->unaligned
) {
3494 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
3495 unsigned remainder
[3];
3497 /* If aligned, these should be an entire block size,
3500 remainder
[0] = blocks
[0] + cs_block_size
[0] -
3501 align_u32_npot(blocks
[0], cs_block_size
[0]);
3502 remainder
[1] = blocks
[1] + cs_block_size
[1] -
3503 align_u32_npot(blocks
[1], cs_block_size
[1]);
3504 remainder
[2] = blocks
[2] + cs_block_size
[2] -
3505 align_u32_npot(blocks
[2], cs_block_size
[2]);
3507 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
3508 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
3509 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
3511 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3513 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
3514 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
3516 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
3517 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
3519 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
3520 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
3522 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
3525 if (loc
->sgpr_idx
!= -1) {
3526 assert(!loc
->indirect
);
3527 assert(loc
->num_sgprs
== grid_used
);
3529 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
3530 loc
->sgpr_idx
* 4, grid_used
);
3531 radeon_emit(cs
, blocks
[0]);
3533 radeon_emit(cs
, blocks
[1]);
3535 radeon_emit(cs
, blocks
[2]);
3538 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
3539 PKT3_SHADER_TYPE_S(1));
3540 radeon_emit(cs
, blocks
[0]);
3541 radeon_emit(cs
, blocks
[1]);
3542 radeon_emit(cs
, blocks
[2]);
3543 radeon_emit(cs
, dispatch_initiator
);
3546 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3550 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
3551 const struct radv_dispatch_info
*info
)
3553 radv_emit_compute_pipeline(cmd_buffer
);
3555 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
3556 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
3557 VK_SHADER_STAGE_COMPUTE_BIT
);
3559 si_emit_cache_flush(cmd_buffer
);
3561 radv_emit_dispatch_packets(cmd_buffer
, info
);
3563 radv_cmd_buffer_after_draw(cmd_buffer
);
3566 void radv_CmdDispatch(
3567 VkCommandBuffer commandBuffer
,
3572 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3573 struct radv_dispatch_info info
= {};
3579 radv_dispatch(cmd_buffer
, &info
);
3582 void radv_CmdDispatchIndirect(
3583 VkCommandBuffer commandBuffer
,
3585 VkDeviceSize offset
)
3587 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3588 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3589 struct radv_dispatch_info info
= {};
3591 info
.indirect
= buffer
;
3592 info
.indirect_offset
= offset
;
3594 radv_dispatch(cmd_buffer
, &info
);
3597 void radv_unaligned_dispatch(
3598 struct radv_cmd_buffer
*cmd_buffer
,
3603 struct radv_dispatch_info info
= {};
3610 radv_dispatch(cmd_buffer
, &info
);
3613 void radv_CmdEndRenderPass(
3614 VkCommandBuffer commandBuffer
)
3616 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3618 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
3620 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3622 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
3623 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
3624 radv_handle_subpass_image_transition(cmd_buffer
,
3625 (VkAttachmentReference
){i
, layout
});
3628 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3630 cmd_buffer
->state
.pass
= NULL
;
3631 cmd_buffer
->state
.subpass
= NULL
;
3632 cmd_buffer
->state
.attachments
= NULL
;
3633 cmd_buffer
->state
.framebuffer
= NULL
;
3637 * For HTILE we have the following interesting clear words:
3638 * 0x0000030f: Uncompressed.
3639 * 0xfffffff0: Clear depth to 1.0
3640 * 0x00000000: Clear depth to 0.0
3642 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
3643 struct radv_image
*image
,
3644 const VkImageSubresourceRange
*range
,
3645 uint32_t clear_word
)
3647 assert(range
->baseMipLevel
== 0);
3648 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
3649 unsigned layer_count
= radv_get_layerCount(image
, range
);
3650 uint64_t size
= image
->surface
.htile_slice_size
* layer_count
;
3651 uint64_t offset
= image
->offset
+ image
->htile_offset
+
3652 image
->surface
.htile_slice_size
* range
->baseArrayLayer
;
3653 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3655 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3656 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3658 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
, offset
,
3661 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3664 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3665 struct radv_image
*image
,
3666 VkImageLayout src_layout
,
3667 VkImageLayout dst_layout
,
3668 unsigned src_queue_mask
,
3669 unsigned dst_queue_mask
,
3670 const VkImageSubresourceRange
*range
,
3671 VkImageAspectFlags pending_clears
)
3673 if (dst_layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
&&
3674 (pending_clears
& vk_format_aspects(image
->vk_format
)) == vk_format_aspects(image
->vk_format
) &&
3675 cmd_buffer
->state
.render_area
.offset
.x
== 0 && cmd_buffer
->state
.render_area
.offset
.y
== 0 &&
3676 cmd_buffer
->state
.render_area
.extent
.width
== image
->info
.width
&&
3677 cmd_buffer
->state
.render_area
.extent
.height
== image
->info
.height
) {
3678 /* The clear will initialize htile. */
3680 } else if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
3681 radv_layout_has_htile(image
, dst_layout
, dst_queue_mask
)) {
3682 /* TODO: merge with the clear if applicable */
3683 radv_initialize_htile(cmd_buffer
, image
, range
, 0);
3684 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3685 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3686 radv_initialize_htile(cmd_buffer
, image
, range
, 0xffffffff);
3687 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3688 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3689 VkImageSubresourceRange local_range
= *range
;
3690 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
3691 local_range
.baseMipLevel
= 0;
3692 local_range
.levelCount
= 1;
3694 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3695 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3697 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
3699 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3700 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3704 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
3705 struct radv_image
*image
, uint32_t value
)
3707 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3709 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3710 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3712 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
,
3713 image
->offset
+ image
->cmask
.offset
,
3714 image
->cmask
.size
, value
);
3716 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3719 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3720 struct radv_image
*image
,
3721 VkImageLayout src_layout
,
3722 VkImageLayout dst_layout
,
3723 unsigned src_queue_mask
,
3724 unsigned dst_queue_mask
,
3725 const VkImageSubresourceRange
*range
)
3727 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3728 if (image
->fmask
.size
)
3729 radv_initialise_cmask(cmd_buffer
, image
, 0xccccccccu
);
3731 radv_initialise_cmask(cmd_buffer
, image
, 0xffffffffu
);
3732 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3733 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3734 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3738 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
3739 struct radv_image
*image
, uint32_t value
)
3741 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3743 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3744 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3746 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
,
3747 image
->offset
+ image
->dcc_offset
,
3748 image
->surface
.dcc_size
, value
);
3750 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3751 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3754 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3755 struct radv_image
*image
,
3756 VkImageLayout src_layout
,
3757 VkImageLayout dst_layout
,
3758 unsigned src_queue_mask
,
3759 unsigned dst_queue_mask
,
3760 const VkImageSubresourceRange
*range
)
3762 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3763 radv_initialize_dcc(cmd_buffer
, image
, 0x20202020u
);
3764 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3765 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3766 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3770 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3771 struct radv_image
*image
,
3772 VkImageLayout src_layout
,
3773 VkImageLayout dst_layout
,
3774 uint32_t src_family
,
3775 uint32_t dst_family
,
3776 const VkImageSubresourceRange
*range
,
3777 VkImageAspectFlags pending_clears
)
3779 if (image
->exclusive
&& src_family
!= dst_family
) {
3780 /* This is an acquire or a release operation and there will be
3781 * a corresponding release/acquire. Do the transition in the
3782 * most flexible queue. */
3784 assert(src_family
== cmd_buffer
->queue_family_index
||
3785 dst_family
== cmd_buffer
->queue_family_index
);
3787 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
3790 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
3791 (src_family
== RADV_QUEUE_GENERAL
||
3792 dst_family
== RADV_QUEUE_GENERAL
))
3796 unsigned src_queue_mask
= radv_image_queue_family_mask(image
, src_family
, cmd_buffer
->queue_family_index
);
3797 unsigned dst_queue_mask
= radv_image_queue_family_mask(image
, dst_family
, cmd_buffer
->queue_family_index
);
3799 if (image
->surface
.htile_size
)
3800 radv_handle_depth_image_transition(cmd_buffer
, image
, src_layout
,
3801 dst_layout
, src_queue_mask
,
3802 dst_queue_mask
, range
,
3805 if (image
->cmask
.size
|| image
->fmask
.size
)
3806 radv_handle_cmask_image_transition(cmd_buffer
, image
, src_layout
,
3807 dst_layout
, src_queue_mask
,
3808 dst_queue_mask
, range
);
3810 if (image
->surface
.dcc_size
)
3811 radv_handle_dcc_image_transition(cmd_buffer
, image
, src_layout
,
3812 dst_layout
, src_queue_mask
,
3813 dst_queue_mask
, range
);
3816 void radv_CmdPipelineBarrier(
3817 VkCommandBuffer commandBuffer
,
3818 VkPipelineStageFlags srcStageMask
,
3819 VkPipelineStageFlags destStageMask
,
3821 uint32_t memoryBarrierCount
,
3822 const VkMemoryBarrier
* pMemoryBarriers
,
3823 uint32_t bufferMemoryBarrierCount
,
3824 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3825 uint32_t imageMemoryBarrierCount
,
3826 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3828 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3829 enum radv_cmd_flush_bits src_flush_bits
= 0;
3830 enum radv_cmd_flush_bits dst_flush_bits
= 0;
3832 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3833 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
);
3834 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
3838 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3839 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
);
3840 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
3844 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3845 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3846 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
);
3847 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
3851 radv_stage_flush(cmd_buffer
, srcStageMask
);
3852 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
3854 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3855 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3856 radv_handle_image_transition(cmd_buffer
, image
,
3857 pImageMemoryBarriers
[i
].oldLayout
,
3858 pImageMemoryBarriers
[i
].newLayout
,
3859 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
3860 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
3861 &pImageMemoryBarriers
[i
].subresourceRange
,
3865 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
3869 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
3870 struct radv_event
*event
,
3871 VkPipelineStageFlags stageMask
,
3874 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3875 uint64_t va
= radv_buffer_get_va(event
->bo
);
3877 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
3879 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 18);
3881 /* TODO: this is overkill. Probably should figure something out from
3882 * the stage mask. */
3884 si_cs_emit_write_event_eop(cs
,
3885 cmd_buffer
->state
.predicating
,
3886 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
3888 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
3891 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3894 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
3896 VkPipelineStageFlags stageMask
)
3898 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3899 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3901 write_event(cmd_buffer
, event
, stageMask
, 1);
3904 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
3906 VkPipelineStageFlags stageMask
)
3908 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3909 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3911 write_event(cmd_buffer
, event
, stageMask
, 0);
3914 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3915 uint32_t eventCount
,
3916 const VkEvent
* pEvents
,
3917 VkPipelineStageFlags srcStageMask
,
3918 VkPipelineStageFlags dstStageMask
,
3919 uint32_t memoryBarrierCount
,
3920 const VkMemoryBarrier
* pMemoryBarriers
,
3921 uint32_t bufferMemoryBarrierCount
,
3922 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3923 uint32_t imageMemoryBarrierCount
,
3924 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3926 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3927 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3929 for (unsigned i
= 0; i
< eventCount
; ++i
) {
3930 RADV_FROM_HANDLE(radv_event
, event
, pEvents
[i
]);
3931 uint64_t va
= radv_buffer_get_va(event
->bo
);
3933 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
3935 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
3937 si_emit_wait_fence(cs
, false, va
, 1, 0xffffffff);
3938 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3942 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3943 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3945 radv_handle_image_transition(cmd_buffer
, image
,
3946 pImageMemoryBarriers
[i
].oldLayout
,
3947 pImageMemoryBarriers
[i
].newLayout
,
3948 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
3949 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
3950 &pImageMemoryBarriers
[i
].subresourceRange
,
3954 /* TODO: figure out how to do memory barriers without waiting */
3955 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
|
3956 RADV_CMD_FLAG_INV_GLOBAL_L2
|
3957 RADV_CMD_FLAG_INV_VMEM_L1
|
3958 RADV_CMD_FLAG_INV_SMEM_L1
;