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radv: Add shader prefetch.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 uint32_t src_family,
42 uint32_t dst_family,
43 const VkImageSubresourceRange *range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static void
191 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
192 {
193 list_del(&cmd_buffer->pool_link);
194
195 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
196 &cmd_buffer->upload.list, list) {
197 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
198 list_del(&up->list);
199 free(up);
200 }
201
202 if (cmd_buffer->upload.upload_bo)
203 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
204 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
205 free(cmd_buffer->push_descriptors.set.mapped_ptr);
206 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
207 }
208
209 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
210 {
211
212 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
213
214 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
215 &cmd_buffer->upload.list, list) {
216 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
217 list_del(&up->list);
218 free(up);
219 }
220
221 cmd_buffer->scratch_size_needed = 0;
222 cmd_buffer->compute_scratch_size_needed = 0;
223 cmd_buffer->esgs_ring_size_needed = 0;
224 cmd_buffer->gsvs_ring_size_needed = 0;
225 cmd_buffer->tess_rings_needed = false;
226 cmd_buffer->sample_positions_needed = false;
227
228 if (cmd_buffer->upload.upload_bo)
229 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
230 cmd_buffer->upload.upload_bo, 8);
231 cmd_buffer->upload.offset = 0;
232
233 cmd_buffer->record_fail = false;
234
235 cmd_buffer->ring_offsets_idx = -1;
236 }
237
238 static bool
239 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
240 uint64_t min_needed)
241 {
242 uint64_t new_size;
243 struct radeon_winsys_bo *bo;
244 struct radv_cmd_buffer_upload *upload;
245 struct radv_device *device = cmd_buffer->device;
246
247 new_size = MAX2(min_needed, 16 * 1024);
248 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
249
250 bo = device->ws->buffer_create(device->ws,
251 new_size, 4096,
252 RADEON_DOMAIN_GTT,
253 RADEON_FLAG_CPU_ACCESS);
254
255 if (!bo) {
256 cmd_buffer->record_fail = true;
257 return false;
258 }
259
260 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
261 if (cmd_buffer->upload.upload_bo) {
262 upload = malloc(sizeof(*upload));
263
264 if (!upload) {
265 cmd_buffer->record_fail = true;
266 device->ws->buffer_destroy(bo);
267 return false;
268 }
269
270 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
271 list_add(&upload->list, &cmd_buffer->upload.list);
272 }
273
274 cmd_buffer->upload.upload_bo = bo;
275 cmd_buffer->upload.size = new_size;
276 cmd_buffer->upload.offset = 0;
277 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
278
279 if (!cmd_buffer->upload.map) {
280 cmd_buffer->record_fail = true;
281 return false;
282 }
283
284 return true;
285 }
286
287 bool
288 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
289 unsigned size,
290 unsigned alignment,
291 unsigned *out_offset,
292 void **ptr)
293 {
294 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
295 if (offset + size > cmd_buffer->upload.size) {
296 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
297 return false;
298 offset = 0;
299 }
300
301 *out_offset = offset;
302 *ptr = cmd_buffer->upload.map + offset;
303
304 cmd_buffer->upload.offset = offset + size;
305 return true;
306 }
307
308 bool
309 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
310 unsigned size, unsigned alignment,
311 const void *data, unsigned *out_offset)
312 {
313 uint8_t *ptr;
314
315 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
316 out_offset, (void **)&ptr))
317 return false;
318
319 if (ptr)
320 memcpy(ptr, data, size);
321
322 return true;
323 }
324
325 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
326 {
327 struct radv_device *device = cmd_buffer->device;
328 struct radeon_winsys_cs *cs = cmd_buffer->cs;
329 uint64_t va;
330
331 if (!device->trace_bo)
332 return;
333
334 va = device->ws->buffer_get_va(device->trace_bo);
335
336 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
337
338 ++cmd_buffer->state.trace_id;
339 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
340 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
341 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
342 S_370_WR_CONFIRM(1) |
343 S_370_ENGINE_SEL(V_370_ME));
344 radeon_emit(cs, va);
345 radeon_emit(cs, va >> 32);
346 radeon_emit(cs, cmd_buffer->state.trace_id);
347 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
348 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
349 }
350
351 static void
352 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
353 struct radv_pipeline *pipeline)
354 {
355 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
356 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
357 8);
358 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
359 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
360 }
361
362 static void
363 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
364 struct radv_pipeline *pipeline)
365 {
366 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
367 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
369
370 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
371 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
372 }
373
374 /* 12.4 fixed-point */
375 static unsigned radv_pack_float_12p4(float x)
376 {
377 return x <= 0 ? 0 :
378 x >= 4096 ? 0xffff : x * 16;
379 }
380
381 static uint32_t
382 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
383 {
384 switch (stage) {
385 case MESA_SHADER_FRAGMENT:
386 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
387 case MESA_SHADER_VERTEX:
388 if (has_tess)
389 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
390 else
391 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
392 case MESA_SHADER_GEOMETRY:
393 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
394 case MESA_SHADER_COMPUTE:
395 return R_00B900_COMPUTE_USER_DATA_0;
396 case MESA_SHADER_TESS_CTRL:
397 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
398 case MESA_SHADER_TESS_EVAL:
399 if (has_gs)
400 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
401 else
402 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
403 default:
404 unreachable("unknown shader");
405 }
406 }
407
408 static struct ac_userdata_info *
409 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
410 gl_shader_stage stage,
411 int idx)
412 {
413 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
414 }
415
416 static void
417 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
418 struct radv_pipeline *pipeline,
419 gl_shader_stage stage,
420 int idx, uint64_t va)
421 {
422 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
423 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
424 if (loc->sgpr_idx == -1)
425 return;
426 assert(loc->num_sgprs == 2);
427 assert(!loc->indirect);
428 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
429 radeon_emit(cmd_buffer->cs, va);
430 radeon_emit(cmd_buffer->cs, va >> 32);
431 }
432
433 static void
434 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
435 struct radv_pipeline *pipeline)
436 {
437 int num_samples = pipeline->graphics.ms.num_samples;
438 struct radv_multisample_state *ms = &pipeline->graphics.ms;
439 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
440
441 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
442 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
443 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
444
445 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
446 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
447
448 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
449 return;
450
451 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
452 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
453 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
454
455 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
456
457 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
458 uint32_t offset;
459 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
460 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
461 if (loc->sgpr_idx == -1)
462 return;
463 assert(loc->num_sgprs == 1);
464 assert(!loc->indirect);
465 switch (num_samples) {
466 default:
467 offset = 0;
468 break;
469 case 2:
470 offset = 1;
471 break;
472 case 4:
473 offset = 3;
474 break;
475 case 8:
476 offset = 7;
477 break;
478 case 16:
479 offset = 15;
480 break;
481 }
482
483 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
484 cmd_buffer->sample_positions_needed = true;
485 }
486 }
487
488 static void
489 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
490 struct radv_pipeline *pipeline)
491 {
492 struct radv_raster_state *raster = &pipeline->graphics.raster;
493
494 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
495 raster->pa_cl_clip_cntl);
496
497 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
498 raster->spi_interp_control);
499
500 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
501 unsigned tmp = (unsigned)(1.0 * 8.0);
502 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
503 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
504 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
505
506 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
507 raster->pa_su_vtx_cntl);
508
509 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
510 raster->pa_su_sc_mode_cntl);
511 }
512
513 static void
514 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
515 struct radv_pipeline *pipeline,
516 struct radv_shader_variant *shader,
517 struct ac_vs_output_info *outinfo)
518 {
519 struct radeon_winsys *ws = cmd_buffer->device->ws;
520 uint64_t va = ws->buffer_get_va(shader->bo);
521 unsigned export_count;
522
523 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
524 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
525
526 export_count = MAX2(1, outinfo->param_exports);
527 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
528 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
529
530 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
531 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
532 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
533 V_02870C_SPI_SHADER_4COMP :
534 V_02870C_SPI_SHADER_NONE) |
535 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
536 V_02870C_SPI_SHADER_4COMP :
537 V_02870C_SPI_SHADER_NONE) |
538 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
539 V_02870C_SPI_SHADER_4COMP :
540 V_02870C_SPI_SHADER_NONE));
541
542
543 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
544 radeon_emit(cmd_buffer->cs, va >> 8);
545 radeon_emit(cmd_buffer->cs, va >> 40);
546 radeon_emit(cmd_buffer->cs, shader->rsrc1);
547 radeon_emit(cmd_buffer->cs, shader->rsrc2);
548
549 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
550 S_028818_VTX_W0_FMT(1) |
551 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
552 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
553 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
554
555
556 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
557 pipeline->graphics.pa_cl_vs_out_cntl);
558
559 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
560 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
561 }
562
563 static void
564 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
565 struct radv_shader_variant *shader,
566 struct ac_es_output_info *outinfo)
567 {
568 struct radeon_winsys *ws = cmd_buffer->device->ws;
569 uint64_t va = ws->buffer_get_va(shader->bo);
570
571 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
572 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
573
574 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
575 outinfo->esgs_itemsize / 4);
576 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
577 radeon_emit(cmd_buffer->cs, va >> 8);
578 radeon_emit(cmd_buffer->cs, va >> 40);
579 radeon_emit(cmd_buffer->cs, shader->rsrc1);
580 radeon_emit(cmd_buffer->cs, shader->rsrc2);
581 }
582
583 static void
584 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
585 struct radv_shader_variant *shader)
586 {
587 struct radeon_winsys *ws = cmd_buffer->device->ws;
588 uint64_t va = ws->buffer_get_va(shader->bo);
589 uint32_t rsrc2 = shader->rsrc2;
590
591 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
592 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
593
594 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
595 radeon_emit(cmd_buffer->cs, va >> 8);
596 radeon_emit(cmd_buffer->cs, va >> 40);
597
598 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
599 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
600 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
601 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
602
603 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
604 radeon_emit(cmd_buffer->cs, shader->rsrc1);
605 radeon_emit(cmd_buffer->cs, rsrc2);
606 }
607
608 static void
609 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
610 struct radv_shader_variant *shader)
611 {
612 struct radeon_winsys *ws = cmd_buffer->device->ws;
613 uint64_t va = ws->buffer_get_va(shader->bo);
614
615 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
616 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
617
618 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
619 radeon_emit(cmd_buffer->cs, va >> 8);
620 radeon_emit(cmd_buffer->cs, va >> 40);
621 radeon_emit(cmd_buffer->cs, shader->rsrc1);
622 radeon_emit(cmd_buffer->cs, shader->rsrc2);
623 }
624
625 static void
626 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
627 struct radv_pipeline *pipeline)
628 {
629 struct radv_shader_variant *vs;
630
631 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
632
633 vs = pipeline->shaders[MESA_SHADER_VERTEX];
634
635 if (vs->info.vs.as_ls)
636 radv_emit_hw_ls(cmd_buffer, vs);
637 else if (vs->info.vs.as_es)
638 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
639 else
640 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
641
642 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
643 }
644
645
646 static void
647 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
648 struct radv_pipeline *pipeline)
649 {
650 if (!radv_pipeline_has_tess(pipeline))
651 return;
652
653 struct radv_shader_variant *tes, *tcs;
654
655 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
656 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
657
658 if (tes->info.tes.as_es)
659 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
660 else
661 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
662
663 radv_emit_hw_hs(cmd_buffer, tcs);
664
665 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
666 pipeline->graphics.tess.tf_param);
667
668 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
669 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
670 pipeline->graphics.tess.ls_hs_config);
671 else
672 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
673 pipeline->graphics.tess.ls_hs_config);
674
675 struct ac_userdata_info *loc;
676
677 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
678 if (loc->sgpr_idx != -1) {
679 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
680 assert(loc->num_sgprs == 4);
681 assert(!loc->indirect);
682 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
683 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
684 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
685 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
686 pipeline->graphics.tess.num_tcs_input_cp << 26);
687 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
688 }
689
690 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
691 if (loc->sgpr_idx != -1) {
692 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
693 assert(loc->num_sgprs == 1);
694 assert(!loc->indirect);
695
696 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
697 pipeline->graphics.tess.offchip_layout);
698 }
699
700 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
701 if (loc->sgpr_idx != -1) {
702 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
703 assert(loc->num_sgprs == 1);
704 assert(!loc->indirect);
705
706 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
707 pipeline->graphics.tess.tcs_in_layout);
708 }
709 }
710
711 static void
712 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
713 struct radv_pipeline *pipeline)
714 {
715 struct radeon_winsys *ws = cmd_buffer->device->ws;
716 struct radv_shader_variant *gs;
717 uint64_t va;
718
719 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
720
721 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
722 if (!gs)
723 return;
724
725 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
726
727 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
728 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
729 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
730 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
731
732 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
733
734 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
735
736 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
737 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
738 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
739 radeon_emit(cmd_buffer->cs, 0);
740 radeon_emit(cmd_buffer->cs, 0);
741 radeon_emit(cmd_buffer->cs, 0);
742
743 uint32_t gs_num_invocations = gs->info.gs.invocations;
744 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
745 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
746 S_028B90_ENABLE(gs_num_invocations > 0));
747
748 va = ws->buffer_get_va(gs->bo);
749 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
750 si_cp_dma_prefetch(cmd_buffer, va, gs->code_size);
751 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
752 radeon_emit(cmd_buffer->cs, va >> 8);
753 radeon_emit(cmd_buffer->cs, va >> 40);
754 radeon_emit(cmd_buffer->cs, gs->rsrc1);
755 radeon_emit(cmd_buffer->cs, gs->rsrc2);
756
757 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
758
759 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
760 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
761 if (loc->sgpr_idx != -1) {
762 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
763 uint32_t num_entries = 64;
764 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
765
766 if (is_vi)
767 num_entries *= stride;
768
769 stride = S_008F04_STRIDE(stride);
770 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
771 radeon_emit(cmd_buffer->cs, stride);
772 radeon_emit(cmd_buffer->cs, num_entries);
773 }
774 }
775
776 static void
777 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
778 struct radv_pipeline *pipeline)
779 {
780 struct radeon_winsys *ws = cmd_buffer->device->ws;
781 struct radv_shader_variant *ps;
782 uint64_t va;
783 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
784 struct radv_blend_state *blend = &pipeline->graphics.blend;
785 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
786
787 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
788
789 va = ws->buffer_get_va(ps->bo);
790 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
791 si_cp_dma_prefetch(cmd_buffer, va, ps->code_size);
792
793 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
794 radeon_emit(cmd_buffer->cs, va >> 8);
795 radeon_emit(cmd_buffer->cs, va >> 40);
796 radeon_emit(cmd_buffer->cs, ps->rsrc1);
797 radeon_emit(cmd_buffer->cs, ps->rsrc2);
798
799 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
800 pipeline->graphics.db_shader_control);
801
802 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
803 ps->config.spi_ps_input_ena);
804
805 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
806 ps->config.spi_ps_input_addr);
807
808 if (ps->info.fs.force_persample)
809 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
810
811 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
812 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
813
814 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
815
816 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
817 pipeline->graphics.shader_z_format);
818
819 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
820
821 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
822 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
823
824 if (pipeline->graphics.ps_input_cntl_num) {
825 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
826 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
827 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
828 }
829 }
830 }
831
832 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
833 struct radv_pipeline *pipeline)
834 {
835 uint32_t vtx_reuse_depth = 30;
836 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
837 return;
838
839 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
840 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
841 vtx_reuse_depth = 14;
842 }
843 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
844 vtx_reuse_depth);
845 }
846
847 static void
848 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
849 struct radv_pipeline *pipeline)
850 {
851 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
852 return;
853
854 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
855 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
856 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
857 radv_update_multisample_state(cmd_buffer, pipeline);
858 radv_emit_vertex_shader(cmd_buffer, pipeline);
859 radv_emit_tess_shaders(cmd_buffer, pipeline);
860 radv_emit_geometry_shader(cmd_buffer, pipeline);
861 radv_emit_fragment_shader(cmd_buffer, pipeline);
862 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
863
864 cmd_buffer->scratch_size_needed =
865 MAX2(cmd_buffer->scratch_size_needed,
866 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
867
868 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
869 S_0286E8_WAVES(pipeline->max_waves) |
870 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
871
872 if (!cmd_buffer->state.emitted_pipeline ||
873 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
874 pipeline->graphics.can_use_guardband)
875 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
876 cmd_buffer->state.emitted_pipeline = pipeline;
877 }
878
879 static void
880 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
881 {
882 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
883 cmd_buffer->state.dynamic.viewport.viewports);
884 }
885
886 static void
887 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
888 {
889 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
890 si_write_scissors(cmd_buffer->cs, 0, count,
891 cmd_buffer->state.dynamic.scissor.scissors,
892 cmd_buffer->state.dynamic.viewport.viewports,
893 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
894 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
895 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
896 }
897
898 static void
899 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
900 int index,
901 struct radv_color_buffer_info *cb)
902 {
903 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
904 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
905 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
906 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
907 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
908 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
909 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
910 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
911 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
912 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
913 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
914 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
915 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
916
917 if (is_vi) { /* DCC BASE */
918 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
919 }
920 }
921
922 static void
923 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
924 struct radv_ds_buffer_info *ds,
925 struct radv_image *image,
926 VkImageLayout layout)
927 {
928 uint32_t db_z_info = ds->db_z_info;
929
930 if (!radv_layout_has_htile(image, layout))
931 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
932
933 if (!radv_layout_can_expclear(image, layout))
934 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
935
936 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
937 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
938
939 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
940 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
941 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
942 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
943 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
944 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
945 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
946 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
947 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
948 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
949
950 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
951 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
952 ds->pa_su_poly_offset_db_fmt_cntl);
953 }
954
955 /*
956 * To hw resolve multisample images both src and dst need to have the same
957 * micro tiling mode. However we don't always know in advance when creating
958 * the images. This function gets called if we have a resolve attachment,
959 * and tests if the attachment image has the same tiling mode, then it
960 * checks if the generated framebuffer data has the same tiling mode, and
961 * updates it if not.
962 */
963 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
964 struct radv_attachment_info *att,
965 uint32_t micro_tile_mode)
966 {
967 struct radv_image *image = att->attachment->image;
968 uint32_t tile_mode_index;
969 if (image->surface.nsamples <= 1)
970 return;
971
972 if (image->surface.micro_tile_mode != micro_tile_mode) {
973 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
974 }
975
976 if (att->cb.micro_tile_mode != micro_tile_mode) {
977 tile_mode_index = image->surface.tiling_index[0];
978
979 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
980 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
981 att->cb.micro_tile_mode = micro_tile_mode;
982 }
983 }
984
985 void
986 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
987 struct radv_image *image,
988 VkClearDepthStencilValue ds_clear_value,
989 VkImageAspectFlags aspects)
990 {
991 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
992 va += image->offset + image->clear_value_offset;
993 unsigned reg_offset = 0, reg_count = 0;
994
995 if (!image->surface.htile_size || !aspects)
996 return;
997
998 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
999 ++reg_count;
1000 } else {
1001 ++reg_offset;
1002 va += 4;
1003 }
1004 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1005 ++reg_count;
1006
1007 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1008
1009 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1010 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1011 S_370_WR_CONFIRM(1) |
1012 S_370_ENGINE_SEL(V_370_PFP));
1013 radeon_emit(cmd_buffer->cs, va);
1014 radeon_emit(cmd_buffer->cs, va >> 32);
1015 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1016 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1017 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1018 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1019
1020 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1021 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1022 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1023 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1024 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1025 }
1026
1027 static void
1028 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1029 struct radv_image *image)
1030 {
1031 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1032 va += image->offset + image->clear_value_offset;
1033
1034 if (!image->surface.htile_size)
1035 return;
1036
1037 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1038
1039 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1040 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1041 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1042 COPY_DATA_COUNT_SEL);
1043 radeon_emit(cmd_buffer->cs, va);
1044 radeon_emit(cmd_buffer->cs, va >> 32);
1045 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1046 radeon_emit(cmd_buffer->cs, 0);
1047
1048 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1049 radeon_emit(cmd_buffer->cs, 0);
1050 }
1051
1052 void
1053 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1054 struct radv_image *image,
1055 int idx,
1056 uint32_t color_values[2])
1057 {
1058 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1059 va += image->offset + image->clear_value_offset;
1060
1061 if (!image->cmask.size && !image->surface.dcc_size)
1062 return;
1063
1064 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1065
1066 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1067 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1068 S_370_WR_CONFIRM(1) |
1069 S_370_ENGINE_SEL(V_370_PFP));
1070 radeon_emit(cmd_buffer->cs, va);
1071 radeon_emit(cmd_buffer->cs, va >> 32);
1072 radeon_emit(cmd_buffer->cs, color_values[0]);
1073 radeon_emit(cmd_buffer->cs, color_values[1]);
1074
1075 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1076 radeon_emit(cmd_buffer->cs, color_values[0]);
1077 radeon_emit(cmd_buffer->cs, color_values[1]);
1078 }
1079
1080 static void
1081 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1082 struct radv_image *image,
1083 int idx)
1084 {
1085 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1086 va += image->offset + image->clear_value_offset;
1087
1088 if (!image->cmask.size && !image->surface.dcc_size)
1089 return;
1090
1091 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1092 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1093
1094 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1095 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1096 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1097 COPY_DATA_COUNT_SEL);
1098 radeon_emit(cmd_buffer->cs, va);
1099 radeon_emit(cmd_buffer->cs, va >> 32);
1100 radeon_emit(cmd_buffer->cs, reg >> 2);
1101 radeon_emit(cmd_buffer->cs, 0);
1102
1103 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1104 radeon_emit(cmd_buffer->cs, 0);
1105 }
1106
1107 void
1108 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1109 {
1110 int i;
1111 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1112 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1113 int dst_resolve_micro_tile_mode = -1;
1114
1115 if (subpass->has_resolve) {
1116 uint32_t a = subpass->resolve_attachments[0].attachment;
1117 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
1118 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
1119 }
1120 for (i = 0; i < subpass->color_count; ++i) {
1121 int idx = subpass->color_attachments[i].attachment;
1122 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1123
1124 if (dst_resolve_micro_tile_mode != -1) {
1125 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
1126 att, dst_resolve_micro_tile_mode);
1127 }
1128 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1129
1130 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1131 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1132
1133 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1134 }
1135
1136 for (i = subpass->color_count; i < 8; i++)
1137 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1138 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1139
1140 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1141 int idx = subpass->depth_stencil_attachment.attachment;
1142 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1143 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1144 struct radv_image *image = att->attachment->image;
1145 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1146
1147 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1148
1149 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1150 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1151 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1152 }
1153 radv_load_depth_clear_regs(cmd_buffer, image);
1154 } else {
1155 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1156 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1157 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1158 }
1159 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1160 S_028208_BR_X(framebuffer->width) |
1161 S_028208_BR_Y(framebuffer->height));
1162 }
1163
1164 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1165 {
1166 uint32_t db_count_control;
1167
1168 if(!cmd_buffer->state.active_occlusion_queries) {
1169 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1170 db_count_control = 0;
1171 } else {
1172 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1173 }
1174 } else {
1175 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1176 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1177 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1178 S_028004_ZPASS_ENABLE(1) |
1179 S_028004_SLICE_EVEN_ENABLE(1) |
1180 S_028004_SLICE_ODD_ENABLE(1);
1181 } else {
1182 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1183 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1184 }
1185 }
1186
1187 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1188 }
1189
1190 static void
1191 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1192 {
1193 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1194
1195 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1196 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1197 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1198 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1199 }
1200
1201 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1202 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1203 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1204 }
1205
1206 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1207 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1208 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1209 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1210 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1211 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1212 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1213 S_028430_STENCILOPVAL(1));
1214 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1215 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1216 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1217 S_028434_STENCILOPVAL_BF(1));
1218 }
1219
1220 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1221 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1222 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1223 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1224 }
1225
1226 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1227 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1228 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1229 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1230 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1231
1232 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1233 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1234 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1235 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1236 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1237 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1238 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1239 }
1240 }
1241
1242 cmd_buffer->state.dirty = 0;
1243 }
1244
1245 static void
1246 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1247 struct radv_pipeline *pipeline,
1248 int idx,
1249 uint64_t va,
1250 gl_shader_stage stage)
1251 {
1252 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1253 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1254
1255 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1256 return;
1257
1258 assert(!desc_set_loc->indirect);
1259 assert(desc_set_loc->num_sgprs == 2);
1260 radeon_set_sh_reg_seq(cmd_buffer->cs,
1261 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1262 radeon_emit(cmd_buffer->cs, va);
1263 radeon_emit(cmd_buffer->cs, va >> 32);
1264 }
1265
1266 static void
1267 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1268 struct radv_pipeline *pipeline,
1269 VkShaderStageFlags stages,
1270 struct radv_descriptor_set *set,
1271 unsigned idx)
1272 {
1273 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1274 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1275 idx, set->va,
1276 MESA_SHADER_FRAGMENT);
1277
1278 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1279 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1280 idx, set->va,
1281 MESA_SHADER_VERTEX);
1282
1283 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1284 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1285 idx, set->va,
1286 MESA_SHADER_GEOMETRY);
1287
1288 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1289 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1290 idx, set->va,
1291 MESA_SHADER_TESS_CTRL);
1292
1293 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1294 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1295 idx, set->va,
1296 MESA_SHADER_TESS_EVAL);
1297
1298 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1299 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1300 idx, set->va,
1301 MESA_SHADER_COMPUTE);
1302 }
1303
1304 static void
1305 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1306 {
1307 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1308 uint32_t *ptr = NULL;
1309 unsigned bo_offset;
1310
1311 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1312 &bo_offset,
1313 (void**) &ptr))
1314 return;
1315
1316 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1317 set->va += bo_offset;
1318
1319 memcpy(ptr, set->mapped_ptr, set->size);
1320 }
1321
1322 static void
1323 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1324 struct radv_pipeline *pipeline)
1325 {
1326 uint32_t size = MAX_SETS * 2 * 4;
1327 uint32_t offset;
1328 void *ptr;
1329
1330 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1331 256, &offset, &ptr))
1332 return;
1333
1334 for (unsigned i = 0; i < MAX_SETS; i++) {
1335 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1336 uint64_t set_va = 0;
1337 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1338 if (set)
1339 set_va = set->va;
1340 uptr[0] = set_va & 0xffffffff;
1341 uptr[1] = set_va >> 32;
1342 }
1343
1344 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1345 va += offset;
1346
1347 if (pipeline->shaders[MESA_SHADER_VERTEX])
1348 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1349 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1350
1351 if (pipeline->shaders[MESA_SHADER_FRAGMENT])
1352 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1353 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1354
1355 if (radv_pipeline_has_gs(pipeline))
1356 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1357 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1358
1359 if (radv_pipeline_has_tess(pipeline))
1360 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL,
1361 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1362
1363 if (radv_pipeline_has_tess(pipeline))
1364 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL,
1365 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1366
1367 if (pipeline->shaders[MESA_SHADER_COMPUTE])
1368 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1369 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1370 }
1371
1372 static void
1373 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1374 struct radv_pipeline *pipeline,
1375 VkShaderStageFlags stages)
1376 {
1377 unsigned i;
1378
1379 if (!cmd_buffer->state.descriptors_dirty)
1380 return;
1381
1382 if (cmd_buffer->state.push_descriptors_dirty)
1383 radv_flush_push_descriptors(cmd_buffer);
1384
1385 if (pipeline->need_indirect_descriptor_sets) {
1386 radv_flush_indirect_descriptor_sets(cmd_buffer, pipeline);
1387 }
1388
1389 for (i = 0; i < MAX_SETS; i++) {
1390 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1391 continue;
1392 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1393 if (!set)
1394 continue;
1395
1396 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1397 }
1398 cmd_buffer->state.descriptors_dirty = 0;
1399 cmd_buffer->state.push_descriptors_dirty = false;
1400 }
1401
1402 static void
1403 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1404 struct radv_pipeline *pipeline,
1405 VkShaderStageFlags stages)
1406 {
1407 struct radv_pipeline_layout *layout = pipeline->layout;
1408 unsigned offset;
1409 void *ptr;
1410 uint64_t va;
1411
1412 stages &= cmd_buffer->push_constant_stages;
1413 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1414 return;
1415
1416 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1417 16 * layout->dynamic_offset_count,
1418 256, &offset, &ptr))
1419 return;
1420
1421 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1422 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1423 16 * layout->dynamic_offset_count);
1424
1425 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1426 va += offset;
1427
1428 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1429 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1430 AC_UD_PUSH_CONSTANTS, va);
1431
1432 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1433 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1434 AC_UD_PUSH_CONSTANTS, va);
1435
1436 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1437 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1438 AC_UD_PUSH_CONSTANTS, va);
1439
1440 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1441 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL,
1442 AC_UD_PUSH_CONSTANTS, va);
1443
1444 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1445 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL,
1446 AC_UD_PUSH_CONSTANTS, va);
1447
1448 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1449 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1450 AC_UD_PUSH_CONSTANTS, va);
1451
1452 cmd_buffer->push_constant_stages &= ~stages;
1453 }
1454
1455 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1456 bool indexed_draw)
1457 {
1458 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1459
1460 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1461 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1462 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1463 primitive_reset_en);
1464 }
1465
1466 if (primitive_reset_en) {
1467 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1468
1469 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1470 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1471 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1472 primitive_reset_index);
1473 }
1474 }
1475 }
1476
1477 static void
1478 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1479 bool indexed_draw, bool instanced_draw,
1480 bool indirect_draw,
1481 uint32_t draw_vertex_count)
1482 {
1483 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1484 struct radv_device *device = cmd_buffer->device;
1485 uint32_t ia_multi_vgt_param;
1486
1487 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1488 cmd_buffer->cs, 4096);
1489
1490 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1491 cmd_buffer->state.pipeline->num_vertex_attribs &&
1492 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1493 unsigned vb_offset;
1494 void *vb_ptr;
1495 uint32_t i = 0;
1496 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1497 uint64_t va;
1498
1499 /* allocate some descriptor state for vertex buffers */
1500 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1501 &vb_offset, &vb_ptr);
1502
1503 for (i = 0; i < num_attribs; i++) {
1504 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1505 uint32_t offset;
1506 int vb = cmd_buffer->state.pipeline->va_binding[i];
1507 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1508 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1509
1510 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1511 va = device->ws->buffer_get_va(buffer->bo);
1512
1513 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1514 va += offset + buffer->offset;
1515 desc[0] = va;
1516 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1517 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1518 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1519 else
1520 desc[2] = buffer->size - offset;
1521 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1522 }
1523
1524 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1525 va += vb_offset;
1526
1527 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1528 AC_UD_VS_VERTEX_BUFFERS, va);
1529 }
1530
1531 cmd_buffer->state.vertex_descriptors_dirty = false;
1532 cmd_buffer->state.vb_dirty = 0;
1533 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1534 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1535
1536 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1537 radv_emit_framebuffer_state(cmd_buffer);
1538
1539 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1540 radv_emit_viewport(cmd_buffer);
1541
1542 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1543 radv_emit_scissor(cmd_buffer);
1544
1545 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1546 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1547 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1548 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1549 else
1550 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1551 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1552 }
1553
1554 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1555 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1556
1557 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1558 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1559 } else {
1560 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1561 }
1562 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1563 }
1564
1565 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1566
1567 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1568
1569 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1570 VK_SHADER_STAGE_ALL_GRAPHICS);
1571 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1572 VK_SHADER_STAGE_ALL_GRAPHICS);
1573
1574 assert(cmd_buffer->cs->cdw <= cdw_max);
1575
1576 si_emit_cache_flush(cmd_buffer);
1577 }
1578
1579 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1580 VkPipelineStageFlags src_stage_mask)
1581 {
1582 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1583 VK_PIPELINE_STAGE_TRANSFER_BIT |
1584 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1585 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1586 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1587 }
1588
1589 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1590 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1591 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1592 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1593 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1594 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1595 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1596 VK_PIPELINE_STAGE_TRANSFER_BIT |
1597 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1598 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1599 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1600 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1601 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1602 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1603 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1604 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1605 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1606 }
1607 }
1608
1609 static enum radv_cmd_flush_bits
1610 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1611 VkAccessFlags src_flags)
1612 {
1613 enum radv_cmd_flush_bits flush_bits = 0;
1614 uint32_t b;
1615 for_each_bit(b, src_flags) {
1616 switch ((VkAccessFlagBits)(1 << b)) {
1617 case VK_ACCESS_SHADER_WRITE_BIT:
1618 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1619 break;
1620 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1621 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1622 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1623 break;
1624 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1625 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1626 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1627 break;
1628 case VK_ACCESS_TRANSFER_WRITE_BIT:
1629 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1630 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1631 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1632 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1633 RADV_CMD_FLAG_INV_GLOBAL_L2;
1634 break;
1635 default:
1636 break;
1637 }
1638 }
1639 return flush_bits;
1640 }
1641
1642 static enum radv_cmd_flush_bits
1643 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1644 VkAccessFlags dst_flags,
1645 struct radv_image *image)
1646 {
1647 enum radv_cmd_flush_bits flush_bits = 0;
1648 uint32_t b;
1649 for_each_bit(b, dst_flags) {
1650 switch ((VkAccessFlagBits)(1 << b)) {
1651 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1652 case VK_ACCESS_INDEX_READ_BIT:
1653 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1654 break;
1655 case VK_ACCESS_UNIFORM_READ_BIT:
1656 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1657 break;
1658 case VK_ACCESS_SHADER_READ_BIT:
1659 case VK_ACCESS_TRANSFER_READ_BIT:
1660 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1661 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1662 RADV_CMD_FLAG_INV_GLOBAL_L2;
1663 break;
1664 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1665 /* TODO: change to image && when the image gets passed
1666 * through from the subpass. */
1667 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1668 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1669 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1670 break;
1671 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1672 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1673 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1674 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1675 break;
1676 default:
1677 break;
1678 }
1679 }
1680 return flush_bits;
1681 }
1682
1683 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1684 {
1685 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1686 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1687 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1688 NULL);
1689 }
1690
1691 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1692 VkAttachmentReference att)
1693 {
1694 unsigned idx = att.attachment;
1695 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1696 VkImageSubresourceRange range;
1697 range.aspectMask = 0;
1698 range.baseMipLevel = view->base_mip;
1699 range.levelCount = 1;
1700 range.baseArrayLayer = view->base_layer;
1701 range.layerCount = cmd_buffer->state.framebuffer->layers;
1702
1703 radv_handle_image_transition(cmd_buffer,
1704 view->image,
1705 cmd_buffer->state.attachments[idx].current_layout,
1706 att.layout, 0, 0, &range,
1707 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1708
1709 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1710
1711
1712 }
1713
1714 void
1715 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1716 const struct radv_subpass *subpass, bool transitions)
1717 {
1718 if (transitions) {
1719 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1720
1721 for (unsigned i = 0; i < subpass->color_count; ++i) {
1722 radv_handle_subpass_image_transition(cmd_buffer,
1723 subpass->color_attachments[i]);
1724 }
1725
1726 for (unsigned i = 0; i < subpass->input_count; ++i) {
1727 radv_handle_subpass_image_transition(cmd_buffer,
1728 subpass->input_attachments[i]);
1729 }
1730
1731 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1732 radv_handle_subpass_image_transition(cmd_buffer,
1733 subpass->depth_stencil_attachment);
1734 }
1735 }
1736
1737 cmd_buffer->state.subpass = subpass;
1738
1739 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1740 }
1741
1742 static void
1743 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1744 struct radv_render_pass *pass,
1745 const VkRenderPassBeginInfo *info)
1746 {
1747 struct radv_cmd_state *state = &cmd_buffer->state;
1748
1749 if (pass->attachment_count == 0) {
1750 state->attachments = NULL;
1751 return;
1752 }
1753
1754 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1755 pass->attachment_count *
1756 sizeof(state->attachments[0]),
1757 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1758 if (state->attachments == NULL) {
1759 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1760 abort();
1761 }
1762
1763 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1764 struct radv_render_pass_attachment *att = &pass->attachments[i];
1765 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1766 VkImageAspectFlags clear_aspects = 0;
1767
1768 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1769 /* color attachment */
1770 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1771 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1772 }
1773 } else {
1774 /* depthstencil attachment */
1775 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1776 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1777 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1778 }
1779 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1780 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1781 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1782 }
1783 }
1784
1785 state->attachments[i].pending_clear_aspects = clear_aspects;
1786 if (clear_aspects && info) {
1787 assert(info->clearValueCount > i);
1788 state->attachments[i].clear_value = info->pClearValues[i];
1789 }
1790
1791 state->attachments[i].current_layout = att->initial_layout;
1792 }
1793 }
1794
1795 VkResult radv_AllocateCommandBuffers(
1796 VkDevice _device,
1797 const VkCommandBufferAllocateInfo *pAllocateInfo,
1798 VkCommandBuffer *pCommandBuffers)
1799 {
1800 RADV_FROM_HANDLE(radv_device, device, _device);
1801 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1802
1803 VkResult result = VK_SUCCESS;
1804 uint32_t i;
1805
1806 memset(pCommandBuffers, 0,
1807 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1808
1809 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1810
1811 if (!list_empty(&pool->free_cmd_buffers)) {
1812 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1813
1814 list_del(&cmd_buffer->pool_link);
1815 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1816
1817 radv_reset_cmd_buffer(cmd_buffer);
1818 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1819 cmd_buffer->level = pAllocateInfo->level;
1820
1821 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1822 result = VK_SUCCESS;
1823 } else {
1824 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1825 &pCommandBuffers[i]);
1826 }
1827 if (result != VK_SUCCESS)
1828 break;
1829 }
1830
1831 if (result != VK_SUCCESS)
1832 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1833 i, pCommandBuffers);
1834
1835 return result;
1836 }
1837
1838 void radv_FreeCommandBuffers(
1839 VkDevice device,
1840 VkCommandPool commandPool,
1841 uint32_t commandBufferCount,
1842 const VkCommandBuffer *pCommandBuffers)
1843 {
1844 for (uint32_t i = 0; i < commandBufferCount; i++) {
1845 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1846
1847 if (cmd_buffer) {
1848 if (cmd_buffer->pool) {
1849 list_del(&cmd_buffer->pool_link);
1850 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1851 } else
1852 radv_cmd_buffer_destroy(cmd_buffer);
1853
1854 }
1855 }
1856 }
1857
1858 VkResult radv_ResetCommandBuffer(
1859 VkCommandBuffer commandBuffer,
1860 VkCommandBufferResetFlags flags)
1861 {
1862 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1863 radv_reset_cmd_buffer(cmd_buffer);
1864 return VK_SUCCESS;
1865 }
1866
1867 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1868 {
1869 struct radv_device *device = cmd_buffer->device;
1870 if (device->gfx_init) {
1871 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1872 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1873 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1874 radeon_emit(cmd_buffer->cs, va);
1875 radeon_emit(cmd_buffer->cs, (va >> 32) & 0xffff);
1876 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1877 } else
1878 si_init_config(cmd_buffer);
1879 }
1880
1881 VkResult radv_BeginCommandBuffer(
1882 VkCommandBuffer commandBuffer,
1883 const VkCommandBufferBeginInfo *pBeginInfo)
1884 {
1885 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1886 radv_reset_cmd_buffer(cmd_buffer);
1887
1888 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1889 cmd_buffer->state.last_primitive_reset_en = -1;
1890
1891 /* setup initial configuration into command buffer */
1892 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1893 switch (cmd_buffer->queue_family_index) {
1894 case RADV_QUEUE_GENERAL:
1895 emit_gfx_buffer_state(cmd_buffer);
1896 radv_set_db_count_control(cmd_buffer);
1897 break;
1898 case RADV_QUEUE_COMPUTE:
1899 si_init_compute(cmd_buffer);
1900 break;
1901 case RADV_QUEUE_TRANSFER:
1902 default:
1903 break;
1904 }
1905 }
1906
1907 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1908 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1909 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1910
1911 struct radv_subpass *subpass =
1912 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1913
1914 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1915 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1916 }
1917
1918 radv_cmd_buffer_trace_emit(cmd_buffer);
1919 return VK_SUCCESS;
1920 }
1921
1922 void radv_CmdBindVertexBuffers(
1923 VkCommandBuffer commandBuffer,
1924 uint32_t firstBinding,
1925 uint32_t bindingCount,
1926 const VkBuffer* pBuffers,
1927 const VkDeviceSize* pOffsets)
1928 {
1929 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1930 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1931
1932 /* We have to defer setting up vertex buffer since we need the buffer
1933 * stride from the pipeline. */
1934
1935 assert(firstBinding + bindingCount < MAX_VBS);
1936 for (uint32_t i = 0; i < bindingCount; i++) {
1937 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1938 vb[firstBinding + i].offset = pOffsets[i];
1939 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1940 }
1941 }
1942
1943 void radv_CmdBindIndexBuffer(
1944 VkCommandBuffer commandBuffer,
1945 VkBuffer buffer,
1946 VkDeviceSize offset,
1947 VkIndexType indexType)
1948 {
1949 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1950
1951 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1952 cmd_buffer->state.index_offset = offset;
1953 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1954 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1955 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1956 }
1957
1958
1959 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1960 struct radv_descriptor_set *set,
1961 unsigned idx)
1962 {
1963 struct radeon_winsys *ws = cmd_buffer->device->ws;
1964
1965 cmd_buffer->state.descriptors[idx] = set;
1966 cmd_buffer->state.descriptors_dirty |= (1u << idx);
1967 if (!set)
1968 return;
1969
1970 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1971 if (set->descriptors[j])
1972 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1973
1974 if(set->bo)
1975 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1976 }
1977
1978 void radv_CmdBindDescriptorSets(
1979 VkCommandBuffer commandBuffer,
1980 VkPipelineBindPoint pipelineBindPoint,
1981 VkPipelineLayout _layout,
1982 uint32_t firstSet,
1983 uint32_t descriptorSetCount,
1984 const VkDescriptorSet* pDescriptorSets,
1985 uint32_t dynamicOffsetCount,
1986 const uint32_t* pDynamicOffsets)
1987 {
1988 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1989 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1990 unsigned dyn_idx = 0;
1991
1992 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1993 unsigned idx = i + firstSet;
1994 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1995 radv_bind_descriptor_set(cmd_buffer, set, idx);
1996
1997 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1998 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1999 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2000 assert(dyn_idx < dynamicOffsetCount);
2001
2002 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2003 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2004 dst[0] = va;
2005 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2006 dst[2] = range->size;
2007 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2008 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2009 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2010 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2011 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2012 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2013 cmd_buffer->push_constant_stages |=
2014 set->layout->dynamic_shader_stages;
2015 }
2016 }
2017 }
2018
2019 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2020 struct radv_descriptor_set *set,
2021 struct radv_descriptor_set_layout *layout)
2022 {
2023 set->size = layout->size;
2024 set->layout = layout;
2025
2026 if (cmd_buffer->push_descriptors.capacity < set->size) {
2027 size_t new_size = MAX2(set->size, 1024);
2028 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2029 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2030
2031 free(set->mapped_ptr);
2032 set->mapped_ptr = malloc(new_size);
2033
2034 if (!set->mapped_ptr) {
2035 cmd_buffer->push_descriptors.capacity = 0;
2036 cmd_buffer->record_fail = true;
2037 return false;
2038 }
2039
2040 cmd_buffer->push_descriptors.capacity = new_size;
2041 }
2042
2043 return true;
2044 }
2045
2046 void radv_meta_push_descriptor_set(
2047 struct radv_cmd_buffer* cmd_buffer,
2048 VkPipelineBindPoint pipelineBindPoint,
2049 VkPipelineLayout _layout,
2050 uint32_t set,
2051 uint32_t descriptorWriteCount,
2052 const VkWriteDescriptorSet* pDescriptorWrites)
2053 {
2054 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2055 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2056 unsigned bo_offset;
2057
2058 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2059
2060 push_set->size = layout->set[set].layout->size;
2061 push_set->layout = layout->set[set].layout;
2062
2063 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2064 &bo_offset,
2065 (void**) &push_set->mapped_ptr))
2066 return;
2067
2068 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2069 push_set->va += bo_offset;
2070
2071 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2072 radv_descriptor_set_to_handle(push_set),
2073 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2074
2075 cmd_buffer->state.descriptors[set] = push_set;
2076 cmd_buffer->state.descriptors_dirty |= (1u << set);
2077 }
2078
2079 void radv_CmdPushDescriptorSetKHR(
2080 VkCommandBuffer commandBuffer,
2081 VkPipelineBindPoint pipelineBindPoint,
2082 VkPipelineLayout _layout,
2083 uint32_t set,
2084 uint32_t descriptorWriteCount,
2085 const VkWriteDescriptorSet* pDescriptorWrites)
2086 {
2087 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2088 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2089 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2090
2091 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2092
2093 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2094 return;
2095
2096 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2097 radv_descriptor_set_to_handle(push_set),
2098 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2099
2100 cmd_buffer->state.descriptors[set] = push_set;
2101 cmd_buffer->state.descriptors_dirty |= (1u << set);
2102 cmd_buffer->state.push_descriptors_dirty = true;
2103 }
2104
2105 void radv_CmdPushDescriptorSetWithTemplateKHR(
2106 VkCommandBuffer commandBuffer,
2107 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2108 VkPipelineLayout _layout,
2109 uint32_t set,
2110 const void* pData)
2111 {
2112 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2113 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2114 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2115
2116 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2117
2118 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2119 return;
2120
2121 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2122 descriptorUpdateTemplate, pData);
2123
2124 cmd_buffer->state.descriptors[set] = push_set;
2125 cmd_buffer->state.descriptors_dirty |= (1u << set);
2126 cmd_buffer->state.push_descriptors_dirty = true;
2127 }
2128
2129 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2130 VkPipelineLayout layout,
2131 VkShaderStageFlags stageFlags,
2132 uint32_t offset,
2133 uint32_t size,
2134 const void* pValues)
2135 {
2136 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2137 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2138 cmd_buffer->push_constant_stages |= stageFlags;
2139 }
2140
2141 VkResult radv_EndCommandBuffer(
2142 VkCommandBuffer commandBuffer)
2143 {
2144 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2145
2146 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
2147 si_emit_cache_flush(cmd_buffer);
2148
2149 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
2150 cmd_buffer->record_fail)
2151 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2152 return VK_SUCCESS;
2153 }
2154
2155 static void
2156 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2157 {
2158 struct radeon_winsys *ws = cmd_buffer->device->ws;
2159 struct radv_shader_variant *compute_shader;
2160 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2161 uint64_t va;
2162
2163 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2164 return;
2165
2166 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2167
2168 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2169 va = ws->buffer_get_va(compute_shader->bo);
2170
2171 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2172
2173 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2174 cmd_buffer->cs, 16);
2175
2176 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2177 radeon_emit(cmd_buffer->cs, va >> 8);
2178 radeon_emit(cmd_buffer->cs, va >> 40);
2179
2180 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2181 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2182 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2183
2184
2185 cmd_buffer->compute_scratch_size_needed =
2186 MAX2(cmd_buffer->compute_scratch_size_needed,
2187 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2188
2189 /* change these once we have scratch support */
2190 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2191 S_00B860_WAVES(pipeline->max_waves) |
2192 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2193
2194 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2195 radeon_emit(cmd_buffer->cs,
2196 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2197 radeon_emit(cmd_buffer->cs,
2198 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2199 radeon_emit(cmd_buffer->cs,
2200 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2201
2202 assert(cmd_buffer->cs->cdw <= cdw_max);
2203 }
2204
2205
2206 void radv_CmdBindPipeline(
2207 VkCommandBuffer commandBuffer,
2208 VkPipelineBindPoint pipelineBindPoint,
2209 VkPipeline _pipeline)
2210 {
2211 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2212 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2213
2214 for (unsigned i = 0; i < MAX_SETS; i++) {
2215 if (cmd_buffer->state.descriptors[i])
2216 cmd_buffer->state.descriptors_dirty |= (1u << i);
2217 }
2218
2219 switch (pipelineBindPoint) {
2220 case VK_PIPELINE_BIND_POINT_COMPUTE:
2221 cmd_buffer->state.compute_pipeline = pipeline;
2222 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2223 break;
2224 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2225 cmd_buffer->state.pipeline = pipeline;
2226 cmd_buffer->state.vertex_descriptors_dirty = true;
2227 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2228 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2229
2230 /* Apply the dynamic state from the pipeline */
2231 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2232 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2233 &pipeline->dynamic_state,
2234 pipeline->dynamic_state_mask);
2235
2236 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2237 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2238 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2239 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2240
2241 if (radv_pipeline_has_tess(pipeline))
2242 cmd_buffer->tess_rings_needed = true;
2243
2244 if (radv_pipeline_has_gs(pipeline)) {
2245 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2246 AC_UD_SCRATCH_RING_OFFSETS);
2247 if (cmd_buffer->ring_offsets_idx == -1)
2248 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2249 else if (loc->sgpr_idx != -1)
2250 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2251 }
2252 break;
2253 default:
2254 assert(!"invalid bind point");
2255 break;
2256 }
2257 }
2258
2259 void radv_CmdSetViewport(
2260 VkCommandBuffer commandBuffer,
2261 uint32_t firstViewport,
2262 uint32_t viewportCount,
2263 const VkViewport* pViewports)
2264 {
2265 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2266
2267 const uint32_t total_count = firstViewport + viewportCount;
2268 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2269 cmd_buffer->state.dynamic.viewport.count = total_count;
2270
2271 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2272 pViewports, viewportCount * sizeof(*pViewports));
2273
2274 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2275 }
2276
2277 void radv_CmdSetScissor(
2278 VkCommandBuffer commandBuffer,
2279 uint32_t firstScissor,
2280 uint32_t scissorCount,
2281 const VkRect2D* pScissors)
2282 {
2283 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2284
2285 const uint32_t total_count = firstScissor + scissorCount;
2286 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2287 cmd_buffer->state.dynamic.scissor.count = total_count;
2288
2289 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2290 pScissors, scissorCount * sizeof(*pScissors));
2291 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2292 }
2293
2294 void radv_CmdSetLineWidth(
2295 VkCommandBuffer commandBuffer,
2296 float lineWidth)
2297 {
2298 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2299 cmd_buffer->state.dynamic.line_width = lineWidth;
2300 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2301 }
2302
2303 void radv_CmdSetDepthBias(
2304 VkCommandBuffer commandBuffer,
2305 float depthBiasConstantFactor,
2306 float depthBiasClamp,
2307 float depthBiasSlopeFactor)
2308 {
2309 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2310
2311 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2312 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2313 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2314
2315 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2316 }
2317
2318 void radv_CmdSetBlendConstants(
2319 VkCommandBuffer commandBuffer,
2320 const float blendConstants[4])
2321 {
2322 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2323
2324 memcpy(cmd_buffer->state.dynamic.blend_constants,
2325 blendConstants, sizeof(float) * 4);
2326
2327 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2328 }
2329
2330 void radv_CmdSetDepthBounds(
2331 VkCommandBuffer commandBuffer,
2332 float minDepthBounds,
2333 float maxDepthBounds)
2334 {
2335 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2336
2337 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2338 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2339
2340 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2341 }
2342
2343 void radv_CmdSetStencilCompareMask(
2344 VkCommandBuffer commandBuffer,
2345 VkStencilFaceFlags faceMask,
2346 uint32_t compareMask)
2347 {
2348 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2349
2350 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2351 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2352 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2353 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2354
2355 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2356 }
2357
2358 void radv_CmdSetStencilWriteMask(
2359 VkCommandBuffer commandBuffer,
2360 VkStencilFaceFlags faceMask,
2361 uint32_t writeMask)
2362 {
2363 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2364
2365 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2366 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2367 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2368 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2369
2370 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2371 }
2372
2373 void radv_CmdSetStencilReference(
2374 VkCommandBuffer commandBuffer,
2375 VkStencilFaceFlags faceMask,
2376 uint32_t reference)
2377 {
2378 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2379
2380 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2381 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2382 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2383 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2384
2385 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2386 }
2387
2388
2389 void radv_CmdExecuteCommands(
2390 VkCommandBuffer commandBuffer,
2391 uint32_t commandBufferCount,
2392 const VkCommandBuffer* pCmdBuffers)
2393 {
2394 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2395
2396 /* Emit pending flushes on primary prior to executing secondary */
2397 si_emit_cache_flush(primary);
2398
2399 for (uint32_t i = 0; i < commandBufferCount; i++) {
2400 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2401
2402 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2403 secondary->scratch_size_needed);
2404 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2405 secondary->compute_scratch_size_needed);
2406
2407 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2408 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2409 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2410 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2411 if (secondary->tess_rings_needed)
2412 primary->tess_rings_needed = true;
2413 if (secondary->sample_positions_needed)
2414 primary->sample_positions_needed = true;
2415
2416 if (secondary->ring_offsets_idx != -1) {
2417 if (primary->ring_offsets_idx == -1)
2418 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2419 else
2420 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2421 }
2422 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2423 }
2424
2425 /* if we execute secondary we need to re-emit out pipelines */
2426 if (commandBufferCount) {
2427 primary->state.emitted_pipeline = NULL;
2428 primary->state.emitted_compute_pipeline = NULL;
2429 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2430 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2431 primary->state.last_primitive_reset_en = -1;
2432 primary->state.last_primitive_reset_index = 0;
2433 }
2434 }
2435
2436 VkResult radv_CreateCommandPool(
2437 VkDevice _device,
2438 const VkCommandPoolCreateInfo* pCreateInfo,
2439 const VkAllocationCallbacks* pAllocator,
2440 VkCommandPool* pCmdPool)
2441 {
2442 RADV_FROM_HANDLE(radv_device, device, _device);
2443 struct radv_cmd_pool *pool;
2444
2445 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2446 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2447 if (pool == NULL)
2448 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2449
2450 if (pAllocator)
2451 pool->alloc = *pAllocator;
2452 else
2453 pool->alloc = device->alloc;
2454
2455 list_inithead(&pool->cmd_buffers);
2456 list_inithead(&pool->free_cmd_buffers);
2457
2458 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2459
2460 *pCmdPool = radv_cmd_pool_to_handle(pool);
2461
2462 return VK_SUCCESS;
2463
2464 }
2465
2466 void radv_DestroyCommandPool(
2467 VkDevice _device,
2468 VkCommandPool commandPool,
2469 const VkAllocationCallbacks* pAllocator)
2470 {
2471 RADV_FROM_HANDLE(radv_device, device, _device);
2472 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2473
2474 if (!pool)
2475 return;
2476
2477 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2478 &pool->cmd_buffers, pool_link) {
2479 radv_cmd_buffer_destroy(cmd_buffer);
2480 }
2481
2482 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2483 &pool->free_cmd_buffers, pool_link) {
2484 radv_cmd_buffer_destroy(cmd_buffer);
2485 }
2486
2487 vk_free2(&device->alloc, pAllocator, pool);
2488 }
2489
2490 VkResult radv_ResetCommandPool(
2491 VkDevice device,
2492 VkCommandPool commandPool,
2493 VkCommandPoolResetFlags flags)
2494 {
2495 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2496
2497 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2498 &pool->cmd_buffers, pool_link) {
2499 radv_reset_cmd_buffer(cmd_buffer);
2500 }
2501
2502 return VK_SUCCESS;
2503 }
2504
2505 void radv_TrimCommandPoolKHR(
2506 VkDevice device,
2507 VkCommandPool commandPool,
2508 VkCommandPoolTrimFlagsKHR flags)
2509 {
2510 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2511
2512 if (!pool)
2513 return;
2514
2515 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2516 &pool->free_cmd_buffers, pool_link) {
2517 radv_cmd_buffer_destroy(cmd_buffer);
2518 }
2519 }
2520
2521 void radv_CmdBeginRenderPass(
2522 VkCommandBuffer commandBuffer,
2523 const VkRenderPassBeginInfo* pRenderPassBegin,
2524 VkSubpassContents contents)
2525 {
2526 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2527 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2528 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2529
2530 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2531 cmd_buffer->cs, 2048);
2532
2533 cmd_buffer->state.framebuffer = framebuffer;
2534 cmd_buffer->state.pass = pass;
2535 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2536 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2537
2538 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2539 assert(cmd_buffer->cs->cdw <= cdw_max);
2540
2541 radv_cmd_buffer_clear_subpass(cmd_buffer);
2542 }
2543
2544 void radv_CmdNextSubpass(
2545 VkCommandBuffer commandBuffer,
2546 VkSubpassContents contents)
2547 {
2548 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2549
2550 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2551
2552 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2553 2048);
2554
2555 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2556 radv_cmd_buffer_clear_subpass(cmd_buffer);
2557 }
2558
2559 void radv_CmdDraw(
2560 VkCommandBuffer commandBuffer,
2561 uint32_t vertexCount,
2562 uint32_t instanceCount,
2563 uint32_t firstVertex,
2564 uint32_t firstInstance)
2565 {
2566 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2567
2568 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2569
2570 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2571
2572 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2573 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2574 if (loc->sgpr_idx != -1) {
2575 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2576 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2577 int vs_num = 2;
2578 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2579 vs_num = 3;
2580
2581 assert (loc->num_sgprs == vs_num);
2582 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
2583 radeon_emit(cmd_buffer->cs, firstVertex);
2584 radeon_emit(cmd_buffer->cs, firstInstance);
2585 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2586 radeon_emit(cmd_buffer->cs, 0);
2587 }
2588 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2589 radeon_emit(cmd_buffer->cs, instanceCount);
2590
2591 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2592 radeon_emit(cmd_buffer->cs, vertexCount);
2593 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2594 S_0287F0_USE_OPAQUE(0));
2595
2596 assert(cmd_buffer->cs->cdw <= cdw_max);
2597
2598 radv_cmd_buffer_trace_emit(cmd_buffer);
2599 }
2600
2601 void radv_CmdDrawIndexed(
2602 VkCommandBuffer commandBuffer,
2603 uint32_t indexCount,
2604 uint32_t instanceCount,
2605 uint32_t firstIndex,
2606 int32_t vertexOffset,
2607 uint32_t firstInstance)
2608 {
2609 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2610 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2611 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2612 uint64_t index_va;
2613
2614 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2615
2616 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2617
2618 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2619 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2620
2621 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2622 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2623 if (loc->sgpr_idx != -1) {
2624 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2625 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2626 int vs_num = 2;
2627 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2628 vs_num = 3;
2629
2630 assert (loc->num_sgprs == vs_num);
2631 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
2632 radeon_emit(cmd_buffer->cs, vertexOffset);
2633 radeon_emit(cmd_buffer->cs, firstInstance);
2634 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2635 radeon_emit(cmd_buffer->cs, 0);
2636 }
2637 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2638 radeon_emit(cmd_buffer->cs, instanceCount);
2639
2640 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2641 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2642 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2643 radeon_emit(cmd_buffer->cs, index_max_size);
2644 radeon_emit(cmd_buffer->cs, index_va);
2645 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2646 radeon_emit(cmd_buffer->cs, indexCount);
2647 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2648
2649 assert(cmd_buffer->cs->cdw <= cdw_max);
2650 radv_cmd_buffer_trace_emit(cmd_buffer);
2651 }
2652
2653 static void
2654 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2655 VkBuffer _buffer,
2656 VkDeviceSize offset,
2657 VkBuffer _count_buffer,
2658 VkDeviceSize count_offset,
2659 uint32_t draw_count,
2660 uint32_t stride,
2661 bool indexed)
2662 {
2663 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2664 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2665 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2666 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2667 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2668 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2669 indirect_va += offset + buffer->offset;
2670 uint64_t count_va = 0;
2671
2672 if (count_buffer) {
2673 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2674 count_va += count_offset + count_buffer->offset;
2675 }
2676
2677 if (!draw_count)
2678 return;
2679
2680 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2681
2682 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2683 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2684 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2685 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2686 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2687 assert(loc->sgpr_idx != -1);
2688 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2689 radeon_emit(cs, 1);
2690 radeon_emit(cs, indirect_va);
2691 radeon_emit(cs, indirect_va >> 32);
2692
2693 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2694 PKT3_DRAW_INDIRECT_MULTI,
2695 8, false));
2696 radeon_emit(cs, 0);
2697 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2698 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2699 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2700 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2701 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2702 radeon_emit(cs, draw_count); /* count */
2703 radeon_emit(cs, count_va); /* count_addr */
2704 radeon_emit(cs, count_va >> 32);
2705 radeon_emit(cs, stride); /* stride */
2706 radeon_emit(cs, di_src_sel);
2707 radv_cmd_buffer_trace_emit(cmd_buffer);
2708 }
2709
2710 static void
2711 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2712 VkBuffer buffer,
2713 VkDeviceSize offset,
2714 VkBuffer countBuffer,
2715 VkDeviceSize countBufferOffset,
2716 uint32_t maxDrawCount,
2717 uint32_t stride)
2718 {
2719 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2720 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2721
2722 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2723 cmd_buffer->cs, 14);
2724
2725 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2726 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2727
2728 assert(cmd_buffer->cs->cdw <= cdw_max);
2729 }
2730
2731 static void
2732 radv_cmd_draw_indexed_indirect_count(
2733 VkCommandBuffer commandBuffer,
2734 VkBuffer buffer,
2735 VkDeviceSize offset,
2736 VkBuffer countBuffer,
2737 VkDeviceSize countBufferOffset,
2738 uint32_t maxDrawCount,
2739 uint32_t stride)
2740 {
2741 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2742 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2743 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2744 uint64_t index_va;
2745 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2746
2747 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2748 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2749
2750 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2751
2752 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2753 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2754
2755 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2756 radeon_emit(cmd_buffer->cs, index_va);
2757 radeon_emit(cmd_buffer->cs, index_va >> 32);
2758
2759 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2760 radeon_emit(cmd_buffer->cs, index_max_size);
2761
2762 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2763 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2764
2765 assert(cmd_buffer->cs->cdw <= cdw_max);
2766 }
2767
2768 void radv_CmdDrawIndirect(
2769 VkCommandBuffer commandBuffer,
2770 VkBuffer buffer,
2771 VkDeviceSize offset,
2772 uint32_t drawCount,
2773 uint32_t stride)
2774 {
2775 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2776 VK_NULL_HANDLE, 0, drawCount, stride);
2777 }
2778
2779 void radv_CmdDrawIndexedIndirect(
2780 VkCommandBuffer commandBuffer,
2781 VkBuffer buffer,
2782 VkDeviceSize offset,
2783 uint32_t drawCount,
2784 uint32_t stride)
2785 {
2786 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2787 VK_NULL_HANDLE, 0, drawCount, stride);
2788 }
2789
2790 void radv_CmdDrawIndirectCountAMD(
2791 VkCommandBuffer commandBuffer,
2792 VkBuffer buffer,
2793 VkDeviceSize offset,
2794 VkBuffer countBuffer,
2795 VkDeviceSize countBufferOffset,
2796 uint32_t maxDrawCount,
2797 uint32_t stride)
2798 {
2799 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2800 countBuffer, countBufferOffset,
2801 maxDrawCount, stride);
2802 }
2803
2804 void radv_CmdDrawIndexedIndirectCountAMD(
2805 VkCommandBuffer commandBuffer,
2806 VkBuffer buffer,
2807 VkDeviceSize offset,
2808 VkBuffer countBuffer,
2809 VkDeviceSize countBufferOffset,
2810 uint32_t maxDrawCount,
2811 uint32_t stride)
2812 {
2813 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2814 countBuffer, countBufferOffset,
2815 maxDrawCount, stride);
2816 }
2817
2818 static void
2819 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2820 {
2821 radv_emit_compute_pipeline(cmd_buffer);
2822 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2823 VK_SHADER_STAGE_COMPUTE_BIT);
2824 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2825 VK_SHADER_STAGE_COMPUTE_BIT);
2826 si_emit_cache_flush(cmd_buffer);
2827 }
2828
2829 void radv_CmdDispatch(
2830 VkCommandBuffer commandBuffer,
2831 uint32_t x,
2832 uint32_t y,
2833 uint32_t z)
2834 {
2835 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2836
2837 radv_flush_compute_state(cmd_buffer);
2838
2839 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2840
2841 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2842 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2843 if (loc->sgpr_idx != -1) {
2844 assert(!loc->indirect);
2845 uint8_t grid_used = cmd_buffer->state.pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2846 assert(loc->num_sgprs == grid_used);
2847 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2848 radeon_emit(cmd_buffer->cs, x);
2849 if (grid_used > 1)
2850 radeon_emit(cmd_buffer->cs, y);
2851 if (grid_used > 2)
2852 radeon_emit(cmd_buffer->cs, z);
2853 }
2854
2855 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2856 PKT3_SHADER_TYPE_S(1));
2857 radeon_emit(cmd_buffer->cs, x);
2858 radeon_emit(cmd_buffer->cs, y);
2859 radeon_emit(cmd_buffer->cs, z);
2860 radeon_emit(cmd_buffer->cs, 1);
2861
2862 assert(cmd_buffer->cs->cdw <= cdw_max);
2863 radv_cmd_buffer_trace_emit(cmd_buffer);
2864 }
2865
2866 void radv_CmdDispatchIndirect(
2867 VkCommandBuffer commandBuffer,
2868 VkBuffer _buffer,
2869 VkDeviceSize offset)
2870 {
2871 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2872 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2873 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2874 va += buffer->offset + offset;
2875
2876 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2877
2878 radv_flush_compute_state(cmd_buffer);
2879
2880 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2881 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2882 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2883 if (loc->sgpr_idx != -1) {
2884 uint8_t grid_used = cmd_buffer->state.pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2885 for (unsigned i = 0; i < grid_used; ++i) {
2886 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2887 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2888 COPY_DATA_DST_SEL(COPY_DATA_REG));
2889 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2890 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2891 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2892 radeon_emit(cmd_buffer->cs, 0);
2893 }
2894 }
2895
2896 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2897 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2898 PKT3_SHADER_TYPE_S(1));
2899 radeon_emit(cmd_buffer->cs, va);
2900 radeon_emit(cmd_buffer->cs, va >> 32);
2901 radeon_emit(cmd_buffer->cs, 1);
2902 } else {
2903 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2904 PKT3_SHADER_TYPE_S(1));
2905 radeon_emit(cmd_buffer->cs, 1);
2906 radeon_emit(cmd_buffer->cs, va);
2907 radeon_emit(cmd_buffer->cs, va >> 32);
2908
2909 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2910 PKT3_SHADER_TYPE_S(1));
2911 radeon_emit(cmd_buffer->cs, 0);
2912 radeon_emit(cmd_buffer->cs, 1);
2913 }
2914
2915 assert(cmd_buffer->cs->cdw <= cdw_max);
2916 radv_cmd_buffer_trace_emit(cmd_buffer);
2917 }
2918
2919 void radv_unaligned_dispatch(
2920 struct radv_cmd_buffer *cmd_buffer,
2921 uint32_t x,
2922 uint32_t y,
2923 uint32_t z)
2924 {
2925 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2926 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2927 uint32_t blocks[3], remainder[3];
2928
2929 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2930 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2931 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2932
2933 /* If aligned, these should be an entire block size, not 0 */
2934 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2935 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2936 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2937
2938 radv_flush_compute_state(cmd_buffer);
2939
2940 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2941
2942 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2943 radeon_emit(cmd_buffer->cs,
2944 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2945 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2946 radeon_emit(cmd_buffer->cs,
2947 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2948 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2949 radeon_emit(cmd_buffer->cs,
2950 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2951 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2952
2953 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2954 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2955 if (loc->sgpr_idx != -1) {
2956 uint8_t grid_used = cmd_buffer->state.pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2957 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2958 radeon_emit(cmd_buffer->cs, blocks[0]);
2959 if (grid_used > 1)
2960 radeon_emit(cmd_buffer->cs, blocks[1]);
2961 if (grid_used > 2)
2962 radeon_emit(cmd_buffer->cs, blocks[2]);
2963 }
2964 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2965 PKT3_SHADER_TYPE_S(1));
2966 radeon_emit(cmd_buffer->cs, blocks[0]);
2967 radeon_emit(cmd_buffer->cs, blocks[1]);
2968 radeon_emit(cmd_buffer->cs, blocks[2]);
2969 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2970 S_00B800_PARTIAL_TG_EN(1));
2971
2972 assert(cmd_buffer->cs->cdw <= cdw_max);
2973 radv_cmd_buffer_trace_emit(cmd_buffer);
2974 }
2975
2976 void radv_CmdEndRenderPass(
2977 VkCommandBuffer commandBuffer)
2978 {
2979 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2980
2981 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2982
2983 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2984
2985 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2986 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2987 radv_handle_subpass_image_transition(cmd_buffer,
2988 (VkAttachmentReference){i, layout});
2989 }
2990
2991 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2992
2993 cmd_buffer->state.pass = NULL;
2994 cmd_buffer->state.subpass = NULL;
2995 cmd_buffer->state.attachments = NULL;
2996 cmd_buffer->state.framebuffer = NULL;
2997 }
2998
2999
3000 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3001 struct radv_image *image,
3002 const VkImageSubresourceRange *range)
3003 {
3004 assert(range->baseMipLevel == 0);
3005 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3006 unsigned layer_count = radv_get_layerCount(image, range);
3007 uint64_t size = image->surface.htile_slice_size * layer_count;
3008 uint64_t offset = image->offset + image->htile_offset +
3009 image->surface.htile_slice_size * range->baseArrayLayer;
3010
3011 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3012 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3013
3014 radv_fill_buffer(cmd_buffer, image->bo, offset, size, 0xffffffff);
3015
3016 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3017 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3018 RADV_CMD_FLAG_INV_VMEM_L1 |
3019 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3020 }
3021
3022 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3023 struct radv_image *image,
3024 VkImageLayout src_layout,
3025 VkImageLayout dst_layout,
3026 const VkImageSubresourceRange *range,
3027 VkImageAspectFlags pending_clears)
3028 {
3029 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3030 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3031 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3032 cmd_buffer->state.render_area.extent.width == image->extent.width &&
3033 cmd_buffer->state.render_area.extent.height == image->extent.height) {
3034 /* The clear will initialize htile. */
3035 return;
3036 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3037 radv_layout_has_htile(image, dst_layout)) {
3038 /* TODO: merge with the clear if applicable */
3039 radv_initialize_htile(cmd_buffer, image, range);
3040 } else if (!radv_layout_has_htile(image, src_layout) &&
3041 radv_layout_has_htile(image, dst_layout)) {
3042 radv_initialize_htile(cmd_buffer, image, range);
3043 } else if ((radv_layout_has_htile(image, src_layout) &&
3044 !radv_layout_has_htile(image, dst_layout)) ||
3045 (radv_layout_is_htile_compressed(image, src_layout) &&
3046 !radv_layout_is_htile_compressed(image, dst_layout))) {
3047 VkImageSubresourceRange local_range = *range;
3048 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3049 local_range.baseMipLevel = 0;
3050 local_range.levelCount = 1;
3051
3052 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3053 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3054
3055 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3056
3057 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3058 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3059 }
3060 }
3061
3062 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3063 struct radv_image *image, uint32_t value)
3064 {
3065 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3066 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3067
3068 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3069 image->cmask.size, value);
3070
3071 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3072 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3073 RADV_CMD_FLAG_INV_VMEM_L1 |
3074 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3075 }
3076
3077 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3078 struct radv_image *image,
3079 VkImageLayout src_layout,
3080 VkImageLayout dst_layout,
3081 unsigned src_queue_mask,
3082 unsigned dst_queue_mask,
3083 const VkImageSubresourceRange *range,
3084 VkImageAspectFlags pending_clears)
3085 {
3086 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3087 if (image->fmask.size)
3088 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3089 else
3090 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3091 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3092 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3093 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3094 }
3095 }
3096
3097 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3098 struct radv_image *image, uint32_t value)
3099 {
3100
3101 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3102 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3103
3104 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3105 image->surface.dcc_size, value);
3106
3107 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3108 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3109 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3110 RADV_CMD_FLAG_INV_VMEM_L1 |
3111 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3112 }
3113
3114 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3115 struct radv_image *image,
3116 VkImageLayout src_layout,
3117 VkImageLayout dst_layout,
3118 unsigned src_queue_mask,
3119 unsigned dst_queue_mask,
3120 const VkImageSubresourceRange *range,
3121 VkImageAspectFlags pending_clears)
3122 {
3123 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3124 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3125 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3126 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3127 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3128 }
3129 }
3130
3131 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3132 struct radv_image *image,
3133 VkImageLayout src_layout,
3134 VkImageLayout dst_layout,
3135 uint32_t src_family,
3136 uint32_t dst_family,
3137 const VkImageSubresourceRange *range,
3138 VkImageAspectFlags pending_clears)
3139 {
3140 if (image->exclusive && src_family != dst_family) {
3141 /* This is an acquire or a release operation and there will be
3142 * a corresponding release/acquire. Do the transition in the
3143 * most flexible queue. */
3144
3145 assert(src_family == cmd_buffer->queue_family_index ||
3146 dst_family == cmd_buffer->queue_family_index);
3147
3148 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3149 return;
3150
3151 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3152 (src_family == RADV_QUEUE_GENERAL ||
3153 dst_family == RADV_QUEUE_GENERAL))
3154 return;
3155 }
3156
3157 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3158 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3159
3160 if (image->surface.htile_size)
3161 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3162 dst_layout, range, pending_clears);
3163
3164 if (image->cmask.size)
3165 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3166 dst_layout, src_queue_mask,
3167 dst_queue_mask, range,
3168 pending_clears);
3169
3170 if (image->surface.dcc_size)
3171 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3172 dst_layout, src_queue_mask,
3173 dst_queue_mask, range,
3174 pending_clears);
3175 }
3176
3177 void radv_CmdPipelineBarrier(
3178 VkCommandBuffer commandBuffer,
3179 VkPipelineStageFlags srcStageMask,
3180 VkPipelineStageFlags destStageMask,
3181 VkBool32 byRegion,
3182 uint32_t memoryBarrierCount,
3183 const VkMemoryBarrier* pMemoryBarriers,
3184 uint32_t bufferMemoryBarrierCount,
3185 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3186 uint32_t imageMemoryBarrierCount,
3187 const VkImageMemoryBarrier* pImageMemoryBarriers)
3188 {
3189 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3190 enum radv_cmd_flush_bits src_flush_bits = 0;
3191 enum radv_cmd_flush_bits dst_flush_bits = 0;
3192
3193 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3194 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3195 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3196 NULL);
3197 }
3198
3199 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3200 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3201 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3202 NULL);
3203 }
3204
3205 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3206 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3207 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3208 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3209 image);
3210 }
3211
3212 radv_stage_flush(cmd_buffer, srcStageMask);
3213 cmd_buffer->state.flush_bits |= src_flush_bits;
3214
3215 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3216 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3217 radv_handle_image_transition(cmd_buffer, image,
3218 pImageMemoryBarriers[i].oldLayout,
3219 pImageMemoryBarriers[i].newLayout,
3220 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3221 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3222 &pImageMemoryBarriers[i].subresourceRange,
3223 0);
3224 }
3225
3226 cmd_buffer->state.flush_bits |= dst_flush_bits;
3227 }
3228
3229
3230 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3231 struct radv_event *event,
3232 VkPipelineStageFlags stageMask,
3233 unsigned value)
3234 {
3235 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3236 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3237
3238 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3239
3240 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
3241
3242 /* TODO: this is overkill. Probably should figure something out from
3243 * the stage mask. */
3244
3245 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
3246 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
3247 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
3248 EVENT_INDEX(5));
3249 radeon_emit(cs, va);
3250 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
3251 radeon_emit(cs, 2);
3252 radeon_emit(cs, 0);
3253 }
3254
3255 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
3256 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
3257 EVENT_INDEX(5));
3258 radeon_emit(cs, va);
3259 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
3260 radeon_emit(cs, value);
3261 radeon_emit(cs, 0);
3262
3263 assert(cmd_buffer->cs->cdw <= cdw_max);
3264 }
3265
3266 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3267 VkEvent _event,
3268 VkPipelineStageFlags stageMask)
3269 {
3270 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3271 RADV_FROM_HANDLE(radv_event, event, _event);
3272
3273 write_event(cmd_buffer, event, stageMask, 1);
3274 }
3275
3276 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3277 VkEvent _event,
3278 VkPipelineStageFlags stageMask)
3279 {
3280 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3281 RADV_FROM_HANDLE(radv_event, event, _event);
3282
3283 write_event(cmd_buffer, event, stageMask, 0);
3284 }
3285
3286 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3287 uint32_t eventCount,
3288 const VkEvent* pEvents,
3289 VkPipelineStageFlags srcStageMask,
3290 VkPipelineStageFlags dstStageMask,
3291 uint32_t memoryBarrierCount,
3292 const VkMemoryBarrier* pMemoryBarriers,
3293 uint32_t bufferMemoryBarrierCount,
3294 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3295 uint32_t imageMemoryBarrierCount,
3296 const VkImageMemoryBarrier* pImageMemoryBarriers)
3297 {
3298 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3299 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3300
3301 for (unsigned i = 0; i < eventCount; ++i) {
3302 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3303 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3304
3305 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3306
3307 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3308
3309 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
3310 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
3311 radeon_emit(cs, va);
3312 radeon_emit(cs, va >> 32);
3313 radeon_emit(cs, 1); /* reference value */
3314 radeon_emit(cs, 0xffffffff); /* mask */
3315 radeon_emit(cs, 4); /* poll interval */
3316
3317 assert(cmd_buffer->cs->cdw <= cdw_max);
3318 }
3319
3320
3321 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3322 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3323
3324 radv_handle_image_transition(cmd_buffer, image,
3325 pImageMemoryBarriers[i].oldLayout,
3326 pImageMemoryBarriers[i].newLayout,
3327 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3328 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3329 &pImageMemoryBarriers[i].subresourceRange,
3330 0);
3331 }
3332
3333 /* TODO: figure out how to do memory barriers without waiting */
3334 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3335 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3336 RADV_CMD_FLAG_INV_VMEM_L1 |
3337 RADV_CMD_FLAG_INV_SMEM_L1;
3338 }