projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: refactor out the constant setting user sgpr code.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
36 struct radv_image *image,
37 VkImageLayout src_layout,
38 VkImageLayout dst_layout,
39 VkImageSubresourceRange range,
40 VkImageAspectFlags pending_clears);
41
42 const struct radv_dynamic_state default_dynamic_state = {
43 .viewport = {
44 .count = 0,
45 },
46 .scissor = {
47 .count = 0,
48 },
49 .line_width = 1.0f,
50 .depth_bias = {
51 .bias = 0.0f,
52 .clamp = 0.0f,
53 .slope = 0.0f,
54 },
55 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
56 .depth_bounds = {
57 .min = 0.0f,
58 .max = 1.0f,
59 },
60 .stencil_compare_mask = {
61 .front = ~0u,
62 .back = ~0u,
63 },
64 .stencil_write_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_reference = {
69 .front = 0u,
70 .back = 0u,
71 },
72 };
73
74 void
75 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
76 const struct radv_dynamic_state *src,
77 uint32_t copy_mask)
78 {
79 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
80 dest->viewport.count = src->viewport.count;
81 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
82 src->viewport.count);
83 }
84
85 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
86 dest->scissor.count = src->scissor.count;
87 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
88 src->scissor.count);
89 }
90
91 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
92 dest->line_width = src->line_width;
93
94 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
95 dest->depth_bias = src->depth_bias;
96
97 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
98 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
99
100 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
101 dest->depth_bounds = src->depth_bounds;
102
103 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
104 dest->stencil_compare_mask = src->stencil_compare_mask;
105
106 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
107 dest->stencil_write_mask = src->stencil_write_mask;
108
109 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
110 dest->stencil_reference = src->stencil_reference;
111 }
112
113 static VkResult radv_create_cmd_buffer(
114 struct radv_device * device,
115 struct radv_cmd_pool * pool,
116 VkCommandBufferLevel level,
117 VkCommandBuffer* pCommandBuffer)
118 {
119 struct radv_cmd_buffer *cmd_buffer;
120 VkResult result;
121
122 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
123 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
124 if (cmd_buffer == NULL)
125 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
126
127 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
128 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
129 cmd_buffer->device = device;
130 cmd_buffer->pool = pool;
131 cmd_buffer->level = level;
132
133 if (pool) {
134 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
135 } else {
136 /* Init the pool_link so we can safefly call list_del when we destroy
137 * the command buffer
138 */
139 list_inithead(&cmd_buffer->pool_link);
140 }
141
142 cmd_buffer->cs = device->ws->cs_create(device->ws, RING_GFX);
143 if (!cmd_buffer->cs) {
144 result = VK_ERROR_OUT_OF_HOST_MEMORY;
145 goto fail;
146 }
147
148 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
149
150 cmd_buffer->upload.offset = 0;
151 cmd_buffer->upload.size = 0;
152 list_inithead(&cmd_buffer->upload.list);
153
154 return VK_SUCCESS;
155
156 fail:
157 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
158
159 return result;
160 }
161
162 static bool
163 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
164 uint64_t min_needed)
165 {
166 uint64_t new_size;
167 struct radeon_winsys_bo *bo;
168 struct radv_cmd_buffer_upload *upload;
169 struct radv_device *device = cmd_buffer->device;
170
171 new_size = MAX2(min_needed, 16 * 1024);
172 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
173
174 bo = device->ws->buffer_create(device->ws,
175 new_size, 4096,
176 RADEON_DOMAIN_GTT,
177 RADEON_FLAG_CPU_ACCESS);
178
179 if (!bo) {
180 cmd_buffer->record_fail = true;
181 return false;
182 }
183
184 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
185 if (cmd_buffer->upload.upload_bo) {
186 upload = malloc(sizeof(*upload));
187
188 if (!upload) {
189 cmd_buffer->record_fail = true;
190 device->ws->buffer_destroy(bo);
191 return false;
192 }
193
194 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
195 list_add(&upload->list, &cmd_buffer->upload.list);
196 }
197
198 cmd_buffer->upload.upload_bo = bo;
199 cmd_buffer->upload.size = new_size;
200 cmd_buffer->upload.offset = 0;
201 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
202
203 if (!cmd_buffer->upload.map) {
204 cmd_buffer->record_fail = true;
205 return false;
206 }
207
208 return true;
209 }
210
211 bool
212 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
213 unsigned size,
214 unsigned alignment,
215 unsigned *out_offset,
216 void **ptr)
217 {
218 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
219 if (offset + size > cmd_buffer->upload.size) {
220 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
221 return false;
222 offset = 0;
223 }
224
225 *out_offset = offset;
226 *ptr = cmd_buffer->upload.map + offset;
227
228 cmd_buffer->upload.offset = offset + size;
229 return true;
230 }
231
232 bool
233 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
234 unsigned size, unsigned alignment,
235 const void *data, unsigned *out_offset)
236 {
237 uint8_t *ptr;
238
239 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
240 out_offset, (void **)&ptr))
241 return false;
242
243 if (ptr)
244 memcpy(ptr, data, size);
245
246 return true;
247 }
248
249 static void
250 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
251 struct radv_pipeline *pipeline)
252 {
253 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
254 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
255 8);
256 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
257 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
258 }
259
260 static void
261 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
262 struct radv_pipeline *pipeline)
263 {
264 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
265 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
266 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
267
268 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
269 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
270 }
271
272 /* 12.4 fixed-point */
273 static unsigned radv_pack_float_12p4(float x)
274 {
275 return x <= 0 ? 0 :
276 x >= 4096 ? 0xffff : x * 16;
277 }
278
279 static void
280 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
281 struct radv_pipeline *pipeline)
282 {
283 int num_samples = pipeline->graphics.ms.num_samples;
284 struct radv_multisample_state *ms = &pipeline->graphics.ms;
285 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
286
287 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
288 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
289 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
290
291 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
292 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
293
294 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
295 return;
296
297 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
298 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
299 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
300
301 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
302
303 uint32_t samples_offset;
304 void *samples_ptr;
305 void *src;
306 radv_cmd_buffer_upload_alloc(cmd_buffer, num_samples * 4 * 2, 256, &samples_offset,
307 &samples_ptr);
308 switch (num_samples) {
309 case 1:
310 src = cmd_buffer->device->sample_locations_1x;
311 break;
312 case 2:
313 src = cmd_buffer->device->sample_locations_2x;
314 break;
315 case 4:
316 src = cmd_buffer->device->sample_locations_4x;
317 break;
318 case 8:
319 src = cmd_buffer->device->sample_locations_8x;
320 break;
321 case 16:
322 src = cmd_buffer->device->sample_locations_16x;
323 break;
324 }
325 memcpy(samples_ptr, src, num_samples * 4 * 2);
326
327 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
328 va += samples_offset;
329
330 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B030_SPI_SHADER_USER_DATA_PS_0 + AC_USERDATA_PS_SAMPLE_POS * 4, 2);
331 radeon_emit(cmd_buffer->cs, va);
332 radeon_emit(cmd_buffer->cs, va >> 32);
333 }
334
335 static void
336 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
337 struct radv_pipeline *pipeline)
338 {
339 struct radv_raster_state *raster = &pipeline->graphics.raster;
340
341 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
342 raster->pa_cl_clip_cntl);
343
344 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
345 raster->spi_interp_control);
346
347 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
348 radeon_emit(cmd_buffer->cs, 0);
349 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
350 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
351
352 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
353 raster->pa_su_vtx_cntl);
354
355 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
356 raster->pa_su_sc_mode_cntl);
357 }
358
359 static void
360 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
361 struct radv_pipeline *pipeline)
362 {
363 struct radeon_winsys *ws = cmd_buffer->device->ws;
364 struct radv_shader_variant *vs;
365 uint64_t va;
366 unsigned export_count;
367 unsigned clip_dist_mask, cull_dist_mask, total_mask;
368
369 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
370
371 vs = pipeline->shaders[MESA_SHADER_VERTEX];
372 va = ws->buffer_get_va(vs->bo);
373 ws->cs_add_buffer(cmd_buffer->cs, vs->bo, 8);
374
375 clip_dist_mask = vs->info.vs.clip_dist_mask;
376 cull_dist_mask = vs->info.vs.cull_dist_mask;
377 total_mask = clip_dist_mask | cull_dist_mask;
378 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, 0);
379 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
380
381 export_count = MAX2(1, vs->info.vs.param_exports);
382 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
383 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
384 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
385 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
386 S_02870C_POS1_EXPORT_FORMAT(vs->info.vs.pos_exports > 1 ?
387 V_02870C_SPI_SHADER_4COMP :
388 V_02870C_SPI_SHADER_NONE) |
389 S_02870C_POS2_EXPORT_FORMAT(vs->info.vs.pos_exports > 2 ?
390 V_02870C_SPI_SHADER_4COMP :
391 V_02870C_SPI_SHADER_NONE) |
392 S_02870C_POS3_EXPORT_FORMAT(vs->info.vs.pos_exports > 3 ?
393 V_02870C_SPI_SHADER_4COMP :
394 V_02870C_SPI_SHADER_NONE));
395
396 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
397 radeon_emit(cmd_buffer->cs, va >> 8);
398 radeon_emit(cmd_buffer->cs, va >> 40);
399 radeon_emit(cmd_buffer->cs, vs->rsrc1);
400 radeon_emit(cmd_buffer->cs, vs->rsrc2);
401
402 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
403 S_028818_VTX_W0_FMT(1) |
404 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
405 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
406 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
407
408 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
409 S_02881C_USE_VTX_POINT_SIZE(vs->info.vs.writes_pointsize) |
410 S_02881C_VS_OUT_MISC_VEC_ENA(vs->info.vs.writes_pointsize) |
411 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
412 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
413 pipeline->graphics.raster.pa_cl_vs_out_cntl |
414 cull_dist_mask << 8 |
415 clip_dist_mask);
416
417 }
418
419
420
421 static void
422 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
423 struct radv_pipeline *pipeline)
424 {
425 struct radeon_winsys *ws = cmd_buffer->device->ws;
426 struct radv_shader_variant *ps, *vs;
427 uint64_t va;
428 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
429 struct radv_blend_state *blend = &pipeline->graphics.blend;
430 unsigned ps_offset = 0;
431 unsigned z_order;
432 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
433
434 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
435 vs = pipeline->shaders[MESA_SHADER_VERTEX];
436 va = ws->buffer_get_va(ps->bo);
437 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
438
439 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
440 radeon_emit(cmd_buffer->cs, va >> 8);
441 radeon_emit(cmd_buffer->cs, va >> 40);
442 radeon_emit(cmd_buffer->cs, ps->rsrc1);
443 radeon_emit(cmd_buffer->cs, ps->rsrc2);
444
445 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
446 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
447 else
448 z_order = V_02880C_LATE_Z;
449
450
451 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
452 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
453 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
454 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
455 S_02880C_Z_ORDER(z_order) |
456 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
457 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
458 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory));
459
460 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
461 ps->config.spi_ps_input_ena);
462
463 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
464 ps->config.spi_ps_input_addr);
465
466 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(0);
467 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
468 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
469
470 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
471
472 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
473 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
474 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
475 V_028710_SPI_SHADER_ZERO);
476
477 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
478
479 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
480 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
481
482 if (ps->info.fs.has_pcoord) {
483 unsigned val;
484 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
485 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
486 ps_offset = 1;
487 }
488
489 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
490 unsigned vs_offset, flat_shade;
491 unsigned val;
492
493 if (!(ps->info.fs.input_mask & (1u << i)))
494 continue;
495
496
497 if (!(vs->info.vs.export_mask & (1u << i))) {
498 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset,
499 S_028644_OFFSET(0x20));
500 ++ps_offset;
501 continue;
502 }
503
504 vs_offset = util_bitcount(vs->info.vs.export_mask & ((1u << i) - 1));
505 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
506
507 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
508 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
509 ++ps_offset;
510 }
511 }
512
513 static void
514 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
515 struct radv_pipeline *pipeline)
516 {
517 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
518 return;
519
520 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
521 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
522 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
523 radv_update_multisample_state(cmd_buffer, pipeline);
524 radv_emit_vertex_shader(cmd_buffer, pipeline);
525 radv_emit_fragment_shader(cmd_buffer, pipeline);
526
527 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
528 pipeline->graphics.prim_restart_enable);
529
530 cmd_buffer->state.emitted_pipeline = pipeline;
531 }
532
533 static void
534 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
535 {
536 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
537 cmd_buffer->state.dynamic.viewport.viewports);
538 }
539
540 static void
541 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
542 {
543 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
544 si_write_scissors(cmd_buffer->cs, 0, count,
545 cmd_buffer->state.dynamic.scissor.scissors);
546 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
547 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
548 }
549
550 static void
551 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
552 int index,
553 struct radv_color_buffer_info *cb)
554 {
555 bool is_vi = cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= VI;
556 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
557 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
558 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
559 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
560 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
561 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
562 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
563 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
564 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
565 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
566 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
567 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
568
569 if (is_vi) { /* DCC BASE */
570 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
571 }
572 }
573
574 static void
575 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
576 struct radv_ds_buffer_info *ds,
577 struct radv_image *image,
578 VkImageLayout layout)
579 {
580 uint32_t db_z_info = ds->db_z_info;
581
582 if (!radv_layout_has_htile(image, layout))
583 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
584
585 if (!radv_layout_can_expclear(image, layout))
586 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
587
588 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
589 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
590
591 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
592 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
593 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
594 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
595 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
596 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
597 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
598 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
599 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
600 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
601
602 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
603 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
604 ds->pa_su_poly_offset_db_fmt_cntl);
605 }
606
607 /*
608 * To hw resolve multisample images both src and dst need to have the same
609 * micro tiling mode. However we don't always know in advance when creating
610 * the images. This function gets called if we have a resolve attachment,
611 * and tests if the attachment image has the same tiling mode, then it
612 * checks if the generated framebuffer data has the same tiling mode, and
613 * updates it if not.
614 */
615 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
616 struct radv_attachment_info *att,
617 uint32_t micro_tile_mode)
618 {
619 struct radv_image *image = att->attachment->image;
620 uint32_t tile_mode_index;
621 if (image->surface.nsamples <= 1)
622 return;
623
624 if (image->surface.micro_tile_mode != micro_tile_mode) {
625 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
626 }
627
628 if (att->cb.micro_tile_mode != micro_tile_mode) {
629 tile_mode_index = image->surface.tiling_index[0];
630
631 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
632 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
633 att->cb.micro_tile_mode = micro_tile_mode;
634 }
635 }
636
637 void
638 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
639 struct radv_image *image,
640 VkClearDepthStencilValue ds_clear_value,
641 VkImageAspectFlags aspects)
642 {
643 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
644 va += image->offset + image->clear_value_offset;
645 unsigned reg_offset = 0, reg_count = 0;
646
647 if (!image->htile.size || !aspects)
648 return;
649
650 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
651 ++reg_count;
652 } else {
653 ++reg_offset;
654 va += 4;
655 }
656 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
657 ++reg_count;
658
659 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
660
661 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
662 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
663 S_370_WR_CONFIRM(1) |
664 S_370_ENGINE_SEL(V_370_PFP));
665 radeon_emit(cmd_buffer->cs, va);
666 radeon_emit(cmd_buffer->cs, va >> 32);
667 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
668 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
669 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
670 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
671
672 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
673 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
674 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
675 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
676 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
677 }
678
679 static void
680 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
681 struct radv_image *image)
682 {
683 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
684 va += image->offset + image->clear_value_offset;
685
686 if (!image->htile.size)
687 return;
688
689 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
690
691 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
692 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
693 COPY_DATA_DST_SEL(COPY_DATA_REG) |
694 COPY_DATA_COUNT_SEL);
695 radeon_emit(cmd_buffer->cs, va);
696 radeon_emit(cmd_buffer->cs, va >> 32);
697 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
698 radeon_emit(cmd_buffer->cs, 0);
699
700 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
701 radeon_emit(cmd_buffer->cs, 0);
702 }
703
704 void
705 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
706 struct radv_image *image,
707 int idx,
708 uint32_t color_values[2])
709 {
710 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
711 va += image->offset + image->clear_value_offset;
712
713 if (!image->cmask.size && !image->surface.dcc_size)
714 return;
715
716 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
717
718 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
719 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
720 S_370_WR_CONFIRM(1) |
721 S_370_ENGINE_SEL(V_370_PFP));
722 radeon_emit(cmd_buffer->cs, va);
723 radeon_emit(cmd_buffer->cs, va >> 32);
724 radeon_emit(cmd_buffer->cs, color_values[0]);
725 radeon_emit(cmd_buffer->cs, color_values[1]);
726
727 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
728 radeon_emit(cmd_buffer->cs, color_values[0]);
729 radeon_emit(cmd_buffer->cs, color_values[1]);
730 }
731
732 static void
733 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
734 struct radv_image *image,
735 int idx)
736 {
737 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
738 va += image->offset + image->clear_value_offset;
739
740 if (!image->cmask.size && !image->surface.dcc_size)
741 return;
742
743 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
744 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
745
746 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
747 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
748 COPY_DATA_DST_SEL(COPY_DATA_REG) |
749 COPY_DATA_COUNT_SEL);
750 radeon_emit(cmd_buffer->cs, va);
751 radeon_emit(cmd_buffer->cs, va >> 32);
752 radeon_emit(cmd_buffer->cs, reg >> 2);
753 radeon_emit(cmd_buffer->cs, 0);
754
755 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
756 radeon_emit(cmd_buffer->cs, 0);
757 }
758
759 void
760 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
761 {
762 int i;
763 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
764 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
765 int dst_resolve_micro_tile_mode = -1;
766
767 if (subpass->has_resolve) {
768 uint32_t a = subpass->resolve_attachments[0].attachment;
769 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
770 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
771 }
772 for (i = 0; i < subpass->color_count; ++i) {
773 int idx = subpass->color_attachments[i].attachment;
774 struct radv_attachment_info *att = &framebuffer->attachments[idx];
775
776 if (dst_resolve_micro_tile_mode != -1) {
777 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
778 att, dst_resolve_micro_tile_mode);
779 }
780 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
781
782 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
783 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
784
785 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
786 }
787
788 for (i = subpass->color_count; i < 8; i++)
789 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
790 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
791
792 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
793 int idx = subpass->depth_stencil_attachment.attachment;
794 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
795 struct radv_attachment_info *att = &framebuffer->attachments[idx];
796 struct radv_image *image = att->attachment->image;
797 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
798
799 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
800
801 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
802 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
803 cmd_buffer->state.offset_scale = att->ds.offset_scale;
804 }
805 radv_load_depth_clear_regs(cmd_buffer, image);
806 } else {
807 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
808 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
809 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
810 }
811 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
812 S_028208_BR_X(framebuffer->width) |
813 S_028208_BR_Y(framebuffer->height));
814 }
815
816 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
817 {
818 uint32_t db_count_control;
819
820 if(!cmd_buffer->state.active_occlusion_queries) {
821 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= CIK) {
822 db_count_control = 0;
823 } else {
824 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
825 }
826 } else {
827 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= CIK) {
828 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
829 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
830 S_028004_ZPASS_ENABLE(1) |
831 S_028004_SLICE_EVEN_ENABLE(1) |
832 S_028004_SLICE_ODD_ENABLE(1);
833 } else {
834 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
835 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
836 }
837 }
838
839 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
840 }
841
842 static void
843 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
844 {
845 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
846
847 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
848 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
849 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
850 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
851 }
852
853 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
854 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
855 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
856 }
857
858 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
859 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
860 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
861 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
862 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
863 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
864 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
865 S_028430_STENCILOPVAL(1));
866 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
867 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
868 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
869 S_028434_STENCILOPVAL_BF(1));
870 }
871
872 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
873 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
874 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
875 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
876 }
877
878 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
879 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
880 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
881 unsigned slope = fui(d->depth_bias.slope * 16.0f);
882 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
883
884 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
885 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
886 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
887 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
888 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
889 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
890 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
891 }
892 }
893
894 cmd_buffer->state.dirty = 0;
895 }
896
897 static void
898 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
899 int idx,
900 uint64_t va,
901 uint32_t base_reg)
902 {
903 radeon_set_sh_reg_seq(cmd_buffer->cs,
904 base_reg + 8 * idx, 2);
905 radeon_emit(cmd_buffer->cs, va);
906 radeon_emit(cmd_buffer->cs, va >> 32);
907 }
908
909 static void
910 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
911 VkShaderStageFlags stages,
912 struct radv_descriptor_set *set,
913 unsigned idx)
914 {
915 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
916 emit_stage_descriptor_set_userdata(cmd_buffer, idx, set->va, R_00B030_SPI_SHADER_USER_DATA_PS_0);
917
918 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
919 emit_stage_descriptor_set_userdata(cmd_buffer, idx, set->va, R_00B130_SPI_SHADER_USER_DATA_VS_0);
920
921 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
922 emit_stage_descriptor_set_userdata(cmd_buffer, idx, set->va, R_00B900_COMPUTE_USER_DATA_0);
923 }
924
925 static void
926 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
927 VkShaderStageFlags stages)
928 {
929 unsigned i;
930 if (!cmd_buffer->state.descriptors_dirty)
931 return;
932
933 for (i = 0; i < MAX_SETS; i++) {
934 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
935 continue;
936 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
937 if (!set)
938 continue;
939
940 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
941 }
942 cmd_buffer->state.descriptors_dirty = 0;
943 }
944
945 static void
946 emit_constants_set_userdata(struct radv_cmd_buffer *cmd_buffer,
947 uint64_t va,
948 uint32_t base_reg)
949 {
950 radeon_set_sh_reg_seq(cmd_buffer->cs,
951 base_reg + 4 * AC_USERDATA_PUSH_CONST_DYN, 2);
952 radeon_emit(cmd_buffer->cs, va);
953 radeon_emit(cmd_buffer->cs, va >> 32);
954 }
955
956 static void
957 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
958 struct radv_pipeline *pipeline,
959 VkShaderStageFlags stages)
960 {
961 struct radv_pipeline_layout *layout = pipeline->layout;
962 unsigned offset;
963 void *ptr;
964 uint64_t va;
965
966 stages &= cmd_buffer->push_constant_stages;
967 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
968 return;
969
970 radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
971 16 * layout->dynamic_offset_count,
972 256, &offset, &ptr);
973
974 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
975 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
976 16 * layout->dynamic_offset_count);
977
978 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
979 va += offset;
980
981 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
982 emit_constants_set_userdata(cmd_buffer, va, R_00B130_SPI_SHADER_USER_DATA_VS_0);
983
984 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
985 emit_constants_set_userdata(cmd_buffer, va, R_00B030_SPI_SHADER_USER_DATA_PS_0);
986
987 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
988 emit_constants_set_userdata(cmd_buffer, va, R_00B900_COMPUTE_USER_DATA_0);
989
990 cmd_buffer->push_constant_stages &= ~stages;
991 }
992
993 static void
994 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer)
995 {
996 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
997 struct radv_device *device = cmd_buffer->device;
998 uint32_t ia_multi_vgt_param;
999 uint32_t ls_hs_config = 0;
1000
1001 unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
1002 4096);
1003
1004 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1005 cmd_buffer->state.pipeline->num_vertex_attribs) {
1006 unsigned vb_offset;
1007 void *vb_ptr;
1008 uint32_t i = 0;
1009 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1010 uint64_t va;
1011
1012 /* allocate some descriptor state for vertex buffers */
1013 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1014 &vb_offset, &vb_ptr);
1015
1016 for (i = 0; i < num_attribs; i++) {
1017 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1018 uint32_t offset;
1019 int vb = cmd_buffer->state.pipeline->va_binding[i];
1020 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1021 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1022
1023 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1024 va = device->ws->buffer_get_va(buffer->bo);
1025
1026 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1027 va += offset + buffer->offset;
1028 desc[0] = va;
1029 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1030 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class <= CIK && stride)
1031 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1032 else
1033 desc[2] = buffer->size - offset;
1034 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1035 }
1036
1037 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1038 va += vb_offset;
1039 radeon_set_sh_reg_seq(cmd_buffer->cs,
1040 R_00B130_SPI_SHADER_USER_DATA_VS_0 + AC_USERDATA_VS_VERTEX_BUFFERS * 4, 2);
1041 radeon_emit(cmd_buffer->cs, va);
1042 radeon_emit(cmd_buffer->cs, va >> 32);
1043
1044 }
1045
1046 cmd_buffer->state.vertex_descriptors_dirty = false;
1047 cmd_buffer->state.vb_dirty = 0;
1048 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1049 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1050
1051 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1052 radv_emit_framebuffer_state(cmd_buffer);
1053
1054 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1055 radv_emit_viewport(cmd_buffer);
1056
1057 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR))
1058 radv_emit_scissor(cmd_buffer);
1059
1060 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1061 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, 0);
1062 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer);
1063
1064 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1065 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1066 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
1067 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1068 } else {
1069 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1070 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1071 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
1072 }
1073 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1074 }
1075
1076 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1077
1078 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1079 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1080 VK_SHADER_STAGE_ALL_GRAPHICS);
1081
1082 assert(cmd_buffer->cs->cdw <= cdw_max);
1083
1084 si_emit_cache_flush(cmd_buffer);
1085 }
1086
1087 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1088 VkPipelineStageFlags src_stage_mask)
1089 {
1090 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1091 VK_PIPELINE_STAGE_TRANSFER_BIT |
1092 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1093 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1094 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1095 }
1096
1097 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1098 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1099 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1100 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1101 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1102 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1103 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1104 VK_PIPELINE_STAGE_TRANSFER_BIT |
1105 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1106 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1107 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1108 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1109 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1110 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1111 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1112 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1113 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1114 }
1115 }
1116
1117 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1118 {
1119 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1120
1121 /* TODO: actual cache flushes */
1122 }
1123
1124 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1125 VkAttachmentReference att)
1126 {
1127 unsigned idx = att.attachment;
1128 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1129 VkImageSubresourceRange range;
1130 range.aspectMask = 0;
1131 range.baseMipLevel = view->base_mip;
1132 range.levelCount = 1;
1133 range.baseArrayLayer = view->base_layer;
1134 range.layerCount = cmd_buffer->state.framebuffer->layers;
1135
1136 radv_handle_image_transition(cmd_buffer,
1137 view->image,
1138 cmd_buffer->state.attachments[idx].current_layout,
1139 att.layout, range,
1140 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1141
1142 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1143
1144
1145 }
1146
1147 void
1148 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1149 const struct radv_subpass *subpass, bool transitions)
1150 {
1151 if (transitions) {
1152 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1153
1154 for (unsigned i = 0; i < subpass->color_count; ++i) {
1155 radv_handle_subpass_image_transition(cmd_buffer,
1156 subpass->color_attachments[i]);
1157 }
1158
1159 for (unsigned i = 0; i < subpass->input_count; ++i) {
1160 radv_handle_subpass_image_transition(cmd_buffer,
1161 subpass->input_attachments[i]);
1162 }
1163
1164 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1165 radv_handle_subpass_image_transition(cmd_buffer,
1166 subpass->depth_stencil_attachment);
1167 }
1168 }
1169
1170 cmd_buffer->state.subpass = subpass;
1171
1172 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1173 }
1174
1175 static void
1176 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1177 struct radv_render_pass *pass,
1178 const VkRenderPassBeginInfo *info)
1179 {
1180 struct radv_cmd_state *state = &cmd_buffer->state;
1181
1182 if (pass->attachment_count == 0) {
1183 state->attachments = NULL;
1184 return;
1185 }
1186
1187 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1188 pass->attachment_count *
1189 sizeof(state->attachments[0]),
1190 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1191 if (state->attachments == NULL) {
1192 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1193 abort();
1194 }
1195
1196 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1197 struct radv_render_pass_attachment *att = &pass->attachments[i];
1198 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1199 VkImageAspectFlags clear_aspects = 0;
1200
1201 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1202 /* color attachment */
1203 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1204 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1205 }
1206 } else {
1207 /* depthstencil attachment */
1208 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1209 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1210 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1211 }
1212 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1213 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1214 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1215 }
1216 }
1217
1218 state->attachments[i].pending_clear_aspects = clear_aspects;
1219 if (clear_aspects && info) {
1220 assert(info->clearValueCount > i);
1221 state->attachments[i].clear_value = info->pClearValues[i];
1222 }
1223
1224 state->attachments[i].current_layout = att->initial_layout;
1225 }
1226 }
1227
1228 VkResult radv_AllocateCommandBuffers(
1229 VkDevice _device,
1230 const VkCommandBufferAllocateInfo *pAllocateInfo,
1231 VkCommandBuffer *pCommandBuffers)
1232 {
1233 RADV_FROM_HANDLE(radv_device, device, _device);
1234 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1235
1236 VkResult result = VK_SUCCESS;
1237 uint32_t i;
1238
1239 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1240 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1241 &pCommandBuffers[i]);
1242 if (result != VK_SUCCESS)
1243 break;
1244 }
1245
1246 if (result != VK_SUCCESS)
1247 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1248 i, pCommandBuffers);
1249
1250 return result;
1251 }
1252
1253 static void
1254 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
1255 {
1256 list_del(&cmd_buffer->pool_link);
1257
1258 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1259 &cmd_buffer->upload.list, list) {
1260 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1261 list_del(&up->list);
1262 free(up);
1263 }
1264
1265 if (cmd_buffer->upload.upload_bo)
1266 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
1267 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
1268 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1269 }
1270
1271 void radv_FreeCommandBuffers(
1272 VkDevice device,
1273 VkCommandPool commandPool,
1274 uint32_t commandBufferCount,
1275 const VkCommandBuffer *pCommandBuffers)
1276 {
1277 for (uint32_t i = 0; i < commandBufferCount; i++) {
1278 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1279
1280 if (cmd_buffer)
1281 radv_cmd_buffer_destroy(cmd_buffer);
1282 }
1283 }
1284
1285 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
1286 {
1287
1288 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
1289
1290 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1291 &cmd_buffer->upload.list, list) {
1292 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1293 list_del(&up->list);
1294 free(up);
1295 }
1296
1297 if (cmd_buffer->upload.upload_bo)
1298 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
1299 cmd_buffer->upload.upload_bo, 8);
1300 cmd_buffer->upload.offset = 0;
1301
1302 cmd_buffer->record_fail = false;
1303 }
1304
1305 VkResult radv_ResetCommandBuffer(
1306 VkCommandBuffer commandBuffer,
1307 VkCommandBufferResetFlags flags)
1308 {
1309 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1310 radv_reset_cmd_buffer(cmd_buffer);
1311 return VK_SUCCESS;
1312 }
1313
1314 VkResult radv_BeginCommandBuffer(
1315 VkCommandBuffer commandBuffer,
1316 const VkCommandBufferBeginInfo *pBeginInfo)
1317 {
1318 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1319 radv_reset_cmd_buffer(cmd_buffer);
1320
1321 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1322
1323 /* setup initial configuration into command buffer */
1324 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1325 /* Flush read caches at the beginning of CS not flushed by the kernel. */
1326 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_ICACHE |
1327 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1328 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1329 RADV_CMD_FLAG_INV_VMEM_L1 |
1330 RADV_CMD_FLAG_INV_SMEM_L1 |
1331 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
1332 RADV_CMD_FLAG_INV_GLOBAL_L2;
1333 si_init_config(&cmd_buffer->device->instance->physicalDevice, cmd_buffer);
1334 radv_set_db_count_control(cmd_buffer);
1335 si_emit_cache_flush(cmd_buffer);
1336 }
1337
1338 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1339 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1340 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1341
1342 struct radv_subpass *subpass =
1343 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1344
1345 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1346 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1347 }
1348
1349 return VK_SUCCESS;
1350 }
1351
1352 void radv_CmdBindVertexBuffers(
1353 VkCommandBuffer commandBuffer,
1354 uint32_t firstBinding,
1355 uint32_t bindingCount,
1356 const VkBuffer* pBuffers,
1357 const VkDeviceSize* pOffsets)
1358 {
1359 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1360 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1361
1362 /* We have to defer setting up vertex buffer since we need the buffer
1363 * stride from the pipeline. */
1364
1365 assert(firstBinding + bindingCount < MAX_VBS);
1366 for (uint32_t i = 0; i < bindingCount; i++) {
1367 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1368 vb[firstBinding + i].offset = pOffsets[i];
1369 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1370 }
1371 }
1372
1373 void radv_CmdBindIndexBuffer(
1374 VkCommandBuffer commandBuffer,
1375 VkBuffer buffer,
1376 VkDeviceSize offset,
1377 VkIndexType indexType)
1378 {
1379 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1380
1381 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1382 cmd_buffer->state.index_offset = offset;
1383 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1384 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1385 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1386 }
1387
1388
1389 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1390 struct radv_descriptor_set *set,
1391 unsigned idx)
1392 {
1393 struct radeon_winsys *ws = cmd_buffer->device->ws;
1394
1395 cmd_buffer->state.descriptors[idx] = set;
1396 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1397 if (!set)
1398 return;
1399
1400 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1401 if (set->descriptors[j])
1402 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1403
1404 if(set->bo)
1405 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1406 }
1407
1408 void radv_CmdBindDescriptorSets(
1409 VkCommandBuffer commandBuffer,
1410 VkPipelineBindPoint pipelineBindPoint,
1411 VkPipelineLayout _layout,
1412 uint32_t firstSet,
1413 uint32_t descriptorSetCount,
1414 const VkDescriptorSet* pDescriptorSets,
1415 uint32_t dynamicOffsetCount,
1416 const uint32_t* pDynamicOffsets)
1417 {
1418 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1419 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1420 unsigned dyn_idx = 0;
1421
1422 unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
1423 MAX_SETS * 4 * 6);
1424
1425 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1426 unsigned idx = i + firstSet;
1427 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1428 radv_bind_descriptor_set(cmd_buffer, set, idx);
1429
1430 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1431 unsigned idx = j + layout->set[i].dynamic_offset_start;
1432 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1433 assert(dyn_idx < dynamicOffsetCount);
1434
1435 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1436 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1437 dst[0] = va;
1438 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1439 dst[2] = range->size;
1440 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1441 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1442 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1443 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1444 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1445 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1446 cmd_buffer->push_constant_stages |=
1447 set->layout->dynamic_shader_stages;
1448 }
1449 }
1450
1451 assert(cmd_buffer->cs->cdw <= cdw_max);
1452 }
1453
1454 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1455 VkPipelineLayout layout,
1456 VkShaderStageFlags stageFlags,
1457 uint32_t offset,
1458 uint32_t size,
1459 const void* pValues)
1460 {
1461 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1462 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1463 cmd_buffer->push_constant_stages |= stageFlags;
1464 }
1465
1466 VkResult radv_EndCommandBuffer(
1467 VkCommandBuffer commandBuffer)
1468 {
1469 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1470
1471 si_emit_cache_flush(cmd_buffer);
1472 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1473 cmd_buffer->record_fail)
1474 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1475 return VK_SUCCESS;
1476 }
1477
1478 static void
1479 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1480 {
1481 struct radeon_winsys *ws = cmd_buffer->device->ws;
1482 struct radv_shader_variant *compute_shader;
1483 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1484 uint64_t va;
1485
1486 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1487 return;
1488
1489 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1490
1491 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1492 va = ws->buffer_get_va(compute_shader->bo);
1493
1494 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1495
1496 unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 16);
1497
1498 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1499 radeon_emit(cmd_buffer->cs, va >> 8);
1500 radeon_emit(cmd_buffer->cs, va >> 40);
1501
1502 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1503 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1504 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1505
1506 /* change these once we have scratch support */
1507 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1508 S_00B860_WAVES(32) | S_00B860_WAVESIZE(0));
1509
1510 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1511 radeon_emit(cmd_buffer->cs,
1512 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1513 radeon_emit(cmd_buffer->cs,
1514 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1515 radeon_emit(cmd_buffer->cs,
1516 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1517
1518 assert(cmd_buffer->cs->cdw <= cdw_max);
1519 }
1520
1521
1522 void radv_CmdBindPipeline(
1523 VkCommandBuffer commandBuffer,
1524 VkPipelineBindPoint pipelineBindPoint,
1525 VkPipeline _pipeline)
1526 {
1527 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1528 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1529
1530 for (unsigned i = 0; i < MAX_SETS; i++) {
1531 if (cmd_buffer->state.descriptors[i])
1532 cmd_buffer->state.descriptors_dirty |= (1 << i);
1533 }
1534
1535 switch (pipelineBindPoint) {
1536 case VK_PIPELINE_BIND_POINT_COMPUTE:
1537 cmd_buffer->state.compute_pipeline = pipeline;
1538 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
1539 break;
1540 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1541 cmd_buffer->state.pipeline = pipeline;
1542 cmd_buffer->state.vertex_descriptors_dirty = true;
1543 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1544 cmd_buffer->push_constant_stages |= pipeline->active_stages;
1545
1546 /* Apply the dynamic state from the pipeline */
1547 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
1548 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
1549 &pipeline->dynamic_state,
1550 pipeline->dynamic_state_mask);
1551 break;
1552 default:
1553 assert(!"invalid bind point");
1554 break;
1555 }
1556 }
1557
1558 void radv_CmdSetViewport(
1559 VkCommandBuffer commandBuffer,
1560 uint32_t firstViewport,
1561 uint32_t viewportCount,
1562 const VkViewport* pViewports)
1563 {
1564 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1565
1566 const uint32_t total_count = firstViewport + viewportCount;
1567 if (cmd_buffer->state.dynamic.viewport.count < total_count)
1568 cmd_buffer->state.dynamic.viewport.count = total_count;
1569
1570 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
1571 pViewports, viewportCount * sizeof(*pViewports));
1572
1573 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
1574 }
1575
1576 void radv_CmdSetScissor(
1577 VkCommandBuffer commandBuffer,
1578 uint32_t firstScissor,
1579 uint32_t scissorCount,
1580 const VkRect2D* pScissors)
1581 {
1582 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1583
1584 const uint32_t total_count = firstScissor + scissorCount;
1585 if (cmd_buffer->state.dynamic.scissor.count < total_count)
1586 cmd_buffer->state.dynamic.scissor.count = total_count;
1587
1588 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
1589 pScissors, scissorCount * sizeof(*pScissors));
1590 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1591 }
1592
1593 void radv_CmdSetLineWidth(
1594 VkCommandBuffer commandBuffer,
1595 float lineWidth)
1596 {
1597 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1598 cmd_buffer->state.dynamic.line_width = lineWidth;
1599 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1600 }
1601
1602 void radv_CmdSetDepthBias(
1603 VkCommandBuffer commandBuffer,
1604 float depthBiasConstantFactor,
1605 float depthBiasClamp,
1606 float depthBiasSlopeFactor)
1607 {
1608 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1609
1610 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
1611 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
1612 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
1613
1614 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1615 }
1616
1617 void radv_CmdSetBlendConstants(
1618 VkCommandBuffer commandBuffer,
1619 const float blendConstants[4])
1620 {
1621 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1622
1623 memcpy(cmd_buffer->state.dynamic.blend_constants,
1624 blendConstants, sizeof(float) * 4);
1625
1626 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
1627 }
1628
1629 void radv_CmdSetDepthBounds(
1630 VkCommandBuffer commandBuffer,
1631 float minDepthBounds,
1632 float maxDepthBounds)
1633 {
1634 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1635
1636 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
1637 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
1638
1639 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
1640 }
1641
1642 void radv_CmdSetStencilCompareMask(
1643 VkCommandBuffer commandBuffer,
1644 VkStencilFaceFlags faceMask,
1645 uint32_t compareMask)
1646 {
1647 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1648
1649 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1650 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
1651 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1652 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
1653
1654 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1655 }
1656
1657 void radv_CmdSetStencilWriteMask(
1658 VkCommandBuffer commandBuffer,
1659 VkStencilFaceFlags faceMask,
1660 uint32_t writeMask)
1661 {
1662 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1663
1664 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1665 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
1666 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1667 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
1668
1669 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1670 }
1671
1672 void radv_CmdSetStencilReference(
1673 VkCommandBuffer commandBuffer,
1674 VkStencilFaceFlags faceMask,
1675 uint32_t reference)
1676 {
1677 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1678
1679 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1680 cmd_buffer->state.dynamic.stencil_reference.front = reference;
1681 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1682 cmd_buffer->state.dynamic.stencil_reference.back = reference;
1683
1684 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1685 }
1686
1687
1688 void radv_CmdExecuteCommands(
1689 VkCommandBuffer commandBuffer,
1690 uint32_t commandBufferCount,
1691 const VkCommandBuffer* pCmdBuffers)
1692 {
1693 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
1694
1695 for (uint32_t i = 0; i < commandBufferCount; i++) {
1696 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
1697
1698 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
1699 }
1700
1701 /* if we execute secondary we need to re-emit out pipelines */
1702 if (commandBufferCount) {
1703 primary->state.emitted_pipeline = NULL;
1704 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1705 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
1706 }
1707 }
1708
1709 VkResult radv_CreateCommandPool(
1710 VkDevice _device,
1711 const VkCommandPoolCreateInfo* pCreateInfo,
1712 const VkAllocationCallbacks* pAllocator,
1713 VkCommandPool* pCmdPool)
1714 {
1715 RADV_FROM_HANDLE(radv_device, device, _device);
1716 struct radv_cmd_pool *pool;
1717
1718 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
1719 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1720 if (pool == NULL)
1721 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1722
1723 if (pAllocator)
1724 pool->alloc = *pAllocator;
1725 else
1726 pool->alloc = device->alloc;
1727
1728 list_inithead(&pool->cmd_buffers);
1729
1730 *pCmdPool = radv_cmd_pool_to_handle(pool);
1731
1732 return VK_SUCCESS;
1733
1734 }
1735
1736 void radv_DestroyCommandPool(
1737 VkDevice _device,
1738 VkCommandPool commandPool,
1739 const VkAllocationCallbacks* pAllocator)
1740 {
1741 RADV_FROM_HANDLE(radv_device, device, _device);
1742 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
1743
1744 if (!pool)
1745 return;
1746
1747 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
1748 &pool->cmd_buffers, pool_link) {
1749 radv_cmd_buffer_destroy(cmd_buffer);
1750 }
1751
1752 vk_free2(&device->alloc, pAllocator, pool);
1753 }
1754
1755 VkResult radv_ResetCommandPool(
1756 VkDevice device,
1757 VkCommandPool commandPool,
1758 VkCommandPoolResetFlags flags)
1759 {
1760 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
1761
1762 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
1763 &pool->cmd_buffers, pool_link) {
1764 radv_reset_cmd_buffer(cmd_buffer);
1765 }
1766
1767 return VK_SUCCESS;
1768 }
1769
1770 void radv_CmdBeginRenderPass(
1771 VkCommandBuffer commandBuffer,
1772 const VkRenderPassBeginInfo* pRenderPassBegin,
1773 VkSubpassContents contents)
1774 {
1775 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1776 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
1777 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
1778
1779 unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
1780 2048);
1781
1782 cmd_buffer->state.framebuffer = framebuffer;
1783 cmd_buffer->state.pass = pass;
1784 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
1785 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
1786
1787 si_emit_cache_flush(cmd_buffer);
1788
1789 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
1790 assert(cmd_buffer->cs->cdw <= cdw_max);
1791
1792 radv_cmd_buffer_clear_subpass(cmd_buffer);
1793 }
1794
1795 void radv_CmdNextSubpass(
1796 VkCommandBuffer commandBuffer,
1797 VkSubpassContents contents)
1798 {
1799 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1800
1801 si_emit_cache_flush(cmd_buffer);
1802 radv_cmd_buffer_resolve_subpass(cmd_buffer);
1803
1804 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
1805 2048);
1806
1807 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
1808 radv_cmd_buffer_clear_subpass(cmd_buffer);
1809 }
1810
1811 void radv_CmdDraw(
1812 VkCommandBuffer commandBuffer,
1813 uint32_t vertexCount,
1814 uint32_t instanceCount,
1815 uint32_t firstVertex,
1816 uint32_t firstInstance)
1817 {
1818 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1819 radv_cmd_buffer_flush_state(cmd_buffer);
1820
1821 unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1822
1823 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B130_SPI_SHADER_USER_DATA_VS_0 + AC_USERDATA_VS_BASE_VERTEX * 4, 2);
1824 radeon_emit(cmd_buffer->cs, firstVertex);
1825 radeon_emit(cmd_buffer->cs, firstInstance);
1826 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
1827 radeon_emit(cmd_buffer->cs, instanceCount);
1828
1829 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
1830 radeon_emit(cmd_buffer->cs, vertexCount);
1831 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1832 S_0287F0_USE_OPAQUE(0));
1833
1834 assert(cmd_buffer->cs->cdw <= cdw_max);
1835 }
1836
1837 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
1838 {
1839 uint32_t primitive_reset_index = cmd_buffer->state.last_primitive_reset_index ? 0xffffffffu : 0xffffu;
1840
1841 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
1842 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1843 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1844 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1845 primitive_reset_index);
1846 }
1847 }
1848
1849 void radv_CmdDrawIndexed(
1850 VkCommandBuffer commandBuffer,
1851 uint32_t indexCount,
1852 uint32_t instanceCount,
1853 uint32_t firstIndex,
1854 int32_t vertexOffset,
1855 uint32_t firstInstance)
1856 {
1857 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1858 int index_size = cmd_buffer->state.index_type ? 4 : 2;
1859 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
1860 uint64_t index_va;
1861
1862 radv_cmd_buffer_flush_state(cmd_buffer);
1863 radv_emit_primitive_reset_index(cmd_buffer);
1864
1865 unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 14);
1866
1867 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1868 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
1869
1870 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B130_SPI_SHADER_USER_DATA_VS_0 + AC_USERDATA_VS_BASE_VERTEX * 4, 2);
1871 radeon_emit(cmd_buffer->cs, vertexOffset);
1872 radeon_emit(cmd_buffer->cs, firstInstance);
1873 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
1874 radeon_emit(cmd_buffer->cs, instanceCount);
1875
1876 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
1877 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
1878 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
1879 radeon_emit(cmd_buffer->cs, index_max_size);
1880 radeon_emit(cmd_buffer->cs, index_va);
1881 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
1882 radeon_emit(cmd_buffer->cs, indexCount);
1883 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
1884
1885 assert(cmd_buffer->cs->cdw <= cdw_max);
1886 }
1887
1888 static void
1889 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
1890 VkBuffer _buffer,
1891 VkDeviceSize offset,
1892 VkBuffer _count_buffer,
1893 VkDeviceSize count_offset,
1894 uint32_t draw_count,
1895 uint32_t stride,
1896 bool indexed)
1897 {
1898 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1899 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
1900 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1901 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
1902 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
1903 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
1904 indirect_va += offset + buffer->offset;
1905 uint64_t count_va = 0;
1906
1907 if (count_buffer) {
1908 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
1909 count_va += count_offset + count_buffer->offset;
1910 }
1911
1912 if (!draw_count)
1913 return;
1914
1915 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
1916
1917 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
1918 radeon_emit(cs, 1);
1919 radeon_emit(cs, indirect_va);
1920 radeon_emit(cs, indirect_va >> 32);
1921
1922 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
1923 PKT3_DRAW_INDIRECT_MULTI,
1924 8, false));
1925 radeon_emit(cs, 0);
1926 radeon_emit(cs, ((R_00B130_SPI_SHADER_USER_DATA_VS_0 + AC_USERDATA_VS_BASE_VERTEX * 4) - SI_SH_REG_OFFSET) >> 2);
1927 radeon_emit(cs, ((R_00B130_SPI_SHADER_USER_DATA_VS_0 + AC_USERDATA_VS_START_INSTANCE * 4) - SI_SH_REG_OFFSET) >> 2);
1928 radeon_emit(cs, S_2C3_COUNT_INDIRECT_ENABLE(!!count_va)); /* draw_index and count_indirect enable */
1929 radeon_emit(cs, draw_count); /* count */
1930 radeon_emit(cs, count_va); /* count_addr */
1931 radeon_emit(cs, count_va >> 32);
1932 radeon_emit(cs, stride); /* stride */
1933 radeon_emit(cs, di_src_sel);
1934 }
1935
1936 static void
1937 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
1938 VkBuffer buffer,
1939 VkDeviceSize offset,
1940 VkBuffer countBuffer,
1941 VkDeviceSize countBufferOffset,
1942 uint32_t maxDrawCount,
1943 uint32_t stride)
1944 {
1945 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1946 radv_cmd_buffer_flush_state(cmd_buffer);
1947
1948 unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 14);
1949
1950 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
1951 countBuffer, countBufferOffset, maxDrawCount, stride, false);
1952
1953 assert(cmd_buffer->cs->cdw <= cdw_max);
1954 }
1955
1956 static void
1957 radv_cmd_draw_indexed_indirect_count(
1958 VkCommandBuffer commandBuffer,
1959 VkBuffer buffer,
1960 VkDeviceSize offset,
1961 VkBuffer countBuffer,
1962 VkDeviceSize countBufferOffset,
1963 uint32_t maxDrawCount,
1964 uint32_t stride)
1965 {
1966 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1967 int index_size = cmd_buffer->state.index_type ? 4 : 2;
1968 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
1969 uint64_t index_va;
1970 radv_cmd_buffer_flush_state(cmd_buffer);
1971 radv_emit_primitive_reset_index(cmd_buffer);
1972
1973 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
1974 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
1975
1976 unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
1977
1978 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1979 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
1980
1981 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1982 radeon_emit(cmd_buffer->cs, index_va);
1983 radeon_emit(cmd_buffer->cs, index_va >> 32);
1984
1985 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1986 radeon_emit(cmd_buffer->cs, index_max_size);
1987
1988 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
1989 countBuffer, countBufferOffset, maxDrawCount, stride, true);
1990
1991 assert(cmd_buffer->cs->cdw <= cdw_max);
1992 }
1993
1994 void radv_CmdDrawIndirect(
1995 VkCommandBuffer commandBuffer,
1996 VkBuffer buffer,
1997 VkDeviceSize offset,
1998 uint32_t drawCount,
1999 uint32_t stride)
2000 {
2001 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2002 VK_NULL_HANDLE, 0, drawCount, stride);
2003 }
2004
2005 void radv_CmdDrawIndexedIndirect(
2006 VkCommandBuffer commandBuffer,
2007 VkBuffer buffer,
2008 VkDeviceSize offset,
2009 uint32_t drawCount,
2010 uint32_t stride)
2011 {
2012 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2013 VK_NULL_HANDLE, 0, drawCount, stride);
2014 }
2015
2016 void radv_CmdDrawIndirectCountAMD(
2017 VkCommandBuffer commandBuffer,
2018 VkBuffer buffer,
2019 VkDeviceSize offset,
2020 VkBuffer countBuffer,
2021 VkDeviceSize countBufferOffset,
2022 uint32_t maxDrawCount,
2023 uint32_t stride)
2024 {
2025 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2026 countBuffer, countBufferOffset,
2027 maxDrawCount, stride);
2028 }
2029
2030 void radv_CmdDrawIndexedIndirectCountAMD(
2031 VkCommandBuffer commandBuffer,
2032 VkBuffer buffer,
2033 VkDeviceSize offset,
2034 VkBuffer countBuffer,
2035 VkDeviceSize countBufferOffset,
2036 uint32_t maxDrawCount,
2037 uint32_t stride)
2038 {
2039 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2040 countBuffer, countBufferOffset,
2041 maxDrawCount, stride);
2042 }
2043
2044 static void
2045 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2046 {
2047 radv_emit_compute_pipeline(cmd_buffer);
2048 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
2049 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2050 VK_SHADER_STAGE_COMPUTE_BIT);
2051 si_emit_cache_flush(cmd_buffer);
2052 }
2053
2054 void radv_CmdDispatch(
2055 VkCommandBuffer commandBuffer,
2056 uint32_t x,
2057 uint32_t y,
2058 uint32_t z)
2059 {
2060 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2061
2062 radv_flush_compute_state(cmd_buffer);
2063
2064 unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2065
2066 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + AC_USERDATA_CS_GRID_SIZE * 4, 3);
2067 radeon_emit(cmd_buffer->cs, x);
2068 radeon_emit(cmd_buffer->cs, y);
2069 radeon_emit(cmd_buffer->cs, z);
2070
2071 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2072 PKT3_SHADER_TYPE_S(1));
2073 radeon_emit(cmd_buffer->cs, x);
2074 radeon_emit(cmd_buffer->cs, y);
2075 radeon_emit(cmd_buffer->cs, z);
2076 radeon_emit(cmd_buffer->cs, 1);
2077
2078 assert(cmd_buffer->cs->cdw <= cdw_max);
2079 }
2080
2081 void radv_CmdDispatchIndirect(
2082 VkCommandBuffer commandBuffer,
2083 VkBuffer _buffer,
2084 VkDeviceSize offset)
2085 {
2086 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2087 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2088 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2089 va += buffer->offset + offset;
2090
2091 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2092
2093 radv_flush_compute_state(cmd_buffer);
2094
2095 unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2096
2097 for (unsigned i = 0; i < 3; ++i) {
2098 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2099 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2100 COPY_DATA_DST_SEL(COPY_DATA_REG));
2101 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2102 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2103 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + AC_USERDATA_CS_GRID_SIZE * 4) >> 2) + i);
2104 radeon_emit(cmd_buffer->cs, 0);
2105 }
2106
2107 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2108 PKT3_SHADER_TYPE_S(1));
2109 radeon_emit(cmd_buffer->cs, 1);
2110 radeon_emit(cmd_buffer->cs, va);
2111 radeon_emit(cmd_buffer->cs, va >> 32);
2112
2113 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2114 PKT3_SHADER_TYPE_S(1));
2115 radeon_emit(cmd_buffer->cs, 0);
2116 radeon_emit(cmd_buffer->cs, 1);
2117
2118 assert(cmd_buffer->cs->cdw <= cdw_max);
2119 }
2120
2121 void radv_unaligned_dispatch(
2122 struct radv_cmd_buffer *cmd_buffer,
2123 uint32_t x,
2124 uint32_t y,
2125 uint32_t z)
2126 {
2127 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2128 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2129 uint32_t blocks[3], remainder[3];
2130
2131 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2132 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2133 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2134
2135 /* If aligned, these should be an entire block size, not 0 */
2136 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2137 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2138 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2139
2140 radv_flush_compute_state(cmd_buffer);
2141
2142 unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2143
2144 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2145 radeon_emit(cmd_buffer->cs,
2146 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2147 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2148 radeon_emit(cmd_buffer->cs,
2149 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2150 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2151 radeon_emit(cmd_buffer->cs,
2152 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2153 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2154
2155 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + AC_USERDATA_CS_GRID_SIZE * 4, 3);
2156 radeon_emit(cmd_buffer->cs, blocks[0]);
2157 radeon_emit(cmd_buffer->cs, blocks[1]);
2158 radeon_emit(cmd_buffer->cs, blocks[2]);
2159
2160 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2161 PKT3_SHADER_TYPE_S(1));
2162 radeon_emit(cmd_buffer->cs, blocks[0]);
2163 radeon_emit(cmd_buffer->cs, blocks[1]);
2164 radeon_emit(cmd_buffer->cs, blocks[2]);
2165 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2166 S_00B800_PARTIAL_TG_EN(1));
2167
2168 assert(cmd_buffer->cs->cdw <= cdw_max);
2169 }
2170
2171 void radv_CmdEndRenderPass(
2172 VkCommandBuffer commandBuffer)
2173 {
2174 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2175
2176 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2177
2178 si_emit_cache_flush(cmd_buffer);
2179 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2180
2181 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2182 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2183 radv_handle_subpass_image_transition(cmd_buffer,
2184 (VkAttachmentReference){i, layout});
2185 }
2186
2187 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2188
2189 cmd_buffer->state.pass = NULL;
2190 cmd_buffer->state.subpass = NULL;
2191 cmd_buffer->state.attachments = NULL;
2192 cmd_buffer->state.framebuffer = NULL;
2193 }
2194
2195
2196 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2197 struct radv_image *image)
2198 {
2199
2200 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2201 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2202
2203 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->htile.offset,
2204 image->htile.size, 0xffffffff);
2205
2206 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2207 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2208 RADV_CMD_FLAG_INV_VMEM_L1 |
2209 RADV_CMD_FLAG_INV_GLOBAL_L2;
2210 }
2211
2212 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2213 struct radv_image *image,
2214 VkImageLayout src_layout,
2215 VkImageLayout dst_layout,
2216 VkImageSubresourceRange range,
2217 VkImageAspectFlags pending_clears)
2218 {
2219 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2220 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2221 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2222 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2223 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2224 /* The clear will initialize htile. */
2225 return;
2226 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2227 radv_layout_has_htile(image, dst_layout)) {
2228 /* TODO: merge with the clear if applicable */
2229 radv_initialize_htile(cmd_buffer, image);
2230 } else if (!radv_layout_has_htile(image, src_layout) &&
2231 radv_layout_has_htile(image, dst_layout)) {
2232 radv_initialize_htile(cmd_buffer, image);
2233 } else if ((radv_layout_has_htile(image, src_layout) &&
2234 !radv_layout_has_htile(image, dst_layout)) ||
2235 (radv_layout_is_htile_compressed(image, src_layout) &&
2236 !radv_layout_is_htile_compressed(image, dst_layout))) {
2237
2238 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2239 range.baseMipLevel = 0;
2240 range.levelCount = 1;
2241
2242 radv_decompress_depth_image_inplace(cmd_buffer, image, &range);
2243 }
2244 }
2245
2246 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2247 struct radv_image *image, uint32_t value)
2248 {
2249 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2250 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2251
2252 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2253 image->cmask.size, value);
2254
2255 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2256 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2257 RADV_CMD_FLAG_INV_VMEM_L1 |
2258 RADV_CMD_FLAG_INV_GLOBAL_L2;
2259 }
2260
2261 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2262 struct radv_image *image,
2263 VkImageLayout src_layout,
2264 VkImageLayout dst_layout,
2265 VkImageSubresourceRange range,
2266 VkImageAspectFlags pending_clears)
2267 {
2268 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2269 if (image->fmask.size)
2270 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2271 else
2272 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2273 } else if (radv_layout_has_cmask(image, src_layout) &&
2274 !radv_layout_has_cmask(image, dst_layout)) {
2275 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2276 }
2277 }
2278
2279 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2280 struct radv_image *image, uint32_t value)
2281 {
2282
2283 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2284 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2285
2286 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2287 image->surface.dcc_size, value);
2288
2289 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2290 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2291 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2292 RADV_CMD_FLAG_INV_VMEM_L1 |
2293 RADV_CMD_FLAG_INV_GLOBAL_L2;
2294 }
2295
2296 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2297 struct radv_image *image,
2298 VkImageLayout src_layout,
2299 VkImageLayout dst_layout,
2300 VkImageSubresourceRange range,
2301 VkImageAspectFlags pending_clears)
2302 {
2303 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2304 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2305 } else if(src_layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
2306 dst_layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL) {
2307 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2308 }
2309 }
2310
2311 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2312 struct radv_image *image,
2313 VkImageLayout src_layout,
2314 VkImageLayout dst_layout,
2315 VkImageSubresourceRange range,
2316 VkImageAspectFlags pending_clears)
2317 {
2318 if (image->htile.size)
2319 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2320 dst_layout, range, pending_clears);
2321
2322 if (image->cmask.size)
2323 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2324 dst_layout, range, pending_clears);
2325
2326 if (image->surface.dcc_size)
2327 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2328 dst_layout, range, pending_clears);
2329 }
2330
2331 void radv_CmdPipelineBarrier(
2332 VkCommandBuffer commandBuffer,
2333 VkPipelineStageFlags srcStageMask,
2334 VkPipelineStageFlags destStageMask,
2335 VkBool32 byRegion,
2336 uint32_t memoryBarrierCount,
2337 const VkMemoryBarrier* pMemoryBarriers,
2338 uint32_t bufferMemoryBarrierCount,
2339 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2340 uint32_t imageMemoryBarrierCount,
2341 const VkImageMemoryBarrier* pImageMemoryBarriers)
2342 {
2343 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2344 VkAccessFlags src_flags = 0;
2345 VkAccessFlags dst_flags = 0;
2346 uint32_t b;
2347 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2348 src_flags |= pMemoryBarriers[i].srcAccessMask;
2349 dst_flags |= pMemoryBarriers[i].dstAccessMask;
2350 }
2351
2352 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2353 src_flags |= pBufferMemoryBarriers[i].srcAccessMask;
2354 dst_flags |= pBufferMemoryBarriers[i].dstAccessMask;
2355 }
2356
2357 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2358 src_flags |= pImageMemoryBarriers[i].srcAccessMask;
2359 dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
2360 }
2361
2362 enum radv_cmd_flush_bits flush_bits = 0;
2363 for_each_bit(b, src_flags) {
2364 switch ((VkAccessFlagBits)(1 << b)) {
2365 case VK_ACCESS_SHADER_WRITE_BIT:
2366 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2367 break;
2368 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2369 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2370 break;
2371 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2372 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2373 break;
2374 case VK_ACCESS_TRANSFER_WRITE_BIT:
2375 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2376 break;
2377 default:
2378 break;
2379 }
2380 }
2381 cmd_buffer->state.flush_bits |= flush_bits;
2382
2383 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2384 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2385 radv_handle_image_transition(cmd_buffer, image,
2386 pImageMemoryBarriers[i].oldLayout,
2387 pImageMemoryBarriers[i].newLayout,
2388 pImageMemoryBarriers[i].subresourceRange,
2389 0);
2390 }
2391
2392 flush_bits = 0;
2393
2394 for_each_bit(b, dst_flags) {
2395 switch ((VkAccessFlagBits)(1 << b)) {
2396 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2397 case VK_ACCESS_INDEX_READ_BIT:
2398 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2399 case VK_ACCESS_UNIFORM_READ_BIT:
2400 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2401 break;
2402 case VK_ACCESS_SHADER_READ_BIT:
2403 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2404 break;
2405 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2406 case VK_ACCESS_TRANSFER_READ_BIT:
2407 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2408 flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER | RADV_CMD_FLAG_INV_GLOBAL_L2;
2409 default:
2410 break;
2411 }
2412 }
2413
2414 flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2415 RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2416
2417 cmd_buffer->state.flush_bits |= flush_bits;
2418 }
2419
2420
2421 static void write_event(struct radv_cmd_buffer *cmd_buffer,
2422 struct radv_event *event,
2423 VkPipelineStageFlags stageMask,
2424 unsigned value)
2425 {
2426 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2427 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2428
2429 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2430
2431 unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
2432
2433 /* TODO: this is overkill. Probably should figure something out from
2434 * the stage mask. */
2435
2436 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class == CIK) {
2437 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2438 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2439 EVENT_INDEX(5));
2440 radeon_emit(cs, va);
2441 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2442 radeon_emit(cs, 2);
2443 radeon_emit(cs, 0);
2444 }
2445
2446 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2447 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2448 EVENT_INDEX(5));
2449 radeon_emit(cs, va);
2450 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2451 radeon_emit(cs, value);
2452 radeon_emit(cs, 0);
2453
2454 assert(cmd_buffer->cs->cdw <= cdw_max);
2455 }
2456
2457 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
2458 VkEvent _event,
2459 VkPipelineStageFlags stageMask)
2460 {
2461 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2462 RADV_FROM_HANDLE(radv_event, event, _event);
2463
2464 write_event(cmd_buffer, event, stageMask, 1);
2465 }
2466
2467 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
2468 VkEvent _event,
2469 VkPipelineStageFlags stageMask)
2470 {
2471 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2472 RADV_FROM_HANDLE(radv_event, event, _event);
2473
2474 write_event(cmd_buffer, event, stageMask, 0);
2475 }
2476
2477 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
2478 uint32_t eventCount,
2479 const VkEvent* pEvents,
2480 VkPipelineStageFlags srcStageMask,
2481 VkPipelineStageFlags dstStageMask,
2482 uint32_t memoryBarrierCount,
2483 const VkMemoryBarrier* pMemoryBarriers,
2484 uint32_t bufferMemoryBarrierCount,
2485 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2486 uint32_t imageMemoryBarrierCount,
2487 const VkImageMemoryBarrier* pImageMemoryBarriers)
2488 {
2489 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2490 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2491
2492 for (unsigned i = 0; i < eventCount; ++i) {
2493 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
2494 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2495
2496 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2497
2498 unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
2499
2500 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
2501 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
2502 radeon_emit(cs, va);
2503 radeon_emit(cs, va >> 32);
2504 radeon_emit(cs, 1); /* reference value */
2505 radeon_emit(cs, 0xffffffff); /* mask */
2506 radeon_emit(cs, 4); /* poll interval */
2507
2508 assert(cmd_buffer->cs->cdw <= cdw_max);
2509 }
2510
2511
2512 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2513 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2514
2515 radv_handle_image_transition(cmd_buffer, image,
2516 pImageMemoryBarriers[i].oldLayout,
2517 pImageMemoryBarriers[i].newLayout,
2518 pImageMemoryBarriers[i].subresourceRange,
2519 0);
2520 }
2521
2522 /* TODO: figure out how to do memory barriers without waiting */
2523 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
2524 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2525 RADV_CMD_FLAG_INV_VMEM_L1 |
2526 RADV_CMD_FLAG_INV_SMEM_L1;
2527 }