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radv: store the FCE predicate for each mip
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 struct radv_sample_locations_state *sample_locs);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109 dest->sample_location.count = src->sample_location.count;
110
111 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
112 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
113 src->viewport.count * sizeof(VkViewport))) {
114 typed_memcpy(dest->viewport.viewports,
115 src->viewport.viewports,
116 src->viewport.count);
117 dest_mask |= RADV_DYNAMIC_VIEWPORT;
118 }
119 }
120
121 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
122 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
123 src->scissor.count * sizeof(VkRect2D))) {
124 typed_memcpy(dest->scissor.scissors,
125 src->scissor.scissors, src->scissor.count);
126 dest_mask |= RADV_DYNAMIC_SCISSOR;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
131 if (dest->line_width != src->line_width) {
132 dest->line_width = src->line_width;
133 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
134 }
135 }
136
137 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
138 if (memcmp(&dest->depth_bias, &src->depth_bias,
139 sizeof(src->depth_bias))) {
140 dest->depth_bias = src->depth_bias;
141 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
142 }
143 }
144
145 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
146 if (memcmp(&dest->blend_constants, &src->blend_constants,
147 sizeof(src->blend_constants))) {
148 typed_memcpy(dest->blend_constants,
149 src->blend_constants, 4);
150 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
151 }
152 }
153
154 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
155 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
156 sizeof(src->depth_bounds))) {
157 dest->depth_bounds = src->depth_bounds;
158 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
159 }
160 }
161
162 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
163 if (memcmp(&dest->stencil_compare_mask,
164 &src->stencil_compare_mask,
165 sizeof(src->stencil_compare_mask))) {
166 dest->stencil_compare_mask = src->stencil_compare_mask;
167 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
168 }
169 }
170
171 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
172 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
173 sizeof(src->stencil_write_mask))) {
174 dest->stencil_write_mask = src->stencil_write_mask;
175 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
176 }
177 }
178
179 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
180 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
181 sizeof(src->stencil_reference))) {
182 dest->stencil_reference = src->stencil_reference;
183 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
184 }
185 }
186
187 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
188 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
189 src->discard_rectangle.count * sizeof(VkRect2D))) {
190 typed_memcpy(dest->discard_rectangle.rectangles,
191 src->discard_rectangle.rectangles,
192 src->discard_rectangle.count);
193 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
194 }
195 }
196
197 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
198 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
199 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
200 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
201 memcmp(&dest->sample_location.locations,
202 &src->sample_location.locations,
203 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
204 dest->sample_location.per_pixel = src->sample_location.per_pixel;
205 dest->sample_location.grid_size = src->sample_location.grid_size;
206 typed_memcpy(dest->sample_location.locations,
207 src->sample_location.locations,
208 src->sample_location.count);
209 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
210 }
211 }
212
213 cmd_buffer->state.dirty |= dest_mask;
214 }
215
216 static void
217 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
218 struct radv_pipeline *pipeline)
219 {
220 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
221 struct radv_shader_info *info;
222
223 if (!pipeline->streamout_shader)
224 return;
225
226 info = &pipeline->streamout_shader->info.info;
227 for (int i = 0; i < MAX_SO_BUFFERS; i++)
228 so->stride_in_dw[i] = info->so.strides[i];
229
230 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
231 }
232
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
234 {
235 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
236 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
237 }
238
239 enum ring_type radv_queue_family_to_ring(int f) {
240 switch (f) {
241 case RADV_QUEUE_GENERAL:
242 return RING_GFX;
243 case RADV_QUEUE_COMPUTE:
244 return RING_COMPUTE;
245 case RADV_QUEUE_TRANSFER:
246 return RING_DMA;
247 default:
248 unreachable("Unknown queue family");
249 }
250 }
251
252 static VkResult radv_create_cmd_buffer(
253 struct radv_device * device,
254 struct radv_cmd_pool * pool,
255 VkCommandBufferLevel level,
256 VkCommandBuffer* pCommandBuffer)
257 {
258 struct radv_cmd_buffer *cmd_buffer;
259 unsigned ring;
260 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
262 if (cmd_buffer == NULL)
263 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 cmd_buffer->device = device;
267 cmd_buffer->pool = pool;
268 cmd_buffer->level = level;
269
270 if (pool) {
271 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
272 cmd_buffer->queue_family_index = pool->queue_family_index;
273
274 } else {
275 /* Init the pool_link so we can safely call list_del when we destroy
276 * the command buffer
277 */
278 list_inithead(&cmd_buffer->pool_link);
279 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
280 }
281
282 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
283
284 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
285 if (!cmd_buffer->cs) {
286 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
287 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
288 }
289
290 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
291
292 list_inithead(&cmd_buffer->upload.list);
293
294 return VK_SUCCESS;
295 }
296
297 static void
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
299 {
300 list_del(&cmd_buffer->pool_link);
301
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
303 &cmd_buffer->upload.list, list) {
304 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
305 list_del(&up->list);
306 free(up);
307 }
308
309 if (cmd_buffer->upload.upload_bo)
310 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
311 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
314 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
315
316 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
317 }
318
319 static VkResult
320 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
321 {
322 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
323
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
325 &cmd_buffer->upload.list, list) {
326 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
327 list_del(&up->list);
328 free(up);
329 }
330
331 cmd_buffer->push_constant_stages = 0;
332 cmd_buffer->scratch_size_needed = 0;
333 cmd_buffer->compute_scratch_size_needed = 0;
334 cmd_buffer->esgs_ring_size_needed = 0;
335 cmd_buffer->gsvs_ring_size_needed = 0;
336 cmd_buffer->tess_rings_needed = false;
337 cmd_buffer->sample_positions_needed = false;
338
339 if (cmd_buffer->upload.upload_bo)
340 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
341 cmd_buffer->upload.upload_bo);
342 cmd_buffer->upload.offset = 0;
343
344 cmd_buffer->record_result = VK_SUCCESS;
345
346 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
347
348 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
349 cmd_buffer->descriptors[i].dirty = 0;
350 cmd_buffer->descriptors[i].valid = 0;
351 cmd_buffer->descriptors[i].push_dirty = false;
352 }
353
354 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
355 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
356 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
357 unsigned fence_offset, eop_bug_offset;
358 void *fence_ptr;
359
360 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
361 &fence_ptr);
362
363 cmd_buffer->gfx9_fence_va =
364 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
365 cmd_buffer->gfx9_fence_va += fence_offset;
366
367 /* Allocate a buffer for the EOP bug on GFX9. */
368 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
369 &eop_bug_offset, &fence_ptr);
370 cmd_buffer->gfx9_eop_bug_va =
371 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
372 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
373 }
374
375 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
376
377 return cmd_buffer->record_result;
378 }
379
380 static bool
381 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
382 uint64_t min_needed)
383 {
384 uint64_t new_size;
385 struct radeon_winsys_bo *bo;
386 struct radv_cmd_buffer_upload *upload;
387 struct radv_device *device = cmd_buffer->device;
388
389 new_size = MAX2(min_needed, 16 * 1024);
390 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
391
392 bo = device->ws->buffer_create(device->ws,
393 new_size, 4096,
394 RADEON_DOMAIN_GTT,
395 RADEON_FLAG_CPU_ACCESS|
396 RADEON_FLAG_NO_INTERPROCESS_SHARING |
397 RADEON_FLAG_32BIT,
398 RADV_BO_PRIORITY_UPLOAD_BUFFER);
399
400 if (!bo) {
401 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
402 return false;
403 }
404
405 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
406 if (cmd_buffer->upload.upload_bo) {
407 upload = malloc(sizeof(*upload));
408
409 if (!upload) {
410 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
411 device->ws->buffer_destroy(bo);
412 return false;
413 }
414
415 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
416 list_add(&upload->list, &cmd_buffer->upload.list);
417 }
418
419 cmd_buffer->upload.upload_bo = bo;
420 cmd_buffer->upload.size = new_size;
421 cmd_buffer->upload.offset = 0;
422 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
423
424 if (!cmd_buffer->upload.map) {
425 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
426 return false;
427 }
428
429 return true;
430 }
431
432 bool
433 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
434 unsigned size,
435 unsigned alignment,
436 unsigned *out_offset,
437 void **ptr)
438 {
439 assert(util_is_power_of_two_nonzero(alignment));
440
441 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
442 if (offset + size > cmd_buffer->upload.size) {
443 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
444 return false;
445 offset = 0;
446 }
447
448 *out_offset = offset;
449 *ptr = cmd_buffer->upload.map + offset;
450
451 cmd_buffer->upload.offset = offset + size;
452 return true;
453 }
454
455 bool
456 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
457 unsigned size, unsigned alignment,
458 const void *data, unsigned *out_offset)
459 {
460 uint8_t *ptr;
461
462 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
463 out_offset, (void **)&ptr))
464 return false;
465
466 if (ptr)
467 memcpy(ptr, data, size);
468
469 return true;
470 }
471
472 static void
473 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
474 unsigned count, const uint32_t *data)
475 {
476 struct radeon_cmdbuf *cs = cmd_buffer->cs;
477
478 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
479
480 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
481 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
482 S_370_WR_CONFIRM(1) |
483 S_370_ENGINE_SEL(V_370_ME));
484 radeon_emit(cs, va);
485 radeon_emit(cs, va >> 32);
486 radeon_emit_array(cs, data, count);
487 }
488
489 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
490 {
491 struct radv_device *device = cmd_buffer->device;
492 struct radeon_cmdbuf *cs = cmd_buffer->cs;
493 uint64_t va;
494
495 va = radv_buffer_get_va(device->trace_bo);
496 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
497 va += 4;
498
499 ++cmd_buffer->state.trace_id;
500 radv_emit_write_data_packet(cmd_buffer, va, 1,
501 &cmd_buffer->state.trace_id);
502
503 radeon_check_space(cmd_buffer->device->ws, cs, 2);
504
505 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
506 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
507 }
508
509 static void
510 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
511 enum radv_cmd_flush_bits flags)
512 {
513 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
514 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
515 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
516
517 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
518
519 /* Force wait for graphics or compute engines to be idle. */
520 si_cs_emit_cache_flush(cmd_buffer->cs,
521 cmd_buffer->device->physical_device->rad_info.chip_class,
522 &cmd_buffer->gfx9_fence_idx,
523 cmd_buffer->gfx9_fence_va,
524 radv_cmd_buffer_uses_mec(cmd_buffer),
525 flags, cmd_buffer->gfx9_eop_bug_va);
526 }
527
528 if (unlikely(cmd_buffer->device->trace_bo))
529 radv_cmd_buffer_trace_emit(cmd_buffer);
530 }
531
532 static void
533 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
534 struct radv_pipeline *pipeline, enum ring_type ring)
535 {
536 struct radv_device *device = cmd_buffer->device;
537 uint32_t data[2];
538 uint64_t va;
539
540 va = radv_buffer_get_va(device->trace_bo);
541
542 switch (ring) {
543 case RING_GFX:
544 va += 8;
545 break;
546 case RING_COMPUTE:
547 va += 16;
548 break;
549 default:
550 assert(!"invalid ring type");
551 }
552
553 data[0] = (uintptr_t)pipeline;
554 data[1] = (uintptr_t)pipeline >> 32;
555
556 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
557 }
558
559 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
560 VkPipelineBindPoint bind_point,
561 struct radv_descriptor_set *set,
562 unsigned idx)
563 {
564 struct radv_descriptor_state *descriptors_state =
565 radv_get_descriptors_state(cmd_buffer, bind_point);
566
567 descriptors_state->sets[idx] = set;
568
569 descriptors_state->valid |= (1u << idx); /* active descriptors */
570 descriptors_state->dirty |= (1u << idx);
571 }
572
573 static void
574 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
575 VkPipelineBindPoint bind_point)
576 {
577 struct radv_descriptor_state *descriptors_state =
578 radv_get_descriptors_state(cmd_buffer, bind_point);
579 struct radv_device *device = cmd_buffer->device;
580 uint32_t data[MAX_SETS * 2] = {};
581 uint64_t va;
582 unsigned i;
583 va = radv_buffer_get_va(device->trace_bo) + 24;
584
585 for_each_bit(i, descriptors_state->valid) {
586 struct radv_descriptor_set *set = descriptors_state->sets[i];
587 data[i * 2] = (uint64_t)(uintptr_t)set;
588 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
589 }
590
591 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
592 }
593
594 struct radv_userdata_info *
595 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
596 gl_shader_stage stage,
597 int idx)
598 {
599 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
600 return &shader->info.user_sgprs_locs.shader_data[idx];
601 }
602
603 static void
604 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
605 struct radv_pipeline *pipeline,
606 gl_shader_stage stage,
607 int idx, uint64_t va)
608 {
609 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
610 uint32_t base_reg = pipeline->user_data_0[stage];
611 if (loc->sgpr_idx == -1)
612 return;
613
614 assert(loc->num_sgprs == 1);
615
616 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
617 base_reg + loc->sgpr_idx * 4, va, false);
618 }
619
620 static void
621 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
622 struct radv_pipeline *pipeline,
623 struct radv_descriptor_state *descriptors_state,
624 gl_shader_stage stage)
625 {
626 struct radv_device *device = cmd_buffer->device;
627 struct radeon_cmdbuf *cs = cmd_buffer->cs;
628 uint32_t sh_base = pipeline->user_data_0[stage];
629 struct radv_userdata_locations *locs =
630 &pipeline->shaders[stage]->info.user_sgprs_locs;
631 unsigned mask = locs->descriptor_sets_enabled;
632
633 mask &= descriptors_state->dirty & descriptors_state->valid;
634
635 while (mask) {
636 int start, count;
637
638 u_bit_scan_consecutive_range(&mask, &start, &count);
639
640 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
641 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
642
643 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
644 for (int i = 0; i < count; i++) {
645 struct radv_descriptor_set *set =
646 descriptors_state->sets[start + i];
647
648 radv_emit_shader_pointer_body(device, cs, set->va, true);
649 }
650 }
651 }
652
653 /**
654 * Convert the user sample locations to hardware sample locations (the values
655 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
656 */
657 static void
658 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
659 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
660 {
661 uint32_t x_offset = x % state->grid_size.width;
662 uint32_t y_offset = y % state->grid_size.height;
663 uint32_t num_samples = (uint32_t)state->per_pixel;
664 VkSampleLocationEXT *user_locs;
665 uint32_t pixel_offset;
666
667 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
668
669 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
670 user_locs = &state->locations[pixel_offset];
671
672 for (uint32_t i = 0; i < num_samples; i++) {
673 float shifted_pos_x = user_locs[i].x - 0.5;
674 float shifted_pos_y = user_locs[i].y - 0.5;
675
676 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
677 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
678
679 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
680 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
681 }
682 }
683
684 /**
685 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
686 * locations.
687 */
688 static void
689 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
690 uint32_t *sample_locs_pixel)
691 {
692 for (uint32_t i = 0; i < num_samples; i++) {
693 uint32_t sample_reg_idx = i / 4;
694 uint32_t sample_loc_idx = i % 4;
695 int32_t pos_x = sample_locs[i].x;
696 int32_t pos_y = sample_locs[i].y;
697
698 uint32_t shift_x = 8 * sample_loc_idx;
699 uint32_t shift_y = shift_x + 4;
700
701 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
702 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
703 }
704 }
705
706 /**
707 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
708 * sample locations.
709 */
710 static uint64_t
711 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
712 VkOffset2D *sample_locs,
713 uint32_t num_samples)
714 {
715 uint32_t centroid_priorities[num_samples];
716 uint32_t sample_mask = num_samples - 1;
717 uint32_t distances[num_samples];
718 uint64_t centroid_priority = 0;
719
720 /* Compute the distances from center for each sample. */
721 for (int i = 0; i < num_samples; i++) {
722 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
723 (sample_locs[i].y * sample_locs[i].y);
724 }
725
726 /* Compute the centroid priorities by looking at the distances array. */
727 for (int i = 0; i < num_samples; i++) {
728 uint32_t min_idx = 0;
729
730 for (int j = 1; j < num_samples; j++) {
731 if (distances[j] < distances[min_idx])
732 min_idx = j;
733 }
734
735 centroid_priorities[i] = min_idx;
736 distances[min_idx] = 0xffffffff;
737 }
738
739 /* Compute the final centroid priority. */
740 for (int i = 0; i < 8; i++) {
741 centroid_priority |=
742 centroid_priorities[i & sample_mask] << (i * 4);
743 }
744
745 return centroid_priority << 32 | centroid_priority;
746 }
747
748 /**
749 * Emit the sample locations that are specified with VK_EXT_sample_locations.
750 */
751 static void
752 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
753 {
754 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
755 struct radv_multisample_state *ms = &pipeline->graphics.ms;
756 struct radv_sample_locations_state *sample_location =
757 &cmd_buffer->state.dynamic.sample_location;
758 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
759 struct radeon_cmdbuf *cs = cmd_buffer->cs;
760 uint32_t sample_locs_pixel[4][2] = {};
761 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
762 uint32_t max_sample_dist = 0;
763 uint64_t centroid_priority;
764
765 if (!cmd_buffer->state.dynamic.sample_location.count)
766 return;
767
768 /* Convert the user sample locations to hardware sample locations. */
769 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
770 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
771 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
772 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
773
774 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
775 for (uint32_t i = 0; i < 4; i++) {
776 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
777 sample_locs_pixel[i]);
778 }
779
780 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
781 centroid_priority =
782 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
783 num_samples);
784
785 /* Compute the maximum sample distance from the specified locations. */
786 for (uint32_t i = 0; i < num_samples; i++) {
787 VkOffset2D offset = sample_locs[0][i];
788 max_sample_dist = MAX2(max_sample_dist,
789 MAX2(abs(offset.x), abs(offset.y)));
790 }
791
792 /* Emit the specified user sample locations. */
793 switch (num_samples) {
794 case 2:
795 case 4:
796 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
797 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
798 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
799 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
800 break;
801 case 8:
802 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
803 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
804 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
805 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
806 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
807 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
808 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
809 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
810 break;
811 default:
812 unreachable("invalid number of samples");
813 }
814
815 /* Emit the maximum sample distance and the centroid priority. */
816 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
817
818 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
819 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
820
821 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
822 radeon_emit(cs, pa_sc_aa_config);
823
824 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
825 radeon_emit(cs, centroid_priority);
826 radeon_emit(cs, centroid_priority >> 32);
827
828 /* GFX9: Flush DFSM when the AA mode changes. */
829 if (cmd_buffer->device->dfsm_allowed) {
830 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
831 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
832 }
833
834 cmd_buffer->state.context_roll_without_scissor_emitted = true;
835 }
836
837 static void
838 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
839 struct radv_pipeline *pipeline,
840 gl_shader_stage stage,
841 int idx, int count, uint32_t *values)
842 {
843 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
844 uint32_t base_reg = pipeline->user_data_0[stage];
845 if (loc->sgpr_idx == -1)
846 return;
847
848 assert(loc->num_sgprs == count);
849
850 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
851 radeon_emit_array(cmd_buffer->cs, values, count);
852 }
853
854 static void
855 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
856 struct radv_pipeline *pipeline)
857 {
858 int num_samples = pipeline->graphics.ms.num_samples;
859 struct radv_multisample_state *ms = &pipeline->graphics.ms;
860 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
861
862 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
863 cmd_buffer->sample_positions_needed = true;
864
865 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
866 return;
867
868 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
869 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
870 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
871
872 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
873
874 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
875
876 /* GFX9: Flush DFSM when the AA mode changes. */
877 if (cmd_buffer->device->dfsm_allowed) {
878 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
879 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
880 }
881
882 cmd_buffer->state.context_roll_without_scissor_emitted = true;
883 }
884
885 static void
886 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
887 struct radv_shader_variant *shader)
888 {
889 uint64_t va;
890
891 if (!shader)
892 return;
893
894 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
895
896 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
897 }
898
899 static void
900 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
901 struct radv_pipeline *pipeline,
902 bool vertex_stage_only)
903 {
904 struct radv_cmd_state *state = &cmd_buffer->state;
905 uint32_t mask = state->prefetch_L2_mask;
906
907 if (vertex_stage_only) {
908 /* Fast prefetch path for starting draws as soon as possible.
909 */
910 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
911 RADV_PREFETCH_VBO_DESCRIPTORS);
912 }
913
914 if (mask & RADV_PREFETCH_VS)
915 radv_emit_shader_prefetch(cmd_buffer,
916 pipeline->shaders[MESA_SHADER_VERTEX]);
917
918 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
919 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
920
921 if (mask & RADV_PREFETCH_TCS)
922 radv_emit_shader_prefetch(cmd_buffer,
923 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
924
925 if (mask & RADV_PREFETCH_TES)
926 radv_emit_shader_prefetch(cmd_buffer,
927 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
928
929 if (mask & RADV_PREFETCH_GS) {
930 radv_emit_shader_prefetch(cmd_buffer,
931 pipeline->shaders[MESA_SHADER_GEOMETRY]);
932 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
933 }
934
935 if (mask & RADV_PREFETCH_PS)
936 radv_emit_shader_prefetch(cmd_buffer,
937 pipeline->shaders[MESA_SHADER_FRAGMENT]);
938
939 state->prefetch_L2_mask &= ~mask;
940 }
941
942 static void
943 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
944 {
945 if (!cmd_buffer->device->physical_device->rbplus_allowed)
946 return;
947
948 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
949 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
950 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
951
952 unsigned sx_ps_downconvert = 0;
953 unsigned sx_blend_opt_epsilon = 0;
954 unsigned sx_blend_opt_control = 0;
955
956 for (unsigned i = 0; i < subpass->color_count; ++i) {
957 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
958 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
959 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
960 continue;
961 }
962
963 int idx = subpass->color_attachments[i].attachment;
964 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
965
966 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
967 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
968 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
969 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
970
971 bool has_alpha, has_rgb;
972
973 /* Set if RGB and A are present. */
974 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
975
976 if (format == V_028C70_COLOR_8 ||
977 format == V_028C70_COLOR_16 ||
978 format == V_028C70_COLOR_32)
979 has_rgb = !has_alpha;
980 else
981 has_rgb = true;
982
983 /* Check the colormask and export format. */
984 if (!(colormask & 0x7))
985 has_rgb = false;
986 if (!(colormask & 0x8))
987 has_alpha = false;
988
989 if (spi_format == V_028714_SPI_SHADER_ZERO) {
990 has_rgb = false;
991 has_alpha = false;
992 }
993
994 /* Disable value checking for disabled channels. */
995 if (!has_rgb)
996 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
997 if (!has_alpha)
998 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
999
1000 /* Enable down-conversion for 32bpp and smaller formats. */
1001 switch (format) {
1002 case V_028C70_COLOR_8:
1003 case V_028C70_COLOR_8_8:
1004 case V_028C70_COLOR_8_8_8_8:
1005 /* For 1 and 2-channel formats, use the superset thereof. */
1006 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1007 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1008 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1009 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1010 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1011 }
1012 break;
1013
1014 case V_028C70_COLOR_5_6_5:
1015 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1016 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1017 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1018 }
1019 break;
1020
1021 case V_028C70_COLOR_1_5_5_5:
1022 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1023 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1024 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1025 }
1026 break;
1027
1028 case V_028C70_COLOR_4_4_4_4:
1029 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1030 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1031 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1032 }
1033 break;
1034
1035 case V_028C70_COLOR_32:
1036 if (swap == V_028C70_SWAP_STD &&
1037 spi_format == V_028714_SPI_SHADER_32_R)
1038 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1039 else if (swap == V_028C70_SWAP_ALT_REV &&
1040 spi_format == V_028714_SPI_SHADER_32_AR)
1041 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1042 break;
1043
1044 case V_028C70_COLOR_16:
1045 case V_028C70_COLOR_16_16:
1046 /* For 1-channel formats, use the superset thereof. */
1047 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1048 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1049 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1050 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1051 if (swap == V_028C70_SWAP_STD ||
1052 swap == V_028C70_SWAP_STD_REV)
1053 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1054 else
1055 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1056 }
1057 break;
1058
1059 case V_028C70_COLOR_10_11_11:
1060 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1061 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1062 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1063 }
1064 break;
1065
1066 case V_028C70_COLOR_2_10_10_10:
1067 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1068 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1069 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1070 }
1071 break;
1072 }
1073 }
1074
1075 for (unsigned i = subpass->color_count; i < 8; ++i) {
1076 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1077 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1078 }
1079 /* TODO: avoid redundantly setting context registers */
1080 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1081 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1082 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1083 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1084
1085 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1086 }
1087
1088 static void
1089 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1090 {
1091 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1092
1093 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1094 return;
1095
1096 radv_update_multisample_state(cmd_buffer, pipeline);
1097
1098 cmd_buffer->scratch_size_needed =
1099 MAX2(cmd_buffer->scratch_size_needed,
1100 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1101
1102 if (!cmd_buffer->state.emitted_pipeline ||
1103 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1104 pipeline->graphics.can_use_guardband)
1105 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1106
1107 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1108
1109 if (!cmd_buffer->state.emitted_pipeline ||
1110 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1111 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1112 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1113 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1114 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1115 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1116 }
1117
1118 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1119 if (!pipeline->shaders[i])
1120 continue;
1121
1122 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1123 pipeline->shaders[i]->bo);
1124 }
1125
1126 if (radv_pipeline_has_gs(pipeline))
1127 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1128 pipeline->gs_copy_shader->bo);
1129
1130 if (unlikely(cmd_buffer->device->trace_bo))
1131 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1132
1133 cmd_buffer->state.emitted_pipeline = pipeline;
1134
1135 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1136 }
1137
1138 static void
1139 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1140 {
1141 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1142 cmd_buffer->state.dynamic.viewport.viewports);
1143 }
1144
1145 static void
1146 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1147 {
1148 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1149
1150 si_write_scissors(cmd_buffer->cs, 0, count,
1151 cmd_buffer->state.dynamic.scissor.scissors,
1152 cmd_buffer->state.dynamic.viewport.viewports,
1153 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1154
1155 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1156 }
1157
1158 static void
1159 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1160 {
1161 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1162 return;
1163
1164 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1165 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1166 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1167 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1168 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1169 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1170 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1171 }
1172 }
1173
1174 static void
1175 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1176 {
1177 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1178
1179 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1180 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1181 }
1182
1183 static void
1184 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1185 {
1186 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1187
1188 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1189 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1190 }
1191
1192 static void
1193 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1194 {
1195 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1196
1197 radeon_set_context_reg_seq(cmd_buffer->cs,
1198 R_028430_DB_STENCILREFMASK, 2);
1199 radeon_emit(cmd_buffer->cs,
1200 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1201 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1202 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1203 S_028430_STENCILOPVAL(1));
1204 radeon_emit(cmd_buffer->cs,
1205 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1206 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1207 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1208 S_028434_STENCILOPVAL_BF(1));
1209 }
1210
1211 static void
1212 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1213 {
1214 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1215
1216 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1217 fui(d->depth_bounds.min));
1218 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1219 fui(d->depth_bounds.max));
1220 }
1221
1222 static void
1223 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1224 {
1225 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1226 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1227 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1228
1229
1230 radeon_set_context_reg_seq(cmd_buffer->cs,
1231 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1232 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1233 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1234 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1235 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1236 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1237 }
1238
1239 static void
1240 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1241 int index,
1242 struct radv_attachment_info *att,
1243 struct radv_image *image,
1244 VkImageLayout layout)
1245 {
1246 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1247 struct radv_color_buffer_info *cb = &att->cb;
1248 uint32_t cb_color_info = cb->cb_color_info;
1249
1250 if (!radv_layout_dcc_compressed(image, layout,
1251 radv_image_queue_family_mask(image,
1252 cmd_buffer->queue_family_index,
1253 cmd_buffer->queue_family_index))) {
1254 cb_color_info &= C_028C70_DCC_ENABLE;
1255 }
1256
1257 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1258 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1259 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1260 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1261 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1262 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1263 radeon_emit(cmd_buffer->cs, cb_color_info);
1264 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1265 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1266 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1267 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1268 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1269 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1270
1271 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1272 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1273 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1274
1275 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1276 cb->cb_mrt_epitch);
1277 } else {
1278 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1279 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1280 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1281 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1282 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1283 radeon_emit(cmd_buffer->cs, cb_color_info);
1284 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1285 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1286 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1287 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1288 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1289 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1290
1291 if (is_vi) { /* DCC BASE */
1292 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1293 }
1294 }
1295
1296 if (radv_image_has_dcc(image)) {
1297 /* Drawing with DCC enabled also compresses colorbuffers. */
1298 radv_update_dcc_metadata(cmd_buffer, image, true);
1299 }
1300 }
1301
1302 static void
1303 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1304 struct radv_ds_buffer_info *ds,
1305 struct radv_image *image, VkImageLayout layout,
1306 bool requires_cond_exec)
1307 {
1308 uint32_t db_z_info = ds->db_z_info;
1309 uint32_t db_z_info_reg;
1310
1311 if (!radv_image_is_tc_compat_htile(image))
1312 return;
1313
1314 if (!radv_layout_has_htile(image, layout,
1315 radv_image_queue_family_mask(image,
1316 cmd_buffer->queue_family_index,
1317 cmd_buffer->queue_family_index))) {
1318 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1319 }
1320
1321 db_z_info &= C_028040_ZRANGE_PRECISION;
1322
1323 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1324 db_z_info_reg = R_028038_DB_Z_INFO;
1325 } else {
1326 db_z_info_reg = R_028040_DB_Z_INFO;
1327 }
1328
1329 /* When we don't know the last fast clear value we need to emit a
1330 * conditional packet that will eventually skip the following
1331 * SET_CONTEXT_REG packet.
1332 */
1333 if (requires_cond_exec) {
1334 uint64_t va = radv_buffer_get_va(image->bo);
1335 va += image->offset + image->tc_compat_zrange_offset;
1336
1337 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1338 radeon_emit(cmd_buffer->cs, va);
1339 radeon_emit(cmd_buffer->cs, va >> 32);
1340 radeon_emit(cmd_buffer->cs, 0);
1341 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1342 }
1343
1344 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1345 }
1346
1347 static void
1348 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1349 struct radv_ds_buffer_info *ds,
1350 struct radv_image *image,
1351 VkImageLayout layout)
1352 {
1353 uint32_t db_z_info = ds->db_z_info;
1354 uint32_t db_stencil_info = ds->db_stencil_info;
1355
1356 if (!radv_layout_has_htile(image, layout,
1357 radv_image_queue_family_mask(image,
1358 cmd_buffer->queue_family_index,
1359 cmd_buffer->queue_family_index))) {
1360 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1361 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1362 }
1363
1364 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1365 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1366
1367
1368 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1369 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1370 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1371 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1372 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1373
1374 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1375 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1376 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1377 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1378 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1379 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1380 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1381 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1382 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1383 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1384 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1385
1386 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1387 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1388 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1389 } else {
1390 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1391
1392 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1393 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1394 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1395 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1396 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1397 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1398 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1399 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1400 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1401 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1402
1403 }
1404
1405 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1406 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1407
1408 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1409 ds->pa_su_poly_offset_db_fmt_cntl);
1410 }
1411
1412 /**
1413 * Update the fast clear depth/stencil values if the image is bound as a
1414 * depth/stencil buffer.
1415 */
1416 static void
1417 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1418 struct radv_image *image,
1419 VkClearDepthStencilValue ds_clear_value,
1420 VkImageAspectFlags aspects)
1421 {
1422 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1423 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1424 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1425 struct radv_attachment_info *att;
1426 uint32_t att_idx;
1427
1428 if (!framebuffer || !subpass)
1429 return;
1430
1431 if (!subpass->depth_stencil_attachment)
1432 return;
1433
1434 att_idx = subpass->depth_stencil_attachment->attachment;
1435 att = &framebuffer->attachments[att_idx];
1436 if (att->attachment->image != image)
1437 return;
1438
1439 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1440 radeon_emit(cs, ds_clear_value.stencil);
1441 radeon_emit(cs, fui(ds_clear_value.depth));
1442
1443 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1444 * only needed when clearing Z to 0.0.
1445 */
1446 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1447 ds_clear_value.depth == 0.0) {
1448 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1449
1450 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1451 layout, false);
1452 }
1453
1454 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1455 }
1456
1457 /**
1458 * Set the clear depth/stencil values to the image's metadata.
1459 */
1460 static void
1461 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1462 struct radv_image *image,
1463 VkClearDepthStencilValue ds_clear_value,
1464 VkImageAspectFlags aspects)
1465 {
1466 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1467 uint64_t va = radv_buffer_get_va(image->bo);
1468 unsigned reg_offset = 0, reg_count = 0;
1469
1470 va += image->offset + image->clear_value_offset;
1471
1472 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1473 ++reg_count;
1474 } else {
1475 ++reg_offset;
1476 va += 4;
1477 }
1478 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1479 ++reg_count;
1480
1481 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1482 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1483 S_370_WR_CONFIRM(1) |
1484 S_370_ENGINE_SEL(V_370_PFP));
1485 radeon_emit(cs, va);
1486 radeon_emit(cs, va >> 32);
1487 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1488 radeon_emit(cs, ds_clear_value.stencil);
1489 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1490 radeon_emit(cs, fui(ds_clear_value.depth));
1491 }
1492
1493 /**
1494 * Update the TC-compat metadata value for this image.
1495 */
1496 static void
1497 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1498 struct radv_image *image,
1499 uint32_t value)
1500 {
1501 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1502 uint64_t va = radv_buffer_get_va(image->bo);
1503 va += image->offset + image->tc_compat_zrange_offset;
1504
1505 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1506 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1507 S_370_WR_CONFIRM(1) |
1508 S_370_ENGINE_SEL(V_370_PFP));
1509 radeon_emit(cs, va);
1510 radeon_emit(cs, va >> 32);
1511 radeon_emit(cs, value);
1512 }
1513
1514 static void
1515 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1516 struct radv_image *image,
1517 VkClearDepthStencilValue ds_clear_value)
1518 {
1519 uint64_t va = radv_buffer_get_va(image->bo);
1520 va += image->offset + image->tc_compat_zrange_offset;
1521 uint32_t cond_val;
1522
1523 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1524 * depth clear value is 0.0f.
1525 */
1526 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1527
1528 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1529 }
1530
1531 /**
1532 * Update the clear depth/stencil values for this image.
1533 */
1534 void
1535 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1536 struct radv_image *image,
1537 VkClearDepthStencilValue ds_clear_value,
1538 VkImageAspectFlags aspects)
1539 {
1540 assert(radv_image_has_htile(image));
1541
1542 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1543
1544 if (radv_image_is_tc_compat_htile(image) &&
1545 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1546 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1547 ds_clear_value);
1548 }
1549
1550 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1551 aspects);
1552 }
1553
1554 /**
1555 * Load the clear depth/stencil values from the image's metadata.
1556 */
1557 static void
1558 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1559 struct radv_image *image)
1560 {
1561 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1562 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1563 uint64_t va = radv_buffer_get_va(image->bo);
1564 unsigned reg_offset = 0, reg_count = 0;
1565
1566 va += image->offset + image->clear_value_offset;
1567
1568 if (!radv_image_has_htile(image))
1569 return;
1570
1571 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1572 ++reg_count;
1573 } else {
1574 ++reg_offset;
1575 va += 4;
1576 }
1577 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1578 ++reg_count;
1579
1580 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1581
1582 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1583 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1584 radeon_emit(cs, va);
1585 radeon_emit(cs, va >> 32);
1586 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1587 radeon_emit(cs, reg_count);
1588 } else {
1589 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1590 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1591 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1592 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1593 radeon_emit(cs, va);
1594 radeon_emit(cs, va >> 32);
1595 radeon_emit(cs, reg >> 2);
1596 radeon_emit(cs, 0);
1597
1598 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1599 radeon_emit(cs, 0);
1600 }
1601 }
1602
1603 /*
1604 * With DCC some colors don't require CMASK elimination before being
1605 * used as a texture. This sets a predicate value to determine if the
1606 * cmask eliminate is required.
1607 */
1608 void
1609 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1610 struct radv_image *image,
1611 const VkImageSubresourceRange *range, bool value)
1612 {
1613 uint64_t pred_val = value;
1614 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1615 uint32_t level_count = radv_get_levelCount(image, range);
1616 uint32_t count = 2 * level_count;
1617
1618 assert(radv_image_has_dcc(image));
1619
1620 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1621 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1622 S_370_WR_CONFIRM(1) |
1623 S_370_ENGINE_SEL(V_370_PFP));
1624 radeon_emit(cmd_buffer->cs, va);
1625 radeon_emit(cmd_buffer->cs, va >> 32);
1626
1627 for (uint32_t l = 0; l < level_count; l++) {
1628 radeon_emit(cmd_buffer->cs, pred_val);
1629 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1630 }
1631 }
1632
1633 /**
1634 * Update the DCC predicate to reflect the compression state.
1635 */
1636 void
1637 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1638 struct radv_image *image, bool value)
1639 {
1640 uint64_t pred_val = value;
1641 uint64_t va = radv_buffer_get_va(image->bo);
1642 va += image->offset + image->dcc_pred_offset;
1643
1644 assert(radv_image_has_dcc(image));
1645
1646 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1647 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1648 S_370_WR_CONFIRM(1) |
1649 S_370_ENGINE_SEL(V_370_PFP));
1650 radeon_emit(cmd_buffer->cs, va);
1651 radeon_emit(cmd_buffer->cs, va >> 32);
1652 radeon_emit(cmd_buffer->cs, pred_val);
1653 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1654 }
1655
1656 /**
1657 * Update the fast clear color values if the image is bound as a color buffer.
1658 */
1659 static void
1660 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1661 struct radv_image *image,
1662 int cb_idx,
1663 uint32_t color_values[2])
1664 {
1665 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1666 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1667 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1668 struct radv_attachment_info *att;
1669 uint32_t att_idx;
1670
1671 if (!framebuffer || !subpass)
1672 return;
1673
1674 att_idx = subpass->color_attachments[cb_idx].attachment;
1675 if (att_idx == VK_ATTACHMENT_UNUSED)
1676 return;
1677
1678 att = &framebuffer->attachments[att_idx];
1679 if (att->attachment->image != image)
1680 return;
1681
1682 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1683 radeon_emit(cs, color_values[0]);
1684 radeon_emit(cs, color_values[1]);
1685
1686 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1687 }
1688
1689 /**
1690 * Set the clear color values to the image's metadata.
1691 */
1692 static void
1693 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1694 struct radv_image *image,
1695 const VkImageSubresourceRange *range,
1696 uint32_t color_values[2])
1697 {
1698 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1699 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1700 uint32_t level_count = radv_get_levelCount(image, range);
1701 uint32_t count = 2 * level_count;
1702
1703 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1704
1705 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1706 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1707 S_370_WR_CONFIRM(1) |
1708 S_370_ENGINE_SEL(V_370_PFP));
1709 radeon_emit(cs, va);
1710 radeon_emit(cs, va >> 32);
1711
1712 for (uint32_t l = 0; l < level_count; l++) {
1713 radeon_emit(cs, color_values[0]);
1714 radeon_emit(cs, color_values[1]);
1715 }
1716 }
1717
1718 /**
1719 * Update the clear color values for this image.
1720 */
1721 void
1722 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1723 const struct radv_image_view *iview,
1724 int cb_idx,
1725 uint32_t color_values[2])
1726 {
1727 struct radv_image *image = iview->image;
1728 VkImageSubresourceRange range = {
1729 .aspectMask = iview->aspect_mask,
1730 .baseMipLevel = iview->base_mip,
1731 .levelCount = iview->level_count,
1732 .baseArrayLayer = iview->base_layer,
1733 .layerCount = iview->layer_count,
1734 };
1735
1736 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1737
1738 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1739
1740 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1741 color_values);
1742 }
1743
1744 /**
1745 * Load the clear color values from the image's metadata.
1746 */
1747 static void
1748 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1749 struct radv_image *image,
1750 int cb_idx)
1751 {
1752 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1753 uint64_t va = radv_buffer_get_va(image->bo);
1754
1755 va += image->offset + image->clear_value_offset;
1756
1757 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1758 return;
1759
1760 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1761
1762 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1763 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1764 radeon_emit(cs, va);
1765 radeon_emit(cs, va >> 32);
1766 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1767 radeon_emit(cs, 2);
1768 } else {
1769 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1770 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1771 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1772 COPY_DATA_COUNT_SEL);
1773 radeon_emit(cs, va);
1774 radeon_emit(cs, va >> 32);
1775 radeon_emit(cs, reg >> 2);
1776 radeon_emit(cs, 0);
1777
1778 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1779 radeon_emit(cs, 0);
1780 }
1781 }
1782
1783 static void
1784 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1785 {
1786 int i;
1787 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1788 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1789 unsigned num_bpp64_colorbufs = 0;
1790
1791 /* this may happen for inherited secondary recording */
1792 if (!framebuffer)
1793 return;
1794
1795 for (i = 0; i < 8; ++i) {
1796 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1797 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1798 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1799 continue;
1800 }
1801
1802 int idx = subpass->color_attachments[i].attachment;
1803 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1804 struct radv_image *image = att->attachment->image;
1805 VkImageLayout layout = subpass->color_attachments[i].layout;
1806
1807 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1808
1809 assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1810 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1811 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1812
1813 radv_load_color_clear_metadata(cmd_buffer, image, i);
1814
1815 if (image->planes[0].surface.bpe >= 8)
1816 num_bpp64_colorbufs++;
1817 }
1818
1819 if (subpass->depth_stencil_attachment) {
1820 int idx = subpass->depth_stencil_attachment->attachment;
1821 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1822 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1823 struct radv_image *image = att->attachment->image;
1824 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1825 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1826 cmd_buffer->queue_family_index,
1827 cmd_buffer->queue_family_index);
1828 /* We currently don't support writing decompressed HTILE */
1829 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1830 radv_layout_is_htile_compressed(image, layout, queue_mask));
1831
1832 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1833
1834 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1835 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1836 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1837 }
1838 radv_load_ds_clear_metadata(cmd_buffer, image);
1839 } else {
1840 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1841 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1842 else
1843 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1844
1845 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1846 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1847 }
1848 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1849 S_028208_BR_X(framebuffer->width) |
1850 S_028208_BR_Y(framebuffer->height));
1851
1852 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
1853 uint8_t watermark = 4; /* Default value for GFX8. */
1854
1855 /* For optimal DCC performance. */
1856 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1857 if (num_bpp64_colorbufs >= 5) {
1858 watermark = 8;
1859 } else {
1860 watermark = 6;
1861 }
1862 }
1863
1864 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1865 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1866 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1867 }
1868
1869 if (cmd_buffer->device->dfsm_allowed) {
1870 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1871 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1872 }
1873
1874 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1875 }
1876
1877 static void
1878 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1879 {
1880 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1881 struct radv_cmd_state *state = &cmd_buffer->state;
1882
1883 if (state->index_type != state->last_index_type) {
1884 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1885 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1886 2, state->index_type);
1887 } else {
1888 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1889 radeon_emit(cs, state->index_type);
1890 }
1891
1892 state->last_index_type = state->index_type;
1893 }
1894
1895 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1896 radeon_emit(cs, state->index_va);
1897 radeon_emit(cs, state->index_va >> 32);
1898
1899 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1900 radeon_emit(cs, state->max_index_count);
1901
1902 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1903 }
1904
1905 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1906 {
1907 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1908 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1909 uint32_t pa_sc_mode_cntl_1 =
1910 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1911 uint32_t db_count_control;
1912
1913 if(!cmd_buffer->state.active_occlusion_queries) {
1914 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1915 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1916 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1917 has_perfect_queries) {
1918 /* Re-enable out-of-order rasterization if the
1919 * bound pipeline supports it and if it's has
1920 * been disabled before starting any perfect
1921 * occlusion queries.
1922 */
1923 radeon_set_context_reg(cmd_buffer->cs,
1924 R_028A4C_PA_SC_MODE_CNTL_1,
1925 pa_sc_mode_cntl_1);
1926 }
1927 }
1928 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1929 } else {
1930 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1931 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1932
1933 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1934 db_count_control =
1935 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1936 S_028004_SAMPLE_RATE(sample_rate) |
1937 S_028004_ZPASS_ENABLE(1) |
1938 S_028004_SLICE_EVEN_ENABLE(1) |
1939 S_028004_SLICE_ODD_ENABLE(1);
1940
1941 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1942 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1943 has_perfect_queries) {
1944 /* If the bound pipeline has enabled
1945 * out-of-order rasterization, we should
1946 * disable it before starting any perfect
1947 * occlusion queries.
1948 */
1949 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1950
1951 radeon_set_context_reg(cmd_buffer->cs,
1952 R_028A4C_PA_SC_MODE_CNTL_1,
1953 pa_sc_mode_cntl_1);
1954 }
1955 } else {
1956 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1957 S_028004_SAMPLE_RATE(sample_rate);
1958 }
1959 }
1960
1961 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1962
1963 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1964 }
1965
1966 static void
1967 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1968 {
1969 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1970
1971 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1972 radv_emit_viewport(cmd_buffer);
1973
1974 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1975 !cmd_buffer->device->physical_device->has_scissor_bug)
1976 radv_emit_scissor(cmd_buffer);
1977
1978 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1979 radv_emit_line_width(cmd_buffer);
1980
1981 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1982 radv_emit_blend_constants(cmd_buffer);
1983
1984 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1985 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1986 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1987 radv_emit_stencil(cmd_buffer);
1988
1989 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1990 radv_emit_depth_bounds(cmd_buffer);
1991
1992 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1993 radv_emit_depth_bias(cmd_buffer);
1994
1995 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1996 radv_emit_discard_rectangle(cmd_buffer);
1997
1998 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
1999 radv_emit_sample_locations(cmd_buffer);
2000
2001 cmd_buffer->state.dirty &= ~states;
2002 }
2003
2004 static void
2005 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2006 VkPipelineBindPoint bind_point)
2007 {
2008 struct radv_descriptor_state *descriptors_state =
2009 radv_get_descriptors_state(cmd_buffer, bind_point);
2010 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2011 unsigned bo_offset;
2012
2013 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2014 set->mapped_ptr,
2015 &bo_offset))
2016 return;
2017
2018 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2019 set->va += bo_offset;
2020 }
2021
2022 static void
2023 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2024 VkPipelineBindPoint bind_point)
2025 {
2026 struct radv_descriptor_state *descriptors_state =
2027 radv_get_descriptors_state(cmd_buffer, bind_point);
2028 uint32_t size = MAX_SETS * 4;
2029 uint32_t offset;
2030 void *ptr;
2031
2032 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2033 256, &offset, &ptr))
2034 return;
2035
2036 for (unsigned i = 0; i < MAX_SETS; i++) {
2037 uint32_t *uptr = ((uint32_t *)ptr) + i;
2038 uint64_t set_va = 0;
2039 struct radv_descriptor_set *set = descriptors_state->sets[i];
2040 if (descriptors_state->valid & (1u << i))
2041 set_va = set->va;
2042 uptr[0] = set_va & 0xffffffff;
2043 }
2044
2045 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2046 va += offset;
2047
2048 if (cmd_buffer->state.pipeline) {
2049 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2050 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2051 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2052
2053 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2054 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2055 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2056
2057 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2058 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2059 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2060
2061 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2062 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2063 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2064
2065 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2066 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2067 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2068 }
2069
2070 if (cmd_buffer->state.compute_pipeline)
2071 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2072 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2073 }
2074
2075 static void
2076 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2077 VkShaderStageFlags stages)
2078 {
2079 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2080 VK_PIPELINE_BIND_POINT_COMPUTE :
2081 VK_PIPELINE_BIND_POINT_GRAPHICS;
2082 struct radv_descriptor_state *descriptors_state =
2083 radv_get_descriptors_state(cmd_buffer, bind_point);
2084 struct radv_cmd_state *state = &cmd_buffer->state;
2085 bool flush_indirect_descriptors;
2086
2087 if (!descriptors_state->dirty)
2088 return;
2089
2090 if (descriptors_state->push_dirty)
2091 radv_flush_push_descriptors(cmd_buffer, bind_point);
2092
2093 flush_indirect_descriptors =
2094 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2095 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2096 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2097 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2098
2099 if (flush_indirect_descriptors)
2100 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2101
2102 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2103 cmd_buffer->cs,
2104 MAX_SETS * MESA_SHADER_STAGES * 4);
2105
2106 if (cmd_buffer->state.pipeline) {
2107 radv_foreach_stage(stage, stages) {
2108 if (!cmd_buffer->state.pipeline->shaders[stage])
2109 continue;
2110
2111 radv_emit_descriptor_pointers(cmd_buffer,
2112 cmd_buffer->state.pipeline,
2113 descriptors_state, stage);
2114 }
2115 }
2116
2117 if (cmd_buffer->state.compute_pipeline &&
2118 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2119 radv_emit_descriptor_pointers(cmd_buffer,
2120 cmd_buffer->state.compute_pipeline,
2121 descriptors_state,
2122 MESA_SHADER_COMPUTE);
2123 }
2124
2125 descriptors_state->dirty = 0;
2126 descriptors_state->push_dirty = false;
2127
2128 assert(cmd_buffer->cs->cdw <= cdw_max);
2129
2130 if (unlikely(cmd_buffer->device->trace_bo))
2131 radv_save_descriptors(cmd_buffer, bind_point);
2132 }
2133
2134 static void
2135 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2136 VkShaderStageFlags stages)
2137 {
2138 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2139 ? cmd_buffer->state.compute_pipeline
2140 : cmd_buffer->state.pipeline;
2141 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2142 VK_PIPELINE_BIND_POINT_COMPUTE :
2143 VK_PIPELINE_BIND_POINT_GRAPHICS;
2144 struct radv_descriptor_state *descriptors_state =
2145 radv_get_descriptors_state(cmd_buffer, bind_point);
2146 struct radv_pipeline_layout *layout = pipeline->layout;
2147 struct radv_shader_variant *shader, *prev_shader;
2148 bool need_push_constants = false;
2149 unsigned offset;
2150 void *ptr;
2151 uint64_t va;
2152
2153 stages &= cmd_buffer->push_constant_stages;
2154 if (!stages ||
2155 (!layout->push_constant_size && !layout->dynamic_offset_count))
2156 return;
2157
2158 radv_foreach_stage(stage, stages) {
2159 if (!pipeline->shaders[stage])
2160 continue;
2161
2162 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
2163 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
2164
2165 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
2166 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
2167
2168 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2169 AC_UD_INLINE_PUSH_CONSTANTS,
2170 count,
2171 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2172 }
2173
2174 if (need_push_constants) {
2175 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2176 16 * layout->dynamic_offset_count,
2177 256, &offset, &ptr))
2178 return;
2179
2180 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2181 memcpy((char*)ptr + layout->push_constant_size,
2182 descriptors_state->dynamic_buffers,
2183 16 * layout->dynamic_offset_count);
2184
2185 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2186 va += offset;
2187
2188 MAYBE_UNUSED unsigned cdw_max =
2189 radeon_check_space(cmd_buffer->device->ws,
2190 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2191
2192 prev_shader = NULL;
2193 radv_foreach_stage(stage, stages) {
2194 shader = radv_get_shader(pipeline, stage);
2195
2196 /* Avoid redundantly emitting the address for merged stages. */
2197 if (shader && shader != prev_shader) {
2198 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2199 AC_UD_PUSH_CONSTANTS, va);
2200
2201 prev_shader = shader;
2202 }
2203 }
2204 assert(cmd_buffer->cs->cdw <= cdw_max);
2205 }
2206
2207 cmd_buffer->push_constant_stages &= ~stages;
2208 }
2209
2210 static void
2211 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2212 bool pipeline_is_dirty)
2213 {
2214 if ((pipeline_is_dirty ||
2215 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2216 cmd_buffer->state.pipeline->num_vertex_bindings &&
2217 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
2218 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2219 unsigned vb_offset;
2220 void *vb_ptr;
2221 uint32_t i = 0;
2222 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2223 uint64_t va;
2224
2225 /* allocate some descriptor state for vertex buffers */
2226 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2227 &vb_offset, &vb_ptr))
2228 return;
2229
2230 for (i = 0; i < count; i++) {
2231 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2232 uint32_t offset;
2233 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2234 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2235
2236 if (!buffer)
2237 continue;
2238
2239 va = radv_buffer_get_va(buffer->bo);
2240
2241 offset = cmd_buffer->vertex_bindings[i].offset;
2242 va += offset + buffer->offset;
2243 desc[0] = va;
2244 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2245 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2246 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2247 else
2248 desc[2] = buffer->size - offset;
2249 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2250 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2251 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2252 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2253 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2254 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2255 }
2256
2257 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2258 va += vb_offset;
2259
2260 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2261 AC_UD_VS_VERTEX_BUFFERS, va);
2262
2263 cmd_buffer->state.vb_va = va;
2264 cmd_buffer->state.vb_size = count * 16;
2265 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2266 }
2267 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2268 }
2269
2270 static void
2271 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2272 {
2273 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2274 struct radv_userdata_info *loc;
2275 uint32_t base_reg;
2276
2277 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2278 if (!radv_get_shader(pipeline, stage))
2279 continue;
2280
2281 loc = radv_lookup_user_sgpr(pipeline, stage,
2282 AC_UD_STREAMOUT_BUFFERS);
2283 if (loc->sgpr_idx == -1)
2284 continue;
2285
2286 base_reg = pipeline->user_data_0[stage];
2287
2288 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2289 base_reg + loc->sgpr_idx * 4, va, false);
2290 }
2291
2292 if (pipeline->gs_copy_shader) {
2293 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2294 if (loc->sgpr_idx != -1) {
2295 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2296
2297 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2298 base_reg + loc->sgpr_idx * 4, va, false);
2299 }
2300 }
2301 }
2302
2303 static void
2304 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2305 {
2306 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2307 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2308 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2309 unsigned so_offset;
2310 void *so_ptr;
2311 uint64_t va;
2312
2313 /* Allocate some descriptor state for streamout buffers. */
2314 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2315 MAX_SO_BUFFERS * 16, 256,
2316 &so_offset, &so_ptr))
2317 return;
2318
2319 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2320 struct radv_buffer *buffer = sb[i].buffer;
2321 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2322
2323 if (!(so->enabled_mask & (1 << i)))
2324 continue;
2325
2326 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2327
2328 va += sb[i].offset;
2329
2330 /* Set the descriptor.
2331 *
2332 * On GFX8, the format must be non-INVALID, otherwise
2333 * the buffer will be considered not bound and store
2334 * instructions will be no-ops.
2335 */
2336 desc[0] = va;
2337 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2338 desc[2] = 0xffffffff;
2339 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2340 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2341 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2342 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2343 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2344 }
2345
2346 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2347 va += so_offset;
2348
2349 radv_emit_streamout_buffers(cmd_buffer, va);
2350 }
2351
2352 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2353 }
2354
2355 static void
2356 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2357 {
2358 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2359 radv_flush_streamout_descriptors(cmd_buffer);
2360 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2361 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2362 }
2363
2364 struct radv_draw_info {
2365 /**
2366 * Number of vertices.
2367 */
2368 uint32_t count;
2369
2370 /**
2371 * Index of the first vertex.
2372 */
2373 int32_t vertex_offset;
2374
2375 /**
2376 * First instance id.
2377 */
2378 uint32_t first_instance;
2379
2380 /**
2381 * Number of instances.
2382 */
2383 uint32_t instance_count;
2384
2385 /**
2386 * First index (indexed draws only).
2387 */
2388 uint32_t first_index;
2389
2390 /**
2391 * Whether it's an indexed draw.
2392 */
2393 bool indexed;
2394
2395 /**
2396 * Indirect draw parameters resource.
2397 */
2398 struct radv_buffer *indirect;
2399 uint64_t indirect_offset;
2400 uint32_t stride;
2401
2402 /**
2403 * Draw count parameters resource.
2404 */
2405 struct radv_buffer *count_buffer;
2406 uint64_t count_buffer_offset;
2407
2408 /**
2409 * Stream output parameters resource.
2410 */
2411 struct radv_buffer *strmout_buffer;
2412 uint64_t strmout_buffer_offset;
2413 };
2414
2415 static void
2416 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2417 const struct radv_draw_info *draw_info)
2418 {
2419 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2420 struct radv_cmd_state *state = &cmd_buffer->state;
2421 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2422 uint32_t ia_multi_vgt_param;
2423 int32_t primitive_reset_en;
2424
2425 /* Draw state. */
2426 ia_multi_vgt_param =
2427 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2428 draw_info->indirect,
2429 !!draw_info->strmout_buffer,
2430 draw_info->indirect ? 0 : draw_info->count);
2431
2432 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2433 if (info->chip_class >= GFX9) {
2434 radeon_set_uconfig_reg_idx(cs,
2435 R_030960_IA_MULTI_VGT_PARAM,
2436 4, ia_multi_vgt_param);
2437 } else if (info->chip_class >= GFX7) {
2438 radeon_set_context_reg_idx(cs,
2439 R_028AA8_IA_MULTI_VGT_PARAM,
2440 1, ia_multi_vgt_param);
2441 } else {
2442 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2443 ia_multi_vgt_param);
2444 }
2445 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2446 }
2447
2448 /* Primitive restart. */
2449 primitive_reset_en =
2450 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2451
2452 if (primitive_reset_en != state->last_primitive_reset_en) {
2453 state->last_primitive_reset_en = primitive_reset_en;
2454 if (info->chip_class >= GFX9) {
2455 radeon_set_uconfig_reg(cs,
2456 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2457 primitive_reset_en);
2458 } else {
2459 radeon_set_context_reg(cs,
2460 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2461 primitive_reset_en);
2462 }
2463 }
2464
2465 if (primitive_reset_en) {
2466 uint32_t primitive_reset_index =
2467 state->index_type ? 0xffffffffu : 0xffffu;
2468
2469 if (primitive_reset_index != state->last_primitive_reset_index) {
2470 radeon_set_context_reg(cs,
2471 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2472 primitive_reset_index);
2473 state->last_primitive_reset_index = primitive_reset_index;
2474 }
2475 }
2476
2477 if (draw_info->strmout_buffer) {
2478 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2479
2480 va += draw_info->strmout_buffer->offset +
2481 draw_info->strmout_buffer_offset;
2482
2483 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2484 draw_info->stride);
2485
2486 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2487 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2488 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2489 COPY_DATA_WR_CONFIRM);
2490 radeon_emit(cs, va);
2491 radeon_emit(cs, va >> 32);
2492 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2493 radeon_emit(cs, 0); /* unused */
2494
2495 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2496 }
2497 }
2498
2499 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2500 VkPipelineStageFlags src_stage_mask)
2501 {
2502 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2503 VK_PIPELINE_STAGE_TRANSFER_BIT |
2504 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2505 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2506 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2507 }
2508
2509 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2510 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2511 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2512 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2513 VK_PIPELINE_STAGE_TRANSFER_BIT |
2514 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2515 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2516 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2517 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2518 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2519 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2520 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2521 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2522 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2523 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2524 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2525 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2526 }
2527 }
2528
2529 static enum radv_cmd_flush_bits
2530 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2531 VkAccessFlags src_flags,
2532 struct radv_image *image)
2533 {
2534 bool flush_CB_meta = true, flush_DB_meta = true;
2535 enum radv_cmd_flush_bits flush_bits = 0;
2536 uint32_t b;
2537
2538 if (image) {
2539 if (!radv_image_has_CB_metadata(image))
2540 flush_CB_meta = false;
2541 if (!radv_image_has_htile(image))
2542 flush_DB_meta = false;
2543 }
2544
2545 for_each_bit(b, src_flags) {
2546 switch ((VkAccessFlagBits)(1 << b)) {
2547 case VK_ACCESS_SHADER_WRITE_BIT:
2548 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2549 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2550 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2551 break;
2552 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2553 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2554 if (flush_CB_meta)
2555 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2556 break;
2557 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2558 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2559 if (flush_DB_meta)
2560 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2561 break;
2562 case VK_ACCESS_TRANSFER_WRITE_BIT:
2563 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2564 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2565 RADV_CMD_FLAG_INV_GLOBAL_L2;
2566
2567 if (flush_CB_meta)
2568 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2569 if (flush_DB_meta)
2570 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2571 break;
2572 default:
2573 break;
2574 }
2575 }
2576 return flush_bits;
2577 }
2578
2579 static enum radv_cmd_flush_bits
2580 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2581 VkAccessFlags dst_flags,
2582 struct radv_image *image)
2583 {
2584 bool flush_CB_meta = true, flush_DB_meta = true;
2585 enum radv_cmd_flush_bits flush_bits = 0;
2586 bool flush_CB = true, flush_DB = true;
2587 bool image_is_coherent = false;
2588 uint32_t b;
2589
2590 if (image) {
2591 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2592 flush_CB = false;
2593 flush_DB = false;
2594 }
2595
2596 if (!radv_image_has_CB_metadata(image))
2597 flush_CB_meta = false;
2598 if (!radv_image_has_htile(image))
2599 flush_DB_meta = false;
2600
2601 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2602 if (image->info.samples == 1 &&
2603 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2604 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2605 !vk_format_is_stencil(image->vk_format)) {
2606 /* Single-sample color and single-sample depth
2607 * (not stencil) are coherent with shaders on
2608 * GFX9.
2609 */
2610 image_is_coherent = true;
2611 }
2612 }
2613 }
2614
2615 for_each_bit(b, dst_flags) {
2616 switch ((VkAccessFlagBits)(1 << b)) {
2617 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2618 case VK_ACCESS_INDEX_READ_BIT:
2619 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2620 break;
2621 case VK_ACCESS_UNIFORM_READ_BIT:
2622 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2623 break;
2624 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2625 case VK_ACCESS_TRANSFER_READ_BIT:
2626 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2627 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2628 RADV_CMD_FLAG_INV_GLOBAL_L2;
2629 break;
2630 case VK_ACCESS_SHADER_READ_BIT:
2631 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2632
2633 if (!image_is_coherent)
2634 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2635 break;
2636 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2637 if (flush_CB)
2638 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2639 if (flush_CB_meta)
2640 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2641 break;
2642 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2643 if (flush_DB)
2644 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2645 if (flush_DB_meta)
2646 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2647 break;
2648 default:
2649 break;
2650 }
2651 }
2652 return flush_bits;
2653 }
2654
2655 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2656 const struct radv_subpass_barrier *barrier)
2657 {
2658 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2659 NULL);
2660 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2661 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2662 NULL);
2663 }
2664
2665 static uint32_t
2666 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2667 {
2668 struct radv_cmd_state *state = &cmd_buffer->state;
2669 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2670
2671 /* The id of this subpass shouldn't exceed the number of subpasses in
2672 * this render pass minus 1.
2673 */
2674 assert(subpass_id < state->pass->subpass_count);
2675 return subpass_id;
2676 }
2677
2678 static struct radv_sample_locations_state *
2679 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2680 uint32_t att_idx,
2681 bool begin_subpass)
2682 {
2683 struct radv_cmd_state *state = &cmd_buffer->state;
2684 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2685 struct radv_image_view *view = state->framebuffer->attachments[att_idx].attachment;
2686
2687 if (view->image->info.samples == 1)
2688 return NULL;
2689
2690 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2691 /* Return the initial sample locations if this is the initial
2692 * layout transition of the given subpass attachemnt.
2693 */
2694 if (state->attachments[att_idx].sample_location.count > 0)
2695 return &state->attachments[att_idx].sample_location;
2696 } else {
2697 /* Otherwise return the subpass sample locations if defined. */
2698 if (state->subpass_sample_locs) {
2699 /* Because the driver sets the current subpass before
2700 * initial layout transitions, we should use the sample
2701 * locations from the previous subpass to avoid an
2702 * off-by-one problem. Otherwise, use the sample
2703 * locations for the current subpass for final layout
2704 * transitions.
2705 */
2706 if (begin_subpass)
2707 subpass_id--;
2708
2709 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2710 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2711 return &state->subpass_sample_locs[i].sample_location;
2712 }
2713 }
2714 }
2715
2716 return NULL;
2717 }
2718
2719 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2720 struct radv_subpass_attachment att,
2721 bool begin_subpass)
2722 {
2723 unsigned idx = att.attachment;
2724 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2725 struct radv_sample_locations_state *sample_locs;
2726 VkImageSubresourceRange range;
2727 range.aspectMask = 0;
2728 range.baseMipLevel = view->base_mip;
2729 range.levelCount = 1;
2730 range.baseArrayLayer = view->base_layer;
2731 range.layerCount = cmd_buffer->state.framebuffer->layers;
2732
2733 if (cmd_buffer->state.subpass->view_mask) {
2734 /* If the current subpass uses multiview, the driver might have
2735 * performed a fast color/depth clear to the whole image
2736 * (including all layers). To make sure the driver will
2737 * decompress the image correctly (if needed), we have to
2738 * account for the "real" number of layers. If the view mask is
2739 * sparse, this will decompress more layers than needed.
2740 */
2741 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2742 }
2743
2744 /* Get the subpass sample locations for the given attachment, if NULL
2745 * is returned the driver will use the default HW locations.
2746 */
2747 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2748 begin_subpass);
2749
2750 radv_handle_image_transition(cmd_buffer,
2751 view->image,
2752 cmd_buffer->state.attachments[idx].current_layout,
2753 att.layout, 0, 0, &range, sample_locs);
2754
2755 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2756
2757
2758 }
2759
2760 void
2761 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2762 const struct radv_subpass *subpass)
2763 {
2764 cmd_buffer->state.subpass = subpass;
2765
2766 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2767 }
2768
2769 static VkResult
2770 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2771 struct radv_render_pass *pass,
2772 const VkRenderPassBeginInfo *info)
2773 {
2774 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2775 vk_find_struct_const(info->pNext,
2776 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
2777 struct radv_cmd_state *state = &cmd_buffer->state;
2778 struct radv_framebuffer *framebuffer = state->framebuffer;
2779
2780 if (!sample_locs) {
2781 state->subpass_sample_locs = NULL;
2782 return VK_SUCCESS;
2783 }
2784
2785 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
2786 const VkAttachmentSampleLocationsEXT *att_sample_locs =
2787 &sample_locs->pAttachmentInitialSampleLocations[i];
2788 uint32_t att_idx = att_sample_locs->attachmentIndex;
2789 struct radv_attachment_info *att = &framebuffer->attachments[att_idx];
2790 struct radv_image *image = att->attachment->image;
2791
2792 assert(vk_format_is_depth_or_stencil(image->vk_format));
2793
2794 /* From the Vulkan spec 1.1.108:
2795 *
2796 * "If the image referenced by the framebuffer attachment at
2797 * index attachmentIndex was not created with
2798 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2799 * then the values specified in sampleLocationsInfo are
2800 * ignored."
2801 */
2802 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
2803 continue;
2804
2805 const VkSampleLocationsInfoEXT *sample_locs_info =
2806 &att_sample_locs->sampleLocationsInfo;
2807
2808 state->attachments[att_idx].sample_location.per_pixel =
2809 sample_locs_info->sampleLocationsPerPixel;
2810 state->attachments[att_idx].sample_location.grid_size =
2811 sample_locs_info->sampleLocationGridSize;
2812 state->attachments[att_idx].sample_location.count =
2813 sample_locs_info->sampleLocationsCount;
2814 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
2815 sample_locs_info->pSampleLocations,
2816 sample_locs_info->sampleLocationsCount);
2817 }
2818
2819 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
2820 sample_locs->postSubpassSampleLocationsCount *
2821 sizeof(state->subpass_sample_locs[0]),
2822 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2823 if (state->subpass_sample_locs == NULL) {
2824 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2825 return cmd_buffer->record_result;
2826 }
2827
2828 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
2829
2830 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
2831 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
2832 &sample_locs->pPostSubpassSampleLocations[i];
2833 const VkSampleLocationsInfoEXT *sample_locs_info =
2834 &subpass_sample_locs_info->sampleLocationsInfo;
2835
2836 state->subpass_sample_locs[i].subpass_idx =
2837 subpass_sample_locs_info->subpassIndex;
2838 state->subpass_sample_locs[i].sample_location.per_pixel =
2839 sample_locs_info->sampleLocationsPerPixel;
2840 state->subpass_sample_locs[i].sample_location.grid_size =
2841 sample_locs_info->sampleLocationGridSize;
2842 state->subpass_sample_locs[i].sample_location.count =
2843 sample_locs_info->sampleLocationsCount;
2844 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
2845 sample_locs_info->pSampleLocations,
2846 sample_locs_info->sampleLocationsCount);
2847 }
2848
2849 return VK_SUCCESS;
2850 }
2851
2852 static VkResult
2853 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2854 struct radv_render_pass *pass,
2855 const VkRenderPassBeginInfo *info)
2856 {
2857 struct radv_cmd_state *state = &cmd_buffer->state;
2858
2859 if (pass->attachment_count == 0) {
2860 state->attachments = NULL;
2861 return VK_SUCCESS;
2862 }
2863
2864 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2865 pass->attachment_count *
2866 sizeof(state->attachments[0]),
2867 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2868 if (state->attachments == NULL) {
2869 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2870 return cmd_buffer->record_result;
2871 }
2872
2873 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2874 struct radv_render_pass_attachment *att = &pass->attachments[i];
2875 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2876 VkImageAspectFlags clear_aspects = 0;
2877
2878 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2879 /* color attachment */
2880 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2881 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2882 }
2883 } else {
2884 /* depthstencil attachment */
2885 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2886 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2887 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2888 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2889 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2890 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2891 }
2892 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2893 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2894 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2895 }
2896 }
2897
2898 state->attachments[i].pending_clear_aspects = clear_aspects;
2899 state->attachments[i].cleared_views = 0;
2900 if (clear_aspects && info) {
2901 assert(info->clearValueCount > i);
2902 state->attachments[i].clear_value = info->pClearValues[i];
2903 }
2904
2905 state->attachments[i].current_layout = att->initial_layout;
2906 state->attachments[i].sample_location.count = 0;
2907 }
2908
2909 return VK_SUCCESS;
2910 }
2911
2912 VkResult radv_AllocateCommandBuffers(
2913 VkDevice _device,
2914 const VkCommandBufferAllocateInfo *pAllocateInfo,
2915 VkCommandBuffer *pCommandBuffers)
2916 {
2917 RADV_FROM_HANDLE(radv_device, device, _device);
2918 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2919
2920 VkResult result = VK_SUCCESS;
2921 uint32_t i;
2922
2923 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2924
2925 if (!list_empty(&pool->free_cmd_buffers)) {
2926 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2927
2928 list_del(&cmd_buffer->pool_link);
2929 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2930
2931 result = radv_reset_cmd_buffer(cmd_buffer);
2932 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2933 cmd_buffer->level = pAllocateInfo->level;
2934
2935 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2936 } else {
2937 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2938 &pCommandBuffers[i]);
2939 }
2940 if (result != VK_SUCCESS)
2941 break;
2942 }
2943
2944 if (result != VK_SUCCESS) {
2945 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2946 i, pCommandBuffers);
2947
2948 /* From the Vulkan 1.0.66 spec:
2949 *
2950 * "vkAllocateCommandBuffers can be used to create multiple
2951 * command buffers. If the creation of any of those command
2952 * buffers fails, the implementation must destroy all
2953 * successfully created command buffer objects from this
2954 * command, set all entries of the pCommandBuffers array to
2955 * NULL and return the error."
2956 */
2957 memset(pCommandBuffers, 0,
2958 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2959 }
2960
2961 return result;
2962 }
2963
2964 void radv_FreeCommandBuffers(
2965 VkDevice device,
2966 VkCommandPool commandPool,
2967 uint32_t commandBufferCount,
2968 const VkCommandBuffer *pCommandBuffers)
2969 {
2970 for (uint32_t i = 0; i < commandBufferCount; i++) {
2971 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2972
2973 if (cmd_buffer) {
2974 if (cmd_buffer->pool) {
2975 list_del(&cmd_buffer->pool_link);
2976 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2977 } else
2978 radv_cmd_buffer_destroy(cmd_buffer);
2979
2980 }
2981 }
2982 }
2983
2984 VkResult radv_ResetCommandBuffer(
2985 VkCommandBuffer commandBuffer,
2986 VkCommandBufferResetFlags flags)
2987 {
2988 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2989 return radv_reset_cmd_buffer(cmd_buffer);
2990 }
2991
2992 VkResult radv_BeginCommandBuffer(
2993 VkCommandBuffer commandBuffer,
2994 const VkCommandBufferBeginInfo *pBeginInfo)
2995 {
2996 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2997 VkResult result = VK_SUCCESS;
2998
2999 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3000 /* If the command buffer has already been resetted with
3001 * vkResetCommandBuffer, no need to do it again.
3002 */
3003 result = radv_reset_cmd_buffer(cmd_buffer);
3004 if (result != VK_SUCCESS)
3005 return result;
3006 }
3007
3008 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3009 cmd_buffer->state.last_primitive_reset_en = -1;
3010 cmd_buffer->state.last_index_type = -1;
3011 cmd_buffer->state.last_num_instances = -1;
3012 cmd_buffer->state.last_vertex_offset = -1;
3013 cmd_buffer->state.last_first_instance = -1;
3014 cmd_buffer->state.predication_type = -1;
3015 cmd_buffer->usage_flags = pBeginInfo->flags;
3016
3017 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3018 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3019 assert(pBeginInfo->pInheritanceInfo);
3020 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3021 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3022
3023 struct radv_subpass *subpass =
3024 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3025
3026 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3027 if (result != VK_SUCCESS)
3028 return result;
3029
3030 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3031 }
3032
3033 if (unlikely(cmd_buffer->device->trace_bo)) {
3034 struct radv_device *device = cmd_buffer->device;
3035
3036 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3037 device->trace_bo);
3038
3039 radv_cmd_buffer_trace_emit(cmd_buffer);
3040 }
3041
3042 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3043
3044 return result;
3045 }
3046
3047 void radv_CmdBindVertexBuffers(
3048 VkCommandBuffer commandBuffer,
3049 uint32_t firstBinding,
3050 uint32_t bindingCount,
3051 const VkBuffer* pBuffers,
3052 const VkDeviceSize* pOffsets)
3053 {
3054 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3055 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3056 bool changed = false;
3057
3058 /* We have to defer setting up vertex buffer since we need the buffer
3059 * stride from the pipeline. */
3060
3061 assert(firstBinding + bindingCount <= MAX_VBS);
3062 for (uint32_t i = 0; i < bindingCount; i++) {
3063 uint32_t idx = firstBinding + i;
3064
3065 if (!changed &&
3066 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3067 vb[idx].offset != pOffsets[i])) {
3068 changed = true;
3069 }
3070
3071 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3072 vb[idx].offset = pOffsets[i];
3073
3074 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3075 vb[idx].buffer->bo);
3076 }
3077
3078 if (!changed) {
3079 /* No state changes. */
3080 return;
3081 }
3082
3083 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3084 }
3085
3086 void radv_CmdBindIndexBuffer(
3087 VkCommandBuffer commandBuffer,
3088 VkBuffer buffer,
3089 VkDeviceSize offset,
3090 VkIndexType indexType)
3091 {
3092 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3093 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3094
3095 if (cmd_buffer->state.index_buffer == index_buffer &&
3096 cmd_buffer->state.index_offset == offset &&
3097 cmd_buffer->state.index_type == indexType) {
3098 /* No state changes. */
3099 return;
3100 }
3101
3102 cmd_buffer->state.index_buffer = index_buffer;
3103 cmd_buffer->state.index_offset = offset;
3104 cmd_buffer->state.index_type = indexType; /* vk matches hw */
3105 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3106 cmd_buffer->state.index_va += index_buffer->offset + offset;
3107
3108 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
3109 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
3110 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3111 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3112 }
3113
3114
3115 static void
3116 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3117 VkPipelineBindPoint bind_point,
3118 struct radv_descriptor_set *set, unsigned idx)
3119 {
3120 struct radeon_winsys *ws = cmd_buffer->device->ws;
3121
3122 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3123
3124 assert(set);
3125 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3126
3127 if (!cmd_buffer->device->use_global_bo_list) {
3128 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3129 if (set->descriptors[j])
3130 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3131 }
3132
3133 if(set->bo)
3134 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3135 }
3136
3137 void radv_CmdBindDescriptorSets(
3138 VkCommandBuffer commandBuffer,
3139 VkPipelineBindPoint pipelineBindPoint,
3140 VkPipelineLayout _layout,
3141 uint32_t firstSet,
3142 uint32_t descriptorSetCount,
3143 const VkDescriptorSet* pDescriptorSets,
3144 uint32_t dynamicOffsetCount,
3145 const uint32_t* pDynamicOffsets)
3146 {
3147 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3148 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3149 unsigned dyn_idx = 0;
3150
3151 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3152 struct radv_descriptor_state *descriptors_state =
3153 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3154
3155 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3156 unsigned idx = i + firstSet;
3157 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3158 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3159
3160 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3161 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3162 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3163 assert(dyn_idx < dynamicOffsetCount);
3164
3165 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3166 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3167 dst[0] = va;
3168 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3169 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3170 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3171 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3172 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3173 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3174 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3175 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3176 cmd_buffer->push_constant_stages |=
3177 set->layout->dynamic_shader_stages;
3178 }
3179 }
3180 }
3181
3182 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3183 struct radv_descriptor_set *set,
3184 struct radv_descriptor_set_layout *layout,
3185 VkPipelineBindPoint bind_point)
3186 {
3187 struct radv_descriptor_state *descriptors_state =
3188 radv_get_descriptors_state(cmd_buffer, bind_point);
3189 set->size = layout->size;
3190 set->layout = layout;
3191
3192 if (descriptors_state->push_set.capacity < set->size) {
3193 size_t new_size = MAX2(set->size, 1024);
3194 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3195 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3196
3197 free(set->mapped_ptr);
3198 set->mapped_ptr = malloc(new_size);
3199
3200 if (!set->mapped_ptr) {
3201 descriptors_state->push_set.capacity = 0;
3202 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3203 return false;
3204 }
3205
3206 descriptors_state->push_set.capacity = new_size;
3207 }
3208
3209 return true;
3210 }
3211
3212 void radv_meta_push_descriptor_set(
3213 struct radv_cmd_buffer* cmd_buffer,
3214 VkPipelineBindPoint pipelineBindPoint,
3215 VkPipelineLayout _layout,
3216 uint32_t set,
3217 uint32_t descriptorWriteCount,
3218 const VkWriteDescriptorSet* pDescriptorWrites)
3219 {
3220 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3221 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3222 unsigned bo_offset;
3223
3224 assert(set == 0);
3225 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3226
3227 push_set->size = layout->set[set].layout->size;
3228 push_set->layout = layout->set[set].layout;
3229
3230 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3231 &bo_offset,
3232 (void**) &push_set->mapped_ptr))
3233 return;
3234
3235 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3236 push_set->va += bo_offset;
3237
3238 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3239 radv_descriptor_set_to_handle(push_set),
3240 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3241
3242 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3243 }
3244
3245 void radv_CmdPushDescriptorSetKHR(
3246 VkCommandBuffer commandBuffer,
3247 VkPipelineBindPoint pipelineBindPoint,
3248 VkPipelineLayout _layout,
3249 uint32_t set,
3250 uint32_t descriptorWriteCount,
3251 const VkWriteDescriptorSet* pDescriptorWrites)
3252 {
3253 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3254 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3255 struct radv_descriptor_state *descriptors_state =
3256 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3257 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3258
3259 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3260
3261 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3262 layout->set[set].layout,
3263 pipelineBindPoint))
3264 return;
3265
3266 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3267 * because it is invalid, according to Vulkan spec.
3268 */
3269 for (int i = 0; i < descriptorWriteCount; i++) {
3270 MAYBE_UNUSED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3271 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3272 }
3273
3274 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3275 radv_descriptor_set_to_handle(push_set),
3276 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3277
3278 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3279 descriptors_state->push_dirty = true;
3280 }
3281
3282 void radv_CmdPushDescriptorSetWithTemplateKHR(
3283 VkCommandBuffer commandBuffer,
3284 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3285 VkPipelineLayout _layout,
3286 uint32_t set,
3287 const void* pData)
3288 {
3289 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3290 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3291 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3292 struct radv_descriptor_state *descriptors_state =
3293 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3294 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3295
3296 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3297
3298 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3299 layout->set[set].layout,
3300 templ->bind_point))
3301 return;
3302
3303 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3304 descriptorUpdateTemplate, pData);
3305
3306 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3307 descriptors_state->push_dirty = true;
3308 }
3309
3310 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3311 VkPipelineLayout layout,
3312 VkShaderStageFlags stageFlags,
3313 uint32_t offset,
3314 uint32_t size,
3315 const void* pValues)
3316 {
3317 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3318 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3319 cmd_buffer->push_constant_stages |= stageFlags;
3320 }
3321
3322 VkResult radv_EndCommandBuffer(
3323 VkCommandBuffer commandBuffer)
3324 {
3325 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3326
3327 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3328 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3329 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3330
3331 /* Make sure to sync all pending active queries at the end of
3332 * command buffer.
3333 */
3334 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3335
3336 si_emit_cache_flush(cmd_buffer);
3337 }
3338
3339 /* Make sure CP DMA is idle at the end of IBs because the kernel
3340 * doesn't wait for it.
3341 */
3342 si_cp_dma_wait_for_idle(cmd_buffer);
3343
3344 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3345 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3346
3347 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3348 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3349
3350 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3351
3352 return cmd_buffer->record_result;
3353 }
3354
3355 static void
3356 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3357 {
3358 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3359
3360 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3361 return;
3362
3363 assert(!pipeline->ctx_cs.cdw);
3364
3365 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3366
3367 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3368 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3369
3370 cmd_buffer->compute_scratch_size_needed =
3371 MAX2(cmd_buffer->compute_scratch_size_needed,
3372 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3373
3374 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3375 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3376
3377 if (unlikely(cmd_buffer->device->trace_bo))
3378 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3379 }
3380
3381 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3382 VkPipelineBindPoint bind_point)
3383 {
3384 struct radv_descriptor_state *descriptors_state =
3385 radv_get_descriptors_state(cmd_buffer, bind_point);
3386
3387 descriptors_state->dirty |= descriptors_state->valid;
3388 }
3389
3390 void radv_CmdBindPipeline(
3391 VkCommandBuffer commandBuffer,
3392 VkPipelineBindPoint pipelineBindPoint,
3393 VkPipeline _pipeline)
3394 {
3395 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3396 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3397
3398 switch (pipelineBindPoint) {
3399 case VK_PIPELINE_BIND_POINT_COMPUTE:
3400 if (cmd_buffer->state.compute_pipeline == pipeline)
3401 return;
3402 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3403
3404 cmd_buffer->state.compute_pipeline = pipeline;
3405 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3406 break;
3407 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3408 if (cmd_buffer->state.pipeline == pipeline)
3409 return;
3410 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3411
3412 cmd_buffer->state.pipeline = pipeline;
3413 if (!pipeline)
3414 break;
3415
3416 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3417 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3418
3419 /* the new vertex shader might not have the same user regs */
3420 cmd_buffer->state.last_first_instance = -1;
3421 cmd_buffer->state.last_vertex_offset = -1;
3422
3423 /* Prefetch all pipeline shaders at first draw time. */
3424 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3425
3426 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3427 radv_bind_streamout_state(cmd_buffer, pipeline);
3428
3429 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3430 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3431 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3432 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3433
3434 if (radv_pipeline_has_tess(pipeline))
3435 cmd_buffer->tess_rings_needed = true;
3436 break;
3437 default:
3438 assert(!"invalid bind point");
3439 break;
3440 }
3441 }
3442
3443 void radv_CmdSetViewport(
3444 VkCommandBuffer commandBuffer,
3445 uint32_t firstViewport,
3446 uint32_t viewportCount,
3447 const VkViewport* pViewports)
3448 {
3449 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3450 struct radv_cmd_state *state = &cmd_buffer->state;
3451 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3452
3453 assert(firstViewport < MAX_VIEWPORTS);
3454 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3455
3456 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3457 pViewports, viewportCount * sizeof(*pViewports))) {
3458 return;
3459 }
3460
3461 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3462 viewportCount * sizeof(*pViewports));
3463
3464 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3465 }
3466
3467 void radv_CmdSetScissor(
3468 VkCommandBuffer commandBuffer,
3469 uint32_t firstScissor,
3470 uint32_t scissorCount,
3471 const VkRect2D* pScissors)
3472 {
3473 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3474 struct radv_cmd_state *state = &cmd_buffer->state;
3475 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3476
3477 assert(firstScissor < MAX_SCISSORS);
3478 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3479
3480 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3481 scissorCount * sizeof(*pScissors))) {
3482 return;
3483 }
3484
3485 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3486 scissorCount * sizeof(*pScissors));
3487
3488 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3489 }
3490
3491 void radv_CmdSetLineWidth(
3492 VkCommandBuffer commandBuffer,
3493 float lineWidth)
3494 {
3495 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3496
3497 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3498 return;
3499
3500 cmd_buffer->state.dynamic.line_width = lineWidth;
3501 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3502 }
3503
3504 void radv_CmdSetDepthBias(
3505 VkCommandBuffer commandBuffer,
3506 float depthBiasConstantFactor,
3507 float depthBiasClamp,
3508 float depthBiasSlopeFactor)
3509 {
3510 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3511 struct radv_cmd_state *state = &cmd_buffer->state;
3512
3513 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3514 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3515 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3516 return;
3517 }
3518
3519 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3520 state->dynamic.depth_bias.clamp = depthBiasClamp;
3521 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3522
3523 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3524 }
3525
3526 void radv_CmdSetBlendConstants(
3527 VkCommandBuffer commandBuffer,
3528 const float blendConstants[4])
3529 {
3530 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3531 struct radv_cmd_state *state = &cmd_buffer->state;
3532
3533 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3534 return;
3535
3536 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3537
3538 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3539 }
3540
3541 void radv_CmdSetDepthBounds(
3542 VkCommandBuffer commandBuffer,
3543 float minDepthBounds,
3544 float maxDepthBounds)
3545 {
3546 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3547 struct radv_cmd_state *state = &cmd_buffer->state;
3548
3549 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3550 state->dynamic.depth_bounds.max == maxDepthBounds) {
3551 return;
3552 }
3553
3554 state->dynamic.depth_bounds.min = minDepthBounds;
3555 state->dynamic.depth_bounds.max = maxDepthBounds;
3556
3557 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3558 }
3559
3560 void radv_CmdSetStencilCompareMask(
3561 VkCommandBuffer commandBuffer,
3562 VkStencilFaceFlags faceMask,
3563 uint32_t compareMask)
3564 {
3565 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3566 struct radv_cmd_state *state = &cmd_buffer->state;
3567 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3568 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3569
3570 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3571 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3572 return;
3573 }
3574
3575 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3576 state->dynamic.stencil_compare_mask.front = compareMask;
3577 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3578 state->dynamic.stencil_compare_mask.back = compareMask;
3579
3580 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3581 }
3582
3583 void radv_CmdSetStencilWriteMask(
3584 VkCommandBuffer commandBuffer,
3585 VkStencilFaceFlags faceMask,
3586 uint32_t writeMask)
3587 {
3588 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3589 struct radv_cmd_state *state = &cmd_buffer->state;
3590 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3591 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3592
3593 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3594 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3595 return;
3596 }
3597
3598 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3599 state->dynamic.stencil_write_mask.front = writeMask;
3600 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3601 state->dynamic.stencil_write_mask.back = writeMask;
3602
3603 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3604 }
3605
3606 void radv_CmdSetStencilReference(
3607 VkCommandBuffer commandBuffer,
3608 VkStencilFaceFlags faceMask,
3609 uint32_t reference)
3610 {
3611 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3612 struct radv_cmd_state *state = &cmd_buffer->state;
3613 bool front_same = state->dynamic.stencil_reference.front == reference;
3614 bool back_same = state->dynamic.stencil_reference.back == reference;
3615
3616 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3617 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3618 return;
3619 }
3620
3621 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3622 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3623 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3624 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3625
3626 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3627 }
3628
3629 void radv_CmdSetDiscardRectangleEXT(
3630 VkCommandBuffer commandBuffer,
3631 uint32_t firstDiscardRectangle,
3632 uint32_t discardRectangleCount,
3633 const VkRect2D* pDiscardRectangles)
3634 {
3635 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3636 struct radv_cmd_state *state = &cmd_buffer->state;
3637 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3638
3639 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3640 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3641
3642 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3643 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3644 return;
3645 }
3646
3647 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3648 pDiscardRectangles, discardRectangleCount);
3649
3650 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3651 }
3652
3653 void radv_CmdSetSampleLocationsEXT(
3654 VkCommandBuffer commandBuffer,
3655 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3656 {
3657 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3658 struct radv_cmd_state *state = &cmd_buffer->state;
3659
3660 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3661
3662 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3663 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3664 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3665 typed_memcpy(&state->dynamic.sample_location.locations[0],
3666 pSampleLocationsInfo->pSampleLocations,
3667 pSampleLocationsInfo->sampleLocationsCount);
3668
3669 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3670 }
3671
3672 void radv_CmdExecuteCommands(
3673 VkCommandBuffer commandBuffer,
3674 uint32_t commandBufferCount,
3675 const VkCommandBuffer* pCmdBuffers)
3676 {
3677 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3678
3679 assert(commandBufferCount > 0);
3680
3681 /* Emit pending flushes on primary prior to executing secondary */
3682 si_emit_cache_flush(primary);
3683
3684 for (uint32_t i = 0; i < commandBufferCount; i++) {
3685 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3686
3687 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3688 secondary->scratch_size_needed);
3689 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3690 secondary->compute_scratch_size_needed);
3691
3692 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3693 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3694 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3695 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3696 if (secondary->tess_rings_needed)
3697 primary->tess_rings_needed = true;
3698 if (secondary->sample_positions_needed)
3699 primary->sample_positions_needed = true;
3700
3701 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3702
3703
3704 /* When the secondary command buffer is compute only we don't
3705 * need to re-emit the current graphics pipeline.
3706 */
3707 if (secondary->state.emitted_pipeline) {
3708 primary->state.emitted_pipeline =
3709 secondary->state.emitted_pipeline;
3710 }
3711
3712 /* When the secondary command buffer is graphics only we don't
3713 * need to re-emit the current compute pipeline.
3714 */
3715 if (secondary->state.emitted_compute_pipeline) {
3716 primary->state.emitted_compute_pipeline =
3717 secondary->state.emitted_compute_pipeline;
3718 }
3719
3720 /* Only re-emit the draw packets when needed. */
3721 if (secondary->state.last_primitive_reset_en != -1) {
3722 primary->state.last_primitive_reset_en =
3723 secondary->state.last_primitive_reset_en;
3724 }
3725
3726 if (secondary->state.last_primitive_reset_index) {
3727 primary->state.last_primitive_reset_index =
3728 secondary->state.last_primitive_reset_index;
3729 }
3730
3731 if (secondary->state.last_ia_multi_vgt_param) {
3732 primary->state.last_ia_multi_vgt_param =
3733 secondary->state.last_ia_multi_vgt_param;
3734 }
3735
3736 primary->state.last_first_instance = secondary->state.last_first_instance;
3737 primary->state.last_num_instances = secondary->state.last_num_instances;
3738 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3739
3740 if (secondary->state.last_index_type != -1) {
3741 primary->state.last_index_type =
3742 secondary->state.last_index_type;
3743 }
3744 }
3745
3746 /* After executing commands from secondary buffers we have to dirty
3747 * some states.
3748 */
3749 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3750 RADV_CMD_DIRTY_INDEX_BUFFER |
3751 RADV_CMD_DIRTY_DYNAMIC_ALL;
3752 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3753 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3754 }
3755
3756 VkResult radv_CreateCommandPool(
3757 VkDevice _device,
3758 const VkCommandPoolCreateInfo* pCreateInfo,
3759 const VkAllocationCallbacks* pAllocator,
3760 VkCommandPool* pCmdPool)
3761 {
3762 RADV_FROM_HANDLE(radv_device, device, _device);
3763 struct radv_cmd_pool *pool;
3764
3765 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3766 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3767 if (pool == NULL)
3768 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3769
3770 if (pAllocator)
3771 pool->alloc = *pAllocator;
3772 else
3773 pool->alloc = device->alloc;
3774
3775 list_inithead(&pool->cmd_buffers);
3776 list_inithead(&pool->free_cmd_buffers);
3777
3778 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3779
3780 *pCmdPool = radv_cmd_pool_to_handle(pool);
3781
3782 return VK_SUCCESS;
3783
3784 }
3785
3786 void radv_DestroyCommandPool(
3787 VkDevice _device,
3788 VkCommandPool commandPool,
3789 const VkAllocationCallbacks* pAllocator)
3790 {
3791 RADV_FROM_HANDLE(radv_device, device, _device);
3792 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3793
3794 if (!pool)
3795 return;
3796
3797 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3798 &pool->cmd_buffers, pool_link) {
3799 radv_cmd_buffer_destroy(cmd_buffer);
3800 }
3801
3802 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3803 &pool->free_cmd_buffers, pool_link) {
3804 radv_cmd_buffer_destroy(cmd_buffer);
3805 }
3806
3807 vk_free2(&device->alloc, pAllocator, pool);
3808 }
3809
3810 VkResult radv_ResetCommandPool(
3811 VkDevice device,
3812 VkCommandPool commandPool,
3813 VkCommandPoolResetFlags flags)
3814 {
3815 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3816 VkResult result;
3817
3818 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3819 &pool->cmd_buffers, pool_link) {
3820 result = radv_reset_cmd_buffer(cmd_buffer);
3821 if (result != VK_SUCCESS)
3822 return result;
3823 }
3824
3825 return VK_SUCCESS;
3826 }
3827
3828 void radv_TrimCommandPool(
3829 VkDevice device,
3830 VkCommandPool commandPool,
3831 VkCommandPoolTrimFlags flags)
3832 {
3833 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3834
3835 if (!pool)
3836 return;
3837
3838 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3839 &pool->free_cmd_buffers, pool_link) {
3840 radv_cmd_buffer_destroy(cmd_buffer);
3841 }
3842 }
3843
3844 static void
3845 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3846 uint32_t subpass_id)
3847 {
3848 struct radv_cmd_state *state = &cmd_buffer->state;
3849 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3850
3851 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3852 cmd_buffer->cs, 4096);
3853
3854 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3855
3856 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3857
3858 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3859 const uint32_t a = subpass->attachments[i].attachment;
3860 if (a == VK_ATTACHMENT_UNUSED)
3861 continue;
3862
3863 radv_handle_subpass_image_transition(cmd_buffer,
3864 subpass->attachments[i],
3865 true);
3866 }
3867
3868 radv_cmd_buffer_clear_subpass(cmd_buffer);
3869
3870 assert(cmd_buffer->cs->cdw <= cdw_max);
3871 }
3872
3873 static void
3874 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3875 {
3876 struct radv_cmd_state *state = &cmd_buffer->state;
3877 const struct radv_subpass *subpass = state->subpass;
3878 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3879
3880 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3881
3882 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3883 const uint32_t a = subpass->attachments[i].attachment;
3884 if (a == VK_ATTACHMENT_UNUSED)
3885 continue;
3886
3887 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
3888 continue;
3889
3890 VkImageLayout layout = state->pass->attachments[a].final_layout;
3891 struct radv_subpass_attachment att = { a, layout };
3892 radv_handle_subpass_image_transition(cmd_buffer, att, false);
3893 }
3894 }
3895
3896 void radv_CmdBeginRenderPass(
3897 VkCommandBuffer commandBuffer,
3898 const VkRenderPassBeginInfo* pRenderPassBegin,
3899 VkSubpassContents contents)
3900 {
3901 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3902 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3903 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3904 VkResult result;
3905
3906 cmd_buffer->state.framebuffer = framebuffer;
3907 cmd_buffer->state.pass = pass;
3908 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3909
3910 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3911 if (result != VK_SUCCESS)
3912 return;
3913
3914 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
3915 if (result != VK_SUCCESS)
3916 return;
3917
3918 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
3919 }
3920
3921 void radv_CmdBeginRenderPass2KHR(
3922 VkCommandBuffer commandBuffer,
3923 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3924 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3925 {
3926 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3927 pSubpassBeginInfo->contents);
3928 }
3929
3930 void radv_CmdNextSubpass(
3931 VkCommandBuffer commandBuffer,
3932 VkSubpassContents contents)
3933 {
3934 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3935
3936 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
3937 radv_cmd_buffer_end_subpass(cmd_buffer);
3938 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
3939 }
3940
3941 void radv_CmdNextSubpass2KHR(
3942 VkCommandBuffer commandBuffer,
3943 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3944 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3945 {
3946 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3947 }
3948
3949 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3950 {
3951 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3952 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3953 if (!radv_get_shader(pipeline, stage))
3954 continue;
3955
3956 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3957 if (loc->sgpr_idx == -1)
3958 continue;
3959 uint32_t base_reg = pipeline->user_data_0[stage];
3960 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3961
3962 }
3963 if (pipeline->gs_copy_shader) {
3964 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3965 if (loc->sgpr_idx != -1) {
3966 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3967 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3968 }
3969 }
3970 }
3971
3972 static void
3973 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3974 uint32_t vertex_count,
3975 bool use_opaque)
3976 {
3977 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3978 radeon_emit(cmd_buffer->cs, vertex_count);
3979 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3980 S_0287F0_USE_OPAQUE(use_opaque));
3981 }
3982
3983 static void
3984 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3985 uint64_t index_va,
3986 uint32_t index_count)
3987 {
3988 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3989 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3990 radeon_emit(cmd_buffer->cs, index_va);
3991 radeon_emit(cmd_buffer->cs, index_va >> 32);
3992 radeon_emit(cmd_buffer->cs, index_count);
3993 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3994 }
3995
3996 static void
3997 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3998 bool indexed,
3999 uint32_t draw_count,
4000 uint64_t count_va,
4001 uint32_t stride)
4002 {
4003 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4004 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4005 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4006 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
4007 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4008 bool predicating = cmd_buffer->state.predicating;
4009 assert(base_reg);
4010
4011 /* just reset draw state for vertex data */
4012 cmd_buffer->state.last_first_instance = -1;
4013 cmd_buffer->state.last_num_instances = -1;
4014 cmd_buffer->state.last_vertex_offset = -1;
4015
4016 if (draw_count == 1 && !count_va && !draw_id_enable) {
4017 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4018 PKT3_DRAW_INDIRECT, 3, predicating));
4019 radeon_emit(cs, 0);
4020 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4021 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4022 radeon_emit(cs, di_src_sel);
4023 } else {
4024 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4025 PKT3_DRAW_INDIRECT_MULTI,
4026 8, predicating));
4027 radeon_emit(cs, 0);
4028 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4029 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4030 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4031 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4032 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4033 radeon_emit(cs, draw_count); /* count */
4034 radeon_emit(cs, count_va); /* count_addr */
4035 radeon_emit(cs, count_va >> 32);
4036 radeon_emit(cs, stride); /* stride */
4037 radeon_emit(cs, di_src_sel);
4038 }
4039 }
4040
4041 static void
4042 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4043 const struct radv_draw_info *info)
4044 {
4045 struct radv_cmd_state *state = &cmd_buffer->state;
4046 struct radeon_winsys *ws = cmd_buffer->device->ws;
4047 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4048
4049 if (info->indirect) {
4050 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4051 uint64_t count_va = 0;
4052
4053 va += info->indirect->offset + info->indirect_offset;
4054
4055 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4056
4057 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4058 radeon_emit(cs, 1);
4059 radeon_emit(cs, va);
4060 radeon_emit(cs, va >> 32);
4061
4062 if (info->count_buffer) {
4063 count_va = radv_buffer_get_va(info->count_buffer->bo);
4064 count_va += info->count_buffer->offset +
4065 info->count_buffer_offset;
4066
4067 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4068 }
4069
4070 if (!state->subpass->view_mask) {
4071 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4072 info->indexed,
4073 info->count,
4074 count_va,
4075 info->stride);
4076 } else {
4077 unsigned i;
4078 for_each_bit(i, state->subpass->view_mask) {
4079 radv_emit_view_index(cmd_buffer, i);
4080
4081 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4082 info->indexed,
4083 info->count,
4084 count_va,
4085 info->stride);
4086 }
4087 }
4088 } else {
4089 assert(state->pipeline->graphics.vtx_base_sgpr);
4090
4091 if (info->vertex_offset != state->last_vertex_offset ||
4092 info->first_instance != state->last_first_instance) {
4093 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4094 state->pipeline->graphics.vtx_emit_num);
4095
4096 radeon_emit(cs, info->vertex_offset);
4097 radeon_emit(cs, info->first_instance);
4098 if (state->pipeline->graphics.vtx_emit_num == 3)
4099 radeon_emit(cs, 0);
4100 state->last_first_instance = info->first_instance;
4101 state->last_vertex_offset = info->vertex_offset;
4102 }
4103
4104 if (state->last_num_instances != info->instance_count) {
4105 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4106 radeon_emit(cs, info->instance_count);
4107 state->last_num_instances = info->instance_count;
4108 }
4109
4110 if (info->indexed) {
4111 int index_size = state->index_type ? 4 : 2;
4112 uint64_t index_va;
4113
4114 index_va = state->index_va;
4115 index_va += info->first_index * index_size;
4116
4117 if (!state->subpass->view_mask) {
4118 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4119 index_va,
4120 info->count);
4121 } else {
4122 unsigned i;
4123 for_each_bit(i, state->subpass->view_mask) {
4124 radv_emit_view_index(cmd_buffer, i);
4125
4126 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4127 index_va,
4128 info->count);
4129 }
4130 }
4131 } else {
4132 if (!state->subpass->view_mask) {
4133 radv_cs_emit_draw_packet(cmd_buffer,
4134 info->count,
4135 !!info->strmout_buffer);
4136 } else {
4137 unsigned i;
4138 for_each_bit(i, state->subpass->view_mask) {
4139 radv_emit_view_index(cmd_buffer, i);
4140
4141 radv_cs_emit_draw_packet(cmd_buffer,
4142 info->count,
4143 !!info->strmout_buffer);
4144 }
4145 }
4146 }
4147 }
4148 }
4149
4150 /*
4151 * Vega and raven have a bug which triggers if there are multiple context
4152 * register contexts active at the same time with different scissor values.
4153 *
4154 * There are two possible workarounds:
4155 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4156 * there is only ever 1 active set of scissor values at the same time.
4157 *
4158 * 2) Whenever the hardware switches contexts we have to set the scissor
4159 * registers again even if it is a noop. That way the new context gets
4160 * the correct scissor values.
4161 *
4162 * This implements option 2. radv_need_late_scissor_emission needs to
4163 * return true on affected HW if radv_emit_all_graphics_states sets
4164 * any context registers.
4165 */
4166 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4167 const struct radv_draw_info *info)
4168 {
4169 struct radv_cmd_state *state = &cmd_buffer->state;
4170
4171 if (!cmd_buffer->device->physical_device->has_scissor_bug)
4172 return false;
4173
4174 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4175 return true;
4176
4177 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4178
4179 /* Index, vertex and streamout buffers don't change context regs, and
4180 * pipeline is already handled.
4181 */
4182 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4183 RADV_CMD_DIRTY_VERTEX_BUFFER |
4184 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4185 RADV_CMD_DIRTY_PIPELINE);
4186
4187 if (cmd_buffer->state.dirty & used_states)
4188 return true;
4189
4190 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4191 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
4192 return true;
4193
4194 return false;
4195 }
4196
4197 static void
4198 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4199 const struct radv_draw_info *info)
4200 {
4201 bool late_scissor_emission;
4202
4203 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4204 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4205 radv_emit_rbplus_state(cmd_buffer);
4206
4207 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4208 radv_emit_graphics_pipeline(cmd_buffer);
4209
4210 /* This should be before the cmd_buffer->state.dirty is cleared
4211 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4212 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4213 late_scissor_emission =
4214 radv_need_late_scissor_emission(cmd_buffer, info);
4215
4216 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4217 radv_emit_framebuffer_state(cmd_buffer);
4218
4219 if (info->indexed) {
4220 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4221 radv_emit_index_buffer(cmd_buffer);
4222 } else {
4223 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4224 * so the state must be re-emitted before the next indexed
4225 * draw.
4226 */
4227 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4228 cmd_buffer->state.last_index_type = -1;
4229 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4230 }
4231 }
4232
4233 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4234
4235 radv_emit_draw_registers(cmd_buffer, info);
4236
4237 if (late_scissor_emission)
4238 radv_emit_scissor(cmd_buffer);
4239 }
4240
4241 static void
4242 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4243 const struct radv_draw_info *info)
4244 {
4245 struct radeon_info *rad_info =
4246 &cmd_buffer->device->physical_device->rad_info;
4247 bool has_prefetch =
4248 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4249 bool pipeline_is_dirty =
4250 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4251 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4252
4253 MAYBE_UNUSED unsigned cdw_max =
4254 radeon_check_space(cmd_buffer->device->ws,
4255 cmd_buffer->cs, 4096);
4256
4257 if (likely(!info->indirect)) {
4258 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4259 * no workaround for indirect draws, but we can at least skip
4260 * direct draws.
4261 */
4262 if (unlikely(!info->instance_count))
4263 return;
4264
4265 /* Handle count == 0. */
4266 if (unlikely(!info->count && !info->strmout_buffer))
4267 return;
4268 }
4269
4270 /* Use optimal packet order based on whether we need to sync the
4271 * pipeline.
4272 */
4273 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4274 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4275 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4276 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4277 /* If we have to wait for idle, set all states first, so that
4278 * all SET packets are processed in parallel with previous draw
4279 * calls. Then upload descriptors, set shader pointers, and
4280 * draw, and prefetch at the end. This ensures that the time
4281 * the CUs are idle is very short. (there are only SET_SH
4282 * packets between the wait and the draw)
4283 */
4284 radv_emit_all_graphics_states(cmd_buffer, info);
4285 si_emit_cache_flush(cmd_buffer);
4286 /* <-- CUs are idle here --> */
4287
4288 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4289
4290 radv_emit_draw_packets(cmd_buffer, info);
4291 /* <-- CUs are busy here --> */
4292
4293 /* Start prefetches after the draw has been started. Both will
4294 * run in parallel, but starting the draw first is more
4295 * important.
4296 */
4297 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4298 radv_emit_prefetch_L2(cmd_buffer,
4299 cmd_buffer->state.pipeline, false);
4300 }
4301 } else {
4302 /* If we don't wait for idle, start prefetches first, then set
4303 * states, and draw at the end.
4304 */
4305 si_emit_cache_flush(cmd_buffer);
4306
4307 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4308 /* Only prefetch the vertex shader and VBO descriptors
4309 * in order to start the draw as soon as possible.
4310 */
4311 radv_emit_prefetch_L2(cmd_buffer,
4312 cmd_buffer->state.pipeline, true);
4313 }
4314
4315 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4316
4317 radv_emit_all_graphics_states(cmd_buffer, info);
4318 radv_emit_draw_packets(cmd_buffer, info);
4319
4320 /* Prefetch the remaining shaders after the draw has been
4321 * started.
4322 */
4323 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4324 radv_emit_prefetch_L2(cmd_buffer,
4325 cmd_buffer->state.pipeline, false);
4326 }
4327 }
4328
4329 /* Workaround for a VGT hang when streamout is enabled.
4330 * It must be done after drawing.
4331 */
4332 if (cmd_buffer->state.streamout.streamout_enabled &&
4333 (rad_info->family == CHIP_HAWAII ||
4334 rad_info->family == CHIP_TONGA ||
4335 rad_info->family == CHIP_FIJI)) {
4336 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4337 }
4338
4339 assert(cmd_buffer->cs->cdw <= cdw_max);
4340 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4341 }
4342
4343 void radv_CmdDraw(
4344 VkCommandBuffer commandBuffer,
4345 uint32_t vertexCount,
4346 uint32_t instanceCount,
4347 uint32_t firstVertex,
4348 uint32_t firstInstance)
4349 {
4350 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4351 struct radv_draw_info info = {};
4352
4353 info.count = vertexCount;
4354 info.instance_count = instanceCount;
4355 info.first_instance = firstInstance;
4356 info.vertex_offset = firstVertex;
4357
4358 radv_draw(cmd_buffer, &info);
4359 }
4360
4361 void radv_CmdDrawIndexed(
4362 VkCommandBuffer commandBuffer,
4363 uint32_t indexCount,
4364 uint32_t instanceCount,
4365 uint32_t firstIndex,
4366 int32_t vertexOffset,
4367 uint32_t firstInstance)
4368 {
4369 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4370 struct radv_draw_info info = {};
4371
4372 info.indexed = true;
4373 info.count = indexCount;
4374 info.instance_count = instanceCount;
4375 info.first_index = firstIndex;
4376 info.vertex_offset = vertexOffset;
4377 info.first_instance = firstInstance;
4378
4379 radv_draw(cmd_buffer, &info);
4380 }
4381
4382 void radv_CmdDrawIndirect(
4383 VkCommandBuffer commandBuffer,
4384 VkBuffer _buffer,
4385 VkDeviceSize offset,
4386 uint32_t drawCount,
4387 uint32_t stride)
4388 {
4389 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4390 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4391 struct radv_draw_info info = {};
4392
4393 info.count = drawCount;
4394 info.indirect = buffer;
4395 info.indirect_offset = offset;
4396 info.stride = stride;
4397
4398 radv_draw(cmd_buffer, &info);
4399 }
4400
4401 void radv_CmdDrawIndexedIndirect(
4402 VkCommandBuffer commandBuffer,
4403 VkBuffer _buffer,
4404 VkDeviceSize offset,
4405 uint32_t drawCount,
4406 uint32_t stride)
4407 {
4408 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4409 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4410 struct radv_draw_info info = {};
4411
4412 info.indexed = true;
4413 info.count = drawCount;
4414 info.indirect = buffer;
4415 info.indirect_offset = offset;
4416 info.stride = stride;
4417
4418 radv_draw(cmd_buffer, &info);
4419 }
4420
4421 void radv_CmdDrawIndirectCountKHR(
4422 VkCommandBuffer commandBuffer,
4423 VkBuffer _buffer,
4424 VkDeviceSize offset,
4425 VkBuffer _countBuffer,
4426 VkDeviceSize countBufferOffset,
4427 uint32_t maxDrawCount,
4428 uint32_t stride)
4429 {
4430 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4431 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4432 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4433 struct radv_draw_info info = {};
4434
4435 info.count = maxDrawCount;
4436 info.indirect = buffer;
4437 info.indirect_offset = offset;
4438 info.count_buffer = count_buffer;
4439 info.count_buffer_offset = countBufferOffset;
4440 info.stride = stride;
4441
4442 radv_draw(cmd_buffer, &info);
4443 }
4444
4445 void radv_CmdDrawIndexedIndirectCountKHR(
4446 VkCommandBuffer commandBuffer,
4447 VkBuffer _buffer,
4448 VkDeviceSize offset,
4449 VkBuffer _countBuffer,
4450 VkDeviceSize countBufferOffset,
4451 uint32_t maxDrawCount,
4452 uint32_t stride)
4453 {
4454 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4455 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4456 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4457 struct radv_draw_info info = {};
4458
4459 info.indexed = true;
4460 info.count = maxDrawCount;
4461 info.indirect = buffer;
4462 info.indirect_offset = offset;
4463 info.count_buffer = count_buffer;
4464 info.count_buffer_offset = countBufferOffset;
4465 info.stride = stride;
4466
4467 radv_draw(cmd_buffer, &info);
4468 }
4469
4470 struct radv_dispatch_info {
4471 /**
4472 * Determine the layout of the grid (in block units) to be used.
4473 */
4474 uint32_t blocks[3];
4475
4476 /**
4477 * A starting offset for the grid. If unaligned is set, the offset
4478 * must still be aligned.
4479 */
4480 uint32_t offsets[3];
4481 /**
4482 * Whether it's an unaligned compute dispatch.
4483 */
4484 bool unaligned;
4485
4486 /**
4487 * Indirect compute parameters resource.
4488 */
4489 struct radv_buffer *indirect;
4490 uint64_t indirect_offset;
4491 };
4492
4493 static void
4494 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4495 const struct radv_dispatch_info *info)
4496 {
4497 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4498 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4499 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4500 struct radeon_winsys *ws = cmd_buffer->device->ws;
4501 bool predicating = cmd_buffer->state.predicating;
4502 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4503 struct radv_userdata_info *loc;
4504
4505 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4506 AC_UD_CS_GRID_SIZE);
4507
4508 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4509
4510 if (info->indirect) {
4511 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4512
4513 va += info->indirect->offset + info->indirect_offset;
4514
4515 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4516
4517 if (loc->sgpr_idx != -1) {
4518 for (unsigned i = 0; i < 3; ++i) {
4519 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4520 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4521 COPY_DATA_DST_SEL(COPY_DATA_REG));
4522 radeon_emit(cs, (va + 4 * i));
4523 radeon_emit(cs, (va + 4 * i) >> 32);
4524 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4525 + loc->sgpr_idx * 4) >> 2) + i);
4526 radeon_emit(cs, 0);
4527 }
4528 }
4529
4530 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4531 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4532 PKT3_SHADER_TYPE_S(1));
4533 radeon_emit(cs, va);
4534 radeon_emit(cs, va >> 32);
4535 radeon_emit(cs, dispatch_initiator);
4536 } else {
4537 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4538 PKT3_SHADER_TYPE_S(1));
4539 radeon_emit(cs, 1);
4540 radeon_emit(cs, va);
4541 radeon_emit(cs, va >> 32);
4542
4543 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4544 PKT3_SHADER_TYPE_S(1));
4545 radeon_emit(cs, 0);
4546 radeon_emit(cs, dispatch_initiator);
4547 }
4548 } else {
4549 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4550 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4551
4552 if (info->unaligned) {
4553 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4554 unsigned remainder[3];
4555
4556 /* If aligned, these should be an entire block size,
4557 * not 0.
4558 */
4559 remainder[0] = blocks[0] + cs_block_size[0] -
4560 align_u32_npot(blocks[0], cs_block_size[0]);
4561 remainder[1] = blocks[1] + cs_block_size[1] -
4562 align_u32_npot(blocks[1], cs_block_size[1]);
4563 remainder[2] = blocks[2] + cs_block_size[2] -
4564 align_u32_npot(blocks[2], cs_block_size[2]);
4565
4566 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4567 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4568 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4569
4570 for(unsigned i = 0; i < 3; ++i) {
4571 assert(offsets[i] % cs_block_size[i] == 0);
4572 offsets[i] /= cs_block_size[i];
4573 }
4574
4575 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4576 radeon_emit(cs,
4577 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4578 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4579 radeon_emit(cs,
4580 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4581 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4582 radeon_emit(cs,
4583 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4584 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4585
4586 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4587 }
4588
4589 if (loc->sgpr_idx != -1) {
4590 assert(loc->num_sgprs == 3);
4591
4592 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4593 loc->sgpr_idx * 4, 3);
4594 radeon_emit(cs, blocks[0]);
4595 radeon_emit(cs, blocks[1]);
4596 radeon_emit(cs, blocks[2]);
4597 }
4598
4599 if (offsets[0] || offsets[1] || offsets[2]) {
4600 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4601 radeon_emit(cs, offsets[0]);
4602 radeon_emit(cs, offsets[1]);
4603 radeon_emit(cs, offsets[2]);
4604
4605 /* The blocks in the packet are not counts but end values. */
4606 for (unsigned i = 0; i < 3; ++i)
4607 blocks[i] += offsets[i];
4608 } else {
4609 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4610 }
4611
4612 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4613 PKT3_SHADER_TYPE_S(1));
4614 radeon_emit(cs, blocks[0]);
4615 radeon_emit(cs, blocks[1]);
4616 radeon_emit(cs, blocks[2]);
4617 radeon_emit(cs, dispatch_initiator);
4618 }
4619
4620 assert(cmd_buffer->cs->cdw <= cdw_max);
4621 }
4622
4623 static void
4624 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4625 {
4626 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4627 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4628 }
4629
4630 static void
4631 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4632 const struct radv_dispatch_info *info)
4633 {
4634 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4635 bool has_prefetch =
4636 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4637 bool pipeline_is_dirty = pipeline &&
4638 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4639
4640 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4641 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4642 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4643 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4644 /* If we have to wait for idle, set all states first, so that
4645 * all SET packets are processed in parallel with previous draw
4646 * calls. Then upload descriptors, set shader pointers, and
4647 * dispatch, and prefetch at the end. This ensures that the
4648 * time the CUs are idle is very short. (there are only SET_SH
4649 * packets between the wait and the draw)
4650 */
4651 radv_emit_compute_pipeline(cmd_buffer);
4652 si_emit_cache_flush(cmd_buffer);
4653 /* <-- CUs are idle here --> */
4654
4655 radv_upload_compute_shader_descriptors(cmd_buffer);
4656
4657 radv_emit_dispatch_packets(cmd_buffer, info);
4658 /* <-- CUs are busy here --> */
4659
4660 /* Start prefetches after the dispatch has been started. Both
4661 * will run in parallel, but starting the dispatch first is
4662 * more important.
4663 */
4664 if (has_prefetch && pipeline_is_dirty) {
4665 radv_emit_shader_prefetch(cmd_buffer,
4666 pipeline->shaders[MESA_SHADER_COMPUTE]);
4667 }
4668 } else {
4669 /* If we don't wait for idle, start prefetches first, then set
4670 * states, and dispatch at the end.
4671 */
4672 si_emit_cache_flush(cmd_buffer);
4673
4674 if (has_prefetch && pipeline_is_dirty) {
4675 radv_emit_shader_prefetch(cmd_buffer,
4676 pipeline->shaders[MESA_SHADER_COMPUTE]);
4677 }
4678
4679 radv_upload_compute_shader_descriptors(cmd_buffer);
4680
4681 radv_emit_compute_pipeline(cmd_buffer);
4682 radv_emit_dispatch_packets(cmd_buffer, info);
4683 }
4684
4685 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4686 }
4687
4688 void radv_CmdDispatchBase(
4689 VkCommandBuffer commandBuffer,
4690 uint32_t base_x,
4691 uint32_t base_y,
4692 uint32_t base_z,
4693 uint32_t x,
4694 uint32_t y,
4695 uint32_t z)
4696 {
4697 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4698 struct radv_dispatch_info info = {};
4699
4700 info.blocks[0] = x;
4701 info.blocks[1] = y;
4702 info.blocks[2] = z;
4703
4704 info.offsets[0] = base_x;
4705 info.offsets[1] = base_y;
4706 info.offsets[2] = base_z;
4707 radv_dispatch(cmd_buffer, &info);
4708 }
4709
4710 void radv_CmdDispatch(
4711 VkCommandBuffer commandBuffer,
4712 uint32_t x,
4713 uint32_t y,
4714 uint32_t z)
4715 {
4716 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4717 }
4718
4719 void radv_CmdDispatchIndirect(
4720 VkCommandBuffer commandBuffer,
4721 VkBuffer _buffer,
4722 VkDeviceSize offset)
4723 {
4724 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4725 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4726 struct radv_dispatch_info info = {};
4727
4728 info.indirect = buffer;
4729 info.indirect_offset = offset;
4730
4731 radv_dispatch(cmd_buffer, &info);
4732 }
4733
4734 void radv_unaligned_dispatch(
4735 struct radv_cmd_buffer *cmd_buffer,
4736 uint32_t x,
4737 uint32_t y,
4738 uint32_t z)
4739 {
4740 struct radv_dispatch_info info = {};
4741
4742 info.blocks[0] = x;
4743 info.blocks[1] = y;
4744 info.blocks[2] = z;
4745 info.unaligned = 1;
4746
4747 radv_dispatch(cmd_buffer, &info);
4748 }
4749
4750 void radv_CmdEndRenderPass(
4751 VkCommandBuffer commandBuffer)
4752 {
4753 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4754
4755 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4756
4757 radv_cmd_buffer_end_subpass(cmd_buffer);
4758
4759 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4760 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4761
4762 cmd_buffer->state.pass = NULL;
4763 cmd_buffer->state.subpass = NULL;
4764 cmd_buffer->state.attachments = NULL;
4765 cmd_buffer->state.framebuffer = NULL;
4766 cmd_buffer->state.subpass_sample_locs = NULL;
4767 }
4768
4769 void radv_CmdEndRenderPass2KHR(
4770 VkCommandBuffer commandBuffer,
4771 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4772 {
4773 radv_CmdEndRenderPass(commandBuffer);
4774 }
4775
4776 /*
4777 * For HTILE we have the following interesting clear words:
4778 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4779 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4780 * 0xfffffff0: Clear depth to 1.0
4781 * 0x00000000: Clear depth to 0.0
4782 */
4783 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4784 struct radv_image *image,
4785 const VkImageSubresourceRange *range,
4786 uint32_t clear_word)
4787 {
4788 assert(range->baseMipLevel == 0);
4789 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4790 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4791 struct radv_cmd_state *state = &cmd_buffer->state;
4792 VkClearDepthStencilValue value = {};
4793
4794 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4795 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4796
4797 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
4798
4799 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4800
4801 if (vk_format_is_stencil(image->vk_format))
4802 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4803
4804 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4805
4806 if (radv_image_is_tc_compat_htile(image)) {
4807 /* Initialize the TC-compat metada value to 0 because by
4808 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4809 * need have to conditionally update its value when performing
4810 * a fast depth clear.
4811 */
4812 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4813 }
4814 }
4815
4816 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4817 struct radv_image *image,
4818 VkImageLayout src_layout,
4819 VkImageLayout dst_layout,
4820 unsigned src_queue_mask,
4821 unsigned dst_queue_mask,
4822 const VkImageSubresourceRange *range,
4823 struct radv_sample_locations_state *sample_locs)
4824 {
4825 if (!radv_image_has_htile(image))
4826 return;
4827
4828 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4829 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4830
4831 if (radv_layout_is_htile_compressed(image, dst_layout,
4832 dst_queue_mask)) {
4833 clear_value = 0;
4834 }
4835
4836 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4837 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4838 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4839 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4840 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4841 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4842 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4843 VkImageSubresourceRange local_range = *range;
4844 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4845 local_range.baseMipLevel = 0;
4846 local_range.levelCount = 1;
4847
4848 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4849 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4850
4851 radv_decompress_depth_image_inplace(cmd_buffer, image,
4852 &local_range, sample_locs);
4853
4854 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4855 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4856 }
4857 }
4858
4859 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4860 struct radv_image *image, uint32_t value)
4861 {
4862 struct radv_cmd_state *state = &cmd_buffer->state;
4863
4864 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4865 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4866
4867 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4868
4869 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4870 }
4871
4872 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4873 struct radv_image *image)
4874 {
4875 struct radv_cmd_state *state = &cmd_buffer->state;
4876 static const uint32_t fmask_clear_values[4] = {
4877 0x00000000,
4878 0x02020202,
4879 0xE4E4E4E4,
4880 0x76543210
4881 };
4882 uint32_t log2_samples = util_logbase2(image->info.samples);
4883 uint32_t value = fmask_clear_values[log2_samples];
4884
4885 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4886 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4887
4888 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4889
4890 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4891 }
4892
4893 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4894 struct radv_image *image, uint32_t value)
4895 {
4896 struct radv_cmd_state *state = &cmd_buffer->state;
4897
4898 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4899 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4900
4901 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4902
4903 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4904 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4905 }
4906
4907 /**
4908 * Initialize DCC/FMASK/CMASK metadata for a color image.
4909 */
4910 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4911 struct radv_image *image,
4912 VkImageLayout src_layout,
4913 VkImageLayout dst_layout,
4914 unsigned src_queue_mask,
4915 unsigned dst_queue_mask,
4916 const VkImageSubresourceRange *range)
4917 {
4918 if (radv_image_has_cmask(image)) {
4919 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4920
4921 /* TODO: clarify this. */
4922 if (radv_image_has_fmask(image)) {
4923 value = 0xccccccccu;
4924 }
4925
4926 radv_initialise_cmask(cmd_buffer, image, value);
4927 }
4928
4929 if (radv_image_has_fmask(image)) {
4930 radv_initialize_fmask(cmd_buffer, image);
4931 }
4932
4933 if (radv_image_has_dcc(image)) {
4934 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4935 bool need_decompress_pass = false;
4936
4937 if (radv_layout_dcc_compressed(image, dst_layout,
4938 dst_queue_mask)) {
4939 value = 0x20202020u;
4940 need_decompress_pass = true;
4941 }
4942
4943 radv_initialize_dcc(cmd_buffer, image, value);
4944
4945 radv_update_fce_metadata(cmd_buffer, image, range,
4946 need_decompress_pass);
4947 }
4948
4949 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4950 uint32_t color_values[2] = {};
4951 radv_set_color_clear_metadata(cmd_buffer, image, range,
4952 color_values);
4953 }
4954 }
4955
4956 /**
4957 * Handle color image transitions for DCC/FMASK/CMASK.
4958 */
4959 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4960 struct radv_image *image,
4961 VkImageLayout src_layout,
4962 VkImageLayout dst_layout,
4963 unsigned src_queue_mask,
4964 unsigned dst_queue_mask,
4965 const VkImageSubresourceRange *range)
4966 {
4967 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4968 radv_init_color_image_metadata(cmd_buffer, image,
4969 src_layout, dst_layout,
4970 src_queue_mask, dst_queue_mask,
4971 range);
4972 return;
4973 }
4974
4975 if (radv_image_has_dcc(image)) {
4976 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4977 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4978 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4979 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4980 radv_decompress_dcc(cmd_buffer, image, range);
4981 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4982 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4983 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4984 }
4985 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4986 bool fce_eliminate = false, fmask_expand = false;
4987
4988 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4989 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4990 fce_eliminate = true;
4991 }
4992
4993 if (radv_image_has_fmask(image)) {
4994 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
4995 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
4996 /* A FMASK decompress is required before doing
4997 * a MSAA decompress using FMASK.
4998 */
4999 fmask_expand = true;
5000 }
5001 }
5002
5003 if (fce_eliminate || fmask_expand)
5004 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5005
5006 if (fmask_expand)
5007 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5008 }
5009 }
5010
5011 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5012 struct radv_image *image,
5013 VkImageLayout src_layout,
5014 VkImageLayout dst_layout,
5015 uint32_t src_family,
5016 uint32_t dst_family,
5017 const VkImageSubresourceRange *range,
5018 struct radv_sample_locations_state *sample_locs)
5019 {
5020 if (image->exclusive && src_family != dst_family) {
5021 /* This is an acquire or a release operation and there will be
5022 * a corresponding release/acquire. Do the transition in the
5023 * most flexible queue. */
5024
5025 assert(src_family == cmd_buffer->queue_family_index ||
5026 dst_family == cmd_buffer->queue_family_index);
5027
5028 if (src_family == VK_QUEUE_FAMILY_EXTERNAL)
5029 return;
5030
5031 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5032 return;
5033
5034 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5035 (src_family == RADV_QUEUE_GENERAL ||
5036 dst_family == RADV_QUEUE_GENERAL))
5037 return;
5038 }
5039
5040 if (src_layout == dst_layout)
5041 return;
5042
5043 unsigned src_queue_mask =
5044 radv_image_queue_family_mask(image, src_family,
5045 cmd_buffer->queue_family_index);
5046 unsigned dst_queue_mask =
5047 radv_image_queue_family_mask(image, dst_family,
5048 cmd_buffer->queue_family_index);
5049
5050 if (vk_format_is_depth(image->vk_format)) {
5051 radv_handle_depth_image_transition(cmd_buffer, image,
5052 src_layout, dst_layout,
5053 src_queue_mask, dst_queue_mask,
5054 range, sample_locs);
5055 } else {
5056 radv_handle_color_image_transition(cmd_buffer, image,
5057 src_layout, dst_layout,
5058 src_queue_mask, dst_queue_mask,
5059 range);
5060 }
5061 }
5062
5063 struct radv_barrier_info {
5064 uint32_t eventCount;
5065 const VkEvent *pEvents;
5066 VkPipelineStageFlags srcStageMask;
5067 VkPipelineStageFlags dstStageMask;
5068 };
5069
5070 static void
5071 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5072 uint32_t memoryBarrierCount,
5073 const VkMemoryBarrier *pMemoryBarriers,
5074 uint32_t bufferMemoryBarrierCount,
5075 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5076 uint32_t imageMemoryBarrierCount,
5077 const VkImageMemoryBarrier *pImageMemoryBarriers,
5078 const struct radv_barrier_info *info)
5079 {
5080 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5081 enum radv_cmd_flush_bits src_flush_bits = 0;
5082 enum radv_cmd_flush_bits dst_flush_bits = 0;
5083
5084 for (unsigned i = 0; i < info->eventCount; ++i) {
5085 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5086 uint64_t va = radv_buffer_get_va(event->bo);
5087
5088 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5089
5090 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5091
5092 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5093 assert(cmd_buffer->cs->cdw <= cdw_max);
5094 }
5095
5096 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5097 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5098 NULL);
5099 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5100 NULL);
5101 }
5102
5103 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5104 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5105 NULL);
5106 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5107 NULL);
5108 }
5109
5110 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5111 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5112
5113 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5114 image);
5115 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5116 image);
5117 }
5118
5119 /* The Vulkan spec 1.1.98 says:
5120 *
5121 * "An execution dependency with only
5122 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5123 * will only prevent that stage from executing in subsequently
5124 * submitted commands. As this stage does not perform any actual
5125 * execution, this is not observable - in effect, it does not delay
5126 * processing of subsequent commands. Similarly an execution dependency
5127 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5128 * will effectively not wait for any prior commands to complete."
5129 */
5130 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5131 radv_stage_flush(cmd_buffer, info->srcStageMask);
5132 cmd_buffer->state.flush_bits |= src_flush_bits;
5133
5134 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5135 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5136
5137 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5138 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5139 SAMPLE_LOCATIONS_INFO_EXT);
5140 struct radv_sample_locations_state sample_locations = {};
5141
5142 if (sample_locs_info) {
5143 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5144 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5145 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5146 sample_locations.count = sample_locs_info->sampleLocationsCount;
5147 typed_memcpy(&sample_locations.locations[0],
5148 sample_locs_info->pSampleLocations,
5149 sample_locs_info->sampleLocationsCount);
5150 }
5151
5152 radv_handle_image_transition(cmd_buffer, image,
5153 pImageMemoryBarriers[i].oldLayout,
5154 pImageMemoryBarriers[i].newLayout,
5155 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5156 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5157 &pImageMemoryBarriers[i].subresourceRange,
5158 sample_locs_info ? &sample_locations : NULL);
5159 }
5160
5161 /* Make sure CP DMA is idle because the driver might have performed a
5162 * DMA operation for copying or filling buffers/images.
5163 */
5164 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5165 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5166 si_cp_dma_wait_for_idle(cmd_buffer);
5167
5168 cmd_buffer->state.flush_bits |= dst_flush_bits;
5169 }
5170
5171 void radv_CmdPipelineBarrier(
5172 VkCommandBuffer commandBuffer,
5173 VkPipelineStageFlags srcStageMask,
5174 VkPipelineStageFlags destStageMask,
5175 VkBool32 byRegion,
5176 uint32_t memoryBarrierCount,
5177 const VkMemoryBarrier* pMemoryBarriers,
5178 uint32_t bufferMemoryBarrierCount,
5179 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5180 uint32_t imageMemoryBarrierCount,
5181 const VkImageMemoryBarrier* pImageMemoryBarriers)
5182 {
5183 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5184 struct radv_barrier_info info;
5185
5186 info.eventCount = 0;
5187 info.pEvents = NULL;
5188 info.srcStageMask = srcStageMask;
5189 info.dstStageMask = destStageMask;
5190
5191 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5192 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5193 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5194 }
5195
5196
5197 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5198 struct radv_event *event,
5199 VkPipelineStageFlags stageMask,
5200 unsigned value)
5201 {
5202 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5203 uint64_t va = radv_buffer_get_va(event->bo);
5204
5205 si_emit_cache_flush(cmd_buffer);
5206
5207 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5208
5209 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5210
5211 /* Flags that only require a top-of-pipe event. */
5212 VkPipelineStageFlags top_of_pipe_flags =
5213 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5214
5215 /* Flags that only require a post-index-fetch event. */
5216 VkPipelineStageFlags post_index_fetch_flags =
5217 top_of_pipe_flags |
5218 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5219 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5220
5221 /* Make sure CP DMA is idle because the driver might have performed a
5222 * DMA operation for copying or filling buffers/images.
5223 */
5224 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5225 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5226 si_cp_dma_wait_for_idle(cmd_buffer);
5227
5228 /* TODO: Emit EOS events for syncing PS/CS stages. */
5229
5230 if (!(stageMask & ~top_of_pipe_flags)) {
5231 /* Just need to sync the PFP engine. */
5232 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5233 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5234 S_370_WR_CONFIRM(1) |
5235 S_370_ENGINE_SEL(V_370_PFP));
5236 radeon_emit(cs, va);
5237 radeon_emit(cs, va >> 32);
5238 radeon_emit(cs, value);
5239 } else if (!(stageMask & ~post_index_fetch_flags)) {
5240 /* Sync ME because PFP reads index and indirect buffers. */
5241 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5242 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5243 S_370_WR_CONFIRM(1) |
5244 S_370_ENGINE_SEL(V_370_ME));
5245 radeon_emit(cs, va);
5246 radeon_emit(cs, va >> 32);
5247 radeon_emit(cs, value);
5248 } else {
5249 /* Otherwise, sync all prior GPU work using an EOP event. */
5250 si_cs_emit_write_event_eop(cs,
5251 cmd_buffer->device->physical_device->rad_info.chip_class,
5252 radv_cmd_buffer_uses_mec(cmd_buffer),
5253 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5254 EOP_DATA_SEL_VALUE_32BIT, va, value,
5255 cmd_buffer->gfx9_eop_bug_va);
5256 }
5257
5258 assert(cmd_buffer->cs->cdw <= cdw_max);
5259 }
5260
5261 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5262 VkEvent _event,
5263 VkPipelineStageFlags stageMask)
5264 {
5265 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5266 RADV_FROM_HANDLE(radv_event, event, _event);
5267
5268 write_event(cmd_buffer, event, stageMask, 1);
5269 }
5270
5271 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5272 VkEvent _event,
5273 VkPipelineStageFlags stageMask)
5274 {
5275 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5276 RADV_FROM_HANDLE(radv_event, event, _event);
5277
5278 write_event(cmd_buffer, event, stageMask, 0);
5279 }
5280
5281 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5282 uint32_t eventCount,
5283 const VkEvent* pEvents,
5284 VkPipelineStageFlags srcStageMask,
5285 VkPipelineStageFlags dstStageMask,
5286 uint32_t memoryBarrierCount,
5287 const VkMemoryBarrier* pMemoryBarriers,
5288 uint32_t bufferMemoryBarrierCount,
5289 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5290 uint32_t imageMemoryBarrierCount,
5291 const VkImageMemoryBarrier* pImageMemoryBarriers)
5292 {
5293 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5294 struct radv_barrier_info info;
5295
5296 info.eventCount = eventCount;
5297 info.pEvents = pEvents;
5298 info.srcStageMask = 0;
5299
5300 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5301 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5302 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5303 }
5304
5305
5306 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5307 uint32_t deviceMask)
5308 {
5309 /* No-op */
5310 }
5311
5312 /* VK_EXT_conditional_rendering */
5313 void radv_CmdBeginConditionalRenderingEXT(
5314 VkCommandBuffer commandBuffer,
5315 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5316 {
5317 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5318 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5319 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5320 bool draw_visible = true;
5321 uint64_t pred_value = 0;
5322 uint64_t va, new_va;
5323 unsigned pred_offset;
5324
5325 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5326
5327 /* By default, if the 32-bit value at offset in buffer memory is zero,
5328 * then the rendering commands are discarded, otherwise they are
5329 * executed as normal. If the inverted flag is set, all commands are
5330 * discarded if the value is non zero.
5331 */
5332 if (pConditionalRenderingBegin->flags &
5333 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5334 draw_visible = false;
5335 }
5336
5337 si_emit_cache_flush(cmd_buffer);
5338
5339 /* From the Vulkan spec 1.1.107:
5340 *
5341 * "If the 32-bit value at offset in buffer memory is zero, then the
5342 * rendering commands are discarded, otherwise they are executed as
5343 * normal. If the value of the predicate in buffer memory changes while
5344 * conditional rendering is active, the rendering commands may be
5345 * discarded in an implementation-dependent way. Some implementations
5346 * may latch the value of the predicate upon beginning conditional
5347 * rendering while others may read it before every rendering command."
5348 *
5349 * But, the AMD hardware treats the predicate as a 64-bit value which
5350 * means we need a workaround in the driver. Luckily, it's not required
5351 * to support if the value changes when predication is active.
5352 *
5353 * The workaround is as follows:
5354 * 1) allocate a 64-value in the upload BO and initialize it to 0
5355 * 2) copy the 32-bit predicate value to the upload BO
5356 * 3) use the new allocated VA address for predication
5357 *
5358 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5359 * in ME (+ sync PFP) instead of PFP.
5360 */
5361 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5362
5363 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5364
5365 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5366 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5367 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5368 COPY_DATA_WR_CONFIRM);
5369 radeon_emit(cs, va);
5370 radeon_emit(cs, va >> 32);
5371 radeon_emit(cs, new_va);
5372 radeon_emit(cs, new_va >> 32);
5373
5374 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5375 radeon_emit(cs, 0);
5376
5377 /* Enable predication for this command buffer. */
5378 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5379 cmd_buffer->state.predicating = true;
5380
5381 /* Store conditional rendering user info. */
5382 cmd_buffer->state.predication_type = draw_visible;
5383 cmd_buffer->state.predication_va = new_va;
5384 }
5385
5386 void radv_CmdEndConditionalRenderingEXT(
5387 VkCommandBuffer commandBuffer)
5388 {
5389 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5390
5391 /* Disable predication for this command buffer. */
5392 si_emit_set_predication_state(cmd_buffer, false, 0);
5393 cmd_buffer->state.predicating = false;
5394
5395 /* Reset conditional rendering user info. */
5396 cmd_buffer->state.predication_type = -1;
5397 cmd_buffer->state.predication_va = 0;
5398 }
5399
5400 /* VK_EXT_transform_feedback */
5401 void radv_CmdBindTransformFeedbackBuffersEXT(
5402 VkCommandBuffer commandBuffer,
5403 uint32_t firstBinding,
5404 uint32_t bindingCount,
5405 const VkBuffer* pBuffers,
5406 const VkDeviceSize* pOffsets,
5407 const VkDeviceSize* pSizes)
5408 {
5409 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5410 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5411 uint8_t enabled_mask = 0;
5412
5413 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5414 for (uint32_t i = 0; i < bindingCount; i++) {
5415 uint32_t idx = firstBinding + i;
5416
5417 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5418 sb[idx].offset = pOffsets[i];
5419 sb[idx].size = pSizes[i];
5420
5421 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5422 sb[idx].buffer->bo);
5423
5424 enabled_mask |= 1 << idx;
5425 }
5426
5427 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5428
5429 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5430 }
5431
5432 static void
5433 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5434 {
5435 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5436 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5437
5438 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5439 radeon_emit(cs,
5440 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5441 S_028B94_RAST_STREAM(0) |
5442 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5443 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5444 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5445 radeon_emit(cs, so->hw_enabled_mask &
5446 so->enabled_stream_buffers_mask);
5447
5448 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5449 }
5450
5451 static void
5452 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5453 {
5454 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5455 bool old_streamout_enabled = so->streamout_enabled;
5456 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5457
5458 so->streamout_enabled = enable;
5459
5460 so->hw_enabled_mask = so->enabled_mask |
5461 (so->enabled_mask << 4) |
5462 (so->enabled_mask << 8) |
5463 (so->enabled_mask << 12);
5464
5465 if ((old_streamout_enabled != so->streamout_enabled) ||
5466 (old_hw_enabled_mask != so->hw_enabled_mask))
5467 radv_emit_streamout_enable(cmd_buffer);
5468 }
5469
5470 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5471 {
5472 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5473 unsigned reg_strmout_cntl;
5474
5475 /* The register is at different places on different ASICs. */
5476 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5477 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5478 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5479 } else {
5480 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5481 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5482 }
5483
5484 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5485 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5486
5487 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5488 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5489 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5490 radeon_emit(cs, 0);
5491 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5492 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5493 radeon_emit(cs, 4); /* poll interval */
5494 }
5495
5496 void radv_CmdBeginTransformFeedbackEXT(
5497 VkCommandBuffer commandBuffer,
5498 uint32_t firstCounterBuffer,
5499 uint32_t counterBufferCount,
5500 const VkBuffer* pCounterBuffers,
5501 const VkDeviceSize* pCounterBufferOffsets)
5502 {
5503 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5504 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5505 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5506 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5507 uint32_t i;
5508
5509 radv_flush_vgt_streamout(cmd_buffer);
5510
5511 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5512 for_each_bit(i, so->enabled_mask) {
5513 int32_t counter_buffer_idx = i - firstCounterBuffer;
5514 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5515 counter_buffer_idx = -1;
5516
5517 /* AMD GCN binds streamout buffers as shader resources.
5518 * VGT only counts primitives and tells the shader through
5519 * SGPRs what to do.
5520 */
5521 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5522 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5523 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5524
5525 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5526
5527 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5528 /* The array of counter buffers is optional. */
5529 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5530 uint64_t va = radv_buffer_get_va(buffer->bo);
5531
5532 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5533
5534 /* Append */
5535 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5536 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5537 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5538 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5539 radeon_emit(cs, 0); /* unused */
5540 radeon_emit(cs, 0); /* unused */
5541 radeon_emit(cs, va); /* src address lo */
5542 radeon_emit(cs, va >> 32); /* src address hi */
5543
5544 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5545 } else {
5546 /* Start from the beginning. */
5547 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5548 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5549 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5550 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5551 radeon_emit(cs, 0); /* unused */
5552 radeon_emit(cs, 0); /* unused */
5553 radeon_emit(cs, 0); /* unused */
5554 radeon_emit(cs, 0); /* unused */
5555 }
5556 }
5557
5558 radv_set_streamout_enable(cmd_buffer, true);
5559 }
5560
5561 void radv_CmdEndTransformFeedbackEXT(
5562 VkCommandBuffer commandBuffer,
5563 uint32_t firstCounterBuffer,
5564 uint32_t counterBufferCount,
5565 const VkBuffer* pCounterBuffers,
5566 const VkDeviceSize* pCounterBufferOffsets)
5567 {
5568 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5569 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5570 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5571 uint32_t i;
5572
5573 radv_flush_vgt_streamout(cmd_buffer);
5574
5575 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5576 for_each_bit(i, so->enabled_mask) {
5577 int32_t counter_buffer_idx = i - firstCounterBuffer;
5578 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5579 counter_buffer_idx = -1;
5580
5581 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5582 /* The array of counters buffer is optional. */
5583 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5584 uint64_t va = radv_buffer_get_va(buffer->bo);
5585
5586 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5587
5588 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5589 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5590 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5591 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5592 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5593 radeon_emit(cs, va); /* dst address lo */
5594 radeon_emit(cs, va >> 32); /* dst address hi */
5595 radeon_emit(cs, 0); /* unused */
5596 radeon_emit(cs, 0); /* unused */
5597
5598 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5599 }
5600
5601 /* Deactivate transform feedback by zeroing the buffer size.
5602 * The counters (primitives generated, primitives emitted) may
5603 * be enabled even if there is not buffer bound. This ensures
5604 * that the primitives-emitted query won't increment.
5605 */
5606 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5607
5608 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5609 }
5610
5611 radv_set_streamout_enable(cmd_buffer, false);
5612 }
5613
5614 void radv_CmdDrawIndirectByteCountEXT(
5615 VkCommandBuffer commandBuffer,
5616 uint32_t instanceCount,
5617 uint32_t firstInstance,
5618 VkBuffer _counterBuffer,
5619 VkDeviceSize counterBufferOffset,
5620 uint32_t counterOffset,
5621 uint32_t vertexStride)
5622 {
5623 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5624 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5625 struct radv_draw_info info = {};
5626
5627 info.instance_count = instanceCount;
5628 info.first_instance = firstInstance;
5629 info.strmout_buffer = counterBuffer;
5630 info.strmout_buffer_offset = counterBufferOffset;
5631 info.stride = vertexStride;
5632
5633 radv_draw(cmd_buffer, &info);
5634 }