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amd: remove support for LLVM 6.0
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range);
61
62 const struct radv_dynamic_state default_dynamic_state = {
63 .viewport = {
64 .count = 0,
65 },
66 .scissor = {
67 .count = 0,
68 },
69 .line_width = 1.0f,
70 .depth_bias = {
71 .bias = 0.0f,
72 .clamp = 0.0f,
73 .slope = 0.0f,
74 },
75 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
76 .depth_bounds = {
77 .min = 0.0f,
78 .max = 1.0f,
79 },
80 .stencil_compare_mask = {
81 .front = ~0u,
82 .back = ~0u,
83 },
84 .stencil_write_mask = {
85 .front = ~0u,
86 .back = ~0u,
87 },
88 .stencil_reference = {
89 .front = 0u,
90 .back = 0u,
91 },
92 };
93
94 static void
95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
96 const struct radv_dynamic_state *src)
97 {
98 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
99 uint32_t copy_mask = src->mask;
100 uint32_t dest_mask = 0;
101
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
104 */
105 dest->viewport.count = src->viewport.count;
106 dest->scissor.count = src->scissor.count;
107 dest->discard_rectangle.count = src->discard_rectangle.count;
108
109 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
110 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
111 src->viewport.count * sizeof(VkViewport))) {
112 typed_memcpy(dest->viewport.viewports,
113 src->viewport.viewports,
114 src->viewport.count);
115 dest_mask |= RADV_DYNAMIC_VIEWPORT;
116 }
117 }
118
119 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
120 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
121 src->scissor.count * sizeof(VkRect2D))) {
122 typed_memcpy(dest->scissor.scissors,
123 src->scissor.scissors, src->scissor.count);
124 dest_mask |= RADV_DYNAMIC_SCISSOR;
125 }
126 }
127
128 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
129 if (dest->line_width != src->line_width) {
130 dest->line_width = src->line_width;
131 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
132 }
133 }
134
135 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
136 if (memcmp(&dest->depth_bias, &src->depth_bias,
137 sizeof(src->depth_bias))) {
138 dest->depth_bias = src->depth_bias;
139 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
144 if (memcmp(&dest->blend_constants, &src->blend_constants,
145 sizeof(src->blend_constants))) {
146 typed_memcpy(dest->blend_constants,
147 src->blend_constants, 4);
148 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
149 }
150 }
151
152 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
153 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
154 sizeof(src->depth_bounds))) {
155 dest->depth_bounds = src->depth_bounds;
156 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
161 if (memcmp(&dest->stencil_compare_mask,
162 &src->stencil_compare_mask,
163 sizeof(src->stencil_compare_mask))) {
164 dest->stencil_compare_mask = src->stencil_compare_mask;
165 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
166 }
167 }
168
169 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
170 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
171 sizeof(src->stencil_write_mask))) {
172 dest->stencil_write_mask = src->stencil_write_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
178 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
179 sizeof(src->stencil_reference))) {
180 dest->stencil_reference = src->stencil_reference;
181 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
186 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
187 src->discard_rectangle.count * sizeof(VkRect2D))) {
188 typed_memcpy(dest->discard_rectangle.rectangles,
189 src->discard_rectangle.rectangles,
190 src->discard_rectangle.count);
191 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
192 }
193 }
194
195 cmd_buffer->state.dirty |= dest_mask;
196 }
197
198 static void
199 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
200 struct radv_pipeline *pipeline)
201 {
202 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
203 struct radv_shader_info *info;
204
205 if (!pipeline->streamout_shader)
206 return;
207
208 info = &pipeline->streamout_shader->info.info;
209 for (int i = 0; i < MAX_SO_BUFFERS; i++)
210 so->stride_in_dw[i] = info->so.strides[i];
211
212 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
213 }
214
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
216 {
217 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
218 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
219 }
220
221 enum ring_type radv_queue_family_to_ring(int f) {
222 switch (f) {
223 case RADV_QUEUE_GENERAL:
224 return RING_GFX;
225 case RADV_QUEUE_COMPUTE:
226 return RING_COMPUTE;
227 case RADV_QUEUE_TRANSFER:
228 return RING_DMA;
229 default:
230 unreachable("Unknown queue family");
231 }
232 }
233
234 static VkResult radv_create_cmd_buffer(
235 struct radv_device * device,
236 struct radv_cmd_pool * pool,
237 VkCommandBufferLevel level,
238 VkCommandBuffer* pCommandBuffer)
239 {
240 struct radv_cmd_buffer *cmd_buffer;
241 unsigned ring;
242 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
244 if (cmd_buffer == NULL)
245 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
246
247 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 cmd_buffer->device = device;
249 cmd_buffer->pool = pool;
250 cmd_buffer->level = level;
251
252 if (pool) {
253 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
254 cmd_buffer->queue_family_index = pool->queue_family_index;
255
256 } else {
257 /* Init the pool_link so we can safely call list_del when we destroy
258 * the command buffer
259 */
260 list_inithead(&cmd_buffer->pool_link);
261 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
262 }
263
264 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
265
266 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
267 if (!cmd_buffer->cs) {
268 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
269 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
270 }
271
272 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
273
274 list_inithead(&cmd_buffer->upload.list);
275
276 return VK_SUCCESS;
277 }
278
279 static void
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
281 {
282 list_del(&cmd_buffer->pool_link);
283
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
285 &cmd_buffer->upload.list, list) {
286 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
287 list_del(&up->list);
288 free(up);
289 }
290
291 if (cmd_buffer->upload.upload_bo)
292 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
293 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
294
295 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
296 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
297
298 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
299 }
300
301 static VkResult
302 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
303 {
304
305 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
306
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
308 &cmd_buffer->upload.list, list) {
309 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
310 list_del(&up->list);
311 free(up);
312 }
313
314 cmd_buffer->push_constant_stages = 0;
315 cmd_buffer->scratch_size_needed = 0;
316 cmd_buffer->compute_scratch_size_needed = 0;
317 cmd_buffer->esgs_ring_size_needed = 0;
318 cmd_buffer->gsvs_ring_size_needed = 0;
319 cmd_buffer->tess_rings_needed = false;
320 cmd_buffer->sample_positions_needed = false;
321
322 if (cmd_buffer->upload.upload_bo)
323 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
324 cmd_buffer->upload.upload_bo);
325 cmd_buffer->upload.offset = 0;
326
327 cmd_buffer->record_result = VK_SUCCESS;
328
329 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
330 cmd_buffer->descriptors[i].dirty = 0;
331 cmd_buffer->descriptors[i].valid = 0;
332 cmd_buffer->descriptors[i].push_dirty = false;
333 }
334
335 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
336 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
337 unsigned eop_bug_offset;
338 void *fence_ptr;
339
340 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
341 &cmd_buffer->gfx9_fence_offset,
342 &fence_ptr);
343 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
344
345 /* Allocate a buffer for the EOP bug on GFX9. */
346 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
347 &eop_bug_offset, &fence_ptr);
348 cmd_buffer->gfx9_eop_bug_va =
349 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
350 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
351 }
352
353 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
354
355 return cmd_buffer->record_result;
356 }
357
358 static bool
359 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
360 uint64_t min_needed)
361 {
362 uint64_t new_size;
363 struct radeon_winsys_bo *bo;
364 struct radv_cmd_buffer_upload *upload;
365 struct radv_device *device = cmd_buffer->device;
366
367 new_size = MAX2(min_needed, 16 * 1024);
368 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
369
370 bo = device->ws->buffer_create(device->ws,
371 new_size, 4096,
372 RADEON_DOMAIN_GTT,
373 RADEON_FLAG_CPU_ACCESS|
374 RADEON_FLAG_NO_INTERPROCESS_SHARING |
375 RADEON_FLAG_32BIT);
376
377 if (!bo) {
378 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
379 return false;
380 }
381
382 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
383 if (cmd_buffer->upload.upload_bo) {
384 upload = malloc(sizeof(*upload));
385
386 if (!upload) {
387 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
388 device->ws->buffer_destroy(bo);
389 return false;
390 }
391
392 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
393 list_add(&upload->list, &cmd_buffer->upload.list);
394 }
395
396 cmd_buffer->upload.upload_bo = bo;
397 cmd_buffer->upload.size = new_size;
398 cmd_buffer->upload.offset = 0;
399 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
400
401 if (!cmd_buffer->upload.map) {
402 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
403 return false;
404 }
405
406 return true;
407 }
408
409 bool
410 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
411 unsigned size,
412 unsigned alignment,
413 unsigned *out_offset,
414 void **ptr)
415 {
416 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
417 if (offset + size > cmd_buffer->upload.size) {
418 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
419 return false;
420 offset = 0;
421 }
422
423 *out_offset = offset;
424 *ptr = cmd_buffer->upload.map + offset;
425
426 cmd_buffer->upload.offset = offset + size;
427 return true;
428 }
429
430 bool
431 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
432 unsigned size, unsigned alignment,
433 const void *data, unsigned *out_offset)
434 {
435 uint8_t *ptr;
436
437 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
438 out_offset, (void **)&ptr))
439 return false;
440
441 if (ptr)
442 memcpy(ptr, data, size);
443
444 return true;
445 }
446
447 static void
448 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
449 unsigned count, const uint32_t *data)
450 {
451 struct radeon_cmdbuf *cs = cmd_buffer->cs;
452
453 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
454
455 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
456 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
457 S_370_WR_CONFIRM(1) |
458 S_370_ENGINE_SEL(V_370_ME));
459 radeon_emit(cs, va);
460 radeon_emit(cs, va >> 32);
461 radeon_emit_array(cs, data, count);
462 }
463
464 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
465 {
466 struct radv_device *device = cmd_buffer->device;
467 struct radeon_cmdbuf *cs = cmd_buffer->cs;
468 uint64_t va;
469
470 va = radv_buffer_get_va(device->trace_bo);
471 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
472 va += 4;
473
474 ++cmd_buffer->state.trace_id;
475 radv_emit_write_data_packet(cmd_buffer, va, 1,
476 &cmd_buffer->state.trace_id);
477
478 radeon_check_space(cmd_buffer->device->ws, cs, 2);
479
480 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
481 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
482 }
483
484 static void
485 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
486 enum radv_cmd_flush_bits flags)
487 {
488 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
489 uint32_t *ptr = NULL;
490 uint64_t va = 0;
491
492 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
493 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
494
495 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
496 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
497 cmd_buffer->gfx9_fence_offset;
498 ptr = &cmd_buffer->gfx9_fence_idx;
499 }
500
501 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
502
503 /* Force wait for graphics or compute engines to be idle. */
504 si_cs_emit_cache_flush(cmd_buffer->cs,
505 cmd_buffer->device->physical_device->rad_info.chip_class,
506 ptr, va,
507 radv_cmd_buffer_uses_mec(cmd_buffer),
508 flags, cmd_buffer->gfx9_eop_bug_va);
509 }
510
511 if (unlikely(cmd_buffer->device->trace_bo))
512 radv_cmd_buffer_trace_emit(cmd_buffer);
513 }
514
515 static void
516 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
517 struct radv_pipeline *pipeline, enum ring_type ring)
518 {
519 struct radv_device *device = cmd_buffer->device;
520 uint32_t data[2];
521 uint64_t va;
522
523 va = radv_buffer_get_va(device->trace_bo);
524
525 switch (ring) {
526 case RING_GFX:
527 va += 8;
528 break;
529 case RING_COMPUTE:
530 va += 16;
531 break;
532 default:
533 assert(!"invalid ring type");
534 }
535
536 data[0] = (uintptr_t)pipeline;
537 data[1] = (uintptr_t)pipeline >> 32;
538
539 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
540 }
541
542 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
543 VkPipelineBindPoint bind_point,
544 struct radv_descriptor_set *set,
545 unsigned idx)
546 {
547 struct radv_descriptor_state *descriptors_state =
548 radv_get_descriptors_state(cmd_buffer, bind_point);
549
550 descriptors_state->sets[idx] = set;
551
552 descriptors_state->valid |= (1u << idx); /* active descriptors */
553 descriptors_state->dirty |= (1u << idx);
554 }
555
556 static void
557 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
558 VkPipelineBindPoint bind_point)
559 {
560 struct radv_descriptor_state *descriptors_state =
561 radv_get_descriptors_state(cmd_buffer, bind_point);
562 struct radv_device *device = cmd_buffer->device;
563 uint32_t data[MAX_SETS * 2] = {};
564 uint64_t va;
565 unsigned i;
566 va = radv_buffer_get_va(device->trace_bo) + 24;
567
568 for_each_bit(i, descriptors_state->valid) {
569 struct radv_descriptor_set *set = descriptors_state->sets[i];
570 data[i * 2] = (uintptr_t)set;
571 data[i * 2 + 1] = (uintptr_t)set >> 32;
572 }
573
574 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
575 }
576
577 struct radv_userdata_info *
578 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
579 gl_shader_stage stage,
580 int idx)
581 {
582 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
583 return &shader->info.user_sgprs_locs.shader_data[idx];
584 }
585
586 static void
587 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
588 struct radv_pipeline *pipeline,
589 gl_shader_stage stage,
590 int idx, uint64_t va)
591 {
592 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
593 uint32_t base_reg = pipeline->user_data_0[stage];
594 if (loc->sgpr_idx == -1)
595 return;
596
597 assert(loc->num_sgprs == 1);
598 assert(!loc->indirect);
599
600 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
601 base_reg + loc->sgpr_idx * 4, va, false);
602 }
603
604 static void
605 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
606 struct radv_pipeline *pipeline,
607 struct radv_descriptor_state *descriptors_state,
608 gl_shader_stage stage)
609 {
610 struct radv_device *device = cmd_buffer->device;
611 struct radeon_cmdbuf *cs = cmd_buffer->cs;
612 uint32_t sh_base = pipeline->user_data_0[stage];
613 struct radv_userdata_locations *locs =
614 &pipeline->shaders[stage]->info.user_sgprs_locs;
615 unsigned mask = locs->descriptor_sets_enabled;
616
617 mask &= descriptors_state->dirty & descriptors_state->valid;
618
619 while (mask) {
620 int start, count;
621
622 u_bit_scan_consecutive_range(&mask, &start, &count);
623
624 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
625 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
626
627 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
628 for (int i = 0; i < count; i++) {
629 struct radv_descriptor_set *set =
630 descriptors_state->sets[start + i];
631
632 radv_emit_shader_pointer_body(device, cs, set->va, true);
633 }
634 }
635 }
636
637 static void
638 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
639 struct radv_pipeline *pipeline)
640 {
641 int num_samples = pipeline->graphics.ms.num_samples;
642 struct radv_multisample_state *ms = &pipeline->graphics.ms;
643 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
644
645 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
646 cmd_buffer->sample_positions_needed = true;
647
648 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
649 return;
650
651 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
652 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
653 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
654
655 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
656
657 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
658
659 /* GFX9: Flush DFSM when the AA mode changes. */
660 if (cmd_buffer->device->dfsm_allowed) {
661 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
662 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
663 }
664 }
665
666 static void
667 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
668 struct radv_shader_variant *shader)
669 {
670 uint64_t va;
671
672 if (!shader)
673 return;
674
675 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
676
677 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
678 }
679
680 static void
681 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
682 struct radv_pipeline *pipeline,
683 bool vertex_stage_only)
684 {
685 struct radv_cmd_state *state = &cmd_buffer->state;
686 uint32_t mask = state->prefetch_L2_mask;
687
688 if (vertex_stage_only) {
689 /* Fast prefetch path for starting draws as soon as possible.
690 */
691 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
692 RADV_PREFETCH_VBO_DESCRIPTORS);
693 }
694
695 if (mask & RADV_PREFETCH_VS)
696 radv_emit_shader_prefetch(cmd_buffer,
697 pipeline->shaders[MESA_SHADER_VERTEX]);
698
699 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
700 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
701
702 if (mask & RADV_PREFETCH_TCS)
703 radv_emit_shader_prefetch(cmd_buffer,
704 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
705
706 if (mask & RADV_PREFETCH_TES)
707 radv_emit_shader_prefetch(cmd_buffer,
708 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
709
710 if (mask & RADV_PREFETCH_GS) {
711 radv_emit_shader_prefetch(cmd_buffer,
712 pipeline->shaders[MESA_SHADER_GEOMETRY]);
713 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
714 }
715
716 if (mask & RADV_PREFETCH_PS)
717 radv_emit_shader_prefetch(cmd_buffer,
718 pipeline->shaders[MESA_SHADER_FRAGMENT]);
719
720 state->prefetch_L2_mask &= ~mask;
721 }
722
723 static void
724 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
725 {
726 if (!cmd_buffer->device->physical_device->rbplus_allowed)
727 return;
728
729 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
730 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
731 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
732
733 unsigned sx_ps_downconvert = 0;
734 unsigned sx_blend_opt_epsilon = 0;
735 unsigned sx_blend_opt_control = 0;
736
737 for (unsigned i = 0; i < subpass->color_count; ++i) {
738 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
739 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
740 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
741 continue;
742 }
743
744 int idx = subpass->color_attachments[i].attachment;
745 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
746
747 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
748 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
749 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
750 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
751
752 bool has_alpha, has_rgb;
753
754 /* Set if RGB and A are present. */
755 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
756
757 if (format == V_028C70_COLOR_8 ||
758 format == V_028C70_COLOR_16 ||
759 format == V_028C70_COLOR_32)
760 has_rgb = !has_alpha;
761 else
762 has_rgb = true;
763
764 /* Check the colormask and export format. */
765 if (!(colormask & 0x7))
766 has_rgb = false;
767 if (!(colormask & 0x8))
768 has_alpha = false;
769
770 if (spi_format == V_028714_SPI_SHADER_ZERO) {
771 has_rgb = false;
772 has_alpha = false;
773 }
774
775 /* Disable value checking for disabled channels. */
776 if (!has_rgb)
777 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
778 if (!has_alpha)
779 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
780
781 /* Enable down-conversion for 32bpp and smaller formats. */
782 switch (format) {
783 case V_028C70_COLOR_8:
784 case V_028C70_COLOR_8_8:
785 case V_028C70_COLOR_8_8_8_8:
786 /* For 1 and 2-channel formats, use the superset thereof. */
787 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
788 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
789 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
790 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
791 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
792 }
793 break;
794
795 case V_028C70_COLOR_5_6_5:
796 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
797 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
798 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
799 }
800 break;
801
802 case V_028C70_COLOR_1_5_5_5:
803 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
804 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
805 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
806 }
807 break;
808
809 case V_028C70_COLOR_4_4_4_4:
810 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
811 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
812 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
813 }
814 break;
815
816 case V_028C70_COLOR_32:
817 if (swap == V_028C70_SWAP_STD &&
818 spi_format == V_028714_SPI_SHADER_32_R)
819 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
820 else if (swap == V_028C70_SWAP_ALT_REV &&
821 spi_format == V_028714_SPI_SHADER_32_AR)
822 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
823 break;
824
825 case V_028C70_COLOR_16:
826 case V_028C70_COLOR_16_16:
827 /* For 1-channel formats, use the superset thereof. */
828 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
829 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
830 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
831 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
832 if (swap == V_028C70_SWAP_STD ||
833 swap == V_028C70_SWAP_STD_REV)
834 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
835 else
836 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
837 }
838 break;
839
840 case V_028C70_COLOR_10_11_11:
841 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
842 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
843 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
844 }
845 break;
846
847 case V_028C70_COLOR_2_10_10_10:
848 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
849 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
850 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
851 }
852 break;
853 }
854 }
855
856 for (unsigned i = subpass->color_count; i < 8; ++i) {
857 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
858 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
859 }
860 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
861 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
862 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
863 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
864 }
865
866 static void
867 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
868 {
869 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
870
871 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
872 return;
873
874 radv_update_multisample_state(cmd_buffer, pipeline);
875
876 cmd_buffer->scratch_size_needed =
877 MAX2(cmd_buffer->scratch_size_needed,
878 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
879
880 if (!cmd_buffer->state.emitted_pipeline ||
881 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
882 pipeline->graphics.can_use_guardband)
883 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
884
885 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
886
887 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
888 if (!pipeline->shaders[i])
889 continue;
890
891 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
892 pipeline->shaders[i]->bo);
893 }
894
895 if (radv_pipeline_has_gs(pipeline))
896 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
897 pipeline->gs_copy_shader->bo);
898
899 if (unlikely(cmd_buffer->device->trace_bo))
900 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
901
902 cmd_buffer->state.emitted_pipeline = pipeline;
903
904 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
905 }
906
907 static void
908 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
909 {
910 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
911 cmd_buffer->state.dynamic.viewport.viewports);
912 }
913
914 static void
915 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
916 {
917 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
918
919 si_write_scissors(cmd_buffer->cs, 0, count,
920 cmd_buffer->state.dynamic.scissor.scissors,
921 cmd_buffer->state.dynamic.viewport.viewports,
922 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
923 }
924
925 static void
926 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
927 {
928 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
929 return;
930
931 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
932 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
933 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
934 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
935 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
936 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
937 S_028214_BR_Y(rect.offset.y + rect.extent.height));
938 }
939 }
940
941 static void
942 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
943 {
944 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
945
946 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
947 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
948 }
949
950 static void
951 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
952 {
953 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
954
955 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
956 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
957 }
958
959 static void
960 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
961 {
962 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
963
964 radeon_set_context_reg_seq(cmd_buffer->cs,
965 R_028430_DB_STENCILREFMASK, 2);
966 radeon_emit(cmd_buffer->cs,
967 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
968 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
969 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
970 S_028430_STENCILOPVAL(1));
971 radeon_emit(cmd_buffer->cs,
972 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
973 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
974 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
975 S_028434_STENCILOPVAL_BF(1));
976 }
977
978 static void
979 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
980 {
981 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
982
983 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
984 fui(d->depth_bounds.min));
985 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
986 fui(d->depth_bounds.max));
987 }
988
989 static void
990 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
991 {
992 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
993 unsigned slope = fui(d->depth_bias.slope * 16.0f);
994 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
995
996
997 radeon_set_context_reg_seq(cmd_buffer->cs,
998 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
999 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1000 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1001 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1002 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1003 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1004 }
1005
1006 static void
1007 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1008 int index,
1009 struct radv_attachment_info *att,
1010 struct radv_image *image,
1011 VkImageLayout layout)
1012 {
1013 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1014 struct radv_color_buffer_info *cb = &att->cb;
1015 uint32_t cb_color_info = cb->cb_color_info;
1016
1017 if (!radv_layout_dcc_compressed(image, layout,
1018 radv_image_queue_family_mask(image,
1019 cmd_buffer->queue_family_index,
1020 cmd_buffer->queue_family_index))) {
1021 cb_color_info &= C_028C70_DCC_ENABLE;
1022 }
1023
1024 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1025 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1026 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1027 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1028 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1029 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1030 radeon_emit(cmd_buffer->cs, cb_color_info);
1031 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1032 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1033 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1034 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1035 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1036 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1037
1038 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1039 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1040 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1041
1042 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1043 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1044 } else {
1045 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1046 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1047 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1048 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1049 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1050 radeon_emit(cmd_buffer->cs, cb_color_info);
1051 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1052 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1053 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1054 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1055 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1056 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1057
1058 if (is_vi) { /* DCC BASE */
1059 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1060 }
1061 }
1062 }
1063
1064 static void
1065 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1066 struct radv_ds_buffer_info *ds,
1067 struct radv_image *image, VkImageLayout layout,
1068 bool requires_cond_exec)
1069 {
1070 uint32_t db_z_info = ds->db_z_info;
1071 uint32_t db_z_info_reg;
1072
1073 if (!radv_image_is_tc_compat_htile(image))
1074 return;
1075
1076 if (!radv_layout_has_htile(image, layout,
1077 radv_image_queue_family_mask(image,
1078 cmd_buffer->queue_family_index,
1079 cmd_buffer->queue_family_index))) {
1080 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1081 }
1082
1083 db_z_info &= C_028040_ZRANGE_PRECISION;
1084
1085 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1086 db_z_info_reg = R_028038_DB_Z_INFO;
1087 } else {
1088 db_z_info_reg = R_028040_DB_Z_INFO;
1089 }
1090
1091 /* When we don't know the last fast clear value we need to emit a
1092 * conditional packet that will eventually skip the following
1093 * SET_CONTEXT_REG packet.
1094 */
1095 if (requires_cond_exec) {
1096 uint64_t va = radv_buffer_get_va(image->bo);
1097 va += image->offset + image->tc_compat_zrange_offset;
1098
1099 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1100 radeon_emit(cmd_buffer->cs, va);
1101 radeon_emit(cmd_buffer->cs, va >> 32);
1102 radeon_emit(cmd_buffer->cs, 0);
1103 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1104 }
1105
1106 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1107 }
1108
1109 static void
1110 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1111 struct radv_ds_buffer_info *ds,
1112 struct radv_image *image,
1113 VkImageLayout layout)
1114 {
1115 uint32_t db_z_info = ds->db_z_info;
1116 uint32_t db_stencil_info = ds->db_stencil_info;
1117
1118 if (!radv_layout_has_htile(image, layout,
1119 radv_image_queue_family_mask(image,
1120 cmd_buffer->queue_family_index,
1121 cmd_buffer->queue_family_index))) {
1122 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1123 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1124 }
1125
1126 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1127 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1128
1129
1130 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1131 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1132 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1133 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1134 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1135
1136 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1137 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1138 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1139 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1140 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1141 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1142 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1143 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1144 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1145 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1146 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1147
1148 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1149 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1150 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1151 } else {
1152 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1153
1154 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1155 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1156 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1157 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1158 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1159 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1160 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1161 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1162 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1163 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1164
1165 }
1166
1167 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1168 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1169
1170 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1171 ds->pa_su_poly_offset_db_fmt_cntl);
1172 }
1173
1174 /**
1175 * Update the fast clear depth/stencil values if the image is bound as a
1176 * depth/stencil buffer.
1177 */
1178 static void
1179 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1180 struct radv_image *image,
1181 VkClearDepthStencilValue ds_clear_value,
1182 VkImageAspectFlags aspects)
1183 {
1184 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1185 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1186 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1187 struct radv_attachment_info *att;
1188 uint32_t att_idx;
1189
1190 if (!framebuffer || !subpass)
1191 return;
1192
1193 att_idx = subpass->depth_stencil_attachment.attachment;
1194 if (att_idx == VK_ATTACHMENT_UNUSED)
1195 return;
1196
1197 att = &framebuffer->attachments[att_idx];
1198 if (att->attachment->image != image)
1199 return;
1200
1201 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1202 radeon_emit(cs, ds_clear_value.stencil);
1203 radeon_emit(cs, fui(ds_clear_value.depth));
1204
1205 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1206 * only needed when clearing Z to 0.0.
1207 */
1208 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1209 ds_clear_value.depth == 0.0) {
1210 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1211
1212 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1213 layout, false);
1214 }
1215 }
1216
1217 /**
1218 * Set the clear depth/stencil values to the image's metadata.
1219 */
1220 static void
1221 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1222 struct radv_image *image,
1223 VkClearDepthStencilValue ds_clear_value,
1224 VkImageAspectFlags aspects)
1225 {
1226 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1227 uint64_t va = radv_buffer_get_va(image->bo);
1228 unsigned reg_offset = 0, reg_count = 0;
1229
1230 va += image->offset + image->clear_value_offset;
1231
1232 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1233 ++reg_count;
1234 } else {
1235 ++reg_offset;
1236 va += 4;
1237 }
1238 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1239 ++reg_count;
1240
1241 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1242 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1243 S_370_WR_CONFIRM(1) |
1244 S_370_ENGINE_SEL(V_370_PFP));
1245 radeon_emit(cs, va);
1246 radeon_emit(cs, va >> 32);
1247 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1248 radeon_emit(cs, ds_clear_value.stencil);
1249 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1250 radeon_emit(cs, fui(ds_clear_value.depth));
1251 }
1252
1253 /**
1254 * Update the TC-compat metadata value for this image.
1255 */
1256 static void
1257 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1258 struct radv_image *image,
1259 uint32_t value)
1260 {
1261 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1262 uint64_t va = radv_buffer_get_va(image->bo);
1263 va += image->offset + image->tc_compat_zrange_offset;
1264
1265 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1266 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1267 S_370_WR_CONFIRM(1) |
1268 S_370_ENGINE_SEL(V_370_PFP));
1269 radeon_emit(cs, va);
1270 radeon_emit(cs, va >> 32);
1271 radeon_emit(cs, value);
1272 }
1273
1274 static void
1275 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1276 struct radv_image *image,
1277 VkClearDepthStencilValue ds_clear_value)
1278 {
1279 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1280 uint64_t va = radv_buffer_get_va(image->bo);
1281 va += image->offset + image->tc_compat_zrange_offset;
1282 uint32_t cond_val;
1283
1284 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1285 * depth clear value is 0.0f.
1286 */
1287 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1288
1289 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1290 }
1291
1292 /**
1293 * Update the clear depth/stencil values for this image.
1294 */
1295 void
1296 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1297 struct radv_image *image,
1298 VkClearDepthStencilValue ds_clear_value,
1299 VkImageAspectFlags aspects)
1300 {
1301 assert(radv_image_has_htile(image));
1302
1303 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1304
1305 if (radv_image_is_tc_compat_htile(image) &&
1306 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1307 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1308 ds_clear_value);
1309 }
1310
1311 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1312 aspects);
1313 }
1314
1315 /**
1316 * Load the clear depth/stencil values from the image's metadata.
1317 */
1318 static void
1319 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1320 struct radv_image *image)
1321 {
1322 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1323 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1324 uint64_t va = radv_buffer_get_va(image->bo);
1325 unsigned reg_offset = 0, reg_count = 0;
1326
1327 va += image->offset + image->clear_value_offset;
1328
1329 if (!radv_image_has_htile(image))
1330 return;
1331
1332 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1333 ++reg_count;
1334 } else {
1335 ++reg_offset;
1336 va += 4;
1337 }
1338 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1339 ++reg_count;
1340
1341 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1342
1343 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1344 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1345 radeon_emit(cs, va);
1346 radeon_emit(cs, va >> 32);
1347 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1348 radeon_emit(cs, reg_count);
1349 } else {
1350 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1351 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1352 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1353 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1354 radeon_emit(cs, va);
1355 radeon_emit(cs, va >> 32);
1356 radeon_emit(cs, reg >> 2);
1357 radeon_emit(cs, 0);
1358
1359 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1360 radeon_emit(cs, 0);
1361 }
1362 }
1363
1364 /*
1365 * With DCC some colors don't require CMASK elimination before being
1366 * used as a texture. This sets a predicate value to determine if the
1367 * cmask eliminate is required.
1368 */
1369 void
1370 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1371 struct radv_image *image, bool value)
1372 {
1373 uint64_t pred_val = value;
1374 uint64_t va = radv_buffer_get_va(image->bo);
1375 va += image->offset + image->fce_pred_offset;
1376
1377 assert(radv_image_has_dcc(image));
1378
1379 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1380 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1381 S_370_WR_CONFIRM(1) |
1382 S_370_ENGINE_SEL(V_370_PFP));
1383 radeon_emit(cmd_buffer->cs, va);
1384 radeon_emit(cmd_buffer->cs, va >> 32);
1385 radeon_emit(cmd_buffer->cs, pred_val);
1386 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1387 }
1388
1389 /**
1390 * Update the fast clear color values if the image is bound as a color buffer.
1391 */
1392 static void
1393 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1394 struct radv_image *image,
1395 int cb_idx,
1396 uint32_t color_values[2])
1397 {
1398 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1399 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1400 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1401 struct radv_attachment_info *att;
1402 uint32_t att_idx;
1403
1404 if (!framebuffer || !subpass)
1405 return;
1406
1407 att_idx = subpass->color_attachments[cb_idx].attachment;
1408 if (att_idx == VK_ATTACHMENT_UNUSED)
1409 return;
1410
1411 att = &framebuffer->attachments[att_idx];
1412 if (att->attachment->image != image)
1413 return;
1414
1415 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1416 radeon_emit(cs, color_values[0]);
1417 radeon_emit(cs, color_values[1]);
1418 }
1419
1420 /**
1421 * Set the clear color values to the image's metadata.
1422 */
1423 static void
1424 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1425 struct radv_image *image,
1426 uint32_t color_values[2])
1427 {
1428 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1429 uint64_t va = radv_buffer_get_va(image->bo);
1430
1431 va += image->offset + image->clear_value_offset;
1432
1433 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1434
1435 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1436 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1437 S_370_WR_CONFIRM(1) |
1438 S_370_ENGINE_SEL(V_370_PFP));
1439 radeon_emit(cs, va);
1440 radeon_emit(cs, va >> 32);
1441 radeon_emit(cs, color_values[0]);
1442 radeon_emit(cs, color_values[1]);
1443 }
1444
1445 /**
1446 * Update the clear color values for this image.
1447 */
1448 void
1449 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1450 struct radv_image *image,
1451 int cb_idx,
1452 uint32_t color_values[2])
1453 {
1454 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1455
1456 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1457
1458 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1459 color_values);
1460 }
1461
1462 /**
1463 * Load the clear color values from the image's metadata.
1464 */
1465 static void
1466 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1467 struct radv_image *image,
1468 int cb_idx)
1469 {
1470 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1471 uint64_t va = radv_buffer_get_va(image->bo);
1472
1473 va += image->offset + image->clear_value_offset;
1474
1475 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1476 return;
1477
1478 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1479
1480 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1481 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1482 radeon_emit(cs, va);
1483 radeon_emit(cs, va >> 32);
1484 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1485 radeon_emit(cs, 2);
1486 } else {
1487 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1488 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1489 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1490 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1491 COPY_DATA_COUNT_SEL);
1492 radeon_emit(cs, va);
1493 radeon_emit(cs, va >> 32);
1494 radeon_emit(cs, reg >> 2);
1495 radeon_emit(cs, 0);
1496
1497 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1498 radeon_emit(cs, 0);
1499 }
1500 }
1501
1502 static void
1503 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1504 {
1505 int i;
1506 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1507 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1508 unsigned num_bpp64_colorbufs = 0;
1509
1510 /* this may happen for inherited secondary recording */
1511 if (!framebuffer)
1512 return;
1513
1514 for (i = 0; i < 8; ++i) {
1515 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1516 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1517 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1518 continue;
1519 }
1520
1521 int idx = subpass->color_attachments[i].attachment;
1522 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1523 struct radv_image *image = att->attachment->image;
1524 VkImageLayout layout = subpass->color_attachments[i].layout;
1525
1526 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1527
1528 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1529 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1530
1531 radv_load_color_clear_metadata(cmd_buffer, image, i);
1532
1533 if (image->surface.bpe >= 8)
1534 num_bpp64_colorbufs++;
1535 }
1536
1537 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1538 int idx = subpass->depth_stencil_attachment.attachment;
1539 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1540 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1541 struct radv_image *image = att->attachment->image;
1542 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1543 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1544 cmd_buffer->queue_family_index,
1545 cmd_buffer->queue_family_index);
1546 /* We currently don't support writing decompressed HTILE */
1547 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1548 radv_layout_is_htile_compressed(image, layout, queue_mask));
1549
1550 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1551
1552 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1553 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1554 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1555 }
1556 radv_load_ds_clear_metadata(cmd_buffer, image);
1557 } else {
1558 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1559 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1560 else
1561 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1562
1563 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1564 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1565 }
1566 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1567 S_028208_BR_X(framebuffer->width) |
1568 S_028208_BR_Y(framebuffer->height));
1569
1570 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1571 uint8_t watermark = 4; /* Default value for VI. */
1572
1573 /* For optimal DCC performance. */
1574 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1575 if (num_bpp64_colorbufs >= 5) {
1576 watermark = 8;
1577 } else {
1578 watermark = 6;
1579 }
1580 }
1581
1582 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1583 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1584 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1585 }
1586
1587 if (cmd_buffer->device->dfsm_allowed) {
1588 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1589 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1590 }
1591
1592 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1593 }
1594
1595 static void
1596 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1597 {
1598 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1599 struct radv_cmd_state *state = &cmd_buffer->state;
1600
1601 if (state->index_type != state->last_index_type) {
1602 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1603 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1604 2, state->index_type);
1605 } else {
1606 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1607 radeon_emit(cs, state->index_type);
1608 }
1609
1610 state->last_index_type = state->index_type;
1611 }
1612
1613 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1614 radeon_emit(cs, state->index_va);
1615 radeon_emit(cs, state->index_va >> 32);
1616
1617 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1618 radeon_emit(cs, state->max_index_count);
1619
1620 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1621 }
1622
1623 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1624 {
1625 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1626 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1627 uint32_t pa_sc_mode_cntl_1 =
1628 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1629 uint32_t db_count_control;
1630
1631 if(!cmd_buffer->state.active_occlusion_queries) {
1632 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1633 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1634 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1635 has_perfect_queries) {
1636 /* Re-enable out-of-order rasterization if the
1637 * bound pipeline supports it and if it's has
1638 * been disabled before starting any perfect
1639 * occlusion queries.
1640 */
1641 radeon_set_context_reg(cmd_buffer->cs,
1642 R_028A4C_PA_SC_MODE_CNTL_1,
1643 pa_sc_mode_cntl_1);
1644 }
1645 }
1646 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1647 } else {
1648 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1649 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1650
1651 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1652 db_count_control =
1653 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1654 S_028004_SAMPLE_RATE(sample_rate) |
1655 S_028004_ZPASS_ENABLE(1) |
1656 S_028004_SLICE_EVEN_ENABLE(1) |
1657 S_028004_SLICE_ODD_ENABLE(1);
1658
1659 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1660 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1661 has_perfect_queries) {
1662 /* If the bound pipeline has enabled
1663 * out-of-order rasterization, we should
1664 * disable it before starting any perfect
1665 * occlusion queries.
1666 */
1667 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1668
1669 radeon_set_context_reg(cmd_buffer->cs,
1670 R_028A4C_PA_SC_MODE_CNTL_1,
1671 pa_sc_mode_cntl_1);
1672 }
1673 } else {
1674 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1675 S_028004_SAMPLE_RATE(sample_rate);
1676 }
1677 }
1678
1679 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1680 }
1681
1682 static void
1683 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1684 {
1685 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1686
1687 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1688 radv_emit_viewport(cmd_buffer);
1689
1690 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1691 !cmd_buffer->device->physical_device->has_scissor_bug)
1692 radv_emit_scissor(cmd_buffer);
1693
1694 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1695 radv_emit_line_width(cmd_buffer);
1696
1697 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1698 radv_emit_blend_constants(cmd_buffer);
1699
1700 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1701 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1702 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1703 radv_emit_stencil(cmd_buffer);
1704
1705 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1706 radv_emit_depth_bounds(cmd_buffer);
1707
1708 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1709 radv_emit_depth_bias(cmd_buffer);
1710
1711 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1712 radv_emit_discard_rectangle(cmd_buffer);
1713
1714 cmd_buffer->state.dirty &= ~states;
1715 }
1716
1717 static void
1718 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1719 VkPipelineBindPoint bind_point)
1720 {
1721 struct radv_descriptor_state *descriptors_state =
1722 radv_get_descriptors_state(cmd_buffer, bind_point);
1723 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1724 unsigned bo_offset;
1725
1726 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1727 set->mapped_ptr,
1728 &bo_offset))
1729 return;
1730
1731 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1732 set->va += bo_offset;
1733 }
1734
1735 static void
1736 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1737 VkPipelineBindPoint bind_point)
1738 {
1739 struct radv_descriptor_state *descriptors_state =
1740 radv_get_descriptors_state(cmd_buffer, bind_point);
1741 uint32_t size = MAX_SETS * 4;
1742 uint32_t offset;
1743 void *ptr;
1744
1745 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1746 256, &offset, &ptr))
1747 return;
1748
1749 for (unsigned i = 0; i < MAX_SETS; i++) {
1750 uint32_t *uptr = ((uint32_t *)ptr) + i;
1751 uint64_t set_va = 0;
1752 struct radv_descriptor_set *set = descriptors_state->sets[i];
1753 if (descriptors_state->valid & (1u << i))
1754 set_va = set->va;
1755 uptr[0] = set_va & 0xffffffff;
1756 }
1757
1758 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1759 va += offset;
1760
1761 if (cmd_buffer->state.pipeline) {
1762 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1763 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1764 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1765
1766 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1767 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1768 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1769
1770 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1771 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1772 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1773
1774 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1775 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1776 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1777
1778 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1779 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1780 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1781 }
1782
1783 if (cmd_buffer->state.compute_pipeline)
1784 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1785 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1786 }
1787
1788 static void
1789 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1790 VkShaderStageFlags stages)
1791 {
1792 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1793 VK_PIPELINE_BIND_POINT_COMPUTE :
1794 VK_PIPELINE_BIND_POINT_GRAPHICS;
1795 struct radv_descriptor_state *descriptors_state =
1796 radv_get_descriptors_state(cmd_buffer, bind_point);
1797 struct radv_cmd_state *state = &cmd_buffer->state;
1798 bool flush_indirect_descriptors;
1799
1800 if (!descriptors_state->dirty)
1801 return;
1802
1803 if (descriptors_state->push_dirty)
1804 radv_flush_push_descriptors(cmd_buffer, bind_point);
1805
1806 flush_indirect_descriptors =
1807 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1808 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1809 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1810 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1811
1812 if (flush_indirect_descriptors)
1813 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1814
1815 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1816 cmd_buffer->cs,
1817 MAX_SETS * MESA_SHADER_STAGES * 4);
1818
1819 if (cmd_buffer->state.pipeline) {
1820 radv_foreach_stage(stage, stages) {
1821 if (!cmd_buffer->state.pipeline->shaders[stage])
1822 continue;
1823
1824 radv_emit_descriptor_pointers(cmd_buffer,
1825 cmd_buffer->state.pipeline,
1826 descriptors_state, stage);
1827 }
1828 }
1829
1830 if (cmd_buffer->state.compute_pipeline &&
1831 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1832 radv_emit_descriptor_pointers(cmd_buffer,
1833 cmd_buffer->state.compute_pipeline,
1834 descriptors_state,
1835 MESA_SHADER_COMPUTE);
1836 }
1837
1838 descriptors_state->dirty = 0;
1839 descriptors_state->push_dirty = false;
1840
1841 assert(cmd_buffer->cs->cdw <= cdw_max);
1842
1843 if (unlikely(cmd_buffer->device->trace_bo))
1844 radv_save_descriptors(cmd_buffer, bind_point);
1845 }
1846
1847 static void
1848 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1849 VkShaderStageFlags stages)
1850 {
1851 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1852 ? cmd_buffer->state.compute_pipeline
1853 : cmd_buffer->state.pipeline;
1854 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1855 VK_PIPELINE_BIND_POINT_COMPUTE :
1856 VK_PIPELINE_BIND_POINT_GRAPHICS;
1857 struct radv_descriptor_state *descriptors_state =
1858 radv_get_descriptors_state(cmd_buffer, bind_point);
1859 struct radv_pipeline_layout *layout = pipeline->layout;
1860 struct radv_shader_variant *shader, *prev_shader;
1861 unsigned offset;
1862 void *ptr;
1863 uint64_t va;
1864
1865 stages &= cmd_buffer->push_constant_stages;
1866 if (!stages ||
1867 (!layout->push_constant_size && !layout->dynamic_offset_count))
1868 return;
1869
1870 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1871 16 * layout->dynamic_offset_count,
1872 256, &offset, &ptr))
1873 return;
1874
1875 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1876 memcpy((char*)ptr + layout->push_constant_size,
1877 descriptors_state->dynamic_buffers,
1878 16 * layout->dynamic_offset_count);
1879
1880 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1881 va += offset;
1882
1883 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1884 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1885
1886 prev_shader = NULL;
1887 radv_foreach_stage(stage, stages) {
1888 shader = radv_get_shader(pipeline, stage);
1889
1890 /* Avoid redundantly emitting the address for merged stages. */
1891 if (shader && shader != prev_shader) {
1892 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1893 AC_UD_PUSH_CONSTANTS, va);
1894
1895 prev_shader = shader;
1896 }
1897 }
1898
1899 cmd_buffer->push_constant_stages &= ~stages;
1900 assert(cmd_buffer->cs->cdw <= cdw_max);
1901 }
1902
1903 static void
1904 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1905 bool pipeline_is_dirty)
1906 {
1907 if ((pipeline_is_dirty ||
1908 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1909 cmd_buffer->state.pipeline->vertex_elements.count &&
1910 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1911 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1912 unsigned vb_offset;
1913 void *vb_ptr;
1914 uint32_t i = 0;
1915 uint32_t count = velems->count;
1916 uint64_t va;
1917
1918 /* allocate some descriptor state for vertex buffers */
1919 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1920 &vb_offset, &vb_ptr))
1921 return;
1922
1923 for (i = 0; i < count; i++) {
1924 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1925 uint32_t offset;
1926 int vb = velems->binding[i];
1927 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1928 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1929
1930 va = radv_buffer_get_va(buffer->bo);
1931
1932 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1933 va += offset + buffer->offset;
1934 desc[0] = va;
1935 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1936 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1937 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1938 else
1939 desc[2] = buffer->size - offset;
1940 desc[3] = velems->rsrc_word3[i];
1941 }
1942
1943 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1944 va += vb_offset;
1945
1946 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1947 AC_UD_VS_VERTEX_BUFFERS, va);
1948
1949 cmd_buffer->state.vb_va = va;
1950 cmd_buffer->state.vb_size = count * 16;
1951 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1952 }
1953 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1954 }
1955
1956 static void
1957 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1958 {
1959 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1960 struct radv_userdata_info *loc;
1961 uint32_t base_reg;
1962
1963 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
1964 if (!radv_get_shader(pipeline, stage))
1965 continue;
1966
1967 loc = radv_lookup_user_sgpr(pipeline, stage,
1968 AC_UD_STREAMOUT_BUFFERS);
1969 if (loc->sgpr_idx == -1)
1970 continue;
1971
1972 base_reg = pipeline->user_data_0[stage];
1973
1974 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1975 base_reg + loc->sgpr_idx * 4, va, false);
1976 }
1977
1978 if (pipeline->gs_copy_shader) {
1979 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
1980 if (loc->sgpr_idx != -1) {
1981 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
1982
1983 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1984 base_reg + loc->sgpr_idx * 4, va, false);
1985 }
1986 }
1987 }
1988
1989 static void
1990 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
1991 {
1992 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
1993 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
1994 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
1995 unsigned so_offset;
1996 void *so_ptr;
1997 uint64_t va;
1998
1999 /* Allocate some descriptor state for streamout buffers. */
2000 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2001 MAX_SO_BUFFERS * 16, 256,
2002 &so_offset, &so_ptr))
2003 return;
2004
2005 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2006 struct radv_buffer *buffer = sb[i].buffer;
2007 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2008
2009 if (!(so->enabled_mask & (1 << i)))
2010 continue;
2011
2012 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2013
2014 va += sb[i].offset;
2015
2016 /* Set the descriptor.
2017 *
2018 * On VI, the format must be non-INVALID, otherwise
2019 * the buffer will be considered not bound and store
2020 * instructions will be no-ops.
2021 */
2022 desc[0] = va;
2023 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2024 desc[2] = 0xffffffff;
2025 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2026 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2027 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2028 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2029 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2030 }
2031
2032 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2033 va += so_offset;
2034
2035 radv_emit_streamout_buffers(cmd_buffer, va);
2036 }
2037
2038 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2039 }
2040
2041 static void
2042 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2043 {
2044 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2045 radv_flush_streamout_descriptors(cmd_buffer);
2046 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2047 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2048 }
2049
2050 static void
2051 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
2052 bool instanced_draw, bool indirect_draw,
2053 uint32_t draw_vertex_count)
2054 {
2055 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2056 struct radv_cmd_state *state = &cmd_buffer->state;
2057 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2058 uint32_t ia_multi_vgt_param;
2059 int32_t primitive_reset_en;
2060
2061 /* Draw state. */
2062 ia_multi_vgt_param =
2063 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2064 indirect_draw, draw_vertex_count);
2065
2066 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2067 if (info->chip_class >= GFX9) {
2068 radeon_set_uconfig_reg_idx(cs,
2069 R_030960_IA_MULTI_VGT_PARAM,
2070 4, ia_multi_vgt_param);
2071 } else if (info->chip_class >= CIK) {
2072 radeon_set_context_reg_idx(cs,
2073 R_028AA8_IA_MULTI_VGT_PARAM,
2074 1, ia_multi_vgt_param);
2075 } else {
2076 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2077 ia_multi_vgt_param);
2078 }
2079 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2080 }
2081
2082 /* Primitive restart. */
2083 primitive_reset_en =
2084 indexed_draw && state->pipeline->graphics.prim_restart_enable;
2085
2086 if (primitive_reset_en != state->last_primitive_reset_en) {
2087 state->last_primitive_reset_en = primitive_reset_en;
2088 if (info->chip_class >= GFX9) {
2089 radeon_set_uconfig_reg(cs,
2090 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2091 primitive_reset_en);
2092 } else {
2093 radeon_set_context_reg(cs,
2094 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2095 primitive_reset_en);
2096 }
2097 }
2098
2099 if (primitive_reset_en) {
2100 uint32_t primitive_reset_index =
2101 state->index_type ? 0xffffffffu : 0xffffu;
2102
2103 if (primitive_reset_index != state->last_primitive_reset_index) {
2104 radeon_set_context_reg(cs,
2105 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2106 primitive_reset_index);
2107 state->last_primitive_reset_index = primitive_reset_index;
2108 }
2109 }
2110 }
2111
2112 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2113 VkPipelineStageFlags src_stage_mask)
2114 {
2115 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2116 VK_PIPELINE_STAGE_TRANSFER_BIT |
2117 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2118 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2119 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2120 }
2121
2122 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2123 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2124 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2125 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2126 VK_PIPELINE_STAGE_TRANSFER_BIT |
2127 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2128 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2129 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2130 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2131 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2132 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2133 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2134 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2135 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2136 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2137 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2138 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2139 }
2140 }
2141
2142 static enum radv_cmd_flush_bits
2143 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2144 VkAccessFlags src_flags,
2145 struct radv_image *image)
2146 {
2147 bool flush_CB_meta = true, flush_DB_meta = true;
2148 enum radv_cmd_flush_bits flush_bits = 0;
2149 uint32_t b;
2150
2151 if (image) {
2152 if (!radv_image_has_CB_metadata(image))
2153 flush_CB_meta = false;
2154 if (!radv_image_has_htile(image))
2155 flush_DB_meta = false;
2156 }
2157
2158 for_each_bit(b, src_flags) {
2159 switch ((VkAccessFlagBits)(1 << b)) {
2160 case VK_ACCESS_SHADER_WRITE_BIT:
2161 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2162 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2163 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2164 break;
2165 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2166 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2167 if (flush_CB_meta)
2168 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2169 break;
2170 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2171 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2172 if (flush_DB_meta)
2173 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2174 break;
2175 case VK_ACCESS_TRANSFER_WRITE_BIT:
2176 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2177 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2178 RADV_CMD_FLAG_INV_GLOBAL_L2;
2179
2180 if (flush_CB_meta)
2181 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2182 if (flush_DB_meta)
2183 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2184 break;
2185 default:
2186 break;
2187 }
2188 }
2189 return flush_bits;
2190 }
2191
2192 static enum radv_cmd_flush_bits
2193 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2194 VkAccessFlags dst_flags,
2195 struct radv_image *image)
2196 {
2197 bool flush_CB_meta = true, flush_DB_meta = true;
2198 enum radv_cmd_flush_bits flush_bits = 0;
2199 bool flush_CB = true, flush_DB = true;
2200 bool image_is_coherent = false;
2201 uint32_t b;
2202
2203 if (image) {
2204 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2205 flush_CB = false;
2206 flush_DB = false;
2207 }
2208
2209 if (!radv_image_has_CB_metadata(image))
2210 flush_CB_meta = false;
2211 if (!radv_image_has_htile(image))
2212 flush_DB_meta = false;
2213
2214 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2215 if (image->info.samples == 1 &&
2216 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2217 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2218 !vk_format_is_stencil(image->vk_format)) {
2219 /* Single-sample color and single-sample depth
2220 * (not stencil) are coherent with shaders on
2221 * GFX9.
2222 */
2223 image_is_coherent = true;
2224 }
2225 }
2226 }
2227
2228 for_each_bit(b, dst_flags) {
2229 switch ((VkAccessFlagBits)(1 << b)) {
2230 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2231 case VK_ACCESS_INDEX_READ_BIT:
2232 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2233 break;
2234 case VK_ACCESS_UNIFORM_READ_BIT:
2235 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2236 break;
2237 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2238 case VK_ACCESS_TRANSFER_READ_BIT:
2239 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2240 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2241 RADV_CMD_FLAG_INV_GLOBAL_L2;
2242 break;
2243 case VK_ACCESS_SHADER_READ_BIT:
2244 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2245
2246 if (!image_is_coherent)
2247 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2248 break;
2249 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2250 if (flush_CB)
2251 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2252 if (flush_CB_meta)
2253 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2254 break;
2255 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2256 if (flush_DB)
2257 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2258 if (flush_DB_meta)
2259 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2260 break;
2261 default:
2262 break;
2263 }
2264 }
2265 return flush_bits;
2266 }
2267
2268 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2269 const struct radv_subpass_barrier *barrier)
2270 {
2271 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2272 NULL);
2273 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2274 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2275 NULL);
2276 }
2277
2278 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2279 struct radv_subpass_attachment att)
2280 {
2281 unsigned idx = att.attachment;
2282 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2283 VkImageSubresourceRange range;
2284 range.aspectMask = 0;
2285 range.baseMipLevel = view->base_mip;
2286 range.levelCount = 1;
2287 range.baseArrayLayer = view->base_layer;
2288 range.layerCount = cmd_buffer->state.framebuffer->layers;
2289
2290 radv_handle_image_transition(cmd_buffer,
2291 view->image,
2292 cmd_buffer->state.attachments[idx].current_layout,
2293 att.layout, 0, 0, &range);
2294
2295 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2296
2297
2298 }
2299
2300 void
2301 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2302 const struct radv_subpass *subpass, bool transitions)
2303 {
2304 if (transitions) {
2305 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2306
2307 for (unsigned i = 0; i < subpass->color_count; ++i) {
2308 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2309 radv_handle_subpass_image_transition(cmd_buffer,
2310 subpass->color_attachments[i]);
2311 }
2312
2313 for (unsigned i = 0; i < subpass->input_count; ++i) {
2314 radv_handle_subpass_image_transition(cmd_buffer,
2315 subpass->input_attachments[i]);
2316 }
2317
2318 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2319 radv_handle_subpass_image_transition(cmd_buffer,
2320 subpass->depth_stencil_attachment);
2321 }
2322 }
2323
2324 cmd_buffer->state.subpass = subpass;
2325
2326 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2327 }
2328
2329 static VkResult
2330 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2331 struct radv_render_pass *pass,
2332 const VkRenderPassBeginInfo *info)
2333 {
2334 struct radv_cmd_state *state = &cmd_buffer->state;
2335
2336 if (pass->attachment_count == 0) {
2337 state->attachments = NULL;
2338 return VK_SUCCESS;
2339 }
2340
2341 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2342 pass->attachment_count *
2343 sizeof(state->attachments[0]),
2344 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2345 if (state->attachments == NULL) {
2346 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2347 return cmd_buffer->record_result;
2348 }
2349
2350 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2351 struct radv_render_pass_attachment *att = &pass->attachments[i];
2352 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2353 VkImageAspectFlags clear_aspects = 0;
2354
2355 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2356 /* color attachment */
2357 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2358 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2359 }
2360 } else {
2361 /* depthstencil attachment */
2362 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2363 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2364 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2365 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2366 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2367 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2368 }
2369 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2370 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2371 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2372 }
2373 }
2374
2375 state->attachments[i].pending_clear_aspects = clear_aspects;
2376 state->attachments[i].cleared_views = 0;
2377 if (clear_aspects && info) {
2378 assert(info->clearValueCount > i);
2379 state->attachments[i].clear_value = info->pClearValues[i];
2380 }
2381
2382 state->attachments[i].current_layout = att->initial_layout;
2383 }
2384
2385 return VK_SUCCESS;
2386 }
2387
2388 VkResult radv_AllocateCommandBuffers(
2389 VkDevice _device,
2390 const VkCommandBufferAllocateInfo *pAllocateInfo,
2391 VkCommandBuffer *pCommandBuffers)
2392 {
2393 RADV_FROM_HANDLE(radv_device, device, _device);
2394 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2395
2396 VkResult result = VK_SUCCESS;
2397 uint32_t i;
2398
2399 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2400
2401 if (!list_empty(&pool->free_cmd_buffers)) {
2402 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2403
2404 list_del(&cmd_buffer->pool_link);
2405 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2406
2407 result = radv_reset_cmd_buffer(cmd_buffer);
2408 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2409 cmd_buffer->level = pAllocateInfo->level;
2410
2411 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2412 } else {
2413 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2414 &pCommandBuffers[i]);
2415 }
2416 if (result != VK_SUCCESS)
2417 break;
2418 }
2419
2420 if (result != VK_SUCCESS) {
2421 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2422 i, pCommandBuffers);
2423
2424 /* From the Vulkan 1.0.66 spec:
2425 *
2426 * "vkAllocateCommandBuffers can be used to create multiple
2427 * command buffers. If the creation of any of those command
2428 * buffers fails, the implementation must destroy all
2429 * successfully created command buffer objects from this
2430 * command, set all entries of the pCommandBuffers array to
2431 * NULL and return the error."
2432 */
2433 memset(pCommandBuffers, 0,
2434 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2435 }
2436
2437 return result;
2438 }
2439
2440 void radv_FreeCommandBuffers(
2441 VkDevice device,
2442 VkCommandPool commandPool,
2443 uint32_t commandBufferCount,
2444 const VkCommandBuffer *pCommandBuffers)
2445 {
2446 for (uint32_t i = 0; i < commandBufferCount; i++) {
2447 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2448
2449 if (cmd_buffer) {
2450 if (cmd_buffer->pool) {
2451 list_del(&cmd_buffer->pool_link);
2452 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2453 } else
2454 radv_cmd_buffer_destroy(cmd_buffer);
2455
2456 }
2457 }
2458 }
2459
2460 VkResult radv_ResetCommandBuffer(
2461 VkCommandBuffer commandBuffer,
2462 VkCommandBufferResetFlags flags)
2463 {
2464 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2465 return radv_reset_cmd_buffer(cmd_buffer);
2466 }
2467
2468 VkResult radv_BeginCommandBuffer(
2469 VkCommandBuffer commandBuffer,
2470 const VkCommandBufferBeginInfo *pBeginInfo)
2471 {
2472 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2473 VkResult result = VK_SUCCESS;
2474
2475 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2476 /* If the command buffer has already been resetted with
2477 * vkResetCommandBuffer, no need to do it again.
2478 */
2479 result = radv_reset_cmd_buffer(cmd_buffer);
2480 if (result != VK_SUCCESS)
2481 return result;
2482 }
2483
2484 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2485 cmd_buffer->state.last_primitive_reset_en = -1;
2486 cmd_buffer->state.last_index_type = -1;
2487 cmd_buffer->state.last_num_instances = -1;
2488 cmd_buffer->state.last_vertex_offset = -1;
2489 cmd_buffer->state.last_first_instance = -1;
2490 cmd_buffer->state.predication_type = -1;
2491 cmd_buffer->usage_flags = pBeginInfo->flags;
2492
2493 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2494 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2495 assert(pBeginInfo->pInheritanceInfo);
2496 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2497 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2498
2499 struct radv_subpass *subpass =
2500 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2501
2502 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2503 if (result != VK_SUCCESS)
2504 return result;
2505
2506 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2507 }
2508
2509 if (unlikely(cmd_buffer->device->trace_bo)) {
2510 struct radv_device *device = cmd_buffer->device;
2511
2512 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2513 device->trace_bo);
2514
2515 radv_cmd_buffer_trace_emit(cmd_buffer);
2516 }
2517
2518 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2519
2520 return result;
2521 }
2522
2523 void radv_CmdBindVertexBuffers(
2524 VkCommandBuffer commandBuffer,
2525 uint32_t firstBinding,
2526 uint32_t bindingCount,
2527 const VkBuffer* pBuffers,
2528 const VkDeviceSize* pOffsets)
2529 {
2530 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2531 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2532 bool changed = false;
2533
2534 /* We have to defer setting up vertex buffer since we need the buffer
2535 * stride from the pipeline. */
2536
2537 assert(firstBinding + bindingCount <= MAX_VBS);
2538 for (uint32_t i = 0; i < bindingCount; i++) {
2539 uint32_t idx = firstBinding + i;
2540
2541 if (!changed &&
2542 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2543 vb[idx].offset != pOffsets[i])) {
2544 changed = true;
2545 }
2546
2547 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2548 vb[idx].offset = pOffsets[i];
2549
2550 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2551 vb[idx].buffer->bo);
2552 }
2553
2554 if (!changed) {
2555 /* No state changes. */
2556 return;
2557 }
2558
2559 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2560 }
2561
2562 void radv_CmdBindIndexBuffer(
2563 VkCommandBuffer commandBuffer,
2564 VkBuffer buffer,
2565 VkDeviceSize offset,
2566 VkIndexType indexType)
2567 {
2568 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2569 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2570
2571 if (cmd_buffer->state.index_buffer == index_buffer &&
2572 cmd_buffer->state.index_offset == offset &&
2573 cmd_buffer->state.index_type == indexType) {
2574 /* No state changes. */
2575 return;
2576 }
2577
2578 cmd_buffer->state.index_buffer = index_buffer;
2579 cmd_buffer->state.index_offset = offset;
2580 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2581 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2582 cmd_buffer->state.index_va += index_buffer->offset + offset;
2583
2584 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2585 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2586 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2587 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2588 }
2589
2590
2591 static void
2592 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2593 VkPipelineBindPoint bind_point,
2594 struct radv_descriptor_set *set, unsigned idx)
2595 {
2596 struct radeon_winsys *ws = cmd_buffer->device->ws;
2597
2598 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2599
2600 assert(set);
2601 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2602
2603 if (!cmd_buffer->device->use_global_bo_list) {
2604 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2605 if (set->descriptors[j])
2606 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2607 }
2608
2609 if(set->bo)
2610 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2611 }
2612
2613 void radv_CmdBindDescriptorSets(
2614 VkCommandBuffer commandBuffer,
2615 VkPipelineBindPoint pipelineBindPoint,
2616 VkPipelineLayout _layout,
2617 uint32_t firstSet,
2618 uint32_t descriptorSetCount,
2619 const VkDescriptorSet* pDescriptorSets,
2620 uint32_t dynamicOffsetCount,
2621 const uint32_t* pDynamicOffsets)
2622 {
2623 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2624 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2625 unsigned dyn_idx = 0;
2626
2627 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2628 struct radv_descriptor_state *descriptors_state =
2629 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2630
2631 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2632 unsigned idx = i + firstSet;
2633 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2634 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2635
2636 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2637 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2638 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2639 assert(dyn_idx < dynamicOffsetCount);
2640
2641 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2642 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2643 dst[0] = va;
2644 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2645 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2646 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2647 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2648 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2649 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2650 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2651 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2652 cmd_buffer->push_constant_stages |=
2653 set->layout->dynamic_shader_stages;
2654 }
2655 }
2656 }
2657
2658 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2659 struct radv_descriptor_set *set,
2660 struct radv_descriptor_set_layout *layout,
2661 VkPipelineBindPoint bind_point)
2662 {
2663 struct radv_descriptor_state *descriptors_state =
2664 radv_get_descriptors_state(cmd_buffer, bind_point);
2665 set->size = layout->size;
2666 set->layout = layout;
2667
2668 if (descriptors_state->push_set.capacity < set->size) {
2669 size_t new_size = MAX2(set->size, 1024);
2670 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2671 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2672
2673 free(set->mapped_ptr);
2674 set->mapped_ptr = malloc(new_size);
2675
2676 if (!set->mapped_ptr) {
2677 descriptors_state->push_set.capacity = 0;
2678 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2679 return false;
2680 }
2681
2682 descriptors_state->push_set.capacity = new_size;
2683 }
2684
2685 return true;
2686 }
2687
2688 void radv_meta_push_descriptor_set(
2689 struct radv_cmd_buffer* cmd_buffer,
2690 VkPipelineBindPoint pipelineBindPoint,
2691 VkPipelineLayout _layout,
2692 uint32_t set,
2693 uint32_t descriptorWriteCount,
2694 const VkWriteDescriptorSet* pDescriptorWrites)
2695 {
2696 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2697 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2698 unsigned bo_offset;
2699
2700 assert(set == 0);
2701 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2702
2703 push_set->size = layout->set[set].layout->size;
2704 push_set->layout = layout->set[set].layout;
2705
2706 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2707 &bo_offset,
2708 (void**) &push_set->mapped_ptr))
2709 return;
2710
2711 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2712 push_set->va += bo_offset;
2713
2714 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2715 radv_descriptor_set_to_handle(push_set),
2716 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2717
2718 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2719 }
2720
2721 void radv_CmdPushDescriptorSetKHR(
2722 VkCommandBuffer commandBuffer,
2723 VkPipelineBindPoint pipelineBindPoint,
2724 VkPipelineLayout _layout,
2725 uint32_t set,
2726 uint32_t descriptorWriteCount,
2727 const VkWriteDescriptorSet* pDescriptorWrites)
2728 {
2729 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2730 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2731 struct radv_descriptor_state *descriptors_state =
2732 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2733 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2734
2735 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2736
2737 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2738 layout->set[set].layout,
2739 pipelineBindPoint))
2740 return;
2741
2742 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2743 radv_descriptor_set_to_handle(push_set),
2744 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2745
2746 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2747 descriptors_state->push_dirty = true;
2748 }
2749
2750 void radv_CmdPushDescriptorSetWithTemplateKHR(
2751 VkCommandBuffer commandBuffer,
2752 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2753 VkPipelineLayout _layout,
2754 uint32_t set,
2755 const void* pData)
2756 {
2757 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2758 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2759 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2760 struct radv_descriptor_state *descriptors_state =
2761 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2762 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2763
2764 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2765
2766 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2767 layout->set[set].layout,
2768 templ->bind_point))
2769 return;
2770
2771 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2772 descriptorUpdateTemplate, pData);
2773
2774 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2775 descriptors_state->push_dirty = true;
2776 }
2777
2778 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2779 VkPipelineLayout layout,
2780 VkShaderStageFlags stageFlags,
2781 uint32_t offset,
2782 uint32_t size,
2783 const void* pValues)
2784 {
2785 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2786 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2787 cmd_buffer->push_constant_stages |= stageFlags;
2788 }
2789
2790 VkResult radv_EndCommandBuffer(
2791 VkCommandBuffer commandBuffer)
2792 {
2793 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2794
2795 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2796 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2797 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2798 si_emit_cache_flush(cmd_buffer);
2799 }
2800
2801 /* Make sure CP DMA is idle at the end of IBs because the kernel
2802 * doesn't wait for it.
2803 */
2804 si_cp_dma_wait_for_idle(cmd_buffer);
2805
2806 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2807
2808 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2809 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2810
2811 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2812
2813 return cmd_buffer->record_result;
2814 }
2815
2816 static void
2817 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2818 {
2819 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2820
2821 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2822 return;
2823
2824 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2825
2826 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2827 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2828
2829 cmd_buffer->compute_scratch_size_needed =
2830 MAX2(cmd_buffer->compute_scratch_size_needed,
2831 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2832
2833 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2834 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2835
2836 if (unlikely(cmd_buffer->device->trace_bo))
2837 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2838 }
2839
2840 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2841 VkPipelineBindPoint bind_point)
2842 {
2843 struct radv_descriptor_state *descriptors_state =
2844 radv_get_descriptors_state(cmd_buffer, bind_point);
2845
2846 descriptors_state->dirty |= descriptors_state->valid;
2847 }
2848
2849 void radv_CmdBindPipeline(
2850 VkCommandBuffer commandBuffer,
2851 VkPipelineBindPoint pipelineBindPoint,
2852 VkPipeline _pipeline)
2853 {
2854 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2855 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2856
2857 switch (pipelineBindPoint) {
2858 case VK_PIPELINE_BIND_POINT_COMPUTE:
2859 if (cmd_buffer->state.compute_pipeline == pipeline)
2860 return;
2861 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2862
2863 cmd_buffer->state.compute_pipeline = pipeline;
2864 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2865 break;
2866 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2867 if (cmd_buffer->state.pipeline == pipeline)
2868 return;
2869 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2870
2871 cmd_buffer->state.pipeline = pipeline;
2872 if (!pipeline)
2873 break;
2874
2875 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2876 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2877
2878 /* the new vertex shader might not have the same user regs */
2879 cmd_buffer->state.last_first_instance = -1;
2880 cmd_buffer->state.last_vertex_offset = -1;
2881
2882 /* Prefetch all pipeline shaders at first draw time. */
2883 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2884
2885 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2886 radv_bind_streamout_state(cmd_buffer, pipeline);
2887
2888 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2889 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2890 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2891 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2892
2893 if (radv_pipeline_has_tess(pipeline))
2894 cmd_buffer->tess_rings_needed = true;
2895 break;
2896 default:
2897 assert(!"invalid bind point");
2898 break;
2899 }
2900 }
2901
2902 void radv_CmdSetViewport(
2903 VkCommandBuffer commandBuffer,
2904 uint32_t firstViewport,
2905 uint32_t viewportCount,
2906 const VkViewport* pViewports)
2907 {
2908 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2909 struct radv_cmd_state *state = &cmd_buffer->state;
2910 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2911
2912 assert(firstViewport < MAX_VIEWPORTS);
2913 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2914
2915 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2916 viewportCount * sizeof(*pViewports));
2917
2918 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2919 }
2920
2921 void radv_CmdSetScissor(
2922 VkCommandBuffer commandBuffer,
2923 uint32_t firstScissor,
2924 uint32_t scissorCount,
2925 const VkRect2D* pScissors)
2926 {
2927 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2928 struct radv_cmd_state *state = &cmd_buffer->state;
2929 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2930
2931 assert(firstScissor < MAX_SCISSORS);
2932 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2933
2934 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2935 scissorCount * sizeof(*pScissors));
2936
2937 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2938 }
2939
2940 void radv_CmdSetLineWidth(
2941 VkCommandBuffer commandBuffer,
2942 float lineWidth)
2943 {
2944 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2945 cmd_buffer->state.dynamic.line_width = lineWidth;
2946 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2947 }
2948
2949 void radv_CmdSetDepthBias(
2950 VkCommandBuffer commandBuffer,
2951 float depthBiasConstantFactor,
2952 float depthBiasClamp,
2953 float depthBiasSlopeFactor)
2954 {
2955 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2956
2957 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2958 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2959 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2960
2961 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2962 }
2963
2964 void radv_CmdSetBlendConstants(
2965 VkCommandBuffer commandBuffer,
2966 const float blendConstants[4])
2967 {
2968 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2969
2970 memcpy(cmd_buffer->state.dynamic.blend_constants,
2971 blendConstants, sizeof(float) * 4);
2972
2973 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2974 }
2975
2976 void radv_CmdSetDepthBounds(
2977 VkCommandBuffer commandBuffer,
2978 float minDepthBounds,
2979 float maxDepthBounds)
2980 {
2981 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2982
2983 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2984 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2985
2986 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2987 }
2988
2989 void radv_CmdSetStencilCompareMask(
2990 VkCommandBuffer commandBuffer,
2991 VkStencilFaceFlags faceMask,
2992 uint32_t compareMask)
2993 {
2994 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2995
2996 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2997 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2998 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2999 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
3000
3001 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3002 }
3003
3004 void radv_CmdSetStencilWriteMask(
3005 VkCommandBuffer commandBuffer,
3006 VkStencilFaceFlags faceMask,
3007 uint32_t writeMask)
3008 {
3009 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3010
3011 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3012 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
3013 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3014 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
3015
3016 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3017 }
3018
3019 void radv_CmdSetStencilReference(
3020 VkCommandBuffer commandBuffer,
3021 VkStencilFaceFlags faceMask,
3022 uint32_t reference)
3023 {
3024 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3025
3026 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3027 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3028 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3029 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3030
3031 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3032 }
3033
3034 void radv_CmdSetDiscardRectangleEXT(
3035 VkCommandBuffer commandBuffer,
3036 uint32_t firstDiscardRectangle,
3037 uint32_t discardRectangleCount,
3038 const VkRect2D* pDiscardRectangles)
3039 {
3040 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3041 struct radv_cmd_state *state = &cmd_buffer->state;
3042 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3043
3044 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3045 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3046
3047 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3048 pDiscardRectangles, discardRectangleCount);
3049
3050 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3051 }
3052
3053 void radv_CmdExecuteCommands(
3054 VkCommandBuffer commandBuffer,
3055 uint32_t commandBufferCount,
3056 const VkCommandBuffer* pCmdBuffers)
3057 {
3058 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3059
3060 assert(commandBufferCount > 0);
3061
3062 /* Emit pending flushes on primary prior to executing secondary */
3063 si_emit_cache_flush(primary);
3064
3065 for (uint32_t i = 0; i < commandBufferCount; i++) {
3066 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3067
3068 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3069 secondary->scratch_size_needed);
3070 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3071 secondary->compute_scratch_size_needed);
3072
3073 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3074 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3075 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3076 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3077 if (secondary->tess_rings_needed)
3078 primary->tess_rings_needed = true;
3079 if (secondary->sample_positions_needed)
3080 primary->sample_positions_needed = true;
3081
3082 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3083
3084
3085 /* When the secondary command buffer is compute only we don't
3086 * need to re-emit the current graphics pipeline.
3087 */
3088 if (secondary->state.emitted_pipeline) {
3089 primary->state.emitted_pipeline =
3090 secondary->state.emitted_pipeline;
3091 }
3092
3093 /* When the secondary command buffer is graphics only we don't
3094 * need to re-emit the current compute pipeline.
3095 */
3096 if (secondary->state.emitted_compute_pipeline) {
3097 primary->state.emitted_compute_pipeline =
3098 secondary->state.emitted_compute_pipeline;
3099 }
3100
3101 /* Only re-emit the draw packets when needed. */
3102 if (secondary->state.last_primitive_reset_en != -1) {
3103 primary->state.last_primitive_reset_en =
3104 secondary->state.last_primitive_reset_en;
3105 }
3106
3107 if (secondary->state.last_primitive_reset_index) {
3108 primary->state.last_primitive_reset_index =
3109 secondary->state.last_primitive_reset_index;
3110 }
3111
3112 if (secondary->state.last_ia_multi_vgt_param) {
3113 primary->state.last_ia_multi_vgt_param =
3114 secondary->state.last_ia_multi_vgt_param;
3115 }
3116
3117 primary->state.last_first_instance = secondary->state.last_first_instance;
3118 primary->state.last_num_instances = secondary->state.last_num_instances;
3119 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3120
3121 if (secondary->state.last_index_type != -1) {
3122 primary->state.last_index_type =
3123 secondary->state.last_index_type;
3124 }
3125 }
3126
3127 /* After executing commands from secondary buffers we have to dirty
3128 * some states.
3129 */
3130 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3131 RADV_CMD_DIRTY_INDEX_BUFFER |
3132 RADV_CMD_DIRTY_DYNAMIC_ALL;
3133 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3134 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3135 }
3136
3137 VkResult radv_CreateCommandPool(
3138 VkDevice _device,
3139 const VkCommandPoolCreateInfo* pCreateInfo,
3140 const VkAllocationCallbacks* pAllocator,
3141 VkCommandPool* pCmdPool)
3142 {
3143 RADV_FROM_HANDLE(radv_device, device, _device);
3144 struct radv_cmd_pool *pool;
3145
3146 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3147 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3148 if (pool == NULL)
3149 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3150
3151 if (pAllocator)
3152 pool->alloc = *pAllocator;
3153 else
3154 pool->alloc = device->alloc;
3155
3156 list_inithead(&pool->cmd_buffers);
3157 list_inithead(&pool->free_cmd_buffers);
3158
3159 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3160
3161 *pCmdPool = radv_cmd_pool_to_handle(pool);
3162
3163 return VK_SUCCESS;
3164
3165 }
3166
3167 void radv_DestroyCommandPool(
3168 VkDevice _device,
3169 VkCommandPool commandPool,
3170 const VkAllocationCallbacks* pAllocator)
3171 {
3172 RADV_FROM_HANDLE(radv_device, device, _device);
3173 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3174
3175 if (!pool)
3176 return;
3177
3178 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3179 &pool->cmd_buffers, pool_link) {
3180 radv_cmd_buffer_destroy(cmd_buffer);
3181 }
3182
3183 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3184 &pool->free_cmd_buffers, pool_link) {
3185 radv_cmd_buffer_destroy(cmd_buffer);
3186 }
3187
3188 vk_free2(&device->alloc, pAllocator, pool);
3189 }
3190
3191 VkResult radv_ResetCommandPool(
3192 VkDevice device,
3193 VkCommandPool commandPool,
3194 VkCommandPoolResetFlags flags)
3195 {
3196 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3197 VkResult result;
3198
3199 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3200 &pool->cmd_buffers, pool_link) {
3201 result = radv_reset_cmd_buffer(cmd_buffer);
3202 if (result != VK_SUCCESS)
3203 return result;
3204 }
3205
3206 return VK_SUCCESS;
3207 }
3208
3209 void radv_TrimCommandPool(
3210 VkDevice device,
3211 VkCommandPool commandPool,
3212 VkCommandPoolTrimFlagsKHR flags)
3213 {
3214 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3215
3216 if (!pool)
3217 return;
3218
3219 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3220 &pool->free_cmd_buffers, pool_link) {
3221 radv_cmd_buffer_destroy(cmd_buffer);
3222 }
3223 }
3224
3225 void radv_CmdBeginRenderPass(
3226 VkCommandBuffer commandBuffer,
3227 const VkRenderPassBeginInfo* pRenderPassBegin,
3228 VkSubpassContents contents)
3229 {
3230 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3231 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3232 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3233
3234 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3235 cmd_buffer->cs, 2048);
3236 MAYBE_UNUSED VkResult result;
3237
3238 cmd_buffer->state.framebuffer = framebuffer;
3239 cmd_buffer->state.pass = pass;
3240 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3241
3242 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3243 if (result != VK_SUCCESS)
3244 return;
3245
3246 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3247 assert(cmd_buffer->cs->cdw <= cdw_max);
3248
3249 radv_cmd_buffer_clear_subpass(cmd_buffer);
3250 }
3251
3252 void radv_CmdBeginRenderPass2KHR(
3253 VkCommandBuffer commandBuffer,
3254 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3255 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3256 {
3257 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3258 pSubpassBeginInfo->contents);
3259 }
3260
3261 void radv_CmdNextSubpass(
3262 VkCommandBuffer commandBuffer,
3263 VkSubpassContents contents)
3264 {
3265 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3266
3267 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3268
3269 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3270 2048);
3271
3272 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3273 radv_cmd_buffer_clear_subpass(cmd_buffer);
3274 }
3275
3276 void radv_CmdNextSubpass2KHR(
3277 VkCommandBuffer commandBuffer,
3278 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3279 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3280 {
3281 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3282 }
3283
3284 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3285 {
3286 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3287 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3288 if (!radv_get_shader(pipeline, stage))
3289 continue;
3290
3291 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3292 if (loc->sgpr_idx == -1)
3293 continue;
3294 uint32_t base_reg = pipeline->user_data_0[stage];
3295 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3296
3297 }
3298 if (pipeline->gs_copy_shader) {
3299 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3300 if (loc->sgpr_idx != -1) {
3301 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3302 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3303 }
3304 }
3305 }
3306
3307 static void
3308 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3309 uint32_t vertex_count,
3310 bool use_opaque)
3311 {
3312 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3313 radeon_emit(cmd_buffer->cs, vertex_count);
3314 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3315 S_0287F0_USE_OPAQUE(use_opaque));
3316 }
3317
3318 static void
3319 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3320 uint64_t index_va,
3321 uint32_t index_count)
3322 {
3323 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3324 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3325 radeon_emit(cmd_buffer->cs, index_va);
3326 radeon_emit(cmd_buffer->cs, index_va >> 32);
3327 radeon_emit(cmd_buffer->cs, index_count);
3328 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3329 }
3330
3331 static void
3332 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3333 bool indexed,
3334 uint32_t draw_count,
3335 uint64_t count_va,
3336 uint32_t stride)
3337 {
3338 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3339 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3340 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3341 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3342 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3343 bool predicating = cmd_buffer->state.predicating;
3344 assert(base_reg);
3345
3346 /* just reset draw state for vertex data */
3347 cmd_buffer->state.last_first_instance = -1;
3348 cmd_buffer->state.last_num_instances = -1;
3349 cmd_buffer->state.last_vertex_offset = -1;
3350
3351 if (draw_count == 1 && !count_va && !draw_id_enable) {
3352 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3353 PKT3_DRAW_INDIRECT, 3, predicating));
3354 radeon_emit(cs, 0);
3355 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3356 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3357 radeon_emit(cs, di_src_sel);
3358 } else {
3359 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3360 PKT3_DRAW_INDIRECT_MULTI,
3361 8, predicating));
3362 radeon_emit(cs, 0);
3363 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3364 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3365 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3366 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3367 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3368 radeon_emit(cs, draw_count); /* count */
3369 radeon_emit(cs, count_va); /* count_addr */
3370 radeon_emit(cs, count_va >> 32);
3371 radeon_emit(cs, stride); /* stride */
3372 radeon_emit(cs, di_src_sel);
3373 }
3374 }
3375
3376 struct radv_draw_info {
3377 /**
3378 * Number of vertices.
3379 */
3380 uint32_t count;
3381
3382 /**
3383 * Index of the first vertex.
3384 */
3385 int32_t vertex_offset;
3386
3387 /**
3388 * First instance id.
3389 */
3390 uint32_t first_instance;
3391
3392 /**
3393 * Number of instances.
3394 */
3395 uint32_t instance_count;
3396
3397 /**
3398 * First index (indexed draws only).
3399 */
3400 uint32_t first_index;
3401
3402 /**
3403 * Whether it's an indexed draw.
3404 */
3405 bool indexed;
3406
3407 /**
3408 * Indirect draw parameters resource.
3409 */
3410 struct radv_buffer *indirect;
3411 uint64_t indirect_offset;
3412 uint32_t stride;
3413
3414 /**
3415 * Draw count parameters resource.
3416 */
3417 struct radv_buffer *count_buffer;
3418 uint64_t count_buffer_offset;
3419
3420 /**
3421 * Stream output parameters resource.
3422 */
3423 struct radv_buffer *strmout_buffer;
3424 uint64_t strmout_buffer_offset;
3425 };
3426
3427 static void
3428 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3429 const struct radv_draw_info *info)
3430 {
3431 struct radv_cmd_state *state = &cmd_buffer->state;
3432 struct radeon_winsys *ws = cmd_buffer->device->ws;
3433 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3434
3435 if (info->strmout_buffer) {
3436 uint64_t va = radv_buffer_get_va(info->strmout_buffer->bo);
3437
3438 va += info->strmout_buffer->offset +
3439 info->strmout_buffer_offset;
3440
3441 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
3442 info->stride);
3443
3444 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3445 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3446 COPY_DATA_DST_SEL(COPY_DATA_REG) |
3447 COPY_DATA_WR_CONFIRM);
3448 radeon_emit(cs, va);
3449 radeon_emit(cs, va >> 32);
3450 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
3451 radeon_emit(cs, 0); /* unused */
3452
3453 radv_cs_add_buffer(ws, cs, info->strmout_buffer->bo);
3454 }
3455
3456 if (info->indirect) {
3457 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3458 uint64_t count_va = 0;
3459
3460 va += info->indirect->offset + info->indirect_offset;
3461
3462 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3463
3464 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3465 radeon_emit(cs, 1);
3466 radeon_emit(cs, va);
3467 radeon_emit(cs, va >> 32);
3468
3469 if (info->count_buffer) {
3470 count_va = radv_buffer_get_va(info->count_buffer->bo);
3471 count_va += info->count_buffer->offset +
3472 info->count_buffer_offset;
3473
3474 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3475 }
3476
3477 if (!state->subpass->view_mask) {
3478 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3479 info->indexed,
3480 info->count,
3481 count_va,
3482 info->stride);
3483 } else {
3484 unsigned i;
3485 for_each_bit(i, state->subpass->view_mask) {
3486 radv_emit_view_index(cmd_buffer, i);
3487
3488 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3489 info->indexed,
3490 info->count,
3491 count_va,
3492 info->stride);
3493 }
3494 }
3495 } else {
3496 assert(state->pipeline->graphics.vtx_base_sgpr);
3497
3498 if (info->vertex_offset != state->last_vertex_offset ||
3499 info->first_instance != state->last_first_instance) {
3500 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3501 state->pipeline->graphics.vtx_emit_num);
3502
3503 radeon_emit(cs, info->vertex_offset);
3504 radeon_emit(cs, info->first_instance);
3505 if (state->pipeline->graphics.vtx_emit_num == 3)
3506 radeon_emit(cs, 0);
3507 state->last_first_instance = info->first_instance;
3508 state->last_vertex_offset = info->vertex_offset;
3509 }
3510
3511 if (state->last_num_instances != info->instance_count) {
3512 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3513 radeon_emit(cs, info->instance_count);
3514 state->last_num_instances = info->instance_count;
3515 }
3516
3517 if (info->indexed) {
3518 int index_size = state->index_type ? 4 : 2;
3519 uint64_t index_va;
3520
3521 index_va = state->index_va;
3522 index_va += info->first_index * index_size;
3523
3524 if (!state->subpass->view_mask) {
3525 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3526 index_va,
3527 info->count);
3528 } else {
3529 unsigned i;
3530 for_each_bit(i, state->subpass->view_mask) {
3531 radv_emit_view_index(cmd_buffer, i);
3532
3533 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3534 index_va,
3535 info->count);
3536 }
3537 }
3538 } else {
3539 if (!state->subpass->view_mask) {
3540 radv_cs_emit_draw_packet(cmd_buffer,
3541 info->count,
3542 !!info->strmout_buffer);
3543 } else {
3544 unsigned i;
3545 for_each_bit(i, state->subpass->view_mask) {
3546 radv_emit_view_index(cmd_buffer, i);
3547
3548 radv_cs_emit_draw_packet(cmd_buffer,
3549 info->count,
3550 !!info->strmout_buffer);
3551 }
3552 }
3553 }
3554 }
3555 }
3556
3557 /*
3558 * Vega and raven have a bug which triggers if there are multiple context
3559 * register contexts active at the same time with different scissor values.
3560 *
3561 * There are two possible workarounds:
3562 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3563 * there is only ever 1 active set of scissor values at the same time.
3564 *
3565 * 2) Whenever the hardware switches contexts we have to set the scissor
3566 * registers again even if it is a noop. That way the new context gets
3567 * the correct scissor values.
3568 *
3569 * This implements option 2. radv_need_late_scissor_emission needs to
3570 * return true on affected HW if radv_emit_all_graphics_states sets
3571 * any context registers.
3572 */
3573 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3574 bool indexed_draw)
3575 {
3576 struct radv_cmd_state *state = &cmd_buffer->state;
3577
3578 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3579 return false;
3580
3581 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3582
3583 /* Index, vertex and streamout buffers don't change context regs, and
3584 * pipeline is handled later.
3585 */
3586 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3587 RADV_CMD_DIRTY_VERTEX_BUFFER |
3588 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3589 RADV_CMD_DIRTY_PIPELINE);
3590
3591 /* Assume all state changes except these two can imply context rolls. */
3592 if (cmd_buffer->state.dirty & used_states)
3593 return true;
3594
3595 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3596 return true;
3597
3598 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3599 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3600 return true;
3601
3602 return false;
3603 }
3604
3605 static void
3606 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3607 const struct radv_draw_info *info)
3608 {
3609 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3610
3611 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3612 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3613 radv_emit_rbplus_state(cmd_buffer);
3614
3615 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3616 radv_emit_graphics_pipeline(cmd_buffer);
3617
3618 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3619 radv_emit_framebuffer_state(cmd_buffer);
3620
3621 if (info->indexed) {
3622 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3623 radv_emit_index_buffer(cmd_buffer);
3624 } else {
3625 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3626 * so the state must be re-emitted before the next indexed
3627 * draw.
3628 */
3629 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3630 cmd_buffer->state.last_index_type = -1;
3631 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3632 }
3633 }
3634
3635 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3636
3637 radv_emit_draw_registers(cmd_buffer, info->indexed,
3638 info->instance_count > 1, info->indirect,
3639 info->indirect ? 0 : info->count);
3640
3641 if (late_scissor_emission)
3642 radv_emit_scissor(cmd_buffer);
3643 }
3644
3645 static void
3646 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3647 const struct radv_draw_info *info)
3648 {
3649 struct radeon_info *rad_info =
3650 &cmd_buffer->device->physical_device->rad_info;
3651 bool has_prefetch =
3652 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3653 bool pipeline_is_dirty =
3654 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3655 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3656
3657 MAYBE_UNUSED unsigned cdw_max =
3658 radeon_check_space(cmd_buffer->device->ws,
3659 cmd_buffer->cs, 4096);
3660
3661 /* Use optimal packet order based on whether we need to sync the
3662 * pipeline.
3663 */
3664 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3665 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3666 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3667 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3668 /* If we have to wait for idle, set all states first, so that
3669 * all SET packets are processed in parallel with previous draw
3670 * calls. Then upload descriptors, set shader pointers, and
3671 * draw, and prefetch at the end. This ensures that the time
3672 * the CUs are idle is very short. (there are only SET_SH
3673 * packets between the wait and the draw)
3674 */
3675 radv_emit_all_graphics_states(cmd_buffer, info);
3676 si_emit_cache_flush(cmd_buffer);
3677 /* <-- CUs are idle here --> */
3678
3679 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3680
3681 radv_emit_draw_packets(cmd_buffer, info);
3682 /* <-- CUs are busy here --> */
3683
3684 /* Start prefetches after the draw has been started. Both will
3685 * run in parallel, but starting the draw first is more
3686 * important.
3687 */
3688 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3689 radv_emit_prefetch_L2(cmd_buffer,
3690 cmd_buffer->state.pipeline, false);
3691 }
3692 } else {
3693 /* If we don't wait for idle, start prefetches first, then set
3694 * states, and draw at the end.
3695 */
3696 si_emit_cache_flush(cmd_buffer);
3697
3698 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3699 /* Only prefetch the vertex shader and VBO descriptors
3700 * in order to start the draw as soon as possible.
3701 */
3702 radv_emit_prefetch_L2(cmd_buffer,
3703 cmd_buffer->state.pipeline, true);
3704 }
3705
3706 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3707
3708 radv_emit_all_graphics_states(cmd_buffer, info);
3709 radv_emit_draw_packets(cmd_buffer, info);
3710
3711 /* Prefetch the remaining shaders after the draw has been
3712 * started.
3713 */
3714 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3715 radv_emit_prefetch_L2(cmd_buffer,
3716 cmd_buffer->state.pipeline, false);
3717 }
3718 }
3719
3720 /* Workaround for a VGT hang when streamout is enabled.
3721 * It must be done after drawing.
3722 */
3723 if (cmd_buffer->state.streamout.streamout_enabled &&
3724 (rad_info->family == CHIP_HAWAII ||
3725 rad_info->family == CHIP_TONGA ||
3726 rad_info->family == CHIP_FIJI)) {
3727 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3728 }
3729
3730 assert(cmd_buffer->cs->cdw <= cdw_max);
3731 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3732 }
3733
3734 void radv_CmdDraw(
3735 VkCommandBuffer commandBuffer,
3736 uint32_t vertexCount,
3737 uint32_t instanceCount,
3738 uint32_t firstVertex,
3739 uint32_t firstInstance)
3740 {
3741 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3742 struct radv_draw_info info = {};
3743
3744 info.count = vertexCount;
3745 info.instance_count = instanceCount;
3746 info.first_instance = firstInstance;
3747 info.vertex_offset = firstVertex;
3748
3749 radv_draw(cmd_buffer, &info);
3750 }
3751
3752 void radv_CmdDrawIndexed(
3753 VkCommandBuffer commandBuffer,
3754 uint32_t indexCount,
3755 uint32_t instanceCount,
3756 uint32_t firstIndex,
3757 int32_t vertexOffset,
3758 uint32_t firstInstance)
3759 {
3760 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3761 struct radv_draw_info info = {};
3762
3763 info.indexed = true;
3764 info.count = indexCount;
3765 info.instance_count = instanceCount;
3766 info.first_index = firstIndex;
3767 info.vertex_offset = vertexOffset;
3768 info.first_instance = firstInstance;
3769
3770 radv_draw(cmd_buffer, &info);
3771 }
3772
3773 void radv_CmdDrawIndirect(
3774 VkCommandBuffer commandBuffer,
3775 VkBuffer _buffer,
3776 VkDeviceSize offset,
3777 uint32_t drawCount,
3778 uint32_t stride)
3779 {
3780 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3781 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3782 struct radv_draw_info info = {};
3783
3784 info.count = drawCount;
3785 info.indirect = buffer;
3786 info.indirect_offset = offset;
3787 info.stride = stride;
3788
3789 radv_draw(cmd_buffer, &info);
3790 }
3791
3792 void radv_CmdDrawIndexedIndirect(
3793 VkCommandBuffer commandBuffer,
3794 VkBuffer _buffer,
3795 VkDeviceSize offset,
3796 uint32_t drawCount,
3797 uint32_t stride)
3798 {
3799 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3800 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3801 struct radv_draw_info info = {};
3802
3803 info.indexed = true;
3804 info.count = drawCount;
3805 info.indirect = buffer;
3806 info.indirect_offset = offset;
3807 info.stride = stride;
3808
3809 radv_draw(cmd_buffer, &info);
3810 }
3811
3812 void radv_CmdDrawIndirectCountAMD(
3813 VkCommandBuffer commandBuffer,
3814 VkBuffer _buffer,
3815 VkDeviceSize offset,
3816 VkBuffer _countBuffer,
3817 VkDeviceSize countBufferOffset,
3818 uint32_t maxDrawCount,
3819 uint32_t stride)
3820 {
3821 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3822 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3823 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3824 struct radv_draw_info info = {};
3825
3826 info.count = maxDrawCount;
3827 info.indirect = buffer;
3828 info.indirect_offset = offset;
3829 info.count_buffer = count_buffer;
3830 info.count_buffer_offset = countBufferOffset;
3831 info.stride = stride;
3832
3833 radv_draw(cmd_buffer, &info);
3834 }
3835
3836 void radv_CmdDrawIndexedIndirectCountAMD(
3837 VkCommandBuffer commandBuffer,
3838 VkBuffer _buffer,
3839 VkDeviceSize offset,
3840 VkBuffer _countBuffer,
3841 VkDeviceSize countBufferOffset,
3842 uint32_t maxDrawCount,
3843 uint32_t stride)
3844 {
3845 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3846 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3847 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3848 struct radv_draw_info info = {};
3849
3850 info.indexed = true;
3851 info.count = maxDrawCount;
3852 info.indirect = buffer;
3853 info.indirect_offset = offset;
3854 info.count_buffer = count_buffer;
3855 info.count_buffer_offset = countBufferOffset;
3856 info.stride = stride;
3857
3858 radv_draw(cmd_buffer, &info);
3859 }
3860
3861 void radv_CmdDrawIndirectCountKHR(
3862 VkCommandBuffer commandBuffer,
3863 VkBuffer _buffer,
3864 VkDeviceSize offset,
3865 VkBuffer _countBuffer,
3866 VkDeviceSize countBufferOffset,
3867 uint32_t maxDrawCount,
3868 uint32_t stride)
3869 {
3870 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3871 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3872 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3873 struct radv_draw_info info = {};
3874
3875 info.count = maxDrawCount;
3876 info.indirect = buffer;
3877 info.indirect_offset = offset;
3878 info.count_buffer = count_buffer;
3879 info.count_buffer_offset = countBufferOffset;
3880 info.stride = stride;
3881
3882 radv_draw(cmd_buffer, &info);
3883 }
3884
3885 void radv_CmdDrawIndexedIndirectCountKHR(
3886 VkCommandBuffer commandBuffer,
3887 VkBuffer _buffer,
3888 VkDeviceSize offset,
3889 VkBuffer _countBuffer,
3890 VkDeviceSize countBufferOffset,
3891 uint32_t maxDrawCount,
3892 uint32_t stride)
3893 {
3894 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3895 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3896 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3897 struct radv_draw_info info = {};
3898
3899 info.indexed = true;
3900 info.count = maxDrawCount;
3901 info.indirect = buffer;
3902 info.indirect_offset = offset;
3903 info.count_buffer = count_buffer;
3904 info.count_buffer_offset = countBufferOffset;
3905 info.stride = stride;
3906
3907 radv_draw(cmd_buffer, &info);
3908 }
3909
3910 struct radv_dispatch_info {
3911 /**
3912 * Determine the layout of the grid (in block units) to be used.
3913 */
3914 uint32_t blocks[3];
3915
3916 /**
3917 * A starting offset for the grid. If unaligned is set, the offset
3918 * must still be aligned.
3919 */
3920 uint32_t offsets[3];
3921 /**
3922 * Whether it's an unaligned compute dispatch.
3923 */
3924 bool unaligned;
3925
3926 /**
3927 * Indirect compute parameters resource.
3928 */
3929 struct radv_buffer *indirect;
3930 uint64_t indirect_offset;
3931 };
3932
3933 static void
3934 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3935 const struct radv_dispatch_info *info)
3936 {
3937 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3938 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3939 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3940 struct radeon_winsys *ws = cmd_buffer->device->ws;
3941 bool predicating = cmd_buffer->state.predicating;
3942 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3943 struct radv_userdata_info *loc;
3944
3945 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3946 AC_UD_CS_GRID_SIZE);
3947
3948 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3949
3950 if (info->indirect) {
3951 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3952
3953 va += info->indirect->offset + info->indirect_offset;
3954
3955 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3956
3957 if (loc->sgpr_idx != -1) {
3958 for (unsigned i = 0; i < 3; ++i) {
3959 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3960 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3961 COPY_DATA_DST_SEL(COPY_DATA_REG));
3962 radeon_emit(cs, (va + 4 * i));
3963 radeon_emit(cs, (va + 4 * i) >> 32);
3964 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3965 + loc->sgpr_idx * 4) >> 2) + i);
3966 radeon_emit(cs, 0);
3967 }
3968 }
3969
3970 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3971 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
3972 PKT3_SHADER_TYPE_S(1));
3973 radeon_emit(cs, va);
3974 radeon_emit(cs, va >> 32);
3975 radeon_emit(cs, dispatch_initiator);
3976 } else {
3977 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3978 PKT3_SHADER_TYPE_S(1));
3979 radeon_emit(cs, 1);
3980 radeon_emit(cs, va);
3981 radeon_emit(cs, va >> 32);
3982
3983 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
3984 PKT3_SHADER_TYPE_S(1));
3985 radeon_emit(cs, 0);
3986 radeon_emit(cs, dispatch_initiator);
3987 }
3988 } else {
3989 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3990 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3991
3992 if (info->unaligned) {
3993 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3994 unsigned remainder[3];
3995
3996 /* If aligned, these should be an entire block size,
3997 * not 0.
3998 */
3999 remainder[0] = blocks[0] + cs_block_size[0] -
4000 align_u32_npot(blocks[0], cs_block_size[0]);
4001 remainder[1] = blocks[1] + cs_block_size[1] -
4002 align_u32_npot(blocks[1], cs_block_size[1]);
4003 remainder[2] = blocks[2] + cs_block_size[2] -
4004 align_u32_npot(blocks[2], cs_block_size[2]);
4005
4006 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4007 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4008 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4009
4010 for(unsigned i = 0; i < 3; ++i) {
4011 assert(offsets[i] % cs_block_size[i] == 0);
4012 offsets[i] /= cs_block_size[i];
4013 }
4014
4015 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4016 radeon_emit(cs,
4017 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4018 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4019 radeon_emit(cs,
4020 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4021 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4022 radeon_emit(cs,
4023 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4024 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4025
4026 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4027 }
4028
4029 if (loc->sgpr_idx != -1) {
4030 assert(!loc->indirect);
4031 assert(loc->num_sgprs == 3);
4032
4033 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4034 loc->sgpr_idx * 4, 3);
4035 radeon_emit(cs, blocks[0]);
4036 radeon_emit(cs, blocks[1]);
4037 radeon_emit(cs, blocks[2]);
4038 }
4039
4040 if (offsets[0] || offsets[1] || offsets[2]) {
4041 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4042 radeon_emit(cs, offsets[0]);
4043 radeon_emit(cs, offsets[1]);
4044 radeon_emit(cs, offsets[2]);
4045
4046 /* The blocks in the packet are not counts but end values. */
4047 for (unsigned i = 0; i < 3; ++i)
4048 blocks[i] += offsets[i];
4049 } else {
4050 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4051 }
4052
4053 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4054 PKT3_SHADER_TYPE_S(1));
4055 radeon_emit(cs, blocks[0]);
4056 radeon_emit(cs, blocks[1]);
4057 radeon_emit(cs, blocks[2]);
4058 radeon_emit(cs, dispatch_initiator);
4059 }
4060
4061 assert(cmd_buffer->cs->cdw <= cdw_max);
4062 }
4063
4064 static void
4065 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4066 {
4067 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4068 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4069 }
4070
4071 static void
4072 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4073 const struct radv_dispatch_info *info)
4074 {
4075 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4076 bool has_prefetch =
4077 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4078 bool pipeline_is_dirty = pipeline &&
4079 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4080
4081 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4082 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4083 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4084 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4085 /* If we have to wait for idle, set all states first, so that
4086 * all SET packets are processed in parallel with previous draw
4087 * calls. Then upload descriptors, set shader pointers, and
4088 * dispatch, and prefetch at the end. This ensures that the
4089 * time the CUs are idle is very short. (there are only SET_SH
4090 * packets between the wait and the draw)
4091 */
4092 radv_emit_compute_pipeline(cmd_buffer);
4093 si_emit_cache_flush(cmd_buffer);
4094 /* <-- CUs are idle here --> */
4095
4096 radv_upload_compute_shader_descriptors(cmd_buffer);
4097
4098 radv_emit_dispatch_packets(cmd_buffer, info);
4099 /* <-- CUs are busy here --> */
4100
4101 /* Start prefetches after the dispatch has been started. Both
4102 * will run in parallel, but starting the dispatch first is
4103 * more important.
4104 */
4105 if (has_prefetch && pipeline_is_dirty) {
4106 radv_emit_shader_prefetch(cmd_buffer,
4107 pipeline->shaders[MESA_SHADER_COMPUTE]);
4108 }
4109 } else {
4110 /* If we don't wait for idle, start prefetches first, then set
4111 * states, and dispatch at the end.
4112 */
4113 si_emit_cache_flush(cmd_buffer);
4114
4115 if (has_prefetch && pipeline_is_dirty) {
4116 radv_emit_shader_prefetch(cmd_buffer,
4117 pipeline->shaders[MESA_SHADER_COMPUTE]);
4118 }
4119
4120 radv_upload_compute_shader_descriptors(cmd_buffer);
4121
4122 radv_emit_compute_pipeline(cmd_buffer);
4123 radv_emit_dispatch_packets(cmd_buffer, info);
4124 }
4125
4126 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4127 }
4128
4129 void radv_CmdDispatchBase(
4130 VkCommandBuffer commandBuffer,
4131 uint32_t base_x,
4132 uint32_t base_y,
4133 uint32_t base_z,
4134 uint32_t x,
4135 uint32_t y,
4136 uint32_t z)
4137 {
4138 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4139 struct radv_dispatch_info info = {};
4140
4141 info.blocks[0] = x;
4142 info.blocks[1] = y;
4143 info.blocks[2] = z;
4144
4145 info.offsets[0] = base_x;
4146 info.offsets[1] = base_y;
4147 info.offsets[2] = base_z;
4148 radv_dispatch(cmd_buffer, &info);
4149 }
4150
4151 void radv_CmdDispatch(
4152 VkCommandBuffer commandBuffer,
4153 uint32_t x,
4154 uint32_t y,
4155 uint32_t z)
4156 {
4157 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4158 }
4159
4160 void radv_CmdDispatchIndirect(
4161 VkCommandBuffer commandBuffer,
4162 VkBuffer _buffer,
4163 VkDeviceSize offset)
4164 {
4165 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4166 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4167 struct radv_dispatch_info info = {};
4168
4169 info.indirect = buffer;
4170 info.indirect_offset = offset;
4171
4172 radv_dispatch(cmd_buffer, &info);
4173 }
4174
4175 void radv_unaligned_dispatch(
4176 struct radv_cmd_buffer *cmd_buffer,
4177 uint32_t x,
4178 uint32_t y,
4179 uint32_t z)
4180 {
4181 struct radv_dispatch_info info = {};
4182
4183 info.blocks[0] = x;
4184 info.blocks[1] = y;
4185 info.blocks[2] = z;
4186 info.unaligned = 1;
4187
4188 radv_dispatch(cmd_buffer, &info);
4189 }
4190
4191 void radv_CmdEndRenderPass(
4192 VkCommandBuffer commandBuffer)
4193 {
4194 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4195
4196 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4197
4198 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4199
4200 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4201 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4202 radv_handle_subpass_image_transition(cmd_buffer,
4203 (struct radv_subpass_attachment){i, layout});
4204 }
4205
4206 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4207
4208 cmd_buffer->state.pass = NULL;
4209 cmd_buffer->state.subpass = NULL;
4210 cmd_buffer->state.attachments = NULL;
4211 cmd_buffer->state.framebuffer = NULL;
4212 }
4213
4214 void radv_CmdEndRenderPass2KHR(
4215 VkCommandBuffer commandBuffer,
4216 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4217 {
4218 radv_CmdEndRenderPass(commandBuffer);
4219 }
4220
4221 /*
4222 * For HTILE we have the following interesting clear words:
4223 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4224 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4225 * 0xfffffff0: Clear depth to 1.0
4226 * 0x00000000: Clear depth to 0.0
4227 */
4228 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4229 struct radv_image *image,
4230 const VkImageSubresourceRange *range,
4231 uint32_t clear_word)
4232 {
4233 assert(range->baseMipLevel == 0);
4234 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4235 unsigned layer_count = radv_get_layerCount(image, range);
4236 uint64_t size = image->surface.htile_slice_size * layer_count;
4237 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4238 uint64_t offset = image->offset + image->htile_offset +
4239 image->surface.htile_slice_size * range->baseArrayLayer;
4240 struct radv_cmd_state *state = &cmd_buffer->state;
4241 VkClearDepthStencilValue value = {};
4242
4243 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4244 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4245
4246 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4247 size, clear_word);
4248
4249 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4250
4251 if (vk_format_is_stencil(image->vk_format))
4252 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4253
4254 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4255
4256 if (radv_image_is_tc_compat_htile(image)) {
4257 /* Initialize the TC-compat metada value to 0 because by
4258 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4259 * need have to conditionally update its value when performing
4260 * a fast depth clear.
4261 */
4262 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4263 }
4264 }
4265
4266 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4267 struct radv_image *image,
4268 VkImageLayout src_layout,
4269 VkImageLayout dst_layout,
4270 unsigned src_queue_mask,
4271 unsigned dst_queue_mask,
4272 const VkImageSubresourceRange *range)
4273 {
4274 if (!radv_image_has_htile(image))
4275 return;
4276
4277 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4278 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4279 /* TODO: merge with the clear if applicable */
4280 radv_initialize_htile(cmd_buffer, image, range, 0);
4281 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4282 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4283 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4284 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4285 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4286 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4287 VkImageSubresourceRange local_range = *range;
4288 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4289 local_range.baseMipLevel = 0;
4290 local_range.levelCount = 1;
4291
4292 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4293 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4294
4295 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4296
4297 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4298 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4299 }
4300 }
4301
4302 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4303 struct radv_image *image, uint32_t value)
4304 {
4305 struct radv_cmd_state *state = &cmd_buffer->state;
4306
4307 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4308 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4309
4310 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4311
4312 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4313 }
4314
4315 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4316 struct radv_image *image, uint32_t value)
4317 {
4318 struct radv_cmd_state *state = &cmd_buffer->state;
4319
4320 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4321 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4322
4323 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4324
4325 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4326 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4327 }
4328
4329 /**
4330 * Initialize DCC/FMASK/CMASK metadata for a color image.
4331 */
4332 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4333 struct radv_image *image,
4334 VkImageLayout src_layout,
4335 VkImageLayout dst_layout,
4336 unsigned src_queue_mask,
4337 unsigned dst_queue_mask)
4338 {
4339 if (radv_image_has_cmask(image)) {
4340 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4341
4342 /* TODO: clarify this. */
4343 if (radv_image_has_fmask(image)) {
4344 value = 0xccccccccu;
4345 }
4346
4347 radv_initialise_cmask(cmd_buffer, image, value);
4348 }
4349
4350 if (radv_image_has_dcc(image)) {
4351 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4352 bool need_decompress_pass = false;
4353
4354 if (radv_layout_dcc_compressed(image, dst_layout,
4355 dst_queue_mask)) {
4356 value = 0x20202020u;
4357 need_decompress_pass = true;
4358 }
4359
4360 radv_initialize_dcc(cmd_buffer, image, value);
4361
4362 radv_update_fce_metadata(cmd_buffer, image,
4363 need_decompress_pass);
4364 }
4365
4366 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4367 uint32_t color_values[2] = {};
4368 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4369 }
4370 }
4371
4372 /**
4373 * Handle color image transitions for DCC/FMASK/CMASK.
4374 */
4375 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4376 struct radv_image *image,
4377 VkImageLayout src_layout,
4378 VkImageLayout dst_layout,
4379 unsigned src_queue_mask,
4380 unsigned dst_queue_mask,
4381 const VkImageSubresourceRange *range)
4382 {
4383 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4384 radv_init_color_image_metadata(cmd_buffer, image,
4385 src_layout, dst_layout,
4386 src_queue_mask, dst_queue_mask);
4387 return;
4388 }
4389
4390 if (radv_image_has_dcc(image)) {
4391 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4392 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4393 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4394 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4395 radv_decompress_dcc(cmd_buffer, image, range);
4396 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4397 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4398 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4399 }
4400 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4401 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4402 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4403 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4404 }
4405 }
4406 }
4407
4408 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4409 struct radv_image *image,
4410 VkImageLayout src_layout,
4411 VkImageLayout dst_layout,
4412 uint32_t src_family,
4413 uint32_t dst_family,
4414 const VkImageSubresourceRange *range)
4415 {
4416 if (image->exclusive && src_family != dst_family) {
4417 /* This is an acquire or a release operation and there will be
4418 * a corresponding release/acquire. Do the transition in the
4419 * most flexible queue. */
4420
4421 assert(src_family == cmd_buffer->queue_family_index ||
4422 dst_family == cmd_buffer->queue_family_index);
4423
4424 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4425 return;
4426
4427 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4428 (src_family == RADV_QUEUE_GENERAL ||
4429 dst_family == RADV_QUEUE_GENERAL))
4430 return;
4431 }
4432
4433 unsigned src_queue_mask =
4434 radv_image_queue_family_mask(image, src_family,
4435 cmd_buffer->queue_family_index);
4436 unsigned dst_queue_mask =
4437 radv_image_queue_family_mask(image, dst_family,
4438 cmd_buffer->queue_family_index);
4439
4440 if (vk_format_is_depth(image->vk_format)) {
4441 radv_handle_depth_image_transition(cmd_buffer, image,
4442 src_layout, dst_layout,
4443 src_queue_mask, dst_queue_mask,
4444 range);
4445 } else {
4446 radv_handle_color_image_transition(cmd_buffer, image,
4447 src_layout, dst_layout,
4448 src_queue_mask, dst_queue_mask,
4449 range);
4450 }
4451 }
4452
4453 struct radv_barrier_info {
4454 uint32_t eventCount;
4455 const VkEvent *pEvents;
4456 VkPipelineStageFlags srcStageMask;
4457 };
4458
4459 static void
4460 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4461 uint32_t memoryBarrierCount,
4462 const VkMemoryBarrier *pMemoryBarriers,
4463 uint32_t bufferMemoryBarrierCount,
4464 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4465 uint32_t imageMemoryBarrierCount,
4466 const VkImageMemoryBarrier *pImageMemoryBarriers,
4467 const struct radv_barrier_info *info)
4468 {
4469 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4470 enum radv_cmd_flush_bits src_flush_bits = 0;
4471 enum radv_cmd_flush_bits dst_flush_bits = 0;
4472
4473 for (unsigned i = 0; i < info->eventCount; ++i) {
4474 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4475 uint64_t va = radv_buffer_get_va(event->bo);
4476
4477 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4478
4479 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4480
4481 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4482 assert(cmd_buffer->cs->cdw <= cdw_max);
4483 }
4484
4485 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4486 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4487 NULL);
4488 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4489 NULL);
4490 }
4491
4492 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4493 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4494 NULL);
4495 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4496 NULL);
4497 }
4498
4499 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4500 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4501
4502 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4503 image);
4504 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4505 image);
4506 }
4507
4508 radv_stage_flush(cmd_buffer, info->srcStageMask);
4509 cmd_buffer->state.flush_bits |= src_flush_bits;
4510
4511 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4512 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4513 radv_handle_image_transition(cmd_buffer, image,
4514 pImageMemoryBarriers[i].oldLayout,
4515 pImageMemoryBarriers[i].newLayout,
4516 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4517 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4518 &pImageMemoryBarriers[i].subresourceRange);
4519 }
4520
4521 /* Make sure CP DMA is idle because the driver might have performed a
4522 * DMA operation for copying or filling buffers/images.
4523 */
4524 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4525 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4526 si_cp_dma_wait_for_idle(cmd_buffer);
4527
4528 cmd_buffer->state.flush_bits |= dst_flush_bits;
4529 }
4530
4531 void radv_CmdPipelineBarrier(
4532 VkCommandBuffer commandBuffer,
4533 VkPipelineStageFlags srcStageMask,
4534 VkPipelineStageFlags destStageMask,
4535 VkBool32 byRegion,
4536 uint32_t memoryBarrierCount,
4537 const VkMemoryBarrier* pMemoryBarriers,
4538 uint32_t bufferMemoryBarrierCount,
4539 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4540 uint32_t imageMemoryBarrierCount,
4541 const VkImageMemoryBarrier* pImageMemoryBarriers)
4542 {
4543 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4544 struct radv_barrier_info info;
4545
4546 info.eventCount = 0;
4547 info.pEvents = NULL;
4548 info.srcStageMask = srcStageMask;
4549
4550 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4551 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4552 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4553 }
4554
4555
4556 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4557 struct radv_event *event,
4558 VkPipelineStageFlags stageMask,
4559 unsigned value)
4560 {
4561 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4562 uint64_t va = radv_buffer_get_va(event->bo);
4563
4564 si_emit_cache_flush(cmd_buffer);
4565
4566 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4567
4568 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4569
4570 /* Flags that only require a top-of-pipe event. */
4571 VkPipelineStageFlags top_of_pipe_flags =
4572 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4573
4574 /* Flags that only require a post-index-fetch event. */
4575 VkPipelineStageFlags post_index_fetch_flags =
4576 top_of_pipe_flags |
4577 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4578 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4579
4580 /* Make sure CP DMA is idle because the driver might have performed a
4581 * DMA operation for copying or filling buffers/images.
4582 */
4583 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4584 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4585 si_cp_dma_wait_for_idle(cmd_buffer);
4586
4587 /* TODO: Emit EOS events for syncing PS/CS stages. */
4588
4589 if (!(stageMask & ~top_of_pipe_flags)) {
4590 /* Just need to sync the PFP engine. */
4591 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4592 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4593 S_370_WR_CONFIRM(1) |
4594 S_370_ENGINE_SEL(V_370_PFP));
4595 radeon_emit(cs, va);
4596 radeon_emit(cs, va >> 32);
4597 radeon_emit(cs, value);
4598 } else if (!(stageMask & ~post_index_fetch_flags)) {
4599 /* Sync ME because PFP reads index and indirect buffers. */
4600 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4601 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4602 S_370_WR_CONFIRM(1) |
4603 S_370_ENGINE_SEL(V_370_ME));
4604 radeon_emit(cs, va);
4605 radeon_emit(cs, va >> 32);
4606 radeon_emit(cs, value);
4607 } else {
4608 /* Otherwise, sync all prior GPU work using an EOP event. */
4609 si_cs_emit_write_event_eop(cs,
4610 cmd_buffer->device->physical_device->rad_info.chip_class,
4611 radv_cmd_buffer_uses_mec(cmd_buffer),
4612 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4613 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4614 cmd_buffer->gfx9_eop_bug_va);
4615 }
4616
4617 assert(cmd_buffer->cs->cdw <= cdw_max);
4618 }
4619
4620 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4621 VkEvent _event,
4622 VkPipelineStageFlags stageMask)
4623 {
4624 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4625 RADV_FROM_HANDLE(radv_event, event, _event);
4626
4627 write_event(cmd_buffer, event, stageMask, 1);
4628 }
4629
4630 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4631 VkEvent _event,
4632 VkPipelineStageFlags stageMask)
4633 {
4634 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4635 RADV_FROM_HANDLE(radv_event, event, _event);
4636
4637 write_event(cmd_buffer, event, stageMask, 0);
4638 }
4639
4640 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4641 uint32_t eventCount,
4642 const VkEvent* pEvents,
4643 VkPipelineStageFlags srcStageMask,
4644 VkPipelineStageFlags dstStageMask,
4645 uint32_t memoryBarrierCount,
4646 const VkMemoryBarrier* pMemoryBarriers,
4647 uint32_t bufferMemoryBarrierCount,
4648 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4649 uint32_t imageMemoryBarrierCount,
4650 const VkImageMemoryBarrier* pImageMemoryBarriers)
4651 {
4652 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4653 struct radv_barrier_info info;
4654
4655 info.eventCount = eventCount;
4656 info.pEvents = pEvents;
4657 info.srcStageMask = 0;
4658
4659 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4660 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4661 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4662 }
4663
4664
4665 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4666 uint32_t deviceMask)
4667 {
4668 /* No-op */
4669 }
4670
4671 /* VK_EXT_conditional_rendering */
4672 void radv_CmdBeginConditionalRenderingEXT(
4673 VkCommandBuffer commandBuffer,
4674 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4675 {
4676 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4677 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4678 bool draw_visible = true;
4679 uint64_t va;
4680
4681 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4682
4683 /* By default, if the 32-bit value at offset in buffer memory is zero,
4684 * then the rendering commands are discarded, otherwise they are
4685 * executed as normal. If the inverted flag is set, all commands are
4686 * discarded if the value is non zero.
4687 */
4688 if (pConditionalRenderingBegin->flags &
4689 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4690 draw_visible = false;
4691 }
4692
4693 /* Enable predication for this command buffer. */
4694 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4695 cmd_buffer->state.predicating = true;
4696
4697 /* Store conditional rendering user info. */
4698 cmd_buffer->state.predication_type = draw_visible;
4699 cmd_buffer->state.predication_va = va;
4700 }
4701
4702 void radv_CmdEndConditionalRenderingEXT(
4703 VkCommandBuffer commandBuffer)
4704 {
4705 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4706
4707 /* Disable predication for this command buffer. */
4708 si_emit_set_predication_state(cmd_buffer, false, 0);
4709 cmd_buffer->state.predicating = false;
4710
4711 /* Reset conditional rendering user info. */
4712 cmd_buffer->state.predication_type = -1;
4713 cmd_buffer->state.predication_va = 0;
4714 }
4715
4716 /* VK_EXT_transform_feedback */
4717 void radv_CmdBindTransformFeedbackBuffersEXT(
4718 VkCommandBuffer commandBuffer,
4719 uint32_t firstBinding,
4720 uint32_t bindingCount,
4721 const VkBuffer* pBuffers,
4722 const VkDeviceSize* pOffsets,
4723 const VkDeviceSize* pSizes)
4724 {
4725 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4726 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4727 uint8_t enabled_mask = 0;
4728
4729 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4730 for (uint32_t i = 0; i < bindingCount; i++) {
4731 uint32_t idx = firstBinding + i;
4732
4733 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4734 sb[idx].offset = pOffsets[i];
4735 sb[idx].size = pSizes[i];
4736
4737 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4738 sb[idx].buffer->bo);
4739
4740 enabled_mask |= 1 << idx;
4741 }
4742
4743 cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4744
4745 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4746 }
4747
4748 static void
4749 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4750 {
4751 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4752 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4753
4754 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
4755 radeon_emit(cs,
4756 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
4757 S_028B94_RAST_STREAM(0) |
4758 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
4759 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
4760 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
4761 radeon_emit(cs, so->hw_enabled_mask &
4762 so->enabled_stream_buffers_mask);
4763 }
4764
4765 static void
4766 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
4767 {
4768 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4769 bool old_streamout_enabled = so->streamout_enabled;
4770 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
4771
4772 so->streamout_enabled = enable;
4773
4774 so->hw_enabled_mask = so->enabled_mask |
4775 (so->enabled_mask << 4) |
4776 (so->enabled_mask << 8) |
4777 (so->enabled_mask << 12);
4778
4779 if ((old_streamout_enabled != so->streamout_enabled) ||
4780 (old_hw_enabled_mask != so->hw_enabled_mask))
4781 radv_emit_streamout_enable(cmd_buffer);
4782 }
4783
4784 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
4785 {
4786 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4787 unsigned reg_strmout_cntl;
4788
4789 /* The register is at different places on different ASICs. */
4790 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
4791 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
4792 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
4793 } else {
4794 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
4795 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
4796 }
4797
4798 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4799 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
4800
4801 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
4802 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
4803 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
4804 radeon_emit(cs, 0);
4805 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4806 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4807 radeon_emit(cs, 4); /* poll interval */
4808 }
4809
4810 void radv_CmdBeginTransformFeedbackEXT(
4811 VkCommandBuffer commandBuffer,
4812 uint32_t firstCounterBuffer,
4813 uint32_t counterBufferCount,
4814 const VkBuffer* pCounterBuffers,
4815 const VkDeviceSize* pCounterBufferOffsets)
4816 {
4817 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4818 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4819 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4820 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4821 uint32_t i;
4822
4823 radv_flush_vgt_streamout(cmd_buffer);
4824
4825 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4826 for_each_bit(i, so->enabled_mask) {
4827 int32_t counter_buffer_idx = i - firstCounterBuffer;
4828 if (counter_buffer_idx >= 0 && counter_buffer_idx > counterBufferCount)
4829 counter_buffer_idx = -1;
4830
4831 /* SI binds streamout buffers as shader resources.
4832 * VGT only counts primitives and tells the shader through
4833 * SGPRs what to do.
4834 */
4835 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
4836 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
4837 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
4838
4839 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
4840 /* The array of counter buffers is optional. */
4841 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
4842 uint64_t va = radv_buffer_get_va(buffer->bo);
4843
4844 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
4845
4846 /* Append */
4847 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4848 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4849 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4850 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
4851 radeon_emit(cs, 0); /* unused */
4852 radeon_emit(cs, 0); /* unused */
4853 radeon_emit(cs, va); /* src address lo */
4854 radeon_emit(cs, va >> 32); /* src address hi */
4855
4856 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4857 } else {
4858 /* Start from the beginning. */
4859 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4860 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4861 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4862 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
4863 radeon_emit(cs, 0); /* unused */
4864 radeon_emit(cs, 0); /* unused */
4865 radeon_emit(cs, 0); /* unused */
4866 radeon_emit(cs, 0); /* unused */
4867 }
4868 }
4869
4870 radv_set_streamout_enable(cmd_buffer, true);
4871 }
4872
4873 void radv_CmdEndTransformFeedbackEXT(
4874 VkCommandBuffer commandBuffer,
4875 uint32_t firstCounterBuffer,
4876 uint32_t counterBufferCount,
4877 const VkBuffer* pCounterBuffers,
4878 const VkDeviceSize* pCounterBufferOffsets)
4879 {
4880 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4881 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4882 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4883 uint32_t i;
4884
4885 radv_flush_vgt_streamout(cmd_buffer);
4886
4887 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4888 for_each_bit(i, so->enabled_mask) {
4889 int32_t counter_buffer_idx = i - firstCounterBuffer;
4890 if (counter_buffer_idx >= 0 && counter_buffer_idx > counterBufferCount)
4891 counter_buffer_idx = -1;
4892
4893 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
4894 /* The array of counters buffer is optional. */
4895 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
4896 uint64_t va = radv_buffer_get_va(buffer->bo);
4897
4898 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
4899
4900 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4901 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4902 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4903 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
4904 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
4905 radeon_emit(cs, va); /* dst address lo */
4906 radeon_emit(cs, va >> 32); /* dst address hi */
4907 radeon_emit(cs, 0); /* unused */
4908 radeon_emit(cs, 0); /* unused */
4909
4910 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4911 }
4912
4913 /* Deactivate transform feedback by zeroing the buffer size.
4914 * The counters (primitives generated, primitives emitted) may
4915 * be enabled even if there is not buffer bound. This ensures
4916 * that the primitives-emitted query won't increment.
4917 */
4918 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
4919 }
4920
4921 radv_set_streamout_enable(cmd_buffer, false);
4922 }
4923
4924 void radv_CmdDrawIndirectByteCountEXT(
4925 VkCommandBuffer commandBuffer,
4926 uint32_t instanceCount,
4927 uint32_t firstInstance,
4928 VkBuffer _counterBuffer,
4929 VkDeviceSize counterBufferOffset,
4930 uint32_t counterOffset,
4931 uint32_t vertexStride)
4932 {
4933 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4934 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
4935 struct radv_draw_info info = {};
4936
4937 info.instance_count = instanceCount;
4938 info.first_instance = firstInstance;
4939 info.strmout_buffer = counterBuffer;
4940 info.strmout_buffer_offset = counterBufferOffset;
4941 info.stride = vertexStride;
4942
4943 radv_draw(cmd_buffer, &info);
4944 }