projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: add tessellation ring allocation support. (v2)
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 uint32_t src_family,
42 uint32_t dst_family,
43 const VkImageSubresourceRange *range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static void
191 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
192 {
193 list_del(&cmd_buffer->pool_link);
194
195 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
196 &cmd_buffer->upload.list, list) {
197 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
198 list_del(&up->list);
199 free(up);
200 }
201
202 if (cmd_buffer->upload.upload_bo)
203 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
204 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
205 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
206 }
207
208 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
209 {
210
211 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
212
213 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
214 &cmd_buffer->upload.list, list) {
215 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
216 list_del(&up->list);
217 free(up);
218 }
219
220 cmd_buffer->scratch_size_needed = 0;
221 cmd_buffer->compute_scratch_size_needed = 0;
222 cmd_buffer->esgs_ring_size_needed = 0;
223 cmd_buffer->gsvs_ring_size_needed = 0;
224 cmd_buffer->tess_rings_needed = false;
225
226 if (cmd_buffer->upload.upload_bo)
227 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
228 cmd_buffer->upload.upload_bo, 8);
229 cmd_buffer->upload.offset = 0;
230
231 cmd_buffer->record_fail = false;
232
233 cmd_buffer->ring_offsets_idx = -1;
234 }
235
236 static bool
237 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
238 uint64_t min_needed)
239 {
240 uint64_t new_size;
241 struct radeon_winsys_bo *bo;
242 struct radv_cmd_buffer_upload *upload;
243 struct radv_device *device = cmd_buffer->device;
244
245 new_size = MAX2(min_needed, 16 * 1024);
246 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
247
248 bo = device->ws->buffer_create(device->ws,
249 new_size, 4096,
250 RADEON_DOMAIN_GTT,
251 RADEON_FLAG_CPU_ACCESS);
252
253 if (!bo) {
254 cmd_buffer->record_fail = true;
255 return false;
256 }
257
258 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
259 if (cmd_buffer->upload.upload_bo) {
260 upload = malloc(sizeof(*upload));
261
262 if (!upload) {
263 cmd_buffer->record_fail = true;
264 device->ws->buffer_destroy(bo);
265 return false;
266 }
267
268 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
269 list_add(&upload->list, &cmd_buffer->upload.list);
270 }
271
272 cmd_buffer->upload.upload_bo = bo;
273 cmd_buffer->upload.size = new_size;
274 cmd_buffer->upload.offset = 0;
275 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
276
277 if (!cmd_buffer->upload.map) {
278 cmd_buffer->record_fail = true;
279 return false;
280 }
281
282 return true;
283 }
284
285 bool
286 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
287 unsigned size,
288 unsigned alignment,
289 unsigned *out_offset,
290 void **ptr)
291 {
292 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
293 if (offset + size > cmd_buffer->upload.size) {
294 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
295 return false;
296 offset = 0;
297 }
298
299 *out_offset = offset;
300 *ptr = cmd_buffer->upload.map + offset;
301
302 cmd_buffer->upload.offset = offset + size;
303 return true;
304 }
305
306 bool
307 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
308 unsigned size, unsigned alignment,
309 const void *data, unsigned *out_offset)
310 {
311 uint8_t *ptr;
312
313 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
314 out_offset, (void **)&ptr))
315 return false;
316
317 if (ptr)
318 memcpy(ptr, data, size);
319
320 return true;
321 }
322
323 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
324 {
325 struct radv_device *device = cmd_buffer->device;
326 struct radeon_winsys_cs *cs = cmd_buffer->cs;
327 uint64_t va;
328
329 if (!device->trace_bo)
330 return;
331
332 va = device->ws->buffer_get_va(device->trace_bo);
333
334 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
335
336 ++cmd_buffer->state.trace_id;
337 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
338 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
339 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
340 S_370_WR_CONFIRM(1) |
341 S_370_ENGINE_SEL(V_370_ME));
342 radeon_emit(cs, va);
343 radeon_emit(cs, va >> 32);
344 radeon_emit(cs, cmd_buffer->state.trace_id);
345 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
346 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
347 }
348
349 static void
350 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
351 struct radv_pipeline *pipeline)
352 {
353 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
354 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
355 8);
356 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
357 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
358 }
359
360 static void
361 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
362 struct radv_pipeline *pipeline)
363 {
364 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
365 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
366 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
367
368 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
369 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
370 }
371
372 /* 12.4 fixed-point */
373 static unsigned radv_pack_float_12p4(float x)
374 {
375 return x <= 0 ? 0 :
376 x >= 4096 ? 0xffff : x * 16;
377 }
378
379 static uint32_t
380 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
381 {
382 switch (stage) {
383 case MESA_SHADER_FRAGMENT:
384 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
385 case MESA_SHADER_VERTEX:
386 if (has_tess)
387 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
388 else
389 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
390 case MESA_SHADER_GEOMETRY:
391 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
392 case MESA_SHADER_COMPUTE:
393 return R_00B900_COMPUTE_USER_DATA_0;
394 case MESA_SHADER_TESS_CTRL:
395 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
396 case MESA_SHADER_TESS_EVAL:
397 if (has_gs)
398 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
399 else
400 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
401 default:
402 unreachable("unknown shader");
403 }
404 }
405
406 static struct ac_userdata_info *
407 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
408 gl_shader_stage stage,
409 int idx)
410 {
411 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
412 }
413
414 static void
415 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
416 struct radv_pipeline *pipeline,
417 gl_shader_stage stage,
418 int idx, uint64_t va)
419 {
420 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
421 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
422 if (loc->sgpr_idx == -1)
423 return;
424 assert(loc->num_sgprs == 2);
425 assert(!loc->indirect);
426 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
427 radeon_emit(cmd_buffer->cs, va);
428 radeon_emit(cmd_buffer->cs, va >> 32);
429 }
430
431 static void
432 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
433 struct radv_pipeline *pipeline)
434 {
435 int num_samples = pipeline->graphics.ms.num_samples;
436 struct radv_multisample_state *ms = &pipeline->graphics.ms;
437 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
438
439 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
440 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
441 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
442
443 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
444 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
445
446 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
447 return;
448
449 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
450 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
451 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
452
453 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
454
455 uint32_t samples_offset;
456 void *samples_ptr;
457 void *src;
458 radv_cmd_buffer_upload_alloc(cmd_buffer, num_samples * 4 * 2, 256, &samples_offset,
459 &samples_ptr);
460 switch (num_samples) {
461 case 1:
462 src = cmd_buffer->device->sample_locations_1x;
463 break;
464 case 2:
465 src = cmd_buffer->device->sample_locations_2x;
466 break;
467 case 4:
468 src = cmd_buffer->device->sample_locations_4x;
469 break;
470 case 8:
471 src = cmd_buffer->device->sample_locations_8x;
472 break;
473 case 16:
474 src = cmd_buffer->device->sample_locations_16x;
475 break;
476 default:
477 unreachable("unknown number of samples");
478 }
479 memcpy(samples_ptr, src, num_samples * 4 * 2);
480
481 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
482 va += samples_offset;
483
484 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
485 AC_UD_PS_SAMPLE_POS, va);
486 }
487
488 static void
489 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
490 struct radv_pipeline *pipeline)
491 {
492 struct radv_raster_state *raster = &pipeline->graphics.raster;
493
494 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
495 raster->pa_cl_clip_cntl);
496
497 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
498 raster->spi_interp_control);
499
500 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
501 unsigned tmp = (unsigned)(1.0 * 8.0);
502 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
503 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
504 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
505
506 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
507 raster->pa_su_vtx_cntl);
508
509 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
510 raster->pa_su_sc_mode_cntl);
511 }
512
513 static void
514 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
515 struct radv_pipeline *pipeline,
516 struct radv_shader_variant *shader,
517 struct ac_vs_output_info *outinfo)
518 {
519 struct radeon_winsys *ws = cmd_buffer->device->ws;
520 uint64_t va = ws->buffer_get_va(shader->bo);
521 unsigned export_count;
522
523 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
524
525 export_count = MAX2(1, outinfo->param_exports);
526 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
527 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
528
529 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
530 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
531 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
532 V_02870C_SPI_SHADER_4COMP :
533 V_02870C_SPI_SHADER_NONE) |
534 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
535 V_02870C_SPI_SHADER_4COMP :
536 V_02870C_SPI_SHADER_NONE) |
537 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
538 V_02870C_SPI_SHADER_4COMP :
539 V_02870C_SPI_SHADER_NONE));
540
541
542 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
543 radeon_emit(cmd_buffer->cs, va >> 8);
544 radeon_emit(cmd_buffer->cs, va >> 40);
545 radeon_emit(cmd_buffer->cs, shader->rsrc1);
546 radeon_emit(cmd_buffer->cs, shader->rsrc2);
547
548 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
549 S_028818_VTX_W0_FMT(1) |
550 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
551 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
552 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
553
554
555 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
556 pipeline->graphics.pa_cl_vs_out_cntl);
557
558 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
559 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
560 }
561
562 static void
563 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
564 struct radv_shader_variant *shader,
565 struct ac_es_output_info *outinfo)
566 {
567 struct radeon_winsys *ws = cmd_buffer->device->ws;
568 uint64_t va = ws->buffer_get_va(shader->bo);
569
570 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
571
572 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
573 outinfo->esgs_itemsize / 4);
574 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
575 radeon_emit(cmd_buffer->cs, va >> 8);
576 radeon_emit(cmd_buffer->cs, va >> 40);
577 radeon_emit(cmd_buffer->cs, shader->rsrc1);
578 radeon_emit(cmd_buffer->cs, shader->rsrc2);
579 }
580
581 static void
582 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
583 struct radv_pipeline *pipeline)
584 {
585 struct radv_shader_variant *vs;
586
587 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
588
589 vs = pipeline->shaders[MESA_SHADER_VERTEX];
590
591 if (vs->info.vs.as_es)
592 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
593 else
594 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
595
596 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
597 }
598
599
600 static void
601 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
602 struct radv_pipeline *pipeline)
603 {
604 struct radeon_winsys *ws = cmd_buffer->device->ws;
605 struct radv_shader_variant *gs;
606 uint64_t va;
607
608 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
609
610 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
611 if (!gs)
612 return;
613
614 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
615
616 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
617 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
618 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
619 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
620
621 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
622
623 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
624
625 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
626 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
627 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
628 radeon_emit(cmd_buffer->cs, 0);
629 radeon_emit(cmd_buffer->cs, 0);
630 radeon_emit(cmd_buffer->cs, 0);
631
632 uint32_t gs_num_invocations = gs->info.gs.invocations;
633 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
634 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
635 S_028B90_ENABLE(gs_num_invocations > 0));
636
637 va = ws->buffer_get_va(gs->bo);
638 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
639 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
640 radeon_emit(cmd_buffer->cs, va >> 8);
641 radeon_emit(cmd_buffer->cs, va >> 40);
642 radeon_emit(cmd_buffer->cs, gs->rsrc1);
643 radeon_emit(cmd_buffer->cs, gs->rsrc2);
644
645 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
646
647 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
648 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
649 if (loc->sgpr_idx != -1) {
650 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
651 uint32_t num_entries = 64;
652 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
653
654 if (is_vi)
655 num_entries *= stride;
656
657 stride = S_008F04_STRIDE(stride);
658 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
659 radeon_emit(cmd_buffer->cs, stride);
660 radeon_emit(cmd_buffer->cs, num_entries);
661 }
662 }
663
664 static void
665 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
666 struct radv_pipeline *pipeline)
667 {
668 struct radeon_winsys *ws = cmd_buffer->device->ws;
669 struct radv_shader_variant *ps;
670 uint64_t va;
671 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
672 struct radv_blend_state *blend = &pipeline->graphics.blend;
673 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
674
675 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
676
677 va = ws->buffer_get_va(ps->bo);
678 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
679
680 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
681 radeon_emit(cmd_buffer->cs, va >> 8);
682 radeon_emit(cmd_buffer->cs, va >> 40);
683 radeon_emit(cmd_buffer->cs, ps->rsrc1);
684 radeon_emit(cmd_buffer->cs, ps->rsrc2);
685
686 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
687 pipeline->graphics.db_shader_control);
688
689 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
690 ps->config.spi_ps_input_ena);
691
692 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
693 ps->config.spi_ps_input_addr);
694
695 if (ps->info.fs.force_persample)
696 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
697
698 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
699 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
700
701 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
702
703 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
704 pipeline->graphics.shader_z_format);
705
706 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
707
708 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
709 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
710
711 if (pipeline->graphics.ps_input_cntl_num) {
712 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
713 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
714 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
715 }
716 }
717 }
718
719 static void
720 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
721 struct radv_pipeline *pipeline)
722 {
723 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
724 return;
725
726 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
727 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
728 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
729 radv_update_multisample_state(cmd_buffer, pipeline);
730 radv_emit_vertex_shader(cmd_buffer, pipeline);
731 radv_emit_geometry_shader(cmd_buffer, pipeline);
732 radv_emit_fragment_shader(cmd_buffer, pipeline);
733
734 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
735 pipeline->graphics.prim_restart_enable);
736
737 cmd_buffer->scratch_size_needed =
738 MAX2(cmd_buffer->scratch_size_needed,
739 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
740
741 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
742 S_0286E8_WAVES(pipeline->max_waves) |
743 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
744
745 if (!cmd_buffer->state.emitted_pipeline ||
746 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
747 pipeline->graphics.can_use_guardband)
748 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
749 cmd_buffer->state.emitted_pipeline = pipeline;
750 }
751
752 static void
753 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
754 {
755 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
756 cmd_buffer->state.dynamic.viewport.viewports);
757 }
758
759 static void
760 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
761 {
762 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
763 si_write_scissors(cmd_buffer->cs, 0, count,
764 cmd_buffer->state.dynamic.scissor.scissors,
765 cmd_buffer->state.dynamic.viewport.viewports,
766 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
767 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
768 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
769 }
770
771 static void
772 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
773 int index,
774 struct radv_color_buffer_info *cb)
775 {
776 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
777 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
778 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
779 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
780 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
781 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
782 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
783 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
784 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
785 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
786 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
787 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
788 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
789
790 if (is_vi) { /* DCC BASE */
791 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
792 }
793 }
794
795 static void
796 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
797 struct radv_ds_buffer_info *ds,
798 struct radv_image *image,
799 VkImageLayout layout)
800 {
801 uint32_t db_z_info = ds->db_z_info;
802
803 if (!radv_layout_has_htile(image, layout))
804 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
805
806 if (!radv_layout_can_expclear(image, layout))
807 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
808
809 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
810 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
811
812 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
813 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
814 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
815 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
816 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
817 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
818 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
819 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
820 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
821 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
822
823 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
824 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
825 ds->pa_su_poly_offset_db_fmt_cntl);
826 }
827
828 /*
829 * To hw resolve multisample images both src and dst need to have the same
830 * micro tiling mode. However we don't always know in advance when creating
831 * the images. This function gets called if we have a resolve attachment,
832 * and tests if the attachment image has the same tiling mode, then it
833 * checks if the generated framebuffer data has the same tiling mode, and
834 * updates it if not.
835 */
836 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
837 struct radv_attachment_info *att,
838 uint32_t micro_tile_mode)
839 {
840 struct radv_image *image = att->attachment->image;
841 uint32_t tile_mode_index;
842 if (image->surface.nsamples <= 1)
843 return;
844
845 if (image->surface.micro_tile_mode != micro_tile_mode) {
846 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
847 }
848
849 if (att->cb.micro_tile_mode != micro_tile_mode) {
850 tile_mode_index = image->surface.tiling_index[0];
851
852 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
853 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
854 att->cb.micro_tile_mode = micro_tile_mode;
855 }
856 }
857
858 void
859 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
860 struct radv_image *image,
861 VkClearDepthStencilValue ds_clear_value,
862 VkImageAspectFlags aspects)
863 {
864 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
865 va += image->offset + image->clear_value_offset;
866 unsigned reg_offset = 0, reg_count = 0;
867
868 if (!image->surface.htile_size || !aspects)
869 return;
870
871 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
872 ++reg_count;
873 } else {
874 ++reg_offset;
875 va += 4;
876 }
877 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
878 ++reg_count;
879
880 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
881
882 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
883 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
884 S_370_WR_CONFIRM(1) |
885 S_370_ENGINE_SEL(V_370_PFP));
886 radeon_emit(cmd_buffer->cs, va);
887 radeon_emit(cmd_buffer->cs, va >> 32);
888 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
889 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
890 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
891 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
892
893 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
894 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
895 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
896 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
897 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
898 }
899
900 static void
901 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
902 struct radv_image *image)
903 {
904 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
905 va += image->offset + image->clear_value_offset;
906
907 if (!image->surface.htile_size)
908 return;
909
910 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
911
912 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
913 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
914 COPY_DATA_DST_SEL(COPY_DATA_REG) |
915 COPY_DATA_COUNT_SEL);
916 radeon_emit(cmd_buffer->cs, va);
917 radeon_emit(cmd_buffer->cs, va >> 32);
918 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
919 radeon_emit(cmd_buffer->cs, 0);
920
921 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
922 radeon_emit(cmd_buffer->cs, 0);
923 }
924
925 void
926 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
927 struct radv_image *image,
928 int idx,
929 uint32_t color_values[2])
930 {
931 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
932 va += image->offset + image->clear_value_offset;
933
934 if (!image->cmask.size && !image->surface.dcc_size)
935 return;
936
937 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
938
939 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
940 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
941 S_370_WR_CONFIRM(1) |
942 S_370_ENGINE_SEL(V_370_PFP));
943 radeon_emit(cmd_buffer->cs, va);
944 radeon_emit(cmd_buffer->cs, va >> 32);
945 radeon_emit(cmd_buffer->cs, color_values[0]);
946 radeon_emit(cmd_buffer->cs, color_values[1]);
947
948 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
949 radeon_emit(cmd_buffer->cs, color_values[0]);
950 radeon_emit(cmd_buffer->cs, color_values[1]);
951 }
952
953 static void
954 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
955 struct radv_image *image,
956 int idx)
957 {
958 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
959 va += image->offset + image->clear_value_offset;
960
961 if (!image->cmask.size && !image->surface.dcc_size)
962 return;
963
964 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
965 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
966
967 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
968 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
969 COPY_DATA_DST_SEL(COPY_DATA_REG) |
970 COPY_DATA_COUNT_SEL);
971 radeon_emit(cmd_buffer->cs, va);
972 radeon_emit(cmd_buffer->cs, va >> 32);
973 radeon_emit(cmd_buffer->cs, reg >> 2);
974 radeon_emit(cmd_buffer->cs, 0);
975
976 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
977 radeon_emit(cmd_buffer->cs, 0);
978 }
979
980 void
981 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
982 {
983 int i;
984 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
985 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
986 int dst_resolve_micro_tile_mode = -1;
987
988 if (subpass->has_resolve) {
989 uint32_t a = subpass->resolve_attachments[0].attachment;
990 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
991 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
992 }
993 for (i = 0; i < subpass->color_count; ++i) {
994 int idx = subpass->color_attachments[i].attachment;
995 struct radv_attachment_info *att = &framebuffer->attachments[idx];
996
997 if (dst_resolve_micro_tile_mode != -1) {
998 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
999 att, dst_resolve_micro_tile_mode);
1000 }
1001 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1002
1003 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1004 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1005
1006 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1007 }
1008
1009 for (i = subpass->color_count; i < 8; i++)
1010 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1011 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1012
1013 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1014 int idx = subpass->depth_stencil_attachment.attachment;
1015 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1016 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1017 struct radv_image *image = att->attachment->image;
1018 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1019
1020 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1021
1022 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1023 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1024 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1025 }
1026 radv_load_depth_clear_regs(cmd_buffer, image);
1027 } else {
1028 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1029 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1030 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1031 }
1032 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1033 S_028208_BR_X(framebuffer->width) |
1034 S_028208_BR_Y(framebuffer->height));
1035 }
1036
1037 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1038 {
1039 uint32_t db_count_control;
1040
1041 if(!cmd_buffer->state.active_occlusion_queries) {
1042 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1043 db_count_control = 0;
1044 } else {
1045 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1046 }
1047 } else {
1048 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1049 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1050 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1051 S_028004_ZPASS_ENABLE(1) |
1052 S_028004_SLICE_EVEN_ENABLE(1) |
1053 S_028004_SLICE_ODD_ENABLE(1);
1054 } else {
1055 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1056 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1057 }
1058 }
1059
1060 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1061 }
1062
1063 static void
1064 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1065 {
1066 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1067
1068 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1069 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1070 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1071 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1072 }
1073
1074 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1075 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1076 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1077 }
1078
1079 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1080 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1081 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1082 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1083 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1084 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1085 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1086 S_028430_STENCILOPVAL(1));
1087 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1088 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1089 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1090 S_028434_STENCILOPVAL_BF(1));
1091 }
1092
1093 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1094 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1095 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1096 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1097 }
1098
1099 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1100 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1101 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1102 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1103 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1104
1105 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1106 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1107 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1108 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1109 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1110 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1111 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1112 }
1113 }
1114
1115 cmd_buffer->state.dirty = 0;
1116 }
1117
1118 static void
1119 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1120 struct radv_pipeline *pipeline,
1121 int idx,
1122 uint64_t va,
1123 gl_shader_stage stage)
1124 {
1125 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1126 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1127
1128 if (desc_set_loc->sgpr_idx == -1)
1129 return;
1130
1131 assert(!desc_set_loc->indirect);
1132 assert(desc_set_loc->num_sgprs == 2);
1133 radeon_set_sh_reg_seq(cmd_buffer->cs,
1134 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1135 radeon_emit(cmd_buffer->cs, va);
1136 radeon_emit(cmd_buffer->cs, va >> 32);
1137 }
1138
1139 static void
1140 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1141 struct radv_pipeline *pipeline,
1142 VkShaderStageFlags stages,
1143 struct radv_descriptor_set *set,
1144 unsigned idx)
1145 {
1146 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1147 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1148 idx, set->va,
1149 MESA_SHADER_FRAGMENT);
1150
1151 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1152 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1153 idx, set->va,
1154 MESA_SHADER_VERTEX);
1155
1156 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1157 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1158 idx, set->va,
1159 MESA_SHADER_GEOMETRY);
1160
1161 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1162 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1163 idx, set->va,
1164 MESA_SHADER_TESS_CTRL);
1165
1166 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1167 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1168 idx, set->va,
1169 MESA_SHADER_TESS_EVAL);
1170
1171 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1172 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1173 idx, set->va,
1174 MESA_SHADER_COMPUTE);
1175 }
1176
1177 static void
1178 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1179 struct radv_pipeline *pipeline,
1180 VkShaderStageFlags stages)
1181 {
1182 unsigned i;
1183 if (!cmd_buffer->state.descriptors_dirty)
1184 return;
1185
1186 for (i = 0; i < MAX_SETS; i++) {
1187 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1188 continue;
1189 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1190 if (!set)
1191 continue;
1192
1193 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1194 }
1195 cmd_buffer->state.descriptors_dirty = 0;
1196 }
1197
1198 static void
1199 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1200 struct radv_pipeline *pipeline,
1201 VkShaderStageFlags stages)
1202 {
1203 struct radv_pipeline_layout *layout = pipeline->layout;
1204 unsigned offset;
1205 void *ptr;
1206 uint64_t va;
1207
1208 stages &= cmd_buffer->push_constant_stages;
1209 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1210 return;
1211
1212 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1213 16 * layout->dynamic_offset_count,
1214 256, &offset, &ptr))
1215 return;
1216
1217 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1218 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1219 16 * layout->dynamic_offset_count);
1220
1221 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1222 va += offset;
1223
1224 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1225 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1226 AC_UD_PUSH_CONSTANTS, va);
1227
1228 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1229 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1230 AC_UD_PUSH_CONSTANTS, va);
1231
1232 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1233 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1234 AC_UD_PUSH_CONSTANTS, va);
1235
1236 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1237 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL,
1238 AC_UD_PUSH_CONSTANTS, va);
1239
1240 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1241 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL,
1242 AC_UD_PUSH_CONSTANTS, va);
1243
1244 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1245 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1246 AC_UD_PUSH_CONSTANTS, va);
1247
1248 cmd_buffer->push_constant_stages &= ~stages;
1249 }
1250
1251 static void
1252 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1253 bool instanced_draw, bool indirect_draw,
1254 uint32_t draw_vertex_count)
1255 {
1256 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1257 struct radv_device *device = cmd_buffer->device;
1258 uint32_t ia_multi_vgt_param;
1259 uint32_t ls_hs_config = 0;
1260
1261 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1262 cmd_buffer->cs, 4096);
1263
1264 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1265 cmd_buffer->state.pipeline->num_vertex_attribs) {
1266 unsigned vb_offset;
1267 void *vb_ptr;
1268 uint32_t i = 0;
1269 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1270 uint64_t va;
1271
1272 /* allocate some descriptor state for vertex buffers */
1273 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1274 &vb_offset, &vb_ptr);
1275
1276 for (i = 0; i < num_attribs; i++) {
1277 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1278 uint32_t offset;
1279 int vb = cmd_buffer->state.pipeline->va_binding[i];
1280 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1281 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1282
1283 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1284 va = device->ws->buffer_get_va(buffer->bo);
1285
1286 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1287 va += offset + buffer->offset;
1288 desc[0] = va;
1289 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1290 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1291 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1292 else
1293 desc[2] = buffer->size - offset;
1294 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1295 }
1296
1297 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1298 va += vb_offset;
1299
1300 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1301 AC_UD_VS_VERTEX_BUFFERS, va);
1302 }
1303
1304 cmd_buffer->state.vertex_descriptors_dirty = false;
1305 cmd_buffer->state.vb_dirty = 0;
1306 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1307 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1308
1309 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1310 radv_emit_framebuffer_state(cmd_buffer);
1311
1312 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1313 radv_emit_viewport(cmd_buffer);
1314
1315 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1316 radv_emit_scissor(cmd_buffer);
1317
1318 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1319 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1320 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1321 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1322 else
1323 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1324 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1325 }
1326
1327 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1328 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1329
1330 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1331 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
1332 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1333 } else {
1334 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1335 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
1336 }
1337 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1338 }
1339
1340 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1341
1342 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1343 VK_SHADER_STAGE_ALL_GRAPHICS);
1344 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1345 VK_SHADER_STAGE_ALL_GRAPHICS);
1346
1347 assert(cmd_buffer->cs->cdw <= cdw_max);
1348
1349 si_emit_cache_flush(cmd_buffer);
1350 }
1351
1352 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1353 VkPipelineStageFlags src_stage_mask)
1354 {
1355 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1356 VK_PIPELINE_STAGE_TRANSFER_BIT |
1357 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1358 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1359 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1360 }
1361
1362 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1363 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1364 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1365 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1366 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1367 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1368 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1369 VK_PIPELINE_STAGE_TRANSFER_BIT |
1370 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1371 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1372 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1373 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1374 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1375 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1376 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1377 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1378 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1379 }
1380 }
1381
1382 static enum radv_cmd_flush_bits
1383 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1384 VkAccessFlags src_flags)
1385 {
1386 enum radv_cmd_flush_bits flush_bits = 0;
1387 uint32_t b;
1388 for_each_bit(b, src_flags) {
1389 switch ((VkAccessFlagBits)(1 << b)) {
1390 case VK_ACCESS_SHADER_WRITE_BIT:
1391 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1392 break;
1393 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1394 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1395 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1396 break;
1397 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1398 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1399 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1400 break;
1401 case VK_ACCESS_TRANSFER_WRITE_BIT:
1402 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1403 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1404 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1405 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1406 RADV_CMD_FLAG_INV_GLOBAL_L2;
1407 break;
1408 default:
1409 break;
1410 }
1411 }
1412 return flush_bits;
1413 }
1414
1415 static enum radv_cmd_flush_bits
1416 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1417 VkAccessFlags dst_flags,
1418 struct radv_image *image)
1419 {
1420 enum radv_cmd_flush_bits flush_bits = 0;
1421 uint32_t b;
1422 for_each_bit(b, dst_flags) {
1423 switch ((VkAccessFlagBits)(1 << b)) {
1424 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1425 case VK_ACCESS_INDEX_READ_BIT:
1426 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1427 break;
1428 case VK_ACCESS_UNIFORM_READ_BIT:
1429 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1430 break;
1431 case VK_ACCESS_SHADER_READ_BIT:
1432 case VK_ACCESS_TRANSFER_READ_BIT:
1433 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1434 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1435 RADV_CMD_FLAG_INV_GLOBAL_L2;
1436 break;
1437 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1438 /* TODO: change to image && when the image gets passed
1439 * through from the subpass. */
1440 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1441 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1442 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1443 break;
1444 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1445 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1446 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1447 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1448 break;
1449 default:
1450 break;
1451 }
1452 }
1453 return flush_bits;
1454 }
1455
1456 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1457 {
1458 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1459 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1460 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1461 NULL);
1462 }
1463
1464 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1465 VkAttachmentReference att)
1466 {
1467 unsigned idx = att.attachment;
1468 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1469 VkImageSubresourceRange range;
1470 range.aspectMask = 0;
1471 range.baseMipLevel = view->base_mip;
1472 range.levelCount = 1;
1473 range.baseArrayLayer = view->base_layer;
1474 range.layerCount = cmd_buffer->state.framebuffer->layers;
1475
1476 radv_handle_image_transition(cmd_buffer,
1477 view->image,
1478 cmd_buffer->state.attachments[idx].current_layout,
1479 att.layout, 0, 0, &range,
1480 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1481
1482 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1483
1484
1485 }
1486
1487 void
1488 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1489 const struct radv_subpass *subpass, bool transitions)
1490 {
1491 if (transitions) {
1492 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1493
1494 for (unsigned i = 0; i < subpass->color_count; ++i) {
1495 radv_handle_subpass_image_transition(cmd_buffer,
1496 subpass->color_attachments[i]);
1497 }
1498
1499 for (unsigned i = 0; i < subpass->input_count; ++i) {
1500 radv_handle_subpass_image_transition(cmd_buffer,
1501 subpass->input_attachments[i]);
1502 }
1503
1504 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1505 radv_handle_subpass_image_transition(cmd_buffer,
1506 subpass->depth_stencil_attachment);
1507 }
1508 }
1509
1510 cmd_buffer->state.subpass = subpass;
1511
1512 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1513 }
1514
1515 static void
1516 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1517 struct radv_render_pass *pass,
1518 const VkRenderPassBeginInfo *info)
1519 {
1520 struct radv_cmd_state *state = &cmd_buffer->state;
1521
1522 if (pass->attachment_count == 0) {
1523 state->attachments = NULL;
1524 return;
1525 }
1526
1527 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1528 pass->attachment_count *
1529 sizeof(state->attachments[0]),
1530 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1531 if (state->attachments == NULL) {
1532 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1533 abort();
1534 }
1535
1536 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1537 struct radv_render_pass_attachment *att = &pass->attachments[i];
1538 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1539 VkImageAspectFlags clear_aspects = 0;
1540
1541 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1542 /* color attachment */
1543 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1544 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1545 }
1546 } else {
1547 /* depthstencil attachment */
1548 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1549 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1550 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1551 }
1552 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1553 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1554 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1555 }
1556 }
1557
1558 state->attachments[i].pending_clear_aspects = clear_aspects;
1559 if (clear_aspects && info) {
1560 assert(info->clearValueCount > i);
1561 state->attachments[i].clear_value = info->pClearValues[i];
1562 }
1563
1564 state->attachments[i].current_layout = att->initial_layout;
1565 }
1566 }
1567
1568 VkResult radv_AllocateCommandBuffers(
1569 VkDevice _device,
1570 const VkCommandBufferAllocateInfo *pAllocateInfo,
1571 VkCommandBuffer *pCommandBuffers)
1572 {
1573 RADV_FROM_HANDLE(radv_device, device, _device);
1574 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1575
1576 VkResult result = VK_SUCCESS;
1577 uint32_t i;
1578
1579 memset(pCommandBuffers, 0,
1580 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1581
1582 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1583
1584 if (!list_empty(&pool->free_cmd_buffers)) {
1585 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1586
1587 list_del(&cmd_buffer->pool_link);
1588 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1589
1590 radv_reset_cmd_buffer(cmd_buffer);
1591 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1592 cmd_buffer->level = pAllocateInfo->level;
1593
1594 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1595 result = VK_SUCCESS;
1596 } else {
1597 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1598 &pCommandBuffers[i]);
1599 }
1600 if (result != VK_SUCCESS)
1601 break;
1602 }
1603
1604 if (result != VK_SUCCESS)
1605 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1606 i, pCommandBuffers);
1607
1608 return result;
1609 }
1610
1611 void radv_FreeCommandBuffers(
1612 VkDevice device,
1613 VkCommandPool commandPool,
1614 uint32_t commandBufferCount,
1615 const VkCommandBuffer *pCommandBuffers)
1616 {
1617 for (uint32_t i = 0; i < commandBufferCount; i++) {
1618 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1619
1620 if (cmd_buffer) {
1621 if (cmd_buffer->pool) {
1622 list_del(&cmd_buffer->pool_link);
1623 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1624 } else
1625 radv_cmd_buffer_destroy(cmd_buffer);
1626
1627 }
1628 }
1629 }
1630
1631 VkResult radv_ResetCommandBuffer(
1632 VkCommandBuffer commandBuffer,
1633 VkCommandBufferResetFlags flags)
1634 {
1635 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1636 radv_reset_cmd_buffer(cmd_buffer);
1637 return VK_SUCCESS;
1638 }
1639
1640 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1641 {
1642 struct radv_device *device = cmd_buffer->device;
1643 if (device->gfx_init) {
1644 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1645 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1646 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1647 radeon_emit(cmd_buffer->cs, va);
1648 radeon_emit(cmd_buffer->cs, (va >> 32) & 0xffff);
1649 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1650 } else
1651 si_init_config(cmd_buffer);
1652 }
1653
1654 VkResult radv_BeginCommandBuffer(
1655 VkCommandBuffer commandBuffer,
1656 const VkCommandBufferBeginInfo *pBeginInfo)
1657 {
1658 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1659 radv_reset_cmd_buffer(cmd_buffer);
1660
1661 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1662
1663 /* setup initial configuration into command buffer */
1664 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1665 switch (cmd_buffer->queue_family_index) {
1666 case RADV_QUEUE_GENERAL:
1667 emit_gfx_buffer_state(cmd_buffer);
1668 radv_set_db_count_control(cmd_buffer);
1669 break;
1670 case RADV_QUEUE_COMPUTE:
1671 si_init_compute(cmd_buffer);
1672 break;
1673 case RADV_QUEUE_TRANSFER:
1674 default:
1675 break;
1676 }
1677 }
1678
1679 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1680 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1681 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1682
1683 struct radv_subpass *subpass =
1684 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1685
1686 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1687 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1688 }
1689
1690 return VK_SUCCESS;
1691 }
1692
1693 void radv_CmdBindVertexBuffers(
1694 VkCommandBuffer commandBuffer,
1695 uint32_t firstBinding,
1696 uint32_t bindingCount,
1697 const VkBuffer* pBuffers,
1698 const VkDeviceSize* pOffsets)
1699 {
1700 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1701 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1702
1703 /* We have to defer setting up vertex buffer since we need the buffer
1704 * stride from the pipeline. */
1705
1706 assert(firstBinding + bindingCount < MAX_VBS);
1707 for (uint32_t i = 0; i < bindingCount; i++) {
1708 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1709 vb[firstBinding + i].offset = pOffsets[i];
1710 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1711 }
1712 }
1713
1714 void radv_CmdBindIndexBuffer(
1715 VkCommandBuffer commandBuffer,
1716 VkBuffer buffer,
1717 VkDeviceSize offset,
1718 VkIndexType indexType)
1719 {
1720 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1721
1722 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1723 cmd_buffer->state.index_offset = offset;
1724 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1725 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1726 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1727 }
1728
1729
1730 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1731 struct radv_descriptor_set *set,
1732 unsigned idx)
1733 {
1734 struct radeon_winsys *ws = cmd_buffer->device->ws;
1735
1736 cmd_buffer->state.descriptors[idx] = set;
1737 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1738 if (!set)
1739 return;
1740
1741 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1742 if (set->descriptors[j])
1743 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1744
1745 if(set->bo)
1746 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1747 }
1748
1749 void radv_CmdBindDescriptorSets(
1750 VkCommandBuffer commandBuffer,
1751 VkPipelineBindPoint pipelineBindPoint,
1752 VkPipelineLayout _layout,
1753 uint32_t firstSet,
1754 uint32_t descriptorSetCount,
1755 const VkDescriptorSet* pDescriptorSets,
1756 uint32_t dynamicOffsetCount,
1757 const uint32_t* pDynamicOffsets)
1758 {
1759 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1760 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1761 unsigned dyn_idx = 0;
1762
1763 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1764 cmd_buffer->cs, MAX_SETS * 4 * 6);
1765
1766 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1767 unsigned idx = i + firstSet;
1768 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1769 radv_bind_descriptor_set(cmd_buffer, set, idx);
1770
1771 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1772 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1773 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1774 assert(dyn_idx < dynamicOffsetCount);
1775
1776 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1777 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1778 dst[0] = va;
1779 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1780 dst[2] = range->size;
1781 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1782 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1783 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1784 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1785 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1786 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1787 cmd_buffer->push_constant_stages |=
1788 set->layout->dynamic_shader_stages;
1789 }
1790 }
1791
1792 assert(cmd_buffer->cs->cdw <= cdw_max);
1793 }
1794
1795 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1796 VkPipelineLayout layout,
1797 VkShaderStageFlags stageFlags,
1798 uint32_t offset,
1799 uint32_t size,
1800 const void* pValues)
1801 {
1802 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1803 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1804 cmd_buffer->push_constant_stages |= stageFlags;
1805 }
1806
1807 VkResult radv_EndCommandBuffer(
1808 VkCommandBuffer commandBuffer)
1809 {
1810 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1811
1812 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
1813 si_emit_cache_flush(cmd_buffer);
1814
1815 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1816 cmd_buffer->record_fail)
1817 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1818 return VK_SUCCESS;
1819 }
1820
1821 static void
1822 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1823 {
1824 struct radeon_winsys *ws = cmd_buffer->device->ws;
1825 struct radv_shader_variant *compute_shader;
1826 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1827 uint64_t va;
1828
1829 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1830 return;
1831
1832 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1833
1834 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1835 va = ws->buffer_get_va(compute_shader->bo);
1836
1837 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1838
1839 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1840 cmd_buffer->cs, 16);
1841
1842 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1843 radeon_emit(cmd_buffer->cs, va >> 8);
1844 radeon_emit(cmd_buffer->cs, va >> 40);
1845
1846 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1847 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1848 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1849
1850
1851 cmd_buffer->compute_scratch_size_needed =
1852 MAX2(cmd_buffer->compute_scratch_size_needed,
1853 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1854
1855 /* change these once we have scratch support */
1856 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1857 S_00B860_WAVES(pipeline->max_waves) |
1858 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1859
1860 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1861 radeon_emit(cmd_buffer->cs,
1862 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1863 radeon_emit(cmd_buffer->cs,
1864 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1865 radeon_emit(cmd_buffer->cs,
1866 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1867
1868 assert(cmd_buffer->cs->cdw <= cdw_max);
1869 }
1870
1871
1872 void radv_CmdBindPipeline(
1873 VkCommandBuffer commandBuffer,
1874 VkPipelineBindPoint pipelineBindPoint,
1875 VkPipeline _pipeline)
1876 {
1877 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1878 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1879
1880 for (unsigned i = 0; i < MAX_SETS; i++) {
1881 if (cmd_buffer->state.descriptors[i])
1882 cmd_buffer->state.descriptors_dirty |= (1 << i);
1883 }
1884
1885 switch (pipelineBindPoint) {
1886 case VK_PIPELINE_BIND_POINT_COMPUTE:
1887 cmd_buffer->state.compute_pipeline = pipeline;
1888 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
1889 break;
1890 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1891 cmd_buffer->state.pipeline = pipeline;
1892 cmd_buffer->state.vertex_descriptors_dirty = true;
1893 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1894 cmd_buffer->push_constant_stages |= pipeline->active_stages;
1895
1896 /* Apply the dynamic state from the pipeline */
1897 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
1898 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
1899 &pipeline->dynamic_state,
1900 pipeline->dynamic_state_mask);
1901
1902 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
1903 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
1904 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
1905 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
1906
1907 if (radv_pipeline_has_tess(pipeline))
1908 cmd_buffer->tess_rings_needed = true;
1909
1910 if (radv_pipeline_has_gs(pipeline)) {
1911 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1912 AC_UD_SCRATCH_RING_OFFSETS);
1913 if (cmd_buffer->ring_offsets_idx == -1)
1914 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
1915 else if (loc->sgpr_idx != -1)
1916 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
1917 }
1918 break;
1919 default:
1920 assert(!"invalid bind point");
1921 break;
1922 }
1923 }
1924
1925 void radv_CmdSetViewport(
1926 VkCommandBuffer commandBuffer,
1927 uint32_t firstViewport,
1928 uint32_t viewportCount,
1929 const VkViewport* pViewports)
1930 {
1931 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1932
1933 const uint32_t total_count = firstViewport + viewportCount;
1934 if (cmd_buffer->state.dynamic.viewport.count < total_count)
1935 cmd_buffer->state.dynamic.viewport.count = total_count;
1936
1937 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
1938 pViewports, viewportCount * sizeof(*pViewports));
1939
1940 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
1941 }
1942
1943 void radv_CmdSetScissor(
1944 VkCommandBuffer commandBuffer,
1945 uint32_t firstScissor,
1946 uint32_t scissorCount,
1947 const VkRect2D* pScissors)
1948 {
1949 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1950
1951 const uint32_t total_count = firstScissor + scissorCount;
1952 if (cmd_buffer->state.dynamic.scissor.count < total_count)
1953 cmd_buffer->state.dynamic.scissor.count = total_count;
1954
1955 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
1956 pScissors, scissorCount * sizeof(*pScissors));
1957 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1958 }
1959
1960 void radv_CmdSetLineWidth(
1961 VkCommandBuffer commandBuffer,
1962 float lineWidth)
1963 {
1964 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1965 cmd_buffer->state.dynamic.line_width = lineWidth;
1966 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1967 }
1968
1969 void radv_CmdSetDepthBias(
1970 VkCommandBuffer commandBuffer,
1971 float depthBiasConstantFactor,
1972 float depthBiasClamp,
1973 float depthBiasSlopeFactor)
1974 {
1975 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1976
1977 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
1978 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
1979 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
1980
1981 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1982 }
1983
1984 void radv_CmdSetBlendConstants(
1985 VkCommandBuffer commandBuffer,
1986 const float blendConstants[4])
1987 {
1988 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1989
1990 memcpy(cmd_buffer->state.dynamic.blend_constants,
1991 blendConstants, sizeof(float) * 4);
1992
1993 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
1994 }
1995
1996 void radv_CmdSetDepthBounds(
1997 VkCommandBuffer commandBuffer,
1998 float minDepthBounds,
1999 float maxDepthBounds)
2000 {
2001 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2002
2003 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2004 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2005
2006 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2007 }
2008
2009 void radv_CmdSetStencilCompareMask(
2010 VkCommandBuffer commandBuffer,
2011 VkStencilFaceFlags faceMask,
2012 uint32_t compareMask)
2013 {
2014 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2015
2016 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2017 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2018 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2019 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2020
2021 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2022 }
2023
2024 void radv_CmdSetStencilWriteMask(
2025 VkCommandBuffer commandBuffer,
2026 VkStencilFaceFlags faceMask,
2027 uint32_t writeMask)
2028 {
2029 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2030
2031 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2032 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2033 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2034 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2035
2036 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2037 }
2038
2039 void radv_CmdSetStencilReference(
2040 VkCommandBuffer commandBuffer,
2041 VkStencilFaceFlags faceMask,
2042 uint32_t reference)
2043 {
2044 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2045
2046 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2047 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2048 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2049 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2050
2051 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2052 }
2053
2054
2055 void radv_CmdExecuteCommands(
2056 VkCommandBuffer commandBuffer,
2057 uint32_t commandBufferCount,
2058 const VkCommandBuffer* pCmdBuffers)
2059 {
2060 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2061
2062 /* Emit pending flushes on primary prior to executing secondary */
2063 si_emit_cache_flush(primary);
2064
2065 for (uint32_t i = 0; i < commandBufferCount; i++) {
2066 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2067
2068 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2069 secondary->scratch_size_needed);
2070 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2071 secondary->compute_scratch_size_needed);
2072
2073 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2074 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2075 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2076 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2077 if (secondary->tess_rings_needed)
2078 primary->tess_rings_needed = true;
2079
2080 if (secondary->ring_offsets_idx != -1) {
2081 if (primary->ring_offsets_idx == -1)
2082 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2083 else
2084 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2085 }
2086 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2087 }
2088
2089 /* if we execute secondary we need to re-emit out pipelines */
2090 if (commandBufferCount) {
2091 primary->state.emitted_pipeline = NULL;
2092 primary->state.emitted_compute_pipeline = NULL;
2093 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2094 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2095 }
2096 }
2097
2098 VkResult radv_CreateCommandPool(
2099 VkDevice _device,
2100 const VkCommandPoolCreateInfo* pCreateInfo,
2101 const VkAllocationCallbacks* pAllocator,
2102 VkCommandPool* pCmdPool)
2103 {
2104 RADV_FROM_HANDLE(radv_device, device, _device);
2105 struct radv_cmd_pool *pool;
2106
2107 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2108 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2109 if (pool == NULL)
2110 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2111
2112 if (pAllocator)
2113 pool->alloc = *pAllocator;
2114 else
2115 pool->alloc = device->alloc;
2116
2117 list_inithead(&pool->cmd_buffers);
2118 list_inithead(&pool->free_cmd_buffers);
2119
2120 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2121
2122 *pCmdPool = radv_cmd_pool_to_handle(pool);
2123
2124 return VK_SUCCESS;
2125
2126 }
2127
2128 void radv_DestroyCommandPool(
2129 VkDevice _device,
2130 VkCommandPool commandPool,
2131 const VkAllocationCallbacks* pAllocator)
2132 {
2133 RADV_FROM_HANDLE(radv_device, device, _device);
2134 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2135
2136 if (!pool)
2137 return;
2138
2139 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2140 &pool->cmd_buffers, pool_link) {
2141 radv_cmd_buffer_destroy(cmd_buffer);
2142 }
2143
2144 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2145 &pool->free_cmd_buffers, pool_link) {
2146 radv_cmd_buffer_destroy(cmd_buffer);
2147 }
2148
2149 vk_free2(&device->alloc, pAllocator, pool);
2150 }
2151
2152 VkResult radv_ResetCommandPool(
2153 VkDevice device,
2154 VkCommandPool commandPool,
2155 VkCommandPoolResetFlags flags)
2156 {
2157 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2158
2159 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2160 &pool->cmd_buffers, pool_link) {
2161 radv_reset_cmd_buffer(cmd_buffer);
2162 }
2163
2164 return VK_SUCCESS;
2165 }
2166
2167 void radv_TrimCommandPoolKHR(
2168 VkDevice device,
2169 VkCommandPool commandPool,
2170 VkCommandPoolTrimFlagsKHR flags)
2171 {
2172 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2173
2174 if (!pool)
2175 return;
2176
2177 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2178 &pool->free_cmd_buffers, pool_link) {
2179 radv_cmd_buffer_destroy(cmd_buffer);
2180 }
2181 }
2182
2183 void radv_CmdBeginRenderPass(
2184 VkCommandBuffer commandBuffer,
2185 const VkRenderPassBeginInfo* pRenderPassBegin,
2186 VkSubpassContents contents)
2187 {
2188 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2189 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2190 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2191
2192 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2193 cmd_buffer->cs, 2048);
2194
2195 cmd_buffer->state.framebuffer = framebuffer;
2196 cmd_buffer->state.pass = pass;
2197 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2198 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2199
2200 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2201 assert(cmd_buffer->cs->cdw <= cdw_max);
2202
2203 radv_cmd_buffer_clear_subpass(cmd_buffer);
2204 }
2205
2206 void radv_CmdNextSubpass(
2207 VkCommandBuffer commandBuffer,
2208 VkSubpassContents contents)
2209 {
2210 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2211
2212 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2213
2214 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2215 2048);
2216
2217 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2218 radv_cmd_buffer_clear_subpass(cmd_buffer);
2219 }
2220
2221 void radv_CmdDraw(
2222 VkCommandBuffer commandBuffer,
2223 uint32_t vertexCount,
2224 uint32_t instanceCount,
2225 uint32_t firstVertex,
2226 uint32_t firstInstance)
2227 {
2228 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2229
2230 radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, vertexCount);
2231
2232 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2233
2234 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2235 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2236 if (loc->sgpr_idx != -1) {
2237 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2238 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2239 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2240 radeon_emit(cmd_buffer->cs, firstVertex);
2241 radeon_emit(cmd_buffer->cs, firstInstance);
2242 radeon_emit(cmd_buffer->cs, 0);
2243 }
2244 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2245 radeon_emit(cmd_buffer->cs, instanceCount);
2246
2247 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2248 radeon_emit(cmd_buffer->cs, vertexCount);
2249 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2250 S_0287F0_USE_OPAQUE(0));
2251
2252 assert(cmd_buffer->cs->cdw <= cdw_max);
2253
2254 radv_cmd_buffer_trace_emit(cmd_buffer);
2255 }
2256
2257 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2258 {
2259 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
2260
2261 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
2262 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
2263 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
2264 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2265 primitive_reset_index);
2266 }
2267 }
2268
2269 void radv_CmdDrawIndexed(
2270 VkCommandBuffer commandBuffer,
2271 uint32_t indexCount,
2272 uint32_t instanceCount,
2273 uint32_t firstIndex,
2274 int32_t vertexOffset,
2275 uint32_t firstInstance)
2276 {
2277 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2278 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2279 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2280 uint64_t index_va;
2281
2282 radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, indexCount);
2283 radv_emit_primitive_reset_index(cmd_buffer);
2284
2285 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2286
2287 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2288 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2289
2290 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2291 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2292 if (loc->sgpr_idx != -1) {
2293 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2294 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2295 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2296 radeon_emit(cmd_buffer->cs, vertexOffset);
2297 radeon_emit(cmd_buffer->cs, firstInstance);
2298 radeon_emit(cmd_buffer->cs, 0);
2299 }
2300 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2301 radeon_emit(cmd_buffer->cs, instanceCount);
2302
2303 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2304 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2305 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2306 radeon_emit(cmd_buffer->cs, index_max_size);
2307 radeon_emit(cmd_buffer->cs, index_va);
2308 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2309 radeon_emit(cmd_buffer->cs, indexCount);
2310 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2311
2312 assert(cmd_buffer->cs->cdw <= cdw_max);
2313 radv_cmd_buffer_trace_emit(cmd_buffer);
2314 }
2315
2316 static void
2317 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2318 VkBuffer _buffer,
2319 VkDeviceSize offset,
2320 VkBuffer _count_buffer,
2321 VkDeviceSize count_offset,
2322 uint32_t draw_count,
2323 uint32_t stride,
2324 bool indexed)
2325 {
2326 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2327 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2328 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2329 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2330 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2331 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2332 indirect_va += offset + buffer->offset;
2333 uint64_t count_va = 0;
2334
2335 if (count_buffer) {
2336 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2337 count_va += count_offset + count_buffer->offset;
2338 }
2339
2340 if (!draw_count)
2341 return;
2342
2343 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2344
2345 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2346 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2347 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2348 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2349 assert(loc->sgpr_idx != -1);
2350 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2351 radeon_emit(cs, 1);
2352 radeon_emit(cs, indirect_va);
2353 radeon_emit(cs, indirect_va >> 32);
2354
2355 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2356 PKT3_DRAW_INDIRECT_MULTI,
2357 8, false));
2358 radeon_emit(cs, 0);
2359 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2360 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2361 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2362 S_2C3_DRAW_INDEX_ENABLE(1) |
2363 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2364 radeon_emit(cs, draw_count); /* count */
2365 radeon_emit(cs, count_va); /* count_addr */
2366 radeon_emit(cs, count_va >> 32);
2367 radeon_emit(cs, stride); /* stride */
2368 radeon_emit(cs, di_src_sel);
2369 radv_cmd_buffer_trace_emit(cmd_buffer);
2370 }
2371
2372 static void
2373 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2374 VkBuffer buffer,
2375 VkDeviceSize offset,
2376 VkBuffer countBuffer,
2377 VkDeviceSize countBufferOffset,
2378 uint32_t maxDrawCount,
2379 uint32_t stride)
2380 {
2381 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2382 radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0);
2383
2384 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2385 cmd_buffer->cs, 14);
2386
2387 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2388 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2389
2390 assert(cmd_buffer->cs->cdw <= cdw_max);
2391 }
2392
2393 static void
2394 radv_cmd_draw_indexed_indirect_count(
2395 VkCommandBuffer commandBuffer,
2396 VkBuffer buffer,
2397 VkDeviceSize offset,
2398 VkBuffer countBuffer,
2399 VkDeviceSize countBufferOffset,
2400 uint32_t maxDrawCount,
2401 uint32_t stride)
2402 {
2403 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2404 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2405 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2406 uint64_t index_va;
2407 radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0);
2408 radv_emit_primitive_reset_index(cmd_buffer);
2409
2410 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2411 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2412
2413 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2414
2415 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2416 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2417
2418 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2419 radeon_emit(cmd_buffer->cs, index_va);
2420 radeon_emit(cmd_buffer->cs, index_va >> 32);
2421
2422 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2423 radeon_emit(cmd_buffer->cs, index_max_size);
2424
2425 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2426 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2427
2428 assert(cmd_buffer->cs->cdw <= cdw_max);
2429 }
2430
2431 void radv_CmdDrawIndirect(
2432 VkCommandBuffer commandBuffer,
2433 VkBuffer buffer,
2434 VkDeviceSize offset,
2435 uint32_t drawCount,
2436 uint32_t stride)
2437 {
2438 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2439 VK_NULL_HANDLE, 0, drawCount, stride);
2440 }
2441
2442 void radv_CmdDrawIndexedIndirect(
2443 VkCommandBuffer commandBuffer,
2444 VkBuffer buffer,
2445 VkDeviceSize offset,
2446 uint32_t drawCount,
2447 uint32_t stride)
2448 {
2449 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2450 VK_NULL_HANDLE, 0, drawCount, stride);
2451 }
2452
2453 void radv_CmdDrawIndirectCountAMD(
2454 VkCommandBuffer commandBuffer,
2455 VkBuffer buffer,
2456 VkDeviceSize offset,
2457 VkBuffer countBuffer,
2458 VkDeviceSize countBufferOffset,
2459 uint32_t maxDrawCount,
2460 uint32_t stride)
2461 {
2462 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2463 countBuffer, countBufferOffset,
2464 maxDrawCount, stride);
2465 }
2466
2467 void radv_CmdDrawIndexedIndirectCountAMD(
2468 VkCommandBuffer commandBuffer,
2469 VkBuffer buffer,
2470 VkDeviceSize offset,
2471 VkBuffer countBuffer,
2472 VkDeviceSize countBufferOffset,
2473 uint32_t maxDrawCount,
2474 uint32_t stride)
2475 {
2476 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2477 countBuffer, countBufferOffset,
2478 maxDrawCount, stride);
2479 }
2480
2481 static void
2482 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2483 {
2484 radv_emit_compute_pipeline(cmd_buffer);
2485 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2486 VK_SHADER_STAGE_COMPUTE_BIT);
2487 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2488 VK_SHADER_STAGE_COMPUTE_BIT);
2489 si_emit_cache_flush(cmd_buffer);
2490 }
2491
2492 void radv_CmdDispatch(
2493 VkCommandBuffer commandBuffer,
2494 uint32_t x,
2495 uint32_t y,
2496 uint32_t z)
2497 {
2498 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2499
2500 radv_flush_compute_state(cmd_buffer);
2501
2502 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2503
2504 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2505 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2506 if (loc->sgpr_idx != -1) {
2507 assert(!loc->indirect);
2508 assert(loc->num_sgprs == 3);
2509 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2510 radeon_emit(cmd_buffer->cs, x);
2511 radeon_emit(cmd_buffer->cs, y);
2512 radeon_emit(cmd_buffer->cs, z);
2513 }
2514
2515 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2516 PKT3_SHADER_TYPE_S(1));
2517 radeon_emit(cmd_buffer->cs, x);
2518 radeon_emit(cmd_buffer->cs, y);
2519 radeon_emit(cmd_buffer->cs, z);
2520 radeon_emit(cmd_buffer->cs, 1);
2521
2522 assert(cmd_buffer->cs->cdw <= cdw_max);
2523 radv_cmd_buffer_trace_emit(cmd_buffer);
2524 }
2525
2526 void radv_CmdDispatchIndirect(
2527 VkCommandBuffer commandBuffer,
2528 VkBuffer _buffer,
2529 VkDeviceSize offset)
2530 {
2531 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2532 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2533 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2534 va += buffer->offset + offset;
2535
2536 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2537
2538 radv_flush_compute_state(cmd_buffer);
2539
2540 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2541 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2542 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2543 if (loc->sgpr_idx != -1) {
2544 for (unsigned i = 0; i < 3; ++i) {
2545 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2546 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2547 COPY_DATA_DST_SEL(COPY_DATA_REG));
2548 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2549 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2550 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2551 radeon_emit(cmd_buffer->cs, 0);
2552 }
2553 }
2554
2555 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2556 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2557 PKT3_SHADER_TYPE_S(1));
2558 radeon_emit(cmd_buffer->cs, va);
2559 radeon_emit(cmd_buffer->cs, va >> 32);
2560 radeon_emit(cmd_buffer->cs, 1);
2561 } else {
2562 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2563 PKT3_SHADER_TYPE_S(1));
2564 radeon_emit(cmd_buffer->cs, 1);
2565 radeon_emit(cmd_buffer->cs, va);
2566 radeon_emit(cmd_buffer->cs, va >> 32);
2567
2568 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2569 PKT3_SHADER_TYPE_S(1));
2570 radeon_emit(cmd_buffer->cs, 0);
2571 radeon_emit(cmd_buffer->cs, 1);
2572 }
2573
2574 assert(cmd_buffer->cs->cdw <= cdw_max);
2575 radv_cmd_buffer_trace_emit(cmd_buffer);
2576 }
2577
2578 void radv_unaligned_dispatch(
2579 struct radv_cmd_buffer *cmd_buffer,
2580 uint32_t x,
2581 uint32_t y,
2582 uint32_t z)
2583 {
2584 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2585 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2586 uint32_t blocks[3], remainder[3];
2587
2588 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2589 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2590 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2591
2592 /* If aligned, these should be an entire block size, not 0 */
2593 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2594 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2595 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2596
2597 radv_flush_compute_state(cmd_buffer);
2598
2599 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2600
2601 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2602 radeon_emit(cmd_buffer->cs,
2603 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2604 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2605 radeon_emit(cmd_buffer->cs,
2606 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2607 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2608 radeon_emit(cmd_buffer->cs,
2609 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2610 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2611
2612 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2613 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2614 if (loc->sgpr_idx != -1) {
2615 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2616 radeon_emit(cmd_buffer->cs, blocks[0]);
2617 radeon_emit(cmd_buffer->cs, blocks[1]);
2618 radeon_emit(cmd_buffer->cs, blocks[2]);
2619 }
2620 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2621 PKT3_SHADER_TYPE_S(1));
2622 radeon_emit(cmd_buffer->cs, blocks[0]);
2623 radeon_emit(cmd_buffer->cs, blocks[1]);
2624 radeon_emit(cmd_buffer->cs, blocks[2]);
2625 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2626 S_00B800_PARTIAL_TG_EN(1));
2627
2628 assert(cmd_buffer->cs->cdw <= cdw_max);
2629 radv_cmd_buffer_trace_emit(cmd_buffer);
2630 }
2631
2632 void radv_CmdEndRenderPass(
2633 VkCommandBuffer commandBuffer)
2634 {
2635 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2636
2637 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2638
2639 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2640
2641 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2642 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2643 radv_handle_subpass_image_transition(cmd_buffer,
2644 (VkAttachmentReference){i, layout});
2645 }
2646
2647 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2648
2649 cmd_buffer->state.pass = NULL;
2650 cmd_buffer->state.subpass = NULL;
2651 cmd_buffer->state.attachments = NULL;
2652 cmd_buffer->state.framebuffer = NULL;
2653 }
2654
2655
2656 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2657 struct radv_image *image,
2658 const VkImageSubresourceRange *range)
2659 {
2660 assert(range->baseMipLevel == 0);
2661 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
2662 unsigned layer_count = radv_get_layerCount(image, range);
2663 uint64_t size = image->surface.htile_slice_size * layer_count;
2664 uint64_t offset = image->offset + image->htile_offset +
2665 image->surface.htile_slice_size * range->baseArrayLayer;
2666
2667 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2668 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2669
2670 radv_fill_buffer(cmd_buffer, image->bo, offset, size, 0xffffffff);
2671
2672 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2673 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2674 RADV_CMD_FLAG_INV_VMEM_L1 |
2675 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2676 }
2677
2678 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2679 struct radv_image *image,
2680 VkImageLayout src_layout,
2681 VkImageLayout dst_layout,
2682 const VkImageSubresourceRange *range,
2683 VkImageAspectFlags pending_clears)
2684 {
2685 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2686 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2687 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2688 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2689 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2690 /* The clear will initialize htile. */
2691 return;
2692 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2693 radv_layout_has_htile(image, dst_layout)) {
2694 /* TODO: merge with the clear if applicable */
2695 radv_initialize_htile(cmd_buffer, image, range);
2696 } else if (!radv_layout_has_htile(image, src_layout) &&
2697 radv_layout_has_htile(image, dst_layout)) {
2698 radv_initialize_htile(cmd_buffer, image, range);
2699 } else if ((radv_layout_has_htile(image, src_layout) &&
2700 !radv_layout_has_htile(image, dst_layout)) ||
2701 (radv_layout_is_htile_compressed(image, src_layout) &&
2702 !radv_layout_is_htile_compressed(image, dst_layout))) {
2703 VkImageSubresourceRange local_range = *range;
2704 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2705 local_range.baseMipLevel = 0;
2706 local_range.levelCount = 1;
2707
2708 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2709 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2710
2711 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
2712
2713 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2714 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2715 }
2716 }
2717
2718 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2719 struct radv_image *image, uint32_t value)
2720 {
2721 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2722 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2723
2724 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2725 image->cmask.size, value);
2726
2727 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2728 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2729 RADV_CMD_FLAG_INV_VMEM_L1 |
2730 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2731 }
2732
2733 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2734 struct radv_image *image,
2735 VkImageLayout src_layout,
2736 VkImageLayout dst_layout,
2737 unsigned src_queue_mask,
2738 unsigned dst_queue_mask,
2739 const VkImageSubresourceRange *range,
2740 VkImageAspectFlags pending_clears)
2741 {
2742 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2743 if (image->fmask.size)
2744 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2745 else
2746 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2747 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2748 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2749 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
2750 }
2751 }
2752
2753 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2754 struct radv_image *image, uint32_t value)
2755 {
2756
2757 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2758 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2759
2760 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2761 image->surface.dcc_size, value);
2762
2763 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2764 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2765 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2766 RADV_CMD_FLAG_INV_VMEM_L1 |
2767 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2768 }
2769
2770 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2771 struct radv_image *image,
2772 VkImageLayout src_layout,
2773 VkImageLayout dst_layout,
2774 unsigned src_queue_mask,
2775 unsigned dst_queue_mask,
2776 const VkImageSubresourceRange *range,
2777 VkImageAspectFlags pending_clears)
2778 {
2779 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2780 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2781 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2782 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2783 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
2784 }
2785 }
2786
2787 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2788 struct radv_image *image,
2789 VkImageLayout src_layout,
2790 VkImageLayout dst_layout,
2791 uint32_t src_family,
2792 uint32_t dst_family,
2793 const VkImageSubresourceRange *range,
2794 VkImageAspectFlags pending_clears)
2795 {
2796 if (image->exclusive && src_family != dst_family) {
2797 /* This is an acquire or a release operation and there will be
2798 * a corresponding release/acquire. Do the transition in the
2799 * most flexible queue. */
2800
2801 assert(src_family == cmd_buffer->queue_family_index ||
2802 dst_family == cmd_buffer->queue_family_index);
2803
2804 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
2805 return;
2806
2807 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
2808 (src_family == RADV_QUEUE_GENERAL ||
2809 dst_family == RADV_QUEUE_GENERAL))
2810 return;
2811 }
2812
2813 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
2814 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
2815
2816 if (image->surface.htile_size)
2817 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2818 dst_layout, range, pending_clears);
2819
2820 if (image->cmask.size)
2821 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2822 dst_layout, src_queue_mask,
2823 dst_queue_mask, range,
2824 pending_clears);
2825
2826 if (image->surface.dcc_size)
2827 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2828 dst_layout, src_queue_mask,
2829 dst_queue_mask, range,
2830 pending_clears);
2831 }
2832
2833 void radv_CmdPipelineBarrier(
2834 VkCommandBuffer commandBuffer,
2835 VkPipelineStageFlags srcStageMask,
2836 VkPipelineStageFlags destStageMask,
2837 VkBool32 byRegion,
2838 uint32_t memoryBarrierCount,
2839 const VkMemoryBarrier* pMemoryBarriers,
2840 uint32_t bufferMemoryBarrierCount,
2841 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2842 uint32_t imageMemoryBarrierCount,
2843 const VkImageMemoryBarrier* pImageMemoryBarriers)
2844 {
2845 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2846 enum radv_cmd_flush_bits src_flush_bits = 0;
2847 enum radv_cmd_flush_bits dst_flush_bits = 0;
2848
2849 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2850 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
2851 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
2852 NULL);
2853 }
2854
2855 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2856 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
2857 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
2858 NULL);
2859 }
2860
2861 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2862 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2863 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
2864 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
2865 image);
2866 }
2867
2868 radv_stage_flush(cmd_buffer, srcStageMask);
2869 cmd_buffer->state.flush_bits |= src_flush_bits;
2870
2871 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2872 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2873 radv_handle_image_transition(cmd_buffer, image,
2874 pImageMemoryBarriers[i].oldLayout,
2875 pImageMemoryBarriers[i].newLayout,
2876 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2877 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2878 &pImageMemoryBarriers[i].subresourceRange,
2879 0);
2880 }
2881
2882 cmd_buffer->state.flush_bits |= dst_flush_bits;
2883 }
2884
2885
2886 static void write_event(struct radv_cmd_buffer *cmd_buffer,
2887 struct radv_event *event,
2888 VkPipelineStageFlags stageMask,
2889 unsigned value)
2890 {
2891 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2892 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2893
2894 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2895
2896 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
2897
2898 /* TODO: this is overkill. Probably should figure something out from
2899 * the stage mask. */
2900
2901 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
2902 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2903 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2904 EVENT_INDEX(5));
2905 radeon_emit(cs, va);
2906 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2907 radeon_emit(cs, 2);
2908 radeon_emit(cs, 0);
2909 }
2910
2911 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2912 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2913 EVENT_INDEX(5));
2914 radeon_emit(cs, va);
2915 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2916 radeon_emit(cs, value);
2917 radeon_emit(cs, 0);
2918
2919 assert(cmd_buffer->cs->cdw <= cdw_max);
2920 }
2921
2922 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
2923 VkEvent _event,
2924 VkPipelineStageFlags stageMask)
2925 {
2926 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2927 RADV_FROM_HANDLE(radv_event, event, _event);
2928
2929 write_event(cmd_buffer, event, stageMask, 1);
2930 }
2931
2932 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
2933 VkEvent _event,
2934 VkPipelineStageFlags stageMask)
2935 {
2936 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2937 RADV_FROM_HANDLE(radv_event, event, _event);
2938
2939 write_event(cmd_buffer, event, stageMask, 0);
2940 }
2941
2942 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
2943 uint32_t eventCount,
2944 const VkEvent* pEvents,
2945 VkPipelineStageFlags srcStageMask,
2946 VkPipelineStageFlags dstStageMask,
2947 uint32_t memoryBarrierCount,
2948 const VkMemoryBarrier* pMemoryBarriers,
2949 uint32_t bufferMemoryBarrierCount,
2950 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2951 uint32_t imageMemoryBarrierCount,
2952 const VkImageMemoryBarrier* pImageMemoryBarriers)
2953 {
2954 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2955 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2956
2957 for (unsigned i = 0; i < eventCount; ++i) {
2958 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
2959 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2960
2961 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2962
2963 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
2964
2965 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
2966 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
2967 radeon_emit(cs, va);
2968 radeon_emit(cs, va >> 32);
2969 radeon_emit(cs, 1); /* reference value */
2970 radeon_emit(cs, 0xffffffff); /* mask */
2971 radeon_emit(cs, 4); /* poll interval */
2972
2973 assert(cmd_buffer->cs->cdw <= cdw_max);
2974 }
2975
2976
2977 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2978 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2979
2980 radv_handle_image_transition(cmd_buffer, image,
2981 pImageMemoryBarriers[i].oldLayout,
2982 pImageMemoryBarriers[i].newLayout,
2983 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2984 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2985 &pImageMemoryBarriers[i].subresourceRange,
2986 0);
2987 }
2988
2989 /* TODO: figure out how to do memory barriers without waiting */
2990 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
2991 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2992 RADV_CMD_FLAG_INV_VMEM_L1 |
2993 RADV_CMD_FLAG_INV_SMEM_L1;
2994 }