2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
57 VkImageLayout dst_layout
,
60 const VkImageSubresourceRange
*range
);
62 const struct radv_dynamic_state default_dynamic_state
= {
75 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
80 .stencil_compare_mask
= {
84 .stencil_write_mask
= {
88 .stencil_reference
= {
95 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
96 const struct radv_dynamic_state
*src
)
98 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
99 uint32_t copy_mask
= src
->mask
;
100 uint32_t dest_mask
= 0;
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
105 dest
->viewport
.count
= src
->viewport
.count
;
106 dest
->scissor
.count
= src
->scissor
.count
;
107 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
109 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
110 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
111 src
->viewport
.count
* sizeof(VkViewport
))) {
112 typed_memcpy(dest
->viewport
.viewports
,
113 src
->viewport
.viewports
,
114 src
->viewport
.count
);
115 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
119 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
120 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
121 src
->scissor
.count
* sizeof(VkRect2D
))) {
122 typed_memcpy(dest
->scissor
.scissors
,
123 src
->scissor
.scissors
, src
->scissor
.count
);
124 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
128 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
129 if (dest
->line_width
!= src
->line_width
) {
130 dest
->line_width
= src
->line_width
;
131 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
135 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
136 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
137 sizeof(src
->depth_bias
))) {
138 dest
->depth_bias
= src
->depth_bias
;
139 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
143 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
144 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
145 sizeof(src
->blend_constants
))) {
146 typed_memcpy(dest
->blend_constants
,
147 src
->blend_constants
, 4);
148 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
152 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
153 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
154 sizeof(src
->depth_bounds
))) {
155 dest
->depth_bounds
= src
->depth_bounds
;
156 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
160 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
161 if (memcmp(&dest
->stencil_compare_mask
,
162 &src
->stencil_compare_mask
,
163 sizeof(src
->stencil_compare_mask
))) {
164 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
165 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
169 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
170 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
171 sizeof(src
->stencil_write_mask
))) {
172 dest
->stencil_write_mask
= src
->stencil_write_mask
;
173 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
177 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
178 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
179 sizeof(src
->stencil_reference
))) {
180 dest
->stencil_reference
= src
->stencil_reference
;
181 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
185 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
186 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
187 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
188 typed_memcpy(dest
->discard_rectangle
.rectangles
,
189 src
->discard_rectangle
.rectangles
,
190 src
->discard_rectangle
.count
);
191 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
195 cmd_buffer
->state
.dirty
|= dest_mask
;
199 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
200 struct radv_pipeline
*pipeline
)
202 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
203 struct radv_shader_info
*info
;
205 if (!pipeline
->streamout_shader
)
208 info
= &pipeline
->streamout_shader
->info
.info
;
209 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
210 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
212 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
217 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
218 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
221 enum ring_type
radv_queue_family_to_ring(int f
) {
223 case RADV_QUEUE_GENERAL
:
225 case RADV_QUEUE_COMPUTE
:
227 case RADV_QUEUE_TRANSFER
:
230 unreachable("Unknown queue family");
234 static VkResult
radv_create_cmd_buffer(
235 struct radv_device
* device
,
236 struct radv_cmd_pool
* pool
,
237 VkCommandBufferLevel level
,
238 VkCommandBuffer
* pCommandBuffer
)
240 struct radv_cmd_buffer
*cmd_buffer
;
242 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
244 if (cmd_buffer
== NULL
)
245 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
247 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
248 cmd_buffer
->device
= device
;
249 cmd_buffer
->pool
= pool
;
250 cmd_buffer
->level
= level
;
253 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
254 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
257 /* Init the pool_link so we can safely call list_del when we destroy
260 list_inithead(&cmd_buffer
->pool_link
);
261 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
264 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
266 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
267 if (!cmd_buffer
->cs
) {
268 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
269 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
272 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
274 list_inithead(&cmd_buffer
->upload
.list
);
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
282 list_del(&cmd_buffer
->pool_link
);
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
285 &cmd_buffer
->upload
.list
, list
) {
286 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
291 if (cmd_buffer
->upload
.upload_bo
)
292 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
293 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
295 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
296 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
298 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
302 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
304 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
306 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
307 &cmd_buffer
->upload
.list
, list
) {
308 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
313 cmd_buffer
->push_constant_stages
= 0;
314 cmd_buffer
->scratch_size_needed
= 0;
315 cmd_buffer
->compute_scratch_size_needed
= 0;
316 cmd_buffer
->esgs_ring_size_needed
= 0;
317 cmd_buffer
->gsvs_ring_size_needed
= 0;
318 cmd_buffer
->tess_rings_needed
= false;
319 cmd_buffer
->sample_positions_needed
= false;
321 if (cmd_buffer
->upload
.upload_bo
)
322 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
323 cmd_buffer
->upload
.upload_bo
);
324 cmd_buffer
->upload
.offset
= 0;
326 cmd_buffer
->record_result
= VK_SUCCESS
;
328 memset(cmd_buffer
->vertex_bindings
, 0, sizeof(cmd_buffer
->vertex_bindings
));
330 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
331 cmd_buffer
->descriptors
[i
].dirty
= 0;
332 cmd_buffer
->descriptors
[i
].valid
= 0;
333 cmd_buffer
->descriptors
[i
].push_dirty
= false;
336 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
337 cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
338 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
339 unsigned fence_offset
, eop_bug_offset
;
342 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 8, &fence_offset
,
345 cmd_buffer
->gfx9_fence_va
=
346 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
347 cmd_buffer
->gfx9_fence_va
+= fence_offset
;
349 /* Allocate a buffer for the EOP bug on GFX9. */
350 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 8,
351 &eop_bug_offset
, &fence_ptr
);
352 cmd_buffer
->gfx9_eop_bug_va
=
353 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
354 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
357 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
359 return cmd_buffer
->record_result
;
363 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
367 struct radeon_winsys_bo
*bo
;
368 struct radv_cmd_buffer_upload
*upload
;
369 struct radv_device
*device
= cmd_buffer
->device
;
371 new_size
= MAX2(min_needed
, 16 * 1024);
372 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
374 bo
= device
->ws
->buffer_create(device
->ws
,
377 RADEON_FLAG_CPU_ACCESS
|
378 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
380 RADV_BO_PRIORITY_UPLOAD_BUFFER
);
383 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
387 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
388 if (cmd_buffer
->upload
.upload_bo
) {
389 upload
= malloc(sizeof(*upload
));
392 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
393 device
->ws
->buffer_destroy(bo
);
397 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
398 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
401 cmd_buffer
->upload
.upload_bo
= bo
;
402 cmd_buffer
->upload
.size
= new_size
;
403 cmd_buffer
->upload
.offset
= 0;
404 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
406 if (!cmd_buffer
->upload
.map
) {
407 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
415 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
418 unsigned *out_offset
,
421 assert(util_is_power_of_two_nonzero(alignment
));
423 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
424 if (offset
+ size
> cmd_buffer
->upload
.size
) {
425 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
430 *out_offset
= offset
;
431 *ptr
= cmd_buffer
->upload
.map
+ offset
;
433 cmd_buffer
->upload
.offset
= offset
+ size
;
438 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
439 unsigned size
, unsigned alignment
,
440 const void *data
, unsigned *out_offset
)
444 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
445 out_offset
, (void **)&ptr
))
449 memcpy(ptr
, data
, size
);
455 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
456 unsigned count
, const uint32_t *data
)
458 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
460 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
462 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
463 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
464 S_370_WR_CONFIRM(1) |
465 S_370_ENGINE_SEL(V_370_ME
));
467 radeon_emit(cs
, va
>> 32);
468 radeon_emit_array(cs
, data
, count
);
471 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
473 struct radv_device
*device
= cmd_buffer
->device
;
474 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
477 va
= radv_buffer_get_va(device
->trace_bo
);
478 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
481 ++cmd_buffer
->state
.trace_id
;
482 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
483 &cmd_buffer
->state
.trace_id
);
485 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
487 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
488 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
492 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
493 enum radv_cmd_flush_bits flags
)
495 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
496 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
497 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
499 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
501 /* Force wait for graphics or compute engines to be idle. */
502 si_cs_emit_cache_flush(cmd_buffer
->cs
,
503 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
504 &cmd_buffer
->gfx9_fence_idx
,
505 cmd_buffer
->gfx9_fence_va
,
506 radv_cmd_buffer_uses_mec(cmd_buffer
),
507 flags
, cmd_buffer
->gfx9_eop_bug_va
);
510 if (unlikely(cmd_buffer
->device
->trace_bo
))
511 radv_cmd_buffer_trace_emit(cmd_buffer
);
515 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
516 struct radv_pipeline
*pipeline
, enum ring_type ring
)
518 struct radv_device
*device
= cmd_buffer
->device
;
522 va
= radv_buffer_get_va(device
->trace_bo
);
532 assert(!"invalid ring type");
535 data
[0] = (uintptr_t)pipeline
;
536 data
[1] = (uintptr_t)pipeline
>> 32;
538 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
541 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
542 VkPipelineBindPoint bind_point
,
543 struct radv_descriptor_set
*set
,
546 struct radv_descriptor_state
*descriptors_state
=
547 radv_get_descriptors_state(cmd_buffer
, bind_point
);
549 descriptors_state
->sets
[idx
] = set
;
551 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
552 descriptors_state
->dirty
|= (1u << idx
);
556 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
557 VkPipelineBindPoint bind_point
)
559 struct radv_descriptor_state
*descriptors_state
=
560 radv_get_descriptors_state(cmd_buffer
, bind_point
);
561 struct radv_device
*device
= cmd_buffer
->device
;
562 uint32_t data
[MAX_SETS
* 2] = {};
565 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
567 for_each_bit(i
, descriptors_state
->valid
) {
568 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
569 data
[i
* 2] = (uintptr_t)set
;
570 data
[i
* 2 + 1] = (uintptr_t)set
>> 32;
573 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
576 struct radv_userdata_info
*
577 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
578 gl_shader_stage stage
,
581 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
582 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
586 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
587 struct radv_pipeline
*pipeline
,
588 gl_shader_stage stage
,
589 int idx
, uint64_t va
)
591 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
592 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
593 if (loc
->sgpr_idx
== -1)
596 assert(loc
->num_sgprs
== 1);
598 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
599 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
603 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
604 struct radv_pipeline
*pipeline
,
605 struct radv_descriptor_state
*descriptors_state
,
606 gl_shader_stage stage
)
608 struct radv_device
*device
= cmd_buffer
->device
;
609 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
610 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
611 struct radv_userdata_locations
*locs
=
612 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
613 unsigned mask
= locs
->descriptor_sets_enabled
;
615 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
620 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
622 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
623 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
625 radv_emit_shader_pointer_head(cs
, sh_offset
, count
, true);
626 for (int i
= 0; i
< count
; i
++) {
627 struct radv_descriptor_set
*set
=
628 descriptors_state
->sets
[start
+ i
];
630 radv_emit_shader_pointer_body(device
, cs
, set
->va
, true);
636 radv_emit_inline_push_consts(struct radv_cmd_buffer
*cmd_buffer
,
637 struct radv_pipeline
*pipeline
,
638 gl_shader_stage stage
,
639 int idx
, int count
, uint32_t *values
)
641 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
642 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
643 if (loc
->sgpr_idx
== -1)
646 assert(loc
->num_sgprs
== count
);
648 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, count
);
649 radeon_emit_array(cmd_buffer
->cs
, values
, count
);
653 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
654 struct radv_pipeline
*pipeline
)
656 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
657 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
658 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
660 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
)
661 cmd_buffer
->sample_positions_needed
= true;
663 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
666 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
667 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
668 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
670 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
672 radv_emit_default_sample_locations(cmd_buffer
->cs
, num_samples
);
674 /* GFX9: Flush DFSM when the AA mode changes. */
675 if (cmd_buffer
->device
->dfsm_allowed
) {
676 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
677 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
680 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
684 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
685 struct radv_shader_variant
*shader
)
692 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
694 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
698 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
699 struct radv_pipeline
*pipeline
,
700 bool vertex_stage_only
)
702 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
703 uint32_t mask
= state
->prefetch_L2_mask
;
705 if (vertex_stage_only
) {
706 /* Fast prefetch path for starting draws as soon as possible.
708 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
709 RADV_PREFETCH_VBO_DESCRIPTORS
);
712 if (mask
& RADV_PREFETCH_VS
)
713 radv_emit_shader_prefetch(cmd_buffer
,
714 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
716 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
717 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
719 if (mask
& RADV_PREFETCH_TCS
)
720 radv_emit_shader_prefetch(cmd_buffer
,
721 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
723 if (mask
& RADV_PREFETCH_TES
)
724 radv_emit_shader_prefetch(cmd_buffer
,
725 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
727 if (mask
& RADV_PREFETCH_GS
) {
728 radv_emit_shader_prefetch(cmd_buffer
,
729 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
730 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
733 if (mask
& RADV_PREFETCH_PS
)
734 radv_emit_shader_prefetch(cmd_buffer
,
735 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
737 state
->prefetch_L2_mask
&= ~mask
;
741 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
743 if (!cmd_buffer
->device
->physical_device
->rbplus_allowed
)
746 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
747 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
748 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
750 unsigned sx_ps_downconvert
= 0;
751 unsigned sx_blend_opt_epsilon
= 0;
752 unsigned sx_blend_opt_control
= 0;
754 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
755 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
756 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
757 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
761 int idx
= subpass
->color_attachments
[i
].attachment
;
762 struct radv_color_buffer_info
*cb
= &framebuffer
->attachments
[idx
].cb
;
764 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
765 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
766 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
767 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
769 bool has_alpha
, has_rgb
;
771 /* Set if RGB and A are present. */
772 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
774 if (format
== V_028C70_COLOR_8
||
775 format
== V_028C70_COLOR_16
||
776 format
== V_028C70_COLOR_32
)
777 has_rgb
= !has_alpha
;
781 /* Check the colormask and export format. */
782 if (!(colormask
& 0x7))
784 if (!(colormask
& 0x8))
787 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
792 /* Disable value checking for disabled channels. */
794 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
796 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
798 /* Enable down-conversion for 32bpp and smaller formats. */
800 case V_028C70_COLOR_8
:
801 case V_028C70_COLOR_8_8
:
802 case V_028C70_COLOR_8_8_8_8
:
803 /* For 1 and 2-channel formats, use the superset thereof. */
804 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
805 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
806 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
807 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
808 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
812 case V_028C70_COLOR_5_6_5
:
813 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
814 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
815 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
819 case V_028C70_COLOR_1_5_5_5
:
820 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
821 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
822 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
826 case V_028C70_COLOR_4_4_4_4
:
827 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
828 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
829 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
833 case V_028C70_COLOR_32
:
834 if (swap
== V_028C70_SWAP_STD
&&
835 spi_format
== V_028714_SPI_SHADER_32_R
)
836 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
837 else if (swap
== V_028C70_SWAP_ALT_REV
&&
838 spi_format
== V_028714_SPI_SHADER_32_AR
)
839 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
842 case V_028C70_COLOR_16
:
843 case V_028C70_COLOR_16_16
:
844 /* For 1-channel formats, use the superset thereof. */
845 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
846 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
847 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
848 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
849 if (swap
== V_028C70_SWAP_STD
||
850 swap
== V_028C70_SWAP_STD_REV
)
851 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
853 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
857 case V_028C70_COLOR_10_11_11
:
858 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
859 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
860 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
864 case V_028C70_COLOR_2_10_10_10
:
865 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
866 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
867 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
873 for (unsigned i
= subpass
->color_count
; i
< 8; ++i
) {
874 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
875 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
877 /* TODO: avoid redundantly setting context registers */
878 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
879 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
880 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
881 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
883 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
887 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
889 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
891 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
894 radv_update_multisample_state(cmd_buffer
, pipeline
);
896 cmd_buffer
->scratch_size_needed
=
897 MAX2(cmd_buffer
->scratch_size_needed
,
898 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
900 if (!cmd_buffer
->state
.emitted_pipeline
||
901 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
902 pipeline
->graphics
.can_use_guardband
)
903 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
905 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
907 if (!cmd_buffer
->state
.emitted_pipeline
||
908 cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.cdw
!= pipeline
->ctx_cs
.cdw
||
909 cmd_buffer
->state
.emitted_pipeline
->ctx_cs_hash
!= pipeline
->ctx_cs_hash
||
910 memcmp(cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.buf
,
911 pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
* 4)) {
912 radeon_emit_array(cmd_buffer
->cs
, pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
);
913 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
916 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
917 if (!pipeline
->shaders
[i
])
920 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
921 pipeline
->shaders
[i
]->bo
);
924 if (radv_pipeline_has_gs(pipeline
))
925 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
926 pipeline
->gs_copy_shader
->bo
);
928 if (unlikely(cmd_buffer
->device
->trace_bo
))
929 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
931 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
933 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
937 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
939 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
940 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
944 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
946 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
948 si_write_scissors(cmd_buffer
->cs
, 0, count
,
949 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
950 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
951 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
953 cmd_buffer
->state
.context_roll_without_scissor_emitted
= false;
957 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
959 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
962 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
963 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
964 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
965 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
966 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
967 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
968 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
973 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
975 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
977 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
978 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
982 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
984 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
986 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
987 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
991 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
993 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
995 radeon_set_context_reg_seq(cmd_buffer
->cs
,
996 R_028430_DB_STENCILREFMASK
, 2);
997 radeon_emit(cmd_buffer
->cs
,
998 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
999 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1000 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1001 S_028430_STENCILOPVAL(1));
1002 radeon_emit(cmd_buffer
->cs
,
1003 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1004 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1005 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1006 S_028434_STENCILOPVAL_BF(1));
1010 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1012 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1014 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1015 fui(d
->depth_bounds
.min
));
1016 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1017 fui(d
->depth_bounds
.max
));
1021 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
1023 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1024 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1025 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1028 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1029 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1030 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1031 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1032 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1033 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1034 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1038 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1040 struct radv_attachment_info
*att
,
1041 struct radv_image
*image
,
1042 VkImageLayout layout
)
1044 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
;
1045 struct radv_color_buffer_info
*cb
= &att
->cb
;
1046 uint32_t cb_color_info
= cb
->cb_color_info
;
1048 if (!radv_layout_dcc_compressed(image
, layout
,
1049 radv_image_queue_family_mask(image
,
1050 cmd_buffer
->queue_family_index
,
1051 cmd_buffer
->queue_family_index
))) {
1052 cb_color_info
&= C_028C70_DCC_ENABLE
;
1055 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1056 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1057 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1058 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1059 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1060 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1061 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1062 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1063 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1064 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1065 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1066 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1067 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1069 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1070 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1071 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1073 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1076 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1077 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1078 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1079 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1080 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1081 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1082 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1083 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1084 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1085 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1086 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1087 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1089 if (is_vi
) { /* DCC BASE */
1090 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1094 if (radv_image_has_dcc(image
)) {
1095 /* Drawing with DCC enabled also compresses colorbuffers. */
1096 radv_update_dcc_metadata(cmd_buffer
, image
, true);
1101 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1102 struct radv_ds_buffer_info
*ds
,
1103 struct radv_image
*image
, VkImageLayout layout
,
1104 bool requires_cond_exec
)
1106 uint32_t db_z_info
= ds
->db_z_info
;
1107 uint32_t db_z_info_reg
;
1109 if (!radv_image_is_tc_compat_htile(image
))
1112 if (!radv_layout_has_htile(image
, layout
,
1113 radv_image_queue_family_mask(image
,
1114 cmd_buffer
->queue_family_index
,
1115 cmd_buffer
->queue_family_index
))) {
1116 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1119 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1121 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1122 db_z_info_reg
= R_028038_DB_Z_INFO
;
1124 db_z_info_reg
= R_028040_DB_Z_INFO
;
1127 /* When we don't know the last fast clear value we need to emit a
1128 * conditional packet that will eventually skip the following
1129 * SET_CONTEXT_REG packet.
1131 if (requires_cond_exec
) {
1132 uint64_t va
= radv_buffer_get_va(image
->bo
);
1133 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1135 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_EXEC
, 3, 0));
1136 radeon_emit(cmd_buffer
->cs
, va
);
1137 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1138 radeon_emit(cmd_buffer
->cs
, 0);
1139 radeon_emit(cmd_buffer
->cs
, 3); /* SET_CONTEXT_REG size */
1142 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1146 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1147 struct radv_ds_buffer_info
*ds
,
1148 struct radv_image
*image
,
1149 VkImageLayout layout
)
1151 uint32_t db_z_info
= ds
->db_z_info
;
1152 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1154 if (!radv_layout_has_htile(image
, layout
,
1155 radv_image_queue_family_mask(image
,
1156 cmd_buffer
->queue_family_index
,
1157 cmd_buffer
->queue_family_index
))) {
1158 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1159 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1162 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1163 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1166 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1167 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1168 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1169 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1170 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1172 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1173 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1174 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1175 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1176 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1177 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1178 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1179 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1180 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1181 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1182 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1184 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1185 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1186 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1188 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1190 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1191 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1192 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1193 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1194 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1195 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1196 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1197 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1198 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1199 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1203 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1204 radv_update_zrange_precision(cmd_buffer
, ds
, image
, layout
, true);
1206 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1207 ds
->pa_su_poly_offset_db_fmt_cntl
);
1211 * Update the fast clear depth/stencil values if the image is bound as a
1212 * depth/stencil buffer.
1215 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1216 struct radv_image
*image
,
1217 VkClearDepthStencilValue ds_clear_value
,
1218 VkImageAspectFlags aspects
)
1220 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1221 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1222 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1223 struct radv_attachment_info
*att
;
1226 if (!framebuffer
|| !subpass
)
1229 if (!subpass
->depth_stencil_attachment
)
1232 att_idx
= subpass
->depth_stencil_attachment
->attachment
;
1233 att
= &framebuffer
->attachments
[att_idx
];
1234 if (att
->attachment
->image
!= image
)
1237 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1238 radeon_emit(cs
, ds_clear_value
.stencil
);
1239 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1241 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1242 * only needed when clearing Z to 0.0.
1244 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1245 ds_clear_value
.depth
== 0.0) {
1246 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1248 radv_update_zrange_precision(cmd_buffer
, &att
->ds
, image
,
1252 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1256 * Set the clear depth/stencil values to the image's metadata.
1259 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1260 struct radv_image
*image
,
1261 VkClearDepthStencilValue ds_clear_value
,
1262 VkImageAspectFlags aspects
)
1264 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1265 uint64_t va
= radv_buffer_get_va(image
->bo
);
1266 unsigned reg_offset
= 0, reg_count
= 0;
1268 va
+= image
->offset
+ image
->clear_value_offset
;
1270 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1276 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1279 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, cmd_buffer
->state
.predicating
));
1280 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1281 S_370_WR_CONFIRM(1) |
1282 S_370_ENGINE_SEL(V_370_PFP
));
1283 radeon_emit(cs
, va
);
1284 radeon_emit(cs
, va
>> 32);
1285 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1286 radeon_emit(cs
, ds_clear_value
.stencil
);
1287 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1288 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1292 * Update the TC-compat metadata value for this image.
1295 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1296 struct radv_image
*image
,
1299 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1300 uint64_t va
= radv_buffer_get_va(image
->bo
);
1301 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1303 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, cmd_buffer
->state
.predicating
));
1304 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1305 S_370_WR_CONFIRM(1) |
1306 S_370_ENGINE_SEL(V_370_PFP
));
1307 radeon_emit(cs
, va
);
1308 radeon_emit(cs
, va
>> 32);
1309 radeon_emit(cs
, value
);
1313 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1314 struct radv_image
*image
,
1315 VkClearDepthStencilValue ds_clear_value
)
1317 uint64_t va
= radv_buffer_get_va(image
->bo
);
1318 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1321 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1322 * depth clear value is 0.0f.
1324 cond_val
= ds_clear_value
.depth
== 0.0f
? UINT_MAX
: 0;
1326 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, cond_val
);
1330 * Update the clear depth/stencil values for this image.
1333 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1334 struct radv_image
*image
,
1335 VkClearDepthStencilValue ds_clear_value
,
1336 VkImageAspectFlags aspects
)
1338 assert(radv_image_has_htile(image
));
1340 radv_set_ds_clear_metadata(cmd_buffer
, image
, ds_clear_value
, aspects
);
1342 if (radv_image_is_tc_compat_htile(image
) &&
1343 (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
1344 radv_update_tc_compat_zrange_metadata(cmd_buffer
, image
,
1348 radv_update_bound_fast_clear_ds(cmd_buffer
, image
, ds_clear_value
,
1353 * Load the clear depth/stencil values from the image's metadata.
1356 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1357 struct radv_image
*image
)
1359 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1360 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1361 uint64_t va
= radv_buffer_get_va(image
->bo
);
1362 unsigned reg_offset
= 0, reg_count
= 0;
1364 va
+= image
->offset
+ image
->clear_value_offset
;
1366 if (!radv_image_has_htile(image
))
1369 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1375 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1378 uint32_t reg
= R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
;
1380 if (cmd_buffer
->device
->physical_device
->has_load_ctx_reg_pkt
) {
1381 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, 0));
1382 radeon_emit(cs
, va
);
1383 radeon_emit(cs
, va
>> 32);
1384 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1385 radeon_emit(cs
, reg_count
);
1387 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1388 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1389 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1390 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1391 radeon_emit(cs
, va
);
1392 radeon_emit(cs
, va
>> 32);
1393 radeon_emit(cs
, reg
>> 2);
1396 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1402 * With DCC some colors don't require CMASK elimination before being
1403 * used as a texture. This sets a predicate value to determine if the
1404 * cmask eliminate is required.
1407 radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1408 struct radv_image
*image
, bool value
)
1410 uint64_t pred_val
= value
;
1411 uint64_t va
= radv_buffer_get_va(image
->bo
);
1412 va
+= image
->offset
+ image
->fce_pred_offset
;
1414 assert(radv_image_has_dcc(image
));
1416 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1417 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1418 S_370_WR_CONFIRM(1) |
1419 S_370_ENGINE_SEL(V_370_PFP
));
1420 radeon_emit(cmd_buffer
->cs
, va
);
1421 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1422 radeon_emit(cmd_buffer
->cs
, pred_val
);
1423 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1427 * Update the DCC predicate to reflect the compression state.
1430 radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1431 struct radv_image
*image
, bool value
)
1433 uint64_t pred_val
= value
;
1434 uint64_t va
= radv_buffer_get_va(image
->bo
);
1435 va
+= image
->offset
+ image
->dcc_pred_offset
;
1437 assert(radv_image_has_dcc(image
));
1439 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1440 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1441 S_370_WR_CONFIRM(1) |
1442 S_370_ENGINE_SEL(V_370_PFP
));
1443 radeon_emit(cmd_buffer
->cs
, va
);
1444 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1445 radeon_emit(cmd_buffer
->cs
, pred_val
);
1446 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1450 * Update the fast clear color values if the image is bound as a color buffer.
1453 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1454 struct radv_image
*image
,
1456 uint32_t color_values
[2])
1458 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1459 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1460 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1461 struct radv_attachment_info
*att
;
1464 if (!framebuffer
|| !subpass
)
1467 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1468 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1471 att
= &framebuffer
->attachments
[att_idx
];
1472 if (att
->attachment
->image
!= image
)
1475 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1476 radeon_emit(cs
, color_values
[0]);
1477 radeon_emit(cs
, color_values
[1]);
1479 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1483 * Set the clear color values to the image's metadata.
1486 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1487 struct radv_image
*image
,
1488 uint32_t color_values
[2])
1490 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1491 uint64_t va
= radv_buffer_get_va(image
->bo
);
1493 va
+= image
->offset
+ image
->clear_value_offset
;
1495 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1497 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 4, cmd_buffer
->state
.predicating
));
1498 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1499 S_370_WR_CONFIRM(1) |
1500 S_370_ENGINE_SEL(V_370_PFP
));
1501 radeon_emit(cs
, va
);
1502 radeon_emit(cs
, va
>> 32);
1503 radeon_emit(cs
, color_values
[0]);
1504 radeon_emit(cs
, color_values
[1]);
1508 * Update the clear color values for this image.
1511 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1512 struct radv_image
*image
,
1514 uint32_t color_values
[2])
1516 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1518 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
1520 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1525 * Load the clear color values from the image's metadata.
1528 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1529 struct radv_image
*image
,
1532 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1533 uint64_t va
= radv_buffer_get_va(image
->bo
);
1535 va
+= image
->offset
+ image
->clear_value_offset
;
1537 if (!radv_image_has_cmask(image
) && !radv_image_has_dcc(image
))
1540 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1542 if (cmd_buffer
->device
->physical_device
->has_load_ctx_reg_pkt
) {
1543 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, cmd_buffer
->state
.predicating
));
1544 radeon_emit(cs
, va
);
1545 radeon_emit(cs
, va
>> 32);
1546 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1549 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1550 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1551 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1552 COPY_DATA_COUNT_SEL
);
1553 radeon_emit(cs
, va
);
1554 radeon_emit(cs
, va
>> 32);
1555 radeon_emit(cs
, reg
>> 2);
1558 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1564 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1567 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1568 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1569 unsigned num_bpp64_colorbufs
= 0;
1571 /* this may happen for inherited secondary recording */
1575 for (i
= 0; i
< 8; ++i
) {
1576 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1577 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1578 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1582 int idx
= subpass
->color_attachments
[i
].attachment
;
1583 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1584 struct radv_image
*image
= att
->attachment
->image
;
1585 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
1587 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1589 assert(att
->attachment
->aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
| VK_IMAGE_ASPECT_PLANE_0_BIT
|
1590 VK_IMAGE_ASPECT_PLANE_1_BIT
| VK_IMAGE_ASPECT_PLANE_2_BIT
));
1591 radv_emit_fb_color_state(cmd_buffer
, i
, att
, image
, layout
);
1593 radv_load_color_clear_metadata(cmd_buffer
, image
, i
);
1595 if (image
->planes
[0].surface
.bpe
>= 8)
1596 num_bpp64_colorbufs
++;
1599 if (subpass
->depth_stencil_attachment
) {
1600 int idx
= subpass
->depth_stencil_attachment
->attachment
;
1601 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1602 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1603 struct radv_image
*image
= att
->attachment
->image
;
1604 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1605 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1606 cmd_buffer
->queue_family_index
,
1607 cmd_buffer
->queue_family_index
);
1608 /* We currently don't support writing decompressed HTILE */
1609 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1610 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1612 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1614 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1615 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1616 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1618 radv_load_ds_clear_metadata(cmd_buffer
, image
);
1620 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1621 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1623 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1625 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1626 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1628 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1629 S_028208_BR_X(framebuffer
->width
) |
1630 S_028208_BR_Y(framebuffer
->height
));
1632 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
) {
1633 uint8_t watermark
= 4; /* Default value for GFX8. */
1635 /* For optimal DCC performance. */
1636 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1637 if (num_bpp64_colorbufs
>= 5) {
1644 radeon_set_context_reg(cmd_buffer
->cs
, R_028424_CB_DCC_CONTROL
,
1645 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1646 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
));
1649 if (cmd_buffer
->device
->dfsm_allowed
) {
1650 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1651 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1654 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
1658 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1660 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1661 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1663 if (state
->index_type
!= state
->last_index_type
) {
1664 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1665 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
1666 2, state
->index_type
);
1668 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1669 radeon_emit(cs
, state
->index_type
);
1672 state
->last_index_type
= state
->index_type
;
1675 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
1676 radeon_emit(cs
, state
->index_va
);
1677 radeon_emit(cs
, state
->index_va
>> 32);
1679 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1680 radeon_emit(cs
, state
->max_index_count
);
1682 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
1685 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1687 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
1688 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1689 uint32_t pa_sc_mode_cntl_1
=
1690 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
1691 uint32_t db_count_control
;
1693 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1694 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1695 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1696 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1697 has_perfect_queries
) {
1698 /* Re-enable out-of-order rasterization if the
1699 * bound pipeline supports it and if it's has
1700 * been disabled before starting any perfect
1701 * occlusion queries.
1703 radeon_set_context_reg(cmd_buffer
->cs
,
1704 R_028A4C_PA_SC_MODE_CNTL_1
,
1708 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1710 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1711 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
1713 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1715 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
1716 S_028004_SAMPLE_RATE(sample_rate
) |
1717 S_028004_ZPASS_ENABLE(1) |
1718 S_028004_SLICE_EVEN_ENABLE(1) |
1719 S_028004_SLICE_ODD_ENABLE(1);
1721 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1722 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1723 has_perfect_queries
) {
1724 /* If the bound pipeline has enabled
1725 * out-of-order rasterization, we should
1726 * disable it before starting any perfect
1727 * occlusion queries.
1729 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
1731 radeon_set_context_reg(cmd_buffer
->cs
,
1732 R_028A4C_PA_SC_MODE_CNTL_1
,
1736 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1737 S_028004_SAMPLE_RATE(sample_rate
);
1741 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1743 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1747 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1749 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
1751 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1752 radv_emit_viewport(cmd_buffer
);
1754 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
1755 !cmd_buffer
->device
->physical_device
->has_scissor_bug
)
1756 radv_emit_scissor(cmd_buffer
);
1758 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
1759 radv_emit_line_width(cmd_buffer
);
1761 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1762 radv_emit_blend_constants(cmd_buffer
);
1764 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1765 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1766 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
1767 radv_emit_stencil(cmd_buffer
);
1769 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
1770 radv_emit_depth_bounds(cmd_buffer
);
1772 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
1773 radv_emit_depth_bias(cmd_buffer
);
1775 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
1776 radv_emit_discard_rectangle(cmd_buffer
);
1778 cmd_buffer
->state
.dirty
&= ~states
;
1782 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1783 VkPipelineBindPoint bind_point
)
1785 struct radv_descriptor_state
*descriptors_state
=
1786 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1787 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
1790 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
1795 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1796 set
->va
+= bo_offset
;
1800 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
1801 VkPipelineBindPoint bind_point
)
1803 struct radv_descriptor_state
*descriptors_state
=
1804 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1805 uint32_t size
= MAX_SETS
* 4;
1809 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1810 256, &offset
, &ptr
))
1813 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1814 uint32_t *uptr
= ((uint32_t *)ptr
) + i
;
1815 uint64_t set_va
= 0;
1816 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
1817 if (descriptors_state
->valid
& (1u << i
))
1819 uptr
[0] = set_va
& 0xffffffff;
1822 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1825 if (cmd_buffer
->state
.pipeline
) {
1826 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1827 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1828 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1830 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1831 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1832 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1834 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1835 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1836 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1838 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1839 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1840 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1842 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1843 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1844 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1847 if (cmd_buffer
->state
.compute_pipeline
)
1848 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1849 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1853 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1854 VkShaderStageFlags stages
)
1856 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
1857 VK_PIPELINE_BIND_POINT_COMPUTE
:
1858 VK_PIPELINE_BIND_POINT_GRAPHICS
;
1859 struct radv_descriptor_state
*descriptors_state
=
1860 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1861 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1862 bool flush_indirect_descriptors
;
1864 if (!descriptors_state
->dirty
)
1867 if (descriptors_state
->push_dirty
)
1868 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
1870 flush_indirect_descriptors
=
1871 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
1872 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
1873 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
1874 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
1876 if (flush_indirect_descriptors
)
1877 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
1879 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1881 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1883 if (cmd_buffer
->state
.pipeline
) {
1884 radv_foreach_stage(stage
, stages
) {
1885 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
1888 radv_emit_descriptor_pointers(cmd_buffer
,
1889 cmd_buffer
->state
.pipeline
,
1890 descriptors_state
, stage
);
1894 if (cmd_buffer
->state
.compute_pipeline
&&
1895 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
1896 radv_emit_descriptor_pointers(cmd_buffer
,
1897 cmd_buffer
->state
.compute_pipeline
,
1899 MESA_SHADER_COMPUTE
);
1902 descriptors_state
->dirty
= 0;
1903 descriptors_state
->push_dirty
= false;
1905 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1907 if (unlikely(cmd_buffer
->device
->trace_bo
))
1908 radv_save_descriptors(cmd_buffer
, bind_point
);
1912 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1913 VkShaderStageFlags stages
)
1915 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
1916 ? cmd_buffer
->state
.compute_pipeline
1917 : cmd_buffer
->state
.pipeline
;
1918 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
1919 VK_PIPELINE_BIND_POINT_COMPUTE
:
1920 VK_PIPELINE_BIND_POINT_GRAPHICS
;
1921 struct radv_descriptor_state
*descriptors_state
=
1922 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1923 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1924 struct radv_shader_variant
*shader
, *prev_shader
;
1925 bool need_push_constants
= false;
1930 stages
&= cmd_buffer
->push_constant_stages
;
1932 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1935 radv_foreach_stage(stage
, stages
) {
1936 if (!pipeline
->shaders
[stage
])
1939 need_push_constants
|= pipeline
->shaders
[stage
]->info
.info
.loads_push_constants
;
1940 need_push_constants
|= pipeline
->shaders
[stage
]->info
.info
.loads_dynamic_offsets
;
1942 uint8_t base
= pipeline
->shaders
[stage
]->info
.info
.base_inline_push_consts
;
1943 uint8_t count
= pipeline
->shaders
[stage
]->info
.info
.num_inline_push_consts
;
1945 radv_emit_inline_push_consts(cmd_buffer
, pipeline
, stage
,
1946 AC_UD_INLINE_PUSH_CONSTANTS
,
1948 (uint32_t *)&cmd_buffer
->push_constants
[base
* 4]);
1951 if (need_push_constants
) {
1952 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1953 16 * layout
->dynamic_offset_count
,
1954 256, &offset
, &ptr
))
1957 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1958 memcpy((char*)ptr
+ layout
->push_constant_size
,
1959 descriptors_state
->dynamic_buffers
,
1960 16 * layout
->dynamic_offset_count
);
1962 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1965 MAYBE_UNUSED
unsigned cdw_max
=
1966 radeon_check_space(cmd_buffer
->device
->ws
,
1967 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1970 radv_foreach_stage(stage
, stages
) {
1971 shader
= radv_get_shader(pipeline
, stage
);
1973 /* Avoid redundantly emitting the address for merged stages. */
1974 if (shader
&& shader
!= prev_shader
) {
1975 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1976 AC_UD_PUSH_CONSTANTS
, va
);
1978 prev_shader
= shader
;
1981 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1984 cmd_buffer
->push_constant_stages
&= ~stages
;
1988 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1989 bool pipeline_is_dirty
)
1991 if ((pipeline_is_dirty
||
1992 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
1993 cmd_buffer
->state
.pipeline
->num_vertex_bindings
&&
1994 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.has_vertex_buffers
) {
1995 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
1999 uint32_t count
= cmd_buffer
->state
.pipeline
->num_vertex_bindings
;
2002 /* allocate some descriptor state for vertex buffers */
2003 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
2004 &vb_offset
, &vb_ptr
))
2007 for (i
= 0; i
< count
; i
++) {
2008 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
2010 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[i
].buffer
;
2011 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[i
];
2016 va
= radv_buffer_get_va(buffer
->bo
);
2018 offset
= cmd_buffer
->vertex_bindings
[i
].offset
;
2019 va
+= offset
+ buffer
->offset
;
2021 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
2022 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= GFX7
&& stride
)
2023 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
2025 desc
[2] = buffer
->size
- offset
;
2026 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2027 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2028 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2029 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2030 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
2031 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2034 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2037 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2038 AC_UD_VS_VERTEX_BUFFERS
, va
);
2040 cmd_buffer
->state
.vb_va
= va
;
2041 cmd_buffer
->state
.vb_size
= count
* 16;
2042 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
2044 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
2048 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
2050 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2051 struct radv_userdata_info
*loc
;
2054 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2055 if (!radv_get_shader(pipeline
, stage
))
2058 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
2059 AC_UD_STREAMOUT_BUFFERS
);
2060 if (loc
->sgpr_idx
== -1)
2063 base_reg
= pipeline
->user_data_0
[stage
];
2065 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2066 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2069 if (pipeline
->gs_copy_shader
) {
2070 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
2071 if (loc
->sgpr_idx
!= -1) {
2072 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2074 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2075 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2081 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
2083 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
2084 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
2085 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
2090 /* Allocate some descriptor state for streamout buffers. */
2091 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
2092 MAX_SO_BUFFERS
* 16, 256,
2093 &so_offset
, &so_ptr
))
2096 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
2097 struct radv_buffer
*buffer
= sb
[i
].buffer
;
2098 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
2100 if (!(so
->enabled_mask
& (1 << i
)))
2103 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
2107 /* Set the descriptor.
2109 * On GFX8, the format must be non-INVALID, otherwise
2110 * the buffer will be considered not bound and store
2111 * instructions will be no-ops.
2114 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2115 desc
[2] = 0xffffffff;
2116 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2117 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2118 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2119 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2120 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2123 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2126 radv_emit_streamout_buffers(cmd_buffer
, va
);
2129 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
2133 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
2135 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
2136 radv_flush_streamout_descriptors(cmd_buffer
);
2137 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2138 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2141 struct radv_draw_info
{
2143 * Number of vertices.
2148 * Index of the first vertex.
2150 int32_t vertex_offset
;
2153 * First instance id.
2155 uint32_t first_instance
;
2158 * Number of instances.
2160 uint32_t instance_count
;
2163 * First index (indexed draws only).
2165 uint32_t first_index
;
2168 * Whether it's an indexed draw.
2173 * Indirect draw parameters resource.
2175 struct radv_buffer
*indirect
;
2176 uint64_t indirect_offset
;
2180 * Draw count parameters resource.
2182 struct radv_buffer
*count_buffer
;
2183 uint64_t count_buffer_offset
;
2186 * Stream output parameters resource.
2188 struct radv_buffer
*strmout_buffer
;
2189 uint64_t strmout_buffer_offset
;
2193 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
,
2194 const struct radv_draw_info
*draw_info
)
2196 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2197 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2198 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2199 uint32_t ia_multi_vgt_param
;
2200 int32_t primitive_reset_en
;
2203 ia_multi_vgt_param
=
2204 si_get_ia_multi_vgt_param(cmd_buffer
, draw_info
->instance_count
> 1,
2205 draw_info
->indirect
,
2206 !!draw_info
->strmout_buffer
,
2207 draw_info
->indirect
? 0 : draw_info
->count
);
2209 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2210 if (info
->chip_class
>= GFX9
) {
2211 radeon_set_uconfig_reg_idx(cs
,
2212 R_030960_IA_MULTI_VGT_PARAM
,
2213 4, ia_multi_vgt_param
);
2214 } else if (info
->chip_class
>= GFX7
) {
2215 radeon_set_context_reg_idx(cs
,
2216 R_028AA8_IA_MULTI_VGT_PARAM
,
2217 1, ia_multi_vgt_param
);
2219 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2220 ia_multi_vgt_param
);
2222 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
2225 /* Primitive restart. */
2226 primitive_reset_en
=
2227 draw_info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
;
2229 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
2230 state
->last_primitive_reset_en
= primitive_reset_en
;
2231 if (info
->chip_class
>= GFX9
) {
2232 radeon_set_uconfig_reg(cs
,
2233 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
2234 primitive_reset_en
);
2236 radeon_set_context_reg(cs
,
2237 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
2238 primitive_reset_en
);
2242 if (primitive_reset_en
) {
2243 uint32_t primitive_reset_index
=
2244 state
->index_type
? 0xffffffffu
: 0xffffu
;
2246 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
2247 radeon_set_context_reg(cs
,
2248 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
2249 primitive_reset_index
);
2250 state
->last_primitive_reset_index
= primitive_reset_index
;
2254 if (draw_info
->strmout_buffer
) {
2255 uint64_t va
= radv_buffer_get_va(draw_info
->strmout_buffer
->bo
);
2257 va
+= draw_info
->strmout_buffer
->offset
+
2258 draw_info
->strmout_buffer_offset
;
2260 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
2263 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2264 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2265 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2266 COPY_DATA_WR_CONFIRM
);
2267 radeon_emit(cs
, va
);
2268 radeon_emit(cs
, va
>> 32);
2269 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
2270 radeon_emit(cs
, 0); /* unused */
2272 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, draw_info
->strmout_buffer
->bo
);
2276 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
2277 VkPipelineStageFlags src_stage_mask
)
2279 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
2280 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2281 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2282 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2283 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
2286 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
2287 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
2288 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
2289 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
2290 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2291 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2292 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
2293 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2294 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2295 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
2296 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
2297 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
2298 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
2299 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
2300 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
2301 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
2302 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
2306 static enum radv_cmd_flush_bits
2307 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2308 VkAccessFlags src_flags
,
2309 struct radv_image
*image
)
2311 bool flush_CB_meta
= true, flush_DB_meta
= true;
2312 enum radv_cmd_flush_bits flush_bits
= 0;
2316 if (!radv_image_has_CB_metadata(image
))
2317 flush_CB_meta
= false;
2318 if (!radv_image_has_htile(image
))
2319 flush_DB_meta
= false;
2322 for_each_bit(b
, src_flags
) {
2323 switch ((VkAccessFlagBits
)(1 << b
)) {
2324 case VK_ACCESS_SHADER_WRITE_BIT
:
2325 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
2326 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2327 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2329 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2330 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2332 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2334 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2335 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2337 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2339 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2340 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2341 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2342 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2345 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2347 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2356 static enum radv_cmd_flush_bits
2357 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2358 VkAccessFlags dst_flags
,
2359 struct radv_image
*image
)
2361 bool flush_CB_meta
= true, flush_DB_meta
= true;
2362 enum radv_cmd_flush_bits flush_bits
= 0;
2363 bool flush_CB
= true, flush_DB
= true;
2364 bool image_is_coherent
= false;
2368 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
2373 if (!radv_image_has_CB_metadata(image
))
2374 flush_CB_meta
= false;
2375 if (!radv_image_has_htile(image
))
2376 flush_DB_meta
= false;
2378 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2379 if (image
->info
.samples
== 1 &&
2380 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
2381 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
2382 !vk_format_is_stencil(image
->vk_format
)) {
2383 /* Single-sample color and single-sample depth
2384 * (not stencil) are coherent with shaders on
2387 image_is_coherent
= true;
2392 for_each_bit(b
, dst_flags
) {
2393 switch ((VkAccessFlagBits
)(1 << b
)) {
2394 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2395 case VK_ACCESS_INDEX_READ_BIT
:
2396 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2398 case VK_ACCESS_UNIFORM_READ_BIT
:
2399 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
2401 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2402 case VK_ACCESS_TRANSFER_READ_BIT
:
2403 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2404 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
2405 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2407 case VK_ACCESS_SHADER_READ_BIT
:
2408 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
;
2410 if (!image_is_coherent
)
2411 flush_bits
|= RADV_CMD_FLAG_INV_GLOBAL_L2
;
2413 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2415 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2417 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2419 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2421 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2423 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2432 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2433 const struct radv_subpass_barrier
*barrier
)
2435 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2437 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2438 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2442 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2443 struct radv_subpass_attachment att
)
2445 unsigned idx
= att
.attachment
;
2446 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
2447 VkImageSubresourceRange range
;
2448 range
.aspectMask
= 0;
2449 range
.baseMipLevel
= view
->base_mip
;
2450 range
.levelCount
= 1;
2451 range
.baseArrayLayer
= view
->base_layer
;
2452 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2454 if (cmd_buffer
->state
.subpass
&& cmd_buffer
->state
.subpass
->view_mask
) {
2455 /* If the current subpass uses multiview, the driver might have
2456 * performed a fast color/depth clear to the whole image
2457 * (including all layers). To make sure the driver will
2458 * decompress the image correctly (if needed), we have to
2459 * account for the "real" number of layers. If the view mask is
2460 * sparse, this will decompress more layers than needed.
2462 range
.layerCount
= util_last_bit(cmd_buffer
->state
.subpass
->view_mask
);
2465 radv_handle_image_transition(cmd_buffer
,
2467 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2468 att
.layout
, 0, 0, &range
);
2470 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2476 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2477 const struct radv_subpass
*subpass
)
2479 cmd_buffer
->state
.subpass
= subpass
;
2481 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2485 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
2486 struct radv_render_pass
*pass
,
2487 const VkRenderPassBeginInfo
*info
)
2489 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2491 if (pass
->attachment_count
== 0) {
2492 state
->attachments
= NULL
;
2496 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2497 pass
->attachment_count
*
2498 sizeof(state
->attachments
[0]),
2499 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2500 if (state
->attachments
== NULL
) {
2501 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2502 return cmd_buffer
->record_result
;
2505 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
2506 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
2507 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
2508 VkImageAspectFlags clear_aspects
= 0;
2510 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2511 /* color attachment */
2512 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2513 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
2516 /* depthstencil attachment */
2517 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2518 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2519 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
2520 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2521 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
2522 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2524 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2525 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2526 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2530 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
2531 state
->attachments
[i
].cleared_views
= 0;
2532 if (clear_aspects
&& info
) {
2533 assert(info
->clearValueCount
> i
);
2534 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
2537 state
->attachments
[i
].current_layout
= att
->initial_layout
;
2543 VkResult
radv_AllocateCommandBuffers(
2545 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
2546 VkCommandBuffer
*pCommandBuffers
)
2548 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2549 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
2551 VkResult result
= VK_SUCCESS
;
2554 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
2556 if (!list_empty(&pool
->free_cmd_buffers
)) {
2557 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
2559 list_del(&cmd_buffer
->pool_link
);
2560 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
2562 result
= radv_reset_cmd_buffer(cmd_buffer
);
2563 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2564 cmd_buffer
->level
= pAllocateInfo
->level
;
2566 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
2568 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
2569 &pCommandBuffers
[i
]);
2571 if (result
!= VK_SUCCESS
)
2575 if (result
!= VK_SUCCESS
) {
2576 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
2577 i
, pCommandBuffers
);
2579 /* From the Vulkan 1.0.66 spec:
2581 * "vkAllocateCommandBuffers can be used to create multiple
2582 * command buffers. If the creation of any of those command
2583 * buffers fails, the implementation must destroy all
2584 * successfully created command buffer objects from this
2585 * command, set all entries of the pCommandBuffers array to
2586 * NULL and return the error."
2588 memset(pCommandBuffers
, 0,
2589 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
2595 void radv_FreeCommandBuffers(
2597 VkCommandPool commandPool
,
2598 uint32_t commandBufferCount
,
2599 const VkCommandBuffer
*pCommandBuffers
)
2601 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2602 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
2605 if (cmd_buffer
->pool
) {
2606 list_del(&cmd_buffer
->pool_link
);
2607 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
2609 radv_cmd_buffer_destroy(cmd_buffer
);
2615 VkResult
radv_ResetCommandBuffer(
2616 VkCommandBuffer commandBuffer
,
2617 VkCommandBufferResetFlags flags
)
2619 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2620 return radv_reset_cmd_buffer(cmd_buffer
);
2623 VkResult
radv_BeginCommandBuffer(
2624 VkCommandBuffer commandBuffer
,
2625 const VkCommandBufferBeginInfo
*pBeginInfo
)
2627 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2628 VkResult result
= VK_SUCCESS
;
2630 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
2631 /* If the command buffer has already been resetted with
2632 * vkResetCommandBuffer, no need to do it again.
2634 result
= radv_reset_cmd_buffer(cmd_buffer
);
2635 if (result
!= VK_SUCCESS
)
2639 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
2640 cmd_buffer
->state
.last_primitive_reset_en
= -1;
2641 cmd_buffer
->state
.last_index_type
= -1;
2642 cmd_buffer
->state
.last_num_instances
= -1;
2643 cmd_buffer
->state
.last_vertex_offset
= -1;
2644 cmd_buffer
->state
.last_first_instance
= -1;
2645 cmd_buffer
->state
.predication_type
= -1;
2646 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
2648 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
2649 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
2650 assert(pBeginInfo
->pInheritanceInfo
);
2651 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
2652 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
2654 struct radv_subpass
*subpass
=
2655 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
2657 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
2658 if (result
!= VK_SUCCESS
)
2661 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
2664 if (unlikely(cmd_buffer
->device
->trace_bo
)) {
2665 struct radv_device
*device
= cmd_buffer
->device
;
2667 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
,
2670 radv_cmd_buffer_trace_emit(cmd_buffer
);
2673 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
2678 void radv_CmdBindVertexBuffers(
2679 VkCommandBuffer commandBuffer
,
2680 uint32_t firstBinding
,
2681 uint32_t bindingCount
,
2682 const VkBuffer
* pBuffers
,
2683 const VkDeviceSize
* pOffsets
)
2685 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2686 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
2687 bool changed
= false;
2689 /* We have to defer setting up vertex buffer since we need the buffer
2690 * stride from the pipeline. */
2692 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
2693 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2694 uint32_t idx
= firstBinding
+ i
;
2697 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
2698 vb
[idx
].offset
!= pOffsets
[i
])) {
2702 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2703 vb
[idx
].offset
= pOffsets
[i
];
2705 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2706 vb
[idx
].buffer
->bo
);
2710 /* No state changes. */
2714 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
2717 void radv_CmdBindIndexBuffer(
2718 VkCommandBuffer commandBuffer
,
2720 VkDeviceSize offset
,
2721 VkIndexType indexType
)
2723 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2724 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2726 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
2727 cmd_buffer
->state
.index_offset
== offset
&&
2728 cmd_buffer
->state
.index_type
== indexType
) {
2729 /* No state changes. */
2733 cmd_buffer
->state
.index_buffer
= index_buffer
;
2734 cmd_buffer
->state
.index_offset
= offset
;
2735 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2736 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
2737 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2739 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2740 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2741 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2742 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
2747 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2748 VkPipelineBindPoint bind_point
,
2749 struct radv_descriptor_set
*set
, unsigned idx
)
2751 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2753 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
2756 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2758 if (!cmd_buffer
->device
->use_global_bo_list
) {
2759 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2760 if (set
->descriptors
[j
])
2761 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
2765 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
2768 void radv_CmdBindDescriptorSets(
2769 VkCommandBuffer commandBuffer
,
2770 VkPipelineBindPoint pipelineBindPoint
,
2771 VkPipelineLayout _layout
,
2773 uint32_t descriptorSetCount
,
2774 const VkDescriptorSet
* pDescriptorSets
,
2775 uint32_t dynamicOffsetCount
,
2776 const uint32_t* pDynamicOffsets
)
2778 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2779 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2780 unsigned dyn_idx
= 0;
2782 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
2783 struct radv_descriptor_state
*descriptors_state
=
2784 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
2786 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2787 unsigned idx
= i
+ firstSet
;
2788 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2789 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
2791 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2792 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2793 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
2794 assert(dyn_idx
< dynamicOffsetCount
);
2796 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2797 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2799 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2800 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
2801 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2802 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2803 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2804 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2805 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2806 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2807 cmd_buffer
->push_constant_stages
|=
2808 set
->layout
->dynamic_shader_stages
;
2813 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2814 struct radv_descriptor_set
*set
,
2815 struct radv_descriptor_set_layout
*layout
,
2816 VkPipelineBindPoint bind_point
)
2818 struct radv_descriptor_state
*descriptors_state
=
2819 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2820 set
->size
= layout
->size
;
2821 set
->layout
= layout
;
2823 if (descriptors_state
->push_set
.capacity
< set
->size
) {
2824 size_t new_size
= MAX2(set
->size
, 1024);
2825 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
2826 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2828 free(set
->mapped_ptr
);
2829 set
->mapped_ptr
= malloc(new_size
);
2831 if (!set
->mapped_ptr
) {
2832 descriptors_state
->push_set
.capacity
= 0;
2833 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2837 descriptors_state
->push_set
.capacity
= new_size
;
2843 void radv_meta_push_descriptor_set(
2844 struct radv_cmd_buffer
* cmd_buffer
,
2845 VkPipelineBindPoint pipelineBindPoint
,
2846 VkPipelineLayout _layout
,
2848 uint32_t descriptorWriteCount
,
2849 const VkWriteDescriptorSet
* pDescriptorWrites
)
2851 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2852 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2856 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2858 push_set
->size
= layout
->set
[set
].layout
->size
;
2859 push_set
->layout
= layout
->set
[set
].layout
;
2861 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2863 (void**) &push_set
->mapped_ptr
))
2866 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2867 push_set
->va
+= bo_offset
;
2869 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2870 radv_descriptor_set_to_handle(push_set
),
2871 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2873 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
2876 void radv_CmdPushDescriptorSetKHR(
2877 VkCommandBuffer commandBuffer
,
2878 VkPipelineBindPoint pipelineBindPoint
,
2879 VkPipelineLayout _layout
,
2881 uint32_t descriptorWriteCount
,
2882 const VkWriteDescriptorSet
* pDescriptorWrites
)
2884 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2885 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2886 struct radv_descriptor_state
*descriptors_state
=
2887 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
2888 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
2890 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2892 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
2893 layout
->set
[set
].layout
,
2897 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2898 radv_descriptor_set_to_handle(push_set
),
2899 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2901 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
2902 descriptors_state
->push_dirty
= true;
2905 void radv_CmdPushDescriptorSetWithTemplateKHR(
2906 VkCommandBuffer commandBuffer
,
2907 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2908 VkPipelineLayout _layout
,
2912 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2913 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2914 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
2915 struct radv_descriptor_state
*descriptors_state
=
2916 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
2917 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
2919 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2921 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
2922 layout
->set
[set
].layout
,
2926 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2927 descriptorUpdateTemplate
, pData
);
2929 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
2930 descriptors_state
->push_dirty
= true;
2933 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2934 VkPipelineLayout layout
,
2935 VkShaderStageFlags stageFlags
,
2938 const void* pValues
)
2940 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2941 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2942 cmd_buffer
->push_constant_stages
|= stageFlags
;
2945 VkResult
radv_EndCommandBuffer(
2946 VkCommandBuffer commandBuffer
)
2948 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2950 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
2951 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX6
)
2952 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2953 si_emit_cache_flush(cmd_buffer
);
2956 /* Make sure CP DMA is idle at the end of IBs because the kernel
2957 * doesn't wait for it.
2959 si_cp_dma_wait_for_idle(cmd_buffer
);
2961 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
2963 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
2964 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2966 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
2968 return cmd_buffer
->record_result
;
2972 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2974 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2976 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2979 assert(!pipeline
->ctx_cs
.cdw
);
2981 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2983 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
2984 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
2986 cmd_buffer
->compute_scratch_size_needed
=
2987 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2988 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2990 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2991 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
2993 if (unlikely(cmd_buffer
->device
->trace_bo
))
2994 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
2997 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
2998 VkPipelineBindPoint bind_point
)
3000 struct radv_descriptor_state
*descriptors_state
=
3001 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3003 descriptors_state
->dirty
|= descriptors_state
->valid
;
3006 void radv_CmdBindPipeline(
3007 VkCommandBuffer commandBuffer
,
3008 VkPipelineBindPoint pipelineBindPoint
,
3009 VkPipeline _pipeline
)
3011 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3012 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
3014 switch (pipelineBindPoint
) {
3015 case VK_PIPELINE_BIND_POINT_COMPUTE
:
3016 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
3018 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3020 cmd_buffer
->state
.compute_pipeline
= pipeline
;
3021 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3023 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
3024 if (cmd_buffer
->state
.pipeline
== pipeline
)
3026 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3028 cmd_buffer
->state
.pipeline
= pipeline
;
3032 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
3033 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
3035 /* the new vertex shader might not have the same user regs */
3036 cmd_buffer
->state
.last_first_instance
= -1;
3037 cmd_buffer
->state
.last_vertex_offset
= -1;
3039 /* Prefetch all pipeline shaders at first draw time. */
3040 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
3042 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
3043 radv_bind_streamout_state(cmd_buffer
, pipeline
);
3045 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
3046 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
3047 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
3048 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
3050 if (radv_pipeline_has_tess(pipeline
))
3051 cmd_buffer
->tess_rings_needed
= true;
3054 assert(!"invalid bind point");
3059 void radv_CmdSetViewport(
3060 VkCommandBuffer commandBuffer
,
3061 uint32_t firstViewport
,
3062 uint32_t viewportCount
,
3063 const VkViewport
* pViewports
)
3065 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3066 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3067 MAYBE_UNUSED
const uint32_t total_count
= firstViewport
+ viewportCount
;
3069 assert(firstViewport
< MAX_VIEWPORTS
);
3070 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
3072 if (!memcmp(state
->dynamic
.viewport
.viewports
+ firstViewport
,
3073 pViewports
, viewportCount
* sizeof(*pViewports
))) {
3077 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
3078 viewportCount
* sizeof(*pViewports
));
3080 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
3083 void radv_CmdSetScissor(
3084 VkCommandBuffer commandBuffer
,
3085 uint32_t firstScissor
,
3086 uint32_t scissorCount
,
3087 const VkRect2D
* pScissors
)
3089 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3090 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3091 MAYBE_UNUSED
const uint32_t total_count
= firstScissor
+ scissorCount
;
3093 assert(firstScissor
< MAX_SCISSORS
);
3094 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
3096 if (!memcmp(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3097 scissorCount
* sizeof(*pScissors
))) {
3101 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3102 scissorCount
* sizeof(*pScissors
));
3104 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
3107 void radv_CmdSetLineWidth(
3108 VkCommandBuffer commandBuffer
,
3111 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3113 if (cmd_buffer
->state
.dynamic
.line_width
== lineWidth
)
3116 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
3117 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
3120 void radv_CmdSetDepthBias(
3121 VkCommandBuffer commandBuffer
,
3122 float depthBiasConstantFactor
,
3123 float depthBiasClamp
,
3124 float depthBiasSlopeFactor
)
3126 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3127 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3129 if (state
->dynamic
.depth_bias
.bias
== depthBiasConstantFactor
&&
3130 state
->dynamic
.depth_bias
.clamp
== depthBiasClamp
&&
3131 state
->dynamic
.depth_bias
.slope
== depthBiasSlopeFactor
) {
3135 state
->dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
3136 state
->dynamic
.depth_bias
.clamp
= depthBiasClamp
;
3137 state
->dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
3139 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
3142 void radv_CmdSetBlendConstants(
3143 VkCommandBuffer commandBuffer
,
3144 const float blendConstants
[4])
3146 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3147 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3149 if (!memcmp(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4))
3152 memcpy(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4);
3154 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
3157 void radv_CmdSetDepthBounds(
3158 VkCommandBuffer commandBuffer
,
3159 float minDepthBounds
,
3160 float maxDepthBounds
)
3162 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3163 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3165 if (state
->dynamic
.depth_bounds
.min
== minDepthBounds
&&
3166 state
->dynamic
.depth_bounds
.max
== maxDepthBounds
) {
3170 state
->dynamic
.depth_bounds
.min
= minDepthBounds
;
3171 state
->dynamic
.depth_bounds
.max
= maxDepthBounds
;
3173 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
3176 void radv_CmdSetStencilCompareMask(
3177 VkCommandBuffer commandBuffer
,
3178 VkStencilFaceFlags faceMask
,
3179 uint32_t compareMask
)
3181 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3182 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3183 bool front_same
= state
->dynamic
.stencil_compare_mask
.front
== compareMask
;
3184 bool back_same
= state
->dynamic
.stencil_compare_mask
.back
== compareMask
;
3186 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3187 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3191 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3192 state
->dynamic
.stencil_compare_mask
.front
= compareMask
;
3193 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3194 state
->dynamic
.stencil_compare_mask
.back
= compareMask
;
3196 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
3199 void radv_CmdSetStencilWriteMask(
3200 VkCommandBuffer commandBuffer
,
3201 VkStencilFaceFlags faceMask
,
3204 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3205 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3206 bool front_same
= state
->dynamic
.stencil_write_mask
.front
== writeMask
;
3207 bool back_same
= state
->dynamic
.stencil_write_mask
.back
== writeMask
;
3209 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3210 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3214 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3215 state
->dynamic
.stencil_write_mask
.front
= writeMask
;
3216 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3217 state
->dynamic
.stencil_write_mask
.back
= writeMask
;
3219 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
3222 void radv_CmdSetStencilReference(
3223 VkCommandBuffer commandBuffer
,
3224 VkStencilFaceFlags faceMask
,
3227 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3228 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3229 bool front_same
= state
->dynamic
.stencil_reference
.front
== reference
;
3230 bool back_same
= state
->dynamic
.stencil_reference
.back
== reference
;
3232 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3233 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3237 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3238 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
3239 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3240 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
3242 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
3245 void radv_CmdSetDiscardRectangleEXT(
3246 VkCommandBuffer commandBuffer
,
3247 uint32_t firstDiscardRectangle
,
3248 uint32_t discardRectangleCount
,
3249 const VkRect2D
* pDiscardRectangles
)
3251 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3252 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3253 MAYBE_UNUSED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
3255 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
3256 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
3258 if (!memcmp(state
->dynamic
.discard_rectangle
.rectangles
+ firstDiscardRectangle
,
3259 pDiscardRectangles
, discardRectangleCount
* sizeof(*pDiscardRectangles
))) {
3263 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
3264 pDiscardRectangles
, discardRectangleCount
);
3266 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
3269 void radv_CmdExecuteCommands(
3270 VkCommandBuffer commandBuffer
,
3271 uint32_t commandBufferCount
,
3272 const VkCommandBuffer
* pCmdBuffers
)
3274 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
3276 assert(commandBufferCount
> 0);
3278 /* Emit pending flushes on primary prior to executing secondary */
3279 si_emit_cache_flush(primary
);
3281 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3282 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
3284 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
3285 secondary
->scratch_size_needed
);
3286 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
3287 secondary
->compute_scratch_size_needed
);
3289 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
3290 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
3291 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
3292 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
3293 if (secondary
->tess_rings_needed
)
3294 primary
->tess_rings_needed
= true;
3295 if (secondary
->sample_positions_needed
)
3296 primary
->sample_positions_needed
= true;
3298 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
3301 /* When the secondary command buffer is compute only we don't
3302 * need to re-emit the current graphics pipeline.
3304 if (secondary
->state
.emitted_pipeline
) {
3305 primary
->state
.emitted_pipeline
=
3306 secondary
->state
.emitted_pipeline
;
3309 /* When the secondary command buffer is graphics only we don't
3310 * need to re-emit the current compute pipeline.
3312 if (secondary
->state
.emitted_compute_pipeline
) {
3313 primary
->state
.emitted_compute_pipeline
=
3314 secondary
->state
.emitted_compute_pipeline
;
3317 /* Only re-emit the draw packets when needed. */
3318 if (secondary
->state
.last_primitive_reset_en
!= -1) {
3319 primary
->state
.last_primitive_reset_en
=
3320 secondary
->state
.last_primitive_reset_en
;
3323 if (secondary
->state
.last_primitive_reset_index
) {
3324 primary
->state
.last_primitive_reset_index
=
3325 secondary
->state
.last_primitive_reset_index
;
3328 if (secondary
->state
.last_ia_multi_vgt_param
) {
3329 primary
->state
.last_ia_multi_vgt_param
=
3330 secondary
->state
.last_ia_multi_vgt_param
;
3333 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
3334 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
3335 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
3337 if (secondary
->state
.last_index_type
!= -1) {
3338 primary
->state
.last_index_type
=
3339 secondary
->state
.last_index_type
;
3343 /* After executing commands from secondary buffers we have to dirty
3346 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
3347 RADV_CMD_DIRTY_INDEX_BUFFER
|
3348 RADV_CMD_DIRTY_DYNAMIC_ALL
;
3349 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
3350 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
3353 VkResult
radv_CreateCommandPool(
3355 const VkCommandPoolCreateInfo
* pCreateInfo
,
3356 const VkAllocationCallbacks
* pAllocator
,
3357 VkCommandPool
* pCmdPool
)
3359 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3360 struct radv_cmd_pool
*pool
;
3362 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
3363 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3365 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3368 pool
->alloc
= *pAllocator
;
3370 pool
->alloc
= device
->alloc
;
3372 list_inithead(&pool
->cmd_buffers
);
3373 list_inithead(&pool
->free_cmd_buffers
);
3375 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
3377 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
3383 void radv_DestroyCommandPool(
3385 VkCommandPool commandPool
,
3386 const VkAllocationCallbacks
* pAllocator
)
3388 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3389 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3394 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3395 &pool
->cmd_buffers
, pool_link
) {
3396 radv_cmd_buffer_destroy(cmd_buffer
);
3399 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3400 &pool
->free_cmd_buffers
, pool_link
) {
3401 radv_cmd_buffer_destroy(cmd_buffer
);
3404 vk_free2(&device
->alloc
, pAllocator
, pool
);
3407 VkResult
radv_ResetCommandPool(
3409 VkCommandPool commandPool
,
3410 VkCommandPoolResetFlags flags
)
3412 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3415 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
3416 &pool
->cmd_buffers
, pool_link
) {
3417 result
= radv_reset_cmd_buffer(cmd_buffer
);
3418 if (result
!= VK_SUCCESS
)
3425 void radv_TrimCommandPool(
3427 VkCommandPool commandPool
,
3428 VkCommandPoolTrimFlags flags
)
3430 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3435 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3436 &pool
->free_cmd_buffers
, pool_link
) {
3437 radv_cmd_buffer_destroy(cmd_buffer
);
3442 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
)
3444 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3445 uint32_t subpass_id
= state
->subpass
- state
->pass
->subpasses
;
3447 /* The id of this subpass shouldn't exceed the number of subpasses in
3448 * this render pass minus 1.
3450 assert(subpass_id
< state
->pass
->subpass_count
);
3455 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer
*cmd_buffer
,
3456 uint32_t subpass_id
)
3458 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3459 struct radv_subpass
*subpass
= &state
->pass
->subpasses
[subpass_id
];
3461 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
3462 cmd_buffer
->cs
, 4096);
3464 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
3466 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3467 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3468 if (a
== VK_ATTACHMENT_UNUSED
)
3471 radv_handle_subpass_image_transition(cmd_buffer
,
3472 subpass
->attachments
[i
]);
3475 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
3476 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3478 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3482 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer
*cmd_buffer
)
3484 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3485 const struct radv_subpass
*subpass
= state
->subpass
;
3486 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
3488 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3490 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3491 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3492 if (a
== VK_ATTACHMENT_UNUSED
)
3495 if (state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
3498 VkImageLayout layout
= state
->pass
->attachments
[a
].final_layout
;
3499 radv_handle_subpass_image_transition(cmd_buffer
,
3500 (struct radv_subpass_attachment
){a
, layout
});
3504 void radv_CmdBeginRenderPass(
3505 VkCommandBuffer commandBuffer
,
3506 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3507 VkSubpassContents contents
)
3509 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3510 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3511 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3514 cmd_buffer
->state
.framebuffer
= framebuffer
;
3515 cmd_buffer
->state
.pass
= pass
;
3516 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3518 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
3519 if (result
!= VK_SUCCESS
)
3522 radv_cmd_buffer_begin_subpass(cmd_buffer
, 0);
3525 void radv_CmdBeginRenderPass2KHR(
3526 VkCommandBuffer commandBuffer
,
3527 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
3528 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
3530 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
3531 pSubpassBeginInfo
->contents
);
3534 void radv_CmdNextSubpass(
3535 VkCommandBuffer commandBuffer
,
3536 VkSubpassContents contents
)
3538 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3540 uint32_t prev_subpass
= radv_get_subpass_id(cmd_buffer
);
3541 radv_cmd_buffer_end_subpass(cmd_buffer
);
3542 radv_cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
3545 void radv_CmdNextSubpass2KHR(
3546 VkCommandBuffer commandBuffer
,
3547 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
3548 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3550 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
3553 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
3555 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
3556 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
3557 if (!radv_get_shader(pipeline
, stage
))
3560 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
3561 if (loc
->sgpr_idx
== -1)
3563 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
3564 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3567 if (pipeline
->gs_copy_shader
) {
3568 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
3569 if (loc
->sgpr_idx
!= -1) {
3570 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3571 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3577 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3578 uint32_t vertex_count
,
3581 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
3582 radeon_emit(cmd_buffer
->cs
, vertex_count
);
3583 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
3584 S_0287F0_USE_OPAQUE(use_opaque
));
3588 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
3590 uint32_t index_count
)
3592 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
3593 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
3594 radeon_emit(cmd_buffer
->cs
, index_va
);
3595 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
3596 radeon_emit(cmd_buffer
->cs
, index_count
);
3597 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
3601 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3603 uint32_t draw_count
,
3607 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3608 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
3609 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
3610 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
;
3611 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
3612 bool predicating
= cmd_buffer
->state
.predicating
;
3615 /* just reset draw state for vertex data */
3616 cmd_buffer
->state
.last_first_instance
= -1;
3617 cmd_buffer
->state
.last_num_instances
= -1;
3618 cmd_buffer
->state
.last_vertex_offset
= -1;
3620 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
3621 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
3622 PKT3_DRAW_INDIRECT
, 3, predicating
));
3624 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3625 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3626 radeon_emit(cs
, di_src_sel
);
3628 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
3629 PKT3_DRAW_INDIRECT_MULTI
,
3632 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3633 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3634 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
3635 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
3636 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
3637 radeon_emit(cs
, draw_count
); /* count */
3638 radeon_emit(cs
, count_va
); /* count_addr */
3639 radeon_emit(cs
, count_va
>> 32);
3640 radeon_emit(cs
, stride
); /* stride */
3641 radeon_emit(cs
, di_src_sel
);
3646 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
3647 const struct radv_draw_info
*info
)
3649 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3650 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3651 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3653 if (info
->indirect
) {
3654 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3655 uint64_t count_va
= 0;
3657 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3659 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
3661 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
3663 radeon_emit(cs
, va
);
3664 radeon_emit(cs
, va
>> 32);
3666 if (info
->count_buffer
) {
3667 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
3668 count_va
+= info
->count_buffer
->offset
+
3669 info
->count_buffer_offset
;
3671 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
3674 if (!state
->subpass
->view_mask
) {
3675 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3682 for_each_bit(i
, state
->subpass
->view_mask
) {
3683 radv_emit_view_index(cmd_buffer
, i
);
3685 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3693 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
3695 if (info
->vertex_offset
!= state
->last_vertex_offset
||
3696 info
->first_instance
!= state
->last_first_instance
) {
3697 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
3698 state
->pipeline
->graphics
.vtx_emit_num
);
3700 radeon_emit(cs
, info
->vertex_offset
);
3701 radeon_emit(cs
, info
->first_instance
);
3702 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
3704 state
->last_first_instance
= info
->first_instance
;
3705 state
->last_vertex_offset
= info
->vertex_offset
;
3708 if (state
->last_num_instances
!= info
->instance_count
) {
3709 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
3710 radeon_emit(cs
, info
->instance_count
);
3711 state
->last_num_instances
= info
->instance_count
;
3714 if (info
->indexed
) {
3715 int index_size
= state
->index_type
? 4 : 2;
3718 index_va
= state
->index_va
;
3719 index_va
+= info
->first_index
* index_size
;
3721 if (!state
->subpass
->view_mask
) {
3722 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3727 for_each_bit(i
, state
->subpass
->view_mask
) {
3728 radv_emit_view_index(cmd_buffer
, i
);
3730 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3736 if (!state
->subpass
->view_mask
) {
3737 radv_cs_emit_draw_packet(cmd_buffer
,
3739 !!info
->strmout_buffer
);
3742 for_each_bit(i
, state
->subpass
->view_mask
) {
3743 radv_emit_view_index(cmd_buffer
, i
);
3745 radv_cs_emit_draw_packet(cmd_buffer
,
3747 !!info
->strmout_buffer
);
3755 * Vega and raven have a bug which triggers if there are multiple context
3756 * register contexts active at the same time with different scissor values.
3758 * There are two possible workarounds:
3759 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3760 * there is only ever 1 active set of scissor values at the same time.
3762 * 2) Whenever the hardware switches contexts we have to set the scissor
3763 * registers again even if it is a noop. That way the new context gets
3764 * the correct scissor values.
3766 * This implements option 2. radv_need_late_scissor_emission needs to
3767 * return true on affected HW if radv_emit_all_graphics_states sets
3768 * any context registers.
3770 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
3771 const struct radv_draw_info
*info
)
3773 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3775 if (!cmd_buffer
->device
->physical_device
->has_scissor_bug
)
3778 if (cmd_buffer
->state
.context_roll_without_scissor_emitted
|| info
->strmout_buffer
)
3781 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
3783 /* Index, vertex and streamout buffers don't change context regs, and
3784 * pipeline is already handled.
3786 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
|
3787 RADV_CMD_DIRTY_VERTEX_BUFFER
|
3788 RADV_CMD_DIRTY_STREAMOUT_BUFFER
|
3789 RADV_CMD_DIRTY_PIPELINE
);
3791 if (cmd_buffer
->state
.dirty
& used_states
)
3794 if (info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
&&
3795 (state
->index_type
? 0xffffffffu
: 0xffffu
) != state
->last_primitive_reset_index
)
3802 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
3803 const struct radv_draw_info
*info
)
3805 bool late_scissor_emission
;
3807 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
3808 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
3809 radv_emit_rbplus_state(cmd_buffer
);
3811 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
3812 radv_emit_graphics_pipeline(cmd_buffer
);
3814 /* This should be before the cmd_buffer->state.dirty is cleared
3815 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
3816 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
3817 late_scissor_emission
=
3818 radv_need_late_scissor_emission(cmd_buffer
, info
);
3820 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
3821 radv_emit_framebuffer_state(cmd_buffer
);
3823 if (info
->indexed
) {
3824 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
3825 radv_emit_index_buffer(cmd_buffer
);
3827 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3828 * so the state must be re-emitted before the next indexed
3831 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3832 cmd_buffer
->state
.last_index_type
= -1;
3833 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3837 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
3839 radv_emit_draw_registers(cmd_buffer
, info
);
3841 if (late_scissor_emission
)
3842 radv_emit_scissor(cmd_buffer
);
3846 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
3847 const struct radv_draw_info
*info
)
3849 struct radeon_info
*rad_info
=
3850 &cmd_buffer
->device
->physical_device
->rad_info
;
3852 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3853 bool pipeline_is_dirty
=
3854 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
3855 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
3857 MAYBE_UNUSED
unsigned cdw_max
=
3858 radeon_check_space(cmd_buffer
->device
->ws
,
3859 cmd_buffer
->cs
, 4096);
3861 if (likely(!info
->indirect
)) {
3862 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
3863 * no workaround for indirect draws, but we can at least skip
3866 if (unlikely(!info
->instance_count
))
3869 /* Handle count == 0. */
3870 if (unlikely(!info
->count
&& !info
->strmout_buffer
))
3874 /* Use optimal packet order based on whether we need to sync the
3877 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3878 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3879 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
3880 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
3881 /* If we have to wait for idle, set all states first, so that
3882 * all SET packets are processed in parallel with previous draw
3883 * calls. Then upload descriptors, set shader pointers, and
3884 * draw, and prefetch at the end. This ensures that the time
3885 * the CUs are idle is very short. (there are only SET_SH
3886 * packets between the wait and the draw)
3888 radv_emit_all_graphics_states(cmd_buffer
, info
);
3889 si_emit_cache_flush(cmd_buffer
);
3890 /* <-- CUs are idle here --> */
3892 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
3894 radv_emit_draw_packets(cmd_buffer
, info
);
3895 /* <-- CUs are busy here --> */
3897 /* Start prefetches after the draw has been started. Both will
3898 * run in parallel, but starting the draw first is more
3901 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3902 radv_emit_prefetch_L2(cmd_buffer
,
3903 cmd_buffer
->state
.pipeline
, false);
3906 /* If we don't wait for idle, start prefetches first, then set
3907 * states, and draw at the end.
3909 si_emit_cache_flush(cmd_buffer
);
3911 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3912 /* Only prefetch the vertex shader and VBO descriptors
3913 * in order to start the draw as soon as possible.
3915 radv_emit_prefetch_L2(cmd_buffer
,
3916 cmd_buffer
->state
.pipeline
, true);
3919 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
3921 radv_emit_all_graphics_states(cmd_buffer
, info
);
3922 radv_emit_draw_packets(cmd_buffer
, info
);
3924 /* Prefetch the remaining shaders after the draw has been
3927 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
3928 radv_emit_prefetch_L2(cmd_buffer
,
3929 cmd_buffer
->state
.pipeline
, false);
3933 /* Workaround for a VGT hang when streamout is enabled.
3934 * It must be done after drawing.
3936 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
3937 (rad_info
->family
== CHIP_HAWAII
||
3938 rad_info
->family
== CHIP_TONGA
||
3939 rad_info
->family
== CHIP_FIJI
)) {
3940 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
3943 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3944 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
3948 VkCommandBuffer commandBuffer
,
3949 uint32_t vertexCount
,
3950 uint32_t instanceCount
,
3951 uint32_t firstVertex
,
3952 uint32_t firstInstance
)
3954 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3955 struct radv_draw_info info
= {};
3957 info
.count
= vertexCount
;
3958 info
.instance_count
= instanceCount
;
3959 info
.first_instance
= firstInstance
;
3960 info
.vertex_offset
= firstVertex
;
3962 radv_draw(cmd_buffer
, &info
);
3965 void radv_CmdDrawIndexed(
3966 VkCommandBuffer commandBuffer
,
3967 uint32_t indexCount
,
3968 uint32_t instanceCount
,
3969 uint32_t firstIndex
,
3970 int32_t vertexOffset
,
3971 uint32_t firstInstance
)
3973 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3974 struct radv_draw_info info
= {};
3976 info
.indexed
= true;
3977 info
.count
= indexCount
;
3978 info
.instance_count
= instanceCount
;
3979 info
.first_index
= firstIndex
;
3980 info
.vertex_offset
= vertexOffset
;
3981 info
.first_instance
= firstInstance
;
3983 radv_draw(cmd_buffer
, &info
);
3986 void radv_CmdDrawIndirect(
3987 VkCommandBuffer commandBuffer
,
3989 VkDeviceSize offset
,
3993 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3994 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3995 struct radv_draw_info info
= {};
3997 info
.count
= drawCount
;
3998 info
.indirect
= buffer
;
3999 info
.indirect_offset
= offset
;
4000 info
.stride
= stride
;
4002 radv_draw(cmd_buffer
, &info
);
4005 void radv_CmdDrawIndexedIndirect(
4006 VkCommandBuffer commandBuffer
,
4008 VkDeviceSize offset
,
4012 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4013 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4014 struct radv_draw_info info
= {};
4016 info
.indexed
= true;
4017 info
.count
= drawCount
;
4018 info
.indirect
= buffer
;
4019 info
.indirect_offset
= offset
;
4020 info
.stride
= stride
;
4022 radv_draw(cmd_buffer
, &info
);
4025 void radv_CmdDrawIndirectCountKHR(
4026 VkCommandBuffer commandBuffer
,
4028 VkDeviceSize offset
,
4029 VkBuffer _countBuffer
,
4030 VkDeviceSize countBufferOffset
,
4031 uint32_t maxDrawCount
,
4034 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4035 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4036 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4037 struct radv_draw_info info
= {};
4039 info
.count
= maxDrawCount
;
4040 info
.indirect
= buffer
;
4041 info
.indirect_offset
= offset
;
4042 info
.count_buffer
= count_buffer
;
4043 info
.count_buffer_offset
= countBufferOffset
;
4044 info
.stride
= stride
;
4046 radv_draw(cmd_buffer
, &info
);
4049 void radv_CmdDrawIndexedIndirectCountKHR(
4050 VkCommandBuffer commandBuffer
,
4052 VkDeviceSize offset
,
4053 VkBuffer _countBuffer
,
4054 VkDeviceSize countBufferOffset
,
4055 uint32_t maxDrawCount
,
4058 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4059 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4060 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4061 struct radv_draw_info info
= {};
4063 info
.indexed
= true;
4064 info
.count
= maxDrawCount
;
4065 info
.indirect
= buffer
;
4066 info
.indirect_offset
= offset
;
4067 info
.count_buffer
= count_buffer
;
4068 info
.count_buffer_offset
= countBufferOffset
;
4069 info
.stride
= stride
;
4071 radv_draw(cmd_buffer
, &info
);
4074 struct radv_dispatch_info
{
4076 * Determine the layout of the grid (in block units) to be used.
4081 * A starting offset for the grid. If unaligned is set, the offset
4082 * must still be aligned.
4084 uint32_t offsets
[3];
4086 * Whether it's an unaligned compute dispatch.
4091 * Indirect compute parameters resource.
4093 struct radv_buffer
*indirect
;
4094 uint64_t indirect_offset
;
4098 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
4099 const struct radv_dispatch_info
*info
)
4101 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4102 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4103 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
4104 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4105 bool predicating
= cmd_buffer
->state
.predicating
;
4106 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4107 struct radv_userdata_info
*loc
;
4109 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
4110 AC_UD_CS_GRID_SIZE
);
4112 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
4114 if (info
->indirect
) {
4115 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4117 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4119 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4121 if (loc
->sgpr_idx
!= -1) {
4122 for (unsigned i
= 0; i
< 3; ++i
) {
4123 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
4124 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
4125 COPY_DATA_DST_SEL(COPY_DATA_REG
));
4126 radeon_emit(cs
, (va
+ 4 * i
));
4127 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
4128 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
4129 + loc
->sgpr_idx
* 4) >> 2) + i
);
4134 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
4135 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
4136 PKT3_SHADER_TYPE_S(1));
4137 radeon_emit(cs
, va
);
4138 radeon_emit(cs
, va
>> 32);
4139 radeon_emit(cs
, dispatch_initiator
);
4141 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
4142 PKT3_SHADER_TYPE_S(1));
4144 radeon_emit(cs
, va
);
4145 radeon_emit(cs
, va
>> 32);
4147 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
4148 PKT3_SHADER_TYPE_S(1));
4150 radeon_emit(cs
, dispatch_initiator
);
4153 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
4154 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
4156 if (info
->unaligned
) {
4157 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
4158 unsigned remainder
[3];
4160 /* If aligned, these should be an entire block size,
4163 remainder
[0] = blocks
[0] + cs_block_size
[0] -
4164 align_u32_npot(blocks
[0], cs_block_size
[0]);
4165 remainder
[1] = blocks
[1] + cs_block_size
[1] -
4166 align_u32_npot(blocks
[1], cs_block_size
[1]);
4167 remainder
[2] = blocks
[2] + cs_block_size
[2] -
4168 align_u32_npot(blocks
[2], cs_block_size
[2]);
4170 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
4171 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
4172 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
4174 for(unsigned i
= 0; i
< 3; ++i
) {
4175 assert(offsets
[i
] % cs_block_size
[i
] == 0);
4176 offsets
[i
] /= cs_block_size
[i
];
4179 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
4181 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
4182 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
4184 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
4185 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
4187 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
4188 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
4190 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
4193 if (loc
->sgpr_idx
!= -1) {
4194 assert(loc
->num_sgprs
== 3);
4196 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
4197 loc
->sgpr_idx
* 4, 3);
4198 radeon_emit(cs
, blocks
[0]);
4199 radeon_emit(cs
, blocks
[1]);
4200 radeon_emit(cs
, blocks
[2]);
4203 if (offsets
[0] || offsets
[1] || offsets
[2]) {
4204 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
4205 radeon_emit(cs
, offsets
[0]);
4206 radeon_emit(cs
, offsets
[1]);
4207 radeon_emit(cs
, offsets
[2]);
4209 /* The blocks in the packet are not counts but end values. */
4210 for (unsigned i
= 0; i
< 3; ++i
)
4211 blocks
[i
] += offsets
[i
];
4213 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
4216 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
4217 PKT3_SHADER_TYPE_S(1));
4218 radeon_emit(cs
, blocks
[0]);
4219 radeon_emit(cs
, blocks
[1]);
4220 radeon_emit(cs
, blocks
[2]);
4221 radeon_emit(cs
, dispatch_initiator
);
4224 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4228 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
4230 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4231 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4235 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
4236 const struct radv_dispatch_info
*info
)
4238 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4240 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4241 bool pipeline_is_dirty
= pipeline
&&
4242 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
4244 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4245 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4246 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4247 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4248 /* If we have to wait for idle, set all states first, so that
4249 * all SET packets are processed in parallel with previous draw
4250 * calls. Then upload descriptors, set shader pointers, and
4251 * dispatch, and prefetch at the end. This ensures that the
4252 * time the CUs are idle is very short. (there are only SET_SH
4253 * packets between the wait and the draw)
4255 radv_emit_compute_pipeline(cmd_buffer
);
4256 si_emit_cache_flush(cmd_buffer
);
4257 /* <-- CUs are idle here --> */
4259 radv_upload_compute_shader_descriptors(cmd_buffer
);
4261 radv_emit_dispatch_packets(cmd_buffer
, info
);
4262 /* <-- CUs are busy here --> */
4264 /* Start prefetches after the dispatch has been started. Both
4265 * will run in parallel, but starting the dispatch first is
4268 if (has_prefetch
&& pipeline_is_dirty
) {
4269 radv_emit_shader_prefetch(cmd_buffer
,
4270 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4273 /* If we don't wait for idle, start prefetches first, then set
4274 * states, and dispatch at the end.
4276 si_emit_cache_flush(cmd_buffer
);
4278 if (has_prefetch
&& pipeline_is_dirty
) {
4279 radv_emit_shader_prefetch(cmd_buffer
,
4280 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4283 radv_upload_compute_shader_descriptors(cmd_buffer
);
4285 radv_emit_compute_pipeline(cmd_buffer
);
4286 radv_emit_dispatch_packets(cmd_buffer
, info
);
4289 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
4292 void radv_CmdDispatchBase(
4293 VkCommandBuffer commandBuffer
,
4301 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4302 struct radv_dispatch_info info
= {};
4308 info
.offsets
[0] = base_x
;
4309 info
.offsets
[1] = base_y
;
4310 info
.offsets
[2] = base_z
;
4311 radv_dispatch(cmd_buffer
, &info
);
4314 void radv_CmdDispatch(
4315 VkCommandBuffer commandBuffer
,
4320 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
4323 void radv_CmdDispatchIndirect(
4324 VkCommandBuffer commandBuffer
,
4326 VkDeviceSize offset
)
4328 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4329 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4330 struct radv_dispatch_info info
= {};
4332 info
.indirect
= buffer
;
4333 info
.indirect_offset
= offset
;
4335 radv_dispatch(cmd_buffer
, &info
);
4338 void radv_unaligned_dispatch(
4339 struct radv_cmd_buffer
*cmd_buffer
,
4344 struct radv_dispatch_info info
= {};
4351 radv_dispatch(cmd_buffer
, &info
);
4354 void radv_CmdEndRenderPass(
4355 VkCommandBuffer commandBuffer
)
4357 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4359 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
4361 radv_cmd_buffer_end_subpass(cmd_buffer
);
4363 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
4365 cmd_buffer
->state
.pass
= NULL
;
4366 cmd_buffer
->state
.subpass
= NULL
;
4367 cmd_buffer
->state
.attachments
= NULL
;
4368 cmd_buffer
->state
.framebuffer
= NULL
;
4371 void radv_CmdEndRenderPass2KHR(
4372 VkCommandBuffer commandBuffer
,
4373 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4375 radv_CmdEndRenderPass(commandBuffer
);
4379 * For HTILE we have the following interesting clear words:
4380 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4381 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4382 * 0xfffffff0: Clear depth to 1.0
4383 * 0x00000000: Clear depth to 0.0
4385 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
4386 struct radv_image
*image
,
4387 const VkImageSubresourceRange
*range
,
4388 uint32_t clear_word
)
4390 assert(range
->baseMipLevel
== 0);
4391 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
4392 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4393 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4394 VkClearDepthStencilValue value
= {};
4396 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4397 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4399 state
->flush_bits
|= radv_clear_htile(cmd_buffer
, image
, range
, clear_word
);
4401 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4403 if (vk_format_is_stencil(image
->vk_format
))
4404 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
4406 radv_set_ds_clear_metadata(cmd_buffer
, image
, value
, aspects
);
4408 if (radv_image_is_tc_compat_htile(image
)) {
4409 /* Initialize the TC-compat metada value to 0 because by
4410 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4411 * need have to conditionally update its value when performing
4412 * a fast depth clear.
4414 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, 0);
4418 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4419 struct radv_image
*image
,
4420 VkImageLayout src_layout
,
4421 VkImageLayout dst_layout
,
4422 unsigned src_queue_mask
,
4423 unsigned dst_queue_mask
,
4424 const VkImageSubresourceRange
*range
)
4426 if (!radv_image_has_htile(image
))
4429 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
4430 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
4432 if (radv_layout_is_htile_compressed(image
, dst_layout
,
4437 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
4438 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4439 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4440 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
4441 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
4442 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4443 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4444 VkImageSubresourceRange local_range
= *range
;
4445 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4446 local_range
.baseMipLevel
= 0;
4447 local_range
.levelCount
= 1;
4449 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4450 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4452 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
4454 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4455 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4459 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
4460 struct radv_image
*image
, uint32_t value
)
4462 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4464 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4465 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4467 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, value
);
4469 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4472 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
4473 struct radv_image
*image
)
4475 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4476 static const uint32_t fmask_clear_values
[4] = {
4482 uint32_t log2_samples
= util_logbase2(image
->info
.samples
);
4483 uint32_t value
= fmask_clear_values
[log2_samples
];
4485 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4486 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4488 state
->flush_bits
|= radv_clear_fmask(cmd_buffer
, image
, value
);
4490 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4493 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
4494 struct radv_image
*image
, uint32_t value
)
4496 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4498 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4499 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4501 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, value
);
4503 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4504 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4508 * Initialize DCC/FMASK/CMASK metadata for a color image.
4510 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
4511 struct radv_image
*image
,
4512 VkImageLayout src_layout
,
4513 VkImageLayout dst_layout
,
4514 unsigned src_queue_mask
,
4515 unsigned dst_queue_mask
)
4517 if (radv_image_has_cmask(image
)) {
4518 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4520 /* TODO: clarify this. */
4521 if (radv_image_has_fmask(image
)) {
4522 value
= 0xccccccccu
;
4525 radv_initialise_cmask(cmd_buffer
, image
, value
);
4528 if (radv_image_has_fmask(image
)) {
4529 radv_initialize_fmask(cmd_buffer
, image
);
4532 if (radv_image_has_dcc(image
)) {
4533 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4534 bool need_decompress_pass
= false;
4536 if (radv_layout_dcc_compressed(image
, dst_layout
,
4538 value
= 0x20202020u
;
4539 need_decompress_pass
= true;
4542 radv_initialize_dcc(cmd_buffer
, image
, value
);
4544 radv_update_fce_metadata(cmd_buffer
, image
,
4545 need_decompress_pass
);
4548 if (radv_image_has_cmask(image
) || radv_image_has_dcc(image
)) {
4549 uint32_t color_values
[2] = {};
4550 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
4555 * Handle color image transitions for DCC/FMASK/CMASK.
4557 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4558 struct radv_image
*image
,
4559 VkImageLayout src_layout
,
4560 VkImageLayout dst_layout
,
4561 unsigned src_queue_mask
,
4562 unsigned dst_queue_mask
,
4563 const VkImageSubresourceRange
*range
)
4565 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
4566 radv_init_color_image_metadata(cmd_buffer
, image
,
4567 src_layout
, dst_layout
,
4568 src_queue_mask
, dst_queue_mask
);
4572 if (radv_image_has_dcc(image
)) {
4573 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
4574 radv_initialize_dcc(cmd_buffer
, image
, 0xffffffffu
);
4575 } else if (radv_layout_dcc_compressed(image
, src_layout
, src_queue_mask
) &&
4576 !radv_layout_dcc_compressed(image
, dst_layout
, dst_queue_mask
)) {
4577 radv_decompress_dcc(cmd_buffer
, image
, range
);
4578 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4579 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4580 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4582 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
4583 bool fce_eliminate
= false, fmask_expand
= false;
4585 if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4586 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4587 fce_eliminate
= true;
4590 if (radv_image_has_fmask(image
)) {
4591 if (src_layout
!= VK_IMAGE_LAYOUT_GENERAL
&&
4592 dst_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
4593 /* A FMASK decompress is required before doing
4594 * a MSAA decompress using FMASK.
4596 fmask_expand
= true;
4600 if (fce_eliminate
|| fmask_expand
)
4601 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4604 radv_expand_fmask_image_inplace(cmd_buffer
, image
, range
);
4608 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4609 struct radv_image
*image
,
4610 VkImageLayout src_layout
,
4611 VkImageLayout dst_layout
,
4612 uint32_t src_family
,
4613 uint32_t dst_family
,
4614 const VkImageSubresourceRange
*range
)
4616 if (image
->exclusive
&& src_family
!= dst_family
) {
4617 /* This is an acquire or a release operation and there will be
4618 * a corresponding release/acquire. Do the transition in the
4619 * most flexible queue. */
4621 assert(src_family
== cmd_buffer
->queue_family_index
||
4622 dst_family
== cmd_buffer
->queue_family_index
);
4624 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
4627 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
4628 (src_family
== RADV_QUEUE_GENERAL
||
4629 dst_family
== RADV_QUEUE_GENERAL
))
4633 if (src_layout
== dst_layout
)
4636 unsigned src_queue_mask
=
4637 radv_image_queue_family_mask(image
, src_family
,
4638 cmd_buffer
->queue_family_index
);
4639 unsigned dst_queue_mask
=
4640 radv_image_queue_family_mask(image
, dst_family
,
4641 cmd_buffer
->queue_family_index
);
4643 if (vk_format_is_depth(image
->vk_format
)) {
4644 radv_handle_depth_image_transition(cmd_buffer
, image
,
4645 src_layout
, dst_layout
,
4646 src_queue_mask
, dst_queue_mask
,
4649 radv_handle_color_image_transition(cmd_buffer
, image
,
4650 src_layout
, dst_layout
,
4651 src_queue_mask
, dst_queue_mask
,
4656 struct radv_barrier_info
{
4657 uint32_t eventCount
;
4658 const VkEvent
*pEvents
;
4659 VkPipelineStageFlags srcStageMask
;
4660 VkPipelineStageFlags dstStageMask
;
4664 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
4665 uint32_t memoryBarrierCount
,
4666 const VkMemoryBarrier
*pMemoryBarriers
,
4667 uint32_t bufferMemoryBarrierCount
,
4668 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
4669 uint32_t imageMemoryBarrierCount
,
4670 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
4671 const struct radv_barrier_info
*info
)
4673 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4674 enum radv_cmd_flush_bits src_flush_bits
= 0;
4675 enum radv_cmd_flush_bits dst_flush_bits
= 0;
4677 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
4678 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
4679 uint64_t va
= radv_buffer_get_va(event
->bo
);
4681 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
4683 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
4685 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
4686 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4689 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
4690 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
4692 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
4696 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
4697 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
4699 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
4703 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4704 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4706 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
4708 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
4712 /* The Vulkan spec 1.1.98 says:
4714 * "An execution dependency with only
4715 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
4716 * will only prevent that stage from executing in subsequently
4717 * submitted commands. As this stage does not perform any actual
4718 * execution, this is not observable - in effect, it does not delay
4719 * processing of subsequent commands. Similarly an execution dependency
4720 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
4721 * will effectively not wait for any prior commands to complete."
4723 if (info
->dstStageMask
!= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
)
4724 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
4725 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
4727 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4728 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4729 radv_handle_image_transition(cmd_buffer
, image
,
4730 pImageMemoryBarriers
[i
].oldLayout
,
4731 pImageMemoryBarriers
[i
].newLayout
,
4732 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
4733 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
4734 &pImageMemoryBarriers
[i
].subresourceRange
);
4737 /* Make sure CP DMA is idle because the driver might have performed a
4738 * DMA operation for copying or filling buffers/images.
4740 if (info
->srcStageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
4741 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
4742 si_cp_dma_wait_for_idle(cmd_buffer
);
4744 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
4747 void radv_CmdPipelineBarrier(
4748 VkCommandBuffer commandBuffer
,
4749 VkPipelineStageFlags srcStageMask
,
4750 VkPipelineStageFlags destStageMask
,
4752 uint32_t memoryBarrierCount
,
4753 const VkMemoryBarrier
* pMemoryBarriers
,
4754 uint32_t bufferMemoryBarrierCount
,
4755 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4756 uint32_t imageMemoryBarrierCount
,
4757 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4759 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4760 struct radv_barrier_info info
;
4762 info
.eventCount
= 0;
4763 info
.pEvents
= NULL
;
4764 info
.srcStageMask
= srcStageMask
;
4765 info
.dstStageMask
= destStageMask
;
4767 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
4768 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4769 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
4773 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
4774 struct radv_event
*event
,
4775 VkPipelineStageFlags stageMask
,
4778 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4779 uint64_t va
= radv_buffer_get_va(event
->bo
);
4781 si_emit_cache_flush(cmd_buffer
);
4783 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
4785 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 21);
4787 /* Flags that only require a top-of-pipe event. */
4788 VkPipelineStageFlags top_of_pipe_flags
=
4789 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
4791 /* Flags that only require a post-index-fetch event. */
4792 VkPipelineStageFlags post_index_fetch_flags
=
4794 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
4795 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
4797 /* Make sure CP DMA is idle because the driver might have performed a
4798 * DMA operation for copying or filling buffers/images.
4800 if (stageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
4801 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
4802 si_cp_dma_wait_for_idle(cmd_buffer
);
4804 /* TODO: Emit EOS events for syncing PS/CS stages. */
4806 if (!(stageMask
& ~top_of_pipe_flags
)) {
4807 /* Just need to sync the PFP engine. */
4808 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
4809 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
4810 S_370_WR_CONFIRM(1) |
4811 S_370_ENGINE_SEL(V_370_PFP
));
4812 radeon_emit(cs
, va
);
4813 radeon_emit(cs
, va
>> 32);
4814 radeon_emit(cs
, value
);
4815 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
4816 /* Sync ME because PFP reads index and indirect buffers. */
4817 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
4818 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
4819 S_370_WR_CONFIRM(1) |
4820 S_370_ENGINE_SEL(V_370_ME
));
4821 radeon_emit(cs
, va
);
4822 radeon_emit(cs
, va
>> 32);
4823 radeon_emit(cs
, value
);
4825 /* Otherwise, sync all prior GPU work using an EOP event. */
4826 si_cs_emit_write_event_eop(cs
,
4827 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
4828 radv_cmd_buffer_uses_mec(cmd_buffer
),
4829 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
4830 EOP_DATA_SEL_VALUE_32BIT
, va
, value
,
4831 cmd_buffer
->gfx9_eop_bug_va
);
4834 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4837 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
4839 VkPipelineStageFlags stageMask
)
4841 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4842 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4844 write_event(cmd_buffer
, event
, stageMask
, 1);
4847 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
4849 VkPipelineStageFlags stageMask
)
4851 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4852 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4854 write_event(cmd_buffer
, event
, stageMask
, 0);
4857 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
4858 uint32_t eventCount
,
4859 const VkEvent
* pEvents
,
4860 VkPipelineStageFlags srcStageMask
,
4861 VkPipelineStageFlags dstStageMask
,
4862 uint32_t memoryBarrierCount
,
4863 const VkMemoryBarrier
* pMemoryBarriers
,
4864 uint32_t bufferMemoryBarrierCount
,
4865 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4866 uint32_t imageMemoryBarrierCount
,
4867 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4869 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4870 struct radv_barrier_info info
;
4872 info
.eventCount
= eventCount
;
4873 info
.pEvents
= pEvents
;
4874 info
.srcStageMask
= 0;
4876 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
4877 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4878 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
4882 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
4883 uint32_t deviceMask
)
4888 /* VK_EXT_conditional_rendering */
4889 void radv_CmdBeginConditionalRenderingEXT(
4890 VkCommandBuffer commandBuffer
,
4891 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
4893 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4894 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
4895 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4896 bool draw_visible
= true;
4897 uint64_t pred_value
= 0;
4898 uint64_t va
, new_va
;
4899 unsigned pred_offset
;
4901 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
4903 /* By default, if the 32-bit value at offset in buffer memory is zero,
4904 * then the rendering commands are discarded, otherwise they are
4905 * executed as normal. If the inverted flag is set, all commands are
4906 * discarded if the value is non zero.
4908 if (pConditionalRenderingBegin
->flags
&
4909 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
4910 draw_visible
= false;
4913 si_emit_cache_flush(cmd_buffer
);
4915 /* From the Vulkan spec 1.1.107:
4917 * "If the 32-bit value at offset in buffer memory is zero, then the
4918 * rendering commands are discarded, otherwise they are executed as
4919 * normal. If the value of the predicate in buffer memory changes while
4920 * conditional rendering is active, the rendering commands may be
4921 * discarded in an implementation-dependent way. Some implementations
4922 * may latch the value of the predicate upon beginning conditional
4923 * rendering while others may read it before every rendering command."
4925 * But, the AMD hardware treats the predicate as a 64-bit value which
4926 * means we need a workaround in the driver. Luckily, it's not required
4927 * to support if the value changes when predication is active.
4929 * The workaround is as follows:
4930 * 1) allocate a 64-value in the upload BO and initialize it to 0
4931 * 2) copy the 32-bit predicate value to the upload BO
4932 * 3) use the new allocated VA address for predication
4934 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
4935 * in ME (+ sync PFP) instead of PFP.
4937 radv_cmd_buffer_upload_data(cmd_buffer
, 8, 16, &pred_value
, &pred_offset
);
4939 new_va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
) + pred_offset
;
4941 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
4942 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
4943 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
4944 COPY_DATA_WR_CONFIRM
);
4945 radeon_emit(cs
, va
);
4946 radeon_emit(cs
, va
>> 32);
4947 radeon_emit(cs
, new_va
);
4948 radeon_emit(cs
, new_va
>> 32);
4950 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
4953 /* Enable predication for this command buffer. */
4954 si_emit_set_predication_state(cmd_buffer
, draw_visible
, new_va
);
4955 cmd_buffer
->state
.predicating
= true;
4957 /* Store conditional rendering user info. */
4958 cmd_buffer
->state
.predication_type
= draw_visible
;
4959 cmd_buffer
->state
.predication_va
= new_va
;
4962 void radv_CmdEndConditionalRenderingEXT(
4963 VkCommandBuffer commandBuffer
)
4965 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4967 /* Disable predication for this command buffer. */
4968 si_emit_set_predication_state(cmd_buffer
, false, 0);
4969 cmd_buffer
->state
.predicating
= false;
4971 /* Reset conditional rendering user info. */
4972 cmd_buffer
->state
.predication_type
= -1;
4973 cmd_buffer
->state
.predication_va
= 0;
4976 /* VK_EXT_transform_feedback */
4977 void radv_CmdBindTransformFeedbackBuffersEXT(
4978 VkCommandBuffer commandBuffer
,
4979 uint32_t firstBinding
,
4980 uint32_t bindingCount
,
4981 const VkBuffer
* pBuffers
,
4982 const VkDeviceSize
* pOffsets
,
4983 const VkDeviceSize
* pSizes
)
4985 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4986 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
4987 uint8_t enabled_mask
= 0;
4989 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
4990 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
4991 uint32_t idx
= firstBinding
+ i
;
4993 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
4994 sb
[idx
].offset
= pOffsets
[i
];
4995 sb
[idx
].size
= pSizes
[i
];
4997 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
4998 sb
[idx
].buffer
->bo
);
5000 enabled_mask
|= 1 << idx
;
5003 cmd_buffer
->state
.streamout
.enabled_mask
|= enabled_mask
;
5005 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
5009 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
5011 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5012 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5014 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
5016 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
5017 S_028B94_RAST_STREAM(0) |
5018 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
5019 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
5020 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
5021 radeon_emit(cs
, so
->hw_enabled_mask
&
5022 so
->enabled_stream_buffers_mask
);
5024 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5028 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
5030 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5031 bool old_streamout_enabled
= so
->streamout_enabled
;
5032 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
5034 so
->streamout_enabled
= enable
;
5036 so
->hw_enabled_mask
= so
->enabled_mask
|
5037 (so
->enabled_mask
<< 4) |
5038 (so
->enabled_mask
<< 8) |
5039 (so
->enabled_mask
<< 12);
5041 if ((old_streamout_enabled
!= so
->streamout_enabled
) ||
5042 (old_hw_enabled_mask
!= so
->hw_enabled_mask
))
5043 radv_emit_streamout_enable(cmd_buffer
);
5046 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
5048 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5049 unsigned reg_strmout_cntl
;
5051 /* The register is at different places on different ASICs. */
5052 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
5053 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
5054 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
5056 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
5057 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
5060 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
5061 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
5063 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
5064 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
5065 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
5067 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5068 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5069 radeon_emit(cs
, 4); /* poll interval */
5072 void radv_CmdBeginTransformFeedbackEXT(
5073 VkCommandBuffer commandBuffer
,
5074 uint32_t firstCounterBuffer
,
5075 uint32_t counterBufferCount
,
5076 const VkBuffer
* pCounterBuffers
,
5077 const VkDeviceSize
* pCounterBufferOffsets
)
5079 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5080 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5081 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5082 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5085 radv_flush_vgt_streamout(cmd_buffer
);
5087 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5088 for_each_bit(i
, so
->enabled_mask
) {
5089 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5090 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5091 counter_buffer_idx
= -1;
5093 /* AMD GCN binds streamout buffers as shader resources.
5094 * VGT only counts primitives and tells the shader through
5097 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
5098 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
5099 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
5101 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5103 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
5104 /* The array of counter buffers is optional. */
5105 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5106 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
5108 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5111 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5112 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5113 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5114 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
5115 radeon_emit(cs
, 0); /* unused */
5116 radeon_emit(cs
, 0); /* unused */
5117 radeon_emit(cs
, va
); /* src address lo */
5118 radeon_emit(cs
, va
>> 32); /* src address hi */
5120 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5122 /* Start from the beginning. */
5123 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5124 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5125 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5126 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
5127 radeon_emit(cs
, 0); /* unused */
5128 radeon_emit(cs
, 0); /* unused */
5129 radeon_emit(cs
, 0); /* unused */
5130 radeon_emit(cs
, 0); /* unused */
5134 radv_set_streamout_enable(cmd_buffer
, true);
5137 void radv_CmdEndTransformFeedbackEXT(
5138 VkCommandBuffer commandBuffer
,
5139 uint32_t firstCounterBuffer
,
5140 uint32_t counterBufferCount
,
5141 const VkBuffer
* pCounterBuffers
,
5142 const VkDeviceSize
* pCounterBufferOffsets
)
5144 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5145 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5146 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5149 radv_flush_vgt_streamout(cmd_buffer
);
5151 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5152 for_each_bit(i
, so
->enabled_mask
) {
5153 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5154 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5155 counter_buffer_idx
= -1;
5157 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
5158 /* The array of counters buffer is optional. */
5159 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5160 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
5162 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5164 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5165 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5166 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5167 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
5168 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
5169 radeon_emit(cs
, va
); /* dst address lo */
5170 radeon_emit(cs
, va
>> 32); /* dst address hi */
5171 radeon_emit(cs
, 0); /* unused */
5172 radeon_emit(cs
, 0); /* unused */
5174 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5177 /* Deactivate transform feedback by zeroing the buffer size.
5178 * The counters (primitives generated, primitives emitted) may
5179 * be enabled even if there is not buffer bound. This ensures
5180 * that the primitives-emitted query won't increment.
5182 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
5184 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5187 radv_set_streamout_enable(cmd_buffer
, false);
5190 void radv_CmdDrawIndirectByteCountEXT(
5191 VkCommandBuffer commandBuffer
,
5192 uint32_t instanceCount
,
5193 uint32_t firstInstance
,
5194 VkBuffer _counterBuffer
,
5195 VkDeviceSize counterBufferOffset
,
5196 uint32_t counterOffset
,
5197 uint32_t vertexStride
)
5199 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5200 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
5201 struct radv_draw_info info
= {};
5203 info
.instance_count
= instanceCount
;
5204 info
.first_instance
= firstInstance
;
5205 info
.strmout_buffer
= counterBuffer
;
5206 info
.strmout_buffer_offset
= counterBufferOffset
;
5207 info
.stride
= vertexStride
;
5209 radv_draw(cmd_buffer
, &info
);