2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
40 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
41 struct radv_image
*image
,
42 VkImageLayout src_layout
,
43 VkImageLayout dst_layout
,
46 const VkImageSubresourceRange
*range
,
47 VkImageAspectFlags pending_clears
);
49 const struct radv_dynamic_state default_dynamic_state
= {
62 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
67 .stencil_compare_mask
= {
71 .stencil_write_mask
= {
75 .stencil_reference
= {
82 radv_dynamic_state_copy(struct radv_dynamic_state
*dest
,
83 const struct radv_dynamic_state
*src
,
86 /* Make sure to copy the number of viewports/scissors because they can
87 * only be specified at pipeline creation time.
89 dest
->viewport
.count
= src
->viewport
.count
;
90 dest
->scissor
.count
= src
->scissor
.count
;
92 if (copy_mask
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
93 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
97 if (copy_mask
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
98 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
102 if (copy_mask
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
))
103 dest
->line_width
= src
->line_width
;
105 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
))
106 dest
->depth_bias
= src
->depth_bias
;
108 if (copy_mask
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
109 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
111 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
))
112 dest
->depth_bounds
= src
->depth_bounds
;
114 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
))
115 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
117 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
))
118 dest
->stencil_write_mask
= src
->stencil_write_mask
;
120 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
))
121 dest
->stencil_reference
= src
->stencil_reference
;
124 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
126 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
127 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
130 enum ring_type
radv_queue_family_to_ring(int f
) {
132 case RADV_QUEUE_GENERAL
:
134 case RADV_QUEUE_COMPUTE
:
136 case RADV_QUEUE_TRANSFER
:
139 unreachable("Unknown queue family");
143 static VkResult
radv_create_cmd_buffer(
144 struct radv_device
* device
,
145 struct radv_cmd_pool
* pool
,
146 VkCommandBufferLevel level
,
147 VkCommandBuffer
* pCommandBuffer
)
149 struct radv_cmd_buffer
*cmd_buffer
;
151 cmd_buffer
= vk_alloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
152 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
153 if (cmd_buffer
== NULL
)
154 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
156 memset(cmd_buffer
, 0, sizeof(*cmd_buffer
));
157 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
158 cmd_buffer
->device
= device
;
159 cmd_buffer
->pool
= pool
;
160 cmd_buffer
->level
= level
;
163 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
164 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
167 /* Init the pool_link so we can safefly call list_del when we destroy
170 list_inithead(&cmd_buffer
->pool_link
);
171 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
174 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
176 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
177 if (!cmd_buffer
->cs
) {
178 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
179 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
182 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
184 cmd_buffer
->upload
.offset
= 0;
185 cmd_buffer
->upload
.size
= 0;
186 list_inithead(&cmd_buffer
->upload
.list
);
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
194 list_del(&cmd_buffer
->pool_link
);
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
197 &cmd_buffer
->upload
.list
, list
) {
198 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
203 if (cmd_buffer
->upload
.upload_bo
)
204 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
205 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
206 free(cmd_buffer
->push_descriptors
.set
.mapped_ptr
);
207 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
211 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
214 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
216 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
217 &cmd_buffer
->upload
.list
, list
) {
218 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
223 cmd_buffer
->push_constant_stages
= 0;
224 cmd_buffer
->scratch_size_needed
= 0;
225 cmd_buffer
->compute_scratch_size_needed
= 0;
226 cmd_buffer
->esgs_ring_size_needed
= 0;
227 cmd_buffer
->gsvs_ring_size_needed
= 0;
228 cmd_buffer
->tess_rings_needed
= false;
229 cmd_buffer
->sample_positions_needed
= false;
231 if (cmd_buffer
->upload
.upload_bo
)
232 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
,
233 cmd_buffer
->upload
.upload_bo
, 8);
234 cmd_buffer
->upload
.offset
= 0;
236 cmd_buffer
->record_result
= VK_SUCCESS
;
238 cmd_buffer
->ring_offsets_idx
= -1;
240 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
242 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 0,
243 &cmd_buffer
->gfx9_fence_offset
,
245 cmd_buffer
->gfx9_fence_bo
= cmd_buffer
->upload
.upload_bo
;
248 return cmd_buffer
->record_result
;
252 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
256 struct radeon_winsys_bo
*bo
;
257 struct radv_cmd_buffer_upload
*upload
;
258 struct radv_device
*device
= cmd_buffer
->device
;
260 new_size
= MAX2(min_needed
, 16 * 1024);
261 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
263 bo
= device
->ws
->buffer_create(device
->ws
,
266 RADEON_FLAG_CPU_ACCESS
);
269 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
273 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, bo
, 8);
274 if (cmd_buffer
->upload
.upload_bo
) {
275 upload
= malloc(sizeof(*upload
));
278 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
279 device
->ws
->buffer_destroy(bo
);
283 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
284 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
287 cmd_buffer
->upload
.upload_bo
= bo
;
288 cmd_buffer
->upload
.size
= new_size
;
289 cmd_buffer
->upload
.offset
= 0;
290 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
292 if (!cmd_buffer
->upload
.map
) {
293 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
301 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
304 unsigned *out_offset
,
307 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
308 if (offset
+ size
> cmd_buffer
->upload
.size
) {
309 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
314 *out_offset
= offset
;
315 *ptr
= cmd_buffer
->upload
.map
+ offset
;
317 cmd_buffer
->upload
.offset
= offset
+ size
;
322 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
323 unsigned size
, unsigned alignment
,
324 const void *data
, unsigned *out_offset
)
328 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
329 out_offset
, (void **)&ptr
))
333 memcpy(ptr
, data
, size
);
339 radv_emit_write_data_packet(struct radeon_winsys_cs
*cs
, uint64_t va
,
340 unsigned count
, const uint32_t *data
)
342 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
343 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
344 S_370_WR_CONFIRM(1) |
345 S_370_ENGINE_SEL(V_370_ME
));
347 radeon_emit(cs
, va
>> 32);
348 radeon_emit_array(cs
, data
, count
);
351 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
353 struct radv_device
*device
= cmd_buffer
->device
;
354 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
357 if (!device
->trace_bo
)
360 va
= radv_buffer_get_va(device
->trace_bo
);
361 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
364 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 7);
366 ++cmd_buffer
->state
.trace_id
;
367 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
368 radv_emit_write_data_packet(cs
, va
, 1, &cmd_buffer
->state
.trace_id
);
369 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
370 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
374 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
)
376 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
377 enum radv_cmd_flush_bits flags
;
379 /* Force wait for graphics/compute engines to be idle. */
380 flags
= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
381 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
383 si_cs_emit_cache_flush(cmd_buffer
->cs
, false,
384 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
386 radv_cmd_buffer_uses_mec(cmd_buffer
),
390 radv_cmd_buffer_trace_emit(cmd_buffer
);
394 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
395 struct radv_pipeline
*pipeline
, enum ring_type ring
)
397 struct radv_device
*device
= cmd_buffer
->device
;
398 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
402 if (!device
->trace_bo
)
405 va
= radv_buffer_get_va(device
->trace_bo
);
415 assert(!"invalid ring type");
418 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
421 data
[0] = (uintptr_t)pipeline
;
422 data
[1] = (uintptr_t)pipeline
>> 32;
424 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
425 radv_emit_write_data_packet(cs
, va
, 2, data
);
429 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
431 struct radv_device
*device
= cmd_buffer
->device
;
432 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
433 uint32_t data
[MAX_SETS
* 2] = {};
436 if (!device
->trace_bo
)
439 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
441 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
442 cmd_buffer
->cs
, 4 + MAX_SETS
* 2);
444 for (int i
= 0; i
< MAX_SETS
; i
++) {
445 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
449 data
[i
* 2] = (uintptr_t)set
;
450 data
[i
* 2 + 1] = (uintptr_t)set
>> 32;
453 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
454 radv_emit_write_data_packet(cs
, va
, MAX_SETS
* 2, data
);
458 radv_emit_graphics_blend_state(struct radv_cmd_buffer
*cmd_buffer
,
459 struct radv_pipeline
*pipeline
)
461 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028780_CB_BLEND0_CONTROL
, 8);
462 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.cb_blend_control
,
464 radeon_set_context_reg(cmd_buffer
->cs
, R_028808_CB_COLOR_CONTROL
, pipeline
->graphics
.blend
.cb_color_control
);
465 radeon_set_context_reg(cmd_buffer
->cs
, R_028B70_DB_ALPHA_TO_MASK
, pipeline
->graphics
.blend
.db_alpha_to_mask
);
467 if (cmd_buffer
->device
->physical_device
->has_rbplus
) {
469 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
470 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.sx_mrt_blend_opt
, 8);
472 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
473 radeon_emit(cmd_buffer
->cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
474 radeon_emit(cmd_buffer
->cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
475 radeon_emit(cmd_buffer
->cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
480 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer
*cmd_buffer
,
481 struct radv_pipeline
*pipeline
)
483 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
484 radeon_set_context_reg(cmd_buffer
->cs
, R_028800_DB_DEPTH_CONTROL
, ds
->db_depth_control
);
485 radeon_set_context_reg(cmd_buffer
->cs
, R_02842C_DB_STENCIL_CONTROL
, ds
->db_stencil_control
);
487 radeon_set_context_reg(cmd_buffer
->cs
, R_028000_DB_RENDER_CONTROL
, ds
->db_render_control
);
488 radeon_set_context_reg(cmd_buffer
->cs
, R_028010_DB_RENDER_OVERRIDE2
, ds
->db_render_override2
);
491 struct ac_userdata_info
*
492 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
493 gl_shader_stage stage
,
496 return &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.shader_data
[idx
];
500 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
501 struct radv_pipeline
*pipeline
,
502 gl_shader_stage stage
,
503 int idx
, uint64_t va
)
505 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
506 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
507 if (loc
->sgpr_idx
== -1)
509 assert(loc
->num_sgprs
== 2);
510 assert(!loc
->indirect
);
511 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 2);
512 radeon_emit(cmd_buffer
->cs
, va
);
513 radeon_emit(cmd_buffer
->cs
, va
>> 32);
517 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
518 struct radv_pipeline
*pipeline
)
520 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
521 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
522 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
524 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
525 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[0]);
526 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[1]);
528 radeon_set_context_reg(cmd_buffer
->cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
529 radeon_set_context_reg(cmd_buffer
->cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
531 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
534 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
535 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
536 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
538 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
540 /* GFX9: Flush DFSM when the AA mode changes. */
541 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
542 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
543 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
545 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
) {
547 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_FRAGMENT
, AC_UD_PS_SAMPLE_POS_OFFSET
);
548 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
549 if (loc
->sgpr_idx
== -1)
551 assert(loc
->num_sgprs
== 1);
552 assert(!loc
->indirect
);
553 switch (num_samples
) {
571 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, offset
);
572 cmd_buffer
->sample_positions_needed
= true;
577 radv_emit_graphics_raster_state(struct radv_cmd_buffer
*cmd_buffer
,
578 struct radv_pipeline
*pipeline
)
580 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
582 radeon_set_context_reg(cmd_buffer
->cs
, R_028810_PA_CL_CLIP_CNTL
,
583 raster
->pa_cl_clip_cntl
);
584 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
585 raster
->spi_interp_control
);
586 radeon_set_context_reg(cmd_buffer
->cs
, R_028BE4_PA_SU_VTX_CNTL
,
587 raster
->pa_su_vtx_cntl
);
588 radeon_set_context_reg(cmd_buffer
->cs
, R_028814_PA_SU_SC_MODE_CNTL
,
589 raster
->pa_su_sc_mode_cntl
);
593 radv_emit_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
596 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
597 si_cp_dma_prefetch(cmd_buffer
, va
, size
);
601 radv_emit_hw_vs(struct radv_cmd_buffer
*cmd_buffer
,
602 struct radv_pipeline
*pipeline
,
603 struct radv_shader_variant
*shader
,
604 struct ac_vs_output_info
*outinfo
)
606 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
607 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
608 unsigned export_count
;
610 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
611 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
613 export_count
= MAX2(1, outinfo
->param_exports
);
614 radeon_set_context_reg(cmd_buffer
->cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
615 S_0286C4_VS_EXPORT_COUNT(export_count
- 1));
617 radeon_set_context_reg(cmd_buffer
->cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
618 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
619 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
620 V_02870C_SPI_SHADER_4COMP
:
621 V_02870C_SPI_SHADER_NONE
) |
622 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
623 V_02870C_SPI_SHADER_4COMP
:
624 V_02870C_SPI_SHADER_NONE
) |
625 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
626 V_02870C_SPI_SHADER_4COMP
:
627 V_02870C_SPI_SHADER_NONE
));
630 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
631 radeon_emit(cmd_buffer
->cs
, va
>> 8);
632 radeon_emit(cmd_buffer
->cs
, va
>> 40);
633 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
634 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
636 radeon_set_context_reg(cmd_buffer
->cs
, R_028818_PA_CL_VTE_CNTL
,
637 S_028818_VTX_W0_FMT(1) |
638 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
639 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
640 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
643 radeon_set_context_reg(cmd_buffer
->cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
644 pipeline
->graphics
.pa_cl_vs_out_cntl
);
646 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= VI
)
647 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB4_VGT_REUSE_OFF
,
648 S_028AB4_REUSE_OFF(outinfo
->writes_viewport_index
));
652 radv_emit_hw_es(struct radv_cmd_buffer
*cmd_buffer
,
653 struct radv_shader_variant
*shader
,
654 struct ac_es_output_info
*outinfo
)
656 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
657 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
659 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
660 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
662 radeon_set_context_reg(cmd_buffer
->cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
663 outinfo
->esgs_itemsize
/ 4);
664 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
665 radeon_emit(cmd_buffer
->cs
, va
>> 8);
666 radeon_emit(cmd_buffer
->cs
, va
>> 40);
667 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
668 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
672 radv_emit_hw_ls(struct radv_cmd_buffer
*cmd_buffer
,
673 struct radv_shader_variant
*shader
)
675 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
676 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
677 uint32_t rsrc2
= shader
->rsrc2
;
679 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
680 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
682 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
683 radeon_emit(cmd_buffer
->cs
, va
>> 8);
684 radeon_emit(cmd_buffer
->cs
, va
>> 40);
686 rsrc2
|= S_00B52C_LDS_SIZE(cmd_buffer
->state
.pipeline
->graphics
.tess
.lds_size
);
687 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== CIK
&&
688 cmd_buffer
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
689 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
691 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
692 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
693 radeon_emit(cmd_buffer
->cs
, rsrc2
);
697 radv_emit_hw_hs(struct radv_cmd_buffer
*cmd_buffer
,
698 struct radv_shader_variant
*shader
)
700 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
701 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
703 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
704 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
706 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
707 radeon_emit(cmd_buffer
->cs
, va
>> 8);
708 radeon_emit(cmd_buffer
->cs
, va
>> 40);
709 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
710 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
714 radv_emit_vertex_shader(struct radv_cmd_buffer
*cmd_buffer
,
715 struct radv_pipeline
*pipeline
)
717 struct radv_shader_variant
*vs
;
719 assert (pipeline
->shaders
[MESA_SHADER_VERTEX
]);
721 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
723 if (vs
->info
.vs
.as_ls
)
724 radv_emit_hw_ls(cmd_buffer
, vs
);
725 else if (vs
->info
.vs
.as_es
)
726 radv_emit_hw_es(cmd_buffer
, vs
, &vs
->info
.vs
.es_info
);
728 radv_emit_hw_vs(cmd_buffer
, pipeline
, vs
, &vs
->info
.vs
.outinfo
);
730 radeon_set_context_reg(cmd_buffer
->cs
, R_028A84_VGT_PRIMITIVEID_EN
, pipeline
->graphics
.vgt_primitiveid_en
);
735 radv_emit_tess_shaders(struct radv_cmd_buffer
*cmd_buffer
,
736 struct radv_pipeline
*pipeline
)
738 if (!radv_pipeline_has_tess(pipeline
))
741 struct radv_shader_variant
*tes
, *tcs
;
743 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
744 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
746 if (tes
->info
.tes
.as_es
)
747 radv_emit_hw_es(cmd_buffer
, tes
, &tes
->info
.tes
.es_info
);
749 radv_emit_hw_vs(cmd_buffer
, pipeline
, tes
, &tes
->info
.tes
.outinfo
);
751 radv_emit_hw_hs(cmd_buffer
, tcs
);
753 radeon_set_context_reg(cmd_buffer
->cs
, R_028B6C_VGT_TF_PARAM
,
754 pipeline
->graphics
.tess
.tf_param
);
756 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
757 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
758 pipeline
->graphics
.tess
.ls_hs_config
);
760 radeon_set_context_reg(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
,
761 pipeline
->graphics
.tess
.ls_hs_config
);
763 struct ac_userdata_info
*loc
;
765 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_CTRL
, AC_UD_TCS_OFFCHIP_LAYOUT
);
766 if (loc
->sgpr_idx
!= -1) {
767 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
768 assert(loc
->num_sgprs
== 4);
769 assert(!loc
->indirect
);
770 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 4);
771 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.offchip_layout
);
772 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_offsets
);
773 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_layout
|
774 pipeline
->graphics
.tess
.num_tcs_input_cp
<< 26);
775 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_in_layout
);
778 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_EVAL
, AC_UD_TES_OFFCHIP_LAYOUT
);
779 if (loc
->sgpr_idx
!= -1) {
780 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
781 assert(loc
->num_sgprs
== 1);
782 assert(!loc
->indirect
);
784 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
785 pipeline
->graphics
.tess
.offchip_layout
);
788 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
, AC_UD_VS_LS_TCS_IN_LAYOUT
);
789 if (loc
->sgpr_idx
!= -1) {
790 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
791 assert(loc
->num_sgprs
== 1);
792 assert(!loc
->indirect
);
794 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
795 pipeline
->graphics
.tess
.tcs_in_layout
);
800 radv_emit_geometry_shader(struct radv_cmd_buffer
*cmd_buffer
,
801 struct radv_pipeline
*pipeline
)
803 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
804 struct radv_shader_variant
*gs
;
807 radeon_set_context_reg(cmd_buffer
->cs
, R_028A40_VGT_GS_MODE
, pipeline
->graphics
.vgt_gs_mode
);
809 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
813 uint32_t gsvs_itemsize
= gs
->info
.gs
.max_gsvs_emit_size
>> 2;
815 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
816 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
817 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
818 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
820 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
);
822 radeon_set_context_reg(cmd_buffer
->cs
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs
->info
.gs
.vertices_out
);
824 uint32_t gs_vert_itemsize
= gs
->info
.gs
.gsvs_vertex_size
;
825 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
826 radeon_emit(cmd_buffer
->cs
, gs_vert_itemsize
>> 2);
827 radeon_emit(cmd_buffer
->cs
, 0);
828 radeon_emit(cmd_buffer
->cs
, 0);
829 radeon_emit(cmd_buffer
->cs
, 0);
831 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
832 radeon_set_context_reg(cmd_buffer
->cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
833 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
834 S_028B90_ENABLE(gs_num_invocations
> 0));
836 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
837 ws
->cs_add_buffer(cmd_buffer
->cs
, gs
->bo
, 8);
838 radv_emit_prefetch(cmd_buffer
, va
, gs
->code_size
);
840 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
841 radeon_emit(cmd_buffer
->cs
, va
>> 8);
842 radeon_emit(cmd_buffer
->cs
, va
>> 40);
843 radeon_emit(cmd_buffer
->cs
, gs
->rsrc1
);
844 radeon_emit(cmd_buffer
->cs
, gs
->rsrc2
);
846 radv_emit_hw_vs(cmd_buffer
, pipeline
, pipeline
->gs_copy_shader
, &pipeline
->gs_copy_shader
->info
.vs
.outinfo
);
848 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
849 AC_UD_GS_VS_RING_STRIDE_ENTRIES
);
850 if (loc
->sgpr_idx
!= -1) {
851 uint32_t stride
= gs
->info
.gs
.max_gsvs_emit_size
;
852 uint32_t num_entries
= 64;
853 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
856 num_entries
*= stride
;
858 stride
= S_008F04_STRIDE(stride
);
859 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
+ loc
->sgpr_idx
* 4, 2);
860 radeon_emit(cmd_buffer
->cs
, stride
);
861 radeon_emit(cmd_buffer
->cs
, num_entries
);
866 radv_emit_fragment_shader(struct radv_cmd_buffer
*cmd_buffer
,
867 struct radv_pipeline
*pipeline
)
869 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
870 struct radv_shader_variant
*ps
;
872 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
873 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
874 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
876 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
877 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
878 ws
->cs_add_buffer(cmd_buffer
->cs
, ps
->bo
, 8);
879 radv_emit_prefetch(cmd_buffer
, va
, ps
->code_size
);
881 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
882 radeon_emit(cmd_buffer
->cs
, va
>> 8);
883 radeon_emit(cmd_buffer
->cs
, va
>> 40);
884 radeon_emit(cmd_buffer
->cs
, ps
->rsrc1
);
885 radeon_emit(cmd_buffer
->cs
, ps
->rsrc2
);
887 radeon_set_context_reg(cmd_buffer
->cs
, R_02880C_DB_SHADER_CONTROL
,
888 pipeline
->graphics
.db_shader_control
);
890 radeon_set_context_reg(cmd_buffer
->cs
, R_0286CC_SPI_PS_INPUT_ENA
,
891 ps
->config
.spi_ps_input_ena
);
893 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
894 ps
->config
.spi_ps_input_addr
);
896 if (ps
->info
.info
.ps
.force_persample
)
897 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
899 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D8_SPI_PS_IN_CONTROL
,
900 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
902 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
904 radeon_set_context_reg(cmd_buffer
->cs
, R_028710_SPI_SHADER_Z_FORMAT
,
905 pipeline
->graphics
.shader_z_format
);
907 radeon_set_context_reg(cmd_buffer
->cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
909 radeon_set_context_reg(cmd_buffer
->cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
910 radeon_set_context_reg(cmd_buffer
->cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
912 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
914 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
915 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
918 if (pipeline
->graphics
.ps_input_cntl_num
) {
919 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028644_SPI_PS_INPUT_CNTL_0
, pipeline
->graphics
.ps_input_cntl_num
);
920 for (unsigned i
= 0; i
< pipeline
->graphics
.ps_input_cntl_num
; i
++) {
921 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.ps_input_cntl
[i
]);
927 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer
*cmd_buffer
,
928 struct radv_pipeline
*pipeline
)
930 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
932 if (cmd_buffer
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
)
935 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
936 pipeline
->graphics
.vtx_reuse_depth
);
940 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
942 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
944 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
947 radv_emit_graphics_depth_stencil_state(cmd_buffer
, pipeline
);
948 radv_emit_graphics_blend_state(cmd_buffer
, pipeline
);
949 radv_emit_graphics_raster_state(cmd_buffer
, pipeline
);
950 radv_update_multisample_state(cmd_buffer
, pipeline
);
951 radv_emit_vertex_shader(cmd_buffer
, pipeline
);
952 radv_emit_tess_shaders(cmd_buffer
, pipeline
);
953 radv_emit_geometry_shader(cmd_buffer
, pipeline
);
954 radv_emit_fragment_shader(cmd_buffer
, pipeline
);
955 radv_emit_vgt_vertex_reuse(cmd_buffer
, pipeline
);
957 cmd_buffer
->scratch_size_needed
=
958 MAX2(cmd_buffer
->scratch_size_needed
,
959 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
961 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E8_SPI_TMPRING_SIZE
,
962 S_0286E8_WAVES(pipeline
->max_waves
) |
963 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
965 if (!cmd_buffer
->state
.emitted_pipeline
||
966 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
967 pipeline
->graphics
.can_use_guardband
)
968 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
970 radeon_set_context_reg(cmd_buffer
->cs
, R_028B54_VGT_SHADER_STAGES_EN
, pipeline
->graphics
.vgt_shader_stages_en
);
972 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
973 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, pipeline
->graphics
.prim
);
975 radeon_set_config_reg(cmd_buffer
->cs
, R_008958_VGT_PRIMITIVE_TYPE
, pipeline
->graphics
.prim
);
977 radeon_set_context_reg(cmd_buffer
->cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, pipeline
->graphics
.gs_out
);
979 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
981 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
985 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
987 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
988 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
992 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
994 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
996 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
997 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
998 si_emit_cache_flush(cmd_buffer
);
1000 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1001 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1002 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1003 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1004 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
,
1005 cmd_buffer
->state
.pipeline
->graphics
.ms
.pa_sc_mode_cntl_0
| S_028A48_VPORT_SCISSOR_ENABLE(count
? 1 : 0));
1009 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1011 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1013 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1014 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1018 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1020 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1022 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1023 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1027 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1029 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1031 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1032 R_028430_DB_STENCILREFMASK
, 2);
1033 radeon_emit(cmd_buffer
->cs
,
1034 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1035 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1036 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1037 S_028430_STENCILOPVAL(1));
1038 radeon_emit(cmd_buffer
->cs
,
1039 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1040 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1041 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1042 S_028434_STENCILOPVAL_BF(1));
1046 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1048 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1050 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1051 fui(d
->depth_bounds
.min
));
1052 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1053 fui(d
->depth_bounds
.max
));
1057 radv_emit_depth_biais(struct radv_cmd_buffer
*cmd_buffer
)
1059 struct radv_raster_state
*raster
= &cmd_buffer
->state
.pipeline
->graphics
.raster
;
1060 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1061 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1062 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1064 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster
->pa_su_sc_mode_cntl
)) {
1065 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1066 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1067 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1068 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1069 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1070 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1071 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1076 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1078 struct radv_color_buffer_info
*cb
)
1080 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
1082 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1083 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1084 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1085 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
>> 32);
1086 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1087 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1088 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
1089 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1090 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1091 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1092 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
>> 32);
1093 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1094 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
>> 32);
1096 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1097 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1098 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
>> 32);
1100 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1103 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1104 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1105 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1106 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1107 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1108 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
1109 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1110 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1111 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1112 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1113 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1114 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1116 if (is_vi
) { /* DCC BASE */
1117 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1123 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1124 struct radv_ds_buffer_info
*ds
,
1125 struct radv_image
*image
,
1126 VkImageLayout layout
)
1128 uint32_t db_z_info
= ds
->db_z_info
;
1129 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1131 if (!radv_layout_has_htile(image
, layout
,
1132 radv_image_queue_family_mask(image
,
1133 cmd_buffer
->queue_family_index
,
1134 cmd_buffer
->queue_family_index
))) {
1135 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1136 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1139 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1140 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1143 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1144 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1145 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1146 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1147 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1149 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1150 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1151 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1152 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1153 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32); /* DB_Z_READ_BASE_HI */
1154 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1155 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
1156 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1157 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
>> 32); /* DB_Z_WRITE_BASE_HI */
1158 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1159 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
1161 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1162 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1163 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1165 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1167 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1168 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1169 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1170 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1171 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1172 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1173 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1174 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1175 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1176 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1180 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1181 ds
->pa_su_poly_offset_db_fmt_cntl
);
1185 radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1186 struct radv_image
*image
,
1187 VkClearDepthStencilValue ds_clear_value
,
1188 VkImageAspectFlags aspects
)
1190 uint64_t va
= radv_buffer_get_va(image
->bo
);
1191 va
+= image
->offset
+ image
->clear_value_offset
;
1192 unsigned reg_offset
= 0, reg_count
= 0;
1194 if (!image
->surface
.htile_size
|| !aspects
)
1197 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1203 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1206 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1208 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
1209 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1210 S_370_WR_CONFIRM(1) |
1211 S_370_ENGINE_SEL(V_370_PFP
));
1212 radeon_emit(cmd_buffer
->cs
, va
);
1213 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1214 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1215 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
);
1216 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1217 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
));
1219 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
, reg_count
);
1220 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1221 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
); /* R_028028_DB_STENCIL_CLEAR */
1222 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1223 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
)); /* R_02802C_DB_DEPTH_CLEAR */
1227 radv_load_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1228 struct radv_image
*image
)
1230 uint64_t va
= radv_buffer_get_va(image
->bo
);
1231 va
+= image
->offset
+ image
->clear_value_offset
;
1233 if (!image
->surface
.htile_size
)
1236 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1238 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1239 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1240 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1241 COPY_DATA_COUNT_SEL
);
1242 radeon_emit(cmd_buffer
->cs
, va
);
1243 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1244 radeon_emit(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
>> 2);
1245 radeon_emit(cmd_buffer
->cs
, 0);
1247 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1248 radeon_emit(cmd_buffer
->cs
, 0);
1252 *with DCC some colors don't require CMASK elimiation before being
1253 * used as a texture. This sets a predicate value to determine if the
1254 * cmask eliminate is required.
1257 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1258 struct radv_image
*image
,
1261 uint64_t pred_val
= value
;
1262 uint64_t va
= radv_buffer_get_va(image
->bo
);
1263 va
+= image
->offset
+ image
->dcc_pred_offset
;
1265 if (!image
->surface
.dcc_size
)
1268 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1270 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1271 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1272 S_370_WR_CONFIRM(1) |
1273 S_370_ENGINE_SEL(V_370_PFP
));
1274 radeon_emit(cmd_buffer
->cs
, va
);
1275 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1276 radeon_emit(cmd_buffer
->cs
, pred_val
);
1277 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1281 radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1282 struct radv_image
*image
,
1284 uint32_t color_values
[2])
1286 uint64_t va
= radv_buffer_get_va(image
->bo
);
1287 va
+= image
->offset
+ image
->clear_value_offset
;
1289 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1292 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1294 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1295 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1296 S_370_WR_CONFIRM(1) |
1297 S_370_ENGINE_SEL(V_370_PFP
));
1298 radeon_emit(cmd_buffer
->cs
, va
);
1299 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1300 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1301 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1303 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c, 2);
1304 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1305 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1309 radv_load_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1310 struct radv_image
*image
,
1313 uint64_t va
= radv_buffer_get_va(image
->bo
);
1314 va
+= image
->offset
+ image
->clear_value_offset
;
1316 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1319 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c;
1320 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1322 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1323 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1324 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1325 COPY_DATA_COUNT_SEL
);
1326 radeon_emit(cmd_buffer
->cs
, va
);
1327 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1328 radeon_emit(cmd_buffer
->cs
, reg
>> 2);
1329 radeon_emit(cmd_buffer
->cs
, 0);
1331 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1332 radeon_emit(cmd_buffer
->cs
, 0);
1336 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1339 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1340 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1342 /* this may happen for inherited secondary recording */
1346 for (i
= 0; i
< 8; ++i
) {
1347 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1348 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1349 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1353 int idx
= subpass
->color_attachments
[i
].attachment
;
1354 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1356 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1358 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
1359 radv_emit_fb_color_state(cmd_buffer
, i
, &att
->cb
);
1361 radv_load_color_clear_regs(cmd_buffer
, att
->attachment
->image
, i
);
1364 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1365 int idx
= subpass
->depth_stencil_attachment
.attachment
;
1366 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1367 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1368 struct radv_image
*image
= att
->attachment
->image
;
1369 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1370 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1371 cmd_buffer
->queue_family_index
,
1372 cmd_buffer
->queue_family_index
);
1373 /* We currently don't support writing decompressed HTILE */
1374 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1375 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1377 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1379 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1380 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1381 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1383 radv_load_depth_clear_regs(cmd_buffer
, image
);
1385 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1386 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1388 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1390 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1391 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1393 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1394 S_028208_BR_X(framebuffer
->width
) |
1395 S_028208_BR_Y(framebuffer
->height
));
1397 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1398 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1399 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1403 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1405 uint32_t db_count_control
;
1407 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1408 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1409 db_count_control
= 0;
1411 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1414 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1415 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1416 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1417 S_028004_ZPASS_ENABLE(1) |
1418 S_028004_SLICE_EVEN_ENABLE(1) |
1419 S_028004_SLICE_ODD_ENABLE(1);
1421 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1422 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1426 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1430 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1432 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer
->state
.pipeline
->graphics
.raster
.pa_cl_clip_cntl
))
1435 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1436 radv_emit_viewport(cmd_buffer
);
1438 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1439 radv_emit_scissor(cmd_buffer
);
1441 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
1442 radv_emit_line_width(cmd_buffer
);
1444 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1445 radv_emit_blend_constants(cmd_buffer
);
1447 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1448 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1449 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
1450 radv_emit_stencil(cmd_buffer
);
1452 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
1453 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
))
1454 radv_emit_depth_bounds(cmd_buffer
);
1456 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
1457 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
))
1458 radv_emit_depth_biais(cmd_buffer
);
1460 cmd_buffer
->state
.dirty
= 0;
1464 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1465 struct radv_pipeline
*pipeline
,
1468 gl_shader_stage stage
)
1470 struct ac_userdata_info
*desc_set_loc
= &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.descriptor_sets
[idx
];
1471 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
1473 if (desc_set_loc
->sgpr_idx
== -1 || desc_set_loc
->indirect
)
1476 assert(!desc_set_loc
->indirect
);
1477 assert(desc_set_loc
->num_sgprs
== 2);
1478 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
1479 base_reg
+ desc_set_loc
->sgpr_idx
* 4, 2);
1480 radeon_emit(cmd_buffer
->cs
, va
);
1481 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1485 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1486 VkShaderStageFlags stages
,
1487 struct radv_descriptor_set
*set
,
1490 if (cmd_buffer
->state
.pipeline
) {
1491 radv_foreach_stage(stage
, stages
) {
1492 if (cmd_buffer
->state
.pipeline
->shaders
[stage
])
1493 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1499 if (cmd_buffer
->state
.compute_pipeline
&& (stages
& VK_SHADER_STAGE_COMPUTE_BIT
))
1500 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
1502 MESA_SHADER_COMPUTE
);
1506 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
1508 struct radv_descriptor_set
*set
= &cmd_buffer
->push_descriptors
.set
;
1511 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
1516 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1517 set
->va
+= bo_offset
;
1521 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
)
1523 uint32_t size
= MAX_SETS
* 2 * 4;
1527 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1528 256, &offset
, &ptr
))
1531 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1532 uint32_t *uptr
= ((uint32_t *)ptr
) + i
* 2;
1533 uint64_t set_va
= 0;
1534 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
1537 uptr
[0] = set_va
& 0xffffffff;
1538 uptr
[1] = set_va
>> 32;
1541 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1544 if (cmd_buffer
->state
.pipeline
) {
1545 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1546 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1547 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1549 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1550 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1551 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1553 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1554 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1555 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1557 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1558 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1559 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1561 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1562 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1563 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1566 if (cmd_buffer
->state
.compute_pipeline
)
1567 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1568 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1572 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1573 VkShaderStageFlags stages
)
1577 if (!cmd_buffer
->state
.descriptors_dirty
)
1580 if (cmd_buffer
->state
.push_descriptors_dirty
)
1581 radv_flush_push_descriptors(cmd_buffer
);
1583 if ((cmd_buffer
->state
.pipeline
&& cmd_buffer
->state
.pipeline
->need_indirect_descriptor_sets
) ||
1584 (cmd_buffer
->state
.compute_pipeline
&& cmd_buffer
->state
.compute_pipeline
->need_indirect_descriptor_sets
)) {
1585 radv_flush_indirect_descriptor_sets(cmd_buffer
);
1588 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1590 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1592 for_each_bit(i
, cmd_buffer
->state
.descriptors_dirty
) {
1593 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
1597 radv_emit_descriptor_set_userdata(cmd_buffer
, stages
, set
, i
);
1599 cmd_buffer
->state
.descriptors_dirty
= 0;
1600 cmd_buffer
->state
.push_descriptors_dirty
= false;
1602 radv_save_descriptors(cmd_buffer
);
1604 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1608 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1609 struct radv_pipeline
*pipeline
,
1610 VkShaderStageFlags stages
)
1612 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1617 stages
&= cmd_buffer
->push_constant_stages
;
1618 if (!stages
|| !layout
|| (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1621 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1622 16 * layout
->dynamic_offset_count
,
1623 256, &offset
, &ptr
))
1626 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1627 memcpy((char*)ptr
+ layout
->push_constant_size
, cmd_buffer
->dynamic_buffers
,
1628 16 * layout
->dynamic_offset_count
);
1630 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1633 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1634 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1636 radv_foreach_stage(stage
, stages
) {
1637 if (pipeline
->shaders
[stage
]) {
1638 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1639 AC_UD_PUSH_CONSTANTS
, va
);
1643 cmd_buffer
->push_constant_stages
&= ~stages
;
1644 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1647 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer
*cmd_buffer
,
1650 int32_t primitive_reset_en
= indexed_draw
&& cmd_buffer
->state
.pipeline
->graphics
.prim_restart_enable
;
1652 if (primitive_reset_en
!= cmd_buffer
->state
.last_primitive_reset_en
) {
1653 cmd_buffer
->state
.last_primitive_reset_en
= primitive_reset_en
;
1654 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1655 radeon_set_uconfig_reg(cmd_buffer
->cs
, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
1656 primitive_reset_en
);
1658 radeon_set_context_reg(cmd_buffer
->cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
1659 primitive_reset_en
);
1663 if (primitive_reset_en
) {
1664 uint32_t primitive_reset_index
= cmd_buffer
->state
.index_type
? 0xffffffffu
: 0xffffu
;
1666 if (primitive_reset_index
!= cmd_buffer
->state
.last_primitive_reset_index
) {
1667 cmd_buffer
->state
.last_primitive_reset_index
= primitive_reset_index
;
1668 radeon_set_context_reg(cmd_buffer
->cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
1669 primitive_reset_index
);
1675 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
1677 struct radv_device
*device
= cmd_buffer
->device
;
1679 if ((cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
|| cmd_buffer
->state
.vb_dirty
) &&
1680 cmd_buffer
->state
.pipeline
->vertex_elements
.count
&&
1681 cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.has_vertex_buffers
) {
1682 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
1686 uint32_t count
= velems
->count
;
1689 /* allocate some descriptor state for vertex buffers */
1690 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
1691 &vb_offset
, &vb_ptr
))
1694 for (i
= 0; i
< count
; i
++) {
1695 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
1697 int vb
= velems
->binding
[i
];
1698 struct radv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1699 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
1701 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, buffer
->bo
, 8);
1702 va
= radv_buffer_get_va(buffer
->bo
);
1704 offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
+ velems
->offset
[i
];
1705 va
+= offset
+ buffer
->offset
;
1707 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
1708 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= CIK
&& stride
)
1709 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
1711 desc
[2] = buffer
->size
- offset
;
1712 desc
[3] = velems
->rsrc_word3
[i
];
1715 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1718 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1719 AC_UD_VS_VERTEX_BUFFERS
, va
);
1721 cmd_buffer
->state
.vb_dirty
= false;
1727 radv_cmd_buffer_flush_state(struct radv_cmd_buffer
*cmd_buffer
,
1728 bool indexed_draw
, bool instanced_draw
,
1730 uint32_t draw_vertex_count
)
1732 uint32_t ia_multi_vgt_param
;
1734 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1735 cmd_buffer
->cs
, 4096);
1737 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer
))
1740 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
1741 radv_emit_graphics_pipeline(cmd_buffer
);
1743 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_RENDER_TARGETS
)
1744 radv_emit_framebuffer_state(cmd_buffer
);
1746 ia_multi_vgt_param
= si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
, indirect_draw
, draw_vertex_count
);
1747 if (cmd_buffer
->state
.last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
1748 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1749 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_030960_IA_MULTI_VGT_PARAM
, 4, ia_multi_vgt_param
);
1750 else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
1751 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028AA8_IA_MULTI_VGT_PARAM
, 1, ia_multi_vgt_param
);
1753 radeon_set_context_reg(cmd_buffer
->cs
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
1754 cmd_buffer
->state
.last_ia_multi_vgt_param
= ia_multi_vgt_param
;
1757 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
1759 radv_emit_primitive_reset_state(cmd_buffer
, indexed_draw
);
1761 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
1762 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1763 VK_SHADER_STAGE_ALL_GRAPHICS
);
1765 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1767 si_emit_cache_flush(cmd_buffer
);
1770 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
1771 VkPipelineStageFlags src_stage_mask
)
1773 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
1774 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1775 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1776 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1777 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
1780 if (src_stage_mask
& (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
1781 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
1782 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
1783 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
1784 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
1785 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
1786 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
1787 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1788 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1789 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
1790 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1791 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1792 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
|
1793 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
1794 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
1795 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
)) {
1796 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
1800 static enum radv_cmd_flush_bits
1801 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1802 VkAccessFlags src_flags
)
1804 enum radv_cmd_flush_bits flush_bits
= 0;
1806 for_each_bit(b
, src_flags
) {
1807 switch ((VkAccessFlagBits
)(1 << b
)) {
1808 case VK_ACCESS_SHADER_WRITE_BIT
:
1809 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
1811 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1812 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1813 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1815 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1816 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1817 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1819 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1820 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1821 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1822 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1823 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
1824 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1833 static enum radv_cmd_flush_bits
1834 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1835 VkAccessFlags dst_flags
,
1836 struct radv_image
*image
)
1838 enum radv_cmd_flush_bits flush_bits
= 0;
1840 for_each_bit(b
, dst_flags
) {
1841 switch ((VkAccessFlagBits
)(1 << b
)) {
1842 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1843 case VK_ACCESS_INDEX_READ_BIT
:
1844 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1846 case VK_ACCESS_UNIFORM_READ_BIT
:
1847 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
1849 case VK_ACCESS_SHADER_READ_BIT
:
1850 case VK_ACCESS_TRANSFER_READ_BIT
:
1851 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1852 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
1853 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1855 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
1856 /* TODO: change to image && when the image gets passed
1857 * through from the subpass. */
1858 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
1859 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1860 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1862 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
1863 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
1864 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1865 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1874 static void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
, const struct radv_subpass_barrier
*barrier
)
1876 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
);
1877 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
1878 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
1882 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
1883 VkAttachmentReference att
)
1885 unsigned idx
= att
.attachment
;
1886 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
1887 VkImageSubresourceRange range
;
1888 range
.aspectMask
= 0;
1889 range
.baseMipLevel
= view
->base_mip
;
1890 range
.levelCount
= 1;
1891 range
.baseArrayLayer
= view
->base_layer
;
1892 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
1894 radv_handle_image_transition(cmd_buffer
,
1896 cmd_buffer
->state
.attachments
[idx
].current_layout
,
1897 att
.layout
, 0, 0, &range
,
1898 cmd_buffer
->state
.attachments
[idx
].pending_clear_aspects
);
1900 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
1906 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1907 const struct radv_subpass
*subpass
, bool transitions
)
1910 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
1912 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1913 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1914 radv_handle_subpass_image_transition(cmd_buffer
,
1915 subpass
->color_attachments
[i
]);
1918 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
1919 radv_handle_subpass_image_transition(cmd_buffer
,
1920 subpass
->input_attachments
[i
]);
1923 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1924 radv_handle_subpass_image_transition(cmd_buffer
,
1925 subpass
->depth_stencil_attachment
);
1929 cmd_buffer
->state
.subpass
= subpass
;
1931 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_RENDER_TARGETS
;
1935 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
1936 struct radv_render_pass
*pass
,
1937 const VkRenderPassBeginInfo
*info
)
1939 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1941 if (pass
->attachment_count
== 0) {
1942 state
->attachments
= NULL
;
1946 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1947 pass
->attachment_count
*
1948 sizeof(state
->attachments
[0]),
1949 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1950 if (state
->attachments
== NULL
) {
1951 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1952 return cmd_buffer
->record_result
;
1955 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1956 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1957 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1958 VkImageAspectFlags clear_aspects
= 0;
1960 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
1961 /* color attachment */
1962 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1963 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1966 /* depthstencil attachment */
1967 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1968 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1969 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1970 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
1971 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
1972 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1974 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
1975 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1976 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1980 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1981 state
->attachments
[i
].cleared_views
= 0;
1982 if (clear_aspects
&& info
) {
1983 assert(info
->clearValueCount
> i
);
1984 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
1987 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1993 VkResult
radv_AllocateCommandBuffers(
1995 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1996 VkCommandBuffer
*pCommandBuffers
)
1998 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1999 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
2001 VkResult result
= VK_SUCCESS
;
2004 memset(pCommandBuffers
, 0,
2005 sizeof(*pCommandBuffers
)*pAllocateInfo
->commandBufferCount
);
2007 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
2009 if (!list_empty(&pool
->free_cmd_buffers
)) {
2010 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
2012 list_del(&cmd_buffer
->pool_link
);
2013 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
2015 result
= radv_reset_cmd_buffer(cmd_buffer
);
2016 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2017 cmd_buffer
->level
= pAllocateInfo
->level
;
2019 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
2021 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
2022 &pCommandBuffers
[i
]);
2024 if (result
!= VK_SUCCESS
)
2028 if (result
!= VK_SUCCESS
)
2029 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
2030 i
, pCommandBuffers
);
2035 void radv_FreeCommandBuffers(
2037 VkCommandPool commandPool
,
2038 uint32_t commandBufferCount
,
2039 const VkCommandBuffer
*pCommandBuffers
)
2041 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2042 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
2045 if (cmd_buffer
->pool
) {
2046 list_del(&cmd_buffer
->pool_link
);
2047 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
2049 radv_cmd_buffer_destroy(cmd_buffer
);
2055 VkResult
radv_ResetCommandBuffer(
2056 VkCommandBuffer commandBuffer
,
2057 VkCommandBufferResetFlags flags
)
2059 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2060 return radv_reset_cmd_buffer(cmd_buffer
);
2063 static void emit_gfx_buffer_state(struct radv_cmd_buffer
*cmd_buffer
)
2065 struct radv_device
*device
= cmd_buffer
->device
;
2066 if (device
->gfx_init
) {
2067 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2068 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, device
->gfx_init
, 8);
2069 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2070 radeon_emit(cmd_buffer
->cs
, va
);
2071 radeon_emit(cmd_buffer
->cs
, va
>> 32);
2072 radeon_emit(cmd_buffer
->cs
, device
->gfx_init_size_dw
& 0xffff);
2074 si_init_config(cmd_buffer
);
2077 VkResult
radv_BeginCommandBuffer(
2078 VkCommandBuffer commandBuffer
,
2079 const VkCommandBufferBeginInfo
*pBeginInfo
)
2081 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2084 result
= radv_reset_cmd_buffer(cmd_buffer
);
2085 if (result
!= VK_SUCCESS
)
2088 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
2089 cmd_buffer
->state
.last_primitive_reset_en
= -1;
2090 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
2092 /* setup initial configuration into command buffer */
2093 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
2094 switch (cmd_buffer
->queue_family_index
) {
2095 case RADV_QUEUE_GENERAL
:
2096 emit_gfx_buffer_state(cmd_buffer
);
2097 radv_set_db_count_control(cmd_buffer
);
2099 case RADV_QUEUE_COMPUTE
:
2100 si_init_compute(cmd_buffer
);
2102 case RADV_QUEUE_TRANSFER
:
2108 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2109 assert(pBeginInfo
->pInheritanceInfo
);
2110 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
2111 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
2113 struct radv_subpass
*subpass
=
2114 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
2116 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
2117 if (result
!= VK_SUCCESS
)
2120 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
2123 radv_cmd_buffer_trace_emit(cmd_buffer
);
2127 void radv_CmdBindVertexBuffers(
2128 VkCommandBuffer commandBuffer
,
2129 uint32_t firstBinding
,
2130 uint32_t bindingCount
,
2131 const VkBuffer
* pBuffers
,
2132 const VkDeviceSize
* pOffsets
)
2134 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2135 struct radv_vertex_binding
*vb
= cmd_buffer
->state
.vertex_bindings
;
2137 /* We have to defer setting up vertex buffer since we need the buffer
2138 * stride from the pipeline. */
2140 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
2141 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2142 vb
[firstBinding
+ i
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2143 vb
[firstBinding
+ i
].offset
= pOffsets
[i
];
2146 cmd_buffer
->state
.vb_dirty
= true;
2149 void radv_CmdBindIndexBuffer(
2150 VkCommandBuffer commandBuffer
,
2152 VkDeviceSize offset
,
2153 VkIndexType indexType
)
2155 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2156 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2158 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2159 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
2160 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2162 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2163 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2164 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2165 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, index_buffer
->bo
, 8);
2169 void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2170 struct radv_descriptor_set
*set
,
2173 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2175 cmd_buffer
->state
.descriptors
[idx
] = set
;
2176 cmd_buffer
->state
.descriptors_dirty
|= (1u << idx
);
2180 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2182 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2183 if (set
->descriptors
[j
])
2184 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->descriptors
[j
], 7);
2187 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->bo
, 8);
2190 void radv_CmdBindDescriptorSets(
2191 VkCommandBuffer commandBuffer
,
2192 VkPipelineBindPoint pipelineBindPoint
,
2193 VkPipelineLayout _layout
,
2195 uint32_t descriptorSetCount
,
2196 const VkDescriptorSet
* pDescriptorSets
,
2197 uint32_t dynamicOffsetCount
,
2198 const uint32_t* pDynamicOffsets
)
2200 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2201 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2202 unsigned dyn_idx
= 0;
2204 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2205 unsigned idx
= i
+ firstSet
;
2206 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2207 radv_bind_descriptor_set(cmd_buffer
, set
, idx
);
2209 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2210 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2211 uint32_t *dst
= cmd_buffer
->dynamic_buffers
+ idx
* 4;
2212 assert(dyn_idx
< dynamicOffsetCount
);
2214 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2215 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2217 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2218 dst
[2] = range
->size
;
2219 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2220 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2221 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2222 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2223 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2224 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2225 cmd_buffer
->push_constant_stages
|=
2226 set
->layout
->dynamic_shader_stages
;
2231 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2232 struct radv_descriptor_set
*set
,
2233 struct radv_descriptor_set_layout
*layout
)
2235 set
->size
= layout
->size
;
2236 set
->layout
= layout
;
2238 if (cmd_buffer
->push_descriptors
.capacity
< set
->size
) {
2239 size_t new_size
= MAX2(set
->size
, 1024);
2240 new_size
= MAX2(new_size
, 2 * cmd_buffer
->push_descriptors
.capacity
);
2241 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2243 free(set
->mapped_ptr
);
2244 set
->mapped_ptr
= malloc(new_size
);
2246 if (!set
->mapped_ptr
) {
2247 cmd_buffer
->push_descriptors
.capacity
= 0;
2248 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2252 cmd_buffer
->push_descriptors
.capacity
= new_size
;
2258 void radv_meta_push_descriptor_set(
2259 struct radv_cmd_buffer
* cmd_buffer
,
2260 VkPipelineBindPoint pipelineBindPoint
,
2261 VkPipelineLayout _layout
,
2263 uint32_t descriptorWriteCount
,
2264 const VkWriteDescriptorSet
* pDescriptorWrites
)
2266 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2267 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2271 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2273 push_set
->size
= layout
->set
[set
].layout
->size
;
2274 push_set
->layout
= layout
->set
[set
].layout
;
2276 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2278 (void**) &push_set
->mapped_ptr
))
2281 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2282 push_set
->va
+= bo_offset
;
2284 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2285 radv_descriptor_set_to_handle(push_set
),
2286 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2288 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2289 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2292 void radv_CmdPushDescriptorSetKHR(
2293 VkCommandBuffer commandBuffer
,
2294 VkPipelineBindPoint pipelineBindPoint
,
2295 VkPipelineLayout _layout
,
2297 uint32_t descriptorWriteCount
,
2298 const VkWriteDescriptorSet
* pDescriptorWrites
)
2300 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2301 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2302 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2304 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2306 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2309 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2310 radv_descriptor_set_to_handle(push_set
),
2311 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2313 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2314 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2315 cmd_buffer
->state
.push_descriptors_dirty
= true;
2318 void radv_CmdPushDescriptorSetWithTemplateKHR(
2319 VkCommandBuffer commandBuffer
,
2320 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
2321 VkPipelineLayout _layout
,
2325 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2326 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2327 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2329 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2331 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2334 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2335 descriptorUpdateTemplate
, pData
);
2337 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2338 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2339 cmd_buffer
->state
.push_descriptors_dirty
= true;
2342 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2343 VkPipelineLayout layout
,
2344 VkShaderStageFlags stageFlags
,
2347 const void* pValues
)
2349 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2350 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2351 cmd_buffer
->push_constant_stages
|= stageFlags
;
2354 VkResult
radv_EndCommandBuffer(
2355 VkCommandBuffer commandBuffer
)
2357 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2359 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
2360 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== SI
)
2361 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2362 si_emit_cache_flush(cmd_buffer
);
2365 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
2366 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2368 return cmd_buffer
->record_result
;
2372 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2374 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2375 struct radv_shader_variant
*compute_shader
;
2376 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2379 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2382 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2384 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
2385 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
2387 ws
->cs_add_buffer(cmd_buffer
->cs
, compute_shader
->bo
, 8);
2388 radv_emit_prefetch(cmd_buffer
, va
, compute_shader
->code_size
);
2390 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2391 cmd_buffer
->cs
, 16);
2393 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
2394 radeon_emit(cmd_buffer
->cs
, va
>> 8);
2395 radeon_emit(cmd_buffer
->cs
, va
>> 40);
2397 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
2398 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc1
);
2399 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc2
);
2402 cmd_buffer
->compute_scratch_size_needed
=
2403 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2404 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2406 /* change these once we have scratch support */
2407 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
2408 S_00B860_WAVES(pipeline
->max_waves
) |
2409 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
2411 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
2412 radeon_emit(cmd_buffer
->cs
,
2413 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
2414 radeon_emit(cmd_buffer
->cs
,
2415 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
2416 radeon_emit(cmd_buffer
->cs
,
2417 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
2419 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2420 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
2423 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
)
2425 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2426 if (cmd_buffer
->state
.descriptors
[i
])
2427 cmd_buffer
->state
.descriptors_dirty
|= (1u << i
);
2431 void radv_CmdBindPipeline(
2432 VkCommandBuffer commandBuffer
,
2433 VkPipelineBindPoint pipelineBindPoint
,
2434 VkPipeline _pipeline
)
2436 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2437 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
2439 switch (pipelineBindPoint
) {
2440 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2441 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
2443 radv_mark_descriptor_sets_dirty(cmd_buffer
);
2445 cmd_buffer
->state
.compute_pipeline
= pipeline
;
2446 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2448 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2449 if (cmd_buffer
->state
.pipeline
== pipeline
)
2451 radv_mark_descriptor_sets_dirty(cmd_buffer
);
2453 cmd_buffer
->state
.pipeline
= pipeline
;
2457 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2458 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
2460 /* Apply the dynamic state from the pipeline */
2461 cmd_buffer
->state
.dirty
|= pipeline
->dynamic_state_mask
;
2462 radv_dynamic_state_copy(&cmd_buffer
->state
.dynamic
,
2463 &pipeline
->dynamic_state
,
2464 pipeline
->dynamic_state_mask
);
2466 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
2467 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
2468 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
2469 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
2471 if (radv_pipeline_has_tess(pipeline
))
2472 cmd_buffer
->tess_rings_needed
= true;
2474 if (radv_pipeline_has_gs(pipeline
)) {
2475 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2476 AC_UD_SCRATCH_RING_OFFSETS
);
2477 if (cmd_buffer
->ring_offsets_idx
== -1)
2478 cmd_buffer
->ring_offsets_idx
= loc
->sgpr_idx
;
2479 else if (loc
->sgpr_idx
!= -1)
2480 assert(loc
->sgpr_idx
== cmd_buffer
->ring_offsets_idx
);
2484 assert(!"invalid bind point");
2489 void radv_CmdSetViewport(
2490 VkCommandBuffer commandBuffer
,
2491 uint32_t firstViewport
,
2492 uint32_t viewportCount
,
2493 const VkViewport
* pViewports
)
2495 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2496 const uint32_t total_count
= firstViewport
+ viewportCount
;
2498 assert(firstViewport
< MAX_VIEWPORTS
);
2499 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
2501 memcpy(cmd_buffer
->state
.dynamic
.viewport
.viewports
+ firstViewport
,
2502 pViewports
, viewportCount
* sizeof(*pViewports
));
2504 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2507 void radv_CmdSetScissor(
2508 VkCommandBuffer commandBuffer
,
2509 uint32_t firstScissor
,
2510 uint32_t scissorCount
,
2511 const VkRect2D
* pScissors
)
2513 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2514 const uint32_t total_count
= firstScissor
+ scissorCount
;
2516 assert(firstScissor
< MAX_SCISSORS
);
2517 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
2519 memcpy(cmd_buffer
->state
.dynamic
.scissor
.scissors
+ firstScissor
,
2520 pScissors
, scissorCount
* sizeof(*pScissors
));
2521 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2524 void radv_CmdSetLineWidth(
2525 VkCommandBuffer commandBuffer
,
2528 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2529 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
2530 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2533 void radv_CmdSetDepthBias(
2534 VkCommandBuffer commandBuffer
,
2535 float depthBiasConstantFactor
,
2536 float depthBiasClamp
,
2537 float depthBiasSlopeFactor
)
2539 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2541 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
2542 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
2543 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
2545 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2548 void radv_CmdSetBlendConstants(
2549 VkCommandBuffer commandBuffer
,
2550 const float blendConstants
[4])
2552 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2554 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
2555 blendConstants
, sizeof(float) * 4);
2557 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2560 void radv_CmdSetDepthBounds(
2561 VkCommandBuffer commandBuffer
,
2562 float minDepthBounds
,
2563 float maxDepthBounds
)
2565 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2567 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
2568 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
2570 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2573 void radv_CmdSetStencilCompareMask(
2574 VkCommandBuffer commandBuffer
,
2575 VkStencilFaceFlags faceMask
,
2576 uint32_t compareMask
)
2578 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2580 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2581 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2582 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2583 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2585 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2588 void radv_CmdSetStencilWriteMask(
2589 VkCommandBuffer commandBuffer
,
2590 VkStencilFaceFlags faceMask
,
2593 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2595 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2596 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2597 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2598 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2600 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2603 void radv_CmdSetStencilReference(
2604 VkCommandBuffer commandBuffer
,
2605 VkStencilFaceFlags faceMask
,
2608 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2610 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2611 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
2612 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2613 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
2615 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2618 void radv_CmdExecuteCommands(
2619 VkCommandBuffer commandBuffer
,
2620 uint32_t commandBufferCount
,
2621 const VkCommandBuffer
* pCmdBuffers
)
2623 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
2625 assert(commandBufferCount
> 0);
2627 /* Emit pending flushes on primary prior to executing secondary */
2628 si_emit_cache_flush(primary
);
2630 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2631 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2633 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
2634 secondary
->scratch_size_needed
);
2635 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
2636 secondary
->compute_scratch_size_needed
);
2638 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
2639 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
2640 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
2641 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
2642 if (secondary
->tess_rings_needed
)
2643 primary
->tess_rings_needed
= true;
2644 if (secondary
->sample_positions_needed
)
2645 primary
->sample_positions_needed
= true;
2647 if (secondary
->ring_offsets_idx
!= -1) {
2648 if (primary
->ring_offsets_idx
== -1)
2649 primary
->ring_offsets_idx
= secondary
->ring_offsets_idx
;
2651 assert(secondary
->ring_offsets_idx
== primary
->ring_offsets_idx
);
2653 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
2656 /* When the secondary command buffer is compute only we don't
2657 * need to re-emit the current graphics pipeline.
2659 if (secondary
->state
.emitted_pipeline
) {
2660 primary
->state
.emitted_pipeline
=
2661 secondary
->state
.emitted_pipeline
;
2664 /* When the secondary command buffer is graphics only we don't
2665 * need to re-emit the current compute pipeline.
2667 if (secondary
->state
.emitted_compute_pipeline
) {
2668 primary
->state
.emitted_compute_pipeline
=
2669 secondary
->state
.emitted_compute_pipeline
;
2672 /* Only re-emit the draw packets when needed. */
2673 if (secondary
->state
.last_primitive_reset_en
!= -1) {
2674 primary
->state
.last_primitive_reset_en
=
2675 secondary
->state
.last_primitive_reset_en
;
2678 if (secondary
->state
.last_primitive_reset_index
) {
2679 primary
->state
.last_primitive_reset_index
=
2680 secondary
->state
.last_primitive_reset_index
;
2684 /* After executing commands from secondary buffers we have to dirty
2687 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2688 primary
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_ALL
;
2689 radv_mark_descriptor_sets_dirty(primary
);
2692 VkResult
radv_CreateCommandPool(
2694 const VkCommandPoolCreateInfo
* pCreateInfo
,
2695 const VkAllocationCallbacks
* pAllocator
,
2696 VkCommandPool
* pCmdPool
)
2698 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2699 struct radv_cmd_pool
*pool
;
2701 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2702 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2704 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2707 pool
->alloc
= *pAllocator
;
2709 pool
->alloc
= device
->alloc
;
2711 list_inithead(&pool
->cmd_buffers
);
2712 list_inithead(&pool
->free_cmd_buffers
);
2714 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2716 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
2722 void radv_DestroyCommandPool(
2724 VkCommandPool commandPool
,
2725 const VkAllocationCallbacks
* pAllocator
)
2727 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2728 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2733 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2734 &pool
->cmd_buffers
, pool_link
) {
2735 radv_cmd_buffer_destroy(cmd_buffer
);
2738 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2739 &pool
->free_cmd_buffers
, pool_link
) {
2740 radv_cmd_buffer_destroy(cmd_buffer
);
2743 vk_free2(&device
->alloc
, pAllocator
, pool
);
2746 VkResult
radv_ResetCommandPool(
2748 VkCommandPool commandPool
,
2749 VkCommandPoolResetFlags flags
)
2751 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2754 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
2755 &pool
->cmd_buffers
, pool_link
) {
2756 result
= radv_reset_cmd_buffer(cmd_buffer
);
2757 if (result
!= VK_SUCCESS
)
2764 void radv_TrimCommandPoolKHR(
2766 VkCommandPool commandPool
,
2767 VkCommandPoolTrimFlagsKHR flags
)
2769 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2774 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2775 &pool
->free_cmd_buffers
, pool_link
) {
2776 radv_cmd_buffer_destroy(cmd_buffer
);
2780 void radv_CmdBeginRenderPass(
2781 VkCommandBuffer commandBuffer
,
2782 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2783 VkSubpassContents contents
)
2785 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2786 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2787 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2789 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2790 cmd_buffer
->cs
, 2048);
2791 MAYBE_UNUSED VkResult result
;
2793 cmd_buffer
->state
.framebuffer
= framebuffer
;
2794 cmd_buffer
->state
.pass
= pass
;
2795 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2797 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
2798 if (result
!= VK_SUCCESS
)
2801 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
2802 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2804 radv_cmd_buffer_clear_subpass(cmd_buffer
);
2807 void radv_CmdNextSubpass(
2808 VkCommandBuffer commandBuffer
,
2809 VkSubpassContents contents
)
2811 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2813 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
2815 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2818 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
2819 radv_cmd_buffer_clear_subpass(cmd_buffer
);
2822 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
2824 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2825 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2826 if (!pipeline
->shaders
[stage
])
2828 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
2829 if (loc
->sgpr_idx
== -1)
2831 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
2832 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
2835 if (pipeline
->gs_copy_shader
) {
2836 struct ac_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
2837 if (loc
->sgpr_idx
!= -1) {
2838 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2839 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
2845 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
2846 uint32_t vertex_count
)
2848 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
2849 radeon_emit(cmd_buffer
->cs
, vertex_count
);
2850 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
2851 S_0287F0_USE_OPAQUE(0));
2855 VkCommandBuffer commandBuffer
,
2856 uint32_t vertexCount
,
2857 uint32_t instanceCount
,
2858 uint32_t firstVertex
,
2859 uint32_t firstInstance
)
2861 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2863 radv_cmd_buffer_flush_state(cmd_buffer
, false, (instanceCount
> 1), false, vertexCount
);
2865 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 20 * MAX_VIEWS
);
2867 assert(cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
);
2868 radeon_set_sh_reg_seq(cmd_buffer
->cs
, cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
,
2869 cmd_buffer
->state
.pipeline
->graphics
.vtx_emit_num
);
2870 radeon_emit(cmd_buffer
->cs
, firstVertex
);
2871 radeon_emit(cmd_buffer
->cs
, firstInstance
);
2872 if (cmd_buffer
->state
.pipeline
->graphics
.vtx_emit_num
== 3)
2873 radeon_emit(cmd_buffer
->cs
, 0);
2875 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_NUM_INSTANCES
, 0, cmd_buffer
->state
.predicating
));
2876 radeon_emit(cmd_buffer
->cs
, instanceCount
);
2878 if (!cmd_buffer
->state
.subpass
->view_mask
) {
2879 radv_cs_emit_draw_packet(cmd_buffer
, vertexCount
);
2882 for_each_bit(i
, cmd_buffer
->state
.subpass
->view_mask
) {
2883 radv_emit_view_index(cmd_buffer
, i
);
2885 radv_cs_emit_draw_packet(cmd_buffer
, vertexCount
);
2889 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2891 radv_cmd_buffer_after_draw(cmd_buffer
);
2896 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
2898 uint32_t index_count
)
2900 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, false));
2901 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
2902 radeon_emit(cmd_buffer
->cs
, index_va
);
2903 radeon_emit(cmd_buffer
->cs
, (index_va
>> 32UL) & 0xFF);
2904 radeon_emit(cmd_buffer
->cs
, index_count
);
2905 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
2908 void radv_CmdDrawIndexed(
2909 VkCommandBuffer commandBuffer
,
2910 uint32_t indexCount
,
2911 uint32_t instanceCount
,
2912 uint32_t firstIndex
,
2913 int32_t vertexOffset
,
2914 uint32_t firstInstance
)
2916 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2917 int index_size
= cmd_buffer
->state
.index_type
? 4 : 2;
2920 radv_cmd_buffer_flush_state(cmd_buffer
, true, (instanceCount
> 1), false, indexCount
);
2922 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 26 * MAX_VIEWS
);
2924 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2925 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_03090C_VGT_INDEX_TYPE
,
2926 2, cmd_buffer
->state
.index_type
);
2928 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2929 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.index_type
);
2932 assert(cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
);
2933 radeon_set_sh_reg_seq(cmd_buffer
->cs
, cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
,
2934 cmd_buffer
->state
.pipeline
->graphics
.vtx_emit_num
);
2935 radeon_emit(cmd_buffer
->cs
, vertexOffset
);
2936 radeon_emit(cmd_buffer
->cs
, firstInstance
);
2937 if (cmd_buffer
->state
.pipeline
->graphics
.vtx_emit_num
== 3)
2938 radeon_emit(cmd_buffer
->cs
, 0);
2940 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
2941 radeon_emit(cmd_buffer
->cs
, instanceCount
);
2943 index_va
= cmd_buffer
->state
.index_va
;
2944 index_va
+= firstIndex
* index_size
;
2945 if (!cmd_buffer
->state
.subpass
->view_mask
) {
2946 radv_cs_emit_draw_indexed_packet(cmd_buffer
, index_va
, indexCount
);
2949 for_each_bit(i
, cmd_buffer
->state
.subpass
->view_mask
) {
2950 radv_emit_view_index(cmd_buffer
, i
);
2952 radv_cs_emit_draw_indexed_packet(cmd_buffer
, index_va
, indexCount
);
2956 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2957 radv_cmd_buffer_after_draw(cmd_buffer
);
2961 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
2963 uint32_t draw_count
,
2967 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
2968 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
2969 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
2970 bool draw_id_enable
= cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.needs_draw_id
;
2971 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
2974 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
2975 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
2976 PKT3_DRAW_INDIRECT
, 3, false));
2978 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
2979 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
2980 radeon_emit(cs
, di_src_sel
);
2982 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
2983 PKT3_DRAW_INDIRECT_MULTI
,
2986 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
2987 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
2988 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
2989 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
2990 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
2991 radeon_emit(cs
, draw_count
); /* count */
2992 radeon_emit(cs
, count_va
); /* count_addr */
2993 radeon_emit(cs
, count_va
>> 32);
2994 radeon_emit(cs
, stride
); /* stride */
2995 radeon_emit(cs
, di_src_sel
);
3000 radv_emit_indirect_draw(struct radv_cmd_buffer
*cmd_buffer
,
3002 VkDeviceSize offset
,
3003 VkBuffer _count_buffer
,
3004 VkDeviceSize count_offset
,
3005 uint32_t draw_count
,
3009 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3010 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _count_buffer
);
3011 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3013 uint64_t indirect_va
= radv_buffer_get_va(buffer
->bo
);
3014 indirect_va
+= offset
+ buffer
->offset
;
3015 uint64_t count_va
= 0;
3018 count_va
= radv_buffer_get_va(count_buffer
->bo
);
3019 count_va
+= count_offset
+ count_buffer
->offset
;
3021 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, count_buffer
->bo
, 8);
3027 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, buffer
->bo
, 8);
3029 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
3031 radeon_emit(cs
, indirect_va
);
3032 radeon_emit(cs
, indirect_va
>> 32);
3034 if (!cmd_buffer
->state
.subpass
->view_mask
) {
3035 radv_cs_emit_indirect_draw_packet(cmd_buffer
, indexed
, draw_count
, count_va
, stride
);
3038 for_each_bit(i
, cmd_buffer
->state
.subpass
->view_mask
) {
3039 radv_emit_view_index(cmd_buffer
, i
);
3041 radv_cs_emit_indirect_draw_packet(cmd_buffer
, indexed
, draw_count
, count_va
, stride
);
3044 radv_cmd_buffer_after_draw(cmd_buffer
);
3048 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer
,
3050 VkDeviceSize offset
,
3051 VkBuffer countBuffer
,
3052 VkDeviceSize countBufferOffset
,
3053 uint32_t maxDrawCount
,
3056 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3057 radv_cmd_buffer_flush_state(cmd_buffer
, false, false, true, 0);
3059 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
3060 cmd_buffer
->cs
, 24 * MAX_VIEWS
);
3062 radv_emit_indirect_draw(cmd_buffer
, buffer
, offset
,
3063 countBuffer
, countBufferOffset
, maxDrawCount
, stride
, false);
3065 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3069 radv_cmd_draw_indexed_indirect_count(
3070 VkCommandBuffer commandBuffer
,
3072 VkDeviceSize offset
,
3073 VkBuffer countBuffer
,
3074 VkDeviceSize countBufferOffset
,
3075 uint32_t maxDrawCount
,
3078 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3080 radv_cmd_buffer_flush_state(cmd_buffer
, true, false, true, 0);
3082 index_va
= cmd_buffer
->state
.index_va
;
3084 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 31 * MAX_VIEWS
);
3086 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3087 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
,
3088 R_03090C_VGT_INDEX_TYPE
,
3089 2, cmd_buffer
->state
.index_type
);
3091 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
3092 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.index_type
);
3095 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
3096 radeon_emit(cmd_buffer
->cs
, index_va
);
3097 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
3099 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
3100 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
3102 radv_emit_indirect_draw(cmd_buffer
, buffer
, offset
,
3103 countBuffer
, countBufferOffset
, maxDrawCount
, stride
, true);
3105 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3108 void radv_CmdDrawIndirect(
3109 VkCommandBuffer commandBuffer
,
3111 VkDeviceSize offset
,
3115 radv_cmd_draw_indirect_count(commandBuffer
, buffer
, offset
,
3116 VK_NULL_HANDLE
, 0, drawCount
, stride
);
3119 void radv_CmdDrawIndexedIndirect(
3120 VkCommandBuffer commandBuffer
,
3122 VkDeviceSize offset
,
3126 radv_cmd_draw_indexed_indirect_count(commandBuffer
, buffer
, offset
,
3127 VK_NULL_HANDLE
, 0, drawCount
, stride
);
3130 void radv_CmdDrawIndirectCountAMD(
3131 VkCommandBuffer commandBuffer
,
3133 VkDeviceSize offset
,
3134 VkBuffer countBuffer
,
3135 VkDeviceSize countBufferOffset
,
3136 uint32_t maxDrawCount
,
3139 radv_cmd_draw_indirect_count(commandBuffer
, buffer
, offset
,
3140 countBuffer
, countBufferOffset
,
3141 maxDrawCount
, stride
);
3144 void radv_CmdDrawIndexedIndirectCountAMD(
3145 VkCommandBuffer commandBuffer
,
3147 VkDeviceSize offset
,
3148 VkBuffer countBuffer
,
3149 VkDeviceSize countBufferOffset
,
3150 uint32_t maxDrawCount
,
3153 radv_cmd_draw_indexed_indirect_count(commandBuffer
, buffer
, offset
,
3154 countBuffer
, countBufferOffset
,
3155 maxDrawCount
, stride
);
3158 struct radv_dispatch_info
{
3160 * Determine the layout of the grid (in block units) to be used.
3165 * Whether it's an unaligned compute dispatch.
3170 * Indirect compute parameters resource.
3172 struct radv_buffer
*indirect
;
3173 uint64_t indirect_offset
;
3177 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
3178 const struct radv_dispatch_info
*info
)
3180 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3181 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3182 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3183 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3184 struct ac_userdata_info
*loc
;
3187 grid_used
= compute_shader
->info
.info
.cs
.grid_components_used
;
3189 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
3190 AC_UD_CS_GRID_SIZE
);
3192 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
3194 if (info
->indirect
) {
3195 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3197 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3199 ws
->cs_add_buffer(cs
, info
->indirect
->bo
, 8);
3201 if (loc
->sgpr_idx
!= -1) {
3202 for (unsigned i
= 0; i
< grid_used
; ++i
) {
3203 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3204 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
3205 COPY_DATA_DST_SEL(COPY_DATA_REG
));
3206 radeon_emit(cs
, (va
+ 4 * i
));
3207 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
3208 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
3209 + loc
->sgpr_idx
* 4) >> 2) + i
);
3214 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
3215 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, 0) |
3216 PKT3_SHADER_TYPE_S(1));
3217 radeon_emit(cs
, va
);
3218 radeon_emit(cs
, va
>> 32);
3221 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
3222 PKT3_SHADER_TYPE_S(1));
3224 radeon_emit(cs
, va
);
3225 radeon_emit(cs
, va
>> 32);
3227 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, 0) |
3228 PKT3_SHADER_TYPE_S(1));
3233 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
3234 unsigned dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1) |
3235 S_00B800_FORCE_START_AT_000(1);
3237 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3238 /* If the KMD allows it (there is a KMD hw register for
3239 * it), allow launching waves out-of-order.
3241 dispatch_initiator
|= S_00B800_ORDER_MODE(1);
3244 if (info
->unaligned
) {
3245 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
3246 unsigned remainder
[3];
3248 /* If aligned, these should be an entire block size,
3251 remainder
[0] = blocks
[0] + cs_block_size
[0] -
3252 align_u32_npot(blocks
[0], cs_block_size
[0]);
3253 remainder
[1] = blocks
[1] + cs_block_size
[1] -
3254 align_u32_npot(blocks
[1], cs_block_size
[1]);
3255 remainder
[2] = blocks
[2] + cs_block_size
[2] -
3256 align_u32_npot(blocks
[2], cs_block_size
[2]);
3258 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
3259 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
3260 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
3262 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3264 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
3265 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
3267 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
3268 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
3270 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
3271 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
3273 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
3276 if (loc
->sgpr_idx
!= -1) {
3277 assert(!loc
->indirect
);
3278 assert(loc
->num_sgprs
== grid_used
);
3280 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
3281 loc
->sgpr_idx
* 4, grid_used
);
3282 radeon_emit(cs
, blocks
[0]);
3284 radeon_emit(cs
, blocks
[1]);
3286 radeon_emit(cs
, blocks
[2]);
3289 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
3290 PKT3_SHADER_TYPE_S(1));
3291 radeon_emit(cs
, blocks
[0]);
3292 radeon_emit(cs
, blocks
[1]);
3293 radeon_emit(cs
, blocks
[2]);
3294 radeon_emit(cs
, dispatch_initiator
);
3297 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3301 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
3302 const struct radv_dispatch_info
*info
)
3304 radv_emit_compute_pipeline(cmd_buffer
);
3306 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
3307 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
3308 VK_SHADER_STAGE_COMPUTE_BIT
);
3310 si_emit_cache_flush(cmd_buffer
);
3312 radv_emit_dispatch_packets(cmd_buffer
, info
);
3314 radv_cmd_buffer_after_draw(cmd_buffer
);
3317 void radv_CmdDispatch(
3318 VkCommandBuffer commandBuffer
,
3323 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3324 struct radv_dispatch_info info
= {};
3330 radv_dispatch(cmd_buffer
, &info
);
3333 void radv_CmdDispatchIndirect(
3334 VkCommandBuffer commandBuffer
,
3336 VkDeviceSize offset
)
3338 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3339 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3340 struct radv_dispatch_info info
= {};
3342 info
.indirect
= buffer
;
3343 info
.indirect_offset
= offset
;
3345 radv_dispatch(cmd_buffer
, &info
);
3348 void radv_unaligned_dispatch(
3349 struct radv_cmd_buffer
*cmd_buffer
,
3354 struct radv_dispatch_info info
= {};
3361 radv_dispatch(cmd_buffer
, &info
);
3364 void radv_CmdEndRenderPass(
3365 VkCommandBuffer commandBuffer
)
3367 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3369 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
3371 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3373 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
3374 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
3375 radv_handle_subpass_image_transition(cmd_buffer
,
3376 (VkAttachmentReference
){i
, layout
});
3379 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3381 cmd_buffer
->state
.pass
= NULL
;
3382 cmd_buffer
->state
.subpass
= NULL
;
3383 cmd_buffer
->state
.attachments
= NULL
;
3384 cmd_buffer
->state
.framebuffer
= NULL
;
3388 * For HTILE we have the following interesting clear words:
3389 * 0x0000030f: Uncompressed.
3390 * 0xfffffff0: Clear depth to 1.0
3391 * 0x00000000: Clear depth to 0.0
3393 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
3394 struct radv_image
*image
,
3395 const VkImageSubresourceRange
*range
,
3396 uint32_t clear_word
)
3398 assert(range
->baseMipLevel
== 0);
3399 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
3400 unsigned layer_count
= radv_get_layerCount(image
, range
);
3401 uint64_t size
= image
->surface
.htile_slice_size
* layer_count
;
3402 uint64_t offset
= image
->offset
+ image
->htile_offset
+
3403 image
->surface
.htile_slice_size
* range
->baseArrayLayer
;
3405 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3406 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3408 radv_fill_buffer(cmd_buffer
, image
->bo
, offset
, size
, clear_word
);
3410 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
3411 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3412 RADV_CMD_FLAG_INV_VMEM_L1
|
3413 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3416 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3417 struct radv_image
*image
,
3418 VkImageLayout src_layout
,
3419 VkImageLayout dst_layout
,
3420 unsigned src_queue_mask
,
3421 unsigned dst_queue_mask
,
3422 const VkImageSubresourceRange
*range
,
3423 VkImageAspectFlags pending_clears
)
3425 if (dst_layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
&&
3426 (pending_clears
& vk_format_aspects(image
->vk_format
)) == vk_format_aspects(image
->vk_format
) &&
3427 cmd_buffer
->state
.render_area
.offset
.x
== 0 && cmd_buffer
->state
.render_area
.offset
.y
== 0 &&
3428 cmd_buffer
->state
.render_area
.extent
.width
== image
->info
.width
&&
3429 cmd_buffer
->state
.render_area
.extent
.height
== image
->info
.height
) {
3430 /* The clear will initialize htile. */
3432 } else if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
3433 radv_layout_has_htile(image
, dst_layout
, dst_queue_mask
)) {
3434 /* TODO: merge with the clear if applicable */
3435 radv_initialize_htile(cmd_buffer
, image
, range
, 0);
3436 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3437 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3438 radv_initialize_htile(cmd_buffer
, image
, range
, 0xffffffff);
3439 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3440 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3441 VkImageSubresourceRange local_range
= *range
;
3442 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
3443 local_range
.baseMipLevel
= 0;
3444 local_range
.levelCount
= 1;
3446 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3447 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3449 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
3451 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3452 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3456 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
3457 struct radv_image
*image
, uint32_t value
)
3459 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3460 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3462 radv_fill_buffer(cmd_buffer
, image
->bo
, image
->offset
+ image
->cmask
.offset
,
3463 image
->cmask
.size
, value
);
3465 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
3466 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3467 RADV_CMD_FLAG_INV_VMEM_L1
|
3468 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3471 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3472 struct radv_image
*image
,
3473 VkImageLayout src_layout
,
3474 VkImageLayout dst_layout
,
3475 unsigned src_queue_mask
,
3476 unsigned dst_queue_mask
,
3477 const VkImageSubresourceRange
*range
)
3479 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3480 if (image
->fmask
.size
)
3481 radv_initialise_cmask(cmd_buffer
, image
, 0xccccccccu
);
3483 radv_initialise_cmask(cmd_buffer
, image
, 0xffffffffu
);
3484 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3485 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3486 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3490 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
3491 struct radv_image
*image
, uint32_t value
)
3494 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3495 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3497 radv_fill_buffer(cmd_buffer
, image
->bo
, image
->offset
+ image
->dcc_offset
,
3498 image
->surface
.dcc_size
, value
);
3500 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3501 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
3502 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3503 RADV_CMD_FLAG_INV_VMEM_L1
|
3504 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3507 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3508 struct radv_image
*image
,
3509 VkImageLayout src_layout
,
3510 VkImageLayout dst_layout
,
3511 unsigned src_queue_mask
,
3512 unsigned dst_queue_mask
,
3513 const VkImageSubresourceRange
*range
)
3515 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3516 radv_initialize_dcc(cmd_buffer
, image
, 0x20202020u
);
3517 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3518 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3519 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3523 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3524 struct radv_image
*image
,
3525 VkImageLayout src_layout
,
3526 VkImageLayout dst_layout
,
3527 uint32_t src_family
,
3528 uint32_t dst_family
,
3529 const VkImageSubresourceRange
*range
,
3530 VkImageAspectFlags pending_clears
)
3532 if (image
->exclusive
&& src_family
!= dst_family
) {
3533 /* This is an acquire or a release operation and there will be
3534 * a corresponding release/acquire. Do the transition in the
3535 * most flexible queue. */
3537 assert(src_family
== cmd_buffer
->queue_family_index
||
3538 dst_family
== cmd_buffer
->queue_family_index
);
3540 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
3543 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
3544 (src_family
== RADV_QUEUE_GENERAL
||
3545 dst_family
== RADV_QUEUE_GENERAL
))
3549 unsigned src_queue_mask
= radv_image_queue_family_mask(image
, src_family
, cmd_buffer
->queue_family_index
);
3550 unsigned dst_queue_mask
= radv_image_queue_family_mask(image
, dst_family
, cmd_buffer
->queue_family_index
);
3552 if (image
->surface
.htile_size
)
3553 radv_handle_depth_image_transition(cmd_buffer
, image
, src_layout
,
3554 dst_layout
, src_queue_mask
,
3555 dst_queue_mask
, range
,
3558 if (image
->cmask
.size
|| image
->fmask
.size
)
3559 radv_handle_cmask_image_transition(cmd_buffer
, image
, src_layout
,
3560 dst_layout
, src_queue_mask
,
3561 dst_queue_mask
, range
);
3563 if (image
->surface
.dcc_size
)
3564 radv_handle_dcc_image_transition(cmd_buffer
, image
, src_layout
,
3565 dst_layout
, src_queue_mask
,
3566 dst_queue_mask
, range
);
3569 void radv_CmdPipelineBarrier(
3570 VkCommandBuffer commandBuffer
,
3571 VkPipelineStageFlags srcStageMask
,
3572 VkPipelineStageFlags destStageMask
,
3574 uint32_t memoryBarrierCount
,
3575 const VkMemoryBarrier
* pMemoryBarriers
,
3576 uint32_t bufferMemoryBarrierCount
,
3577 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3578 uint32_t imageMemoryBarrierCount
,
3579 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3581 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3582 enum radv_cmd_flush_bits src_flush_bits
= 0;
3583 enum radv_cmd_flush_bits dst_flush_bits
= 0;
3585 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3586 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
);
3587 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
3591 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3592 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
);
3593 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
3597 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3598 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3599 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
);
3600 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
3604 radv_stage_flush(cmd_buffer
, srcStageMask
);
3605 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
3607 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3608 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3609 radv_handle_image_transition(cmd_buffer
, image
,
3610 pImageMemoryBarriers
[i
].oldLayout
,
3611 pImageMemoryBarriers
[i
].newLayout
,
3612 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
3613 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
3614 &pImageMemoryBarriers
[i
].subresourceRange
,
3618 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
3622 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
3623 struct radv_event
*event
,
3624 VkPipelineStageFlags stageMask
,
3627 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3628 uint64_t va
= radv_buffer_get_va(event
->bo
);
3630 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
3632 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 18);
3634 /* TODO: this is overkill. Probably should figure something out from
3635 * the stage mask. */
3637 si_cs_emit_write_event_eop(cs
,
3638 cmd_buffer
->state
.predicating
,
3639 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
3641 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
3644 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3647 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
3649 VkPipelineStageFlags stageMask
)
3651 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3652 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3654 write_event(cmd_buffer
, event
, stageMask
, 1);
3657 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
3659 VkPipelineStageFlags stageMask
)
3661 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3662 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3664 write_event(cmd_buffer
, event
, stageMask
, 0);
3667 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3668 uint32_t eventCount
,
3669 const VkEvent
* pEvents
,
3670 VkPipelineStageFlags srcStageMask
,
3671 VkPipelineStageFlags dstStageMask
,
3672 uint32_t memoryBarrierCount
,
3673 const VkMemoryBarrier
* pMemoryBarriers
,
3674 uint32_t bufferMemoryBarrierCount
,
3675 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3676 uint32_t imageMemoryBarrierCount
,
3677 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3679 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3680 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3682 for (unsigned i
= 0; i
< eventCount
; ++i
) {
3683 RADV_FROM_HANDLE(radv_event
, event
, pEvents
[i
]);
3684 uint64_t va
= radv_buffer_get_va(event
->bo
);
3686 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
3688 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
3690 si_emit_wait_fence(cs
, false, va
, 1, 0xffffffff);
3691 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3695 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3696 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3698 radv_handle_image_transition(cmd_buffer
, image
,
3699 pImageMemoryBarriers
[i
].oldLayout
,
3700 pImageMemoryBarriers
[i
].newLayout
,
3701 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
3702 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
3703 &pImageMemoryBarriers
[i
].subresourceRange
,
3707 /* TODO: figure out how to do memory barriers without waiting */
3708 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
|
3709 RADV_CMD_FLAG_INV_GLOBAL_L2
|
3710 RADV_CMD_FLAG_INV_VMEM_L1
|
3711 RADV_CMD_FLAG_INV_SMEM_L1
;