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radv: rename radv_emit_prefetch() to radv_emit_prefetch_L2()
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safefly call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo, 8);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 cmd_buffer->ring_offsets_idx = -1;
314
315 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
316 cmd_buffer->descriptors[i].dirty = 0;
317 cmd_buffer->descriptors[i].valid = 0;
318 cmd_buffer->descriptors[i].push_dirty = false;
319 }
320
321 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
322 void *fence_ptr;
323 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
324 &cmd_buffer->gfx9_fence_offset,
325 &fence_ptr);
326 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
327 }
328
329 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
330
331 return cmd_buffer->record_result;
332 }
333
334 static bool
335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
336 uint64_t min_needed)
337 {
338 uint64_t new_size;
339 struct radeon_winsys_bo *bo;
340 struct radv_cmd_buffer_upload *upload;
341 struct radv_device *device = cmd_buffer->device;
342
343 new_size = MAX2(min_needed, 16 * 1024);
344 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
345
346 bo = device->ws->buffer_create(device->ws,
347 new_size, 4096,
348 RADEON_DOMAIN_GTT,
349 RADEON_FLAG_CPU_ACCESS|
350 RADEON_FLAG_NO_INTERPROCESS_SHARING);
351
352 if (!bo) {
353 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
354 return false;
355 }
356
357 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
358 if (cmd_buffer->upload.upload_bo) {
359 upload = malloc(sizeof(*upload));
360
361 if (!upload) {
362 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
363 device->ws->buffer_destroy(bo);
364 return false;
365 }
366
367 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
368 list_add(&upload->list, &cmd_buffer->upload.list);
369 }
370
371 cmd_buffer->upload.upload_bo = bo;
372 cmd_buffer->upload.size = new_size;
373 cmd_buffer->upload.offset = 0;
374 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
375
376 if (!cmd_buffer->upload.map) {
377 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
378 return false;
379 }
380
381 return true;
382 }
383
384 bool
385 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
386 unsigned size,
387 unsigned alignment,
388 unsigned *out_offset,
389 void **ptr)
390 {
391 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
392 if (offset + size > cmd_buffer->upload.size) {
393 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
394 return false;
395 offset = 0;
396 }
397
398 *out_offset = offset;
399 *ptr = cmd_buffer->upload.map + offset;
400
401 cmd_buffer->upload.offset = offset + size;
402 return true;
403 }
404
405 bool
406 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
407 unsigned size, unsigned alignment,
408 const void *data, unsigned *out_offset)
409 {
410 uint8_t *ptr;
411
412 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
413 out_offset, (void **)&ptr))
414 return false;
415
416 if (ptr)
417 memcpy(ptr, data, size);
418
419 return true;
420 }
421
422 static void
423 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
424 unsigned count, const uint32_t *data)
425 {
426 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
427 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
428 S_370_WR_CONFIRM(1) |
429 S_370_ENGINE_SEL(V_370_ME));
430 radeon_emit(cs, va);
431 radeon_emit(cs, va >> 32);
432 radeon_emit_array(cs, data, count);
433 }
434
435 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
436 {
437 struct radv_device *device = cmd_buffer->device;
438 struct radeon_winsys_cs *cs = cmd_buffer->cs;
439 uint64_t va;
440
441 va = radv_buffer_get_va(device->trace_bo);
442 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
443 va += 4;
444
445 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
446
447 ++cmd_buffer->state.trace_id;
448 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
449 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
450 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
451 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
452 }
453
454 static void
455 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
456 enum radv_cmd_flush_bits flags)
457 {
458 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
459 uint32_t *ptr = NULL;
460 uint64_t va = 0;
461
462 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
463 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
464
465 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
466 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
467 cmd_buffer->gfx9_fence_offset;
468 ptr = &cmd_buffer->gfx9_fence_idx;
469 }
470
471 /* Force wait for graphics or compute engines to be idle. */
472 si_cs_emit_cache_flush(cmd_buffer->cs,
473 cmd_buffer->device->physical_device->rad_info.chip_class,
474 ptr, va,
475 radv_cmd_buffer_uses_mec(cmd_buffer),
476 flags);
477 }
478
479 if (unlikely(cmd_buffer->device->trace_bo))
480 radv_cmd_buffer_trace_emit(cmd_buffer);
481 }
482
483 static void
484 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
485 struct radv_pipeline *pipeline, enum ring_type ring)
486 {
487 struct radv_device *device = cmd_buffer->device;
488 struct radeon_winsys_cs *cs = cmd_buffer->cs;
489 uint32_t data[2];
490 uint64_t va;
491
492 va = radv_buffer_get_va(device->trace_bo);
493
494 switch (ring) {
495 case RING_GFX:
496 va += 8;
497 break;
498 case RING_COMPUTE:
499 va += 16;
500 break;
501 default:
502 assert(!"invalid ring type");
503 }
504
505 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
506 cmd_buffer->cs, 6);
507
508 data[0] = (uintptr_t)pipeline;
509 data[1] = (uintptr_t)pipeline >> 32;
510
511 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
512 radv_emit_write_data_packet(cs, va, 2, data);
513 }
514
515 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
516 VkPipelineBindPoint bind_point,
517 struct radv_descriptor_set *set,
518 unsigned idx)
519 {
520 struct radv_descriptor_state *descriptors_state =
521 radv_get_descriptors_state(cmd_buffer, bind_point);
522
523 descriptors_state->sets[idx] = set;
524 if (set)
525 descriptors_state->valid |= (1u << idx);
526 else
527 descriptors_state->valid &= ~(1u << idx);
528 descriptors_state->dirty |= (1u << idx);
529 }
530
531 static void
532 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
533 VkPipelineBindPoint bind_point)
534 {
535 struct radv_descriptor_state *descriptors_state =
536 radv_get_descriptors_state(cmd_buffer, bind_point);
537 struct radv_device *device = cmd_buffer->device;
538 struct radeon_winsys_cs *cs = cmd_buffer->cs;
539 uint32_t data[MAX_SETS * 2] = {};
540 uint64_t va;
541 unsigned i;
542 va = radv_buffer_get_va(device->trace_bo) + 24;
543
544 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
545 cmd_buffer->cs, 4 + MAX_SETS * 2);
546
547 for_each_bit(i, descriptors_state->valid) {
548 struct radv_descriptor_set *set = descriptors_state->sets[i];
549 data[i * 2] = (uintptr_t)set;
550 data[i * 2 + 1] = (uintptr_t)set >> 32;
551 }
552
553 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
554 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
555 }
556
557 struct radv_userdata_info *
558 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
559 gl_shader_stage stage,
560 int idx)
561 {
562 if (stage == MESA_SHADER_VERTEX) {
563 if (pipeline->shaders[MESA_SHADER_VERTEX])
564 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
565 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
566 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
567 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
568 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
569 } else if (stage == MESA_SHADER_TESS_EVAL) {
570 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
571 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
572 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
573 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
574 }
575 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
576 }
577
578 static void
579 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
580 struct radv_pipeline *pipeline,
581 gl_shader_stage stage,
582 int idx, uint64_t va)
583 {
584 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
585 uint32_t base_reg = pipeline->user_data_0[stage];
586 if (loc->sgpr_idx == -1)
587 return;
588 assert(loc->num_sgprs == 2);
589 assert(!loc->indirect);
590 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
591 radeon_emit(cmd_buffer->cs, va);
592 radeon_emit(cmd_buffer->cs, va >> 32);
593 }
594
595 static void
596 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
597 struct radv_pipeline *pipeline)
598 {
599 int num_samples = pipeline->graphics.ms.num_samples;
600 struct radv_multisample_state *ms = &pipeline->graphics.ms;
601 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
602
603 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
604 cmd_buffer->sample_positions_needed = true;
605
606 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
607 return;
608
609 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
610 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
611 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
612
613 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
614
615 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
616
617 /* GFX9: Flush DFSM when the AA mode changes. */
618 if (cmd_buffer->device->dfsm_allowed) {
619 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
620 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
621 }
622 }
623
624 static void
625 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
626 struct radv_shader_variant *shader)
627 {
628 struct radeon_winsys *ws = cmd_buffer->device->ws;
629 struct radeon_winsys_cs *cs = cmd_buffer->cs;
630 uint64_t va;
631
632 if (!shader)
633 return;
634
635 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
636
637 radv_cs_add_buffer(ws, cs, shader->bo, 8);
638 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
639 }
640
641 static void
642 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
643 struct radv_pipeline *pipeline)
644 {
645 struct radv_cmd_state *state = &cmd_buffer->state;
646
647 if (cmd_buffer->device->physical_device->rad_info.chip_class < CIK)
648 return;
649
650 if (state->prefetch_L2_mask & RADV_PREFETCH_VS)
651 radv_emit_shader_prefetch(cmd_buffer,
652 pipeline->shaders[MESA_SHADER_VERTEX]);
653
654 if (state->prefetch_L2_mask & RADV_PREFETCH_VBO_DESCRIPTORS)
655 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
656
657 if (state->prefetch_L2_mask & RADV_PREFETCH_TCS)
658 radv_emit_shader_prefetch(cmd_buffer,
659 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
660
661 if (state->prefetch_L2_mask & RADV_PREFETCH_TES)
662 radv_emit_shader_prefetch(cmd_buffer,
663 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
664
665 if (state->prefetch_L2_mask & RADV_PREFETCH_GS) {
666 radv_emit_shader_prefetch(cmd_buffer,
667 pipeline->shaders[MESA_SHADER_GEOMETRY]);
668 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
669 }
670
671 if (state->prefetch_L2_mask & RADV_PREFETCH_PS)
672 radv_emit_shader_prefetch(cmd_buffer,
673 pipeline->shaders[MESA_SHADER_FRAGMENT]);
674
675 state->prefetch_L2_mask = 0;
676 }
677
678 static void
679 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
680 {
681 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
682
683 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
684 return;
685
686 radv_update_multisample_state(cmd_buffer, pipeline);
687
688 cmd_buffer->scratch_size_needed =
689 MAX2(cmd_buffer->scratch_size_needed,
690 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
691
692 if (!cmd_buffer->state.emitted_pipeline ||
693 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
694 pipeline->graphics.can_use_guardband)
695 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
696
697 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
698
699 if (unlikely(cmd_buffer->device->trace_bo))
700 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
701
702 cmd_buffer->state.emitted_pipeline = pipeline;
703
704 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
705 }
706
707 static void
708 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
709 {
710 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
711 cmd_buffer->state.dynamic.viewport.viewports);
712 }
713
714 static void
715 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
716 {
717 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
718
719 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
720 * scissor registers are changed. There is also a more efficient but
721 * more involved alternative workaround.
722 */
723 if (cmd_buffer->device->physical_device->has_scissor_bug) {
724 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
725 si_emit_cache_flush(cmd_buffer);
726 }
727 si_write_scissors(cmd_buffer->cs, 0, count,
728 cmd_buffer->state.dynamic.scissor.scissors,
729 cmd_buffer->state.dynamic.viewport.viewports,
730 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
731 }
732
733 static void
734 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
735 {
736 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
737 return;
738
739 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
740 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
741 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
742 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
743 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
744 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
745 S_028214_BR_Y(rect.offset.y + rect.extent.height));
746 }
747 }
748
749 static void
750 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
751 {
752 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
753
754 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
755 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
756 }
757
758 static void
759 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
760 {
761 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
762
763 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
764 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
765 }
766
767 static void
768 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
769 {
770 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
771
772 radeon_set_context_reg_seq(cmd_buffer->cs,
773 R_028430_DB_STENCILREFMASK, 2);
774 radeon_emit(cmd_buffer->cs,
775 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
776 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
777 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
778 S_028430_STENCILOPVAL(1));
779 radeon_emit(cmd_buffer->cs,
780 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
781 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
782 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
783 S_028434_STENCILOPVAL_BF(1));
784 }
785
786 static void
787 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
788 {
789 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
790
791 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
792 fui(d->depth_bounds.min));
793 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
794 fui(d->depth_bounds.max));
795 }
796
797 static void
798 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
799 {
800 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
801 unsigned slope = fui(d->depth_bias.slope * 16.0f);
802 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
803
804
805 radeon_set_context_reg_seq(cmd_buffer->cs,
806 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
807 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
808 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
809 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
810 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
811 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
812 }
813
814 static void
815 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
816 int index,
817 struct radv_attachment_info *att,
818 struct radv_image *image,
819 VkImageLayout layout)
820 {
821 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
822 struct radv_color_buffer_info *cb = &att->cb;
823 uint32_t cb_color_info = cb->cb_color_info;
824
825 if (!radv_layout_dcc_compressed(image, layout,
826 radv_image_queue_family_mask(image,
827 cmd_buffer->queue_family_index,
828 cmd_buffer->queue_family_index))) {
829 cb_color_info &= C_028C70_DCC_ENABLE;
830 }
831
832 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
833 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
834 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
835 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
836 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
837 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
838 radeon_emit(cmd_buffer->cs, cb_color_info);
839 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
840 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
841 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
842 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
843 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
844 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
845
846 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
847 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
848 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
849
850 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
851 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
852 } else {
853 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
854 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
855 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
856 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
857 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
858 radeon_emit(cmd_buffer->cs, cb_color_info);
859 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
860 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
861 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
862 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
863 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
864 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
865
866 if (is_vi) { /* DCC BASE */
867 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
868 }
869 }
870 }
871
872 static void
873 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
874 struct radv_ds_buffer_info *ds,
875 struct radv_image *image,
876 VkImageLayout layout)
877 {
878 uint32_t db_z_info = ds->db_z_info;
879 uint32_t db_stencil_info = ds->db_stencil_info;
880
881 if (!radv_layout_has_htile(image, layout,
882 radv_image_queue_family_mask(image,
883 cmd_buffer->queue_family_index,
884 cmd_buffer->queue_family_index))) {
885 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
886 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
887 }
888
889 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
890 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
891
892
893 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
894 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
895 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
896 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
897 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
898
899 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
900 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
901 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
902 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
903 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
904 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
905 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
906 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
907 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
908 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
909 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
910
911 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
912 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
913 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
914 } else {
915 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
916
917 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
918 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
919 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
920 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
921 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
922 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
923 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
924 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
925 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
926 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
927
928 }
929
930 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
931 ds->pa_su_poly_offset_db_fmt_cntl);
932 }
933
934 void
935 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
936 struct radv_image *image,
937 VkClearDepthStencilValue ds_clear_value,
938 VkImageAspectFlags aspects)
939 {
940 uint64_t va = radv_buffer_get_va(image->bo);
941 va += image->offset + image->clear_value_offset;
942 unsigned reg_offset = 0, reg_count = 0;
943
944 assert(image->surface.htile_size);
945
946 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
947 ++reg_count;
948 } else {
949 ++reg_offset;
950 va += 4;
951 }
952 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
953 ++reg_count;
954
955 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
956 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
957 S_370_WR_CONFIRM(1) |
958 S_370_ENGINE_SEL(V_370_PFP));
959 radeon_emit(cmd_buffer->cs, va);
960 radeon_emit(cmd_buffer->cs, va >> 32);
961 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
962 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
963 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
964 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
965
966 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
967 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
968 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
969 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
970 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
971 }
972
973 static void
974 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
975 struct radv_image *image)
976 {
977 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
978 uint64_t va = radv_buffer_get_va(image->bo);
979 va += image->offset + image->clear_value_offset;
980 unsigned reg_offset = 0, reg_count = 0;
981
982 if (!image->surface.htile_size)
983 return;
984
985 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
986 ++reg_count;
987 } else {
988 ++reg_offset;
989 va += 4;
990 }
991 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
992 ++reg_count;
993
994 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
995 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
996 COPY_DATA_DST_SEL(COPY_DATA_REG) |
997 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
998 radeon_emit(cmd_buffer->cs, va);
999 radeon_emit(cmd_buffer->cs, va >> 32);
1000 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1001 radeon_emit(cmd_buffer->cs, 0);
1002
1003 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1004 radeon_emit(cmd_buffer->cs, 0);
1005 }
1006
1007 /*
1008 *with DCC some colors don't require CMASK elimiation before being
1009 * used as a texture. This sets a predicate value to determine if the
1010 * cmask eliminate is required.
1011 */
1012 void
1013 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1014 struct radv_image *image,
1015 bool value)
1016 {
1017 uint64_t pred_val = value;
1018 uint64_t va = radv_buffer_get_va(image->bo);
1019 va += image->offset + image->dcc_pred_offset;
1020
1021 assert(image->surface.dcc_size);
1022
1023 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1024 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1025 S_370_WR_CONFIRM(1) |
1026 S_370_ENGINE_SEL(V_370_PFP));
1027 radeon_emit(cmd_buffer->cs, va);
1028 radeon_emit(cmd_buffer->cs, va >> 32);
1029 radeon_emit(cmd_buffer->cs, pred_val);
1030 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1031 }
1032
1033 void
1034 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1035 struct radv_image *image,
1036 int idx,
1037 uint32_t color_values[2])
1038 {
1039 uint64_t va = radv_buffer_get_va(image->bo);
1040 va += image->offset + image->clear_value_offset;
1041
1042 assert(image->cmask.size || image->surface.dcc_size);
1043
1044 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1045 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1046 S_370_WR_CONFIRM(1) |
1047 S_370_ENGINE_SEL(V_370_PFP));
1048 radeon_emit(cmd_buffer->cs, va);
1049 radeon_emit(cmd_buffer->cs, va >> 32);
1050 radeon_emit(cmd_buffer->cs, color_values[0]);
1051 radeon_emit(cmd_buffer->cs, color_values[1]);
1052
1053 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1054 radeon_emit(cmd_buffer->cs, color_values[0]);
1055 radeon_emit(cmd_buffer->cs, color_values[1]);
1056 }
1057
1058 static void
1059 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1060 struct radv_image *image,
1061 int idx)
1062 {
1063 uint64_t va = radv_buffer_get_va(image->bo);
1064 va += image->offset + image->clear_value_offset;
1065
1066 if (!image->cmask.size && !image->surface.dcc_size)
1067 return;
1068
1069 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1070
1071 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1072 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1073 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1074 COPY_DATA_COUNT_SEL);
1075 radeon_emit(cmd_buffer->cs, va);
1076 radeon_emit(cmd_buffer->cs, va >> 32);
1077 radeon_emit(cmd_buffer->cs, reg >> 2);
1078 radeon_emit(cmd_buffer->cs, 0);
1079
1080 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1081 radeon_emit(cmd_buffer->cs, 0);
1082 }
1083
1084 static void
1085 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1086 {
1087 int i;
1088 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1089 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1090
1091 /* this may happen for inherited secondary recording */
1092 if (!framebuffer)
1093 return;
1094
1095 for (i = 0; i < 8; ++i) {
1096 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1097 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1098 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1099 continue;
1100 }
1101
1102 int idx = subpass->color_attachments[i].attachment;
1103 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1104 struct radv_image *image = att->attachment->image;
1105 VkImageLayout layout = subpass->color_attachments[i].layout;
1106
1107 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1108
1109 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1110 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1111
1112 radv_load_color_clear_regs(cmd_buffer, image, i);
1113 }
1114
1115 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1116 int idx = subpass->depth_stencil_attachment.attachment;
1117 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1118 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1119 struct radv_image *image = att->attachment->image;
1120 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1121 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1122 cmd_buffer->queue_family_index,
1123 cmd_buffer->queue_family_index);
1124 /* We currently don't support writing decompressed HTILE */
1125 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1126 radv_layout_is_htile_compressed(image, layout, queue_mask));
1127
1128 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1129
1130 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1131 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1132 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1133 }
1134 radv_load_depth_clear_regs(cmd_buffer, image);
1135 } else {
1136 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1137 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1138 else
1139 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1140
1141 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1142 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1143 }
1144 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1145 S_028208_BR_X(framebuffer->width) |
1146 S_028208_BR_Y(framebuffer->height));
1147
1148 if (cmd_buffer->device->dfsm_allowed) {
1149 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1150 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1151 }
1152
1153 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1154 }
1155
1156 static void
1157 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1158 {
1159 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1160 struct radv_cmd_state *state = &cmd_buffer->state;
1161
1162 if (state->index_type != state->last_index_type) {
1163 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1164 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1165 2, state->index_type);
1166 } else {
1167 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1168 radeon_emit(cs, state->index_type);
1169 }
1170
1171 state->last_index_type = state->index_type;
1172 }
1173
1174 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1175 radeon_emit(cs, state->index_va);
1176 radeon_emit(cs, state->index_va >> 32);
1177
1178 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1179 radeon_emit(cs, state->max_index_count);
1180
1181 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1182 }
1183
1184 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1185 {
1186 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1187 uint32_t pa_sc_mode_cntl_1 =
1188 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1189 uint32_t db_count_control;
1190
1191 if(!cmd_buffer->state.active_occlusion_queries) {
1192 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1193 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1194 pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
1195 /* Re-enable out-of-order rasterization if the
1196 * bound pipeline supports it and if it's has
1197 * been disabled before starting occlusion
1198 * queries.
1199 */
1200 radeon_set_context_reg(cmd_buffer->cs,
1201 R_028A4C_PA_SC_MODE_CNTL_1,
1202 pa_sc_mode_cntl_1);
1203 }
1204 db_count_control = 0;
1205 } else {
1206 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1207 }
1208 } else {
1209 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1210 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1211
1212 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1213 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1214 S_028004_SAMPLE_RATE(sample_rate) |
1215 S_028004_ZPASS_ENABLE(1) |
1216 S_028004_SLICE_EVEN_ENABLE(1) |
1217 S_028004_SLICE_ODD_ENABLE(1);
1218
1219 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1220 pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
1221 /* If the bound pipeline has enabled
1222 * out-of-order rasterization, we should
1223 * disable it before starting occlusion
1224 * queries.
1225 */
1226 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1227
1228 radeon_set_context_reg(cmd_buffer->cs,
1229 R_028A4C_PA_SC_MODE_CNTL_1,
1230 pa_sc_mode_cntl_1);
1231 }
1232 } else {
1233 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1234 S_028004_SAMPLE_RATE(sample_rate);
1235 }
1236 }
1237
1238 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1239 }
1240
1241 static void
1242 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1243 {
1244 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1245
1246 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1247 radv_emit_viewport(cmd_buffer);
1248
1249 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1250 radv_emit_scissor(cmd_buffer);
1251
1252 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1253 radv_emit_line_width(cmd_buffer);
1254
1255 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1256 radv_emit_blend_constants(cmd_buffer);
1257
1258 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1259 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1260 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1261 radv_emit_stencil(cmd_buffer);
1262
1263 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1264 radv_emit_depth_bounds(cmd_buffer);
1265
1266 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1267 radv_emit_depth_bias(cmd_buffer);
1268
1269 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1270 radv_emit_discard_rectangle(cmd_buffer);
1271
1272 cmd_buffer->state.dirty &= ~states;
1273 }
1274
1275 static void
1276 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1277 struct radv_pipeline *pipeline,
1278 int idx,
1279 uint64_t va,
1280 gl_shader_stage stage)
1281 {
1282 struct radv_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1283 uint32_t base_reg = pipeline->user_data_0[stage];
1284
1285 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1286 return;
1287
1288 assert(!desc_set_loc->indirect);
1289 assert(desc_set_loc->num_sgprs == 2);
1290 radeon_set_sh_reg_seq(cmd_buffer->cs,
1291 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1292 radeon_emit(cmd_buffer->cs, va);
1293 radeon_emit(cmd_buffer->cs, va >> 32);
1294 }
1295
1296 static void
1297 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1298 VkShaderStageFlags stages,
1299 struct radv_descriptor_set *set,
1300 unsigned idx)
1301 {
1302 if (cmd_buffer->state.pipeline) {
1303 radv_foreach_stage(stage, stages) {
1304 if (cmd_buffer->state.pipeline->shaders[stage])
1305 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1306 idx, set->va,
1307 stage);
1308 }
1309 }
1310
1311 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1312 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1313 idx, set->va,
1314 MESA_SHADER_COMPUTE);
1315 }
1316
1317 static void
1318 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1319 VkPipelineBindPoint bind_point)
1320 {
1321 struct radv_descriptor_state *descriptors_state =
1322 radv_get_descriptors_state(cmd_buffer, bind_point);
1323 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1324 unsigned bo_offset;
1325
1326 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1327 set->mapped_ptr,
1328 &bo_offset))
1329 return;
1330
1331 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1332 set->va += bo_offset;
1333 }
1334
1335 static void
1336 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1337 VkPipelineBindPoint bind_point)
1338 {
1339 struct radv_descriptor_state *descriptors_state =
1340 radv_get_descriptors_state(cmd_buffer, bind_point);
1341 uint32_t size = MAX_SETS * 2 * 4;
1342 uint32_t offset;
1343 void *ptr;
1344
1345 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1346 256, &offset, &ptr))
1347 return;
1348
1349 for (unsigned i = 0; i < MAX_SETS; i++) {
1350 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1351 uint64_t set_va = 0;
1352 struct radv_descriptor_set *set = descriptors_state->sets[i];
1353 if (descriptors_state->valid & (1u << i))
1354 set_va = set->va;
1355 uptr[0] = set_va & 0xffffffff;
1356 uptr[1] = set_va >> 32;
1357 }
1358
1359 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1360 va += offset;
1361
1362 if (cmd_buffer->state.pipeline) {
1363 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1364 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1365 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1366
1367 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1368 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1369 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1370
1371 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1372 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1373 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1374
1375 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1376 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1377 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1378
1379 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1380 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1381 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1382 }
1383
1384 if (cmd_buffer->state.compute_pipeline)
1385 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1386 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1387 }
1388
1389 static void
1390 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1391 VkShaderStageFlags stages)
1392 {
1393 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1394 VK_PIPELINE_BIND_POINT_COMPUTE :
1395 VK_PIPELINE_BIND_POINT_GRAPHICS;
1396 struct radv_descriptor_state *descriptors_state =
1397 radv_get_descriptors_state(cmd_buffer, bind_point);
1398 unsigned i;
1399
1400 if (!descriptors_state->dirty)
1401 return;
1402
1403 if (descriptors_state->push_dirty)
1404 radv_flush_push_descriptors(cmd_buffer, bind_point);
1405
1406 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1407 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1408 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1409 }
1410
1411 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1412 cmd_buffer->cs,
1413 MAX_SETS * MESA_SHADER_STAGES * 4);
1414
1415 for_each_bit(i, descriptors_state->dirty) {
1416 struct radv_descriptor_set *set = descriptors_state->sets[i];
1417 if (!(descriptors_state->valid & (1u << i)))
1418 continue;
1419
1420 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1421 }
1422 descriptors_state->dirty = 0;
1423 descriptors_state->push_dirty = false;
1424
1425 if (unlikely(cmd_buffer->device->trace_bo))
1426 radv_save_descriptors(cmd_buffer, bind_point);
1427
1428 assert(cmd_buffer->cs->cdw <= cdw_max);
1429 }
1430
1431 static void
1432 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1433 struct radv_pipeline *pipeline,
1434 VkShaderStageFlags stages)
1435 {
1436 struct radv_pipeline_layout *layout = pipeline->layout;
1437 unsigned offset;
1438 void *ptr;
1439 uint64_t va;
1440
1441 stages &= cmd_buffer->push_constant_stages;
1442 if (!stages ||
1443 (!layout->push_constant_size && !layout->dynamic_offset_count))
1444 return;
1445
1446 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1447 16 * layout->dynamic_offset_count,
1448 256, &offset, &ptr))
1449 return;
1450
1451 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1452 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1453 16 * layout->dynamic_offset_count);
1454
1455 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1456 va += offset;
1457
1458 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1459 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1460
1461 radv_foreach_stage(stage, stages) {
1462 if (pipeline->shaders[stage]) {
1463 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1464 AC_UD_PUSH_CONSTANTS, va);
1465 }
1466 }
1467
1468 cmd_buffer->push_constant_stages &= ~stages;
1469 assert(cmd_buffer->cs->cdw <= cdw_max);
1470 }
1471
1472 static bool
1473 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1474 {
1475 if ((pipeline_is_dirty ||
1476 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1477 cmd_buffer->state.pipeline->vertex_elements.count &&
1478 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1479 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1480 unsigned vb_offset;
1481 void *vb_ptr;
1482 uint32_t i = 0;
1483 uint32_t count = velems->count;
1484 uint64_t va;
1485
1486 /* allocate some descriptor state for vertex buffers */
1487 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1488 &vb_offset, &vb_ptr))
1489 return false;
1490
1491 for (i = 0; i < count; i++) {
1492 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1493 uint32_t offset;
1494 int vb = velems->binding[i];
1495 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1496 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1497
1498 va = radv_buffer_get_va(buffer->bo);
1499
1500 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1501 va += offset + buffer->offset;
1502 desc[0] = va;
1503 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1504 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1505 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1506 else
1507 desc[2] = buffer->size - offset;
1508 desc[3] = velems->rsrc_word3[i];
1509 }
1510
1511 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1512 va += vb_offset;
1513
1514 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1515 AC_UD_VS_VERTEX_BUFFERS, va);
1516
1517 cmd_buffer->state.vb_va = va;
1518 cmd_buffer->state.vb_size = count * 16;
1519 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1520 }
1521 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1522
1523 return true;
1524 }
1525
1526 static bool
1527 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1528 {
1529 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1530 return false;
1531
1532 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1533 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1534 VK_SHADER_STAGE_ALL_GRAPHICS);
1535
1536 return true;
1537 }
1538
1539 static void
1540 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1541 bool instanced_draw, bool indirect_draw,
1542 uint32_t draw_vertex_count)
1543 {
1544 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1545 struct radv_cmd_state *state = &cmd_buffer->state;
1546 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1547 uint32_t ia_multi_vgt_param;
1548 int32_t primitive_reset_en;
1549
1550 /* Draw state. */
1551 ia_multi_vgt_param =
1552 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1553 indirect_draw, draw_vertex_count);
1554
1555 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1556 if (info->chip_class >= GFX9) {
1557 radeon_set_uconfig_reg_idx(cs,
1558 R_030960_IA_MULTI_VGT_PARAM,
1559 4, ia_multi_vgt_param);
1560 } else if (info->chip_class >= CIK) {
1561 radeon_set_context_reg_idx(cs,
1562 R_028AA8_IA_MULTI_VGT_PARAM,
1563 1, ia_multi_vgt_param);
1564 } else {
1565 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1566 ia_multi_vgt_param);
1567 }
1568 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1569 }
1570
1571 /* Primitive restart. */
1572 primitive_reset_en =
1573 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1574
1575 if (primitive_reset_en != state->last_primitive_reset_en) {
1576 state->last_primitive_reset_en = primitive_reset_en;
1577 if (info->chip_class >= GFX9) {
1578 radeon_set_uconfig_reg(cs,
1579 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1580 primitive_reset_en);
1581 } else {
1582 radeon_set_context_reg(cs,
1583 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1584 primitive_reset_en);
1585 }
1586 }
1587
1588 if (primitive_reset_en) {
1589 uint32_t primitive_reset_index =
1590 state->index_type ? 0xffffffffu : 0xffffu;
1591
1592 if (primitive_reset_index != state->last_primitive_reset_index) {
1593 radeon_set_context_reg(cs,
1594 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1595 primitive_reset_index);
1596 state->last_primitive_reset_index = primitive_reset_index;
1597 }
1598 }
1599 }
1600
1601 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1602 VkPipelineStageFlags src_stage_mask)
1603 {
1604 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1605 VK_PIPELINE_STAGE_TRANSFER_BIT |
1606 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1607 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1608 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1609 }
1610
1611 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1612 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1613 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1614 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1615 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1616 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1617 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1618 VK_PIPELINE_STAGE_TRANSFER_BIT |
1619 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1620 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1621 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1622 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1623 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1624 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1625 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1626 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1627 }
1628 }
1629
1630 static enum radv_cmd_flush_bits
1631 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1632 VkAccessFlags src_flags)
1633 {
1634 enum radv_cmd_flush_bits flush_bits = 0;
1635 uint32_t b;
1636 for_each_bit(b, src_flags) {
1637 switch ((VkAccessFlagBits)(1 << b)) {
1638 case VK_ACCESS_SHADER_WRITE_BIT:
1639 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1640 break;
1641 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1642 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1643 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1644 break;
1645 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1646 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1647 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1648 break;
1649 case VK_ACCESS_TRANSFER_WRITE_BIT:
1650 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1651 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1652 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1653 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1654 RADV_CMD_FLAG_INV_GLOBAL_L2;
1655 break;
1656 default:
1657 break;
1658 }
1659 }
1660 return flush_bits;
1661 }
1662
1663 static enum radv_cmd_flush_bits
1664 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1665 VkAccessFlags dst_flags,
1666 struct radv_image *image)
1667 {
1668 enum radv_cmd_flush_bits flush_bits = 0;
1669 uint32_t b;
1670 for_each_bit(b, dst_flags) {
1671 switch ((VkAccessFlagBits)(1 << b)) {
1672 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1673 case VK_ACCESS_INDEX_READ_BIT:
1674 break;
1675 case VK_ACCESS_UNIFORM_READ_BIT:
1676 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1677 break;
1678 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1679 case VK_ACCESS_SHADER_READ_BIT:
1680 case VK_ACCESS_TRANSFER_READ_BIT:
1681 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1682 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1683 RADV_CMD_FLAG_INV_GLOBAL_L2;
1684 break;
1685 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1686 /* TODO: change to image && when the image gets passed
1687 * through from the subpass. */
1688 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1689 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1690 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1691 break;
1692 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1693 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1694 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1695 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1696 break;
1697 default:
1698 break;
1699 }
1700 }
1701 return flush_bits;
1702 }
1703
1704 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1705 {
1706 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1707 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1708 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1709 NULL);
1710 }
1711
1712 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1713 VkAttachmentReference att)
1714 {
1715 unsigned idx = att.attachment;
1716 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1717 VkImageSubresourceRange range;
1718 range.aspectMask = 0;
1719 range.baseMipLevel = view->base_mip;
1720 range.levelCount = 1;
1721 range.baseArrayLayer = view->base_layer;
1722 range.layerCount = cmd_buffer->state.framebuffer->layers;
1723
1724 radv_handle_image_transition(cmd_buffer,
1725 view->image,
1726 cmd_buffer->state.attachments[idx].current_layout,
1727 att.layout, 0, 0, &range,
1728 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1729
1730 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1731
1732
1733 }
1734
1735 void
1736 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1737 const struct radv_subpass *subpass, bool transitions)
1738 {
1739 if (transitions) {
1740 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1741
1742 for (unsigned i = 0; i < subpass->color_count; ++i) {
1743 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1744 radv_handle_subpass_image_transition(cmd_buffer,
1745 subpass->color_attachments[i]);
1746 }
1747
1748 for (unsigned i = 0; i < subpass->input_count; ++i) {
1749 radv_handle_subpass_image_transition(cmd_buffer,
1750 subpass->input_attachments[i]);
1751 }
1752
1753 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1754 radv_handle_subpass_image_transition(cmd_buffer,
1755 subpass->depth_stencil_attachment);
1756 }
1757 }
1758
1759 cmd_buffer->state.subpass = subpass;
1760
1761 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
1762 }
1763
1764 static VkResult
1765 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1766 struct radv_render_pass *pass,
1767 const VkRenderPassBeginInfo *info)
1768 {
1769 struct radv_cmd_state *state = &cmd_buffer->state;
1770
1771 if (pass->attachment_count == 0) {
1772 state->attachments = NULL;
1773 return VK_SUCCESS;
1774 }
1775
1776 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1777 pass->attachment_count *
1778 sizeof(state->attachments[0]),
1779 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1780 if (state->attachments == NULL) {
1781 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1782 return cmd_buffer->record_result;
1783 }
1784
1785 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1786 struct radv_render_pass_attachment *att = &pass->attachments[i];
1787 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1788 VkImageAspectFlags clear_aspects = 0;
1789
1790 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1791 /* color attachment */
1792 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1793 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1794 }
1795 } else {
1796 /* depthstencil attachment */
1797 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1798 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1799 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1800 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1801 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1802 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1803 }
1804 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1805 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1806 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1807 }
1808 }
1809
1810 state->attachments[i].pending_clear_aspects = clear_aspects;
1811 state->attachments[i].cleared_views = 0;
1812 if (clear_aspects && info) {
1813 assert(info->clearValueCount > i);
1814 state->attachments[i].clear_value = info->pClearValues[i];
1815 }
1816
1817 state->attachments[i].current_layout = att->initial_layout;
1818 }
1819
1820 return VK_SUCCESS;
1821 }
1822
1823 VkResult radv_AllocateCommandBuffers(
1824 VkDevice _device,
1825 const VkCommandBufferAllocateInfo *pAllocateInfo,
1826 VkCommandBuffer *pCommandBuffers)
1827 {
1828 RADV_FROM_HANDLE(radv_device, device, _device);
1829 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1830
1831 VkResult result = VK_SUCCESS;
1832 uint32_t i;
1833
1834 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1835
1836 if (!list_empty(&pool->free_cmd_buffers)) {
1837 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1838
1839 list_del(&cmd_buffer->pool_link);
1840 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1841
1842 result = radv_reset_cmd_buffer(cmd_buffer);
1843 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1844 cmd_buffer->level = pAllocateInfo->level;
1845
1846 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1847 } else {
1848 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1849 &pCommandBuffers[i]);
1850 }
1851 if (result != VK_SUCCESS)
1852 break;
1853 }
1854
1855 if (result != VK_SUCCESS) {
1856 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1857 i, pCommandBuffers);
1858
1859 /* From the Vulkan 1.0.66 spec:
1860 *
1861 * "vkAllocateCommandBuffers can be used to create multiple
1862 * command buffers. If the creation of any of those command
1863 * buffers fails, the implementation must destroy all
1864 * successfully created command buffer objects from this
1865 * command, set all entries of the pCommandBuffers array to
1866 * NULL and return the error."
1867 */
1868 memset(pCommandBuffers, 0,
1869 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1870 }
1871
1872 return result;
1873 }
1874
1875 void radv_FreeCommandBuffers(
1876 VkDevice device,
1877 VkCommandPool commandPool,
1878 uint32_t commandBufferCount,
1879 const VkCommandBuffer *pCommandBuffers)
1880 {
1881 for (uint32_t i = 0; i < commandBufferCount; i++) {
1882 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1883
1884 if (cmd_buffer) {
1885 if (cmd_buffer->pool) {
1886 list_del(&cmd_buffer->pool_link);
1887 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1888 } else
1889 radv_cmd_buffer_destroy(cmd_buffer);
1890
1891 }
1892 }
1893 }
1894
1895 VkResult radv_ResetCommandBuffer(
1896 VkCommandBuffer commandBuffer,
1897 VkCommandBufferResetFlags flags)
1898 {
1899 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1900 return radv_reset_cmd_buffer(cmd_buffer);
1901 }
1902
1903 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1904 {
1905 struct radv_device *device = cmd_buffer->device;
1906 if (device->gfx_init) {
1907 uint64_t va = radv_buffer_get_va(device->gfx_init);
1908 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
1909 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1910 radeon_emit(cmd_buffer->cs, va);
1911 radeon_emit(cmd_buffer->cs, va >> 32);
1912 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1913 } else
1914 si_init_config(cmd_buffer);
1915 }
1916
1917 VkResult radv_BeginCommandBuffer(
1918 VkCommandBuffer commandBuffer,
1919 const VkCommandBufferBeginInfo *pBeginInfo)
1920 {
1921 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1922 VkResult result = VK_SUCCESS;
1923
1924 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
1925 /* If the command buffer has already been resetted with
1926 * vkResetCommandBuffer, no need to do it again.
1927 */
1928 result = radv_reset_cmd_buffer(cmd_buffer);
1929 if (result != VK_SUCCESS)
1930 return result;
1931 }
1932
1933 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1934 cmd_buffer->state.last_primitive_reset_en = -1;
1935 cmd_buffer->state.last_index_type = -1;
1936 cmd_buffer->state.last_num_instances = -1;
1937 cmd_buffer->state.last_vertex_offset = -1;
1938 cmd_buffer->state.last_first_instance = -1;
1939 cmd_buffer->usage_flags = pBeginInfo->flags;
1940
1941 /* setup initial configuration into command buffer */
1942 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1943 switch (cmd_buffer->queue_family_index) {
1944 case RADV_QUEUE_GENERAL:
1945 emit_gfx_buffer_state(cmd_buffer);
1946 break;
1947 case RADV_QUEUE_COMPUTE:
1948 si_init_compute(cmd_buffer);
1949 break;
1950 case RADV_QUEUE_TRANSFER:
1951 default:
1952 break;
1953 }
1954 }
1955
1956 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1957 assert(pBeginInfo->pInheritanceInfo);
1958 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1959 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1960
1961 struct radv_subpass *subpass =
1962 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1963
1964 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1965 if (result != VK_SUCCESS)
1966 return result;
1967
1968 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1969 }
1970
1971 if (unlikely(cmd_buffer->device->trace_bo))
1972 radv_cmd_buffer_trace_emit(cmd_buffer);
1973
1974 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
1975
1976 return result;
1977 }
1978
1979 void radv_CmdBindVertexBuffers(
1980 VkCommandBuffer commandBuffer,
1981 uint32_t firstBinding,
1982 uint32_t bindingCount,
1983 const VkBuffer* pBuffers,
1984 const VkDeviceSize* pOffsets)
1985 {
1986 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1987 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
1988 bool changed = false;
1989
1990 /* We have to defer setting up vertex buffer since we need the buffer
1991 * stride from the pipeline. */
1992
1993 assert(firstBinding + bindingCount <= MAX_VBS);
1994 for (uint32_t i = 0; i < bindingCount; i++) {
1995 uint32_t idx = firstBinding + i;
1996
1997 if (!changed &&
1998 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
1999 vb[idx].offset != pOffsets[i])) {
2000 changed = true;
2001 }
2002
2003 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2004 vb[idx].offset = pOffsets[i];
2005
2006 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2007 vb[idx].buffer->bo, 8);
2008 }
2009
2010 if (!changed) {
2011 /* No state changes. */
2012 return;
2013 }
2014
2015 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2016 }
2017
2018 void radv_CmdBindIndexBuffer(
2019 VkCommandBuffer commandBuffer,
2020 VkBuffer buffer,
2021 VkDeviceSize offset,
2022 VkIndexType indexType)
2023 {
2024 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2025 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2026
2027 if (cmd_buffer->state.index_buffer == index_buffer &&
2028 cmd_buffer->state.index_offset == offset &&
2029 cmd_buffer->state.index_type == indexType) {
2030 /* No state changes. */
2031 return;
2032 }
2033
2034 cmd_buffer->state.index_buffer = index_buffer;
2035 cmd_buffer->state.index_offset = offset;
2036 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2037 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2038 cmd_buffer->state.index_va += index_buffer->offset + offset;
2039
2040 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2041 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2042 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2043 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2044 }
2045
2046
2047 static void
2048 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2049 VkPipelineBindPoint bind_point,
2050 struct radv_descriptor_set *set, unsigned idx)
2051 {
2052 struct radeon_winsys *ws = cmd_buffer->device->ws;
2053
2054 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2055 if (!set)
2056 return;
2057
2058 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2059
2060 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2061 if (set->descriptors[j])
2062 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2063
2064 if(set->bo)
2065 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2066 }
2067
2068 void radv_CmdBindDescriptorSets(
2069 VkCommandBuffer commandBuffer,
2070 VkPipelineBindPoint pipelineBindPoint,
2071 VkPipelineLayout _layout,
2072 uint32_t firstSet,
2073 uint32_t descriptorSetCount,
2074 const VkDescriptorSet* pDescriptorSets,
2075 uint32_t dynamicOffsetCount,
2076 const uint32_t* pDynamicOffsets)
2077 {
2078 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2079 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2080 unsigned dyn_idx = 0;
2081
2082 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2083 unsigned idx = i + firstSet;
2084 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2085 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2086
2087 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2088 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2089 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2090 assert(dyn_idx < dynamicOffsetCount);
2091
2092 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2093 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2094 dst[0] = va;
2095 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2096 dst[2] = range->size;
2097 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2098 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2099 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2100 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2101 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2102 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2103 cmd_buffer->push_constant_stages |=
2104 set->layout->dynamic_shader_stages;
2105 }
2106 }
2107 }
2108
2109 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2110 struct radv_descriptor_set *set,
2111 struct radv_descriptor_set_layout *layout,
2112 VkPipelineBindPoint bind_point)
2113 {
2114 struct radv_descriptor_state *descriptors_state =
2115 radv_get_descriptors_state(cmd_buffer, bind_point);
2116 set->size = layout->size;
2117 set->layout = layout;
2118
2119 if (descriptors_state->push_set.capacity < set->size) {
2120 size_t new_size = MAX2(set->size, 1024);
2121 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2122 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2123
2124 free(set->mapped_ptr);
2125 set->mapped_ptr = malloc(new_size);
2126
2127 if (!set->mapped_ptr) {
2128 descriptors_state->push_set.capacity = 0;
2129 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2130 return false;
2131 }
2132
2133 descriptors_state->push_set.capacity = new_size;
2134 }
2135
2136 return true;
2137 }
2138
2139 void radv_meta_push_descriptor_set(
2140 struct radv_cmd_buffer* cmd_buffer,
2141 VkPipelineBindPoint pipelineBindPoint,
2142 VkPipelineLayout _layout,
2143 uint32_t set,
2144 uint32_t descriptorWriteCount,
2145 const VkWriteDescriptorSet* pDescriptorWrites)
2146 {
2147 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2148 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2149 unsigned bo_offset;
2150
2151 assert(set == 0);
2152 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2153
2154 push_set->size = layout->set[set].layout->size;
2155 push_set->layout = layout->set[set].layout;
2156
2157 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2158 &bo_offset,
2159 (void**) &push_set->mapped_ptr))
2160 return;
2161
2162 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2163 push_set->va += bo_offset;
2164
2165 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2166 radv_descriptor_set_to_handle(push_set),
2167 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2168
2169 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2170 }
2171
2172 void radv_CmdPushDescriptorSetKHR(
2173 VkCommandBuffer commandBuffer,
2174 VkPipelineBindPoint pipelineBindPoint,
2175 VkPipelineLayout _layout,
2176 uint32_t set,
2177 uint32_t descriptorWriteCount,
2178 const VkWriteDescriptorSet* pDescriptorWrites)
2179 {
2180 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2181 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2182 struct radv_descriptor_state *descriptors_state =
2183 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2184 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2185
2186 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2187
2188 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2189 layout->set[set].layout,
2190 pipelineBindPoint))
2191 return;
2192
2193 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2194 radv_descriptor_set_to_handle(push_set),
2195 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2196
2197 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2198 descriptors_state->push_dirty = true;
2199 }
2200
2201 void radv_CmdPushDescriptorSetWithTemplateKHR(
2202 VkCommandBuffer commandBuffer,
2203 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2204 VkPipelineLayout _layout,
2205 uint32_t set,
2206 const void* pData)
2207 {
2208 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2209 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2210 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2211 struct radv_descriptor_state *descriptors_state =
2212 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2213 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2214
2215 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2216
2217 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2218 layout->set[set].layout,
2219 templ->bind_point))
2220 return;
2221
2222 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2223 descriptorUpdateTemplate, pData);
2224
2225 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2226 descriptors_state->push_dirty = true;
2227 }
2228
2229 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2230 VkPipelineLayout layout,
2231 VkShaderStageFlags stageFlags,
2232 uint32_t offset,
2233 uint32_t size,
2234 const void* pValues)
2235 {
2236 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2237 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2238 cmd_buffer->push_constant_stages |= stageFlags;
2239 }
2240
2241 VkResult radv_EndCommandBuffer(
2242 VkCommandBuffer commandBuffer)
2243 {
2244 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2245
2246 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2247 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2248 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2249 si_emit_cache_flush(cmd_buffer);
2250 }
2251
2252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2253
2254 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2255 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2256
2257 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2258
2259 return cmd_buffer->record_result;
2260 }
2261
2262 static void
2263 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2264 {
2265 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2266
2267 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2268 return;
2269
2270 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2271
2272 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2273 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2274
2275 cmd_buffer->compute_scratch_size_needed =
2276 MAX2(cmd_buffer->compute_scratch_size_needed,
2277 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2278
2279 if (unlikely(cmd_buffer->device->trace_bo))
2280 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2281 }
2282
2283 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2284 VkPipelineBindPoint bind_point)
2285 {
2286 struct radv_descriptor_state *descriptors_state =
2287 radv_get_descriptors_state(cmd_buffer, bind_point);
2288
2289 descriptors_state->dirty |= descriptors_state->valid;
2290 }
2291
2292 void radv_CmdBindPipeline(
2293 VkCommandBuffer commandBuffer,
2294 VkPipelineBindPoint pipelineBindPoint,
2295 VkPipeline _pipeline)
2296 {
2297 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2298 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2299
2300 switch (pipelineBindPoint) {
2301 case VK_PIPELINE_BIND_POINT_COMPUTE:
2302 if (cmd_buffer->state.compute_pipeline == pipeline)
2303 return;
2304 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2305
2306 cmd_buffer->state.compute_pipeline = pipeline;
2307 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2308 break;
2309 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2310 if (cmd_buffer->state.pipeline == pipeline)
2311 return;
2312 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2313
2314 cmd_buffer->state.pipeline = pipeline;
2315 if (!pipeline)
2316 break;
2317
2318 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2319 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2320
2321 /* the new vertex shader might not have the same user regs */
2322 cmd_buffer->state.last_first_instance = -1;
2323 cmd_buffer->state.last_vertex_offset = -1;
2324
2325 /* Prefetch all pipeline shaders at first draw time. */
2326 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2327
2328 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2329
2330 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2331 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2332 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2333 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2334
2335 if (radv_pipeline_has_tess(pipeline))
2336 cmd_buffer->tess_rings_needed = true;
2337
2338 if (radv_pipeline_has_gs(pipeline)) {
2339 struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2340 AC_UD_SCRATCH_RING_OFFSETS);
2341 if (cmd_buffer->ring_offsets_idx == -1)
2342 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2343 else if (loc->sgpr_idx != -1)
2344 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2345 }
2346 break;
2347 default:
2348 assert(!"invalid bind point");
2349 break;
2350 }
2351 }
2352
2353 void radv_CmdSetViewport(
2354 VkCommandBuffer commandBuffer,
2355 uint32_t firstViewport,
2356 uint32_t viewportCount,
2357 const VkViewport* pViewports)
2358 {
2359 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2360 struct radv_cmd_state *state = &cmd_buffer->state;
2361 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2362
2363 assert(firstViewport < MAX_VIEWPORTS);
2364 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2365
2366 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2367 /* Try to skip unnecessary PS partial flushes when the viewports
2368 * don't change.
2369 */
2370 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2371 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2372 !memcmp(state->dynamic.viewport.viewports + firstViewport,
2373 pViewports, viewportCount * sizeof(*pViewports))) {
2374 return;
2375 }
2376 }
2377
2378 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2379 viewportCount * sizeof(*pViewports));
2380
2381 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2382 }
2383
2384 void radv_CmdSetScissor(
2385 VkCommandBuffer commandBuffer,
2386 uint32_t firstScissor,
2387 uint32_t scissorCount,
2388 const VkRect2D* pScissors)
2389 {
2390 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2391 struct radv_cmd_state *state = &cmd_buffer->state;
2392 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2393
2394 assert(firstScissor < MAX_SCISSORS);
2395 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2396
2397 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2398 /* Try to skip unnecessary PS partial flushes when the scissors
2399 * don't change.
2400 */
2401 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2402 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2403 !memcmp(state->dynamic.scissor.scissors + firstScissor,
2404 pScissors, scissorCount * sizeof(*pScissors))) {
2405 return;
2406 }
2407 }
2408
2409 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2410 scissorCount * sizeof(*pScissors));
2411
2412 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2413 }
2414
2415 void radv_CmdSetLineWidth(
2416 VkCommandBuffer commandBuffer,
2417 float lineWidth)
2418 {
2419 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2420 cmd_buffer->state.dynamic.line_width = lineWidth;
2421 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2422 }
2423
2424 void radv_CmdSetDepthBias(
2425 VkCommandBuffer commandBuffer,
2426 float depthBiasConstantFactor,
2427 float depthBiasClamp,
2428 float depthBiasSlopeFactor)
2429 {
2430 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2431
2432 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2433 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2434 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2435
2436 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2437 }
2438
2439 void radv_CmdSetBlendConstants(
2440 VkCommandBuffer commandBuffer,
2441 const float blendConstants[4])
2442 {
2443 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2444
2445 memcpy(cmd_buffer->state.dynamic.blend_constants,
2446 blendConstants, sizeof(float) * 4);
2447
2448 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2449 }
2450
2451 void radv_CmdSetDepthBounds(
2452 VkCommandBuffer commandBuffer,
2453 float minDepthBounds,
2454 float maxDepthBounds)
2455 {
2456 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2457
2458 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2459 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2460
2461 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2462 }
2463
2464 void radv_CmdSetStencilCompareMask(
2465 VkCommandBuffer commandBuffer,
2466 VkStencilFaceFlags faceMask,
2467 uint32_t compareMask)
2468 {
2469 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2470
2471 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2472 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2473 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2474 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2475
2476 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2477 }
2478
2479 void radv_CmdSetStencilWriteMask(
2480 VkCommandBuffer commandBuffer,
2481 VkStencilFaceFlags faceMask,
2482 uint32_t writeMask)
2483 {
2484 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2485
2486 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2487 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2488 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2489 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2490
2491 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2492 }
2493
2494 void radv_CmdSetStencilReference(
2495 VkCommandBuffer commandBuffer,
2496 VkStencilFaceFlags faceMask,
2497 uint32_t reference)
2498 {
2499 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2500
2501 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2502 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2503 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2504 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2505
2506 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2507 }
2508
2509 void radv_CmdSetDiscardRectangleEXT(
2510 VkCommandBuffer commandBuffer,
2511 uint32_t firstDiscardRectangle,
2512 uint32_t discardRectangleCount,
2513 const VkRect2D* pDiscardRectangles)
2514 {
2515 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2516 struct radv_cmd_state *state = &cmd_buffer->state;
2517 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2518
2519 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2520 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2521
2522 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2523 pDiscardRectangles, discardRectangleCount);
2524
2525 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2526 }
2527
2528 void radv_CmdExecuteCommands(
2529 VkCommandBuffer commandBuffer,
2530 uint32_t commandBufferCount,
2531 const VkCommandBuffer* pCmdBuffers)
2532 {
2533 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2534
2535 assert(commandBufferCount > 0);
2536
2537 /* Emit pending flushes on primary prior to executing secondary */
2538 si_emit_cache_flush(primary);
2539
2540 for (uint32_t i = 0; i < commandBufferCount; i++) {
2541 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2542
2543 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2544 secondary->scratch_size_needed);
2545 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2546 secondary->compute_scratch_size_needed);
2547
2548 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2549 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2550 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2551 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2552 if (secondary->tess_rings_needed)
2553 primary->tess_rings_needed = true;
2554 if (secondary->sample_positions_needed)
2555 primary->sample_positions_needed = true;
2556
2557 if (secondary->ring_offsets_idx != -1) {
2558 if (primary->ring_offsets_idx == -1)
2559 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2560 else
2561 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2562 }
2563 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2564
2565
2566 /* When the secondary command buffer is compute only we don't
2567 * need to re-emit the current graphics pipeline.
2568 */
2569 if (secondary->state.emitted_pipeline) {
2570 primary->state.emitted_pipeline =
2571 secondary->state.emitted_pipeline;
2572 }
2573
2574 /* When the secondary command buffer is graphics only we don't
2575 * need to re-emit the current compute pipeline.
2576 */
2577 if (secondary->state.emitted_compute_pipeline) {
2578 primary->state.emitted_compute_pipeline =
2579 secondary->state.emitted_compute_pipeline;
2580 }
2581
2582 /* Only re-emit the draw packets when needed. */
2583 if (secondary->state.last_primitive_reset_en != -1) {
2584 primary->state.last_primitive_reset_en =
2585 secondary->state.last_primitive_reset_en;
2586 }
2587
2588 if (secondary->state.last_primitive_reset_index) {
2589 primary->state.last_primitive_reset_index =
2590 secondary->state.last_primitive_reset_index;
2591 }
2592
2593 if (secondary->state.last_ia_multi_vgt_param) {
2594 primary->state.last_ia_multi_vgt_param =
2595 secondary->state.last_ia_multi_vgt_param;
2596 }
2597
2598 if (secondary->state.last_first_instance != -1) {
2599 primary->state.last_first_instance =
2600 secondary->state.last_first_instance;
2601 }
2602
2603 if (secondary->state.last_num_instances != -1) {
2604 primary->state.last_num_instances =
2605 secondary->state.last_num_instances;
2606 }
2607
2608 if (secondary->state.last_vertex_offset != -1) {
2609 primary->state.last_vertex_offset =
2610 secondary->state.last_vertex_offset;
2611 }
2612
2613 if (secondary->state.last_index_type != -1) {
2614 primary->state.last_index_type =
2615 secondary->state.last_index_type;
2616 }
2617 }
2618
2619 /* After executing commands from secondary buffers we have to dirty
2620 * some states.
2621 */
2622 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2623 RADV_CMD_DIRTY_INDEX_BUFFER |
2624 RADV_CMD_DIRTY_DYNAMIC_ALL;
2625 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2626 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2627 }
2628
2629 VkResult radv_CreateCommandPool(
2630 VkDevice _device,
2631 const VkCommandPoolCreateInfo* pCreateInfo,
2632 const VkAllocationCallbacks* pAllocator,
2633 VkCommandPool* pCmdPool)
2634 {
2635 RADV_FROM_HANDLE(radv_device, device, _device);
2636 struct radv_cmd_pool *pool;
2637
2638 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2639 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2640 if (pool == NULL)
2641 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2642
2643 if (pAllocator)
2644 pool->alloc = *pAllocator;
2645 else
2646 pool->alloc = device->alloc;
2647
2648 list_inithead(&pool->cmd_buffers);
2649 list_inithead(&pool->free_cmd_buffers);
2650
2651 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2652
2653 *pCmdPool = radv_cmd_pool_to_handle(pool);
2654
2655 return VK_SUCCESS;
2656
2657 }
2658
2659 void radv_DestroyCommandPool(
2660 VkDevice _device,
2661 VkCommandPool commandPool,
2662 const VkAllocationCallbacks* pAllocator)
2663 {
2664 RADV_FROM_HANDLE(radv_device, device, _device);
2665 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2666
2667 if (!pool)
2668 return;
2669
2670 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2671 &pool->cmd_buffers, pool_link) {
2672 radv_cmd_buffer_destroy(cmd_buffer);
2673 }
2674
2675 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2676 &pool->free_cmd_buffers, pool_link) {
2677 radv_cmd_buffer_destroy(cmd_buffer);
2678 }
2679
2680 vk_free2(&device->alloc, pAllocator, pool);
2681 }
2682
2683 VkResult radv_ResetCommandPool(
2684 VkDevice device,
2685 VkCommandPool commandPool,
2686 VkCommandPoolResetFlags flags)
2687 {
2688 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2689 VkResult result;
2690
2691 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2692 &pool->cmd_buffers, pool_link) {
2693 result = radv_reset_cmd_buffer(cmd_buffer);
2694 if (result != VK_SUCCESS)
2695 return result;
2696 }
2697
2698 return VK_SUCCESS;
2699 }
2700
2701 void radv_TrimCommandPool(
2702 VkDevice device,
2703 VkCommandPool commandPool,
2704 VkCommandPoolTrimFlagsKHR flags)
2705 {
2706 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2707
2708 if (!pool)
2709 return;
2710
2711 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2712 &pool->free_cmd_buffers, pool_link) {
2713 radv_cmd_buffer_destroy(cmd_buffer);
2714 }
2715 }
2716
2717 void radv_CmdBeginRenderPass(
2718 VkCommandBuffer commandBuffer,
2719 const VkRenderPassBeginInfo* pRenderPassBegin,
2720 VkSubpassContents contents)
2721 {
2722 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2723 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2724 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2725
2726 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2727 cmd_buffer->cs, 2048);
2728 MAYBE_UNUSED VkResult result;
2729
2730 cmd_buffer->state.framebuffer = framebuffer;
2731 cmd_buffer->state.pass = pass;
2732 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2733
2734 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2735 if (result != VK_SUCCESS)
2736 return;
2737
2738 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2739 assert(cmd_buffer->cs->cdw <= cdw_max);
2740
2741 radv_cmd_buffer_clear_subpass(cmd_buffer);
2742 }
2743
2744 void radv_CmdNextSubpass(
2745 VkCommandBuffer commandBuffer,
2746 VkSubpassContents contents)
2747 {
2748 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2749
2750 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2751
2752 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2753 2048);
2754
2755 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2756 radv_cmd_buffer_clear_subpass(cmd_buffer);
2757 }
2758
2759 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2760 {
2761 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2762 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2763 if (!pipeline->shaders[stage])
2764 continue;
2765 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2766 if (loc->sgpr_idx == -1)
2767 continue;
2768 uint32_t base_reg = pipeline->user_data_0[stage];
2769 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2770
2771 }
2772 if (pipeline->gs_copy_shader) {
2773 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2774 if (loc->sgpr_idx != -1) {
2775 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2776 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2777 }
2778 }
2779 }
2780
2781 static void
2782 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2783 uint32_t vertex_count)
2784 {
2785 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2786 radeon_emit(cmd_buffer->cs, vertex_count);
2787 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2788 S_0287F0_USE_OPAQUE(0));
2789 }
2790
2791 static void
2792 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2793 uint64_t index_va,
2794 uint32_t index_count)
2795 {
2796 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2797 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2798 radeon_emit(cmd_buffer->cs, index_va);
2799 radeon_emit(cmd_buffer->cs, index_va >> 32);
2800 radeon_emit(cmd_buffer->cs, index_count);
2801 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2802 }
2803
2804 static void
2805 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2806 bool indexed,
2807 uint32_t draw_count,
2808 uint64_t count_va,
2809 uint32_t stride)
2810 {
2811 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2812 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2813 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2814 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
2815 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2816 assert(base_reg);
2817
2818 /* just reset draw state for vertex data */
2819 cmd_buffer->state.last_first_instance = -1;
2820 cmd_buffer->state.last_num_instances = -1;
2821 cmd_buffer->state.last_vertex_offset = -1;
2822
2823 if (draw_count == 1 && !count_va && !draw_id_enable) {
2824 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2825 PKT3_DRAW_INDIRECT, 3, false));
2826 radeon_emit(cs, 0);
2827 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2828 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2829 radeon_emit(cs, di_src_sel);
2830 } else {
2831 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2832 PKT3_DRAW_INDIRECT_MULTI,
2833 8, false));
2834 radeon_emit(cs, 0);
2835 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2836 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2837 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2838 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2839 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2840 radeon_emit(cs, draw_count); /* count */
2841 radeon_emit(cs, count_va); /* count_addr */
2842 radeon_emit(cs, count_va >> 32);
2843 radeon_emit(cs, stride); /* stride */
2844 radeon_emit(cs, di_src_sel);
2845 }
2846 }
2847
2848 struct radv_draw_info {
2849 /**
2850 * Number of vertices.
2851 */
2852 uint32_t count;
2853
2854 /**
2855 * Index of the first vertex.
2856 */
2857 int32_t vertex_offset;
2858
2859 /**
2860 * First instance id.
2861 */
2862 uint32_t first_instance;
2863
2864 /**
2865 * Number of instances.
2866 */
2867 uint32_t instance_count;
2868
2869 /**
2870 * First index (indexed draws only).
2871 */
2872 uint32_t first_index;
2873
2874 /**
2875 * Whether it's an indexed draw.
2876 */
2877 bool indexed;
2878
2879 /**
2880 * Indirect draw parameters resource.
2881 */
2882 struct radv_buffer *indirect;
2883 uint64_t indirect_offset;
2884 uint32_t stride;
2885
2886 /**
2887 * Draw count parameters resource.
2888 */
2889 struct radv_buffer *count_buffer;
2890 uint64_t count_buffer_offset;
2891 };
2892
2893 static void
2894 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
2895 const struct radv_draw_info *info)
2896 {
2897 struct radv_cmd_state *state = &cmd_buffer->state;
2898 struct radeon_winsys *ws = cmd_buffer->device->ws;
2899 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2900
2901 if (info->indirect) {
2902 uint64_t va = radv_buffer_get_va(info->indirect->bo);
2903 uint64_t count_va = 0;
2904
2905 va += info->indirect->offset + info->indirect_offset;
2906
2907 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
2908
2909 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2910 radeon_emit(cs, 1);
2911 radeon_emit(cs, va);
2912 radeon_emit(cs, va >> 32);
2913
2914 if (info->count_buffer) {
2915 count_va = radv_buffer_get_va(info->count_buffer->bo);
2916 count_va += info->count_buffer->offset +
2917 info->count_buffer_offset;
2918
2919 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
2920 }
2921
2922 if (!state->subpass->view_mask) {
2923 radv_cs_emit_indirect_draw_packet(cmd_buffer,
2924 info->indexed,
2925 info->count,
2926 count_va,
2927 info->stride);
2928 } else {
2929 unsigned i;
2930 for_each_bit(i, state->subpass->view_mask) {
2931 radv_emit_view_index(cmd_buffer, i);
2932
2933 radv_cs_emit_indirect_draw_packet(cmd_buffer,
2934 info->indexed,
2935 info->count,
2936 count_va,
2937 info->stride);
2938 }
2939 }
2940 } else {
2941 assert(state->pipeline->graphics.vtx_base_sgpr);
2942
2943 if (info->vertex_offset != state->last_vertex_offset ||
2944 info->first_instance != state->last_first_instance) {
2945 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
2946 state->pipeline->graphics.vtx_emit_num);
2947
2948 radeon_emit(cs, info->vertex_offset);
2949 radeon_emit(cs, info->first_instance);
2950 if (state->pipeline->graphics.vtx_emit_num == 3)
2951 radeon_emit(cs, 0);
2952 state->last_first_instance = info->first_instance;
2953 state->last_vertex_offset = info->vertex_offset;
2954 }
2955
2956 if (state->last_num_instances != info->instance_count) {
2957 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
2958 radeon_emit(cs, info->instance_count);
2959 state->last_num_instances = info->instance_count;
2960 }
2961
2962 if (info->indexed) {
2963 int index_size = state->index_type ? 4 : 2;
2964 uint64_t index_va;
2965
2966 index_va = state->index_va;
2967 index_va += info->first_index * index_size;
2968
2969 if (!state->subpass->view_mask) {
2970 radv_cs_emit_draw_indexed_packet(cmd_buffer,
2971 index_va,
2972 info->count);
2973 } else {
2974 unsigned i;
2975 for_each_bit(i, state->subpass->view_mask) {
2976 radv_emit_view_index(cmd_buffer, i);
2977
2978 radv_cs_emit_draw_indexed_packet(cmd_buffer,
2979 index_va,
2980 info->count);
2981 }
2982 }
2983 } else {
2984 if (!state->subpass->view_mask) {
2985 radv_cs_emit_draw_packet(cmd_buffer, info->count);
2986 } else {
2987 unsigned i;
2988 for_each_bit(i, state->subpass->view_mask) {
2989 radv_emit_view_index(cmd_buffer, i);
2990
2991 radv_cs_emit_draw_packet(cmd_buffer,
2992 info->count);
2993 }
2994 }
2995 }
2996 }
2997 }
2998
2999 static void
3000 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3001 const struct radv_draw_info *info)
3002 {
3003 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3004 radv_emit_graphics_pipeline(cmd_buffer);
3005
3006 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3007 radv_emit_framebuffer_state(cmd_buffer);
3008
3009 if (info->indexed) {
3010 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3011 radv_emit_index_buffer(cmd_buffer);
3012 } else {
3013 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3014 * so the state must be re-emitted before the next indexed
3015 * draw.
3016 */
3017 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3018 cmd_buffer->state.last_index_type = -1;
3019 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3020 }
3021 }
3022
3023 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3024
3025 radv_emit_draw_registers(cmd_buffer, info->indexed,
3026 info->instance_count > 1, info->indirect,
3027 info->indirect ? 0 : info->count);
3028 }
3029
3030 static void
3031 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3032 const struct radv_draw_info *info)
3033 {
3034 bool pipeline_is_dirty =
3035 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3036 cmd_buffer->state.pipeline &&
3037 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3038
3039 MAYBE_UNUSED unsigned cdw_max =
3040 radeon_check_space(cmd_buffer->device->ws,
3041 cmd_buffer->cs, 4096);
3042
3043 /* Use optimal packet order based on whether we need to sync the
3044 * pipeline.
3045 */
3046 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3047 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3048 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3049 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3050 /* If we have to wait for idle, set all states first, so that
3051 * all SET packets are processed in parallel with previous draw
3052 * calls. Then upload descriptors, set shader pointers, and
3053 * draw, and prefetch at the end. This ensures that the time
3054 * the CUs are idle is very short. (there are only SET_SH
3055 * packets between the wait and the draw)
3056 */
3057 radv_emit_all_graphics_states(cmd_buffer, info);
3058 si_emit_cache_flush(cmd_buffer);
3059 /* <-- CUs are idle here --> */
3060
3061 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3062 return;
3063
3064 radv_emit_draw_packets(cmd_buffer, info);
3065 /* <-- CUs are busy here --> */
3066
3067 /* Start prefetches after the draw has been started. Both will
3068 * run in parallel, but starting the draw first is more
3069 * important.
3070 */
3071 if (cmd_buffer->state.prefetch_L2_mask) {
3072 radv_emit_prefetch_L2(cmd_buffer,
3073 cmd_buffer->state.pipeline);
3074 }
3075 } else {
3076 /* If we don't wait for idle, start prefetches first, then set
3077 * states, and draw at the end.
3078 */
3079 si_emit_cache_flush(cmd_buffer);
3080
3081 if (cmd_buffer->state.prefetch_L2_mask) {
3082 radv_emit_prefetch_L2(cmd_buffer,
3083 cmd_buffer->state.pipeline);
3084 }
3085
3086 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3087 return;
3088
3089 radv_emit_all_graphics_states(cmd_buffer, info);
3090 radv_emit_draw_packets(cmd_buffer, info);
3091 }
3092
3093 assert(cmd_buffer->cs->cdw <= cdw_max);
3094 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3095 }
3096
3097 void radv_CmdDraw(
3098 VkCommandBuffer commandBuffer,
3099 uint32_t vertexCount,
3100 uint32_t instanceCount,
3101 uint32_t firstVertex,
3102 uint32_t firstInstance)
3103 {
3104 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3105 struct radv_draw_info info = {};
3106
3107 info.count = vertexCount;
3108 info.instance_count = instanceCount;
3109 info.first_instance = firstInstance;
3110 info.vertex_offset = firstVertex;
3111
3112 radv_draw(cmd_buffer, &info);
3113 }
3114
3115 void radv_CmdDrawIndexed(
3116 VkCommandBuffer commandBuffer,
3117 uint32_t indexCount,
3118 uint32_t instanceCount,
3119 uint32_t firstIndex,
3120 int32_t vertexOffset,
3121 uint32_t firstInstance)
3122 {
3123 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3124 struct radv_draw_info info = {};
3125
3126 info.indexed = true;
3127 info.count = indexCount;
3128 info.instance_count = instanceCount;
3129 info.first_index = firstIndex;
3130 info.vertex_offset = vertexOffset;
3131 info.first_instance = firstInstance;
3132
3133 radv_draw(cmd_buffer, &info);
3134 }
3135
3136 void radv_CmdDrawIndirect(
3137 VkCommandBuffer commandBuffer,
3138 VkBuffer _buffer,
3139 VkDeviceSize offset,
3140 uint32_t drawCount,
3141 uint32_t stride)
3142 {
3143 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3144 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3145 struct radv_draw_info info = {};
3146
3147 info.count = drawCount;
3148 info.indirect = buffer;
3149 info.indirect_offset = offset;
3150 info.stride = stride;
3151
3152 radv_draw(cmd_buffer, &info);
3153 }
3154
3155 void radv_CmdDrawIndexedIndirect(
3156 VkCommandBuffer commandBuffer,
3157 VkBuffer _buffer,
3158 VkDeviceSize offset,
3159 uint32_t drawCount,
3160 uint32_t stride)
3161 {
3162 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3163 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3164 struct radv_draw_info info = {};
3165
3166 info.indexed = true;
3167 info.count = drawCount;
3168 info.indirect = buffer;
3169 info.indirect_offset = offset;
3170 info.stride = stride;
3171
3172 radv_draw(cmd_buffer, &info);
3173 }
3174
3175 void radv_CmdDrawIndirectCountAMD(
3176 VkCommandBuffer commandBuffer,
3177 VkBuffer _buffer,
3178 VkDeviceSize offset,
3179 VkBuffer _countBuffer,
3180 VkDeviceSize countBufferOffset,
3181 uint32_t maxDrawCount,
3182 uint32_t stride)
3183 {
3184 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3185 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3186 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3187 struct radv_draw_info info = {};
3188
3189 info.count = maxDrawCount;
3190 info.indirect = buffer;
3191 info.indirect_offset = offset;
3192 info.count_buffer = count_buffer;
3193 info.count_buffer_offset = countBufferOffset;
3194 info.stride = stride;
3195
3196 radv_draw(cmd_buffer, &info);
3197 }
3198
3199 void radv_CmdDrawIndexedIndirectCountAMD(
3200 VkCommandBuffer commandBuffer,
3201 VkBuffer _buffer,
3202 VkDeviceSize offset,
3203 VkBuffer _countBuffer,
3204 VkDeviceSize countBufferOffset,
3205 uint32_t maxDrawCount,
3206 uint32_t stride)
3207 {
3208 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3209 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3210 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3211 struct radv_draw_info info = {};
3212
3213 info.indexed = true;
3214 info.count = maxDrawCount;
3215 info.indirect = buffer;
3216 info.indirect_offset = offset;
3217 info.count_buffer = count_buffer;
3218 info.count_buffer_offset = countBufferOffset;
3219 info.stride = stride;
3220
3221 radv_draw(cmd_buffer, &info);
3222 }
3223
3224 struct radv_dispatch_info {
3225 /**
3226 * Determine the layout of the grid (in block units) to be used.
3227 */
3228 uint32_t blocks[3];
3229
3230 /**
3231 * A starting offset for the grid. If unaligned is set, the offset
3232 * must still be aligned.
3233 */
3234 uint32_t offsets[3];
3235 /**
3236 * Whether it's an unaligned compute dispatch.
3237 */
3238 bool unaligned;
3239
3240 /**
3241 * Indirect compute parameters resource.
3242 */
3243 struct radv_buffer *indirect;
3244 uint64_t indirect_offset;
3245 };
3246
3247 static void
3248 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3249 const struct radv_dispatch_info *info)
3250 {
3251 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3252 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3253 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3254 struct radeon_winsys *ws = cmd_buffer->device->ws;
3255 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3256 struct radv_userdata_info *loc;
3257
3258 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3259 AC_UD_CS_GRID_SIZE);
3260
3261 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3262
3263 if (info->indirect) {
3264 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3265
3266 va += info->indirect->offset + info->indirect_offset;
3267
3268 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3269
3270 if (loc->sgpr_idx != -1) {
3271 for (unsigned i = 0; i < 3; ++i) {
3272 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3273 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3274 COPY_DATA_DST_SEL(COPY_DATA_REG));
3275 radeon_emit(cs, (va + 4 * i));
3276 radeon_emit(cs, (va + 4 * i) >> 32);
3277 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3278 + loc->sgpr_idx * 4) >> 2) + i);
3279 radeon_emit(cs, 0);
3280 }
3281 }
3282
3283 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3284 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3285 PKT3_SHADER_TYPE_S(1));
3286 radeon_emit(cs, va);
3287 radeon_emit(cs, va >> 32);
3288 radeon_emit(cs, dispatch_initiator);
3289 } else {
3290 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3291 PKT3_SHADER_TYPE_S(1));
3292 radeon_emit(cs, 1);
3293 radeon_emit(cs, va);
3294 radeon_emit(cs, va >> 32);
3295
3296 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3297 PKT3_SHADER_TYPE_S(1));
3298 radeon_emit(cs, 0);
3299 radeon_emit(cs, dispatch_initiator);
3300 }
3301 } else {
3302 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3303 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3304
3305 if (info->unaligned) {
3306 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3307 unsigned remainder[3];
3308
3309 /* If aligned, these should be an entire block size,
3310 * not 0.
3311 */
3312 remainder[0] = blocks[0] + cs_block_size[0] -
3313 align_u32_npot(blocks[0], cs_block_size[0]);
3314 remainder[1] = blocks[1] + cs_block_size[1] -
3315 align_u32_npot(blocks[1], cs_block_size[1]);
3316 remainder[2] = blocks[2] + cs_block_size[2] -
3317 align_u32_npot(blocks[2], cs_block_size[2]);
3318
3319 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3320 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3321 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3322
3323 for(unsigned i = 0; i < 3; ++i) {
3324 assert(offsets[i] % cs_block_size[i] == 0);
3325 offsets[i] /= cs_block_size[i];
3326 }
3327
3328 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3329 radeon_emit(cs,
3330 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3331 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3332 radeon_emit(cs,
3333 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3334 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3335 radeon_emit(cs,
3336 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3337 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3338
3339 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3340 }
3341
3342 if (loc->sgpr_idx != -1) {
3343 assert(!loc->indirect);
3344 assert(loc->num_sgprs == 3);
3345
3346 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3347 loc->sgpr_idx * 4, 3);
3348 radeon_emit(cs, blocks[0]);
3349 radeon_emit(cs, blocks[1]);
3350 radeon_emit(cs, blocks[2]);
3351 }
3352
3353 if (offsets[0] || offsets[1] || offsets[2]) {
3354 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3355 radeon_emit(cs, offsets[0]);
3356 radeon_emit(cs, offsets[1]);
3357 radeon_emit(cs, offsets[2]);
3358
3359 /* The blocks in the packet are not counts but end values. */
3360 for (unsigned i = 0; i < 3; ++i)
3361 blocks[i] += offsets[i];
3362 } else {
3363 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3364 }
3365
3366 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3367 PKT3_SHADER_TYPE_S(1));
3368 radeon_emit(cs, blocks[0]);
3369 radeon_emit(cs, blocks[1]);
3370 radeon_emit(cs, blocks[2]);
3371 radeon_emit(cs, dispatch_initiator);
3372 }
3373
3374 assert(cmd_buffer->cs->cdw <= cdw_max);
3375 }
3376
3377 static void
3378 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3379 {
3380 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3381 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3382 VK_SHADER_STAGE_COMPUTE_BIT);
3383 }
3384
3385 static void
3386 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3387 const struct radv_dispatch_info *info)
3388 {
3389 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3390 bool pipeline_is_dirty = pipeline &&
3391 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3392
3393 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3394 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3395 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3396 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3397 /* If we have to wait for idle, set all states first, so that
3398 * all SET packets are processed in parallel with previous draw
3399 * calls. Then upload descriptors, set shader pointers, and
3400 * dispatch, and prefetch at the end. This ensures that the
3401 * time the CUs are idle is very short. (there are only SET_SH
3402 * packets between the wait and the draw)
3403 */
3404 radv_emit_compute_pipeline(cmd_buffer);
3405 si_emit_cache_flush(cmd_buffer);
3406 /* <-- CUs are idle here --> */
3407
3408 radv_upload_compute_shader_descriptors(cmd_buffer);
3409
3410 radv_emit_dispatch_packets(cmd_buffer, info);
3411 /* <-- CUs are busy here --> */
3412
3413 /* Start prefetches after the dispatch has been started. Both
3414 * will run in parallel, but starting the dispatch first is
3415 * more important.
3416 */
3417 if (pipeline_is_dirty) {
3418 radv_emit_shader_prefetch(cmd_buffer,
3419 pipeline->shaders[MESA_SHADER_COMPUTE]);
3420 }
3421 } else {
3422 /* If we don't wait for idle, start prefetches first, then set
3423 * states, and dispatch at the end.
3424 */
3425 si_emit_cache_flush(cmd_buffer);
3426
3427 if (pipeline_is_dirty) {
3428 radv_emit_shader_prefetch(cmd_buffer,
3429 pipeline->shaders[MESA_SHADER_COMPUTE]);
3430 }
3431
3432 radv_upload_compute_shader_descriptors(cmd_buffer);
3433
3434 radv_emit_compute_pipeline(cmd_buffer);
3435 radv_emit_dispatch_packets(cmd_buffer, info);
3436 }
3437
3438 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3439 }
3440
3441 void radv_CmdDispatchBase(
3442 VkCommandBuffer commandBuffer,
3443 uint32_t base_x,
3444 uint32_t base_y,
3445 uint32_t base_z,
3446 uint32_t x,
3447 uint32_t y,
3448 uint32_t z)
3449 {
3450 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3451 struct radv_dispatch_info info = {};
3452
3453 info.blocks[0] = x;
3454 info.blocks[1] = y;
3455 info.blocks[2] = z;
3456
3457 info.offsets[0] = base_x;
3458 info.offsets[1] = base_y;
3459 info.offsets[2] = base_z;
3460 radv_dispatch(cmd_buffer, &info);
3461 }
3462
3463 void radv_CmdDispatch(
3464 VkCommandBuffer commandBuffer,
3465 uint32_t x,
3466 uint32_t y,
3467 uint32_t z)
3468 {
3469 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3470 }
3471
3472 void radv_CmdDispatchIndirect(
3473 VkCommandBuffer commandBuffer,
3474 VkBuffer _buffer,
3475 VkDeviceSize offset)
3476 {
3477 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3478 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3479 struct radv_dispatch_info info = {};
3480
3481 info.indirect = buffer;
3482 info.indirect_offset = offset;
3483
3484 radv_dispatch(cmd_buffer, &info);
3485 }
3486
3487 void radv_unaligned_dispatch(
3488 struct radv_cmd_buffer *cmd_buffer,
3489 uint32_t x,
3490 uint32_t y,
3491 uint32_t z)
3492 {
3493 struct radv_dispatch_info info = {};
3494
3495 info.blocks[0] = x;
3496 info.blocks[1] = y;
3497 info.blocks[2] = z;
3498 info.unaligned = 1;
3499
3500 radv_dispatch(cmd_buffer, &info);
3501 }
3502
3503 void radv_CmdEndRenderPass(
3504 VkCommandBuffer commandBuffer)
3505 {
3506 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3507
3508 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3509
3510 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3511
3512 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3513 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3514 radv_handle_subpass_image_transition(cmd_buffer,
3515 (VkAttachmentReference){i, layout});
3516 }
3517
3518 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3519
3520 cmd_buffer->state.pass = NULL;
3521 cmd_buffer->state.subpass = NULL;
3522 cmd_buffer->state.attachments = NULL;
3523 cmd_buffer->state.framebuffer = NULL;
3524 }
3525
3526 /*
3527 * For HTILE we have the following interesting clear words:
3528 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3529 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3530 * 0xfffffff0: Clear depth to 1.0
3531 * 0x00000000: Clear depth to 0.0
3532 */
3533 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3534 struct radv_image *image,
3535 const VkImageSubresourceRange *range,
3536 uint32_t clear_word)
3537 {
3538 assert(range->baseMipLevel == 0);
3539 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3540 unsigned layer_count = radv_get_layerCount(image, range);
3541 uint64_t size = image->surface.htile_slice_size * layer_count;
3542 uint64_t offset = image->offset + image->htile_offset +
3543 image->surface.htile_slice_size * range->baseArrayLayer;
3544 struct radv_cmd_state *state = &cmd_buffer->state;
3545
3546 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3547 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3548
3549 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3550 size, clear_word);
3551
3552 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3553 }
3554
3555 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3556 struct radv_image *image,
3557 VkImageLayout src_layout,
3558 VkImageLayout dst_layout,
3559 unsigned src_queue_mask,
3560 unsigned dst_queue_mask,
3561 const VkImageSubresourceRange *range,
3562 VkImageAspectFlags pending_clears)
3563 {
3564 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3565 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3566 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3567 cmd_buffer->state.render_area.extent.width == image->info.width &&
3568 cmd_buffer->state.render_area.extent.height == image->info.height) {
3569 /* The clear will initialize htile. */
3570 return;
3571 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3572 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3573 /* TODO: merge with the clear if applicable */
3574 radv_initialize_htile(cmd_buffer, image, range, 0);
3575 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3576 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3577 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3578 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3579 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3580 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3581 VkImageSubresourceRange local_range = *range;
3582 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3583 local_range.baseMipLevel = 0;
3584 local_range.levelCount = 1;
3585
3586 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3587 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3588
3589 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3590
3591 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3592 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3593 }
3594 }
3595
3596 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3597 struct radv_image *image, uint32_t value)
3598 {
3599 struct radv_cmd_state *state = &cmd_buffer->state;
3600
3601 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3602 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3603
3604 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3605 image->offset + image->cmask.offset,
3606 image->cmask.size, value);
3607
3608 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3609 }
3610
3611 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3612 struct radv_image *image,
3613 VkImageLayout src_layout,
3614 VkImageLayout dst_layout,
3615 unsigned src_queue_mask,
3616 unsigned dst_queue_mask,
3617 const VkImageSubresourceRange *range)
3618 {
3619 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3620 if (image->fmask.size)
3621 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3622 else
3623 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3624 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3625 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3626 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3627 }
3628 }
3629
3630 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3631 struct radv_image *image, uint32_t value)
3632 {
3633 struct radv_cmd_state *state = &cmd_buffer->state;
3634
3635 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3636 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3637
3638 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3639 image->offset + image->dcc_offset,
3640 image->surface.dcc_size, value);
3641
3642 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3643 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3644 }
3645
3646 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3647 struct radv_image *image,
3648 VkImageLayout src_layout,
3649 VkImageLayout dst_layout,
3650 unsigned src_queue_mask,
3651 unsigned dst_queue_mask,
3652 const VkImageSubresourceRange *range)
3653 {
3654 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
3655 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
3656 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3657 radv_initialize_dcc(cmd_buffer, image,
3658 radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ?
3659 0x20202020u : 0xffffffffu);
3660 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3661 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3662 radv_decompress_dcc(cmd_buffer, image, range);
3663 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3664 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3665 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3666 }
3667 }
3668
3669 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3670 struct radv_image *image,
3671 VkImageLayout src_layout,
3672 VkImageLayout dst_layout,
3673 uint32_t src_family,
3674 uint32_t dst_family,
3675 const VkImageSubresourceRange *range,
3676 VkImageAspectFlags pending_clears)
3677 {
3678 if (image->exclusive && src_family != dst_family) {
3679 /* This is an acquire or a release operation and there will be
3680 * a corresponding release/acquire. Do the transition in the
3681 * most flexible queue. */
3682
3683 assert(src_family == cmd_buffer->queue_family_index ||
3684 dst_family == cmd_buffer->queue_family_index);
3685
3686 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3687 return;
3688
3689 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3690 (src_family == RADV_QUEUE_GENERAL ||
3691 dst_family == RADV_QUEUE_GENERAL))
3692 return;
3693 }
3694
3695 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3696 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3697
3698 if (image->surface.htile_size)
3699 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3700 dst_layout, src_queue_mask,
3701 dst_queue_mask, range,
3702 pending_clears);
3703
3704 if (image->cmask.size || image->fmask.size)
3705 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3706 dst_layout, src_queue_mask,
3707 dst_queue_mask, range);
3708
3709 if (image->surface.dcc_size)
3710 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3711 dst_layout, src_queue_mask,
3712 dst_queue_mask, range);
3713 }
3714
3715 void radv_CmdPipelineBarrier(
3716 VkCommandBuffer commandBuffer,
3717 VkPipelineStageFlags srcStageMask,
3718 VkPipelineStageFlags destStageMask,
3719 VkBool32 byRegion,
3720 uint32_t memoryBarrierCount,
3721 const VkMemoryBarrier* pMemoryBarriers,
3722 uint32_t bufferMemoryBarrierCount,
3723 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3724 uint32_t imageMemoryBarrierCount,
3725 const VkImageMemoryBarrier* pImageMemoryBarriers)
3726 {
3727 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3728 enum radv_cmd_flush_bits src_flush_bits = 0;
3729 enum radv_cmd_flush_bits dst_flush_bits = 0;
3730
3731 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3732 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3733 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3734 NULL);
3735 }
3736
3737 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3738 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3739 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3740 NULL);
3741 }
3742
3743 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3744 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3745 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3746 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3747 image);
3748 }
3749
3750 radv_stage_flush(cmd_buffer, srcStageMask);
3751 cmd_buffer->state.flush_bits |= src_flush_bits;
3752
3753 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3754 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3755 radv_handle_image_transition(cmd_buffer, image,
3756 pImageMemoryBarriers[i].oldLayout,
3757 pImageMemoryBarriers[i].newLayout,
3758 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3759 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3760 &pImageMemoryBarriers[i].subresourceRange,
3761 0);
3762 }
3763
3764 cmd_buffer->state.flush_bits |= dst_flush_bits;
3765 }
3766
3767
3768 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3769 struct radv_event *event,
3770 VkPipelineStageFlags stageMask,
3771 unsigned value)
3772 {
3773 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3774 uint64_t va = radv_buffer_get_va(event->bo);
3775
3776 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3777
3778 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3779
3780 /* TODO: this is overkill. Probably should figure something out from
3781 * the stage mask. */
3782
3783 si_cs_emit_write_event_eop(cs,
3784 cmd_buffer->state.predicating,
3785 cmd_buffer->device->physical_device->rad_info.chip_class,
3786 radv_cmd_buffer_uses_mec(cmd_buffer),
3787 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3788 1, va, 2, value);
3789
3790 assert(cmd_buffer->cs->cdw <= cdw_max);
3791 }
3792
3793 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3794 VkEvent _event,
3795 VkPipelineStageFlags stageMask)
3796 {
3797 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3798 RADV_FROM_HANDLE(radv_event, event, _event);
3799
3800 write_event(cmd_buffer, event, stageMask, 1);
3801 }
3802
3803 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3804 VkEvent _event,
3805 VkPipelineStageFlags stageMask)
3806 {
3807 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3808 RADV_FROM_HANDLE(radv_event, event, _event);
3809
3810 write_event(cmd_buffer, event, stageMask, 0);
3811 }
3812
3813 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3814 uint32_t eventCount,
3815 const VkEvent* pEvents,
3816 VkPipelineStageFlags srcStageMask,
3817 VkPipelineStageFlags dstStageMask,
3818 uint32_t memoryBarrierCount,
3819 const VkMemoryBarrier* pMemoryBarriers,
3820 uint32_t bufferMemoryBarrierCount,
3821 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3822 uint32_t imageMemoryBarrierCount,
3823 const VkImageMemoryBarrier* pImageMemoryBarriers)
3824 {
3825 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3826 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3827
3828 for (unsigned i = 0; i < eventCount; ++i) {
3829 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3830 uint64_t va = radv_buffer_get_va(event->bo);
3831
3832 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3833
3834 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3835
3836 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3837 assert(cmd_buffer->cs->cdw <= cdw_max);
3838 }
3839
3840
3841 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3842 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3843
3844 radv_handle_image_transition(cmd_buffer, image,
3845 pImageMemoryBarriers[i].oldLayout,
3846 pImageMemoryBarriers[i].newLayout,
3847 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3848 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3849 &pImageMemoryBarriers[i].subresourceRange,
3850 0);
3851 }
3852
3853 /* TODO: figure out how to do memory barriers without waiting */
3854 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3855 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3856 RADV_CMD_FLAG_INV_VMEM_L1 |
3857 RADV_CMD_FLAG_INV_SMEM_L1;
3858 }
3859
3860
3861 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
3862 uint32_t deviceMask)
3863 {
3864 /* No-op */
3865 }