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radv: Do not change scratch settings while shaders are active.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 bool src_render_loop,
58 VkImageLayout dst_layout,
59 bool dst_render_loop,
60 uint32_t src_family,
61 uint32_t dst_family,
62 const VkImageSubresourceRange *range,
63 struct radv_sample_locations_state *sample_locs);
64
65 const struct radv_dynamic_state default_dynamic_state = {
66 .viewport = {
67 .count = 0,
68 },
69 .scissor = {
70 .count = 0,
71 },
72 .line_width = 1.0f,
73 .depth_bias = {
74 .bias = 0.0f,
75 .clamp = 0.0f,
76 .slope = 0.0f,
77 },
78 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
79 .depth_bounds = {
80 .min = 0.0f,
81 .max = 1.0f,
82 },
83 .stencil_compare_mask = {
84 .front = ~0u,
85 .back = ~0u,
86 },
87 .stencil_write_mask = {
88 .front = ~0u,
89 .back = ~0u,
90 },
91 .stencil_reference = {
92 .front = 0u,
93 .back = 0u,
94 },
95 };
96
97 static void
98 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
99 const struct radv_dynamic_state *src)
100 {
101 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
102 uint32_t copy_mask = src->mask;
103 uint32_t dest_mask = 0;
104
105 /* Make sure to copy the number of viewports/scissors because they can
106 * only be specified at pipeline creation time.
107 */
108 dest->viewport.count = src->viewport.count;
109 dest->scissor.count = src->scissor.count;
110 dest->discard_rectangle.count = src->discard_rectangle.count;
111 dest->sample_location.count = src->sample_location.count;
112
113 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
114 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
115 src->viewport.count * sizeof(VkViewport))) {
116 typed_memcpy(dest->viewport.viewports,
117 src->viewport.viewports,
118 src->viewport.count);
119 dest_mask |= RADV_DYNAMIC_VIEWPORT;
120 }
121 }
122
123 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
124 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
125 src->scissor.count * sizeof(VkRect2D))) {
126 typed_memcpy(dest->scissor.scissors,
127 src->scissor.scissors, src->scissor.count);
128 dest_mask |= RADV_DYNAMIC_SCISSOR;
129 }
130 }
131
132 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
133 if (dest->line_width != src->line_width) {
134 dest->line_width = src->line_width;
135 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
136 }
137 }
138
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
140 if (memcmp(&dest->depth_bias, &src->depth_bias,
141 sizeof(src->depth_bias))) {
142 dest->depth_bias = src->depth_bias;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
144 }
145 }
146
147 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
148 if (memcmp(&dest->blend_constants, &src->blend_constants,
149 sizeof(src->blend_constants))) {
150 typed_memcpy(dest->blend_constants,
151 src->blend_constants, 4);
152 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
153 }
154 }
155
156 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
157 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
158 sizeof(src->depth_bounds))) {
159 dest->depth_bounds = src->depth_bounds;
160 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
161 }
162 }
163
164 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
165 if (memcmp(&dest->stencil_compare_mask,
166 &src->stencil_compare_mask,
167 sizeof(src->stencil_compare_mask))) {
168 dest->stencil_compare_mask = src->stencil_compare_mask;
169 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
170 }
171 }
172
173 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
174 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
175 sizeof(src->stencil_write_mask))) {
176 dest->stencil_write_mask = src->stencil_write_mask;
177 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
178 }
179 }
180
181 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
182 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
183 sizeof(src->stencil_reference))) {
184 dest->stencil_reference = src->stencil_reference;
185 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
186 }
187 }
188
189 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
190 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
191 src->discard_rectangle.count * sizeof(VkRect2D))) {
192 typed_memcpy(dest->discard_rectangle.rectangles,
193 src->discard_rectangle.rectangles,
194 src->discard_rectangle.count);
195 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
196 }
197 }
198
199 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
200 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
201 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
202 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
203 memcmp(&dest->sample_location.locations,
204 &src->sample_location.locations,
205 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
206 dest->sample_location.per_pixel = src->sample_location.per_pixel;
207 dest->sample_location.grid_size = src->sample_location.grid_size;
208 typed_memcpy(dest->sample_location.locations,
209 src->sample_location.locations,
210 src->sample_location.count);
211 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
212 }
213 }
214
215 cmd_buffer->state.dirty |= dest_mask;
216 }
217
218 static void
219 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
220 struct radv_pipeline *pipeline)
221 {
222 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
223 struct radv_shader_info *info;
224
225 if (!pipeline->streamout_shader ||
226 cmd_buffer->device->physical_device->use_ngg_streamout)
227 return;
228
229 info = &pipeline->streamout_shader->info;
230 for (int i = 0; i < MAX_SO_BUFFERS; i++)
231 so->stride_in_dw[i] = info->so.strides[i];
232
233 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
234 }
235
236 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
237 {
238 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
239 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
240 }
241
242 enum ring_type radv_queue_family_to_ring(int f) {
243 switch (f) {
244 case RADV_QUEUE_GENERAL:
245 return RING_GFX;
246 case RADV_QUEUE_COMPUTE:
247 return RING_COMPUTE;
248 case RADV_QUEUE_TRANSFER:
249 return RING_DMA;
250 default:
251 unreachable("Unknown queue family");
252 }
253 }
254
255 static VkResult radv_create_cmd_buffer(
256 struct radv_device * device,
257 struct radv_cmd_pool * pool,
258 VkCommandBufferLevel level,
259 VkCommandBuffer* pCommandBuffer)
260 {
261 struct radv_cmd_buffer *cmd_buffer;
262 unsigned ring;
263 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
265 if (cmd_buffer == NULL)
266 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
267
268 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
269 cmd_buffer->device = device;
270 cmd_buffer->pool = pool;
271 cmd_buffer->level = level;
272
273 if (pool) {
274 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
275 cmd_buffer->queue_family_index = pool->queue_family_index;
276
277 } else {
278 /* Init the pool_link so we can safely call list_del when we destroy
279 * the command buffer
280 */
281 list_inithead(&cmd_buffer->pool_link);
282 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
283 }
284
285 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
286
287 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
288 if (!cmd_buffer->cs) {
289 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
290 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
291 }
292
293 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
294
295 list_inithead(&cmd_buffer->upload.list);
296
297 return VK_SUCCESS;
298 }
299
300 static void
301 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
302 {
303 list_del(&cmd_buffer->pool_link);
304
305 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
306 &cmd_buffer->upload.list, list) {
307 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
308 list_del(&up->list);
309 free(up);
310 }
311
312 if (cmd_buffer->upload.upload_bo)
313 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
314 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
315
316 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
317 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
318
319 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
320 }
321
322 static VkResult
323 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
324 {
325 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
326
327 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
328 &cmd_buffer->upload.list, list) {
329 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
330 list_del(&up->list);
331 free(up);
332 }
333
334 cmd_buffer->push_constant_stages = 0;
335 cmd_buffer->scratch_size_per_wave_needed = 0;
336 cmd_buffer->scratch_waves_wanted = 0;
337 cmd_buffer->compute_scratch_size_per_wave_needed = 0;
338 cmd_buffer->compute_scratch_waves_wanted = 0;
339 cmd_buffer->esgs_ring_size_needed = 0;
340 cmd_buffer->gsvs_ring_size_needed = 0;
341 cmd_buffer->tess_rings_needed = false;
342 cmd_buffer->gds_needed = false;
343 cmd_buffer->sample_positions_needed = false;
344
345 if (cmd_buffer->upload.upload_bo)
346 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
347 cmd_buffer->upload.upload_bo);
348 cmd_buffer->upload.offset = 0;
349
350 cmd_buffer->record_result = VK_SUCCESS;
351
352 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
353
354 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
355 cmd_buffer->descriptors[i].dirty = 0;
356 cmd_buffer->descriptors[i].valid = 0;
357 cmd_buffer->descriptors[i].push_dirty = false;
358 }
359
360 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
361 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
362 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
363 unsigned fence_offset, eop_bug_offset;
364 void *fence_ptr;
365
366 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
367 &fence_ptr);
368
369 cmd_buffer->gfx9_fence_va =
370 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
371 cmd_buffer->gfx9_fence_va += fence_offset;
372
373 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
374 /* Allocate a buffer for the EOP bug on GFX9. */
375 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
376 &eop_bug_offset, &fence_ptr);
377 cmd_buffer->gfx9_eop_bug_va =
378 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
379 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
380 }
381 }
382
383 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
384
385 return cmd_buffer->record_result;
386 }
387
388 static bool
389 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
390 uint64_t min_needed)
391 {
392 uint64_t new_size;
393 struct radeon_winsys_bo *bo;
394 struct radv_cmd_buffer_upload *upload;
395 struct radv_device *device = cmd_buffer->device;
396
397 new_size = MAX2(min_needed, 16 * 1024);
398 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
399
400 bo = device->ws->buffer_create(device->ws,
401 new_size, 4096,
402 RADEON_DOMAIN_GTT,
403 RADEON_FLAG_CPU_ACCESS|
404 RADEON_FLAG_NO_INTERPROCESS_SHARING |
405 RADEON_FLAG_32BIT,
406 RADV_BO_PRIORITY_UPLOAD_BUFFER);
407
408 if (!bo) {
409 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
410 return false;
411 }
412
413 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
414 if (cmd_buffer->upload.upload_bo) {
415 upload = malloc(sizeof(*upload));
416
417 if (!upload) {
418 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
419 device->ws->buffer_destroy(bo);
420 return false;
421 }
422
423 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
424 list_add(&upload->list, &cmd_buffer->upload.list);
425 }
426
427 cmd_buffer->upload.upload_bo = bo;
428 cmd_buffer->upload.size = new_size;
429 cmd_buffer->upload.offset = 0;
430 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
431
432 if (!cmd_buffer->upload.map) {
433 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
434 return false;
435 }
436
437 return true;
438 }
439
440 bool
441 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
442 unsigned size,
443 unsigned alignment,
444 unsigned *out_offset,
445 void **ptr)
446 {
447 assert(util_is_power_of_two_nonzero(alignment));
448
449 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
450 if (offset + size > cmd_buffer->upload.size) {
451 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
452 return false;
453 offset = 0;
454 }
455
456 *out_offset = offset;
457 *ptr = cmd_buffer->upload.map + offset;
458
459 cmd_buffer->upload.offset = offset + size;
460 return true;
461 }
462
463 bool
464 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
465 unsigned size, unsigned alignment,
466 const void *data, unsigned *out_offset)
467 {
468 uint8_t *ptr;
469
470 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
471 out_offset, (void **)&ptr))
472 return false;
473
474 if (ptr)
475 memcpy(ptr, data, size);
476
477 return true;
478 }
479
480 static void
481 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
482 unsigned count, const uint32_t *data)
483 {
484 struct radeon_cmdbuf *cs = cmd_buffer->cs;
485
486 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
487
488 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
489 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
490 S_370_WR_CONFIRM(1) |
491 S_370_ENGINE_SEL(V_370_ME));
492 radeon_emit(cs, va);
493 radeon_emit(cs, va >> 32);
494 radeon_emit_array(cs, data, count);
495 }
496
497 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
498 {
499 struct radv_device *device = cmd_buffer->device;
500 struct radeon_cmdbuf *cs = cmd_buffer->cs;
501 uint64_t va;
502
503 va = radv_buffer_get_va(device->trace_bo);
504 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
505 va += 4;
506
507 ++cmd_buffer->state.trace_id;
508 radv_emit_write_data_packet(cmd_buffer, va, 1,
509 &cmd_buffer->state.trace_id);
510
511 radeon_check_space(cmd_buffer->device->ws, cs, 2);
512
513 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
514 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
515 }
516
517 static void
518 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
519 enum radv_cmd_flush_bits flags)
520 {
521 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
522 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
523 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
524
525 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
526
527 /* Force wait for graphics or compute engines to be idle. */
528 si_cs_emit_cache_flush(cmd_buffer->cs,
529 cmd_buffer->device->physical_device->rad_info.chip_class,
530 &cmd_buffer->gfx9_fence_idx,
531 cmd_buffer->gfx9_fence_va,
532 radv_cmd_buffer_uses_mec(cmd_buffer),
533 flags, cmd_buffer->gfx9_eop_bug_va);
534 }
535
536 if (unlikely(cmd_buffer->device->trace_bo))
537 radv_cmd_buffer_trace_emit(cmd_buffer);
538 }
539
540 static void
541 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
542 struct radv_pipeline *pipeline, enum ring_type ring)
543 {
544 struct radv_device *device = cmd_buffer->device;
545 uint32_t data[2];
546 uint64_t va;
547
548 va = radv_buffer_get_va(device->trace_bo);
549
550 switch (ring) {
551 case RING_GFX:
552 va += 8;
553 break;
554 case RING_COMPUTE:
555 va += 16;
556 break;
557 default:
558 assert(!"invalid ring type");
559 }
560
561 uint64_t pipeline_address = (uintptr_t)pipeline;
562 data[0] = pipeline_address;
563 data[1] = pipeline_address >> 32;
564
565 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
566 }
567
568 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
569 VkPipelineBindPoint bind_point,
570 struct radv_descriptor_set *set,
571 unsigned idx)
572 {
573 struct radv_descriptor_state *descriptors_state =
574 radv_get_descriptors_state(cmd_buffer, bind_point);
575
576 descriptors_state->sets[idx] = set;
577
578 descriptors_state->valid |= (1u << idx); /* active descriptors */
579 descriptors_state->dirty |= (1u << idx);
580 }
581
582 static void
583 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
584 VkPipelineBindPoint bind_point)
585 {
586 struct radv_descriptor_state *descriptors_state =
587 radv_get_descriptors_state(cmd_buffer, bind_point);
588 struct radv_device *device = cmd_buffer->device;
589 uint32_t data[MAX_SETS * 2] = {};
590 uint64_t va;
591 unsigned i;
592 va = radv_buffer_get_va(device->trace_bo) + 24;
593
594 for_each_bit(i, descriptors_state->valid) {
595 struct radv_descriptor_set *set = descriptors_state->sets[i];
596 data[i * 2] = (uint64_t)(uintptr_t)set;
597 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
598 }
599
600 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
601 }
602
603 struct radv_userdata_info *
604 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
605 gl_shader_stage stage,
606 int idx)
607 {
608 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
609 return &shader->info.user_sgprs_locs.shader_data[idx];
610 }
611
612 static void
613 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
614 struct radv_pipeline *pipeline,
615 gl_shader_stage stage,
616 int idx, uint64_t va)
617 {
618 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
619 uint32_t base_reg = pipeline->user_data_0[stage];
620 if (loc->sgpr_idx == -1)
621 return;
622
623 assert(loc->num_sgprs == 1);
624
625 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
626 base_reg + loc->sgpr_idx * 4, va, false);
627 }
628
629 static void
630 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
631 struct radv_pipeline *pipeline,
632 struct radv_descriptor_state *descriptors_state,
633 gl_shader_stage stage)
634 {
635 struct radv_device *device = cmd_buffer->device;
636 struct radeon_cmdbuf *cs = cmd_buffer->cs;
637 uint32_t sh_base = pipeline->user_data_0[stage];
638 struct radv_userdata_locations *locs =
639 &pipeline->shaders[stage]->info.user_sgprs_locs;
640 unsigned mask = locs->descriptor_sets_enabled;
641
642 mask &= descriptors_state->dirty & descriptors_state->valid;
643
644 while (mask) {
645 int start, count;
646
647 u_bit_scan_consecutive_range(&mask, &start, &count);
648
649 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
650 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
651
652 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
653 for (int i = 0; i < count; i++) {
654 struct radv_descriptor_set *set =
655 descriptors_state->sets[start + i];
656
657 radv_emit_shader_pointer_body(device, cs, set->va, true);
658 }
659 }
660 }
661
662 /**
663 * Convert the user sample locations to hardware sample locations (the values
664 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
665 */
666 static void
667 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
668 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
669 {
670 uint32_t x_offset = x % state->grid_size.width;
671 uint32_t y_offset = y % state->grid_size.height;
672 uint32_t num_samples = (uint32_t)state->per_pixel;
673 VkSampleLocationEXT *user_locs;
674 uint32_t pixel_offset;
675
676 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
677
678 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
679 user_locs = &state->locations[pixel_offset];
680
681 for (uint32_t i = 0; i < num_samples; i++) {
682 float shifted_pos_x = user_locs[i].x - 0.5;
683 float shifted_pos_y = user_locs[i].y - 0.5;
684
685 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
686 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
687
688 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
689 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
690 }
691 }
692
693 /**
694 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
695 * locations.
696 */
697 static void
698 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
699 uint32_t *sample_locs_pixel)
700 {
701 for (uint32_t i = 0; i < num_samples; i++) {
702 uint32_t sample_reg_idx = i / 4;
703 uint32_t sample_loc_idx = i % 4;
704 int32_t pos_x = sample_locs[i].x;
705 int32_t pos_y = sample_locs[i].y;
706
707 uint32_t shift_x = 8 * sample_loc_idx;
708 uint32_t shift_y = shift_x + 4;
709
710 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
711 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
712 }
713 }
714
715 /**
716 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
717 * sample locations.
718 */
719 static uint64_t
720 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
721 VkOffset2D *sample_locs,
722 uint32_t num_samples)
723 {
724 uint32_t centroid_priorities[num_samples];
725 uint32_t sample_mask = num_samples - 1;
726 uint32_t distances[num_samples];
727 uint64_t centroid_priority = 0;
728
729 /* Compute the distances from center for each sample. */
730 for (int i = 0; i < num_samples; i++) {
731 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
732 (sample_locs[i].y * sample_locs[i].y);
733 }
734
735 /* Compute the centroid priorities by looking at the distances array. */
736 for (int i = 0; i < num_samples; i++) {
737 uint32_t min_idx = 0;
738
739 for (int j = 1; j < num_samples; j++) {
740 if (distances[j] < distances[min_idx])
741 min_idx = j;
742 }
743
744 centroid_priorities[i] = min_idx;
745 distances[min_idx] = 0xffffffff;
746 }
747
748 /* Compute the final centroid priority. */
749 for (int i = 0; i < 8; i++) {
750 centroid_priority |=
751 centroid_priorities[i & sample_mask] << (i * 4);
752 }
753
754 return centroid_priority << 32 | centroid_priority;
755 }
756
757 /**
758 * Emit the sample locations that are specified with VK_EXT_sample_locations.
759 */
760 static void
761 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
762 {
763 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
764 struct radv_multisample_state *ms = &pipeline->graphics.ms;
765 struct radv_sample_locations_state *sample_location =
766 &cmd_buffer->state.dynamic.sample_location;
767 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
768 struct radeon_cmdbuf *cs = cmd_buffer->cs;
769 uint32_t sample_locs_pixel[4][2] = {};
770 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
771 uint32_t max_sample_dist = 0;
772 uint64_t centroid_priority;
773
774 if (!cmd_buffer->state.dynamic.sample_location.count)
775 return;
776
777 /* Convert the user sample locations to hardware sample locations. */
778 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
779 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
780 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
781 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
782
783 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
784 for (uint32_t i = 0; i < 4; i++) {
785 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
786 sample_locs_pixel[i]);
787 }
788
789 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
790 centroid_priority =
791 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
792 num_samples);
793
794 /* Compute the maximum sample distance from the specified locations. */
795 for (uint32_t i = 0; i < num_samples; i++) {
796 VkOffset2D offset = sample_locs[0][i];
797 max_sample_dist = MAX2(max_sample_dist,
798 MAX2(abs(offset.x), abs(offset.y)));
799 }
800
801 /* Emit the specified user sample locations. */
802 switch (num_samples) {
803 case 2:
804 case 4:
805 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
806 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
807 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
808 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
809 break;
810 case 8:
811 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
812 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
813 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
814 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
815 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
816 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
817 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
818 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
819 break;
820 default:
821 unreachable("invalid number of samples");
822 }
823
824 /* Emit the maximum sample distance and the centroid priority. */
825 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
826
827 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
828 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
829
830 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
831 radeon_emit(cs, pa_sc_aa_config);
832
833 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
834 radeon_emit(cs, centroid_priority);
835 radeon_emit(cs, centroid_priority >> 32);
836
837 /* GFX9: Flush DFSM when the AA mode changes. */
838 if (cmd_buffer->device->dfsm_allowed) {
839 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
840 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
841 }
842
843 cmd_buffer->state.context_roll_without_scissor_emitted = true;
844 }
845
846 static void
847 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
848 struct radv_pipeline *pipeline,
849 gl_shader_stage stage,
850 int idx, int count, uint32_t *values)
851 {
852 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
853 uint32_t base_reg = pipeline->user_data_0[stage];
854 if (loc->sgpr_idx == -1)
855 return;
856
857 assert(loc->num_sgprs == count);
858
859 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
860 radeon_emit_array(cmd_buffer->cs, values, count);
861 }
862
863 static void
864 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
865 struct radv_pipeline *pipeline)
866 {
867 int num_samples = pipeline->graphics.ms.num_samples;
868 struct radv_multisample_state *ms = &pipeline->graphics.ms;
869 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
870
871 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
872 cmd_buffer->sample_positions_needed = true;
873
874 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
875 return;
876
877 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
878 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
879 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
880
881 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
882
883 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
884
885 /* GFX9: Flush DFSM when the AA mode changes. */
886 if (cmd_buffer->device->dfsm_allowed) {
887 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
888 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
889 }
890
891 cmd_buffer->state.context_roll_without_scissor_emitted = true;
892 }
893
894 static void
895 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer,
896 struct radv_pipeline *pipeline)
897 {
898 const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
899
900
901 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
902 return;
903
904 if (old_pipeline &&
905 old_pipeline->graphics.binning.pa_sc_binner_cntl_0 == pipeline->graphics.binning.pa_sc_binner_cntl_0 &&
906 old_pipeline->graphics.binning.db_dfsm_control == pipeline->graphics.binning.db_dfsm_control)
907 return;
908
909 bool binning_flush = false;
910 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||
911 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||
912 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||
913 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
914 binning_flush = !old_pipeline ||
915 G_028C44_BINNING_MODE(old_pipeline->graphics.binning.pa_sc_binner_cntl_0) !=
916 G_028C44_BINNING_MODE(pipeline->graphics.binning.pa_sc_binner_cntl_0);
917 }
918
919 radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,
920 pipeline->graphics.binning.pa_sc_binner_cntl_0 |
921 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush));
922
923 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
924 radeon_set_context_reg(cmd_buffer->cs, R_028038_DB_DFSM_CONTROL,
925 pipeline->graphics.binning.db_dfsm_control);
926 } else {
927 radeon_set_context_reg(cmd_buffer->cs, R_028060_DB_DFSM_CONTROL,
928 pipeline->graphics.binning.db_dfsm_control);
929 }
930
931 cmd_buffer->state.context_roll_without_scissor_emitted = true;
932 }
933
934
935 static void
936 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
937 struct radv_shader_variant *shader)
938 {
939 uint64_t va;
940
941 if (!shader)
942 return;
943
944 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
945
946 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
947 }
948
949 static void
950 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
951 struct radv_pipeline *pipeline,
952 bool vertex_stage_only)
953 {
954 struct radv_cmd_state *state = &cmd_buffer->state;
955 uint32_t mask = state->prefetch_L2_mask;
956
957 if (vertex_stage_only) {
958 /* Fast prefetch path for starting draws as soon as possible.
959 */
960 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
961 RADV_PREFETCH_VBO_DESCRIPTORS);
962 }
963
964 if (mask & RADV_PREFETCH_VS)
965 radv_emit_shader_prefetch(cmd_buffer,
966 pipeline->shaders[MESA_SHADER_VERTEX]);
967
968 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
969 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
970
971 if (mask & RADV_PREFETCH_TCS)
972 radv_emit_shader_prefetch(cmd_buffer,
973 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
974
975 if (mask & RADV_PREFETCH_TES)
976 radv_emit_shader_prefetch(cmd_buffer,
977 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
978
979 if (mask & RADV_PREFETCH_GS) {
980 radv_emit_shader_prefetch(cmd_buffer,
981 pipeline->shaders[MESA_SHADER_GEOMETRY]);
982 if (radv_pipeline_has_gs_copy_shader(pipeline))
983 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
984 }
985
986 if (mask & RADV_PREFETCH_PS)
987 radv_emit_shader_prefetch(cmd_buffer,
988 pipeline->shaders[MESA_SHADER_FRAGMENT]);
989
990 state->prefetch_L2_mask &= ~mask;
991 }
992
993 static void
994 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
995 {
996 if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
997 return;
998
999 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1000 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1001
1002 unsigned sx_ps_downconvert = 0;
1003 unsigned sx_blend_opt_epsilon = 0;
1004 unsigned sx_blend_opt_control = 0;
1005
1006 if (!cmd_buffer->state.attachments || !subpass)
1007 return;
1008
1009 for (unsigned i = 0; i < subpass->color_count; ++i) {
1010 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1011 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1012 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1013 continue;
1014 }
1015
1016 int idx = subpass->color_attachments[i].attachment;
1017 struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
1018
1019 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
1020 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
1021 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
1022 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1023
1024 bool has_alpha, has_rgb;
1025
1026 /* Set if RGB and A are present. */
1027 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
1028
1029 if (format == V_028C70_COLOR_8 ||
1030 format == V_028C70_COLOR_16 ||
1031 format == V_028C70_COLOR_32)
1032 has_rgb = !has_alpha;
1033 else
1034 has_rgb = true;
1035
1036 /* Check the colormask and export format. */
1037 if (!(colormask & 0x7))
1038 has_rgb = false;
1039 if (!(colormask & 0x8))
1040 has_alpha = false;
1041
1042 if (spi_format == V_028714_SPI_SHADER_ZERO) {
1043 has_rgb = false;
1044 has_alpha = false;
1045 }
1046
1047 /* Disable value checking for disabled channels. */
1048 if (!has_rgb)
1049 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1050 if (!has_alpha)
1051 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1052
1053 /* Enable down-conversion for 32bpp and smaller formats. */
1054 switch (format) {
1055 case V_028C70_COLOR_8:
1056 case V_028C70_COLOR_8_8:
1057 case V_028C70_COLOR_8_8_8_8:
1058 /* For 1 and 2-channel formats, use the superset thereof. */
1059 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1060 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1061 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1062 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1063 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1064 }
1065 break;
1066
1067 case V_028C70_COLOR_5_6_5:
1068 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1069 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1070 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1071 }
1072 break;
1073
1074 case V_028C70_COLOR_1_5_5_5:
1075 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1076 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1077 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1078 }
1079 break;
1080
1081 case V_028C70_COLOR_4_4_4_4:
1082 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1083 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1084 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1085 }
1086 break;
1087
1088 case V_028C70_COLOR_32:
1089 if (swap == V_028C70_SWAP_STD &&
1090 spi_format == V_028714_SPI_SHADER_32_R)
1091 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1092 else if (swap == V_028C70_SWAP_ALT_REV &&
1093 spi_format == V_028714_SPI_SHADER_32_AR)
1094 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1095 break;
1096
1097 case V_028C70_COLOR_16:
1098 case V_028C70_COLOR_16_16:
1099 /* For 1-channel formats, use the superset thereof. */
1100 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1101 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1102 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1103 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1104 if (swap == V_028C70_SWAP_STD ||
1105 swap == V_028C70_SWAP_STD_REV)
1106 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1107 else
1108 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1109 }
1110 break;
1111
1112 case V_028C70_COLOR_10_11_11:
1113 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1114 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1115 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1116 }
1117 break;
1118
1119 case V_028C70_COLOR_2_10_10_10:
1120 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1121 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1122 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1123 }
1124 break;
1125 }
1126 }
1127
1128 for (unsigned i = subpass->color_count; i < 8; ++i) {
1129 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1130 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1131 }
1132 /* TODO: avoid redundantly setting context registers */
1133 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1134 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1135 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1136 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1137
1138 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1139 }
1140
1141 static void
1142 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1143 {
1144 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1145
1146 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1147 return;
1148
1149 radv_update_multisample_state(cmd_buffer, pipeline);
1150 radv_update_binning_state(cmd_buffer, pipeline);
1151
1152 cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed,
1153 pipeline->scratch_bytes_per_wave);
1154 cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted,
1155 pipeline->max_waves);
1156
1157 if (!cmd_buffer->state.emitted_pipeline ||
1158 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1159 pipeline->graphics.can_use_guardband)
1160 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1161
1162 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1163
1164 if (!cmd_buffer->state.emitted_pipeline ||
1165 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1166 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1167 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1168 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1169 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1170 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1171 }
1172
1173 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1174 if (!pipeline->shaders[i])
1175 continue;
1176
1177 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1178 pipeline->shaders[i]->bo);
1179 }
1180
1181 if (radv_pipeline_has_gs_copy_shader(pipeline))
1182 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1183 pipeline->gs_copy_shader->bo);
1184
1185 if (unlikely(cmd_buffer->device->trace_bo))
1186 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1187
1188 cmd_buffer->state.emitted_pipeline = pipeline;
1189
1190 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1191 }
1192
1193 static void
1194 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1195 {
1196 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1197 cmd_buffer->state.dynamic.viewport.viewports);
1198 }
1199
1200 static void
1201 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1202 {
1203 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1204
1205 si_write_scissors(cmd_buffer->cs, 0, count,
1206 cmd_buffer->state.dynamic.scissor.scissors,
1207 cmd_buffer->state.dynamic.viewport.viewports,
1208 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1209
1210 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1211 }
1212
1213 static void
1214 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1215 {
1216 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1217 return;
1218
1219 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1220 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1221 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1222 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1223 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1224 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1225 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1226 }
1227 }
1228
1229 static void
1230 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1231 {
1232 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1233
1234 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1235 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1236 }
1237
1238 static void
1239 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1240 {
1241 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1242
1243 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1244 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1245 }
1246
1247 static void
1248 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1249 {
1250 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1251
1252 radeon_set_context_reg_seq(cmd_buffer->cs,
1253 R_028430_DB_STENCILREFMASK, 2);
1254 radeon_emit(cmd_buffer->cs,
1255 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1256 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1257 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1258 S_028430_STENCILOPVAL(1));
1259 radeon_emit(cmd_buffer->cs,
1260 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1261 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1262 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1263 S_028434_STENCILOPVAL_BF(1));
1264 }
1265
1266 static void
1267 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1268 {
1269 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1270
1271 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1272 fui(d->depth_bounds.min));
1273 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1274 fui(d->depth_bounds.max));
1275 }
1276
1277 static void
1278 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1279 {
1280 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1281 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1282 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1283
1284
1285 radeon_set_context_reg_seq(cmd_buffer->cs,
1286 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1287 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1288 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1289 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1290 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1291 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1292 }
1293
1294 static void
1295 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1296 int index,
1297 struct radv_color_buffer_info *cb,
1298 struct radv_image_view *iview,
1299 VkImageLayout layout,
1300 bool in_render_loop)
1301 {
1302 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1303 uint32_t cb_color_info = cb->cb_color_info;
1304 struct radv_image *image = iview->image;
1305
1306 if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
1307 radv_image_queue_family_mask(image,
1308 cmd_buffer->queue_family_index,
1309 cmd_buffer->queue_family_index))) {
1310 cb_color_info &= C_028C70_DCC_ENABLE;
1311 }
1312
1313 if (radv_image_is_tc_compat_cmask(image) &&
1314 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1315 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1316 /* If this bit is set, the FMASK decompression operation
1317 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1318 */
1319 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1320 }
1321
1322 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1323 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1324 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1325 radeon_emit(cmd_buffer->cs, 0);
1326 radeon_emit(cmd_buffer->cs, 0);
1327 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1328 radeon_emit(cmd_buffer->cs, cb_color_info);
1329 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1330 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1331 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1332 radeon_emit(cmd_buffer->cs, 0);
1333 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1334 radeon_emit(cmd_buffer->cs, 0);
1335
1336 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1337 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1338
1339 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1340 cb->cb_color_base >> 32);
1341 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1342 cb->cb_color_cmask >> 32);
1343 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1344 cb->cb_color_fmask >> 32);
1345 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1346 cb->cb_dcc_base >> 32);
1347 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1348 cb->cb_color_attrib2);
1349 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1350 cb->cb_color_attrib3);
1351 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1352 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1353 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1354 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1355 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1356 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1357 radeon_emit(cmd_buffer->cs, cb_color_info);
1358 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1359 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1360 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1361 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1362 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1363 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1364
1365 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1366 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1367 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1368
1369 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1370 cb->cb_mrt_epitch);
1371 } else {
1372 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1373 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1374 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1375 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1376 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1377 radeon_emit(cmd_buffer->cs, cb_color_info);
1378 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1379 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1380 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1381 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1382 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1383 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1384
1385 if (is_vi) { /* DCC BASE */
1386 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1387 }
1388 }
1389
1390 if (radv_dcc_enabled(image, iview->base_mip)) {
1391 /* Drawing with DCC enabled also compresses colorbuffers. */
1392 VkImageSubresourceRange range = {
1393 .aspectMask = iview->aspect_mask,
1394 .baseMipLevel = iview->base_mip,
1395 .levelCount = iview->level_count,
1396 .baseArrayLayer = iview->base_layer,
1397 .layerCount = iview->layer_count,
1398 };
1399
1400 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1401 }
1402 }
1403
1404 static void
1405 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1406 struct radv_ds_buffer_info *ds,
1407 const struct radv_image_view *iview,
1408 VkImageLayout layout,
1409 bool in_render_loop, bool requires_cond_exec)
1410 {
1411 const struct radv_image *image = iview->image;
1412 uint32_t db_z_info = ds->db_z_info;
1413 uint32_t db_z_info_reg;
1414
1415 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||
1416 !radv_image_is_tc_compat_htile(image))
1417 return;
1418
1419 if (!radv_layout_has_htile(image, layout, in_render_loop,
1420 radv_image_queue_family_mask(image,
1421 cmd_buffer->queue_family_index,
1422 cmd_buffer->queue_family_index))) {
1423 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1424 }
1425
1426 db_z_info &= C_028040_ZRANGE_PRECISION;
1427
1428 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1429 db_z_info_reg = R_028038_DB_Z_INFO;
1430 } else {
1431 db_z_info_reg = R_028040_DB_Z_INFO;
1432 }
1433
1434 /* When we don't know the last fast clear value we need to emit a
1435 * conditional packet that will eventually skip the following
1436 * SET_CONTEXT_REG packet.
1437 */
1438 if (requires_cond_exec) {
1439 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
1440
1441 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1442 radeon_emit(cmd_buffer->cs, va);
1443 radeon_emit(cmd_buffer->cs, va >> 32);
1444 radeon_emit(cmd_buffer->cs, 0);
1445 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1446 }
1447
1448 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1449 }
1450
1451 static void
1452 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1453 struct radv_ds_buffer_info *ds,
1454 struct radv_image_view *iview,
1455 VkImageLayout layout,
1456 bool in_render_loop)
1457 {
1458 const struct radv_image *image = iview->image;
1459 uint32_t db_z_info = ds->db_z_info;
1460 uint32_t db_stencil_info = ds->db_stencil_info;
1461
1462 if (!radv_layout_has_htile(image, layout, in_render_loop,
1463 radv_image_queue_family_mask(image,
1464 cmd_buffer->queue_family_index,
1465 cmd_buffer->queue_family_index))) {
1466 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1467 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1468 }
1469
1470 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1471 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1472
1473 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1474 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1475 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1476
1477 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1478 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1479 radeon_emit(cmd_buffer->cs, db_z_info);
1480 radeon_emit(cmd_buffer->cs, db_stencil_info);
1481 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1482 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1483 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1484 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1485
1486 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1487 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1488 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1489 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1490 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1491 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1492 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1493 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1494 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1495 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1496 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1497
1498 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1499 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1500 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1501 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1502 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1503 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1504 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1505 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1506 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1507 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1508 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1509
1510 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1511 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1512 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1513 } else {
1514 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1515
1516 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1517 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1518 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1519 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1520 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1521 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1522 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1523 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1524 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1525 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1526
1527 }
1528
1529 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1530 radv_update_zrange_precision(cmd_buffer, ds, iview, layout,
1531 in_render_loop, true);
1532
1533 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1534 ds->pa_su_poly_offset_db_fmt_cntl);
1535 }
1536
1537 /**
1538 * Update the fast clear depth/stencil values if the image is bound as a
1539 * depth/stencil buffer.
1540 */
1541 static void
1542 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1543 const struct radv_image_view *iview,
1544 VkClearDepthStencilValue ds_clear_value,
1545 VkImageAspectFlags aspects)
1546 {
1547 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1548 const struct radv_image *image = iview->image;
1549 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1550 uint32_t att_idx;
1551
1552 if (!cmd_buffer->state.attachments || !subpass)
1553 return;
1554
1555 if (!subpass->depth_stencil_attachment)
1556 return;
1557
1558 att_idx = subpass->depth_stencil_attachment->attachment;
1559 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1560 return;
1561
1562 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1563 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1564 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1565 radeon_emit(cs, ds_clear_value.stencil);
1566 radeon_emit(cs, fui(ds_clear_value.depth));
1567 } else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1568 radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
1569 radeon_emit(cs, fui(ds_clear_value.depth));
1570 } else {
1571 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1572 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
1573 radeon_emit(cs, ds_clear_value.stencil);
1574 }
1575
1576 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1577 * only needed when clearing Z to 0.0.
1578 */
1579 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1580 ds_clear_value.depth == 0.0) {
1581 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1582 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1583
1584 radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds,
1585 iview, layout, in_render_loop, false);
1586 }
1587
1588 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1589 }
1590
1591 /**
1592 * Set the clear depth/stencil values to the image's metadata.
1593 */
1594 static void
1595 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1596 struct radv_image *image,
1597 const VkImageSubresourceRange *range,
1598 VkClearDepthStencilValue ds_clear_value,
1599 VkImageAspectFlags aspects)
1600 {
1601 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1602 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
1603 uint32_t level_count = radv_get_levelCount(image, range);
1604
1605 if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
1606 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1607 /* Use the fastest way when both aspects are used. */
1608 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));
1609 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1610 S_370_WR_CONFIRM(1) |
1611 S_370_ENGINE_SEL(V_370_PFP));
1612 radeon_emit(cs, va);
1613 radeon_emit(cs, va >> 32);
1614
1615 for (uint32_t l = 0; l < level_count; l++) {
1616 radeon_emit(cs, ds_clear_value.stencil);
1617 radeon_emit(cs, fui(ds_clear_value.depth));
1618 }
1619 } else {
1620 /* Otherwise we need one WRITE_DATA packet per level. */
1621 for (uint32_t l = 0; l < level_count; l++) {
1622 uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l);
1623 unsigned value;
1624
1625 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
1626 value = fui(ds_clear_value.depth);
1627 va += 4;
1628 } else {
1629 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
1630 value = ds_clear_value.stencil;
1631 }
1632
1633 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1634 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1635 S_370_WR_CONFIRM(1) |
1636 S_370_ENGINE_SEL(V_370_PFP));
1637 radeon_emit(cs, va);
1638 radeon_emit(cs, va >> 32);
1639 radeon_emit(cs, value);
1640 }
1641 }
1642 }
1643
1644 /**
1645 * Update the TC-compat metadata value for this image.
1646 */
1647 static void
1648 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1649 struct radv_image *image,
1650 const VkImageSubresourceRange *range,
1651 uint32_t value)
1652 {
1653 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1654
1655 if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)
1656 return;
1657
1658 uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
1659 uint32_t level_count = radv_get_levelCount(image, range);
1660
1661 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
1662 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1663 S_370_WR_CONFIRM(1) |
1664 S_370_ENGINE_SEL(V_370_PFP));
1665 radeon_emit(cs, va);
1666 radeon_emit(cs, va >> 32);
1667
1668 for (uint32_t l = 0; l < level_count; l++)
1669 radeon_emit(cs, value);
1670 }
1671
1672 static void
1673 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1674 const struct radv_image_view *iview,
1675 VkClearDepthStencilValue ds_clear_value)
1676 {
1677 VkImageSubresourceRange range = {
1678 .aspectMask = iview->aspect_mask,
1679 .baseMipLevel = iview->base_mip,
1680 .levelCount = iview->level_count,
1681 .baseArrayLayer = iview->base_layer,
1682 .layerCount = iview->layer_count,
1683 };
1684 uint32_t cond_val;
1685
1686 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1687 * depth clear value is 0.0f.
1688 */
1689 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1690
1691 radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range,
1692 cond_val);
1693 }
1694
1695 /**
1696 * Update the clear depth/stencil values for this image.
1697 */
1698 void
1699 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1700 const struct radv_image_view *iview,
1701 VkClearDepthStencilValue ds_clear_value,
1702 VkImageAspectFlags aspects)
1703 {
1704 VkImageSubresourceRange range = {
1705 .aspectMask = iview->aspect_mask,
1706 .baseMipLevel = iview->base_mip,
1707 .levelCount = iview->level_count,
1708 .baseArrayLayer = iview->base_layer,
1709 .layerCount = iview->layer_count,
1710 };
1711 struct radv_image *image = iview->image;
1712
1713 assert(radv_image_has_htile(image));
1714
1715 radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
1716 ds_clear_value, aspects);
1717
1718 if (radv_image_is_tc_compat_htile(image) &&
1719 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1720 radv_update_tc_compat_zrange_metadata(cmd_buffer, iview,
1721 ds_clear_value);
1722 }
1723
1724 radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value,
1725 aspects);
1726 }
1727
1728 /**
1729 * Load the clear depth/stencil values from the image's metadata.
1730 */
1731 static void
1732 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1733 const struct radv_image_view *iview)
1734 {
1735 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1736 const struct radv_image *image = iview->image;
1737 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1738 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
1739 unsigned reg_offset = 0, reg_count = 0;
1740
1741 if (!radv_image_has_htile(image))
1742 return;
1743
1744 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1745 ++reg_count;
1746 } else {
1747 ++reg_offset;
1748 va += 4;
1749 }
1750 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1751 ++reg_count;
1752
1753 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1754
1755 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1756 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1757 radeon_emit(cs, va);
1758 radeon_emit(cs, va >> 32);
1759 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1760 radeon_emit(cs, reg_count);
1761 } else {
1762 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1763 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1764 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1765 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1766 radeon_emit(cs, va);
1767 radeon_emit(cs, va >> 32);
1768 radeon_emit(cs, reg >> 2);
1769 radeon_emit(cs, 0);
1770
1771 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1772 radeon_emit(cs, 0);
1773 }
1774 }
1775
1776 /*
1777 * With DCC some colors don't require CMASK elimination before being
1778 * used as a texture. This sets a predicate value to determine if the
1779 * cmask eliminate is required.
1780 */
1781 void
1782 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1783 struct radv_image *image,
1784 const VkImageSubresourceRange *range, bool value)
1785 {
1786 uint64_t pred_val = value;
1787 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1788 uint32_t level_count = radv_get_levelCount(image, range);
1789 uint32_t count = 2 * level_count;
1790
1791 assert(radv_dcc_enabled(image, range->baseMipLevel));
1792
1793 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1794 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1795 S_370_WR_CONFIRM(1) |
1796 S_370_ENGINE_SEL(V_370_PFP));
1797 radeon_emit(cmd_buffer->cs, va);
1798 radeon_emit(cmd_buffer->cs, va >> 32);
1799
1800 for (uint32_t l = 0; l < level_count; l++) {
1801 radeon_emit(cmd_buffer->cs, pred_val);
1802 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1803 }
1804 }
1805
1806 /**
1807 * Update the DCC predicate to reflect the compression state.
1808 */
1809 void
1810 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1811 struct radv_image *image,
1812 const VkImageSubresourceRange *range, bool value)
1813 {
1814 uint64_t pred_val = value;
1815 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1816 uint32_t level_count = radv_get_levelCount(image, range);
1817 uint32_t count = 2 * level_count;
1818
1819 assert(radv_dcc_enabled(image, range->baseMipLevel));
1820
1821 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1822 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1823 S_370_WR_CONFIRM(1) |
1824 S_370_ENGINE_SEL(V_370_PFP));
1825 radeon_emit(cmd_buffer->cs, va);
1826 radeon_emit(cmd_buffer->cs, va >> 32);
1827
1828 for (uint32_t l = 0; l < level_count; l++) {
1829 radeon_emit(cmd_buffer->cs, pred_val);
1830 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1831 }
1832 }
1833
1834 /**
1835 * Update the fast clear color values if the image is bound as a color buffer.
1836 */
1837 static void
1838 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1839 struct radv_image *image,
1840 int cb_idx,
1841 uint32_t color_values[2])
1842 {
1843 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1844 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1845 uint32_t att_idx;
1846
1847 if (!cmd_buffer->state.attachments || !subpass)
1848 return;
1849
1850 att_idx = subpass->color_attachments[cb_idx].attachment;
1851 if (att_idx == VK_ATTACHMENT_UNUSED)
1852 return;
1853
1854 if (cmd_buffer->state.attachments[att_idx].iview->image != image)
1855 return;
1856
1857 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1858 radeon_emit(cs, color_values[0]);
1859 radeon_emit(cs, color_values[1]);
1860
1861 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1862 }
1863
1864 /**
1865 * Set the clear color values to the image's metadata.
1866 */
1867 static void
1868 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1869 struct radv_image *image,
1870 const VkImageSubresourceRange *range,
1871 uint32_t color_values[2])
1872 {
1873 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1874 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1875 uint32_t level_count = radv_get_levelCount(image, range);
1876 uint32_t count = 2 * level_count;
1877
1878 assert(radv_image_has_cmask(image) ||
1879 radv_dcc_enabled(image, range->baseMipLevel));
1880
1881 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1882 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1883 S_370_WR_CONFIRM(1) |
1884 S_370_ENGINE_SEL(V_370_PFP));
1885 radeon_emit(cs, va);
1886 radeon_emit(cs, va >> 32);
1887
1888 for (uint32_t l = 0; l < level_count; l++) {
1889 radeon_emit(cs, color_values[0]);
1890 radeon_emit(cs, color_values[1]);
1891 }
1892 }
1893
1894 /**
1895 * Update the clear color values for this image.
1896 */
1897 void
1898 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1899 const struct radv_image_view *iview,
1900 int cb_idx,
1901 uint32_t color_values[2])
1902 {
1903 struct radv_image *image = iview->image;
1904 VkImageSubresourceRange range = {
1905 .aspectMask = iview->aspect_mask,
1906 .baseMipLevel = iview->base_mip,
1907 .levelCount = iview->level_count,
1908 .baseArrayLayer = iview->base_layer,
1909 .layerCount = iview->layer_count,
1910 };
1911
1912 assert(radv_image_has_cmask(image) ||
1913 radv_dcc_enabled(image, iview->base_mip));
1914
1915 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1916
1917 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1918 color_values);
1919 }
1920
1921 /**
1922 * Load the clear color values from the image's metadata.
1923 */
1924 static void
1925 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1926 struct radv_image_view *iview,
1927 int cb_idx)
1928 {
1929 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1930 struct radv_image *image = iview->image;
1931 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1932
1933 if (!radv_image_has_cmask(image) &&
1934 !radv_dcc_enabled(image, iview->base_mip))
1935 return;
1936
1937 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1938
1939 if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
1940 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1941 radeon_emit(cs, va);
1942 radeon_emit(cs, va >> 32);
1943 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1944 radeon_emit(cs, 2);
1945 } else {
1946 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1947 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1948 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1949 COPY_DATA_COUNT_SEL);
1950 radeon_emit(cs, va);
1951 radeon_emit(cs, va >> 32);
1952 radeon_emit(cs, reg >> 2);
1953 radeon_emit(cs, 0);
1954
1955 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1956 radeon_emit(cs, 0);
1957 }
1958 }
1959
1960 static void
1961 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1962 {
1963 int i;
1964 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1965 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1966
1967 /* this may happen for inherited secondary recording */
1968 if (!framebuffer)
1969 return;
1970
1971 for (i = 0; i < 8; ++i) {
1972 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1973 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1974 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1975 continue;
1976 }
1977
1978 int idx = subpass->color_attachments[i].attachment;
1979 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1980 VkImageLayout layout = subpass->color_attachments[i].layout;
1981 bool in_render_loop = subpass->color_attachments[i].in_render_loop;
1982
1983 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
1984
1985 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1986 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1987 radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
1988
1989 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1990 }
1991
1992 if (subpass->depth_stencil_attachment) {
1993 int idx = subpass->depth_stencil_attachment->attachment;
1994 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1995 bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
1996 struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
1997 struct radv_image *image = iview->image;
1998 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
1999 ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
2000 cmd_buffer->queue_family_index,
2001 cmd_buffer->queue_family_index);
2002 /* We currently don't support writing decompressed HTILE */
2003 assert(radv_layout_has_htile(image, layout, in_render_loop, queue_mask) ==
2004 radv_layout_is_htile_compressed(image, layout, in_render_loop, queue_mask));
2005
2006 radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop);
2007
2008 if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
2009 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2010 cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
2011 }
2012 radv_load_ds_clear_metadata(cmd_buffer, iview);
2013 } else {
2014 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
2015 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
2016 else
2017 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
2018
2019 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2020 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2021 }
2022 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2023 S_028208_BR_X(framebuffer->width) |
2024 S_028208_BR_Y(framebuffer->height));
2025
2026 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
2027 bool disable_constant_encode =
2028 cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
2029 enum chip_class chip_class =
2030 cmd_buffer->device->physical_device->rad_info.chip_class;
2031 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
2032
2033 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
2034 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
2035 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
2036 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
2037 }
2038
2039 if (cmd_buffer->device->dfsm_allowed) {
2040 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2041 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2042 }
2043
2044 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
2045 }
2046
2047 static void
2048 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
2049 {
2050 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2051 struct radv_cmd_state *state = &cmd_buffer->state;
2052
2053 if (state->index_type != state->last_index_type) {
2054 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2055 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2056 cs, R_03090C_VGT_INDEX_TYPE,
2057 2, state->index_type);
2058 } else {
2059 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2060 radeon_emit(cs, state->index_type);
2061 }
2062
2063 state->last_index_type = state->index_type;
2064 }
2065
2066 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2067 radeon_emit(cs, state->index_va);
2068 radeon_emit(cs, state->index_va >> 32);
2069
2070 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2071 radeon_emit(cs, state->max_index_count);
2072
2073 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
2074 }
2075
2076 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
2077 {
2078 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
2079 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2080 uint32_t pa_sc_mode_cntl_1 =
2081 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
2082 uint32_t db_count_control;
2083
2084 if(!cmd_buffer->state.active_occlusion_queries) {
2085 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2086 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2087 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2088 has_perfect_queries) {
2089 /* Re-enable out-of-order rasterization if the
2090 * bound pipeline supports it and if it's has
2091 * been disabled before starting any perfect
2092 * occlusion queries.
2093 */
2094 radeon_set_context_reg(cmd_buffer->cs,
2095 R_028A4C_PA_SC_MODE_CNTL_1,
2096 pa_sc_mode_cntl_1);
2097 }
2098 }
2099 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2100 } else {
2101 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2102 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2103 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2104
2105 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2106 db_count_control =
2107 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2108 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2109 S_028004_SAMPLE_RATE(sample_rate) |
2110 S_028004_ZPASS_ENABLE(1) |
2111 S_028004_SLICE_EVEN_ENABLE(1) |
2112 S_028004_SLICE_ODD_ENABLE(1);
2113
2114 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2115 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2116 has_perfect_queries) {
2117 /* If the bound pipeline has enabled
2118 * out-of-order rasterization, we should
2119 * disable it before starting any perfect
2120 * occlusion queries.
2121 */
2122 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2123
2124 radeon_set_context_reg(cmd_buffer->cs,
2125 R_028A4C_PA_SC_MODE_CNTL_1,
2126 pa_sc_mode_cntl_1);
2127 }
2128 } else {
2129 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2130 S_028004_SAMPLE_RATE(sample_rate);
2131 }
2132 }
2133
2134 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2135
2136 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2137 }
2138
2139 static void
2140 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2141 {
2142 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2143
2144 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2145 radv_emit_viewport(cmd_buffer);
2146
2147 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2148 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
2149 radv_emit_scissor(cmd_buffer);
2150
2151 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2152 radv_emit_line_width(cmd_buffer);
2153
2154 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2155 radv_emit_blend_constants(cmd_buffer);
2156
2157 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2158 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2159 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2160 radv_emit_stencil(cmd_buffer);
2161
2162 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2163 radv_emit_depth_bounds(cmd_buffer);
2164
2165 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2166 radv_emit_depth_bias(cmd_buffer);
2167
2168 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2169 radv_emit_discard_rectangle(cmd_buffer);
2170
2171 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2172 radv_emit_sample_locations(cmd_buffer);
2173
2174 cmd_buffer->state.dirty &= ~states;
2175 }
2176
2177 static void
2178 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2179 VkPipelineBindPoint bind_point)
2180 {
2181 struct radv_descriptor_state *descriptors_state =
2182 radv_get_descriptors_state(cmd_buffer, bind_point);
2183 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2184 unsigned bo_offset;
2185
2186 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2187 set->mapped_ptr,
2188 &bo_offset))
2189 return;
2190
2191 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2192 set->va += bo_offset;
2193 }
2194
2195 static void
2196 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2197 VkPipelineBindPoint bind_point)
2198 {
2199 struct radv_descriptor_state *descriptors_state =
2200 radv_get_descriptors_state(cmd_buffer, bind_point);
2201 uint32_t size = MAX_SETS * 4;
2202 uint32_t offset;
2203 void *ptr;
2204
2205 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2206 256, &offset, &ptr))
2207 return;
2208
2209 for (unsigned i = 0; i < MAX_SETS; i++) {
2210 uint32_t *uptr = ((uint32_t *)ptr) + i;
2211 uint64_t set_va = 0;
2212 struct radv_descriptor_set *set = descriptors_state->sets[i];
2213 if (descriptors_state->valid & (1u << i))
2214 set_va = set->va;
2215 uptr[0] = set_va & 0xffffffff;
2216 }
2217
2218 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2219 va += offset;
2220
2221 if (cmd_buffer->state.pipeline) {
2222 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2223 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2224 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2225
2226 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2227 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2228 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2229
2230 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2231 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2232 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2233
2234 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2235 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2236 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2237
2238 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2239 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2240 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2241 }
2242
2243 if (cmd_buffer->state.compute_pipeline)
2244 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2245 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2246 }
2247
2248 static void
2249 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2250 VkShaderStageFlags stages)
2251 {
2252 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2253 VK_PIPELINE_BIND_POINT_COMPUTE :
2254 VK_PIPELINE_BIND_POINT_GRAPHICS;
2255 struct radv_descriptor_state *descriptors_state =
2256 radv_get_descriptors_state(cmd_buffer, bind_point);
2257 struct radv_cmd_state *state = &cmd_buffer->state;
2258 bool flush_indirect_descriptors;
2259
2260 if (!descriptors_state->dirty)
2261 return;
2262
2263 if (descriptors_state->push_dirty)
2264 radv_flush_push_descriptors(cmd_buffer, bind_point);
2265
2266 flush_indirect_descriptors =
2267 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2268 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2269 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2270 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2271
2272 if (flush_indirect_descriptors)
2273 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2274
2275 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2276 cmd_buffer->cs,
2277 MAX_SETS * MESA_SHADER_STAGES * 4);
2278
2279 if (cmd_buffer->state.pipeline) {
2280 radv_foreach_stage(stage, stages) {
2281 if (!cmd_buffer->state.pipeline->shaders[stage])
2282 continue;
2283
2284 radv_emit_descriptor_pointers(cmd_buffer,
2285 cmd_buffer->state.pipeline,
2286 descriptors_state, stage);
2287 }
2288 }
2289
2290 if (cmd_buffer->state.compute_pipeline &&
2291 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2292 radv_emit_descriptor_pointers(cmd_buffer,
2293 cmd_buffer->state.compute_pipeline,
2294 descriptors_state,
2295 MESA_SHADER_COMPUTE);
2296 }
2297
2298 descriptors_state->dirty = 0;
2299 descriptors_state->push_dirty = false;
2300
2301 assert(cmd_buffer->cs->cdw <= cdw_max);
2302
2303 if (unlikely(cmd_buffer->device->trace_bo))
2304 radv_save_descriptors(cmd_buffer, bind_point);
2305 }
2306
2307 static void
2308 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2309 VkShaderStageFlags stages)
2310 {
2311 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2312 ? cmd_buffer->state.compute_pipeline
2313 : cmd_buffer->state.pipeline;
2314 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2315 VK_PIPELINE_BIND_POINT_COMPUTE :
2316 VK_PIPELINE_BIND_POINT_GRAPHICS;
2317 struct radv_descriptor_state *descriptors_state =
2318 radv_get_descriptors_state(cmd_buffer, bind_point);
2319 struct radv_pipeline_layout *layout = pipeline->layout;
2320 struct radv_shader_variant *shader, *prev_shader;
2321 bool need_push_constants = false;
2322 unsigned offset;
2323 void *ptr;
2324 uint64_t va;
2325
2326 stages &= cmd_buffer->push_constant_stages;
2327 if (!stages ||
2328 (!layout->push_constant_size && !layout->dynamic_offset_count))
2329 return;
2330
2331 radv_foreach_stage(stage, stages) {
2332 shader = radv_get_shader(pipeline, stage);
2333 if (!shader)
2334 continue;
2335
2336 need_push_constants |= shader->info.loads_push_constants;
2337 need_push_constants |= shader->info.loads_dynamic_offsets;
2338
2339 uint8_t base = shader->info.base_inline_push_consts;
2340 uint8_t count = shader->info.num_inline_push_consts;
2341
2342 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2343 AC_UD_INLINE_PUSH_CONSTANTS,
2344 count,
2345 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2346 }
2347
2348 if (need_push_constants) {
2349 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2350 16 * layout->dynamic_offset_count,
2351 256, &offset, &ptr))
2352 return;
2353
2354 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2355 memcpy((char*)ptr + layout->push_constant_size,
2356 descriptors_state->dynamic_buffers,
2357 16 * layout->dynamic_offset_count);
2358
2359 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2360 va += offset;
2361
2362 ASSERTED unsigned cdw_max =
2363 radeon_check_space(cmd_buffer->device->ws,
2364 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2365
2366 prev_shader = NULL;
2367 radv_foreach_stage(stage, stages) {
2368 shader = radv_get_shader(pipeline, stage);
2369
2370 /* Avoid redundantly emitting the address for merged stages. */
2371 if (shader && shader != prev_shader) {
2372 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2373 AC_UD_PUSH_CONSTANTS, va);
2374
2375 prev_shader = shader;
2376 }
2377 }
2378 assert(cmd_buffer->cs->cdw <= cdw_max);
2379 }
2380
2381 cmd_buffer->push_constant_stages &= ~stages;
2382 }
2383
2384 static void
2385 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2386 bool pipeline_is_dirty)
2387 {
2388 if ((pipeline_is_dirty ||
2389 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2390 cmd_buffer->state.pipeline->num_vertex_bindings &&
2391 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.has_vertex_buffers) {
2392 unsigned vb_offset;
2393 void *vb_ptr;
2394 uint32_t i = 0;
2395 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2396 uint64_t va;
2397
2398 /* allocate some descriptor state for vertex buffers */
2399 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2400 &vb_offset, &vb_ptr))
2401 return;
2402
2403 for (i = 0; i < count; i++) {
2404 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2405 uint32_t offset;
2406 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2407 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2408 unsigned num_records;
2409
2410 if (!buffer)
2411 continue;
2412
2413 va = radv_buffer_get_va(buffer->bo);
2414
2415 offset = cmd_buffer->vertex_bindings[i].offset;
2416 va += offset + buffer->offset;
2417
2418 num_records = buffer->size - offset;
2419 if (cmd_buffer->device->physical_device->rad_info.chip_class != GFX8 && stride)
2420 num_records /= stride;
2421
2422 desc[0] = va;
2423 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2424 desc[2] = num_records;
2425 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2426 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2427 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2428 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2429
2430 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2431 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2432 S_008F0C_OOB_SELECT(1) |
2433 S_008F0C_RESOURCE_LEVEL(1);
2434 } else {
2435 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2436 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2437 }
2438 }
2439
2440 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2441 va += vb_offset;
2442
2443 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2444 AC_UD_VS_VERTEX_BUFFERS, va);
2445
2446 cmd_buffer->state.vb_va = va;
2447 cmd_buffer->state.vb_size = count * 16;
2448 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2449 }
2450 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2451 }
2452
2453 static void
2454 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2455 {
2456 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2457 struct radv_userdata_info *loc;
2458 uint32_t base_reg;
2459
2460 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2461 if (!radv_get_shader(pipeline, stage))
2462 continue;
2463
2464 loc = radv_lookup_user_sgpr(pipeline, stage,
2465 AC_UD_STREAMOUT_BUFFERS);
2466 if (loc->sgpr_idx == -1)
2467 continue;
2468
2469 base_reg = pipeline->user_data_0[stage];
2470
2471 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2472 base_reg + loc->sgpr_idx * 4, va, false);
2473 }
2474
2475 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2476 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2477 if (loc->sgpr_idx != -1) {
2478 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2479
2480 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2481 base_reg + loc->sgpr_idx * 4, va, false);
2482 }
2483 }
2484 }
2485
2486 static void
2487 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2488 {
2489 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2490 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2491 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2492 unsigned so_offset;
2493 void *so_ptr;
2494 uint64_t va;
2495
2496 /* Allocate some descriptor state for streamout buffers. */
2497 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2498 MAX_SO_BUFFERS * 16, 256,
2499 &so_offset, &so_ptr))
2500 return;
2501
2502 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2503 struct radv_buffer *buffer = sb[i].buffer;
2504 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2505
2506 if (!(so->enabled_mask & (1 << i)))
2507 continue;
2508
2509 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2510
2511 va += sb[i].offset;
2512
2513 /* Set the descriptor.
2514 *
2515 * On GFX8, the format must be non-INVALID, otherwise
2516 * the buffer will be considered not bound and store
2517 * instructions will be no-ops.
2518 */
2519 uint32_t size = 0xffffffff;
2520
2521 /* Compute the correct buffer size for NGG streamout
2522 * because it's used to determine the max emit per
2523 * buffer.
2524 */
2525 if (cmd_buffer->device->physical_device->use_ngg_streamout)
2526 size = buffer->size - sb[i].offset;
2527
2528 desc[0] = va;
2529 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2530 desc[2] = size;
2531 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2532 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2533 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2534 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2535
2536 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2537 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2538 S_008F0C_OOB_SELECT(3) |
2539 S_008F0C_RESOURCE_LEVEL(1);
2540 } else {
2541 desc[3] |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2542 }
2543 }
2544
2545 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2546 va += so_offset;
2547
2548 radv_emit_streamout_buffers(cmd_buffer, va);
2549 }
2550
2551 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2552 }
2553
2554 static void
2555 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2556 {
2557 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2558 radv_flush_streamout_descriptors(cmd_buffer);
2559 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2560 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2561 }
2562
2563 struct radv_draw_info {
2564 /**
2565 * Number of vertices.
2566 */
2567 uint32_t count;
2568
2569 /**
2570 * Index of the first vertex.
2571 */
2572 int32_t vertex_offset;
2573
2574 /**
2575 * First instance id.
2576 */
2577 uint32_t first_instance;
2578
2579 /**
2580 * Number of instances.
2581 */
2582 uint32_t instance_count;
2583
2584 /**
2585 * First index (indexed draws only).
2586 */
2587 uint32_t first_index;
2588
2589 /**
2590 * Whether it's an indexed draw.
2591 */
2592 bool indexed;
2593
2594 /**
2595 * Indirect draw parameters resource.
2596 */
2597 struct radv_buffer *indirect;
2598 uint64_t indirect_offset;
2599 uint32_t stride;
2600
2601 /**
2602 * Draw count parameters resource.
2603 */
2604 struct radv_buffer *count_buffer;
2605 uint64_t count_buffer_offset;
2606
2607 /**
2608 * Stream output parameters resource.
2609 */
2610 struct radv_buffer *strmout_buffer;
2611 uint64_t strmout_buffer_offset;
2612 };
2613
2614 static uint32_t
2615 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2616 {
2617 switch (cmd_buffer->state.index_type) {
2618 case V_028A7C_VGT_INDEX_8:
2619 return 0xffu;
2620 case V_028A7C_VGT_INDEX_16:
2621 return 0xffffu;
2622 case V_028A7C_VGT_INDEX_32:
2623 return 0xffffffffu;
2624 default:
2625 unreachable("invalid index type");
2626 }
2627 }
2628
2629 static void
2630 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2631 bool instanced_draw, bool indirect_draw,
2632 bool count_from_stream_output,
2633 uint32_t draw_vertex_count)
2634 {
2635 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2636 struct radv_cmd_state *state = &cmd_buffer->state;
2637 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2638 unsigned ia_multi_vgt_param;
2639
2640 ia_multi_vgt_param =
2641 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2642 indirect_draw,
2643 count_from_stream_output,
2644 draw_vertex_count);
2645
2646 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2647 if (info->chip_class == GFX9) {
2648 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2649 cs,
2650 R_030960_IA_MULTI_VGT_PARAM,
2651 4, ia_multi_vgt_param);
2652 } else if (info->chip_class >= GFX7) {
2653 radeon_set_context_reg_idx(cs,
2654 R_028AA8_IA_MULTI_VGT_PARAM,
2655 1, ia_multi_vgt_param);
2656 } else {
2657 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2658 ia_multi_vgt_param);
2659 }
2660 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2661 }
2662 }
2663
2664 static void
2665 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2666 const struct radv_draw_info *draw_info)
2667 {
2668 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2669 struct radv_cmd_state *state = &cmd_buffer->state;
2670 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2671 int32_t primitive_reset_en;
2672
2673 /* Draw state. */
2674 if (info->chip_class < GFX10) {
2675 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2676 draw_info->indirect,
2677 !!draw_info->strmout_buffer,
2678 draw_info->indirect ? 0 : draw_info->count);
2679 }
2680
2681 /* Primitive restart. */
2682 primitive_reset_en =
2683 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2684
2685 if (primitive_reset_en != state->last_primitive_reset_en) {
2686 state->last_primitive_reset_en = primitive_reset_en;
2687 if (info->chip_class >= GFX9) {
2688 radeon_set_uconfig_reg(cs,
2689 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2690 primitive_reset_en);
2691 } else {
2692 radeon_set_context_reg(cs,
2693 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2694 primitive_reset_en);
2695 }
2696 }
2697
2698 if (primitive_reset_en) {
2699 uint32_t primitive_reset_index =
2700 radv_get_primitive_reset_index(cmd_buffer);
2701
2702 if (primitive_reset_index != state->last_primitive_reset_index) {
2703 radeon_set_context_reg(cs,
2704 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2705 primitive_reset_index);
2706 state->last_primitive_reset_index = primitive_reset_index;
2707 }
2708 }
2709
2710 if (draw_info->strmout_buffer) {
2711 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2712
2713 va += draw_info->strmout_buffer->offset +
2714 draw_info->strmout_buffer_offset;
2715
2716 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2717 draw_info->stride);
2718
2719 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2720 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2721 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2722 COPY_DATA_WR_CONFIRM);
2723 radeon_emit(cs, va);
2724 radeon_emit(cs, va >> 32);
2725 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2726 radeon_emit(cs, 0); /* unused */
2727
2728 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2729 }
2730 }
2731
2732 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2733 VkPipelineStageFlags src_stage_mask)
2734 {
2735 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2736 VK_PIPELINE_STAGE_TRANSFER_BIT |
2737 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2738 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2739 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2740 }
2741
2742 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2743 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2744 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2745 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2746 VK_PIPELINE_STAGE_TRANSFER_BIT |
2747 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2748 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2749 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2750 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2751 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2752 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2753 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2754 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2755 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2756 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2757 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2758 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2759 }
2760 }
2761
2762 static enum radv_cmd_flush_bits
2763 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2764 VkAccessFlags src_flags,
2765 struct radv_image *image)
2766 {
2767 bool flush_CB_meta = true, flush_DB_meta = true;
2768 enum radv_cmd_flush_bits flush_bits = 0;
2769 uint32_t b;
2770
2771 if (image) {
2772 if (!radv_image_has_CB_metadata(image))
2773 flush_CB_meta = false;
2774 if (!radv_image_has_htile(image))
2775 flush_DB_meta = false;
2776 }
2777
2778 for_each_bit(b, src_flags) {
2779 switch ((VkAccessFlagBits)(1 << b)) {
2780 case VK_ACCESS_SHADER_WRITE_BIT:
2781 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2782 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2783 flush_bits |= RADV_CMD_FLAG_WB_L2;
2784 break;
2785 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2786 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2787 if (flush_CB_meta)
2788 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2789 break;
2790 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2791 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2792 if (flush_DB_meta)
2793 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2794 break;
2795 case VK_ACCESS_TRANSFER_WRITE_BIT:
2796 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2797 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2798 RADV_CMD_FLAG_INV_L2;
2799
2800 if (flush_CB_meta)
2801 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2802 if (flush_DB_meta)
2803 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2804 break;
2805 default:
2806 break;
2807 }
2808 }
2809 return flush_bits;
2810 }
2811
2812 static enum radv_cmd_flush_bits
2813 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2814 VkAccessFlags dst_flags,
2815 struct radv_image *image)
2816 {
2817 bool flush_CB_meta = true, flush_DB_meta = true;
2818 enum radv_cmd_flush_bits flush_bits = 0;
2819 bool flush_CB = true, flush_DB = true;
2820 bool image_is_coherent = false;
2821 uint32_t b;
2822
2823 if (image) {
2824 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2825 flush_CB = false;
2826 flush_DB = false;
2827 }
2828
2829 if (!radv_image_has_CB_metadata(image))
2830 flush_CB_meta = false;
2831 if (!radv_image_has_htile(image))
2832 flush_DB_meta = false;
2833
2834 /* TODO: implement shader coherent for GFX10 */
2835
2836 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2837 if (image->info.samples == 1 &&
2838 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2839 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2840 !vk_format_is_stencil(image->vk_format)) {
2841 /* Single-sample color and single-sample depth
2842 * (not stencil) are coherent with shaders on
2843 * GFX9.
2844 */
2845 image_is_coherent = true;
2846 }
2847 }
2848 }
2849
2850 for_each_bit(b, dst_flags) {
2851 switch ((VkAccessFlagBits)(1 << b)) {
2852 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2853 case VK_ACCESS_INDEX_READ_BIT:
2854 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2855 break;
2856 case VK_ACCESS_UNIFORM_READ_BIT:
2857 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2858 break;
2859 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2860 case VK_ACCESS_TRANSFER_READ_BIT:
2861 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2862 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2863 RADV_CMD_FLAG_INV_L2;
2864 break;
2865 case VK_ACCESS_SHADER_READ_BIT:
2866 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2867 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
2868 * invalidate the scalar cache. */
2869 if (cmd_buffer->device->physical_device->use_aco)
2870 flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
2871
2872 if (!image_is_coherent)
2873 flush_bits |= RADV_CMD_FLAG_INV_L2;
2874 break;
2875 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2876 if (flush_CB)
2877 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2878 if (flush_CB_meta)
2879 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2880 break;
2881 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2882 if (flush_DB)
2883 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2884 if (flush_DB_meta)
2885 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2886 break;
2887 default:
2888 break;
2889 }
2890 }
2891 return flush_bits;
2892 }
2893
2894 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2895 const struct radv_subpass_barrier *barrier)
2896 {
2897 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2898 NULL);
2899 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2900 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2901 NULL);
2902 }
2903
2904 uint32_t
2905 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2906 {
2907 struct radv_cmd_state *state = &cmd_buffer->state;
2908 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2909
2910 /* The id of this subpass shouldn't exceed the number of subpasses in
2911 * this render pass minus 1.
2912 */
2913 assert(subpass_id < state->pass->subpass_count);
2914 return subpass_id;
2915 }
2916
2917 static struct radv_sample_locations_state *
2918 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2919 uint32_t att_idx,
2920 bool begin_subpass)
2921 {
2922 struct radv_cmd_state *state = &cmd_buffer->state;
2923 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2924 struct radv_image_view *view = state->attachments[att_idx].iview;
2925
2926 if (view->image->info.samples == 1)
2927 return NULL;
2928
2929 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2930 /* Return the initial sample locations if this is the initial
2931 * layout transition of the given subpass attachemnt.
2932 */
2933 if (state->attachments[att_idx].sample_location.count > 0)
2934 return &state->attachments[att_idx].sample_location;
2935 } else {
2936 /* Otherwise return the subpass sample locations if defined. */
2937 if (state->subpass_sample_locs) {
2938 /* Because the driver sets the current subpass before
2939 * initial layout transitions, we should use the sample
2940 * locations from the previous subpass to avoid an
2941 * off-by-one problem. Otherwise, use the sample
2942 * locations for the current subpass for final layout
2943 * transitions.
2944 */
2945 if (begin_subpass)
2946 subpass_id--;
2947
2948 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2949 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2950 return &state->subpass_sample_locs[i].sample_location;
2951 }
2952 }
2953 }
2954
2955 return NULL;
2956 }
2957
2958 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2959 struct radv_subpass_attachment att,
2960 bool begin_subpass)
2961 {
2962 unsigned idx = att.attachment;
2963 struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
2964 struct radv_sample_locations_state *sample_locs;
2965 VkImageSubresourceRange range;
2966 range.aspectMask = 0;
2967 range.baseMipLevel = view->base_mip;
2968 range.levelCount = 1;
2969 range.baseArrayLayer = view->base_layer;
2970 range.layerCount = cmd_buffer->state.framebuffer->layers;
2971
2972 if (cmd_buffer->state.subpass->view_mask) {
2973 /* If the current subpass uses multiview, the driver might have
2974 * performed a fast color/depth clear to the whole image
2975 * (including all layers). To make sure the driver will
2976 * decompress the image correctly (if needed), we have to
2977 * account for the "real" number of layers. If the view mask is
2978 * sparse, this will decompress more layers than needed.
2979 */
2980 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2981 }
2982
2983 /* Get the subpass sample locations for the given attachment, if NULL
2984 * is returned the driver will use the default HW locations.
2985 */
2986 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2987 begin_subpass);
2988
2989 radv_handle_image_transition(cmd_buffer,
2990 view->image,
2991 cmd_buffer->state.attachments[idx].current_layout,
2992 cmd_buffer->state.attachments[idx].current_in_render_loop,
2993 att.layout, att.in_render_loop,
2994 0, 0, &range, sample_locs);
2995
2996 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2997 cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
2998
2999
3000 }
3001
3002 void
3003 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
3004 const struct radv_subpass *subpass)
3005 {
3006 cmd_buffer->state.subpass = subpass;
3007
3008 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
3009 }
3010
3011 static VkResult
3012 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
3013 struct radv_render_pass *pass,
3014 const VkRenderPassBeginInfo *info)
3015 {
3016 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
3017 vk_find_struct_const(info->pNext,
3018 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
3019 struct radv_cmd_state *state = &cmd_buffer->state;
3020
3021 if (!sample_locs) {
3022 state->subpass_sample_locs = NULL;
3023 return VK_SUCCESS;
3024 }
3025
3026 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
3027 const VkAttachmentSampleLocationsEXT *att_sample_locs =
3028 &sample_locs->pAttachmentInitialSampleLocations[i];
3029 uint32_t att_idx = att_sample_locs->attachmentIndex;
3030 struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
3031
3032 assert(vk_format_is_depth_or_stencil(image->vk_format));
3033
3034 /* From the Vulkan spec 1.1.108:
3035 *
3036 * "If the image referenced by the framebuffer attachment at
3037 * index attachmentIndex was not created with
3038 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3039 * then the values specified in sampleLocationsInfo are
3040 * ignored."
3041 */
3042 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
3043 continue;
3044
3045 const VkSampleLocationsInfoEXT *sample_locs_info =
3046 &att_sample_locs->sampleLocationsInfo;
3047
3048 state->attachments[att_idx].sample_location.per_pixel =
3049 sample_locs_info->sampleLocationsPerPixel;
3050 state->attachments[att_idx].sample_location.grid_size =
3051 sample_locs_info->sampleLocationGridSize;
3052 state->attachments[att_idx].sample_location.count =
3053 sample_locs_info->sampleLocationsCount;
3054 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
3055 sample_locs_info->pSampleLocations,
3056 sample_locs_info->sampleLocationsCount);
3057 }
3058
3059 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
3060 sample_locs->postSubpassSampleLocationsCount *
3061 sizeof(state->subpass_sample_locs[0]),
3062 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3063 if (state->subpass_sample_locs == NULL) {
3064 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3065 return cmd_buffer->record_result;
3066 }
3067
3068 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
3069
3070 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
3071 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
3072 &sample_locs->pPostSubpassSampleLocations[i];
3073 const VkSampleLocationsInfoEXT *sample_locs_info =
3074 &subpass_sample_locs_info->sampleLocationsInfo;
3075
3076 state->subpass_sample_locs[i].subpass_idx =
3077 subpass_sample_locs_info->subpassIndex;
3078 state->subpass_sample_locs[i].sample_location.per_pixel =
3079 sample_locs_info->sampleLocationsPerPixel;
3080 state->subpass_sample_locs[i].sample_location.grid_size =
3081 sample_locs_info->sampleLocationGridSize;
3082 state->subpass_sample_locs[i].sample_location.count =
3083 sample_locs_info->sampleLocationsCount;
3084 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
3085 sample_locs_info->pSampleLocations,
3086 sample_locs_info->sampleLocationsCount);
3087 }
3088
3089 return VK_SUCCESS;
3090 }
3091
3092 static VkResult
3093 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
3094 struct radv_render_pass *pass,
3095 const VkRenderPassBeginInfo *info)
3096 {
3097 struct radv_cmd_state *state = &cmd_buffer->state;
3098 const struct VkRenderPassAttachmentBeginInfoKHR *attachment_info = NULL;
3099
3100 if (info) {
3101 attachment_info = vk_find_struct_const(info->pNext,
3102 RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR);
3103 }
3104
3105
3106 if (pass->attachment_count == 0) {
3107 state->attachments = NULL;
3108 return VK_SUCCESS;
3109 }
3110
3111 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
3112 pass->attachment_count *
3113 sizeof(state->attachments[0]),
3114 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3115 if (state->attachments == NULL) {
3116 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3117 return cmd_buffer->record_result;
3118 }
3119
3120 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
3121 struct radv_render_pass_attachment *att = &pass->attachments[i];
3122 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
3123 VkImageAspectFlags clear_aspects = 0;
3124
3125 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
3126 /* color attachment */
3127 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3128 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
3129 }
3130 } else {
3131 /* depthstencil attachment */
3132 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
3133 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3134 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
3135 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3136 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
3137 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3138 }
3139 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
3140 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
3141 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3142 }
3143 }
3144
3145 state->attachments[i].pending_clear_aspects = clear_aspects;
3146 state->attachments[i].cleared_views = 0;
3147 if (clear_aspects && info) {
3148 assert(info->clearValueCount > i);
3149 state->attachments[i].clear_value = info->pClearValues[i];
3150 }
3151
3152 state->attachments[i].current_layout = att->initial_layout;
3153 state->attachments[i].sample_location.count = 0;
3154
3155 struct radv_image_view *iview;
3156 if (attachment_info && attachment_info->attachmentCount > i) {
3157 iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
3158 } else {
3159 iview = state->framebuffer->attachments[i];
3160 }
3161
3162 state->attachments[i].iview = iview;
3163 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3164 radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
3165 } else {
3166 radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
3167 }
3168 }
3169
3170 return VK_SUCCESS;
3171 }
3172
3173 VkResult radv_AllocateCommandBuffers(
3174 VkDevice _device,
3175 const VkCommandBufferAllocateInfo *pAllocateInfo,
3176 VkCommandBuffer *pCommandBuffers)
3177 {
3178 RADV_FROM_HANDLE(radv_device, device, _device);
3179 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3180
3181 VkResult result = VK_SUCCESS;
3182 uint32_t i;
3183
3184 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3185
3186 if (!list_is_empty(&pool->free_cmd_buffers)) {
3187 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3188
3189 list_del(&cmd_buffer->pool_link);
3190 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3191
3192 result = radv_reset_cmd_buffer(cmd_buffer);
3193 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3194 cmd_buffer->level = pAllocateInfo->level;
3195
3196 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3197 } else {
3198 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3199 &pCommandBuffers[i]);
3200 }
3201 if (result != VK_SUCCESS)
3202 break;
3203 }
3204
3205 if (result != VK_SUCCESS) {
3206 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3207 i, pCommandBuffers);
3208
3209 /* From the Vulkan 1.0.66 spec:
3210 *
3211 * "vkAllocateCommandBuffers can be used to create multiple
3212 * command buffers. If the creation of any of those command
3213 * buffers fails, the implementation must destroy all
3214 * successfully created command buffer objects from this
3215 * command, set all entries of the pCommandBuffers array to
3216 * NULL and return the error."
3217 */
3218 memset(pCommandBuffers, 0,
3219 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3220 }
3221
3222 return result;
3223 }
3224
3225 void radv_FreeCommandBuffers(
3226 VkDevice device,
3227 VkCommandPool commandPool,
3228 uint32_t commandBufferCount,
3229 const VkCommandBuffer *pCommandBuffers)
3230 {
3231 for (uint32_t i = 0; i < commandBufferCount; i++) {
3232 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3233
3234 if (cmd_buffer) {
3235 if (cmd_buffer->pool) {
3236 list_del(&cmd_buffer->pool_link);
3237 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3238 } else
3239 radv_cmd_buffer_destroy(cmd_buffer);
3240
3241 }
3242 }
3243 }
3244
3245 VkResult radv_ResetCommandBuffer(
3246 VkCommandBuffer commandBuffer,
3247 VkCommandBufferResetFlags flags)
3248 {
3249 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3250 return radv_reset_cmd_buffer(cmd_buffer);
3251 }
3252
3253 VkResult radv_BeginCommandBuffer(
3254 VkCommandBuffer commandBuffer,
3255 const VkCommandBufferBeginInfo *pBeginInfo)
3256 {
3257 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3258 VkResult result = VK_SUCCESS;
3259
3260 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3261 /* If the command buffer has already been resetted with
3262 * vkResetCommandBuffer, no need to do it again.
3263 */
3264 result = radv_reset_cmd_buffer(cmd_buffer);
3265 if (result != VK_SUCCESS)
3266 return result;
3267 }
3268
3269 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3270 cmd_buffer->state.last_primitive_reset_en = -1;
3271 cmd_buffer->state.last_index_type = -1;
3272 cmd_buffer->state.last_num_instances = -1;
3273 cmd_buffer->state.last_vertex_offset = -1;
3274 cmd_buffer->state.last_first_instance = -1;
3275 cmd_buffer->state.predication_type = -1;
3276 cmd_buffer->usage_flags = pBeginInfo->flags;
3277
3278 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3279 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3280 assert(pBeginInfo->pInheritanceInfo);
3281 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3282 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3283
3284 struct radv_subpass *subpass =
3285 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3286
3287 if (cmd_buffer->state.framebuffer) {
3288 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3289 if (result != VK_SUCCESS)
3290 return result;
3291 }
3292
3293 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3294 }
3295
3296 if (unlikely(cmd_buffer->device->trace_bo)) {
3297 struct radv_device *device = cmd_buffer->device;
3298
3299 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3300 device->trace_bo);
3301
3302 radv_cmd_buffer_trace_emit(cmd_buffer);
3303 }
3304
3305 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3306
3307 return result;
3308 }
3309
3310 void radv_CmdBindVertexBuffers(
3311 VkCommandBuffer commandBuffer,
3312 uint32_t firstBinding,
3313 uint32_t bindingCount,
3314 const VkBuffer* pBuffers,
3315 const VkDeviceSize* pOffsets)
3316 {
3317 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3318 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3319 bool changed = false;
3320
3321 /* We have to defer setting up vertex buffer since we need the buffer
3322 * stride from the pipeline. */
3323
3324 assert(firstBinding + bindingCount <= MAX_VBS);
3325 for (uint32_t i = 0; i < bindingCount; i++) {
3326 uint32_t idx = firstBinding + i;
3327
3328 if (!changed &&
3329 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3330 vb[idx].offset != pOffsets[i])) {
3331 changed = true;
3332 }
3333
3334 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3335 vb[idx].offset = pOffsets[i];
3336
3337 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3338 vb[idx].buffer->bo);
3339 }
3340
3341 if (!changed) {
3342 /* No state changes. */
3343 return;
3344 }
3345
3346 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3347 }
3348
3349 static uint32_t
3350 vk_to_index_type(VkIndexType type)
3351 {
3352 switch (type) {
3353 case VK_INDEX_TYPE_UINT8_EXT:
3354 return V_028A7C_VGT_INDEX_8;
3355 case VK_INDEX_TYPE_UINT16:
3356 return V_028A7C_VGT_INDEX_16;
3357 case VK_INDEX_TYPE_UINT32:
3358 return V_028A7C_VGT_INDEX_32;
3359 default:
3360 unreachable("invalid index type");
3361 }
3362 }
3363
3364 static uint32_t
3365 radv_get_vgt_index_size(uint32_t type)
3366 {
3367 switch (type) {
3368 case V_028A7C_VGT_INDEX_8:
3369 return 1;
3370 case V_028A7C_VGT_INDEX_16:
3371 return 2;
3372 case V_028A7C_VGT_INDEX_32:
3373 return 4;
3374 default:
3375 unreachable("invalid index type");
3376 }
3377 }
3378
3379 void radv_CmdBindIndexBuffer(
3380 VkCommandBuffer commandBuffer,
3381 VkBuffer buffer,
3382 VkDeviceSize offset,
3383 VkIndexType indexType)
3384 {
3385 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3386 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3387
3388 if (cmd_buffer->state.index_buffer == index_buffer &&
3389 cmd_buffer->state.index_offset == offset &&
3390 cmd_buffer->state.index_type == indexType) {
3391 /* No state changes. */
3392 return;
3393 }
3394
3395 cmd_buffer->state.index_buffer = index_buffer;
3396 cmd_buffer->state.index_offset = offset;
3397 cmd_buffer->state.index_type = vk_to_index_type(indexType);
3398 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3399 cmd_buffer->state.index_va += index_buffer->offset + offset;
3400
3401 int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
3402 cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
3403 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3404 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3405 }
3406
3407
3408 static void
3409 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3410 VkPipelineBindPoint bind_point,
3411 struct radv_descriptor_set *set, unsigned idx)
3412 {
3413 struct radeon_winsys *ws = cmd_buffer->device->ws;
3414
3415 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3416
3417 assert(set);
3418 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3419
3420 if (!cmd_buffer->device->use_global_bo_list) {
3421 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3422 if (set->descriptors[j])
3423 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3424 }
3425
3426 if(set->bo)
3427 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3428 }
3429
3430 void radv_CmdBindDescriptorSets(
3431 VkCommandBuffer commandBuffer,
3432 VkPipelineBindPoint pipelineBindPoint,
3433 VkPipelineLayout _layout,
3434 uint32_t firstSet,
3435 uint32_t descriptorSetCount,
3436 const VkDescriptorSet* pDescriptorSets,
3437 uint32_t dynamicOffsetCount,
3438 const uint32_t* pDynamicOffsets)
3439 {
3440 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3441 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3442 unsigned dyn_idx = 0;
3443
3444 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3445 struct radv_descriptor_state *descriptors_state =
3446 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3447
3448 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3449 unsigned idx = i + firstSet;
3450 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3451
3452 /* If the set is already bound we only need to update the
3453 * (potentially changed) dynamic offsets. */
3454 if (descriptors_state->sets[idx] != set ||
3455 !(descriptors_state->valid & (1u << idx))) {
3456 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3457 }
3458
3459 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3460 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3461 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3462 assert(dyn_idx < dynamicOffsetCount);
3463
3464 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3465 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3466 dst[0] = va;
3467 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3468 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3469 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3470 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3471 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3472 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3473
3474 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3475 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3476 S_008F0C_OOB_SELECT(3) |
3477 S_008F0C_RESOURCE_LEVEL(1);
3478 } else {
3479 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3480 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3481 }
3482
3483 cmd_buffer->push_constant_stages |=
3484 set->layout->dynamic_shader_stages;
3485 }
3486 }
3487 }
3488
3489 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3490 struct radv_descriptor_set *set,
3491 struct radv_descriptor_set_layout *layout,
3492 VkPipelineBindPoint bind_point)
3493 {
3494 struct radv_descriptor_state *descriptors_state =
3495 radv_get_descriptors_state(cmd_buffer, bind_point);
3496 set->size = layout->size;
3497 set->layout = layout;
3498
3499 if (descriptors_state->push_set.capacity < set->size) {
3500 size_t new_size = MAX2(set->size, 1024);
3501 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3502 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3503
3504 free(set->mapped_ptr);
3505 set->mapped_ptr = malloc(new_size);
3506
3507 if (!set->mapped_ptr) {
3508 descriptors_state->push_set.capacity = 0;
3509 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3510 return false;
3511 }
3512
3513 descriptors_state->push_set.capacity = new_size;
3514 }
3515
3516 return true;
3517 }
3518
3519 void radv_meta_push_descriptor_set(
3520 struct radv_cmd_buffer* cmd_buffer,
3521 VkPipelineBindPoint pipelineBindPoint,
3522 VkPipelineLayout _layout,
3523 uint32_t set,
3524 uint32_t descriptorWriteCount,
3525 const VkWriteDescriptorSet* pDescriptorWrites)
3526 {
3527 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3528 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3529 unsigned bo_offset;
3530
3531 assert(set == 0);
3532 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3533
3534 push_set->size = layout->set[set].layout->size;
3535 push_set->layout = layout->set[set].layout;
3536
3537 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3538 &bo_offset,
3539 (void**) &push_set->mapped_ptr))
3540 return;
3541
3542 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3543 push_set->va += bo_offset;
3544
3545 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3546 radv_descriptor_set_to_handle(push_set),
3547 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3548
3549 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3550 }
3551
3552 void radv_CmdPushDescriptorSetKHR(
3553 VkCommandBuffer commandBuffer,
3554 VkPipelineBindPoint pipelineBindPoint,
3555 VkPipelineLayout _layout,
3556 uint32_t set,
3557 uint32_t descriptorWriteCount,
3558 const VkWriteDescriptorSet* pDescriptorWrites)
3559 {
3560 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3561 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3562 struct radv_descriptor_state *descriptors_state =
3563 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3564 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3565
3566 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3567
3568 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3569 layout->set[set].layout,
3570 pipelineBindPoint))
3571 return;
3572
3573 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3574 * because it is invalid, according to Vulkan spec.
3575 */
3576 for (int i = 0; i < descriptorWriteCount; i++) {
3577 ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3578 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3579 }
3580
3581 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3582 radv_descriptor_set_to_handle(push_set),
3583 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3584
3585 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3586 descriptors_state->push_dirty = true;
3587 }
3588
3589 void radv_CmdPushDescriptorSetWithTemplateKHR(
3590 VkCommandBuffer commandBuffer,
3591 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3592 VkPipelineLayout _layout,
3593 uint32_t set,
3594 const void* pData)
3595 {
3596 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3597 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3598 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3599 struct radv_descriptor_state *descriptors_state =
3600 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3601 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3602
3603 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3604
3605 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3606 layout->set[set].layout,
3607 templ->bind_point))
3608 return;
3609
3610 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3611 descriptorUpdateTemplate, pData);
3612
3613 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3614 descriptors_state->push_dirty = true;
3615 }
3616
3617 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3618 VkPipelineLayout layout,
3619 VkShaderStageFlags stageFlags,
3620 uint32_t offset,
3621 uint32_t size,
3622 const void* pValues)
3623 {
3624 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3625 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3626 cmd_buffer->push_constant_stages |= stageFlags;
3627 }
3628
3629 VkResult radv_EndCommandBuffer(
3630 VkCommandBuffer commandBuffer)
3631 {
3632 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3633
3634 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3635 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3636 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3637
3638 /* Make sure to sync all pending active queries at the end of
3639 * command buffer.
3640 */
3641 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3642
3643 /* Since NGG streamout uses GDS, we need to make GDS idle when
3644 * we leave the IB, otherwise another process might overwrite
3645 * it while our shaders are busy.
3646 */
3647 if (cmd_buffer->gds_needed)
3648 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
3649
3650 si_emit_cache_flush(cmd_buffer);
3651 }
3652
3653 /* Make sure CP DMA is idle at the end of IBs because the kernel
3654 * doesn't wait for it.
3655 */
3656 si_cp_dma_wait_for_idle(cmd_buffer);
3657
3658 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3659 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3660
3661 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3662 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3663
3664 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3665
3666 return cmd_buffer->record_result;
3667 }
3668
3669 static void
3670 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3671 {
3672 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3673
3674 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3675 return;
3676
3677 assert(!pipeline->ctx_cs.cdw);
3678
3679 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3680
3681 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3682 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3683
3684 cmd_buffer->compute_scratch_size_per_wave_needed = MAX2(cmd_buffer->compute_scratch_size_per_wave_needed,
3685 pipeline->scratch_bytes_per_wave);
3686 cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted,
3687 pipeline->max_waves);
3688
3689 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3690 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3691
3692 if (unlikely(cmd_buffer->device->trace_bo))
3693 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3694 }
3695
3696 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3697 VkPipelineBindPoint bind_point)
3698 {
3699 struct radv_descriptor_state *descriptors_state =
3700 radv_get_descriptors_state(cmd_buffer, bind_point);
3701
3702 descriptors_state->dirty |= descriptors_state->valid;
3703 }
3704
3705 void radv_CmdBindPipeline(
3706 VkCommandBuffer commandBuffer,
3707 VkPipelineBindPoint pipelineBindPoint,
3708 VkPipeline _pipeline)
3709 {
3710 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3711 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3712
3713 switch (pipelineBindPoint) {
3714 case VK_PIPELINE_BIND_POINT_COMPUTE:
3715 if (cmd_buffer->state.compute_pipeline == pipeline)
3716 return;
3717 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3718
3719 cmd_buffer->state.compute_pipeline = pipeline;
3720 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3721 break;
3722 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3723 if (cmd_buffer->state.pipeline == pipeline)
3724 return;
3725 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3726
3727 cmd_buffer->state.pipeline = pipeline;
3728 if (!pipeline)
3729 break;
3730
3731 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3732 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3733
3734 /* the new vertex shader might not have the same user regs */
3735 cmd_buffer->state.last_first_instance = -1;
3736 cmd_buffer->state.last_vertex_offset = -1;
3737
3738 /* Prefetch all pipeline shaders at first draw time. */
3739 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3740
3741 if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3742 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3743 cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3744 cmd_buffer->state.emitted_pipeline &&
3745 radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
3746 !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {
3747 /* Transitioning from NGG to legacy GS requires
3748 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
3749 * at the beginning of IBs when legacy GS ring pointers
3750 * are set.
3751 */
3752 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
3753 }
3754
3755 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3756 radv_bind_streamout_state(cmd_buffer, pipeline);
3757
3758 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3759 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3760 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3761 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3762
3763 if (radv_pipeline_has_tess(pipeline))
3764 cmd_buffer->tess_rings_needed = true;
3765 break;
3766 default:
3767 assert(!"invalid bind point");
3768 break;
3769 }
3770 }
3771
3772 void radv_CmdSetViewport(
3773 VkCommandBuffer commandBuffer,
3774 uint32_t firstViewport,
3775 uint32_t viewportCount,
3776 const VkViewport* pViewports)
3777 {
3778 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3779 struct radv_cmd_state *state = &cmd_buffer->state;
3780 ASSERTED const uint32_t total_count = firstViewport + viewportCount;
3781
3782 assert(firstViewport < MAX_VIEWPORTS);
3783 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3784
3785 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3786 pViewports, viewportCount * sizeof(*pViewports))) {
3787 return;
3788 }
3789
3790 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3791 viewportCount * sizeof(*pViewports));
3792
3793 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3794 }
3795
3796 void radv_CmdSetScissor(
3797 VkCommandBuffer commandBuffer,
3798 uint32_t firstScissor,
3799 uint32_t scissorCount,
3800 const VkRect2D* pScissors)
3801 {
3802 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3803 struct radv_cmd_state *state = &cmd_buffer->state;
3804 ASSERTED const uint32_t total_count = firstScissor + scissorCount;
3805
3806 assert(firstScissor < MAX_SCISSORS);
3807 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3808
3809 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3810 scissorCount * sizeof(*pScissors))) {
3811 return;
3812 }
3813
3814 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3815 scissorCount * sizeof(*pScissors));
3816
3817 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3818 }
3819
3820 void radv_CmdSetLineWidth(
3821 VkCommandBuffer commandBuffer,
3822 float lineWidth)
3823 {
3824 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3825
3826 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3827 return;
3828
3829 cmd_buffer->state.dynamic.line_width = lineWidth;
3830 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3831 }
3832
3833 void radv_CmdSetDepthBias(
3834 VkCommandBuffer commandBuffer,
3835 float depthBiasConstantFactor,
3836 float depthBiasClamp,
3837 float depthBiasSlopeFactor)
3838 {
3839 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3840 struct radv_cmd_state *state = &cmd_buffer->state;
3841
3842 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3843 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3844 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3845 return;
3846 }
3847
3848 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3849 state->dynamic.depth_bias.clamp = depthBiasClamp;
3850 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3851
3852 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3853 }
3854
3855 void radv_CmdSetBlendConstants(
3856 VkCommandBuffer commandBuffer,
3857 const float blendConstants[4])
3858 {
3859 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3860 struct radv_cmd_state *state = &cmd_buffer->state;
3861
3862 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3863 return;
3864
3865 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3866
3867 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3868 }
3869
3870 void radv_CmdSetDepthBounds(
3871 VkCommandBuffer commandBuffer,
3872 float minDepthBounds,
3873 float maxDepthBounds)
3874 {
3875 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3876 struct radv_cmd_state *state = &cmd_buffer->state;
3877
3878 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3879 state->dynamic.depth_bounds.max == maxDepthBounds) {
3880 return;
3881 }
3882
3883 state->dynamic.depth_bounds.min = minDepthBounds;
3884 state->dynamic.depth_bounds.max = maxDepthBounds;
3885
3886 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3887 }
3888
3889 void radv_CmdSetStencilCompareMask(
3890 VkCommandBuffer commandBuffer,
3891 VkStencilFaceFlags faceMask,
3892 uint32_t compareMask)
3893 {
3894 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3895 struct radv_cmd_state *state = &cmd_buffer->state;
3896 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3897 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3898
3899 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3900 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3901 return;
3902 }
3903
3904 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3905 state->dynamic.stencil_compare_mask.front = compareMask;
3906 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3907 state->dynamic.stencil_compare_mask.back = compareMask;
3908
3909 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3910 }
3911
3912 void radv_CmdSetStencilWriteMask(
3913 VkCommandBuffer commandBuffer,
3914 VkStencilFaceFlags faceMask,
3915 uint32_t writeMask)
3916 {
3917 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3918 struct radv_cmd_state *state = &cmd_buffer->state;
3919 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3920 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3921
3922 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3923 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3924 return;
3925 }
3926
3927 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3928 state->dynamic.stencil_write_mask.front = writeMask;
3929 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3930 state->dynamic.stencil_write_mask.back = writeMask;
3931
3932 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3933 }
3934
3935 void radv_CmdSetStencilReference(
3936 VkCommandBuffer commandBuffer,
3937 VkStencilFaceFlags faceMask,
3938 uint32_t reference)
3939 {
3940 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3941 struct radv_cmd_state *state = &cmd_buffer->state;
3942 bool front_same = state->dynamic.stencil_reference.front == reference;
3943 bool back_same = state->dynamic.stencil_reference.back == reference;
3944
3945 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3946 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3947 return;
3948 }
3949
3950 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3951 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3952 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3953 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3954
3955 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3956 }
3957
3958 void radv_CmdSetDiscardRectangleEXT(
3959 VkCommandBuffer commandBuffer,
3960 uint32_t firstDiscardRectangle,
3961 uint32_t discardRectangleCount,
3962 const VkRect2D* pDiscardRectangles)
3963 {
3964 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3965 struct radv_cmd_state *state = &cmd_buffer->state;
3966 ASSERTED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3967
3968 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3969 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3970
3971 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3972 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3973 return;
3974 }
3975
3976 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3977 pDiscardRectangles, discardRectangleCount);
3978
3979 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3980 }
3981
3982 void radv_CmdSetSampleLocationsEXT(
3983 VkCommandBuffer commandBuffer,
3984 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3985 {
3986 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3987 struct radv_cmd_state *state = &cmd_buffer->state;
3988
3989 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3990
3991 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3992 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3993 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3994 typed_memcpy(&state->dynamic.sample_location.locations[0],
3995 pSampleLocationsInfo->pSampleLocations,
3996 pSampleLocationsInfo->sampleLocationsCount);
3997
3998 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3999 }
4000
4001 void radv_CmdExecuteCommands(
4002 VkCommandBuffer commandBuffer,
4003 uint32_t commandBufferCount,
4004 const VkCommandBuffer* pCmdBuffers)
4005 {
4006 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
4007
4008 assert(commandBufferCount > 0);
4009
4010 /* Emit pending flushes on primary prior to executing secondary */
4011 si_emit_cache_flush(primary);
4012
4013 for (uint32_t i = 0; i < commandBufferCount; i++) {
4014 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
4015
4016 primary->scratch_size_per_wave_needed = MAX2(primary->scratch_size_per_wave_needed,
4017 secondary->scratch_size_per_wave_needed);
4018 primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted,
4019 secondary->scratch_waves_wanted);
4020 primary->compute_scratch_size_per_wave_needed = MAX2(primary->compute_scratch_size_per_wave_needed,
4021 secondary->compute_scratch_size_per_wave_needed);
4022 primary->compute_scratch_waves_wanted = MAX2(primary->compute_scratch_waves_wanted,
4023 secondary->compute_scratch_waves_wanted);
4024
4025 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
4026 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
4027 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
4028 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
4029 if (secondary->tess_rings_needed)
4030 primary->tess_rings_needed = true;
4031 if (secondary->sample_positions_needed)
4032 primary->sample_positions_needed = true;
4033
4034 if (!secondary->state.framebuffer &&
4035 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
4036 /* Emit the framebuffer state from primary if secondary
4037 * has been recorded without a framebuffer, otherwise
4038 * fast color/depth clears can't work.
4039 */
4040 radv_emit_framebuffer_state(primary);
4041 }
4042
4043 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
4044
4045
4046 /* When the secondary command buffer is compute only we don't
4047 * need to re-emit the current graphics pipeline.
4048 */
4049 if (secondary->state.emitted_pipeline) {
4050 primary->state.emitted_pipeline =
4051 secondary->state.emitted_pipeline;
4052 }
4053
4054 /* When the secondary command buffer is graphics only we don't
4055 * need to re-emit the current compute pipeline.
4056 */
4057 if (secondary->state.emitted_compute_pipeline) {
4058 primary->state.emitted_compute_pipeline =
4059 secondary->state.emitted_compute_pipeline;
4060 }
4061
4062 /* Only re-emit the draw packets when needed. */
4063 if (secondary->state.last_primitive_reset_en != -1) {
4064 primary->state.last_primitive_reset_en =
4065 secondary->state.last_primitive_reset_en;
4066 }
4067
4068 if (secondary->state.last_primitive_reset_index) {
4069 primary->state.last_primitive_reset_index =
4070 secondary->state.last_primitive_reset_index;
4071 }
4072
4073 if (secondary->state.last_ia_multi_vgt_param) {
4074 primary->state.last_ia_multi_vgt_param =
4075 secondary->state.last_ia_multi_vgt_param;
4076 }
4077
4078 primary->state.last_first_instance = secondary->state.last_first_instance;
4079 primary->state.last_num_instances = secondary->state.last_num_instances;
4080 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
4081
4082 if (secondary->state.last_index_type != -1) {
4083 primary->state.last_index_type =
4084 secondary->state.last_index_type;
4085 }
4086 }
4087
4088 /* After executing commands from secondary buffers we have to dirty
4089 * some states.
4090 */
4091 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
4092 RADV_CMD_DIRTY_INDEX_BUFFER |
4093 RADV_CMD_DIRTY_DYNAMIC_ALL;
4094 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
4095 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
4096 }
4097
4098 VkResult radv_CreateCommandPool(
4099 VkDevice _device,
4100 const VkCommandPoolCreateInfo* pCreateInfo,
4101 const VkAllocationCallbacks* pAllocator,
4102 VkCommandPool* pCmdPool)
4103 {
4104 RADV_FROM_HANDLE(radv_device, device, _device);
4105 struct radv_cmd_pool *pool;
4106
4107 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
4108 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4109 if (pool == NULL)
4110 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4111
4112 if (pAllocator)
4113 pool->alloc = *pAllocator;
4114 else
4115 pool->alloc = device->alloc;
4116
4117 list_inithead(&pool->cmd_buffers);
4118 list_inithead(&pool->free_cmd_buffers);
4119
4120 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
4121
4122 *pCmdPool = radv_cmd_pool_to_handle(pool);
4123
4124 return VK_SUCCESS;
4125
4126 }
4127
4128 void radv_DestroyCommandPool(
4129 VkDevice _device,
4130 VkCommandPool commandPool,
4131 const VkAllocationCallbacks* pAllocator)
4132 {
4133 RADV_FROM_HANDLE(radv_device, device, _device);
4134 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4135
4136 if (!pool)
4137 return;
4138
4139 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4140 &pool->cmd_buffers, pool_link) {
4141 radv_cmd_buffer_destroy(cmd_buffer);
4142 }
4143
4144 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4145 &pool->free_cmd_buffers, pool_link) {
4146 radv_cmd_buffer_destroy(cmd_buffer);
4147 }
4148
4149 vk_free2(&device->alloc, pAllocator, pool);
4150 }
4151
4152 VkResult radv_ResetCommandPool(
4153 VkDevice device,
4154 VkCommandPool commandPool,
4155 VkCommandPoolResetFlags flags)
4156 {
4157 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4158 VkResult result;
4159
4160 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
4161 &pool->cmd_buffers, pool_link) {
4162 result = radv_reset_cmd_buffer(cmd_buffer);
4163 if (result != VK_SUCCESS)
4164 return result;
4165 }
4166
4167 return VK_SUCCESS;
4168 }
4169
4170 void radv_TrimCommandPool(
4171 VkDevice device,
4172 VkCommandPool commandPool,
4173 VkCommandPoolTrimFlags flags)
4174 {
4175 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
4176
4177 if (!pool)
4178 return;
4179
4180 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
4181 &pool->free_cmd_buffers, pool_link) {
4182 radv_cmd_buffer_destroy(cmd_buffer);
4183 }
4184 }
4185
4186 static void
4187 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
4188 uint32_t subpass_id)
4189 {
4190 struct radv_cmd_state *state = &cmd_buffer->state;
4191 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
4192
4193 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
4194 cmd_buffer->cs, 4096);
4195
4196 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
4197
4198 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
4199
4200 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4201 const uint32_t a = subpass->attachments[i].attachment;
4202 if (a == VK_ATTACHMENT_UNUSED)
4203 continue;
4204
4205 radv_handle_subpass_image_transition(cmd_buffer,
4206 subpass->attachments[i],
4207 true);
4208 }
4209
4210 radv_cmd_buffer_clear_subpass(cmd_buffer);
4211
4212 assert(cmd_buffer->cs->cdw <= cdw_max);
4213 }
4214
4215 static void
4216 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
4217 {
4218 struct radv_cmd_state *state = &cmd_buffer->state;
4219 const struct radv_subpass *subpass = state->subpass;
4220 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
4221
4222 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4223
4224 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4225 const uint32_t a = subpass->attachments[i].attachment;
4226 if (a == VK_ATTACHMENT_UNUSED)
4227 continue;
4228
4229 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4230 continue;
4231
4232 VkImageLayout layout = state->pass->attachments[a].final_layout;
4233 struct radv_subpass_attachment att = { a, layout };
4234 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4235 }
4236 }
4237
4238 void radv_CmdBeginRenderPass(
4239 VkCommandBuffer commandBuffer,
4240 const VkRenderPassBeginInfo* pRenderPassBegin,
4241 VkSubpassContents contents)
4242 {
4243 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4244 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4245 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4246 VkResult result;
4247
4248 cmd_buffer->state.framebuffer = framebuffer;
4249 cmd_buffer->state.pass = pass;
4250 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4251
4252 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4253 if (result != VK_SUCCESS)
4254 return;
4255
4256 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4257 if (result != VK_SUCCESS)
4258 return;
4259
4260 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4261 }
4262
4263 void radv_CmdBeginRenderPass2KHR(
4264 VkCommandBuffer commandBuffer,
4265 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4266 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4267 {
4268 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4269 pSubpassBeginInfo->contents);
4270 }
4271
4272 void radv_CmdNextSubpass(
4273 VkCommandBuffer commandBuffer,
4274 VkSubpassContents contents)
4275 {
4276 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4277
4278 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4279 radv_cmd_buffer_end_subpass(cmd_buffer);
4280 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4281 }
4282
4283 void radv_CmdNextSubpass2KHR(
4284 VkCommandBuffer commandBuffer,
4285 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4286 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4287 {
4288 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4289 }
4290
4291 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4292 {
4293 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4294 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4295 if (!radv_get_shader(pipeline, stage))
4296 continue;
4297
4298 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4299 if (loc->sgpr_idx == -1)
4300 continue;
4301 uint32_t base_reg = pipeline->user_data_0[stage];
4302 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4303
4304 }
4305 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4306 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4307 if (loc->sgpr_idx != -1) {
4308 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4309 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4310 }
4311 }
4312 }
4313
4314 static void
4315 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4316 uint32_t vertex_count,
4317 bool use_opaque)
4318 {
4319 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4320 radeon_emit(cmd_buffer->cs, vertex_count);
4321 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4322 S_0287F0_USE_OPAQUE(use_opaque));
4323 }
4324
4325 static void
4326 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4327 uint64_t index_va,
4328 uint32_t index_count)
4329 {
4330 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4331 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4332 radeon_emit(cmd_buffer->cs, index_va);
4333 radeon_emit(cmd_buffer->cs, index_va >> 32);
4334 radeon_emit(cmd_buffer->cs, index_count);
4335 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4336 }
4337
4338 static void
4339 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4340 bool indexed,
4341 uint32_t draw_count,
4342 uint64_t count_va,
4343 uint32_t stride)
4344 {
4345 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4346 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4347 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4348 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id;
4349 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4350 bool predicating = cmd_buffer->state.predicating;
4351 assert(base_reg);
4352
4353 /* just reset draw state for vertex data */
4354 cmd_buffer->state.last_first_instance = -1;
4355 cmd_buffer->state.last_num_instances = -1;
4356 cmd_buffer->state.last_vertex_offset = -1;
4357
4358 if (draw_count == 1 && !count_va && !draw_id_enable) {
4359 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4360 PKT3_DRAW_INDIRECT, 3, predicating));
4361 radeon_emit(cs, 0);
4362 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4363 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4364 radeon_emit(cs, di_src_sel);
4365 } else {
4366 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4367 PKT3_DRAW_INDIRECT_MULTI,
4368 8, predicating));
4369 radeon_emit(cs, 0);
4370 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4371 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4372 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4373 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4374 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4375 radeon_emit(cs, draw_count); /* count */
4376 radeon_emit(cs, count_va); /* count_addr */
4377 radeon_emit(cs, count_va >> 32);
4378 radeon_emit(cs, stride); /* stride */
4379 radeon_emit(cs, di_src_sel);
4380 }
4381 }
4382
4383 static void
4384 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4385 const struct radv_draw_info *info)
4386 {
4387 struct radv_cmd_state *state = &cmd_buffer->state;
4388 struct radeon_winsys *ws = cmd_buffer->device->ws;
4389 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4390
4391 if (info->indirect) {
4392 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4393 uint64_t count_va = 0;
4394
4395 va += info->indirect->offset + info->indirect_offset;
4396
4397 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4398
4399 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4400 radeon_emit(cs, 1);
4401 radeon_emit(cs, va);
4402 radeon_emit(cs, va >> 32);
4403
4404 if (info->count_buffer) {
4405 count_va = radv_buffer_get_va(info->count_buffer->bo);
4406 count_va += info->count_buffer->offset +
4407 info->count_buffer_offset;
4408
4409 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4410 }
4411
4412 if (!state->subpass->view_mask) {
4413 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4414 info->indexed,
4415 info->count,
4416 count_va,
4417 info->stride);
4418 } else {
4419 unsigned i;
4420 for_each_bit(i, state->subpass->view_mask) {
4421 radv_emit_view_index(cmd_buffer, i);
4422
4423 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4424 info->indexed,
4425 info->count,
4426 count_va,
4427 info->stride);
4428 }
4429 }
4430 } else {
4431 assert(state->pipeline->graphics.vtx_base_sgpr);
4432
4433 if (info->vertex_offset != state->last_vertex_offset ||
4434 info->first_instance != state->last_first_instance) {
4435 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4436 state->pipeline->graphics.vtx_emit_num);
4437
4438 radeon_emit(cs, info->vertex_offset);
4439 radeon_emit(cs, info->first_instance);
4440 if (state->pipeline->graphics.vtx_emit_num == 3)
4441 radeon_emit(cs, 0);
4442 state->last_first_instance = info->first_instance;
4443 state->last_vertex_offset = info->vertex_offset;
4444 }
4445
4446 if (state->last_num_instances != info->instance_count) {
4447 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4448 radeon_emit(cs, info->instance_count);
4449 state->last_num_instances = info->instance_count;
4450 }
4451
4452 if (info->indexed) {
4453 int index_size = radv_get_vgt_index_size(state->index_type);
4454 uint64_t index_va;
4455
4456 /* Skip draw calls with 0-sized index buffers. They
4457 * cause a hang on some chips, like Navi10-14.
4458 */
4459 if (!cmd_buffer->state.max_index_count)
4460 return;
4461
4462 index_va = state->index_va;
4463 index_va += info->first_index * index_size;
4464
4465 if (!state->subpass->view_mask) {
4466 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4467 index_va,
4468 info->count);
4469 } else {
4470 unsigned i;
4471 for_each_bit(i, state->subpass->view_mask) {
4472 radv_emit_view_index(cmd_buffer, i);
4473
4474 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4475 index_va,
4476 info->count);
4477 }
4478 }
4479 } else {
4480 if (!state->subpass->view_mask) {
4481 radv_cs_emit_draw_packet(cmd_buffer,
4482 info->count,
4483 !!info->strmout_buffer);
4484 } else {
4485 unsigned i;
4486 for_each_bit(i, state->subpass->view_mask) {
4487 radv_emit_view_index(cmd_buffer, i);
4488
4489 radv_cs_emit_draw_packet(cmd_buffer,
4490 info->count,
4491 !!info->strmout_buffer);
4492 }
4493 }
4494 }
4495 }
4496 }
4497
4498 /*
4499 * Vega and raven have a bug which triggers if there are multiple context
4500 * register contexts active at the same time with different scissor values.
4501 *
4502 * There are two possible workarounds:
4503 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4504 * there is only ever 1 active set of scissor values at the same time.
4505 *
4506 * 2) Whenever the hardware switches contexts we have to set the scissor
4507 * registers again even if it is a noop. That way the new context gets
4508 * the correct scissor values.
4509 *
4510 * This implements option 2. radv_need_late_scissor_emission needs to
4511 * return true on affected HW if radv_emit_all_graphics_states sets
4512 * any context registers.
4513 */
4514 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4515 const struct radv_draw_info *info)
4516 {
4517 struct radv_cmd_state *state = &cmd_buffer->state;
4518
4519 if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)
4520 return false;
4521
4522 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4523 return true;
4524
4525 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4526
4527 /* Index, vertex and streamout buffers don't change context regs, and
4528 * pipeline is already handled.
4529 */
4530 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4531 RADV_CMD_DIRTY_VERTEX_BUFFER |
4532 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4533 RADV_CMD_DIRTY_PIPELINE);
4534
4535 if (cmd_buffer->state.dirty & used_states)
4536 return true;
4537
4538 uint32_t primitive_reset_index =
4539 radv_get_primitive_reset_index(cmd_buffer);
4540
4541 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4542 primitive_reset_index != state->last_primitive_reset_index)
4543 return true;
4544
4545 return false;
4546 }
4547
4548 static void
4549 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4550 const struct radv_draw_info *info)
4551 {
4552 bool late_scissor_emission;
4553
4554 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4555 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4556 radv_emit_rbplus_state(cmd_buffer);
4557
4558 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4559 radv_emit_graphics_pipeline(cmd_buffer);
4560
4561 /* This should be before the cmd_buffer->state.dirty is cleared
4562 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4563 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4564 late_scissor_emission =
4565 radv_need_late_scissor_emission(cmd_buffer, info);
4566
4567 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4568 radv_emit_framebuffer_state(cmd_buffer);
4569
4570 if (info->indexed) {
4571 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4572 radv_emit_index_buffer(cmd_buffer);
4573 } else {
4574 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4575 * so the state must be re-emitted before the next indexed
4576 * draw.
4577 */
4578 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4579 cmd_buffer->state.last_index_type = -1;
4580 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4581 }
4582 }
4583
4584 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4585
4586 radv_emit_draw_registers(cmd_buffer, info);
4587
4588 if (late_scissor_emission)
4589 radv_emit_scissor(cmd_buffer);
4590 }
4591
4592 static void
4593 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4594 const struct radv_draw_info *info)
4595 {
4596 struct radeon_info *rad_info =
4597 &cmd_buffer->device->physical_device->rad_info;
4598 bool has_prefetch =
4599 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4600 bool pipeline_is_dirty =
4601 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4602 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4603
4604 ASSERTED unsigned cdw_max =
4605 radeon_check_space(cmd_buffer->device->ws,
4606 cmd_buffer->cs, 4096);
4607
4608 if (likely(!info->indirect)) {
4609 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4610 * no workaround for indirect draws, but we can at least skip
4611 * direct draws.
4612 */
4613 if (unlikely(!info->instance_count))
4614 return;
4615
4616 /* Handle count == 0. */
4617 if (unlikely(!info->count && !info->strmout_buffer))
4618 return;
4619 }
4620
4621 /* Use optimal packet order based on whether we need to sync the
4622 * pipeline.
4623 */
4624 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4625 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4626 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4627 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4628 /* If we have to wait for idle, set all states first, so that
4629 * all SET packets are processed in parallel with previous draw
4630 * calls. Then upload descriptors, set shader pointers, and
4631 * draw, and prefetch at the end. This ensures that the time
4632 * the CUs are idle is very short. (there are only SET_SH
4633 * packets between the wait and the draw)
4634 */
4635 radv_emit_all_graphics_states(cmd_buffer, info);
4636 si_emit_cache_flush(cmd_buffer);
4637 /* <-- CUs are idle here --> */
4638
4639 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4640
4641 radv_emit_draw_packets(cmd_buffer, info);
4642 /* <-- CUs are busy here --> */
4643
4644 /* Start prefetches after the draw has been started. Both will
4645 * run in parallel, but starting the draw first is more
4646 * important.
4647 */
4648 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4649 radv_emit_prefetch_L2(cmd_buffer,
4650 cmd_buffer->state.pipeline, false);
4651 }
4652 } else {
4653 /* If we don't wait for idle, start prefetches first, then set
4654 * states, and draw at the end.
4655 */
4656 si_emit_cache_flush(cmd_buffer);
4657
4658 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4659 /* Only prefetch the vertex shader and VBO descriptors
4660 * in order to start the draw as soon as possible.
4661 */
4662 radv_emit_prefetch_L2(cmd_buffer,
4663 cmd_buffer->state.pipeline, true);
4664 }
4665
4666 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4667
4668 radv_emit_all_graphics_states(cmd_buffer, info);
4669 radv_emit_draw_packets(cmd_buffer, info);
4670
4671 /* Prefetch the remaining shaders after the draw has been
4672 * started.
4673 */
4674 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4675 radv_emit_prefetch_L2(cmd_buffer,
4676 cmd_buffer->state.pipeline, false);
4677 }
4678 }
4679
4680 /* Workaround for a VGT hang when streamout is enabled.
4681 * It must be done after drawing.
4682 */
4683 if (cmd_buffer->state.streamout.streamout_enabled &&
4684 (rad_info->family == CHIP_HAWAII ||
4685 rad_info->family == CHIP_TONGA ||
4686 rad_info->family == CHIP_FIJI)) {
4687 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4688 }
4689
4690 assert(cmd_buffer->cs->cdw <= cdw_max);
4691 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4692 }
4693
4694 void radv_CmdDraw(
4695 VkCommandBuffer commandBuffer,
4696 uint32_t vertexCount,
4697 uint32_t instanceCount,
4698 uint32_t firstVertex,
4699 uint32_t firstInstance)
4700 {
4701 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4702 struct radv_draw_info info = {};
4703
4704 info.count = vertexCount;
4705 info.instance_count = instanceCount;
4706 info.first_instance = firstInstance;
4707 info.vertex_offset = firstVertex;
4708
4709 radv_draw(cmd_buffer, &info);
4710 }
4711
4712 void radv_CmdDrawIndexed(
4713 VkCommandBuffer commandBuffer,
4714 uint32_t indexCount,
4715 uint32_t instanceCount,
4716 uint32_t firstIndex,
4717 int32_t vertexOffset,
4718 uint32_t firstInstance)
4719 {
4720 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4721 struct radv_draw_info info = {};
4722
4723 info.indexed = true;
4724 info.count = indexCount;
4725 info.instance_count = instanceCount;
4726 info.first_index = firstIndex;
4727 info.vertex_offset = vertexOffset;
4728 info.first_instance = firstInstance;
4729
4730 radv_draw(cmd_buffer, &info);
4731 }
4732
4733 void radv_CmdDrawIndirect(
4734 VkCommandBuffer commandBuffer,
4735 VkBuffer _buffer,
4736 VkDeviceSize offset,
4737 uint32_t drawCount,
4738 uint32_t stride)
4739 {
4740 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4741 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4742 struct radv_draw_info info = {};
4743
4744 info.count = drawCount;
4745 info.indirect = buffer;
4746 info.indirect_offset = offset;
4747 info.stride = stride;
4748
4749 radv_draw(cmd_buffer, &info);
4750 }
4751
4752 void radv_CmdDrawIndexedIndirect(
4753 VkCommandBuffer commandBuffer,
4754 VkBuffer _buffer,
4755 VkDeviceSize offset,
4756 uint32_t drawCount,
4757 uint32_t stride)
4758 {
4759 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4760 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4761 struct radv_draw_info info = {};
4762
4763 info.indexed = true;
4764 info.count = drawCount;
4765 info.indirect = buffer;
4766 info.indirect_offset = offset;
4767 info.stride = stride;
4768
4769 radv_draw(cmd_buffer, &info);
4770 }
4771
4772 void radv_CmdDrawIndirectCountKHR(
4773 VkCommandBuffer commandBuffer,
4774 VkBuffer _buffer,
4775 VkDeviceSize offset,
4776 VkBuffer _countBuffer,
4777 VkDeviceSize countBufferOffset,
4778 uint32_t maxDrawCount,
4779 uint32_t stride)
4780 {
4781 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4782 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4783 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4784 struct radv_draw_info info = {};
4785
4786 info.count = maxDrawCount;
4787 info.indirect = buffer;
4788 info.indirect_offset = offset;
4789 info.count_buffer = count_buffer;
4790 info.count_buffer_offset = countBufferOffset;
4791 info.stride = stride;
4792
4793 radv_draw(cmd_buffer, &info);
4794 }
4795
4796 void radv_CmdDrawIndexedIndirectCountKHR(
4797 VkCommandBuffer commandBuffer,
4798 VkBuffer _buffer,
4799 VkDeviceSize offset,
4800 VkBuffer _countBuffer,
4801 VkDeviceSize countBufferOffset,
4802 uint32_t maxDrawCount,
4803 uint32_t stride)
4804 {
4805 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4806 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4807 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4808 struct radv_draw_info info = {};
4809
4810 info.indexed = true;
4811 info.count = maxDrawCount;
4812 info.indirect = buffer;
4813 info.indirect_offset = offset;
4814 info.count_buffer = count_buffer;
4815 info.count_buffer_offset = countBufferOffset;
4816 info.stride = stride;
4817
4818 radv_draw(cmd_buffer, &info);
4819 }
4820
4821 struct radv_dispatch_info {
4822 /**
4823 * Determine the layout of the grid (in block units) to be used.
4824 */
4825 uint32_t blocks[3];
4826
4827 /**
4828 * A starting offset for the grid. If unaligned is set, the offset
4829 * must still be aligned.
4830 */
4831 uint32_t offsets[3];
4832 /**
4833 * Whether it's an unaligned compute dispatch.
4834 */
4835 bool unaligned;
4836
4837 /**
4838 * Indirect compute parameters resource.
4839 */
4840 struct radv_buffer *indirect;
4841 uint64_t indirect_offset;
4842 };
4843
4844 static void
4845 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4846 const struct radv_dispatch_info *info)
4847 {
4848 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4849 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4850 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4851 struct radeon_winsys *ws = cmd_buffer->device->ws;
4852 bool predicating = cmd_buffer->state.predicating;
4853 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4854 struct radv_userdata_info *loc;
4855
4856 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4857 AC_UD_CS_GRID_SIZE);
4858
4859 ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4860
4861 if (compute_shader->info.wave_size == 32) {
4862 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
4863 dispatch_initiator |= S_00B800_CS_W32_EN(1);
4864 }
4865
4866 if (info->indirect) {
4867 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4868
4869 va += info->indirect->offset + info->indirect_offset;
4870
4871 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4872
4873 if (loc->sgpr_idx != -1) {
4874 for (unsigned i = 0; i < 3; ++i) {
4875 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4876 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4877 COPY_DATA_DST_SEL(COPY_DATA_REG));
4878 radeon_emit(cs, (va + 4 * i));
4879 radeon_emit(cs, (va + 4 * i) >> 32);
4880 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4881 + loc->sgpr_idx * 4) >> 2) + i);
4882 radeon_emit(cs, 0);
4883 }
4884 }
4885
4886 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4887 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4888 PKT3_SHADER_TYPE_S(1));
4889 radeon_emit(cs, va);
4890 radeon_emit(cs, va >> 32);
4891 radeon_emit(cs, dispatch_initiator);
4892 } else {
4893 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4894 PKT3_SHADER_TYPE_S(1));
4895 radeon_emit(cs, 1);
4896 radeon_emit(cs, va);
4897 radeon_emit(cs, va >> 32);
4898
4899 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4900 PKT3_SHADER_TYPE_S(1));
4901 radeon_emit(cs, 0);
4902 radeon_emit(cs, dispatch_initiator);
4903 }
4904 } else {
4905 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4906 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4907
4908 if (info->unaligned) {
4909 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4910 unsigned remainder[3];
4911
4912 /* If aligned, these should be an entire block size,
4913 * not 0.
4914 */
4915 remainder[0] = blocks[0] + cs_block_size[0] -
4916 align_u32_npot(blocks[0], cs_block_size[0]);
4917 remainder[1] = blocks[1] + cs_block_size[1] -
4918 align_u32_npot(blocks[1], cs_block_size[1]);
4919 remainder[2] = blocks[2] + cs_block_size[2] -
4920 align_u32_npot(blocks[2], cs_block_size[2]);
4921
4922 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4923 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4924 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4925
4926 for(unsigned i = 0; i < 3; ++i) {
4927 assert(offsets[i] % cs_block_size[i] == 0);
4928 offsets[i] /= cs_block_size[i];
4929 }
4930
4931 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4932 radeon_emit(cs,
4933 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4934 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4935 radeon_emit(cs,
4936 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4937 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4938 radeon_emit(cs,
4939 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4940 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4941
4942 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4943 }
4944
4945 if (loc->sgpr_idx != -1) {
4946 assert(loc->num_sgprs == 3);
4947
4948 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4949 loc->sgpr_idx * 4, 3);
4950 radeon_emit(cs, blocks[0]);
4951 radeon_emit(cs, blocks[1]);
4952 radeon_emit(cs, blocks[2]);
4953 }
4954
4955 if (offsets[0] || offsets[1] || offsets[2]) {
4956 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4957 radeon_emit(cs, offsets[0]);
4958 radeon_emit(cs, offsets[1]);
4959 radeon_emit(cs, offsets[2]);
4960
4961 /* The blocks in the packet are not counts but end values. */
4962 for (unsigned i = 0; i < 3; ++i)
4963 blocks[i] += offsets[i];
4964 } else {
4965 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4966 }
4967
4968 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4969 PKT3_SHADER_TYPE_S(1));
4970 radeon_emit(cs, blocks[0]);
4971 radeon_emit(cs, blocks[1]);
4972 radeon_emit(cs, blocks[2]);
4973 radeon_emit(cs, dispatch_initiator);
4974 }
4975
4976 assert(cmd_buffer->cs->cdw <= cdw_max);
4977 }
4978
4979 static void
4980 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4981 {
4982 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4983 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4984 }
4985
4986 static void
4987 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4988 const struct radv_dispatch_info *info)
4989 {
4990 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4991 bool has_prefetch =
4992 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4993 bool pipeline_is_dirty = pipeline &&
4994 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4995
4996 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4997 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4998 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4999 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
5000 /* If we have to wait for idle, set all states first, so that
5001 * all SET packets are processed in parallel with previous draw
5002 * calls. Then upload descriptors, set shader pointers, and
5003 * dispatch, and prefetch at the end. This ensures that the
5004 * time the CUs are idle is very short. (there are only SET_SH
5005 * packets between the wait and the draw)
5006 */
5007 radv_emit_compute_pipeline(cmd_buffer);
5008 si_emit_cache_flush(cmd_buffer);
5009 /* <-- CUs are idle here --> */
5010
5011 radv_upload_compute_shader_descriptors(cmd_buffer);
5012
5013 radv_emit_dispatch_packets(cmd_buffer, info);
5014 /* <-- CUs are busy here --> */
5015
5016 /* Start prefetches after the dispatch has been started. Both
5017 * will run in parallel, but starting the dispatch first is
5018 * more important.
5019 */
5020 if (has_prefetch && pipeline_is_dirty) {
5021 radv_emit_shader_prefetch(cmd_buffer,
5022 pipeline->shaders[MESA_SHADER_COMPUTE]);
5023 }
5024 } else {
5025 /* If we don't wait for idle, start prefetches first, then set
5026 * states, and dispatch at the end.
5027 */
5028 si_emit_cache_flush(cmd_buffer);
5029
5030 if (has_prefetch && pipeline_is_dirty) {
5031 radv_emit_shader_prefetch(cmd_buffer,
5032 pipeline->shaders[MESA_SHADER_COMPUTE]);
5033 }
5034
5035 radv_upload_compute_shader_descriptors(cmd_buffer);
5036
5037 radv_emit_compute_pipeline(cmd_buffer);
5038 radv_emit_dispatch_packets(cmd_buffer, info);
5039 }
5040
5041 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
5042 }
5043
5044 void radv_CmdDispatchBase(
5045 VkCommandBuffer commandBuffer,
5046 uint32_t base_x,
5047 uint32_t base_y,
5048 uint32_t base_z,
5049 uint32_t x,
5050 uint32_t y,
5051 uint32_t z)
5052 {
5053 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5054 struct radv_dispatch_info info = {};
5055
5056 info.blocks[0] = x;
5057 info.blocks[1] = y;
5058 info.blocks[2] = z;
5059
5060 info.offsets[0] = base_x;
5061 info.offsets[1] = base_y;
5062 info.offsets[2] = base_z;
5063 radv_dispatch(cmd_buffer, &info);
5064 }
5065
5066 void radv_CmdDispatch(
5067 VkCommandBuffer commandBuffer,
5068 uint32_t x,
5069 uint32_t y,
5070 uint32_t z)
5071 {
5072 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
5073 }
5074
5075 void radv_CmdDispatchIndirect(
5076 VkCommandBuffer commandBuffer,
5077 VkBuffer _buffer,
5078 VkDeviceSize offset)
5079 {
5080 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5081 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5082 struct radv_dispatch_info info = {};
5083
5084 info.indirect = buffer;
5085 info.indirect_offset = offset;
5086
5087 radv_dispatch(cmd_buffer, &info);
5088 }
5089
5090 void radv_unaligned_dispatch(
5091 struct radv_cmd_buffer *cmd_buffer,
5092 uint32_t x,
5093 uint32_t y,
5094 uint32_t z)
5095 {
5096 struct radv_dispatch_info info = {};
5097
5098 info.blocks[0] = x;
5099 info.blocks[1] = y;
5100 info.blocks[2] = z;
5101 info.unaligned = 1;
5102
5103 radv_dispatch(cmd_buffer, &info);
5104 }
5105
5106 void radv_CmdEndRenderPass(
5107 VkCommandBuffer commandBuffer)
5108 {
5109 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5110
5111 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
5112
5113 radv_cmd_buffer_end_subpass(cmd_buffer);
5114
5115 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
5116 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
5117
5118 cmd_buffer->state.pass = NULL;
5119 cmd_buffer->state.subpass = NULL;
5120 cmd_buffer->state.attachments = NULL;
5121 cmd_buffer->state.framebuffer = NULL;
5122 cmd_buffer->state.subpass_sample_locs = NULL;
5123 }
5124
5125 void radv_CmdEndRenderPass2KHR(
5126 VkCommandBuffer commandBuffer,
5127 const VkSubpassEndInfoKHR* pSubpassEndInfo)
5128 {
5129 radv_CmdEndRenderPass(commandBuffer);
5130 }
5131
5132 /*
5133 * For HTILE we have the following interesting clear words:
5134 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5135 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5136 * 0xfffffff0: Clear depth to 1.0
5137 * 0x00000000: Clear depth to 0.0
5138 */
5139 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
5140 struct radv_image *image,
5141 const VkImageSubresourceRange *range,
5142 uint32_t clear_word)
5143 {
5144 assert(range->baseMipLevel == 0);
5145 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
5146 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
5147 struct radv_cmd_state *state = &cmd_buffer->state;
5148 VkClearDepthStencilValue value = {};
5149
5150 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5151 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5152
5153 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
5154
5155 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5156
5157 if (vk_format_is_stencil(image->vk_format))
5158 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
5159
5160 radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
5161
5162 if (radv_image_is_tc_compat_htile(image)) {
5163 /* Initialize the TC-compat metada value to 0 because by
5164 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5165 * need have to conditionally update its value when performing
5166 * a fast depth clear.
5167 */
5168 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);
5169 }
5170 }
5171
5172 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
5173 struct radv_image *image,
5174 VkImageLayout src_layout,
5175 bool src_render_loop,
5176 VkImageLayout dst_layout,
5177 bool dst_render_loop,
5178 unsigned src_queue_mask,
5179 unsigned dst_queue_mask,
5180 const VkImageSubresourceRange *range,
5181 struct radv_sample_locations_state *sample_locs)
5182 {
5183 if (!radv_image_has_htile(image))
5184 return;
5185
5186 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5187 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5188
5189 if (radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop,
5190 dst_queue_mask)) {
5191 clear_value = 0;
5192 }
5193
5194 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5195 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5196 radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5197 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
5198 radv_initialize_htile(cmd_buffer, image, range, clear_value);
5199 } else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
5200 !radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5201 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5202 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5203
5204 radv_decompress_depth_image_inplace(cmd_buffer, image, range,
5205 sample_locs);
5206
5207 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
5208 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
5209 }
5210 }
5211
5212 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
5213 struct radv_image *image,
5214 const VkImageSubresourceRange *range,
5215 uint32_t value)
5216 {
5217 struct radv_cmd_state *state = &cmd_buffer->state;
5218
5219 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5220 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5221
5222 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
5223
5224 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5225 }
5226
5227 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
5228 struct radv_image *image,
5229 const VkImageSubresourceRange *range)
5230 {
5231 struct radv_cmd_state *state = &cmd_buffer->state;
5232 static const uint32_t fmask_clear_values[4] = {
5233 0x00000000,
5234 0x02020202,
5235 0xE4E4E4E4,
5236 0x76543210
5237 };
5238 uint32_t log2_samples = util_logbase2(image->info.samples);
5239 uint32_t value = fmask_clear_values[log2_samples];
5240
5241 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5242 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5243
5244 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5245
5246 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5247 }
5248
5249 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5250 struct radv_image *image,
5251 const VkImageSubresourceRange *range, uint32_t value)
5252 {
5253 struct radv_cmd_state *state = &cmd_buffer->state;
5254 unsigned size = 0;
5255
5256 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5257 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5258
5259 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5260
5261 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5262 /* When DCC is enabled with mipmaps, some levels might not
5263 * support fast clears and we have to initialize them as "fully
5264 * expanded".
5265 */
5266 /* Compute the size of all fast clearable DCC levels. */
5267 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5268 struct legacy_surf_level *surf_level =
5269 &image->planes[0].surface.u.legacy.level[i];
5270 unsigned dcc_fast_clear_size =
5271 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5272
5273 if (!dcc_fast_clear_size)
5274 break;
5275
5276 size = surf_level->dcc_offset + dcc_fast_clear_size;
5277 }
5278
5279 /* Initialize the mipmap levels without DCC. */
5280 if (size != image->planes[0].surface.dcc_size) {
5281 state->flush_bits |=
5282 radv_fill_buffer(cmd_buffer, image->bo,
5283 image->offset + image->dcc_offset + size,
5284 image->planes[0].surface.dcc_size - size,
5285 0xffffffff);
5286 }
5287 }
5288
5289 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5290 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5291 }
5292
5293 /**
5294 * Initialize DCC/FMASK/CMASK metadata for a color image.
5295 */
5296 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5297 struct radv_image *image,
5298 VkImageLayout src_layout,
5299 bool src_render_loop,
5300 VkImageLayout dst_layout,
5301 bool dst_render_loop,
5302 unsigned src_queue_mask,
5303 unsigned dst_queue_mask,
5304 const VkImageSubresourceRange *range)
5305 {
5306 if (radv_image_has_cmask(image)) {
5307 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5308
5309 /* TODO: clarify this. */
5310 if (radv_image_has_fmask(image)) {
5311 value = 0xccccccccu;
5312 }
5313
5314 radv_initialise_cmask(cmd_buffer, image, range, value);
5315 }
5316
5317 if (radv_image_has_fmask(image)) {
5318 radv_initialize_fmask(cmd_buffer, image, range);
5319 }
5320
5321 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5322 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5323 bool need_decompress_pass = false;
5324
5325 if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
5326 dst_render_loop,
5327 dst_queue_mask)) {
5328 value = 0x20202020u;
5329 need_decompress_pass = true;
5330 }
5331
5332 radv_initialize_dcc(cmd_buffer, image, range, value);
5333
5334 radv_update_fce_metadata(cmd_buffer, image, range,
5335 need_decompress_pass);
5336 }
5337
5338 if (radv_image_has_cmask(image) ||
5339 radv_dcc_enabled(image, range->baseMipLevel)) {
5340 uint32_t color_values[2] = {};
5341 radv_set_color_clear_metadata(cmd_buffer, image, range,
5342 color_values);
5343 }
5344 }
5345
5346 /**
5347 * Handle color image transitions for DCC/FMASK/CMASK.
5348 */
5349 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5350 struct radv_image *image,
5351 VkImageLayout src_layout,
5352 bool src_render_loop,
5353 VkImageLayout dst_layout,
5354 bool dst_render_loop,
5355 unsigned src_queue_mask,
5356 unsigned dst_queue_mask,
5357 const VkImageSubresourceRange *range)
5358 {
5359 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5360 radv_init_color_image_metadata(cmd_buffer, image,
5361 src_layout, src_render_loop,
5362 dst_layout, dst_render_loop,
5363 src_queue_mask, dst_queue_mask,
5364 range);
5365 return;
5366 }
5367
5368 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5369 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5370 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5371 } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
5372 !radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
5373 radv_decompress_dcc(cmd_buffer, image, range);
5374 } else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5375 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5376 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5377 }
5378 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5379 bool fce_eliminate = false, fmask_expand = false;
5380
5381 if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
5382 !radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
5383 fce_eliminate = true;
5384 }
5385
5386 if (radv_image_has_fmask(image)) {
5387 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5388 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5389 /* A FMASK decompress is required before doing
5390 * a MSAA decompress using FMASK.
5391 */
5392 fmask_expand = true;
5393 }
5394 }
5395
5396 if (fce_eliminate || fmask_expand)
5397 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5398
5399 if (fmask_expand)
5400 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5401 }
5402 }
5403
5404 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5405 struct radv_image *image,
5406 VkImageLayout src_layout,
5407 bool src_render_loop,
5408 VkImageLayout dst_layout,
5409 bool dst_render_loop,
5410 uint32_t src_family,
5411 uint32_t dst_family,
5412 const VkImageSubresourceRange *range,
5413 struct radv_sample_locations_state *sample_locs)
5414 {
5415 if (image->exclusive && src_family != dst_family) {
5416 /* This is an acquire or a release operation and there will be
5417 * a corresponding release/acquire. Do the transition in the
5418 * most flexible queue. */
5419
5420 assert(src_family == cmd_buffer->queue_family_index ||
5421 dst_family == cmd_buffer->queue_family_index);
5422
5423 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5424 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5425 return;
5426
5427 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5428 return;
5429
5430 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5431 (src_family == RADV_QUEUE_GENERAL ||
5432 dst_family == RADV_QUEUE_GENERAL))
5433 return;
5434 }
5435
5436 if (src_layout == dst_layout)
5437 return;
5438
5439 unsigned src_queue_mask =
5440 radv_image_queue_family_mask(image, src_family,
5441 cmd_buffer->queue_family_index);
5442 unsigned dst_queue_mask =
5443 radv_image_queue_family_mask(image, dst_family,
5444 cmd_buffer->queue_family_index);
5445
5446 if (vk_format_is_depth(image->vk_format)) {
5447 radv_handle_depth_image_transition(cmd_buffer, image,
5448 src_layout, src_render_loop,
5449 dst_layout, dst_render_loop,
5450 src_queue_mask, dst_queue_mask,
5451 range, sample_locs);
5452 } else {
5453 radv_handle_color_image_transition(cmd_buffer, image,
5454 src_layout, src_render_loop,
5455 dst_layout, dst_render_loop,
5456 src_queue_mask, dst_queue_mask,
5457 range);
5458 }
5459 }
5460
5461 struct radv_barrier_info {
5462 uint32_t eventCount;
5463 const VkEvent *pEvents;
5464 VkPipelineStageFlags srcStageMask;
5465 VkPipelineStageFlags dstStageMask;
5466 };
5467
5468 static void
5469 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5470 uint32_t memoryBarrierCount,
5471 const VkMemoryBarrier *pMemoryBarriers,
5472 uint32_t bufferMemoryBarrierCount,
5473 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5474 uint32_t imageMemoryBarrierCount,
5475 const VkImageMemoryBarrier *pImageMemoryBarriers,
5476 const struct radv_barrier_info *info)
5477 {
5478 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5479 enum radv_cmd_flush_bits src_flush_bits = 0;
5480 enum radv_cmd_flush_bits dst_flush_bits = 0;
5481
5482 for (unsigned i = 0; i < info->eventCount; ++i) {
5483 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5484 uint64_t va = radv_buffer_get_va(event->bo);
5485
5486 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5487
5488 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5489
5490 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5491 assert(cmd_buffer->cs->cdw <= cdw_max);
5492 }
5493
5494 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5495 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5496 NULL);
5497 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5498 NULL);
5499 }
5500
5501 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5502 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5503 NULL);
5504 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5505 NULL);
5506 }
5507
5508 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5509 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5510
5511 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5512 image);
5513 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5514 image);
5515 }
5516
5517 /* The Vulkan spec 1.1.98 says:
5518 *
5519 * "An execution dependency with only
5520 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5521 * will only prevent that stage from executing in subsequently
5522 * submitted commands. As this stage does not perform any actual
5523 * execution, this is not observable - in effect, it does not delay
5524 * processing of subsequent commands. Similarly an execution dependency
5525 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5526 * will effectively not wait for any prior commands to complete."
5527 */
5528 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5529 radv_stage_flush(cmd_buffer, info->srcStageMask);
5530 cmd_buffer->state.flush_bits |= src_flush_bits;
5531
5532 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5533 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5534
5535 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5536 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5537 SAMPLE_LOCATIONS_INFO_EXT);
5538 struct radv_sample_locations_state sample_locations = {};
5539
5540 if (sample_locs_info) {
5541 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5542 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5543 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5544 sample_locations.count = sample_locs_info->sampleLocationsCount;
5545 typed_memcpy(&sample_locations.locations[0],
5546 sample_locs_info->pSampleLocations,
5547 sample_locs_info->sampleLocationsCount);
5548 }
5549
5550 radv_handle_image_transition(cmd_buffer, image,
5551 pImageMemoryBarriers[i].oldLayout,
5552 false, /* Outside of a renderpass we are never in a renderloop */
5553 pImageMemoryBarriers[i].newLayout,
5554 false, /* Outside of a renderpass we are never in a renderloop */
5555 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5556 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5557 &pImageMemoryBarriers[i].subresourceRange,
5558 sample_locs_info ? &sample_locations : NULL);
5559 }
5560
5561 /* Make sure CP DMA is idle because the driver might have performed a
5562 * DMA operation for copying or filling buffers/images.
5563 */
5564 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5565 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5566 si_cp_dma_wait_for_idle(cmd_buffer);
5567
5568 cmd_buffer->state.flush_bits |= dst_flush_bits;
5569 }
5570
5571 void radv_CmdPipelineBarrier(
5572 VkCommandBuffer commandBuffer,
5573 VkPipelineStageFlags srcStageMask,
5574 VkPipelineStageFlags destStageMask,
5575 VkBool32 byRegion,
5576 uint32_t memoryBarrierCount,
5577 const VkMemoryBarrier* pMemoryBarriers,
5578 uint32_t bufferMemoryBarrierCount,
5579 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5580 uint32_t imageMemoryBarrierCount,
5581 const VkImageMemoryBarrier* pImageMemoryBarriers)
5582 {
5583 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5584 struct radv_barrier_info info;
5585
5586 info.eventCount = 0;
5587 info.pEvents = NULL;
5588 info.srcStageMask = srcStageMask;
5589 info.dstStageMask = destStageMask;
5590
5591 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5592 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5593 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5594 }
5595
5596
5597 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5598 struct radv_event *event,
5599 VkPipelineStageFlags stageMask,
5600 unsigned value)
5601 {
5602 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5603 uint64_t va = radv_buffer_get_va(event->bo);
5604
5605 si_emit_cache_flush(cmd_buffer);
5606
5607 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5608
5609 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5610
5611 /* Flags that only require a top-of-pipe event. */
5612 VkPipelineStageFlags top_of_pipe_flags =
5613 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5614
5615 /* Flags that only require a post-index-fetch event. */
5616 VkPipelineStageFlags post_index_fetch_flags =
5617 top_of_pipe_flags |
5618 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5619 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5620
5621 /* Make sure CP DMA is idle because the driver might have performed a
5622 * DMA operation for copying or filling buffers/images.
5623 */
5624 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5625 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5626 si_cp_dma_wait_for_idle(cmd_buffer);
5627
5628 /* TODO: Emit EOS events for syncing PS/CS stages. */
5629
5630 if (!(stageMask & ~top_of_pipe_flags)) {
5631 /* Just need to sync the PFP engine. */
5632 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5633 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5634 S_370_WR_CONFIRM(1) |
5635 S_370_ENGINE_SEL(V_370_PFP));
5636 radeon_emit(cs, va);
5637 radeon_emit(cs, va >> 32);
5638 radeon_emit(cs, value);
5639 } else if (!(stageMask & ~post_index_fetch_flags)) {
5640 /* Sync ME because PFP reads index and indirect buffers. */
5641 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5642 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5643 S_370_WR_CONFIRM(1) |
5644 S_370_ENGINE_SEL(V_370_ME));
5645 radeon_emit(cs, va);
5646 radeon_emit(cs, va >> 32);
5647 radeon_emit(cs, value);
5648 } else {
5649 /* Otherwise, sync all prior GPU work using an EOP event. */
5650 si_cs_emit_write_event_eop(cs,
5651 cmd_buffer->device->physical_device->rad_info.chip_class,
5652 radv_cmd_buffer_uses_mec(cmd_buffer),
5653 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5654 EOP_DST_SEL_MEM,
5655 EOP_DATA_SEL_VALUE_32BIT, va, value,
5656 cmd_buffer->gfx9_eop_bug_va);
5657 }
5658
5659 assert(cmd_buffer->cs->cdw <= cdw_max);
5660 }
5661
5662 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5663 VkEvent _event,
5664 VkPipelineStageFlags stageMask)
5665 {
5666 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5667 RADV_FROM_HANDLE(radv_event, event, _event);
5668
5669 write_event(cmd_buffer, event, stageMask, 1);
5670 }
5671
5672 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5673 VkEvent _event,
5674 VkPipelineStageFlags stageMask)
5675 {
5676 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5677 RADV_FROM_HANDLE(radv_event, event, _event);
5678
5679 write_event(cmd_buffer, event, stageMask, 0);
5680 }
5681
5682 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5683 uint32_t eventCount,
5684 const VkEvent* pEvents,
5685 VkPipelineStageFlags srcStageMask,
5686 VkPipelineStageFlags dstStageMask,
5687 uint32_t memoryBarrierCount,
5688 const VkMemoryBarrier* pMemoryBarriers,
5689 uint32_t bufferMemoryBarrierCount,
5690 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5691 uint32_t imageMemoryBarrierCount,
5692 const VkImageMemoryBarrier* pImageMemoryBarriers)
5693 {
5694 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5695 struct radv_barrier_info info;
5696
5697 info.eventCount = eventCount;
5698 info.pEvents = pEvents;
5699 info.srcStageMask = 0;
5700
5701 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5702 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5703 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5704 }
5705
5706
5707 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5708 uint32_t deviceMask)
5709 {
5710 /* No-op */
5711 }
5712
5713 /* VK_EXT_conditional_rendering */
5714 void radv_CmdBeginConditionalRenderingEXT(
5715 VkCommandBuffer commandBuffer,
5716 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5717 {
5718 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5719 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5720 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5721 bool draw_visible = true;
5722 uint64_t pred_value = 0;
5723 uint64_t va, new_va;
5724 unsigned pred_offset;
5725
5726 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5727
5728 /* By default, if the 32-bit value at offset in buffer memory is zero,
5729 * then the rendering commands are discarded, otherwise they are
5730 * executed as normal. If the inverted flag is set, all commands are
5731 * discarded if the value is non zero.
5732 */
5733 if (pConditionalRenderingBegin->flags &
5734 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5735 draw_visible = false;
5736 }
5737
5738 si_emit_cache_flush(cmd_buffer);
5739
5740 /* From the Vulkan spec 1.1.107:
5741 *
5742 * "If the 32-bit value at offset in buffer memory is zero, then the
5743 * rendering commands are discarded, otherwise they are executed as
5744 * normal. If the value of the predicate in buffer memory changes while
5745 * conditional rendering is active, the rendering commands may be
5746 * discarded in an implementation-dependent way. Some implementations
5747 * may latch the value of the predicate upon beginning conditional
5748 * rendering while others may read it before every rendering command."
5749 *
5750 * But, the AMD hardware treats the predicate as a 64-bit value which
5751 * means we need a workaround in the driver. Luckily, it's not required
5752 * to support if the value changes when predication is active.
5753 *
5754 * The workaround is as follows:
5755 * 1) allocate a 64-value in the upload BO and initialize it to 0
5756 * 2) copy the 32-bit predicate value to the upload BO
5757 * 3) use the new allocated VA address for predication
5758 *
5759 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5760 * in ME (+ sync PFP) instead of PFP.
5761 */
5762 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5763
5764 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5765
5766 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5767 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5768 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5769 COPY_DATA_WR_CONFIRM);
5770 radeon_emit(cs, va);
5771 radeon_emit(cs, va >> 32);
5772 radeon_emit(cs, new_va);
5773 radeon_emit(cs, new_va >> 32);
5774
5775 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5776 radeon_emit(cs, 0);
5777
5778 /* Enable predication for this command buffer. */
5779 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5780 cmd_buffer->state.predicating = true;
5781
5782 /* Store conditional rendering user info. */
5783 cmd_buffer->state.predication_type = draw_visible;
5784 cmd_buffer->state.predication_va = new_va;
5785 }
5786
5787 void radv_CmdEndConditionalRenderingEXT(
5788 VkCommandBuffer commandBuffer)
5789 {
5790 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5791
5792 /* Disable predication for this command buffer. */
5793 si_emit_set_predication_state(cmd_buffer, false, 0);
5794 cmd_buffer->state.predicating = false;
5795
5796 /* Reset conditional rendering user info. */
5797 cmd_buffer->state.predication_type = -1;
5798 cmd_buffer->state.predication_va = 0;
5799 }
5800
5801 /* VK_EXT_transform_feedback */
5802 void radv_CmdBindTransformFeedbackBuffersEXT(
5803 VkCommandBuffer commandBuffer,
5804 uint32_t firstBinding,
5805 uint32_t bindingCount,
5806 const VkBuffer* pBuffers,
5807 const VkDeviceSize* pOffsets,
5808 const VkDeviceSize* pSizes)
5809 {
5810 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5811 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5812 uint8_t enabled_mask = 0;
5813
5814 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5815 for (uint32_t i = 0; i < bindingCount; i++) {
5816 uint32_t idx = firstBinding + i;
5817
5818 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5819 sb[idx].offset = pOffsets[i];
5820 sb[idx].size = pSizes[i];
5821
5822 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5823 sb[idx].buffer->bo);
5824
5825 enabled_mask |= 1 << idx;
5826 }
5827
5828 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5829
5830 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5831 }
5832
5833 static void
5834 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5835 {
5836 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5837 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5838
5839 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5840 radeon_emit(cs,
5841 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5842 S_028B94_RAST_STREAM(0) |
5843 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5844 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5845 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5846 radeon_emit(cs, so->hw_enabled_mask &
5847 so->enabled_stream_buffers_mask);
5848
5849 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5850 }
5851
5852 static void
5853 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5854 {
5855 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5856 bool old_streamout_enabled = so->streamout_enabled;
5857 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5858
5859 so->streamout_enabled = enable;
5860
5861 so->hw_enabled_mask = so->enabled_mask |
5862 (so->enabled_mask << 4) |
5863 (so->enabled_mask << 8) |
5864 (so->enabled_mask << 12);
5865
5866 if (!cmd_buffer->device->physical_device->use_ngg_streamout &&
5867 ((old_streamout_enabled != so->streamout_enabled) ||
5868 (old_hw_enabled_mask != so->hw_enabled_mask)))
5869 radv_emit_streamout_enable(cmd_buffer);
5870
5871 if (cmd_buffer->device->physical_device->use_ngg_streamout)
5872 cmd_buffer->gds_needed = true;
5873 }
5874
5875 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5876 {
5877 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5878 unsigned reg_strmout_cntl;
5879
5880 /* The register is at different places on different ASICs. */
5881 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5882 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5883 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5884 } else {
5885 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5886 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5887 }
5888
5889 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5890 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5891
5892 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5893 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5894 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5895 radeon_emit(cs, 0);
5896 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5897 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5898 radeon_emit(cs, 4); /* poll interval */
5899 }
5900
5901 static void
5902 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5903 uint32_t firstCounterBuffer,
5904 uint32_t counterBufferCount,
5905 const VkBuffer *pCounterBuffers,
5906 const VkDeviceSize *pCounterBufferOffsets)
5907
5908 {
5909 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5910 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5911 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5912 uint32_t i;
5913
5914 radv_flush_vgt_streamout(cmd_buffer);
5915
5916 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5917 for_each_bit(i, so->enabled_mask) {
5918 int32_t counter_buffer_idx = i - firstCounterBuffer;
5919 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5920 counter_buffer_idx = -1;
5921
5922 /* AMD GCN binds streamout buffers as shader resources.
5923 * VGT only counts primitives and tells the shader through
5924 * SGPRs what to do.
5925 */
5926 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5927 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5928 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5929
5930 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5931
5932 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5933 /* The array of counter buffers is optional. */
5934 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5935 uint64_t va = radv_buffer_get_va(buffer->bo);
5936
5937 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5938
5939 /* Append */
5940 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5941 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5942 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5943 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5944 radeon_emit(cs, 0); /* unused */
5945 radeon_emit(cs, 0); /* unused */
5946 radeon_emit(cs, va); /* src address lo */
5947 radeon_emit(cs, va >> 32); /* src address hi */
5948
5949 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5950 } else {
5951 /* Start from the beginning. */
5952 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5953 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5954 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5955 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5956 radeon_emit(cs, 0); /* unused */
5957 radeon_emit(cs, 0); /* unused */
5958 radeon_emit(cs, 0); /* unused */
5959 radeon_emit(cs, 0); /* unused */
5960 }
5961 }
5962
5963 radv_set_streamout_enable(cmd_buffer, true);
5964 }
5965
5966 static void
5967 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5968 uint32_t firstCounterBuffer,
5969 uint32_t counterBufferCount,
5970 const VkBuffer *pCounterBuffers,
5971 const VkDeviceSize *pCounterBufferOffsets)
5972 {
5973 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5974 unsigned last_target = util_last_bit(so->enabled_mask) - 1;
5975 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5976 uint32_t i;
5977
5978 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
5979 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5980
5981 /* Sync because the next streamout operation will overwrite GDS and we
5982 * have to make sure it's idle.
5983 * TODO: Improve by tracking if there is a streamout operation in
5984 * flight.
5985 */
5986 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
5987 si_emit_cache_flush(cmd_buffer);
5988
5989 for_each_bit(i, so->enabled_mask) {
5990 int32_t counter_buffer_idx = i - firstCounterBuffer;
5991 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5992 counter_buffer_idx = -1;
5993
5994 bool append = counter_buffer_idx >= 0 &&
5995 pCounterBuffers && pCounterBuffers[counter_buffer_idx];
5996 uint64_t va = 0;
5997
5998 if (append) {
5999 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6000
6001 va += radv_buffer_get_va(buffer->bo);
6002 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6003
6004 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6005 }
6006
6007 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
6008 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
6009 S_411_DST_SEL(V_411_GDS) |
6010 S_411_CP_SYNC(i == last_target));
6011 radeon_emit(cs, va);
6012 radeon_emit(cs, va >> 32);
6013 radeon_emit(cs, 4 * i); /* destination in GDS */
6014 radeon_emit(cs, 0);
6015 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) |
6016 S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target));
6017 }
6018
6019 radv_set_streamout_enable(cmd_buffer, true);
6020 }
6021
6022 void radv_CmdBeginTransformFeedbackEXT(
6023 VkCommandBuffer commandBuffer,
6024 uint32_t firstCounterBuffer,
6025 uint32_t counterBufferCount,
6026 const VkBuffer* pCounterBuffers,
6027 const VkDeviceSize* pCounterBufferOffsets)
6028 {
6029 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6030
6031 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6032 gfx10_emit_streamout_begin(cmd_buffer,
6033 firstCounterBuffer, counterBufferCount,
6034 pCounterBuffers, pCounterBufferOffsets);
6035 } else {
6036 radv_emit_streamout_begin(cmd_buffer,
6037 firstCounterBuffer, counterBufferCount,
6038 pCounterBuffers, pCounterBufferOffsets);
6039 }
6040 }
6041
6042 static void
6043 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6044 uint32_t firstCounterBuffer,
6045 uint32_t counterBufferCount,
6046 const VkBuffer *pCounterBuffers,
6047 const VkDeviceSize *pCounterBufferOffsets)
6048 {
6049 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6050 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6051 uint32_t i;
6052
6053 radv_flush_vgt_streamout(cmd_buffer);
6054
6055 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6056 for_each_bit(i, so->enabled_mask) {
6057 int32_t counter_buffer_idx = i - firstCounterBuffer;
6058 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6059 counter_buffer_idx = -1;
6060
6061 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6062 /* The array of counters buffer is optional. */
6063 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6064 uint64_t va = radv_buffer_get_va(buffer->bo);
6065
6066 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6067
6068 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
6069 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
6070 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6071 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
6072 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
6073 radeon_emit(cs, va); /* dst address lo */
6074 radeon_emit(cs, va >> 32); /* dst address hi */
6075 radeon_emit(cs, 0); /* unused */
6076 radeon_emit(cs, 0); /* unused */
6077
6078 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6079 }
6080
6081 /* Deactivate transform feedback by zeroing the buffer size.
6082 * The counters (primitives generated, primitives emitted) may
6083 * be enabled even if there is not buffer bound. This ensures
6084 * that the primitives-emitted query won't increment.
6085 */
6086 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
6087
6088 cmd_buffer->state.context_roll_without_scissor_emitted = true;
6089 }
6090
6091 radv_set_streamout_enable(cmd_buffer, false);
6092 }
6093
6094 static void
6095 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
6096 uint32_t firstCounterBuffer,
6097 uint32_t counterBufferCount,
6098 const VkBuffer *pCounterBuffers,
6099 const VkDeviceSize *pCounterBufferOffsets)
6100 {
6101 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
6102 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6103 uint32_t i;
6104
6105 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
6106 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
6107
6108 for_each_bit(i, so->enabled_mask) {
6109 int32_t counter_buffer_idx = i - firstCounterBuffer;
6110 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
6111 counter_buffer_idx = -1;
6112
6113 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
6114 /* The array of counters buffer is optional. */
6115 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
6116 uint64_t va = radv_buffer_get_va(buffer->bo);
6117
6118 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
6119
6120 si_cs_emit_write_event_eop(cs,
6121 cmd_buffer->device->physical_device->rad_info.chip_class,
6122 radv_cmd_buffer_uses_mec(cmd_buffer),
6123 V_028A90_PS_DONE, 0,
6124 EOP_DST_SEL_TC_L2,
6125 EOP_DATA_SEL_GDS,
6126 va, EOP_DATA_GDS(i, 1), 0);
6127
6128 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
6129 }
6130 }
6131
6132 radv_set_streamout_enable(cmd_buffer, false);
6133 }
6134
6135 void radv_CmdEndTransformFeedbackEXT(
6136 VkCommandBuffer commandBuffer,
6137 uint32_t firstCounterBuffer,
6138 uint32_t counterBufferCount,
6139 const VkBuffer* pCounterBuffers,
6140 const VkDeviceSize* pCounterBufferOffsets)
6141 {
6142 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6143
6144 if (cmd_buffer->device->physical_device->use_ngg_streamout) {
6145 gfx10_emit_streamout_end(cmd_buffer,
6146 firstCounterBuffer, counterBufferCount,
6147 pCounterBuffers, pCounterBufferOffsets);
6148 } else {
6149 radv_emit_streamout_end(cmd_buffer,
6150 firstCounterBuffer, counterBufferCount,
6151 pCounterBuffers, pCounterBufferOffsets);
6152 }
6153 }
6154
6155 void radv_CmdDrawIndirectByteCountEXT(
6156 VkCommandBuffer commandBuffer,
6157 uint32_t instanceCount,
6158 uint32_t firstInstance,
6159 VkBuffer _counterBuffer,
6160 VkDeviceSize counterBufferOffset,
6161 uint32_t counterOffset,
6162 uint32_t vertexStride)
6163 {
6164 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6165 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
6166 struct radv_draw_info info = {};
6167
6168 info.instance_count = instanceCount;
6169 info.first_instance = firstInstance;
6170 info.strmout_buffer = counterBuffer;
6171 info.strmout_buffer_offset = counterBufferOffset;
6172 info.stride = vertexStride;
6173
6174 radv_draw(cmd_buffer, &info);
6175 }
6176
6177 /* VK_AMD_buffer_marker */
6178 void radv_CmdWriteBufferMarkerAMD(
6179 VkCommandBuffer commandBuffer,
6180 VkPipelineStageFlagBits pipelineStage,
6181 VkBuffer dstBuffer,
6182 VkDeviceSize dstOffset,
6183 uint32_t marker)
6184 {
6185 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
6186 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
6187 struct radeon_cmdbuf *cs = cmd_buffer->cs;
6188 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
6189
6190 si_emit_cache_flush(cmd_buffer);
6191
6192 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
6193 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
6194 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
6195 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
6196 COPY_DATA_WR_CONFIRM);
6197 radeon_emit(cs, marker);
6198 radeon_emit(cs, 0);
6199 radeon_emit(cs, va);
6200 radeon_emit(cs, va >> 32);
6201 } else {
6202 si_cs_emit_write_event_eop(cs,
6203 cmd_buffer->device->physical_device->rad_info.chip_class,
6204 radv_cmd_buffer_uses_mec(cmd_buffer),
6205 V_028A90_BOTTOM_OF_PIPE_TS, 0,
6206 EOP_DST_SEL_MEM,
6207 EOP_DATA_SEL_VALUE_32BIT,
6208 va, marker,
6209 cmd_buffer->gfx9_eop_bug_va);
6210 }
6211 }