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radv: Remove vertex_descriptors_dirty.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "gfx9d.h"
33 #include "vk_format.h"
34 #include "radv_meta.h"
35
36 #include "ac_debug.h"
37
38 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
39 struct radv_image *image,
40 VkImageLayout src_layout,
41 VkImageLayout dst_layout,
42 uint32_t src_family,
43 uint32_t dst_family,
44 const VkImageSubresourceRange *range,
45 VkImageAspectFlags pending_clears);
46
47 const struct radv_dynamic_state default_dynamic_state = {
48 .viewport = {
49 .count = 0,
50 },
51 .scissor = {
52 .count = 0,
53 },
54 .line_width = 1.0f,
55 .depth_bias = {
56 .bias = 0.0f,
57 .clamp = 0.0f,
58 .slope = 0.0f,
59 },
60 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
61 .depth_bounds = {
62 .min = 0.0f,
63 .max = 1.0f,
64 },
65 .stencil_compare_mask = {
66 .front = ~0u,
67 .back = ~0u,
68 },
69 .stencil_write_mask = {
70 .front = ~0u,
71 .back = ~0u,
72 },
73 .stencil_reference = {
74 .front = 0u,
75 .back = 0u,
76 },
77 };
78
79 void
80 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
81 const struct radv_dynamic_state *src,
82 uint32_t copy_mask)
83 {
84 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
85 dest->viewport.count = src->viewport.count;
86 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
87 src->viewport.count);
88 }
89
90 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
91 dest->scissor.count = src->scissor.count;
92 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
93 src->scissor.count);
94 }
95
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
97 dest->line_width = src->line_width;
98
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
100 dest->depth_bias = src->depth_bias;
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
103 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
106 dest->depth_bounds = src->depth_bounds;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
109 dest->stencil_compare_mask = src->stencil_compare_mask;
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
112 dest->stencil_write_mask = src->stencil_write_mask;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
115 dest->stencil_reference = src->stencil_reference;
116 }
117
118 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
119 {
120 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
121 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
122 }
123
124 enum ring_type radv_queue_family_to_ring(int f) {
125 switch (f) {
126 case RADV_QUEUE_GENERAL:
127 return RING_GFX;
128 case RADV_QUEUE_COMPUTE:
129 return RING_COMPUTE;
130 case RADV_QUEUE_TRANSFER:
131 return RING_DMA;
132 default:
133 unreachable("Unknown queue family");
134 }
135 }
136
137 static VkResult radv_create_cmd_buffer(
138 struct radv_device * device,
139 struct radv_cmd_pool * pool,
140 VkCommandBufferLevel level,
141 VkCommandBuffer* pCommandBuffer)
142 {
143 struct radv_cmd_buffer *cmd_buffer;
144 VkResult result;
145 unsigned ring;
146 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
147 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
148 if (cmd_buffer == NULL)
149 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
150
151 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
152 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
153 cmd_buffer->device = device;
154 cmd_buffer->pool = pool;
155 cmd_buffer->level = level;
156
157 if (pool) {
158 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
159 cmd_buffer->queue_family_index = pool->queue_family_index;
160
161 } else {
162 /* Init the pool_link so we can safefly call list_del when we destroy
163 * the command buffer
164 */
165 list_inithead(&cmd_buffer->pool_link);
166 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
167 }
168
169 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
170
171 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
172 if (!cmd_buffer->cs) {
173 result = VK_ERROR_OUT_OF_HOST_MEMORY;
174 goto fail;
175 }
176
177 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
178
179 cmd_buffer->upload.offset = 0;
180 cmd_buffer->upload.size = 0;
181 list_inithead(&cmd_buffer->upload.list);
182
183 return VK_SUCCESS;
184
185 fail:
186 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
187
188 return result;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
211 {
212
213 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
214
215 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
216 &cmd_buffer->upload.list, list) {
217 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
218 list_del(&up->list);
219 free(up);
220 }
221
222 cmd_buffer->scratch_size_needed = 0;
223 cmd_buffer->compute_scratch_size_needed = 0;
224 cmd_buffer->esgs_ring_size_needed = 0;
225 cmd_buffer->gsvs_ring_size_needed = 0;
226 cmd_buffer->tess_rings_needed = false;
227 cmd_buffer->sample_positions_needed = false;
228
229 if (cmd_buffer->upload.upload_bo)
230 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
231 cmd_buffer->upload.upload_bo, 8);
232 cmd_buffer->upload.offset = 0;
233
234 cmd_buffer->record_fail = false;
235
236 cmd_buffer->ring_offsets_idx = -1;
237
238 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
239 void *fence_ptr;
240 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
241 &cmd_buffer->gfx9_fence_offset,
242 &fence_ptr);
243 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
244 }
245 }
246
247 static bool
248 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
249 uint64_t min_needed)
250 {
251 uint64_t new_size;
252 struct radeon_winsys_bo *bo;
253 struct radv_cmd_buffer_upload *upload;
254 struct radv_device *device = cmd_buffer->device;
255
256 new_size = MAX2(min_needed, 16 * 1024);
257 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
258
259 bo = device->ws->buffer_create(device->ws,
260 new_size, 4096,
261 RADEON_DOMAIN_GTT,
262 RADEON_FLAG_CPU_ACCESS);
263
264 if (!bo) {
265 cmd_buffer->record_fail = true;
266 return false;
267 }
268
269 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
270 if (cmd_buffer->upload.upload_bo) {
271 upload = malloc(sizeof(*upload));
272
273 if (!upload) {
274 cmd_buffer->record_fail = true;
275 device->ws->buffer_destroy(bo);
276 return false;
277 }
278
279 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
280 list_add(&upload->list, &cmd_buffer->upload.list);
281 }
282
283 cmd_buffer->upload.upload_bo = bo;
284 cmd_buffer->upload.size = new_size;
285 cmd_buffer->upload.offset = 0;
286 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
287
288 if (!cmd_buffer->upload.map) {
289 cmd_buffer->record_fail = true;
290 return false;
291 }
292
293 return true;
294 }
295
296 bool
297 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
298 unsigned size,
299 unsigned alignment,
300 unsigned *out_offset,
301 void **ptr)
302 {
303 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
304 if (offset + size > cmd_buffer->upload.size) {
305 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
306 return false;
307 offset = 0;
308 }
309
310 *out_offset = offset;
311 *ptr = cmd_buffer->upload.map + offset;
312
313 cmd_buffer->upload.offset = offset + size;
314 return true;
315 }
316
317 bool
318 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
319 unsigned size, unsigned alignment,
320 const void *data, unsigned *out_offset)
321 {
322 uint8_t *ptr;
323
324 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
325 out_offset, (void **)&ptr))
326 return false;
327
328 if (ptr)
329 memcpy(ptr, data, size);
330
331 return true;
332 }
333
334 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
335 {
336 struct radv_device *device = cmd_buffer->device;
337 struct radeon_winsys_cs *cs = cmd_buffer->cs;
338 uint64_t va;
339
340 if (!device->trace_bo)
341 return;
342
343 va = device->ws->buffer_get_va(device->trace_bo);
344
345 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
346
347 ++cmd_buffer->state.trace_id;
348 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
349 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
350 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
351 S_370_WR_CONFIRM(1) |
352 S_370_ENGINE_SEL(V_370_ME));
353 radeon_emit(cs, va);
354 radeon_emit(cs, va >> 32);
355 radeon_emit(cs, cmd_buffer->state.trace_id);
356 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
357 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
358 }
359
360 static void
361 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
362 struct radv_pipeline *pipeline)
363 {
364 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
365 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
366 8);
367 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
369
370 if (cmd_buffer->device->physical_device->has_rbplus) {
371 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
372 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
373 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
374 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
375 }
376 }
377
378 static void
379 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
380 struct radv_pipeline *pipeline)
381 {
382 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
383 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
384 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
385
386 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
387 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
388 }
389
390 /* 12.4 fixed-point */
391 static unsigned radv_pack_float_12p4(float x)
392 {
393 return x <= 0 ? 0 :
394 x >= 4096 ? 0xffff : x * 16;
395 }
396
397 static uint32_t
398 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
399 {
400 switch (stage) {
401 case MESA_SHADER_FRAGMENT:
402 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
403 case MESA_SHADER_VERTEX:
404 if (has_tess)
405 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
406 else
407 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
408 case MESA_SHADER_GEOMETRY:
409 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
410 case MESA_SHADER_COMPUTE:
411 return R_00B900_COMPUTE_USER_DATA_0;
412 case MESA_SHADER_TESS_CTRL:
413 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
414 case MESA_SHADER_TESS_EVAL:
415 if (has_gs)
416 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
417 else
418 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
419 default:
420 unreachable("unknown shader");
421 }
422 }
423
424 static struct ac_userdata_info *
425 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
426 gl_shader_stage stage,
427 int idx)
428 {
429 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
430 }
431
432 static void
433 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
434 struct radv_pipeline *pipeline,
435 gl_shader_stage stage,
436 int idx, uint64_t va)
437 {
438 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
439 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
440 if (loc->sgpr_idx == -1)
441 return;
442 assert(loc->num_sgprs == 2);
443 assert(!loc->indirect);
444 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
445 radeon_emit(cmd_buffer->cs, va);
446 radeon_emit(cmd_buffer->cs, va >> 32);
447 }
448
449 static void
450 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
451 struct radv_pipeline *pipeline)
452 {
453 int num_samples = pipeline->graphics.ms.num_samples;
454 struct radv_multisample_state *ms = &pipeline->graphics.ms;
455 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
456
457 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
458 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
459 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
460
461 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
462 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
463
464 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
465 return;
466
467 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
468 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
469 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
470
471 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
472
473 /* GFX9: Flush DFSM when the AA mode changes. */
474 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
475 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
476 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
477 }
478 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
479 uint32_t offset;
480 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
481 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
482 if (loc->sgpr_idx == -1)
483 return;
484 assert(loc->num_sgprs == 1);
485 assert(!loc->indirect);
486 switch (num_samples) {
487 default:
488 offset = 0;
489 break;
490 case 2:
491 offset = 1;
492 break;
493 case 4:
494 offset = 3;
495 break;
496 case 8:
497 offset = 7;
498 break;
499 case 16:
500 offset = 15;
501 break;
502 }
503
504 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
505 cmd_buffer->sample_positions_needed = true;
506 }
507 }
508
509 static void
510 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
511 struct radv_pipeline *pipeline)
512 {
513 struct radv_raster_state *raster = &pipeline->graphics.raster;
514
515 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
516 raster->pa_cl_clip_cntl);
517
518 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
519 raster->spi_interp_control);
520
521 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
522 unsigned tmp = (unsigned)(1.0 * 8.0);
523 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
524 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
525 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
526
527 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
528 raster->pa_su_vtx_cntl);
529
530 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
531 raster->pa_su_sc_mode_cntl);
532 }
533
534 static void
535 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
536 struct radv_pipeline *pipeline,
537 struct radv_shader_variant *shader,
538 struct ac_vs_output_info *outinfo)
539 {
540 struct radeon_winsys *ws = cmd_buffer->device->ws;
541 uint64_t va = ws->buffer_get_va(shader->bo);
542 unsigned export_count;
543
544 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
545 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
546
547 export_count = MAX2(1, outinfo->param_exports);
548 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
549 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
550
551 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
552 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
553 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
554 V_02870C_SPI_SHADER_4COMP :
555 V_02870C_SPI_SHADER_NONE) |
556 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
557 V_02870C_SPI_SHADER_4COMP :
558 V_02870C_SPI_SHADER_NONE) |
559 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
560 V_02870C_SPI_SHADER_4COMP :
561 V_02870C_SPI_SHADER_NONE));
562
563
564 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
565 radeon_emit(cmd_buffer->cs, va >> 8);
566 radeon_emit(cmd_buffer->cs, va >> 40);
567 radeon_emit(cmd_buffer->cs, shader->rsrc1);
568 radeon_emit(cmd_buffer->cs, shader->rsrc2);
569
570 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
571 S_028818_VTX_W0_FMT(1) |
572 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
573 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
574 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
575
576
577 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
578 pipeline->graphics.pa_cl_vs_out_cntl);
579
580 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
581 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
582 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
583 }
584
585 static void
586 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
587 struct radv_shader_variant *shader,
588 struct ac_es_output_info *outinfo)
589 {
590 struct radeon_winsys *ws = cmd_buffer->device->ws;
591 uint64_t va = ws->buffer_get_va(shader->bo);
592
593 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
594 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
595
596 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
597 outinfo->esgs_itemsize / 4);
598 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
599 radeon_emit(cmd_buffer->cs, va >> 8);
600 radeon_emit(cmd_buffer->cs, va >> 40);
601 radeon_emit(cmd_buffer->cs, shader->rsrc1);
602 radeon_emit(cmd_buffer->cs, shader->rsrc2);
603 }
604
605 static void
606 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
607 struct radv_shader_variant *shader)
608 {
609 struct radeon_winsys *ws = cmd_buffer->device->ws;
610 uint64_t va = ws->buffer_get_va(shader->bo);
611 uint32_t rsrc2 = shader->rsrc2;
612
613 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
614 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
615
616 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
617 radeon_emit(cmd_buffer->cs, va >> 8);
618 radeon_emit(cmd_buffer->cs, va >> 40);
619
620 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
621 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
622 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
623 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
624
625 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
626 radeon_emit(cmd_buffer->cs, shader->rsrc1);
627 radeon_emit(cmd_buffer->cs, rsrc2);
628 }
629
630 static void
631 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
632 struct radv_shader_variant *shader)
633 {
634 struct radeon_winsys *ws = cmd_buffer->device->ws;
635 uint64_t va = ws->buffer_get_va(shader->bo);
636
637 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
638 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
639
640 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
641 radeon_emit(cmd_buffer->cs, va >> 8);
642 radeon_emit(cmd_buffer->cs, va >> 40);
643 radeon_emit(cmd_buffer->cs, shader->rsrc1);
644 radeon_emit(cmd_buffer->cs, shader->rsrc2);
645 }
646
647 static void
648 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
649 struct radv_pipeline *pipeline)
650 {
651 struct radv_shader_variant *vs;
652
653 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
654
655 vs = pipeline->shaders[MESA_SHADER_VERTEX];
656
657 if (vs->info.vs.as_ls)
658 radv_emit_hw_ls(cmd_buffer, vs);
659 else if (vs->info.vs.as_es)
660 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
661 else
662 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
663
664 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
665 }
666
667
668 static void
669 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
670 struct radv_pipeline *pipeline)
671 {
672 if (!radv_pipeline_has_tess(pipeline))
673 return;
674
675 struct radv_shader_variant *tes, *tcs;
676
677 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
678 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
679
680 if (tes->info.tes.as_es)
681 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
682 else
683 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
684
685 radv_emit_hw_hs(cmd_buffer, tcs);
686
687 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
688 pipeline->graphics.tess.tf_param);
689
690 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
691 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
692 pipeline->graphics.tess.ls_hs_config);
693 else
694 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
695 pipeline->graphics.tess.ls_hs_config);
696
697 struct ac_userdata_info *loc;
698
699 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
700 if (loc->sgpr_idx != -1) {
701 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
702 assert(loc->num_sgprs == 4);
703 assert(!loc->indirect);
704 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
705 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
706 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
707 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
708 pipeline->graphics.tess.num_tcs_input_cp << 26);
709 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
710 }
711
712 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
713 if (loc->sgpr_idx != -1) {
714 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
715 assert(loc->num_sgprs == 1);
716 assert(!loc->indirect);
717
718 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
719 pipeline->graphics.tess.offchip_layout);
720 }
721
722 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
723 if (loc->sgpr_idx != -1) {
724 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
725 assert(loc->num_sgprs == 1);
726 assert(!loc->indirect);
727
728 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
729 pipeline->graphics.tess.tcs_in_layout);
730 }
731 }
732
733 static void
734 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
735 struct radv_pipeline *pipeline)
736 {
737 struct radeon_winsys *ws = cmd_buffer->device->ws;
738 struct radv_shader_variant *gs;
739 uint64_t va;
740
741 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
742
743 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
744 if (!gs)
745 return;
746
747 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
748
749 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
750 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
751 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
752 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
753
754 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
755
756 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
757
758 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
759 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
760 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
761 radeon_emit(cmd_buffer->cs, 0);
762 radeon_emit(cmd_buffer->cs, 0);
763 radeon_emit(cmd_buffer->cs, 0);
764
765 uint32_t gs_num_invocations = gs->info.gs.invocations;
766 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
767 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
768 S_028B90_ENABLE(gs_num_invocations > 0));
769
770 va = ws->buffer_get_va(gs->bo);
771 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
772 si_cp_dma_prefetch(cmd_buffer, va, gs->code_size);
773 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
774 radeon_emit(cmd_buffer->cs, va >> 8);
775 radeon_emit(cmd_buffer->cs, va >> 40);
776 radeon_emit(cmd_buffer->cs, gs->rsrc1);
777 radeon_emit(cmd_buffer->cs, gs->rsrc2);
778
779 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
780
781 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
782 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
783 if (loc->sgpr_idx != -1) {
784 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
785 uint32_t num_entries = 64;
786 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
787
788 if (is_vi)
789 num_entries *= stride;
790
791 stride = S_008F04_STRIDE(stride);
792 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
793 radeon_emit(cmd_buffer->cs, stride);
794 radeon_emit(cmd_buffer->cs, num_entries);
795 }
796 }
797
798 static void
799 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
800 struct radv_pipeline *pipeline)
801 {
802 struct radeon_winsys *ws = cmd_buffer->device->ws;
803 struct radv_shader_variant *ps;
804 uint64_t va;
805 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
806 struct radv_blend_state *blend = &pipeline->graphics.blend;
807 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
808
809 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
810
811 va = ws->buffer_get_va(ps->bo);
812 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
813 si_cp_dma_prefetch(cmd_buffer, va, ps->code_size);
814
815 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
816 radeon_emit(cmd_buffer->cs, va >> 8);
817 radeon_emit(cmd_buffer->cs, va >> 40);
818 radeon_emit(cmd_buffer->cs, ps->rsrc1);
819 radeon_emit(cmd_buffer->cs, ps->rsrc2);
820
821 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
822 pipeline->graphics.db_shader_control);
823
824 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
825 ps->config.spi_ps_input_ena);
826
827 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
828 ps->config.spi_ps_input_addr);
829
830 if (ps->info.fs.force_persample)
831 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
832
833 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
834 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
835
836 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
837
838 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
839 pipeline->graphics.shader_z_format);
840
841 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
842
843 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
844 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
845
846 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
847 /* optimise this? */
848 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
849 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
850 }
851
852 if (pipeline->graphics.ps_input_cntl_num) {
853 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
854 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
855 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
856 }
857 }
858 }
859
860 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
861 struct radv_pipeline *pipeline)
862 {
863 uint32_t vtx_reuse_depth = 30;
864 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
865 return;
866
867 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
868 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
869 vtx_reuse_depth = 14;
870 }
871 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
872 vtx_reuse_depth);
873 }
874
875 static void
876 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
877 struct radv_pipeline *pipeline)
878 {
879 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
880 return;
881
882 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
883 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
884 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
885 radv_update_multisample_state(cmd_buffer, pipeline);
886 radv_emit_vertex_shader(cmd_buffer, pipeline);
887 radv_emit_tess_shaders(cmd_buffer, pipeline);
888 radv_emit_geometry_shader(cmd_buffer, pipeline);
889 radv_emit_fragment_shader(cmd_buffer, pipeline);
890 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
891
892 cmd_buffer->scratch_size_needed =
893 MAX2(cmd_buffer->scratch_size_needed,
894 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
895
896 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
897 S_0286E8_WAVES(pipeline->max_waves) |
898 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
899
900 if (!cmd_buffer->state.emitted_pipeline ||
901 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
902 pipeline->graphics.can_use_guardband)
903 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
904 cmd_buffer->state.emitted_pipeline = pipeline;
905 }
906
907 static void
908 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
909 {
910 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
911 cmd_buffer->state.dynamic.viewport.viewports);
912 }
913
914 static void
915 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
916 {
917 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
918 si_write_scissors(cmd_buffer->cs, 0, count,
919 cmd_buffer->state.dynamic.scissor.scissors,
920 cmd_buffer->state.dynamic.viewport.viewports,
921 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
922 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
923 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
924 }
925
926 static void
927 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
928 int index,
929 struct radv_color_buffer_info *cb)
930 {
931 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
932
933 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
934 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
935 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
936 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
937 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
938 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
939 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
940 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
941 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
942 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
943 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
944 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
945 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
946
947 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
948 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
949 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
950
951 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
952 cb->gfx9_epitch);
953 } else {
954 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
955 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
956 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
957 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
958 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
959 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
960 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
961 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
962 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
963 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
964 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
965 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
966
967 if (is_vi) { /* DCC BASE */
968 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
969 }
970 }
971 }
972
973 static void
974 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
975 struct radv_ds_buffer_info *ds,
976 struct radv_image *image,
977 VkImageLayout layout)
978 {
979 uint32_t db_z_info = ds->db_z_info;
980 uint32_t db_stencil_info = ds->db_stencil_info;
981
982 if (!radv_layout_has_htile(image, layout,
983 radv_image_queue_family_mask(image,
984 cmd_buffer->queue_family_index,
985 cmd_buffer->queue_family_index))) {
986 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
987 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
988 }
989
990 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
991
992 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
993 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
994 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
995 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
996 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
997
998 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
999 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1000 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1001 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1002 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1003 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1004 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1005 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1006 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1007 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1008 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1009
1010 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1011 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1012 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1013 } else {
1014 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1015
1016 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1017 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1018 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1019 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1020 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1021 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1022 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1023 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1024 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1025 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1026
1027 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1028 }
1029
1030 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1031 ds->pa_su_poly_offset_db_fmt_cntl);
1032 }
1033
1034 void
1035 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1036 struct radv_image *image,
1037 VkClearDepthStencilValue ds_clear_value,
1038 VkImageAspectFlags aspects)
1039 {
1040 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1041 va += image->offset + image->clear_value_offset;
1042 unsigned reg_offset = 0, reg_count = 0;
1043
1044 if (!image->surface.htile_size || !aspects)
1045 return;
1046
1047 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1048 ++reg_count;
1049 } else {
1050 ++reg_offset;
1051 va += 4;
1052 }
1053 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1054 ++reg_count;
1055
1056 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1057
1058 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1059 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1060 S_370_WR_CONFIRM(1) |
1061 S_370_ENGINE_SEL(V_370_PFP));
1062 radeon_emit(cmd_buffer->cs, va);
1063 radeon_emit(cmd_buffer->cs, va >> 32);
1064 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1065 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1066 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1067 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1068
1069 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1070 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1071 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1072 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1073 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1074 }
1075
1076 static void
1077 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1078 struct radv_image *image)
1079 {
1080 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1081 va += image->offset + image->clear_value_offset;
1082
1083 if (!image->surface.htile_size)
1084 return;
1085
1086 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1087
1088 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1089 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1090 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1091 COPY_DATA_COUNT_SEL);
1092 radeon_emit(cmd_buffer->cs, va);
1093 radeon_emit(cmd_buffer->cs, va >> 32);
1094 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1095 radeon_emit(cmd_buffer->cs, 0);
1096
1097 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1098 radeon_emit(cmd_buffer->cs, 0);
1099 }
1100
1101 void
1102 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1103 struct radv_image *image,
1104 int idx,
1105 uint32_t color_values[2])
1106 {
1107 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1108 va += image->offset + image->clear_value_offset;
1109
1110 if (!image->cmask.size && !image->surface.dcc_size)
1111 return;
1112
1113 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1114
1115 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1116 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1117 S_370_WR_CONFIRM(1) |
1118 S_370_ENGINE_SEL(V_370_PFP));
1119 radeon_emit(cmd_buffer->cs, va);
1120 radeon_emit(cmd_buffer->cs, va >> 32);
1121 radeon_emit(cmd_buffer->cs, color_values[0]);
1122 radeon_emit(cmd_buffer->cs, color_values[1]);
1123
1124 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1125 radeon_emit(cmd_buffer->cs, color_values[0]);
1126 radeon_emit(cmd_buffer->cs, color_values[1]);
1127 }
1128
1129 static void
1130 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1131 struct radv_image *image,
1132 int idx)
1133 {
1134 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1135 va += image->offset + image->clear_value_offset;
1136
1137 if (!image->cmask.size && !image->surface.dcc_size)
1138 return;
1139
1140 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1141 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1142
1143 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1144 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1145 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1146 COPY_DATA_COUNT_SEL);
1147 radeon_emit(cmd_buffer->cs, va);
1148 radeon_emit(cmd_buffer->cs, va >> 32);
1149 radeon_emit(cmd_buffer->cs, reg >> 2);
1150 radeon_emit(cmd_buffer->cs, 0);
1151
1152 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1153 radeon_emit(cmd_buffer->cs, 0);
1154 }
1155
1156 void
1157 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1158 {
1159 int i;
1160 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1161 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1162
1163 for (i = 0; i < subpass->color_count; ++i) {
1164 int idx = subpass->color_attachments[i].attachment;
1165 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1166
1167 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1168
1169 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1170 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1171
1172 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1173 }
1174
1175 for (i = subpass->color_count; i < 8; i++)
1176 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1177 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1178
1179 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1180 int idx = subpass->depth_stencil_attachment.attachment;
1181 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1182 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1183 struct radv_image *image = att->attachment->image;
1184 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1185 uint32_t queue_mask = radv_image_queue_family_mask(image,
1186 cmd_buffer->queue_family_index,
1187 cmd_buffer->queue_family_index);
1188 /* We currently don't support writing decompressed HTILE */
1189 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1190 radv_layout_is_htile_compressed(image, layout, queue_mask));
1191
1192 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1193
1194 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1195 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1196 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1197 }
1198 radv_load_depth_clear_regs(cmd_buffer, image);
1199 } else {
1200 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1201 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1202 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1203 }
1204 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1205 S_028208_BR_X(framebuffer->width) |
1206 S_028208_BR_Y(framebuffer->height));
1207
1208 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1209 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1210 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1211 }
1212 }
1213
1214 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1215 {
1216 uint32_t db_count_control;
1217
1218 if(!cmd_buffer->state.active_occlusion_queries) {
1219 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1220 db_count_control = 0;
1221 } else {
1222 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1223 }
1224 } else {
1225 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1226 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1227 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1228 S_028004_ZPASS_ENABLE(1) |
1229 S_028004_SLICE_EVEN_ENABLE(1) |
1230 S_028004_SLICE_ODD_ENABLE(1);
1231 } else {
1232 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1233 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1234 }
1235 }
1236
1237 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1238 }
1239
1240 static void
1241 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1242 {
1243 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1244
1245 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1246 return;
1247
1248 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1249 radv_emit_viewport(cmd_buffer);
1250
1251 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1252 radv_emit_scissor(cmd_buffer);
1253
1254 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1255 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1256 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1257 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1258 }
1259
1260 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1261 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1262 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1263 }
1264
1265 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1266 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1267 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1268 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1269 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1270 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1271 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1272 S_028430_STENCILOPVAL(1));
1273 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1274 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1275 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1276 S_028434_STENCILOPVAL_BF(1));
1277 }
1278
1279 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1280 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1281 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1282 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1283 }
1284
1285 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1286 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1287 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1288 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1289 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1290
1291 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1292 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1293 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1294 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1295 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1296 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1297 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1298 }
1299 }
1300
1301 cmd_buffer->state.dirty = 0;
1302 }
1303
1304 static void
1305 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1306 struct radv_pipeline *pipeline,
1307 int idx,
1308 uint64_t va,
1309 gl_shader_stage stage)
1310 {
1311 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1312 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1313
1314 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1315 return;
1316
1317 assert(!desc_set_loc->indirect);
1318 assert(desc_set_loc->num_sgprs == 2);
1319 radeon_set_sh_reg_seq(cmd_buffer->cs,
1320 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1321 radeon_emit(cmd_buffer->cs, va);
1322 radeon_emit(cmd_buffer->cs, va >> 32);
1323 }
1324
1325 static void
1326 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1327 VkShaderStageFlags stages,
1328 struct radv_descriptor_set *set,
1329 unsigned idx)
1330 {
1331 if (cmd_buffer->state.pipeline) {
1332 radv_foreach_stage(stage, stages) {
1333 if (cmd_buffer->state.pipeline->shaders[stage])
1334 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1335 idx, set->va,
1336 stage);
1337 }
1338 }
1339
1340 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1341 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1342 idx, set->va,
1343 MESA_SHADER_COMPUTE);
1344 }
1345
1346 static void
1347 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1348 {
1349 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1350 uint32_t *ptr = NULL;
1351 unsigned bo_offset;
1352
1353 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1354 &bo_offset,
1355 (void**) &ptr))
1356 return;
1357
1358 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1359 set->va += bo_offset;
1360
1361 memcpy(ptr, set->mapped_ptr, set->size);
1362 }
1363
1364 static void
1365 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1366 {
1367 uint32_t size = MAX_SETS * 2 * 4;
1368 uint32_t offset;
1369 void *ptr;
1370
1371 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1372 256, &offset, &ptr))
1373 return;
1374
1375 for (unsigned i = 0; i < MAX_SETS; i++) {
1376 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1377 uint64_t set_va = 0;
1378 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1379 if (set)
1380 set_va = set->va;
1381 uptr[0] = set_va & 0xffffffff;
1382 uptr[1] = set_va >> 32;
1383 }
1384
1385 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1386 va += offset;
1387
1388 if (cmd_buffer->state.pipeline) {
1389 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1390 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1391 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1392
1393 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1394 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1395 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1396
1397 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1398 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1399 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1400
1401 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1402 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1403 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1404
1405 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1406 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1407 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1408 }
1409
1410 if (cmd_buffer->state.compute_pipeline)
1411 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1412 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1413 }
1414
1415 static void
1416 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1417 VkShaderStageFlags stages)
1418 {
1419 unsigned i;
1420
1421 if (!cmd_buffer->state.descriptors_dirty)
1422 return;
1423
1424 if (cmd_buffer->state.push_descriptors_dirty)
1425 radv_flush_push_descriptors(cmd_buffer);
1426
1427 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1428 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1429 radv_flush_indirect_descriptor_sets(cmd_buffer);
1430 }
1431
1432 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1433 cmd_buffer->cs,
1434 MAX_SETS * MESA_SHADER_STAGES * 4);
1435
1436 for (i = 0; i < MAX_SETS; i++) {
1437 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1438 continue;
1439 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1440 if (!set)
1441 continue;
1442
1443 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1444 }
1445 cmd_buffer->state.descriptors_dirty = 0;
1446 cmd_buffer->state.push_descriptors_dirty = false;
1447 assert(cmd_buffer->cs->cdw <= cdw_max);
1448 }
1449
1450 static void
1451 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1452 struct radv_pipeline *pipeline,
1453 VkShaderStageFlags stages)
1454 {
1455 struct radv_pipeline_layout *layout = pipeline->layout;
1456 unsigned offset;
1457 void *ptr;
1458 uint64_t va;
1459
1460 stages &= cmd_buffer->push_constant_stages;
1461 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1462 return;
1463
1464 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1465 16 * layout->dynamic_offset_count,
1466 256, &offset, &ptr))
1467 return;
1468
1469 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1470 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1471 16 * layout->dynamic_offset_count);
1472
1473 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1474 va += offset;
1475
1476 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1477 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1478
1479 radv_foreach_stage(stage, stages) {
1480 if (pipeline->shaders[stage]) {
1481 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1482 AC_UD_PUSH_CONSTANTS, va);
1483 }
1484 }
1485
1486 cmd_buffer->push_constant_stages &= ~stages;
1487 assert(cmd_buffer->cs->cdw <= cdw_max);
1488 }
1489
1490 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1491 bool indexed_draw)
1492 {
1493 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1494
1495 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1496 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1497 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1498 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1499 primitive_reset_en);
1500 } else {
1501 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1502 primitive_reset_en);
1503 }
1504 }
1505
1506 if (primitive_reset_en) {
1507 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1508
1509 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1510 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1511 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1512 primitive_reset_index);
1513 }
1514 }
1515 }
1516
1517 static void
1518 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1519 bool indexed_draw, bool instanced_draw,
1520 bool indirect_draw,
1521 uint32_t draw_vertex_count)
1522 {
1523 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1524 struct radv_device *device = cmd_buffer->device;
1525 uint32_t ia_multi_vgt_param;
1526
1527 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1528 cmd_buffer->cs, 4096);
1529
1530 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1531 cmd_buffer->state.pipeline->num_vertex_attribs &&
1532 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1533 unsigned vb_offset;
1534 void *vb_ptr;
1535 uint32_t i = 0;
1536 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1537 uint64_t va;
1538
1539 /* allocate some descriptor state for vertex buffers */
1540 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1541 &vb_offset, &vb_ptr);
1542
1543 for (i = 0; i < num_attribs; i++) {
1544 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1545 uint32_t offset;
1546 int vb = cmd_buffer->state.pipeline->va_binding[i];
1547 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1548 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1549
1550 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1551 va = device->ws->buffer_get_va(buffer->bo);
1552
1553 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1554 va += offset + buffer->offset;
1555 desc[0] = va;
1556 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1557 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1558 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1559 else
1560 desc[2] = buffer->size - offset;
1561 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1562 }
1563
1564 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1565 va += vb_offset;
1566
1567 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1568 AC_UD_VS_VERTEX_BUFFERS, va);
1569 }
1570
1571 cmd_buffer->state.vb_dirty = 0;
1572 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1573 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1574
1575 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1576 radv_emit_framebuffer_state(cmd_buffer);
1577
1578 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1579 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1580 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1581 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1582 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1583 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1584 else
1585 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1586 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1587 }
1588
1589 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1590 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1591
1592 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1593 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1594 } else {
1595 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1596 }
1597 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1598 }
1599
1600 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1601
1602 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1603
1604 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1605 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1606 VK_SHADER_STAGE_ALL_GRAPHICS);
1607
1608 assert(cmd_buffer->cs->cdw <= cdw_max);
1609
1610 si_emit_cache_flush(cmd_buffer);
1611 }
1612
1613 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1614 VkPipelineStageFlags src_stage_mask)
1615 {
1616 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1617 VK_PIPELINE_STAGE_TRANSFER_BIT |
1618 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1619 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1620 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1621 }
1622
1623 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1624 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1625 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1626 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1627 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1628 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1629 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1630 VK_PIPELINE_STAGE_TRANSFER_BIT |
1631 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1632 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1633 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1634 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1635 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1636 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1637 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1638 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1639 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1640 }
1641 }
1642
1643 static enum radv_cmd_flush_bits
1644 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1645 VkAccessFlags src_flags)
1646 {
1647 enum radv_cmd_flush_bits flush_bits = 0;
1648 uint32_t b;
1649 for_each_bit(b, src_flags) {
1650 switch ((VkAccessFlagBits)(1 << b)) {
1651 case VK_ACCESS_SHADER_WRITE_BIT:
1652 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1653 break;
1654 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1655 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1656 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1657 break;
1658 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1659 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1660 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1661 break;
1662 case VK_ACCESS_TRANSFER_WRITE_BIT:
1663 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1664 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1665 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1666 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1667 RADV_CMD_FLAG_INV_GLOBAL_L2;
1668 break;
1669 default:
1670 break;
1671 }
1672 }
1673 return flush_bits;
1674 }
1675
1676 static enum radv_cmd_flush_bits
1677 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1678 VkAccessFlags dst_flags,
1679 struct radv_image *image)
1680 {
1681 enum radv_cmd_flush_bits flush_bits = 0;
1682 uint32_t b;
1683 for_each_bit(b, dst_flags) {
1684 switch ((VkAccessFlagBits)(1 << b)) {
1685 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1686 case VK_ACCESS_INDEX_READ_BIT:
1687 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1688 break;
1689 case VK_ACCESS_UNIFORM_READ_BIT:
1690 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1691 break;
1692 case VK_ACCESS_SHADER_READ_BIT:
1693 case VK_ACCESS_TRANSFER_READ_BIT:
1694 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1695 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1696 RADV_CMD_FLAG_INV_GLOBAL_L2;
1697 break;
1698 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1699 /* TODO: change to image && when the image gets passed
1700 * through from the subpass. */
1701 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1702 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1703 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1704 break;
1705 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1706 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1707 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1708 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1709 break;
1710 default:
1711 break;
1712 }
1713 }
1714 return flush_bits;
1715 }
1716
1717 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1718 {
1719 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1720 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1721 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1722 NULL);
1723 }
1724
1725 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1726 VkAttachmentReference att)
1727 {
1728 unsigned idx = att.attachment;
1729 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1730 VkImageSubresourceRange range;
1731 range.aspectMask = 0;
1732 range.baseMipLevel = view->base_mip;
1733 range.levelCount = 1;
1734 range.baseArrayLayer = view->base_layer;
1735 range.layerCount = cmd_buffer->state.framebuffer->layers;
1736
1737 radv_handle_image_transition(cmd_buffer,
1738 view->image,
1739 cmd_buffer->state.attachments[idx].current_layout,
1740 att.layout, 0, 0, &range,
1741 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1742
1743 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1744
1745
1746 }
1747
1748 void
1749 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1750 const struct radv_subpass *subpass, bool transitions)
1751 {
1752 if (transitions) {
1753 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1754
1755 for (unsigned i = 0; i < subpass->color_count; ++i) {
1756 radv_handle_subpass_image_transition(cmd_buffer,
1757 subpass->color_attachments[i]);
1758 }
1759
1760 for (unsigned i = 0; i < subpass->input_count; ++i) {
1761 radv_handle_subpass_image_transition(cmd_buffer,
1762 subpass->input_attachments[i]);
1763 }
1764
1765 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1766 radv_handle_subpass_image_transition(cmd_buffer,
1767 subpass->depth_stencil_attachment);
1768 }
1769 }
1770
1771 cmd_buffer->state.subpass = subpass;
1772
1773 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1774 }
1775
1776 static void
1777 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1778 struct radv_render_pass *pass,
1779 const VkRenderPassBeginInfo *info)
1780 {
1781 struct radv_cmd_state *state = &cmd_buffer->state;
1782
1783 if (pass->attachment_count == 0) {
1784 state->attachments = NULL;
1785 return;
1786 }
1787
1788 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1789 pass->attachment_count *
1790 sizeof(state->attachments[0]),
1791 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1792 if (state->attachments == NULL) {
1793 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1794 abort();
1795 }
1796
1797 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1798 struct radv_render_pass_attachment *att = &pass->attachments[i];
1799 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1800 VkImageAspectFlags clear_aspects = 0;
1801
1802 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1803 /* color attachment */
1804 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1805 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1806 }
1807 } else {
1808 /* depthstencil attachment */
1809 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1810 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1811 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1812 }
1813 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1814 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1815 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1816 }
1817 }
1818
1819 state->attachments[i].pending_clear_aspects = clear_aspects;
1820 if (clear_aspects && info) {
1821 assert(info->clearValueCount > i);
1822 state->attachments[i].clear_value = info->pClearValues[i];
1823 }
1824
1825 state->attachments[i].current_layout = att->initial_layout;
1826 }
1827 }
1828
1829 VkResult radv_AllocateCommandBuffers(
1830 VkDevice _device,
1831 const VkCommandBufferAllocateInfo *pAllocateInfo,
1832 VkCommandBuffer *pCommandBuffers)
1833 {
1834 RADV_FROM_HANDLE(radv_device, device, _device);
1835 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1836
1837 VkResult result = VK_SUCCESS;
1838 uint32_t i;
1839
1840 memset(pCommandBuffers, 0,
1841 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1842
1843 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1844
1845 if (!list_empty(&pool->free_cmd_buffers)) {
1846 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1847
1848 list_del(&cmd_buffer->pool_link);
1849 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1850
1851 radv_reset_cmd_buffer(cmd_buffer);
1852 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1853 cmd_buffer->level = pAllocateInfo->level;
1854
1855 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1856 result = VK_SUCCESS;
1857 } else {
1858 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1859 &pCommandBuffers[i]);
1860 }
1861 if (result != VK_SUCCESS)
1862 break;
1863 }
1864
1865 if (result != VK_SUCCESS)
1866 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1867 i, pCommandBuffers);
1868
1869 return result;
1870 }
1871
1872 void radv_FreeCommandBuffers(
1873 VkDevice device,
1874 VkCommandPool commandPool,
1875 uint32_t commandBufferCount,
1876 const VkCommandBuffer *pCommandBuffers)
1877 {
1878 for (uint32_t i = 0; i < commandBufferCount; i++) {
1879 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1880
1881 if (cmd_buffer) {
1882 if (cmd_buffer->pool) {
1883 list_del(&cmd_buffer->pool_link);
1884 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1885 } else
1886 radv_cmd_buffer_destroy(cmd_buffer);
1887
1888 }
1889 }
1890 }
1891
1892 VkResult radv_ResetCommandBuffer(
1893 VkCommandBuffer commandBuffer,
1894 VkCommandBufferResetFlags flags)
1895 {
1896 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1897 radv_reset_cmd_buffer(cmd_buffer);
1898 return VK_SUCCESS;
1899 }
1900
1901 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1902 {
1903 struct radv_device *device = cmd_buffer->device;
1904 if (device->gfx_init) {
1905 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1906 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1907 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1908 radeon_emit(cmd_buffer->cs, va);
1909 radeon_emit(cmd_buffer->cs, va >> 32);
1910 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1911 } else
1912 si_init_config(cmd_buffer);
1913 }
1914
1915 VkResult radv_BeginCommandBuffer(
1916 VkCommandBuffer commandBuffer,
1917 const VkCommandBufferBeginInfo *pBeginInfo)
1918 {
1919 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1920 radv_reset_cmd_buffer(cmd_buffer);
1921
1922 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1923 cmd_buffer->state.last_primitive_reset_en = -1;
1924
1925 /* setup initial configuration into command buffer */
1926 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1927 switch (cmd_buffer->queue_family_index) {
1928 case RADV_QUEUE_GENERAL:
1929 emit_gfx_buffer_state(cmd_buffer);
1930 radv_set_db_count_control(cmd_buffer);
1931 break;
1932 case RADV_QUEUE_COMPUTE:
1933 si_init_compute(cmd_buffer);
1934 break;
1935 case RADV_QUEUE_TRANSFER:
1936 default:
1937 break;
1938 }
1939 }
1940
1941 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1942 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1943 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1944
1945 struct radv_subpass *subpass =
1946 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1947
1948 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1949 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1950 }
1951
1952 radv_cmd_buffer_trace_emit(cmd_buffer);
1953 return VK_SUCCESS;
1954 }
1955
1956 void radv_CmdBindVertexBuffers(
1957 VkCommandBuffer commandBuffer,
1958 uint32_t firstBinding,
1959 uint32_t bindingCount,
1960 const VkBuffer* pBuffers,
1961 const VkDeviceSize* pOffsets)
1962 {
1963 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1964 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1965
1966 /* We have to defer setting up vertex buffer since we need the buffer
1967 * stride from the pipeline. */
1968
1969 assert(firstBinding + bindingCount < MAX_VBS);
1970 for (uint32_t i = 0; i < bindingCount; i++) {
1971 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1972 vb[firstBinding + i].offset = pOffsets[i];
1973 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1974 }
1975 }
1976
1977 void radv_CmdBindIndexBuffer(
1978 VkCommandBuffer commandBuffer,
1979 VkBuffer buffer,
1980 VkDeviceSize offset,
1981 VkIndexType indexType)
1982 {
1983 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1984
1985 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1986 cmd_buffer->state.index_offset = offset;
1987 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1988 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1989 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1990 }
1991
1992
1993 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1994 struct radv_descriptor_set *set,
1995 unsigned idx)
1996 {
1997 struct radeon_winsys *ws = cmd_buffer->device->ws;
1998
1999 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2000
2001 cmd_buffer->state.descriptors[idx] = set;
2002 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2003 if (!set)
2004 return;
2005
2006 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2007 if (set->descriptors[j])
2008 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2009
2010 if(set->bo)
2011 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2012 }
2013
2014 void radv_CmdBindDescriptorSets(
2015 VkCommandBuffer commandBuffer,
2016 VkPipelineBindPoint pipelineBindPoint,
2017 VkPipelineLayout _layout,
2018 uint32_t firstSet,
2019 uint32_t descriptorSetCount,
2020 const VkDescriptorSet* pDescriptorSets,
2021 uint32_t dynamicOffsetCount,
2022 const uint32_t* pDynamicOffsets)
2023 {
2024 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2025 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2026 unsigned dyn_idx = 0;
2027
2028 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2029 unsigned idx = i + firstSet;
2030 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2031 radv_bind_descriptor_set(cmd_buffer, set, idx);
2032
2033 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2034 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2035 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2036 assert(dyn_idx < dynamicOffsetCount);
2037
2038 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2039 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2040 dst[0] = va;
2041 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2042 dst[2] = range->size;
2043 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2044 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2045 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2046 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2047 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2048 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2049 cmd_buffer->push_constant_stages |=
2050 set->layout->dynamic_shader_stages;
2051 }
2052 }
2053 }
2054
2055 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2056 struct radv_descriptor_set *set,
2057 struct radv_descriptor_set_layout *layout)
2058 {
2059 set->size = layout->size;
2060 set->layout = layout;
2061
2062 if (cmd_buffer->push_descriptors.capacity < set->size) {
2063 size_t new_size = MAX2(set->size, 1024);
2064 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2065 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2066
2067 free(set->mapped_ptr);
2068 set->mapped_ptr = malloc(new_size);
2069
2070 if (!set->mapped_ptr) {
2071 cmd_buffer->push_descriptors.capacity = 0;
2072 cmd_buffer->record_fail = true;
2073 return false;
2074 }
2075
2076 cmd_buffer->push_descriptors.capacity = new_size;
2077 }
2078
2079 return true;
2080 }
2081
2082 void radv_meta_push_descriptor_set(
2083 struct radv_cmd_buffer* cmd_buffer,
2084 VkPipelineBindPoint pipelineBindPoint,
2085 VkPipelineLayout _layout,
2086 uint32_t set,
2087 uint32_t descriptorWriteCount,
2088 const VkWriteDescriptorSet* pDescriptorWrites)
2089 {
2090 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2091 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2092 unsigned bo_offset;
2093
2094 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2095
2096 push_set->size = layout->set[set].layout->size;
2097 push_set->layout = layout->set[set].layout;
2098
2099 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2100 &bo_offset,
2101 (void**) &push_set->mapped_ptr))
2102 return;
2103
2104 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2105 push_set->va += bo_offset;
2106
2107 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2108 radv_descriptor_set_to_handle(push_set),
2109 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2110
2111 cmd_buffer->state.descriptors[set] = push_set;
2112 cmd_buffer->state.descriptors_dirty |= (1u << set);
2113 }
2114
2115 void radv_CmdPushDescriptorSetKHR(
2116 VkCommandBuffer commandBuffer,
2117 VkPipelineBindPoint pipelineBindPoint,
2118 VkPipelineLayout _layout,
2119 uint32_t set,
2120 uint32_t descriptorWriteCount,
2121 const VkWriteDescriptorSet* pDescriptorWrites)
2122 {
2123 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2124 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2125 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2126
2127 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2128
2129 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2130 return;
2131
2132 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2133 radv_descriptor_set_to_handle(push_set),
2134 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2135
2136 cmd_buffer->state.descriptors[set] = push_set;
2137 cmd_buffer->state.descriptors_dirty |= (1u << set);
2138 cmd_buffer->state.push_descriptors_dirty = true;
2139 }
2140
2141 void radv_CmdPushDescriptorSetWithTemplateKHR(
2142 VkCommandBuffer commandBuffer,
2143 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2144 VkPipelineLayout _layout,
2145 uint32_t set,
2146 const void* pData)
2147 {
2148 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2149 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2150 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2151
2152 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2153
2154 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2155 return;
2156
2157 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2158 descriptorUpdateTemplate, pData);
2159
2160 cmd_buffer->state.descriptors[set] = push_set;
2161 cmd_buffer->state.descriptors_dirty |= (1u << set);
2162 cmd_buffer->state.push_descriptors_dirty = true;
2163 }
2164
2165 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2166 VkPipelineLayout layout,
2167 VkShaderStageFlags stageFlags,
2168 uint32_t offset,
2169 uint32_t size,
2170 const void* pValues)
2171 {
2172 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2173 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2174 cmd_buffer->push_constant_stages |= stageFlags;
2175 }
2176
2177 VkResult radv_EndCommandBuffer(
2178 VkCommandBuffer commandBuffer)
2179 {
2180 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2181
2182 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
2183 si_emit_cache_flush(cmd_buffer);
2184
2185 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
2186 cmd_buffer->record_fail)
2187 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2188 return VK_SUCCESS;
2189 }
2190
2191 static void
2192 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2193 {
2194 struct radeon_winsys *ws = cmd_buffer->device->ws;
2195 struct radv_shader_variant *compute_shader;
2196 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2197 uint64_t va;
2198
2199 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2200 return;
2201
2202 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2203
2204 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2205 va = ws->buffer_get_va(compute_shader->bo);
2206
2207 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2208 si_cp_dma_prefetch(cmd_buffer, va, compute_shader->code_size);
2209
2210 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2211 cmd_buffer->cs, 16);
2212
2213 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2214 radeon_emit(cmd_buffer->cs, va >> 8);
2215 radeon_emit(cmd_buffer->cs, va >> 40);
2216
2217 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2218 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2219 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2220
2221
2222 cmd_buffer->compute_scratch_size_needed =
2223 MAX2(cmd_buffer->compute_scratch_size_needed,
2224 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2225
2226 /* change these once we have scratch support */
2227 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2228 S_00B860_WAVES(pipeline->max_waves) |
2229 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2230
2231 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2232 radeon_emit(cmd_buffer->cs,
2233 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2234 radeon_emit(cmd_buffer->cs,
2235 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2236 radeon_emit(cmd_buffer->cs,
2237 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2238
2239 assert(cmd_buffer->cs->cdw <= cdw_max);
2240 }
2241
2242 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2243 {
2244 for (unsigned i = 0; i < MAX_SETS; i++) {
2245 if (cmd_buffer->state.descriptors[i])
2246 cmd_buffer->state.descriptors_dirty |= (1u << i);
2247 }
2248 }
2249
2250 void radv_CmdBindPipeline(
2251 VkCommandBuffer commandBuffer,
2252 VkPipelineBindPoint pipelineBindPoint,
2253 VkPipeline _pipeline)
2254 {
2255 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2256 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2257
2258 radv_mark_descriptor_sets_dirty(cmd_buffer);
2259
2260 switch (pipelineBindPoint) {
2261 case VK_PIPELINE_BIND_POINT_COMPUTE:
2262 cmd_buffer->state.compute_pipeline = pipeline;
2263 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2264 break;
2265 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2266 cmd_buffer->state.pipeline = pipeline;
2267 if (!pipeline)
2268 break;
2269
2270 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2271 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2272
2273 /* Apply the dynamic state from the pipeline */
2274 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2275 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2276 &pipeline->dynamic_state,
2277 pipeline->dynamic_state_mask);
2278
2279 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2280 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2281 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2282 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2283
2284 if (radv_pipeline_has_tess(pipeline))
2285 cmd_buffer->tess_rings_needed = true;
2286
2287 if (radv_pipeline_has_gs(pipeline)) {
2288 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2289 AC_UD_SCRATCH_RING_OFFSETS);
2290 if (cmd_buffer->ring_offsets_idx == -1)
2291 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2292 else if (loc->sgpr_idx != -1)
2293 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2294 }
2295 break;
2296 default:
2297 assert(!"invalid bind point");
2298 break;
2299 }
2300 }
2301
2302 void radv_CmdSetViewport(
2303 VkCommandBuffer commandBuffer,
2304 uint32_t firstViewport,
2305 uint32_t viewportCount,
2306 const VkViewport* pViewports)
2307 {
2308 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2309
2310 const uint32_t total_count = firstViewport + viewportCount;
2311 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2312 cmd_buffer->state.dynamic.viewport.count = total_count;
2313
2314 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2315 pViewports, viewportCount * sizeof(*pViewports));
2316
2317 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2318 }
2319
2320 void radv_CmdSetScissor(
2321 VkCommandBuffer commandBuffer,
2322 uint32_t firstScissor,
2323 uint32_t scissorCount,
2324 const VkRect2D* pScissors)
2325 {
2326 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2327
2328 const uint32_t total_count = firstScissor + scissorCount;
2329 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2330 cmd_buffer->state.dynamic.scissor.count = total_count;
2331
2332 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2333 pScissors, scissorCount * sizeof(*pScissors));
2334 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2335 }
2336
2337 void radv_CmdSetLineWidth(
2338 VkCommandBuffer commandBuffer,
2339 float lineWidth)
2340 {
2341 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2342 cmd_buffer->state.dynamic.line_width = lineWidth;
2343 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2344 }
2345
2346 void radv_CmdSetDepthBias(
2347 VkCommandBuffer commandBuffer,
2348 float depthBiasConstantFactor,
2349 float depthBiasClamp,
2350 float depthBiasSlopeFactor)
2351 {
2352 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2353
2354 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2355 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2356 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2357
2358 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2359 }
2360
2361 void radv_CmdSetBlendConstants(
2362 VkCommandBuffer commandBuffer,
2363 const float blendConstants[4])
2364 {
2365 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2366
2367 memcpy(cmd_buffer->state.dynamic.blend_constants,
2368 blendConstants, sizeof(float) * 4);
2369
2370 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2371 }
2372
2373 void radv_CmdSetDepthBounds(
2374 VkCommandBuffer commandBuffer,
2375 float minDepthBounds,
2376 float maxDepthBounds)
2377 {
2378 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2379
2380 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2381 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2382
2383 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2384 }
2385
2386 void radv_CmdSetStencilCompareMask(
2387 VkCommandBuffer commandBuffer,
2388 VkStencilFaceFlags faceMask,
2389 uint32_t compareMask)
2390 {
2391 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2392
2393 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2394 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2395 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2396 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2397
2398 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2399 }
2400
2401 void radv_CmdSetStencilWriteMask(
2402 VkCommandBuffer commandBuffer,
2403 VkStencilFaceFlags faceMask,
2404 uint32_t writeMask)
2405 {
2406 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2407
2408 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2409 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2410 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2411 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2412
2413 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2414 }
2415
2416 void radv_CmdSetStencilReference(
2417 VkCommandBuffer commandBuffer,
2418 VkStencilFaceFlags faceMask,
2419 uint32_t reference)
2420 {
2421 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2422
2423 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2424 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2425 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2426 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2427
2428 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2429 }
2430
2431 void radv_CmdExecuteCommands(
2432 VkCommandBuffer commandBuffer,
2433 uint32_t commandBufferCount,
2434 const VkCommandBuffer* pCmdBuffers)
2435 {
2436 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2437
2438 /* Emit pending flushes on primary prior to executing secondary */
2439 si_emit_cache_flush(primary);
2440
2441 for (uint32_t i = 0; i < commandBufferCount; i++) {
2442 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2443
2444 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2445 secondary->scratch_size_needed);
2446 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2447 secondary->compute_scratch_size_needed);
2448
2449 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2450 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2451 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2452 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2453 if (secondary->tess_rings_needed)
2454 primary->tess_rings_needed = true;
2455 if (secondary->sample_positions_needed)
2456 primary->sample_positions_needed = true;
2457
2458 if (secondary->ring_offsets_idx != -1) {
2459 if (primary->ring_offsets_idx == -1)
2460 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2461 else
2462 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2463 }
2464 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2465 }
2466
2467 /* if we execute secondary we need to re-emit out pipelines */
2468 if (commandBufferCount) {
2469 primary->state.emitted_pipeline = NULL;
2470 primary->state.emitted_compute_pipeline = NULL;
2471 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2472 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2473 primary->state.last_primitive_reset_en = -1;
2474 primary->state.last_primitive_reset_index = 0;
2475 radv_mark_descriptor_sets_dirty(primary);
2476 }
2477 }
2478
2479 VkResult radv_CreateCommandPool(
2480 VkDevice _device,
2481 const VkCommandPoolCreateInfo* pCreateInfo,
2482 const VkAllocationCallbacks* pAllocator,
2483 VkCommandPool* pCmdPool)
2484 {
2485 RADV_FROM_HANDLE(radv_device, device, _device);
2486 struct radv_cmd_pool *pool;
2487
2488 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2489 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2490 if (pool == NULL)
2491 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2492
2493 if (pAllocator)
2494 pool->alloc = *pAllocator;
2495 else
2496 pool->alloc = device->alloc;
2497
2498 list_inithead(&pool->cmd_buffers);
2499 list_inithead(&pool->free_cmd_buffers);
2500
2501 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2502
2503 *pCmdPool = radv_cmd_pool_to_handle(pool);
2504
2505 return VK_SUCCESS;
2506
2507 }
2508
2509 void radv_DestroyCommandPool(
2510 VkDevice _device,
2511 VkCommandPool commandPool,
2512 const VkAllocationCallbacks* pAllocator)
2513 {
2514 RADV_FROM_HANDLE(radv_device, device, _device);
2515 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2516
2517 if (!pool)
2518 return;
2519
2520 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2521 &pool->cmd_buffers, pool_link) {
2522 radv_cmd_buffer_destroy(cmd_buffer);
2523 }
2524
2525 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2526 &pool->free_cmd_buffers, pool_link) {
2527 radv_cmd_buffer_destroy(cmd_buffer);
2528 }
2529
2530 vk_free2(&device->alloc, pAllocator, pool);
2531 }
2532
2533 VkResult radv_ResetCommandPool(
2534 VkDevice device,
2535 VkCommandPool commandPool,
2536 VkCommandPoolResetFlags flags)
2537 {
2538 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2539
2540 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2541 &pool->cmd_buffers, pool_link) {
2542 radv_reset_cmd_buffer(cmd_buffer);
2543 }
2544
2545 return VK_SUCCESS;
2546 }
2547
2548 void radv_TrimCommandPoolKHR(
2549 VkDevice device,
2550 VkCommandPool commandPool,
2551 VkCommandPoolTrimFlagsKHR flags)
2552 {
2553 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2554
2555 if (!pool)
2556 return;
2557
2558 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2559 &pool->free_cmd_buffers, pool_link) {
2560 radv_cmd_buffer_destroy(cmd_buffer);
2561 }
2562 }
2563
2564 void radv_CmdBeginRenderPass(
2565 VkCommandBuffer commandBuffer,
2566 const VkRenderPassBeginInfo* pRenderPassBegin,
2567 VkSubpassContents contents)
2568 {
2569 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2570 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2571 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2572
2573 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2574 cmd_buffer->cs, 2048);
2575
2576 cmd_buffer->state.framebuffer = framebuffer;
2577 cmd_buffer->state.pass = pass;
2578 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2579 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2580
2581 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2582 assert(cmd_buffer->cs->cdw <= cdw_max);
2583
2584 radv_cmd_buffer_clear_subpass(cmd_buffer);
2585 }
2586
2587 void radv_CmdNextSubpass(
2588 VkCommandBuffer commandBuffer,
2589 VkSubpassContents contents)
2590 {
2591 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2592
2593 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2594
2595 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2596 2048);
2597
2598 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2599 radv_cmd_buffer_clear_subpass(cmd_buffer);
2600 }
2601
2602 void radv_CmdDraw(
2603 VkCommandBuffer commandBuffer,
2604 uint32_t vertexCount,
2605 uint32_t instanceCount,
2606 uint32_t firstVertex,
2607 uint32_t firstInstance)
2608 {
2609 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2610
2611 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2612
2613 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2614
2615 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2616 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2617 if (loc->sgpr_idx != -1) {
2618 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2619 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2620 int vs_num = 2;
2621 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2622 vs_num = 3;
2623
2624 assert (loc->num_sgprs == vs_num);
2625 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
2626 radeon_emit(cmd_buffer->cs, firstVertex);
2627 radeon_emit(cmd_buffer->cs, firstInstance);
2628 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2629 radeon_emit(cmd_buffer->cs, 0);
2630 }
2631 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2632 radeon_emit(cmd_buffer->cs, instanceCount);
2633
2634 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2635 radeon_emit(cmd_buffer->cs, vertexCount);
2636 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2637 S_0287F0_USE_OPAQUE(0));
2638
2639 assert(cmd_buffer->cs->cdw <= cdw_max);
2640
2641 radv_cmd_buffer_trace_emit(cmd_buffer);
2642 }
2643
2644 static
2645 uint32_t radv_get_max_index_count(struct radv_cmd_buffer *cmd_buffer) {
2646 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2647 return (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) >> index_size_shift;
2648 }
2649
2650 void radv_CmdDrawIndexed(
2651 VkCommandBuffer commandBuffer,
2652 uint32_t indexCount,
2653 uint32_t instanceCount,
2654 uint32_t firstIndex,
2655 int32_t vertexOffset,
2656 uint32_t firstInstance)
2657 {
2658 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2659 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2660 uint32_t index_max_size = radv_get_max_index_count(cmd_buffer);
2661 uint64_t index_va;
2662
2663 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2664
2665 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2666
2667 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2668 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
2669 2, cmd_buffer->state.index_type);
2670 } else {
2671 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2672 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2673 }
2674
2675 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2676 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2677 if (loc->sgpr_idx != -1) {
2678 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2679 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2680 int vs_num = 2;
2681 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2682 vs_num = 3;
2683
2684 assert (loc->num_sgprs == vs_num);
2685 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
2686 radeon_emit(cmd_buffer->cs, vertexOffset);
2687 radeon_emit(cmd_buffer->cs, firstInstance);
2688 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2689 radeon_emit(cmd_buffer->cs, 0);
2690 }
2691 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2692 radeon_emit(cmd_buffer->cs, instanceCount);
2693
2694 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2695 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2696 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2697 radeon_emit(cmd_buffer->cs, index_max_size);
2698 radeon_emit(cmd_buffer->cs, index_va);
2699 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2700 radeon_emit(cmd_buffer->cs, indexCount);
2701 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2702
2703 assert(cmd_buffer->cs->cdw <= cdw_max);
2704 radv_cmd_buffer_trace_emit(cmd_buffer);
2705 }
2706
2707 static void
2708 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2709 VkBuffer _buffer,
2710 VkDeviceSize offset,
2711 VkBuffer _count_buffer,
2712 VkDeviceSize count_offset,
2713 uint32_t draw_count,
2714 uint32_t stride,
2715 bool indexed)
2716 {
2717 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2718 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2719 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2720 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2721 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2722 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2723 indirect_va += offset + buffer->offset;
2724 uint64_t count_va = 0;
2725
2726 if (count_buffer) {
2727 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2728 count_va += count_offset + count_buffer->offset;
2729 }
2730
2731 if (!draw_count)
2732 return;
2733
2734 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2735
2736 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2737 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2738 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2739 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2740 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2741 assert(loc->sgpr_idx != -1);
2742 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2743 radeon_emit(cs, 1);
2744 radeon_emit(cs, indirect_va);
2745 radeon_emit(cs, indirect_va >> 32);
2746
2747 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2748 PKT3_DRAW_INDIRECT_MULTI,
2749 8, false));
2750 radeon_emit(cs, 0);
2751 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2752 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2753 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2754 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2755 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2756 radeon_emit(cs, draw_count); /* count */
2757 radeon_emit(cs, count_va); /* count_addr */
2758 radeon_emit(cs, count_va >> 32);
2759 radeon_emit(cs, stride); /* stride */
2760 radeon_emit(cs, di_src_sel);
2761 radv_cmd_buffer_trace_emit(cmd_buffer);
2762 }
2763
2764 static void
2765 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2766 VkBuffer buffer,
2767 VkDeviceSize offset,
2768 VkBuffer countBuffer,
2769 VkDeviceSize countBufferOffset,
2770 uint32_t maxDrawCount,
2771 uint32_t stride)
2772 {
2773 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2774 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2775
2776 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2777 cmd_buffer->cs, 14);
2778
2779 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2780 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2781
2782 assert(cmd_buffer->cs->cdw <= cdw_max);
2783 }
2784
2785 static void
2786 radv_cmd_draw_indexed_indirect_count(
2787 VkCommandBuffer commandBuffer,
2788 VkBuffer buffer,
2789 VkDeviceSize offset,
2790 VkBuffer countBuffer,
2791 VkDeviceSize countBufferOffset,
2792 uint32_t maxDrawCount,
2793 uint32_t stride)
2794 {
2795 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2796 uint32_t index_max_size = radv_get_max_index_count(cmd_buffer);
2797 uint64_t index_va;
2798 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2799
2800 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2801 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2802
2803 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2804
2805 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2806 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2807
2808 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2809 radeon_emit(cmd_buffer->cs, index_va);
2810 radeon_emit(cmd_buffer->cs, index_va >> 32);
2811
2812 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2813 radeon_emit(cmd_buffer->cs, index_max_size);
2814
2815 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2816 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2817
2818 assert(cmd_buffer->cs->cdw <= cdw_max);
2819 }
2820
2821 void radv_CmdDrawIndirect(
2822 VkCommandBuffer commandBuffer,
2823 VkBuffer buffer,
2824 VkDeviceSize offset,
2825 uint32_t drawCount,
2826 uint32_t stride)
2827 {
2828 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2829 VK_NULL_HANDLE, 0, drawCount, stride);
2830 }
2831
2832 void radv_CmdDrawIndexedIndirect(
2833 VkCommandBuffer commandBuffer,
2834 VkBuffer buffer,
2835 VkDeviceSize offset,
2836 uint32_t drawCount,
2837 uint32_t stride)
2838 {
2839 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2840 VK_NULL_HANDLE, 0, drawCount, stride);
2841 }
2842
2843 void radv_CmdDrawIndirectCountAMD(
2844 VkCommandBuffer commandBuffer,
2845 VkBuffer buffer,
2846 VkDeviceSize offset,
2847 VkBuffer countBuffer,
2848 VkDeviceSize countBufferOffset,
2849 uint32_t maxDrawCount,
2850 uint32_t stride)
2851 {
2852 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2853 countBuffer, countBufferOffset,
2854 maxDrawCount, stride);
2855 }
2856
2857 void radv_CmdDrawIndexedIndirectCountAMD(
2858 VkCommandBuffer commandBuffer,
2859 VkBuffer buffer,
2860 VkDeviceSize offset,
2861 VkBuffer countBuffer,
2862 VkDeviceSize countBufferOffset,
2863 uint32_t maxDrawCount,
2864 uint32_t stride)
2865 {
2866 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2867 countBuffer, countBufferOffset,
2868 maxDrawCount, stride);
2869 }
2870
2871 static void
2872 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2873 {
2874 radv_emit_compute_pipeline(cmd_buffer);
2875 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
2876 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2877 VK_SHADER_STAGE_COMPUTE_BIT);
2878 si_emit_cache_flush(cmd_buffer);
2879 }
2880
2881 void radv_CmdDispatch(
2882 VkCommandBuffer commandBuffer,
2883 uint32_t x,
2884 uint32_t y,
2885 uint32_t z)
2886 {
2887 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2888
2889 radv_flush_compute_state(cmd_buffer);
2890
2891 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2892
2893 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2894 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2895 if (loc->sgpr_idx != -1) {
2896 assert(!loc->indirect);
2897 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2898 assert(loc->num_sgprs == grid_used);
2899 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2900 radeon_emit(cmd_buffer->cs, x);
2901 if (grid_used > 1)
2902 radeon_emit(cmd_buffer->cs, y);
2903 if (grid_used > 2)
2904 radeon_emit(cmd_buffer->cs, z);
2905 }
2906
2907 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2908 PKT3_SHADER_TYPE_S(1));
2909 radeon_emit(cmd_buffer->cs, x);
2910 radeon_emit(cmd_buffer->cs, y);
2911 radeon_emit(cmd_buffer->cs, z);
2912 radeon_emit(cmd_buffer->cs, 1);
2913
2914 assert(cmd_buffer->cs->cdw <= cdw_max);
2915 radv_cmd_buffer_trace_emit(cmd_buffer);
2916 }
2917
2918 void radv_CmdDispatchIndirect(
2919 VkCommandBuffer commandBuffer,
2920 VkBuffer _buffer,
2921 VkDeviceSize offset)
2922 {
2923 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2924 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2925 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2926 va += buffer->offset + offset;
2927
2928 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2929
2930 radv_flush_compute_state(cmd_buffer);
2931
2932 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2933 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2934 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2935 if (loc->sgpr_idx != -1) {
2936 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2937 for (unsigned i = 0; i < grid_used; ++i) {
2938 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2939 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2940 COPY_DATA_DST_SEL(COPY_DATA_REG));
2941 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2942 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2943 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2944 radeon_emit(cmd_buffer->cs, 0);
2945 }
2946 }
2947
2948 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2949 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2950 PKT3_SHADER_TYPE_S(1));
2951 radeon_emit(cmd_buffer->cs, va);
2952 radeon_emit(cmd_buffer->cs, va >> 32);
2953 radeon_emit(cmd_buffer->cs, 1);
2954 } else {
2955 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2956 PKT3_SHADER_TYPE_S(1));
2957 radeon_emit(cmd_buffer->cs, 1);
2958 radeon_emit(cmd_buffer->cs, va);
2959 radeon_emit(cmd_buffer->cs, va >> 32);
2960
2961 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2962 PKT3_SHADER_TYPE_S(1));
2963 radeon_emit(cmd_buffer->cs, 0);
2964 radeon_emit(cmd_buffer->cs, 1);
2965 }
2966
2967 assert(cmd_buffer->cs->cdw <= cdw_max);
2968 radv_cmd_buffer_trace_emit(cmd_buffer);
2969 }
2970
2971 void radv_unaligned_dispatch(
2972 struct radv_cmd_buffer *cmd_buffer,
2973 uint32_t x,
2974 uint32_t y,
2975 uint32_t z)
2976 {
2977 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2978 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2979 uint32_t blocks[3], remainder[3];
2980
2981 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2982 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2983 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2984
2985 /* If aligned, these should be an entire block size, not 0 */
2986 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2987 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2988 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2989
2990 radv_flush_compute_state(cmd_buffer);
2991
2992 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2993
2994 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2995 radeon_emit(cmd_buffer->cs,
2996 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2997 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2998 radeon_emit(cmd_buffer->cs,
2999 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
3000 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3001 radeon_emit(cmd_buffer->cs,
3002 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
3003 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3004
3005 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3006 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3007 if (loc->sgpr_idx != -1) {
3008 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3009 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
3010 radeon_emit(cmd_buffer->cs, blocks[0]);
3011 if (grid_used > 1)
3012 radeon_emit(cmd_buffer->cs, blocks[1]);
3013 if (grid_used > 2)
3014 radeon_emit(cmd_buffer->cs, blocks[2]);
3015 }
3016 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3017 PKT3_SHADER_TYPE_S(1));
3018 radeon_emit(cmd_buffer->cs, blocks[0]);
3019 radeon_emit(cmd_buffer->cs, blocks[1]);
3020 radeon_emit(cmd_buffer->cs, blocks[2]);
3021 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
3022 S_00B800_PARTIAL_TG_EN(1));
3023
3024 assert(cmd_buffer->cs->cdw <= cdw_max);
3025 radv_cmd_buffer_trace_emit(cmd_buffer);
3026 }
3027
3028 void radv_CmdEndRenderPass(
3029 VkCommandBuffer commandBuffer)
3030 {
3031 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3032
3033 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3034
3035 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3036
3037 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3038 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3039 radv_handle_subpass_image_transition(cmd_buffer,
3040 (VkAttachmentReference){i, layout});
3041 }
3042
3043 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3044
3045 cmd_buffer->state.pass = NULL;
3046 cmd_buffer->state.subpass = NULL;
3047 cmd_buffer->state.attachments = NULL;
3048 cmd_buffer->state.framebuffer = NULL;
3049 }
3050
3051 /*
3052 * For HTILE we have the following interesting clear words:
3053 * 0x0000030f: Uncompressed.
3054 * 0xfffffff0: Clear depth to 1.0
3055 * 0x00000000: Clear depth to 0.0
3056 */
3057 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3058 struct radv_image *image,
3059 const VkImageSubresourceRange *range,
3060 uint32_t clear_word)
3061 {
3062 assert(range->baseMipLevel == 0);
3063 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3064 unsigned layer_count = radv_get_layerCount(image, range);
3065 uint64_t size = image->surface.htile_slice_size * layer_count;
3066 uint64_t offset = image->offset + image->htile_offset +
3067 image->surface.htile_slice_size * range->baseArrayLayer;
3068
3069 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3070 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3071
3072 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3073
3074 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3075 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3076 RADV_CMD_FLAG_INV_VMEM_L1 |
3077 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3078 }
3079
3080 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3081 struct radv_image *image,
3082 VkImageLayout src_layout,
3083 VkImageLayout dst_layout,
3084 unsigned src_queue_mask,
3085 unsigned dst_queue_mask,
3086 const VkImageSubresourceRange *range,
3087 VkImageAspectFlags pending_clears)
3088 {
3089 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3090 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3091 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3092 cmd_buffer->state.render_area.extent.width == image->info.width &&
3093 cmd_buffer->state.render_area.extent.height == image->info.height) {
3094 /* The clear will initialize htile. */
3095 return;
3096 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3097 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3098 /* TODO: merge with the clear if applicable */
3099 radv_initialize_htile(cmd_buffer, image, range, 0);
3100 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3101 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3102 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3103 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3104 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3105 VkImageSubresourceRange local_range = *range;
3106 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3107 local_range.baseMipLevel = 0;
3108 local_range.levelCount = 1;
3109
3110 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3111 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3112
3113 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3114
3115 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3116 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3117 }
3118 }
3119
3120 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3121 struct radv_image *image, uint32_t value)
3122 {
3123 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3124 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3125
3126 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3127 image->cmask.size, value);
3128
3129 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3130 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3131 RADV_CMD_FLAG_INV_VMEM_L1 |
3132 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3133 }
3134
3135 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3136 struct radv_image *image,
3137 VkImageLayout src_layout,
3138 VkImageLayout dst_layout,
3139 unsigned src_queue_mask,
3140 unsigned dst_queue_mask,
3141 const VkImageSubresourceRange *range,
3142 VkImageAspectFlags pending_clears)
3143 {
3144 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3145 if (image->fmask.size)
3146 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3147 else
3148 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3149 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3150 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3151 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3152 }
3153 }
3154
3155 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3156 struct radv_image *image, uint32_t value)
3157 {
3158
3159 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3160 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3161
3162 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3163 image->surface.dcc_size, value);
3164
3165 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3166 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3167 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3168 RADV_CMD_FLAG_INV_VMEM_L1 |
3169 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3170 }
3171
3172 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3173 struct radv_image *image,
3174 VkImageLayout src_layout,
3175 VkImageLayout dst_layout,
3176 unsigned src_queue_mask,
3177 unsigned dst_queue_mask,
3178 const VkImageSubresourceRange *range,
3179 VkImageAspectFlags pending_clears)
3180 {
3181 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3182 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3183 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3184 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3185 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3186 }
3187 }
3188
3189 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3190 struct radv_image *image,
3191 VkImageLayout src_layout,
3192 VkImageLayout dst_layout,
3193 uint32_t src_family,
3194 uint32_t dst_family,
3195 const VkImageSubresourceRange *range,
3196 VkImageAspectFlags pending_clears)
3197 {
3198 if (image->exclusive && src_family != dst_family) {
3199 /* This is an acquire or a release operation and there will be
3200 * a corresponding release/acquire. Do the transition in the
3201 * most flexible queue. */
3202
3203 assert(src_family == cmd_buffer->queue_family_index ||
3204 dst_family == cmd_buffer->queue_family_index);
3205
3206 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3207 return;
3208
3209 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3210 (src_family == RADV_QUEUE_GENERAL ||
3211 dst_family == RADV_QUEUE_GENERAL))
3212 return;
3213 }
3214
3215 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3216 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3217
3218 if (image->surface.htile_size)
3219 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3220 dst_layout, src_queue_mask,
3221 dst_queue_mask, range,
3222 pending_clears);
3223
3224 if (image->cmask.size)
3225 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3226 dst_layout, src_queue_mask,
3227 dst_queue_mask, range,
3228 pending_clears);
3229
3230 if (image->surface.dcc_size)
3231 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3232 dst_layout, src_queue_mask,
3233 dst_queue_mask, range,
3234 pending_clears);
3235 }
3236
3237 void radv_CmdPipelineBarrier(
3238 VkCommandBuffer commandBuffer,
3239 VkPipelineStageFlags srcStageMask,
3240 VkPipelineStageFlags destStageMask,
3241 VkBool32 byRegion,
3242 uint32_t memoryBarrierCount,
3243 const VkMemoryBarrier* pMemoryBarriers,
3244 uint32_t bufferMemoryBarrierCount,
3245 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3246 uint32_t imageMemoryBarrierCount,
3247 const VkImageMemoryBarrier* pImageMemoryBarriers)
3248 {
3249 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3250 enum radv_cmd_flush_bits src_flush_bits = 0;
3251 enum radv_cmd_flush_bits dst_flush_bits = 0;
3252
3253 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3254 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3255 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3256 NULL);
3257 }
3258
3259 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3260 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3261 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3262 NULL);
3263 }
3264
3265 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3266 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3267 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3268 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3269 image);
3270 }
3271
3272 radv_stage_flush(cmd_buffer, srcStageMask);
3273 cmd_buffer->state.flush_bits |= src_flush_bits;
3274
3275 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3276 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3277 radv_handle_image_transition(cmd_buffer, image,
3278 pImageMemoryBarriers[i].oldLayout,
3279 pImageMemoryBarriers[i].newLayout,
3280 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3281 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3282 &pImageMemoryBarriers[i].subresourceRange,
3283 0);
3284 }
3285
3286 cmd_buffer->state.flush_bits |= dst_flush_bits;
3287 }
3288
3289
3290 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3291 struct radv_event *event,
3292 VkPipelineStageFlags stageMask,
3293 unsigned value)
3294 {
3295 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3296 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3297
3298 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3299
3300 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3301
3302 /* TODO: this is overkill. Probably should figure something out from
3303 * the stage mask. */
3304
3305 si_cs_emit_write_event_eop(cs,
3306 cmd_buffer->device->physical_device->rad_info.chip_class,
3307 false,
3308 EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
3309 1, va, 2, value);
3310
3311 assert(cmd_buffer->cs->cdw <= cdw_max);
3312 }
3313
3314 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3315 VkEvent _event,
3316 VkPipelineStageFlags stageMask)
3317 {
3318 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3319 RADV_FROM_HANDLE(radv_event, event, _event);
3320
3321 write_event(cmd_buffer, event, stageMask, 1);
3322 }
3323
3324 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3325 VkEvent _event,
3326 VkPipelineStageFlags stageMask)
3327 {
3328 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3329 RADV_FROM_HANDLE(radv_event, event, _event);
3330
3331 write_event(cmd_buffer, event, stageMask, 0);
3332 }
3333
3334 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3335 uint32_t eventCount,
3336 const VkEvent* pEvents,
3337 VkPipelineStageFlags srcStageMask,
3338 VkPipelineStageFlags dstStageMask,
3339 uint32_t memoryBarrierCount,
3340 const VkMemoryBarrier* pMemoryBarriers,
3341 uint32_t bufferMemoryBarrierCount,
3342 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3343 uint32_t imageMemoryBarrierCount,
3344 const VkImageMemoryBarrier* pImageMemoryBarriers)
3345 {
3346 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3347 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3348
3349 for (unsigned i = 0; i < eventCount; ++i) {
3350 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3351 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3352
3353 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3354
3355 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3356
3357 si_emit_wait_fence(cs, va, 1, 0xffffffff);
3358 assert(cmd_buffer->cs->cdw <= cdw_max);
3359 }
3360
3361
3362 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3363 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3364
3365 radv_handle_image_transition(cmd_buffer, image,
3366 pImageMemoryBarriers[i].oldLayout,
3367 pImageMemoryBarriers[i].newLayout,
3368 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3369 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3370 &pImageMemoryBarriers[i].subresourceRange,
3371 0);
3372 }
3373
3374 /* TODO: figure out how to do memory barriers without waiting */
3375 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3376 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3377 RADV_CMD_FLAG_INV_VMEM_L1 |
3378 RADV_CMD_FLAG_INV_SMEM_L1;
3379 }