projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: add missed situations for scissor bug workaround
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range);
61
62 const struct radv_dynamic_state default_dynamic_state = {
63 .viewport = {
64 .count = 0,
65 },
66 .scissor = {
67 .count = 0,
68 },
69 .line_width = 1.0f,
70 .depth_bias = {
71 .bias = 0.0f,
72 .clamp = 0.0f,
73 .slope = 0.0f,
74 },
75 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
76 .depth_bounds = {
77 .min = 0.0f,
78 .max = 1.0f,
79 },
80 .stencil_compare_mask = {
81 .front = ~0u,
82 .back = ~0u,
83 },
84 .stencil_write_mask = {
85 .front = ~0u,
86 .back = ~0u,
87 },
88 .stencil_reference = {
89 .front = 0u,
90 .back = 0u,
91 },
92 };
93
94 static void
95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
96 const struct radv_dynamic_state *src)
97 {
98 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
99 uint32_t copy_mask = src->mask;
100 uint32_t dest_mask = 0;
101
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
104 */
105 dest->viewport.count = src->viewport.count;
106 dest->scissor.count = src->scissor.count;
107 dest->discard_rectangle.count = src->discard_rectangle.count;
108
109 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
110 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
111 src->viewport.count * sizeof(VkViewport))) {
112 typed_memcpy(dest->viewport.viewports,
113 src->viewport.viewports,
114 src->viewport.count);
115 dest_mask |= RADV_DYNAMIC_VIEWPORT;
116 }
117 }
118
119 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
120 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
121 src->scissor.count * sizeof(VkRect2D))) {
122 typed_memcpy(dest->scissor.scissors,
123 src->scissor.scissors, src->scissor.count);
124 dest_mask |= RADV_DYNAMIC_SCISSOR;
125 }
126 }
127
128 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
129 if (dest->line_width != src->line_width) {
130 dest->line_width = src->line_width;
131 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
132 }
133 }
134
135 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
136 if (memcmp(&dest->depth_bias, &src->depth_bias,
137 sizeof(src->depth_bias))) {
138 dest->depth_bias = src->depth_bias;
139 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
144 if (memcmp(&dest->blend_constants, &src->blend_constants,
145 sizeof(src->blend_constants))) {
146 typed_memcpy(dest->blend_constants,
147 src->blend_constants, 4);
148 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
149 }
150 }
151
152 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
153 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
154 sizeof(src->depth_bounds))) {
155 dest->depth_bounds = src->depth_bounds;
156 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
161 if (memcmp(&dest->stencil_compare_mask,
162 &src->stencil_compare_mask,
163 sizeof(src->stencil_compare_mask))) {
164 dest->stencil_compare_mask = src->stencil_compare_mask;
165 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
166 }
167 }
168
169 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
170 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
171 sizeof(src->stencil_write_mask))) {
172 dest->stencil_write_mask = src->stencil_write_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
178 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
179 sizeof(src->stencil_reference))) {
180 dest->stencil_reference = src->stencil_reference;
181 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
186 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
187 src->discard_rectangle.count * sizeof(VkRect2D))) {
188 typed_memcpy(dest->discard_rectangle.rectangles,
189 src->discard_rectangle.rectangles,
190 src->discard_rectangle.count);
191 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
192 }
193 }
194
195 cmd_buffer->state.dirty |= dest_mask;
196 }
197
198 static void
199 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
200 struct radv_pipeline *pipeline)
201 {
202 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
203 struct radv_shader_info *info;
204
205 if (!pipeline->streamout_shader)
206 return;
207
208 info = &pipeline->streamout_shader->info.info;
209 for (int i = 0; i < MAX_SO_BUFFERS; i++)
210 so->stride_in_dw[i] = info->so.strides[i];
211
212 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
213 }
214
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
216 {
217 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
218 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
219 }
220
221 enum ring_type radv_queue_family_to_ring(int f) {
222 switch (f) {
223 case RADV_QUEUE_GENERAL:
224 return RING_GFX;
225 case RADV_QUEUE_COMPUTE:
226 return RING_COMPUTE;
227 case RADV_QUEUE_TRANSFER:
228 return RING_DMA;
229 default:
230 unreachable("Unknown queue family");
231 }
232 }
233
234 static VkResult radv_create_cmd_buffer(
235 struct radv_device * device,
236 struct radv_cmd_pool * pool,
237 VkCommandBufferLevel level,
238 VkCommandBuffer* pCommandBuffer)
239 {
240 struct radv_cmd_buffer *cmd_buffer;
241 unsigned ring;
242 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
244 if (cmd_buffer == NULL)
245 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
246
247 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 cmd_buffer->device = device;
249 cmd_buffer->pool = pool;
250 cmd_buffer->level = level;
251
252 if (pool) {
253 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
254 cmd_buffer->queue_family_index = pool->queue_family_index;
255
256 } else {
257 /* Init the pool_link so we can safely call list_del when we destroy
258 * the command buffer
259 */
260 list_inithead(&cmd_buffer->pool_link);
261 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
262 }
263
264 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
265
266 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
267 if (!cmd_buffer->cs) {
268 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
269 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
270 }
271
272 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
273
274 list_inithead(&cmd_buffer->upload.list);
275
276 return VK_SUCCESS;
277 }
278
279 static void
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
281 {
282 list_del(&cmd_buffer->pool_link);
283
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
285 &cmd_buffer->upload.list, list) {
286 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
287 list_del(&up->list);
288 free(up);
289 }
290
291 if (cmd_buffer->upload.upload_bo)
292 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
293 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
294
295 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
296 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
297
298 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
299 }
300
301 static VkResult
302 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
303 {
304
305 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
306
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
308 &cmd_buffer->upload.list, list) {
309 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
310 list_del(&up->list);
311 free(up);
312 }
313
314 cmd_buffer->push_constant_stages = 0;
315 cmd_buffer->scratch_size_needed = 0;
316 cmd_buffer->compute_scratch_size_needed = 0;
317 cmd_buffer->esgs_ring_size_needed = 0;
318 cmd_buffer->gsvs_ring_size_needed = 0;
319 cmd_buffer->tess_rings_needed = false;
320 cmd_buffer->sample_positions_needed = false;
321
322 if (cmd_buffer->upload.upload_bo)
323 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
324 cmd_buffer->upload.upload_bo);
325 cmd_buffer->upload.offset = 0;
326
327 cmd_buffer->record_result = VK_SUCCESS;
328
329 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
330 cmd_buffer->descriptors[i].dirty = 0;
331 cmd_buffer->descriptors[i].valid = 0;
332 cmd_buffer->descriptors[i].push_dirty = false;
333 }
334
335 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
336 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
337 unsigned eop_bug_offset;
338 void *fence_ptr;
339
340 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
341 &cmd_buffer->gfx9_fence_offset,
342 &fence_ptr);
343 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
344
345 /* Allocate a buffer for the EOP bug on GFX9. */
346 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
347 &eop_bug_offset, &fence_ptr);
348 cmd_buffer->gfx9_eop_bug_va =
349 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
350 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
351 }
352
353 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
354
355 return cmd_buffer->record_result;
356 }
357
358 static bool
359 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
360 uint64_t min_needed)
361 {
362 uint64_t new_size;
363 struct radeon_winsys_bo *bo;
364 struct radv_cmd_buffer_upload *upload;
365 struct radv_device *device = cmd_buffer->device;
366
367 new_size = MAX2(min_needed, 16 * 1024);
368 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
369
370 bo = device->ws->buffer_create(device->ws,
371 new_size, 4096,
372 RADEON_DOMAIN_GTT,
373 RADEON_FLAG_CPU_ACCESS|
374 RADEON_FLAG_NO_INTERPROCESS_SHARING |
375 RADEON_FLAG_32BIT);
376
377 if (!bo) {
378 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
379 return false;
380 }
381
382 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
383 if (cmd_buffer->upload.upload_bo) {
384 upload = malloc(sizeof(*upload));
385
386 if (!upload) {
387 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
388 device->ws->buffer_destroy(bo);
389 return false;
390 }
391
392 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
393 list_add(&upload->list, &cmd_buffer->upload.list);
394 }
395
396 cmd_buffer->upload.upload_bo = bo;
397 cmd_buffer->upload.size = new_size;
398 cmd_buffer->upload.offset = 0;
399 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
400
401 if (!cmd_buffer->upload.map) {
402 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
403 return false;
404 }
405
406 return true;
407 }
408
409 bool
410 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
411 unsigned size,
412 unsigned alignment,
413 unsigned *out_offset,
414 void **ptr)
415 {
416 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
417 if (offset + size > cmd_buffer->upload.size) {
418 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
419 return false;
420 offset = 0;
421 }
422
423 *out_offset = offset;
424 *ptr = cmd_buffer->upload.map + offset;
425
426 cmd_buffer->upload.offset = offset + size;
427 return true;
428 }
429
430 bool
431 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
432 unsigned size, unsigned alignment,
433 const void *data, unsigned *out_offset)
434 {
435 uint8_t *ptr;
436
437 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
438 out_offset, (void **)&ptr))
439 return false;
440
441 if (ptr)
442 memcpy(ptr, data, size);
443
444 return true;
445 }
446
447 static void
448 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
449 unsigned count, const uint32_t *data)
450 {
451 struct radeon_cmdbuf *cs = cmd_buffer->cs;
452
453 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
454
455 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
456 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
457 S_370_WR_CONFIRM(1) |
458 S_370_ENGINE_SEL(V_370_ME));
459 radeon_emit(cs, va);
460 radeon_emit(cs, va >> 32);
461 radeon_emit_array(cs, data, count);
462 }
463
464 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
465 {
466 struct radv_device *device = cmd_buffer->device;
467 struct radeon_cmdbuf *cs = cmd_buffer->cs;
468 uint64_t va;
469
470 va = radv_buffer_get_va(device->trace_bo);
471 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
472 va += 4;
473
474 ++cmd_buffer->state.trace_id;
475 radv_emit_write_data_packet(cmd_buffer, va, 1,
476 &cmd_buffer->state.trace_id);
477
478 radeon_check_space(cmd_buffer->device->ws, cs, 2);
479
480 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
481 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
482 }
483
484 static void
485 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
486 enum radv_cmd_flush_bits flags)
487 {
488 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
489 uint32_t *ptr = NULL;
490 uint64_t va = 0;
491
492 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
493 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
494
495 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
496 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
497 cmd_buffer->gfx9_fence_offset;
498 ptr = &cmd_buffer->gfx9_fence_idx;
499 }
500
501 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
502
503 /* Force wait for graphics or compute engines to be idle. */
504 si_cs_emit_cache_flush(cmd_buffer->cs,
505 cmd_buffer->device->physical_device->rad_info.chip_class,
506 ptr, va,
507 radv_cmd_buffer_uses_mec(cmd_buffer),
508 flags, cmd_buffer->gfx9_eop_bug_va);
509 }
510
511 if (unlikely(cmd_buffer->device->trace_bo))
512 radv_cmd_buffer_trace_emit(cmd_buffer);
513 }
514
515 static void
516 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
517 struct radv_pipeline *pipeline, enum ring_type ring)
518 {
519 struct radv_device *device = cmd_buffer->device;
520 uint32_t data[2];
521 uint64_t va;
522
523 va = radv_buffer_get_va(device->trace_bo);
524
525 switch (ring) {
526 case RING_GFX:
527 va += 8;
528 break;
529 case RING_COMPUTE:
530 va += 16;
531 break;
532 default:
533 assert(!"invalid ring type");
534 }
535
536 data[0] = (uintptr_t)pipeline;
537 data[1] = (uintptr_t)pipeline >> 32;
538
539 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
540 }
541
542 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
543 VkPipelineBindPoint bind_point,
544 struct radv_descriptor_set *set,
545 unsigned idx)
546 {
547 struct radv_descriptor_state *descriptors_state =
548 radv_get_descriptors_state(cmd_buffer, bind_point);
549
550 descriptors_state->sets[idx] = set;
551
552 descriptors_state->valid |= (1u << idx); /* active descriptors */
553 descriptors_state->dirty |= (1u << idx);
554 }
555
556 static void
557 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
558 VkPipelineBindPoint bind_point)
559 {
560 struct radv_descriptor_state *descriptors_state =
561 radv_get_descriptors_state(cmd_buffer, bind_point);
562 struct radv_device *device = cmd_buffer->device;
563 uint32_t data[MAX_SETS * 2] = {};
564 uint64_t va;
565 unsigned i;
566 va = radv_buffer_get_va(device->trace_bo) + 24;
567
568 for_each_bit(i, descriptors_state->valid) {
569 struct radv_descriptor_set *set = descriptors_state->sets[i];
570 data[i * 2] = (uintptr_t)set;
571 data[i * 2 + 1] = (uintptr_t)set >> 32;
572 }
573
574 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
575 }
576
577 struct radv_userdata_info *
578 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
579 gl_shader_stage stage,
580 int idx)
581 {
582 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
583 return &shader->info.user_sgprs_locs.shader_data[idx];
584 }
585
586 static void
587 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
588 struct radv_pipeline *pipeline,
589 gl_shader_stage stage,
590 int idx, uint64_t va)
591 {
592 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
593 uint32_t base_reg = pipeline->user_data_0[stage];
594 if (loc->sgpr_idx == -1)
595 return;
596
597 assert(loc->num_sgprs == 1);
598 assert(!loc->indirect);
599
600 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
601 base_reg + loc->sgpr_idx * 4, va, false);
602 }
603
604 static void
605 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
606 struct radv_pipeline *pipeline,
607 struct radv_descriptor_state *descriptors_state,
608 gl_shader_stage stage)
609 {
610 struct radv_device *device = cmd_buffer->device;
611 struct radeon_cmdbuf *cs = cmd_buffer->cs;
612 uint32_t sh_base = pipeline->user_data_0[stage];
613 struct radv_userdata_locations *locs =
614 &pipeline->shaders[stage]->info.user_sgprs_locs;
615 unsigned mask = locs->descriptor_sets_enabled;
616
617 mask &= descriptors_state->dirty & descriptors_state->valid;
618
619 while (mask) {
620 int start, count;
621
622 u_bit_scan_consecutive_range(&mask, &start, &count);
623
624 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
625 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
626
627 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
628 for (int i = 0; i < count; i++) {
629 struct radv_descriptor_set *set =
630 descriptors_state->sets[start + i];
631
632 radv_emit_shader_pointer_body(device, cs, set->va, true);
633 }
634 }
635 }
636
637 static void
638 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
639 struct radv_pipeline *pipeline)
640 {
641 int num_samples = pipeline->graphics.ms.num_samples;
642 struct radv_multisample_state *ms = &pipeline->graphics.ms;
643 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
644
645 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
646 cmd_buffer->sample_positions_needed = true;
647
648 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
649 return;
650
651 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
652 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
653 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
654
655 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
656
657 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
658
659 /* GFX9: Flush DFSM when the AA mode changes. */
660 if (cmd_buffer->device->dfsm_allowed) {
661 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
662 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
663 }
664 }
665
666 static void
667 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
668 struct radv_shader_variant *shader)
669 {
670 uint64_t va;
671
672 if (!shader)
673 return;
674
675 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
676
677 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
678 }
679
680 static void
681 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
682 struct radv_pipeline *pipeline,
683 bool vertex_stage_only)
684 {
685 struct radv_cmd_state *state = &cmd_buffer->state;
686 uint32_t mask = state->prefetch_L2_mask;
687
688 if (vertex_stage_only) {
689 /* Fast prefetch path for starting draws as soon as possible.
690 */
691 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
692 RADV_PREFETCH_VBO_DESCRIPTORS);
693 }
694
695 if (mask & RADV_PREFETCH_VS)
696 radv_emit_shader_prefetch(cmd_buffer,
697 pipeline->shaders[MESA_SHADER_VERTEX]);
698
699 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
700 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
701
702 if (mask & RADV_PREFETCH_TCS)
703 radv_emit_shader_prefetch(cmd_buffer,
704 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
705
706 if (mask & RADV_PREFETCH_TES)
707 radv_emit_shader_prefetch(cmd_buffer,
708 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
709
710 if (mask & RADV_PREFETCH_GS) {
711 radv_emit_shader_prefetch(cmd_buffer,
712 pipeline->shaders[MESA_SHADER_GEOMETRY]);
713 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
714 }
715
716 if (mask & RADV_PREFETCH_PS)
717 radv_emit_shader_prefetch(cmd_buffer,
718 pipeline->shaders[MESA_SHADER_FRAGMENT]);
719
720 state->prefetch_L2_mask &= ~mask;
721 }
722
723 static void
724 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
725 {
726 if (!cmd_buffer->device->physical_device->rbplus_allowed)
727 return;
728
729 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
730 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
731 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
732
733 unsigned sx_ps_downconvert = 0;
734 unsigned sx_blend_opt_epsilon = 0;
735 unsigned sx_blend_opt_control = 0;
736
737 for (unsigned i = 0; i < subpass->color_count; ++i) {
738 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
739 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
740 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
741 continue;
742 }
743
744 int idx = subpass->color_attachments[i].attachment;
745 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
746
747 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
748 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
749 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
750 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
751
752 bool has_alpha, has_rgb;
753
754 /* Set if RGB and A are present. */
755 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
756
757 if (format == V_028C70_COLOR_8 ||
758 format == V_028C70_COLOR_16 ||
759 format == V_028C70_COLOR_32)
760 has_rgb = !has_alpha;
761 else
762 has_rgb = true;
763
764 /* Check the colormask and export format. */
765 if (!(colormask & 0x7))
766 has_rgb = false;
767 if (!(colormask & 0x8))
768 has_alpha = false;
769
770 if (spi_format == V_028714_SPI_SHADER_ZERO) {
771 has_rgb = false;
772 has_alpha = false;
773 }
774
775 /* Disable value checking for disabled channels. */
776 if (!has_rgb)
777 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
778 if (!has_alpha)
779 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
780
781 /* Enable down-conversion for 32bpp and smaller formats. */
782 switch (format) {
783 case V_028C70_COLOR_8:
784 case V_028C70_COLOR_8_8:
785 case V_028C70_COLOR_8_8_8_8:
786 /* For 1 and 2-channel formats, use the superset thereof. */
787 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
788 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
789 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
790 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
791 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
792 }
793 break;
794
795 case V_028C70_COLOR_5_6_5:
796 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
797 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
798 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
799 }
800 break;
801
802 case V_028C70_COLOR_1_5_5_5:
803 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
804 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
805 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
806 }
807 break;
808
809 case V_028C70_COLOR_4_4_4_4:
810 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
811 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
812 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
813 }
814 break;
815
816 case V_028C70_COLOR_32:
817 if (swap == V_028C70_SWAP_STD &&
818 spi_format == V_028714_SPI_SHADER_32_R)
819 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
820 else if (swap == V_028C70_SWAP_ALT_REV &&
821 spi_format == V_028714_SPI_SHADER_32_AR)
822 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
823 break;
824
825 case V_028C70_COLOR_16:
826 case V_028C70_COLOR_16_16:
827 /* For 1-channel formats, use the superset thereof. */
828 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
829 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
830 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
831 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
832 if (swap == V_028C70_SWAP_STD ||
833 swap == V_028C70_SWAP_STD_REV)
834 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
835 else
836 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
837 }
838 break;
839
840 case V_028C70_COLOR_10_11_11:
841 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
842 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
843 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
844 }
845 break;
846
847 case V_028C70_COLOR_2_10_10_10:
848 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
849 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
850 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
851 }
852 break;
853 }
854 }
855
856 for (unsigned i = subpass->color_count; i < 8; ++i) {
857 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
858 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
859 }
860 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
861 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
862 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
863 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
864 }
865
866 static void
867 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
868 {
869 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
870
871 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
872 return;
873
874 radv_update_multisample_state(cmd_buffer, pipeline);
875
876 cmd_buffer->scratch_size_needed =
877 MAX2(cmd_buffer->scratch_size_needed,
878 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
879
880 if (!cmd_buffer->state.emitted_pipeline ||
881 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
882 pipeline->graphics.can_use_guardband)
883 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
884
885 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
886
887 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
888 if (!pipeline->shaders[i])
889 continue;
890
891 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
892 pipeline->shaders[i]->bo);
893 }
894
895 if (radv_pipeline_has_gs(pipeline))
896 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
897 pipeline->gs_copy_shader->bo);
898
899 if (unlikely(cmd_buffer->device->trace_bo))
900 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
901
902 cmd_buffer->state.emitted_pipeline = pipeline;
903
904 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
905 }
906
907 static void
908 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
909 {
910 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
911 cmd_buffer->state.dynamic.viewport.viewports);
912 }
913
914 static void
915 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
916 {
917 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
918
919 si_write_scissors(cmd_buffer->cs, 0, count,
920 cmd_buffer->state.dynamic.scissor.scissors,
921 cmd_buffer->state.dynamic.viewport.viewports,
922 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
923
924 cmd_buffer->state.context_roll_without_scissor_emitted = false;
925 }
926
927 static void
928 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
929 {
930 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
931 return;
932
933 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
934 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
935 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
936 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
937 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
938 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
939 S_028214_BR_Y(rect.offset.y + rect.extent.height));
940 }
941 }
942
943 static void
944 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
945 {
946 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
947
948 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
949 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
950 }
951
952 static void
953 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
954 {
955 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
956
957 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
958 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
959 }
960
961 static void
962 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
963 {
964 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
965
966 radeon_set_context_reg_seq(cmd_buffer->cs,
967 R_028430_DB_STENCILREFMASK, 2);
968 radeon_emit(cmd_buffer->cs,
969 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
970 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
971 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
972 S_028430_STENCILOPVAL(1));
973 radeon_emit(cmd_buffer->cs,
974 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
975 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
976 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
977 S_028434_STENCILOPVAL_BF(1));
978 }
979
980 static void
981 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
982 {
983 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
984
985 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
986 fui(d->depth_bounds.min));
987 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
988 fui(d->depth_bounds.max));
989 }
990
991 static void
992 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
993 {
994 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
995 unsigned slope = fui(d->depth_bias.slope * 16.0f);
996 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
997
998
999 radeon_set_context_reg_seq(cmd_buffer->cs,
1000 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1001 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1002 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1003 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1004 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1005 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1006 }
1007
1008 static void
1009 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1010 int index,
1011 struct radv_attachment_info *att,
1012 struct radv_image *image,
1013 VkImageLayout layout)
1014 {
1015 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1016 struct radv_color_buffer_info *cb = &att->cb;
1017 uint32_t cb_color_info = cb->cb_color_info;
1018
1019 if (!radv_layout_dcc_compressed(image, layout,
1020 radv_image_queue_family_mask(image,
1021 cmd_buffer->queue_family_index,
1022 cmd_buffer->queue_family_index))) {
1023 cb_color_info &= C_028C70_DCC_ENABLE;
1024 }
1025
1026 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1027 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1028 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1029 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1030 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1031 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1032 radeon_emit(cmd_buffer->cs, cb_color_info);
1033 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1034 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1035 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1036 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1037 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1038 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1039
1040 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1041 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1042 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1043
1044 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1045 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1046 } else {
1047 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1048 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1049 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1050 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1051 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1052 radeon_emit(cmd_buffer->cs, cb_color_info);
1053 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1054 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1055 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1056 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1057 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1058 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1059
1060 if (is_vi) { /* DCC BASE */
1061 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1062 }
1063 }
1064
1065 if (radv_image_has_dcc(image)) {
1066 /* Drawing with DCC enabled also compresses colorbuffers. */
1067 radv_update_dcc_metadata(cmd_buffer, image, true);
1068 }
1069 }
1070
1071 static void
1072 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1073 struct radv_ds_buffer_info *ds,
1074 struct radv_image *image, VkImageLayout layout,
1075 bool requires_cond_exec)
1076 {
1077 uint32_t db_z_info = ds->db_z_info;
1078 uint32_t db_z_info_reg;
1079
1080 if (!radv_image_is_tc_compat_htile(image))
1081 return;
1082
1083 if (!radv_layout_has_htile(image, layout,
1084 radv_image_queue_family_mask(image,
1085 cmd_buffer->queue_family_index,
1086 cmd_buffer->queue_family_index))) {
1087 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1088 }
1089
1090 db_z_info &= C_028040_ZRANGE_PRECISION;
1091
1092 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1093 db_z_info_reg = R_028038_DB_Z_INFO;
1094 } else {
1095 db_z_info_reg = R_028040_DB_Z_INFO;
1096 }
1097
1098 /* When we don't know the last fast clear value we need to emit a
1099 * conditional packet that will eventually skip the following
1100 * SET_CONTEXT_REG packet.
1101 */
1102 if (requires_cond_exec) {
1103 uint64_t va = radv_buffer_get_va(image->bo);
1104 va += image->offset + image->tc_compat_zrange_offset;
1105
1106 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1107 radeon_emit(cmd_buffer->cs, va);
1108 radeon_emit(cmd_buffer->cs, va >> 32);
1109 radeon_emit(cmd_buffer->cs, 0);
1110 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1111 }
1112
1113 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1114 }
1115
1116 static void
1117 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1118 struct radv_ds_buffer_info *ds,
1119 struct radv_image *image,
1120 VkImageLayout layout)
1121 {
1122 uint32_t db_z_info = ds->db_z_info;
1123 uint32_t db_stencil_info = ds->db_stencil_info;
1124
1125 if (!radv_layout_has_htile(image, layout,
1126 radv_image_queue_family_mask(image,
1127 cmd_buffer->queue_family_index,
1128 cmd_buffer->queue_family_index))) {
1129 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1130 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1131 }
1132
1133 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1134 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1135
1136
1137 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1138 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1139 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1140 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1141 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1142
1143 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1144 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1145 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1146 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1147 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1148 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1149 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1150 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1151 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1152 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1153 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1154
1155 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1156 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1157 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1158 } else {
1159 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1160
1161 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1162 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1163 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1164 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1165 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1166 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1167 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1168 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1169 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1170 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1171
1172 }
1173
1174 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1175 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1176
1177 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1178 ds->pa_su_poly_offset_db_fmt_cntl);
1179 }
1180
1181 /**
1182 * Update the fast clear depth/stencil values if the image is bound as a
1183 * depth/stencil buffer.
1184 */
1185 static void
1186 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1187 struct radv_image *image,
1188 VkClearDepthStencilValue ds_clear_value,
1189 VkImageAspectFlags aspects)
1190 {
1191 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1192 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1193 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1194 struct radv_attachment_info *att;
1195 uint32_t att_idx;
1196
1197 if (!framebuffer || !subpass)
1198 return;
1199
1200 att_idx = subpass->depth_stencil_attachment.attachment;
1201 if (att_idx == VK_ATTACHMENT_UNUSED)
1202 return;
1203
1204 att = &framebuffer->attachments[att_idx];
1205 if (att->attachment->image != image)
1206 return;
1207
1208 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1209 radeon_emit(cs, ds_clear_value.stencil);
1210 radeon_emit(cs, fui(ds_clear_value.depth));
1211
1212 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1213 * only needed when clearing Z to 0.0.
1214 */
1215 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1216 ds_clear_value.depth == 0.0) {
1217 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1218
1219 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1220 layout, false);
1221 }
1222
1223 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1224 }
1225
1226 /**
1227 * Set the clear depth/stencil values to the image's metadata.
1228 */
1229 static void
1230 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1231 struct radv_image *image,
1232 VkClearDepthStencilValue ds_clear_value,
1233 VkImageAspectFlags aspects)
1234 {
1235 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1236 uint64_t va = radv_buffer_get_va(image->bo);
1237 unsigned reg_offset = 0, reg_count = 0;
1238
1239 va += image->offset + image->clear_value_offset;
1240
1241 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1242 ++reg_count;
1243 } else {
1244 ++reg_offset;
1245 va += 4;
1246 }
1247 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1248 ++reg_count;
1249
1250 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1251 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1252 S_370_WR_CONFIRM(1) |
1253 S_370_ENGINE_SEL(V_370_PFP));
1254 radeon_emit(cs, va);
1255 radeon_emit(cs, va >> 32);
1256 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1257 radeon_emit(cs, ds_clear_value.stencil);
1258 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1259 radeon_emit(cs, fui(ds_clear_value.depth));
1260 }
1261
1262 /**
1263 * Update the TC-compat metadata value for this image.
1264 */
1265 static void
1266 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1267 struct radv_image *image,
1268 uint32_t value)
1269 {
1270 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1271 uint64_t va = radv_buffer_get_va(image->bo);
1272 va += image->offset + image->tc_compat_zrange_offset;
1273
1274 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1275 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1276 S_370_WR_CONFIRM(1) |
1277 S_370_ENGINE_SEL(V_370_PFP));
1278 radeon_emit(cs, va);
1279 radeon_emit(cs, va >> 32);
1280 radeon_emit(cs, value);
1281 }
1282
1283 static void
1284 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1285 struct radv_image *image,
1286 VkClearDepthStencilValue ds_clear_value)
1287 {
1288 uint64_t va = radv_buffer_get_va(image->bo);
1289 va += image->offset + image->tc_compat_zrange_offset;
1290 uint32_t cond_val;
1291
1292 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1293 * depth clear value is 0.0f.
1294 */
1295 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1296
1297 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1298 }
1299
1300 /**
1301 * Update the clear depth/stencil values for this image.
1302 */
1303 void
1304 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1305 struct radv_image *image,
1306 VkClearDepthStencilValue ds_clear_value,
1307 VkImageAspectFlags aspects)
1308 {
1309 assert(radv_image_has_htile(image));
1310
1311 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1312
1313 if (radv_image_is_tc_compat_htile(image) &&
1314 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1315 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1316 ds_clear_value);
1317 }
1318
1319 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1320 aspects);
1321 }
1322
1323 /**
1324 * Load the clear depth/stencil values from the image's metadata.
1325 */
1326 static void
1327 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1328 struct radv_image *image)
1329 {
1330 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1331 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1332 uint64_t va = radv_buffer_get_va(image->bo);
1333 unsigned reg_offset = 0, reg_count = 0;
1334
1335 va += image->offset + image->clear_value_offset;
1336
1337 if (!radv_image_has_htile(image))
1338 return;
1339
1340 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1341 ++reg_count;
1342 } else {
1343 ++reg_offset;
1344 va += 4;
1345 }
1346 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1347 ++reg_count;
1348
1349 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1350
1351 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1352 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1353 radeon_emit(cs, va);
1354 radeon_emit(cs, va >> 32);
1355 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1356 radeon_emit(cs, reg_count);
1357 } else {
1358 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1359 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1360 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1361 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1362 radeon_emit(cs, va);
1363 radeon_emit(cs, va >> 32);
1364 radeon_emit(cs, reg >> 2);
1365 radeon_emit(cs, 0);
1366
1367 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1368 radeon_emit(cs, 0);
1369 }
1370 }
1371
1372 /*
1373 * With DCC some colors don't require CMASK elimination before being
1374 * used as a texture. This sets a predicate value to determine if the
1375 * cmask eliminate is required.
1376 */
1377 void
1378 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1379 struct radv_image *image, bool value)
1380 {
1381 uint64_t pred_val = value;
1382 uint64_t va = radv_buffer_get_va(image->bo);
1383 va += image->offset + image->fce_pred_offset;
1384
1385 assert(radv_image_has_dcc(image));
1386
1387 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1388 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1389 S_370_WR_CONFIRM(1) |
1390 S_370_ENGINE_SEL(V_370_PFP));
1391 radeon_emit(cmd_buffer->cs, va);
1392 radeon_emit(cmd_buffer->cs, va >> 32);
1393 radeon_emit(cmd_buffer->cs, pred_val);
1394 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1395 }
1396
1397 /**
1398 * Update the DCC predicate to reflect the compression state.
1399 */
1400 void
1401 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1402 struct radv_image *image, bool value)
1403 {
1404 uint64_t pred_val = value;
1405 uint64_t va = radv_buffer_get_va(image->bo);
1406 va += image->offset + image->dcc_pred_offset;
1407
1408 assert(radv_image_has_dcc(image));
1409
1410 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1411 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1412 S_370_WR_CONFIRM(1) |
1413 S_370_ENGINE_SEL(V_370_PFP));
1414 radeon_emit(cmd_buffer->cs, va);
1415 radeon_emit(cmd_buffer->cs, va >> 32);
1416 radeon_emit(cmd_buffer->cs, pred_val);
1417 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1418 }
1419
1420 /**
1421 * Update the fast clear color values if the image is bound as a color buffer.
1422 */
1423 static void
1424 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1425 struct radv_image *image,
1426 int cb_idx,
1427 uint32_t color_values[2])
1428 {
1429 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1430 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1431 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1432 struct radv_attachment_info *att;
1433 uint32_t att_idx;
1434
1435 if (!framebuffer || !subpass)
1436 return;
1437
1438 att_idx = subpass->color_attachments[cb_idx].attachment;
1439 if (att_idx == VK_ATTACHMENT_UNUSED)
1440 return;
1441
1442 att = &framebuffer->attachments[att_idx];
1443 if (att->attachment->image != image)
1444 return;
1445
1446 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1447 radeon_emit(cs, color_values[0]);
1448 radeon_emit(cs, color_values[1]);
1449
1450 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1451 }
1452
1453 /**
1454 * Set the clear color values to the image's metadata.
1455 */
1456 static void
1457 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1458 struct radv_image *image,
1459 uint32_t color_values[2])
1460 {
1461 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1462 uint64_t va = radv_buffer_get_va(image->bo);
1463
1464 va += image->offset + image->clear_value_offset;
1465
1466 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1467
1468 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1469 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1470 S_370_WR_CONFIRM(1) |
1471 S_370_ENGINE_SEL(V_370_PFP));
1472 radeon_emit(cs, va);
1473 radeon_emit(cs, va >> 32);
1474 radeon_emit(cs, color_values[0]);
1475 radeon_emit(cs, color_values[1]);
1476 }
1477
1478 /**
1479 * Update the clear color values for this image.
1480 */
1481 void
1482 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1483 struct radv_image *image,
1484 int cb_idx,
1485 uint32_t color_values[2])
1486 {
1487 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1488
1489 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1490
1491 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1492 color_values);
1493 }
1494
1495 /**
1496 * Load the clear color values from the image's metadata.
1497 */
1498 static void
1499 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1500 struct radv_image *image,
1501 int cb_idx)
1502 {
1503 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1504 uint64_t va = radv_buffer_get_va(image->bo);
1505
1506 va += image->offset + image->clear_value_offset;
1507
1508 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1509 return;
1510
1511 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1512
1513 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1514 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1515 radeon_emit(cs, va);
1516 radeon_emit(cs, va >> 32);
1517 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1518 radeon_emit(cs, 2);
1519 } else {
1520 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1521 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1522 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1523 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1524 COPY_DATA_COUNT_SEL);
1525 radeon_emit(cs, va);
1526 radeon_emit(cs, va >> 32);
1527 radeon_emit(cs, reg >> 2);
1528 radeon_emit(cs, 0);
1529
1530 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1531 radeon_emit(cs, 0);
1532 }
1533 }
1534
1535 static void
1536 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1537 {
1538 int i;
1539 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1540 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1541 unsigned num_bpp64_colorbufs = 0;
1542
1543 /* this may happen for inherited secondary recording */
1544 if (!framebuffer)
1545 return;
1546
1547 for (i = 0; i < 8; ++i) {
1548 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1549 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1550 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1551 continue;
1552 }
1553
1554 int idx = subpass->color_attachments[i].attachment;
1555 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1556 struct radv_image *image = att->attachment->image;
1557 VkImageLayout layout = subpass->color_attachments[i].layout;
1558
1559 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1560
1561 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1562 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1563
1564 radv_load_color_clear_metadata(cmd_buffer, image, i);
1565
1566 if (image->surface.bpe >= 8)
1567 num_bpp64_colorbufs++;
1568 }
1569
1570 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1571 int idx = subpass->depth_stencil_attachment.attachment;
1572 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1573 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1574 struct radv_image *image = att->attachment->image;
1575 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1576 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1577 cmd_buffer->queue_family_index,
1578 cmd_buffer->queue_family_index);
1579 /* We currently don't support writing decompressed HTILE */
1580 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1581 radv_layout_is_htile_compressed(image, layout, queue_mask));
1582
1583 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1584
1585 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1586 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1587 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1588 }
1589 radv_load_ds_clear_metadata(cmd_buffer, image);
1590 } else {
1591 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1592 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1593 else
1594 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1595
1596 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1597 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1598 }
1599 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1600 S_028208_BR_X(framebuffer->width) |
1601 S_028208_BR_Y(framebuffer->height));
1602
1603 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1604 uint8_t watermark = 4; /* Default value for VI. */
1605
1606 /* For optimal DCC performance. */
1607 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1608 if (num_bpp64_colorbufs >= 5) {
1609 watermark = 8;
1610 } else {
1611 watermark = 6;
1612 }
1613 }
1614
1615 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1616 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1617 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1618 }
1619
1620 if (cmd_buffer->device->dfsm_allowed) {
1621 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1622 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1623 }
1624
1625 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1626 }
1627
1628 static void
1629 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1630 {
1631 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1632 struct radv_cmd_state *state = &cmd_buffer->state;
1633
1634 if (state->index_type != state->last_index_type) {
1635 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1636 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1637 2, state->index_type);
1638 } else {
1639 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1640 radeon_emit(cs, state->index_type);
1641 }
1642
1643 state->last_index_type = state->index_type;
1644 }
1645
1646 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1647 radeon_emit(cs, state->index_va);
1648 radeon_emit(cs, state->index_va >> 32);
1649
1650 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1651 radeon_emit(cs, state->max_index_count);
1652
1653 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1654 }
1655
1656 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1657 {
1658 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1659 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1660 uint32_t pa_sc_mode_cntl_1 =
1661 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1662 uint32_t db_count_control;
1663
1664 if(!cmd_buffer->state.active_occlusion_queries) {
1665 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1666 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1667 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1668 has_perfect_queries) {
1669 /* Re-enable out-of-order rasterization if the
1670 * bound pipeline supports it and if it's has
1671 * been disabled before starting any perfect
1672 * occlusion queries.
1673 */
1674 radeon_set_context_reg(cmd_buffer->cs,
1675 R_028A4C_PA_SC_MODE_CNTL_1,
1676 pa_sc_mode_cntl_1);
1677 }
1678 }
1679 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1680 } else {
1681 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1682 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1683
1684 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1685 db_count_control =
1686 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1687 S_028004_SAMPLE_RATE(sample_rate) |
1688 S_028004_ZPASS_ENABLE(1) |
1689 S_028004_SLICE_EVEN_ENABLE(1) |
1690 S_028004_SLICE_ODD_ENABLE(1);
1691
1692 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1693 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1694 has_perfect_queries) {
1695 /* If the bound pipeline has enabled
1696 * out-of-order rasterization, we should
1697 * disable it before starting any perfect
1698 * occlusion queries.
1699 */
1700 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1701
1702 radeon_set_context_reg(cmd_buffer->cs,
1703 R_028A4C_PA_SC_MODE_CNTL_1,
1704 pa_sc_mode_cntl_1);
1705 }
1706 } else {
1707 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1708 S_028004_SAMPLE_RATE(sample_rate);
1709 }
1710 }
1711
1712 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1713
1714 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1715 }
1716
1717 static void
1718 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1719 {
1720 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1721
1722 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1723 radv_emit_viewport(cmd_buffer);
1724
1725 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1726 !cmd_buffer->device->physical_device->has_scissor_bug)
1727 radv_emit_scissor(cmd_buffer);
1728
1729 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1730 radv_emit_line_width(cmd_buffer);
1731
1732 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1733 radv_emit_blend_constants(cmd_buffer);
1734
1735 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1736 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1737 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1738 radv_emit_stencil(cmd_buffer);
1739
1740 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1741 radv_emit_depth_bounds(cmd_buffer);
1742
1743 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1744 radv_emit_depth_bias(cmd_buffer);
1745
1746 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1747 radv_emit_discard_rectangle(cmd_buffer);
1748
1749 cmd_buffer->state.dirty &= ~states;
1750 }
1751
1752 static void
1753 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1754 VkPipelineBindPoint bind_point)
1755 {
1756 struct radv_descriptor_state *descriptors_state =
1757 radv_get_descriptors_state(cmd_buffer, bind_point);
1758 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1759 unsigned bo_offset;
1760
1761 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1762 set->mapped_ptr,
1763 &bo_offset))
1764 return;
1765
1766 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1767 set->va += bo_offset;
1768 }
1769
1770 static void
1771 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1772 VkPipelineBindPoint bind_point)
1773 {
1774 struct radv_descriptor_state *descriptors_state =
1775 radv_get_descriptors_state(cmd_buffer, bind_point);
1776 uint32_t size = MAX_SETS * 4;
1777 uint32_t offset;
1778 void *ptr;
1779
1780 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1781 256, &offset, &ptr))
1782 return;
1783
1784 for (unsigned i = 0; i < MAX_SETS; i++) {
1785 uint32_t *uptr = ((uint32_t *)ptr) + i;
1786 uint64_t set_va = 0;
1787 struct radv_descriptor_set *set = descriptors_state->sets[i];
1788 if (descriptors_state->valid & (1u << i))
1789 set_va = set->va;
1790 uptr[0] = set_va & 0xffffffff;
1791 }
1792
1793 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1794 va += offset;
1795
1796 if (cmd_buffer->state.pipeline) {
1797 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1798 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1799 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1800
1801 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1802 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1803 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1804
1805 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1806 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1807 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1808
1809 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1810 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1811 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1812
1813 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1814 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1815 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1816 }
1817
1818 if (cmd_buffer->state.compute_pipeline)
1819 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1820 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1821 }
1822
1823 static void
1824 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1825 VkShaderStageFlags stages)
1826 {
1827 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1828 VK_PIPELINE_BIND_POINT_COMPUTE :
1829 VK_PIPELINE_BIND_POINT_GRAPHICS;
1830 struct radv_descriptor_state *descriptors_state =
1831 radv_get_descriptors_state(cmd_buffer, bind_point);
1832 struct radv_cmd_state *state = &cmd_buffer->state;
1833 bool flush_indirect_descriptors;
1834
1835 if (!descriptors_state->dirty)
1836 return;
1837
1838 if (descriptors_state->push_dirty)
1839 radv_flush_push_descriptors(cmd_buffer, bind_point);
1840
1841 flush_indirect_descriptors =
1842 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1843 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1844 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1845 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1846
1847 if (flush_indirect_descriptors)
1848 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1849
1850 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1851 cmd_buffer->cs,
1852 MAX_SETS * MESA_SHADER_STAGES * 4);
1853
1854 if (cmd_buffer->state.pipeline) {
1855 radv_foreach_stage(stage, stages) {
1856 if (!cmd_buffer->state.pipeline->shaders[stage])
1857 continue;
1858
1859 radv_emit_descriptor_pointers(cmd_buffer,
1860 cmd_buffer->state.pipeline,
1861 descriptors_state, stage);
1862 }
1863 }
1864
1865 if (cmd_buffer->state.compute_pipeline &&
1866 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1867 radv_emit_descriptor_pointers(cmd_buffer,
1868 cmd_buffer->state.compute_pipeline,
1869 descriptors_state,
1870 MESA_SHADER_COMPUTE);
1871 }
1872
1873 descriptors_state->dirty = 0;
1874 descriptors_state->push_dirty = false;
1875
1876 assert(cmd_buffer->cs->cdw <= cdw_max);
1877
1878 if (unlikely(cmd_buffer->device->trace_bo))
1879 radv_save_descriptors(cmd_buffer, bind_point);
1880 }
1881
1882 static void
1883 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1884 VkShaderStageFlags stages)
1885 {
1886 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1887 ? cmd_buffer->state.compute_pipeline
1888 : cmd_buffer->state.pipeline;
1889 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1890 VK_PIPELINE_BIND_POINT_COMPUTE :
1891 VK_PIPELINE_BIND_POINT_GRAPHICS;
1892 struct radv_descriptor_state *descriptors_state =
1893 radv_get_descriptors_state(cmd_buffer, bind_point);
1894 struct radv_pipeline_layout *layout = pipeline->layout;
1895 struct radv_shader_variant *shader, *prev_shader;
1896 unsigned offset;
1897 void *ptr;
1898 uint64_t va;
1899
1900 stages &= cmd_buffer->push_constant_stages;
1901 if (!stages ||
1902 (!layout->push_constant_size && !layout->dynamic_offset_count))
1903 return;
1904
1905 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1906 16 * layout->dynamic_offset_count,
1907 256, &offset, &ptr))
1908 return;
1909
1910 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1911 memcpy((char*)ptr + layout->push_constant_size,
1912 descriptors_state->dynamic_buffers,
1913 16 * layout->dynamic_offset_count);
1914
1915 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1916 va += offset;
1917
1918 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1919 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1920
1921 prev_shader = NULL;
1922 radv_foreach_stage(stage, stages) {
1923 shader = radv_get_shader(pipeline, stage);
1924
1925 /* Avoid redundantly emitting the address for merged stages. */
1926 if (shader && shader != prev_shader) {
1927 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1928 AC_UD_PUSH_CONSTANTS, va);
1929
1930 prev_shader = shader;
1931 }
1932 }
1933
1934 cmd_buffer->push_constant_stages &= ~stages;
1935 assert(cmd_buffer->cs->cdw <= cdw_max);
1936 }
1937
1938 static void
1939 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1940 bool pipeline_is_dirty)
1941 {
1942 if ((pipeline_is_dirty ||
1943 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1944 cmd_buffer->state.pipeline->vertex_elements.count &&
1945 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1946 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1947 unsigned vb_offset;
1948 void *vb_ptr;
1949 uint32_t i = 0;
1950 uint32_t count = velems->count;
1951 uint64_t va;
1952
1953 /* allocate some descriptor state for vertex buffers */
1954 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1955 &vb_offset, &vb_ptr))
1956 return;
1957
1958 for (i = 0; i < count; i++) {
1959 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1960 uint32_t offset;
1961 int vb = velems->binding[i];
1962 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1963 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1964
1965 va = radv_buffer_get_va(buffer->bo);
1966
1967 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1968 va += offset + buffer->offset;
1969 desc[0] = va;
1970 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1971 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1972 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1973 else
1974 desc[2] = buffer->size - offset;
1975 desc[3] = velems->rsrc_word3[i];
1976 }
1977
1978 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1979 va += vb_offset;
1980
1981 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1982 AC_UD_VS_VERTEX_BUFFERS, va);
1983
1984 cmd_buffer->state.vb_va = va;
1985 cmd_buffer->state.vb_size = count * 16;
1986 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1987 }
1988 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1989 }
1990
1991 static void
1992 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1993 {
1994 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1995 struct radv_userdata_info *loc;
1996 uint32_t base_reg;
1997
1998 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
1999 if (!radv_get_shader(pipeline, stage))
2000 continue;
2001
2002 loc = radv_lookup_user_sgpr(pipeline, stage,
2003 AC_UD_STREAMOUT_BUFFERS);
2004 if (loc->sgpr_idx == -1)
2005 continue;
2006
2007 base_reg = pipeline->user_data_0[stage];
2008
2009 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2010 base_reg + loc->sgpr_idx * 4, va, false);
2011 }
2012
2013 if (pipeline->gs_copy_shader) {
2014 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2015 if (loc->sgpr_idx != -1) {
2016 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2017
2018 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2019 base_reg + loc->sgpr_idx * 4, va, false);
2020 }
2021 }
2022 }
2023
2024 static void
2025 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2026 {
2027 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2028 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2029 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2030 unsigned so_offset;
2031 void *so_ptr;
2032 uint64_t va;
2033
2034 /* Allocate some descriptor state for streamout buffers. */
2035 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2036 MAX_SO_BUFFERS * 16, 256,
2037 &so_offset, &so_ptr))
2038 return;
2039
2040 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2041 struct radv_buffer *buffer = sb[i].buffer;
2042 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2043
2044 if (!(so->enabled_mask & (1 << i)))
2045 continue;
2046
2047 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2048
2049 va += sb[i].offset;
2050
2051 /* Set the descriptor.
2052 *
2053 * On VI, the format must be non-INVALID, otherwise
2054 * the buffer will be considered not bound and store
2055 * instructions will be no-ops.
2056 */
2057 desc[0] = va;
2058 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2059 desc[2] = 0xffffffff;
2060 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2061 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2062 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2063 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2064 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2065 }
2066
2067 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2068 va += so_offset;
2069
2070 radv_emit_streamout_buffers(cmd_buffer, va);
2071 }
2072
2073 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2074 }
2075
2076 static void
2077 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2078 {
2079 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2080 radv_flush_streamout_descriptors(cmd_buffer);
2081 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2082 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2083 }
2084
2085 struct radv_draw_info {
2086 /**
2087 * Number of vertices.
2088 */
2089 uint32_t count;
2090
2091 /**
2092 * Index of the first vertex.
2093 */
2094 int32_t vertex_offset;
2095
2096 /**
2097 * First instance id.
2098 */
2099 uint32_t first_instance;
2100
2101 /**
2102 * Number of instances.
2103 */
2104 uint32_t instance_count;
2105
2106 /**
2107 * First index (indexed draws only).
2108 */
2109 uint32_t first_index;
2110
2111 /**
2112 * Whether it's an indexed draw.
2113 */
2114 bool indexed;
2115
2116 /**
2117 * Indirect draw parameters resource.
2118 */
2119 struct radv_buffer *indirect;
2120 uint64_t indirect_offset;
2121 uint32_t stride;
2122
2123 /**
2124 * Draw count parameters resource.
2125 */
2126 struct radv_buffer *count_buffer;
2127 uint64_t count_buffer_offset;
2128
2129 /**
2130 * Stream output parameters resource.
2131 */
2132 struct radv_buffer *strmout_buffer;
2133 uint64_t strmout_buffer_offset;
2134 };
2135
2136 static void
2137 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2138 const struct radv_draw_info *draw_info)
2139 {
2140 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2141 struct radv_cmd_state *state = &cmd_buffer->state;
2142 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2143 uint32_t ia_multi_vgt_param;
2144 int32_t primitive_reset_en;
2145
2146 /* Draw state. */
2147 ia_multi_vgt_param =
2148 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2149 draw_info->indirect,
2150 draw_info->indirect ? 0 : draw_info->count);
2151
2152 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2153 if (info->chip_class >= GFX9) {
2154 radeon_set_uconfig_reg_idx(cs,
2155 R_030960_IA_MULTI_VGT_PARAM,
2156 4, ia_multi_vgt_param);
2157 } else if (info->chip_class >= CIK) {
2158 radeon_set_context_reg_idx(cs,
2159 R_028AA8_IA_MULTI_VGT_PARAM,
2160 1, ia_multi_vgt_param);
2161 } else {
2162 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2163 ia_multi_vgt_param);
2164 }
2165 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2166 }
2167
2168 /* Primitive restart. */
2169 primitive_reset_en =
2170 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2171
2172 if (primitive_reset_en != state->last_primitive_reset_en) {
2173 state->last_primitive_reset_en = primitive_reset_en;
2174 if (info->chip_class >= GFX9) {
2175 radeon_set_uconfig_reg(cs,
2176 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2177 primitive_reset_en);
2178 } else {
2179 radeon_set_context_reg(cs,
2180 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2181 primitive_reset_en);
2182 }
2183 }
2184
2185 if (primitive_reset_en) {
2186 uint32_t primitive_reset_index =
2187 state->index_type ? 0xffffffffu : 0xffffu;
2188
2189 if (primitive_reset_index != state->last_primitive_reset_index) {
2190 radeon_set_context_reg(cs,
2191 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2192 primitive_reset_index);
2193 state->last_primitive_reset_index = primitive_reset_index;
2194 }
2195 }
2196
2197 if (draw_info->strmout_buffer) {
2198 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2199
2200 va += draw_info->strmout_buffer->offset +
2201 draw_info->strmout_buffer_offset;
2202
2203 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2204 draw_info->stride);
2205
2206 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2207 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2208 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2209 COPY_DATA_WR_CONFIRM);
2210 radeon_emit(cs, va);
2211 radeon_emit(cs, va >> 32);
2212 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2213 radeon_emit(cs, 0); /* unused */
2214
2215 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2216 }
2217 }
2218
2219 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2220 VkPipelineStageFlags src_stage_mask)
2221 {
2222 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2223 VK_PIPELINE_STAGE_TRANSFER_BIT |
2224 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2225 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2226 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2227 }
2228
2229 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2230 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2231 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2232 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2233 VK_PIPELINE_STAGE_TRANSFER_BIT |
2234 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2235 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2236 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2237 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2238 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2239 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2240 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2241 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2242 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2243 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2244 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2245 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2246 }
2247 }
2248
2249 static enum radv_cmd_flush_bits
2250 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2251 VkAccessFlags src_flags,
2252 struct radv_image *image)
2253 {
2254 bool flush_CB_meta = true, flush_DB_meta = true;
2255 enum radv_cmd_flush_bits flush_bits = 0;
2256 uint32_t b;
2257
2258 if (image) {
2259 if (!radv_image_has_CB_metadata(image))
2260 flush_CB_meta = false;
2261 if (!radv_image_has_htile(image))
2262 flush_DB_meta = false;
2263 }
2264
2265 for_each_bit(b, src_flags) {
2266 switch ((VkAccessFlagBits)(1 << b)) {
2267 case VK_ACCESS_SHADER_WRITE_BIT:
2268 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2269 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2270 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2271 break;
2272 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2273 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2274 if (flush_CB_meta)
2275 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2276 break;
2277 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2278 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2279 if (flush_DB_meta)
2280 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2281 break;
2282 case VK_ACCESS_TRANSFER_WRITE_BIT:
2283 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2284 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2285 RADV_CMD_FLAG_INV_GLOBAL_L2;
2286
2287 if (flush_CB_meta)
2288 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2289 if (flush_DB_meta)
2290 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2291 break;
2292 default:
2293 break;
2294 }
2295 }
2296 return flush_bits;
2297 }
2298
2299 static enum radv_cmd_flush_bits
2300 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2301 VkAccessFlags dst_flags,
2302 struct radv_image *image)
2303 {
2304 bool flush_CB_meta = true, flush_DB_meta = true;
2305 enum radv_cmd_flush_bits flush_bits = 0;
2306 bool flush_CB = true, flush_DB = true;
2307 bool image_is_coherent = false;
2308 uint32_t b;
2309
2310 if (image) {
2311 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2312 flush_CB = false;
2313 flush_DB = false;
2314 }
2315
2316 if (!radv_image_has_CB_metadata(image))
2317 flush_CB_meta = false;
2318 if (!radv_image_has_htile(image))
2319 flush_DB_meta = false;
2320
2321 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2322 if (image->info.samples == 1 &&
2323 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2324 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2325 !vk_format_is_stencil(image->vk_format)) {
2326 /* Single-sample color and single-sample depth
2327 * (not stencil) are coherent with shaders on
2328 * GFX9.
2329 */
2330 image_is_coherent = true;
2331 }
2332 }
2333 }
2334
2335 for_each_bit(b, dst_flags) {
2336 switch ((VkAccessFlagBits)(1 << b)) {
2337 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2338 case VK_ACCESS_INDEX_READ_BIT:
2339 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2340 break;
2341 case VK_ACCESS_UNIFORM_READ_BIT:
2342 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2343 break;
2344 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2345 case VK_ACCESS_TRANSFER_READ_BIT:
2346 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2347 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2348 RADV_CMD_FLAG_INV_GLOBAL_L2;
2349 break;
2350 case VK_ACCESS_SHADER_READ_BIT:
2351 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2352
2353 if (!image_is_coherent)
2354 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2355 break;
2356 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2357 if (flush_CB)
2358 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2359 if (flush_CB_meta)
2360 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2361 break;
2362 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2363 if (flush_DB)
2364 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2365 if (flush_DB_meta)
2366 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2367 break;
2368 default:
2369 break;
2370 }
2371 }
2372 return flush_bits;
2373 }
2374
2375 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2376 const struct radv_subpass_barrier *barrier)
2377 {
2378 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2379 NULL);
2380 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2381 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2382 NULL);
2383 }
2384
2385 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2386 struct radv_subpass_attachment att)
2387 {
2388 unsigned idx = att.attachment;
2389 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2390 VkImageSubresourceRange range;
2391 range.aspectMask = 0;
2392 range.baseMipLevel = view->base_mip;
2393 range.levelCount = 1;
2394 range.baseArrayLayer = view->base_layer;
2395 range.layerCount = cmd_buffer->state.framebuffer->layers;
2396
2397 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
2398 /* If the current subpass uses multiview, the driver might have
2399 * performed a fast color/depth clear to the whole image
2400 * (including all layers). To make sure the driver will
2401 * decompress the image correctly (if needed), we have to
2402 * account for the "real" number of layers. If the view mask is
2403 * sparse, this will decompress more layers than needed.
2404 */
2405 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2406 }
2407
2408 radv_handle_image_transition(cmd_buffer,
2409 view->image,
2410 cmd_buffer->state.attachments[idx].current_layout,
2411 att.layout, 0, 0, &range);
2412
2413 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2414
2415
2416 }
2417
2418 void
2419 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2420 const struct radv_subpass *subpass, bool transitions)
2421 {
2422 if (transitions) {
2423 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2424
2425 for (unsigned i = 0; i < subpass->color_count; ++i) {
2426 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2427 radv_handle_subpass_image_transition(cmd_buffer,
2428 subpass->color_attachments[i]);
2429 }
2430
2431 for (unsigned i = 0; i < subpass->input_count; ++i) {
2432 radv_handle_subpass_image_transition(cmd_buffer,
2433 subpass->input_attachments[i]);
2434 }
2435
2436 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2437 radv_handle_subpass_image_transition(cmd_buffer,
2438 subpass->depth_stencil_attachment);
2439 }
2440 }
2441
2442 cmd_buffer->state.subpass = subpass;
2443
2444 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2445 }
2446
2447 static VkResult
2448 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2449 struct radv_render_pass *pass,
2450 const VkRenderPassBeginInfo *info)
2451 {
2452 struct radv_cmd_state *state = &cmd_buffer->state;
2453
2454 if (pass->attachment_count == 0) {
2455 state->attachments = NULL;
2456 return VK_SUCCESS;
2457 }
2458
2459 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2460 pass->attachment_count *
2461 sizeof(state->attachments[0]),
2462 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2463 if (state->attachments == NULL) {
2464 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2465 return cmd_buffer->record_result;
2466 }
2467
2468 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2469 struct radv_render_pass_attachment *att = &pass->attachments[i];
2470 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2471 VkImageAspectFlags clear_aspects = 0;
2472
2473 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2474 /* color attachment */
2475 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2476 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2477 }
2478 } else {
2479 /* depthstencil attachment */
2480 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2481 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2482 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2483 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2484 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2485 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2486 }
2487 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2488 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2489 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2490 }
2491 }
2492
2493 state->attachments[i].pending_clear_aspects = clear_aspects;
2494 state->attachments[i].cleared_views = 0;
2495 if (clear_aspects && info) {
2496 assert(info->clearValueCount > i);
2497 state->attachments[i].clear_value = info->pClearValues[i];
2498 }
2499
2500 state->attachments[i].current_layout = att->initial_layout;
2501 }
2502
2503 return VK_SUCCESS;
2504 }
2505
2506 VkResult radv_AllocateCommandBuffers(
2507 VkDevice _device,
2508 const VkCommandBufferAllocateInfo *pAllocateInfo,
2509 VkCommandBuffer *pCommandBuffers)
2510 {
2511 RADV_FROM_HANDLE(radv_device, device, _device);
2512 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2513
2514 VkResult result = VK_SUCCESS;
2515 uint32_t i;
2516
2517 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2518
2519 if (!list_empty(&pool->free_cmd_buffers)) {
2520 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2521
2522 list_del(&cmd_buffer->pool_link);
2523 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2524
2525 result = radv_reset_cmd_buffer(cmd_buffer);
2526 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2527 cmd_buffer->level = pAllocateInfo->level;
2528
2529 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2530 } else {
2531 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2532 &pCommandBuffers[i]);
2533 }
2534 if (result != VK_SUCCESS)
2535 break;
2536 }
2537
2538 if (result != VK_SUCCESS) {
2539 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2540 i, pCommandBuffers);
2541
2542 /* From the Vulkan 1.0.66 spec:
2543 *
2544 * "vkAllocateCommandBuffers can be used to create multiple
2545 * command buffers. If the creation of any of those command
2546 * buffers fails, the implementation must destroy all
2547 * successfully created command buffer objects from this
2548 * command, set all entries of the pCommandBuffers array to
2549 * NULL and return the error."
2550 */
2551 memset(pCommandBuffers, 0,
2552 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2553 }
2554
2555 return result;
2556 }
2557
2558 void radv_FreeCommandBuffers(
2559 VkDevice device,
2560 VkCommandPool commandPool,
2561 uint32_t commandBufferCount,
2562 const VkCommandBuffer *pCommandBuffers)
2563 {
2564 for (uint32_t i = 0; i < commandBufferCount; i++) {
2565 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2566
2567 if (cmd_buffer) {
2568 if (cmd_buffer->pool) {
2569 list_del(&cmd_buffer->pool_link);
2570 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2571 } else
2572 radv_cmd_buffer_destroy(cmd_buffer);
2573
2574 }
2575 }
2576 }
2577
2578 VkResult radv_ResetCommandBuffer(
2579 VkCommandBuffer commandBuffer,
2580 VkCommandBufferResetFlags flags)
2581 {
2582 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2583 return radv_reset_cmd_buffer(cmd_buffer);
2584 }
2585
2586 VkResult radv_BeginCommandBuffer(
2587 VkCommandBuffer commandBuffer,
2588 const VkCommandBufferBeginInfo *pBeginInfo)
2589 {
2590 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2591 VkResult result = VK_SUCCESS;
2592
2593 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2594 /* If the command buffer has already been resetted with
2595 * vkResetCommandBuffer, no need to do it again.
2596 */
2597 result = radv_reset_cmd_buffer(cmd_buffer);
2598 if (result != VK_SUCCESS)
2599 return result;
2600 }
2601
2602 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2603 cmd_buffer->state.last_primitive_reset_en = -1;
2604 cmd_buffer->state.last_index_type = -1;
2605 cmd_buffer->state.last_num_instances = -1;
2606 cmd_buffer->state.last_vertex_offset = -1;
2607 cmd_buffer->state.last_first_instance = -1;
2608 cmd_buffer->state.predication_type = -1;
2609 cmd_buffer->usage_flags = pBeginInfo->flags;
2610
2611 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2612 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2613 assert(pBeginInfo->pInheritanceInfo);
2614 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2615 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2616
2617 struct radv_subpass *subpass =
2618 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2619
2620 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2621 if (result != VK_SUCCESS)
2622 return result;
2623
2624 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2625 }
2626
2627 if (unlikely(cmd_buffer->device->trace_bo)) {
2628 struct radv_device *device = cmd_buffer->device;
2629
2630 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2631 device->trace_bo);
2632
2633 radv_cmd_buffer_trace_emit(cmd_buffer);
2634 }
2635
2636 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2637
2638 return result;
2639 }
2640
2641 void radv_CmdBindVertexBuffers(
2642 VkCommandBuffer commandBuffer,
2643 uint32_t firstBinding,
2644 uint32_t bindingCount,
2645 const VkBuffer* pBuffers,
2646 const VkDeviceSize* pOffsets)
2647 {
2648 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2649 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2650 bool changed = false;
2651
2652 /* We have to defer setting up vertex buffer since we need the buffer
2653 * stride from the pipeline. */
2654
2655 assert(firstBinding + bindingCount <= MAX_VBS);
2656 for (uint32_t i = 0; i < bindingCount; i++) {
2657 uint32_t idx = firstBinding + i;
2658
2659 if (!changed &&
2660 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2661 vb[idx].offset != pOffsets[i])) {
2662 changed = true;
2663 }
2664
2665 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2666 vb[idx].offset = pOffsets[i];
2667
2668 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2669 vb[idx].buffer->bo);
2670 }
2671
2672 if (!changed) {
2673 /* No state changes. */
2674 return;
2675 }
2676
2677 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2678 }
2679
2680 void radv_CmdBindIndexBuffer(
2681 VkCommandBuffer commandBuffer,
2682 VkBuffer buffer,
2683 VkDeviceSize offset,
2684 VkIndexType indexType)
2685 {
2686 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2687 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2688
2689 if (cmd_buffer->state.index_buffer == index_buffer &&
2690 cmd_buffer->state.index_offset == offset &&
2691 cmd_buffer->state.index_type == indexType) {
2692 /* No state changes. */
2693 return;
2694 }
2695
2696 cmd_buffer->state.index_buffer = index_buffer;
2697 cmd_buffer->state.index_offset = offset;
2698 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2699 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2700 cmd_buffer->state.index_va += index_buffer->offset + offset;
2701
2702 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2703 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2704 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2705 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2706 }
2707
2708
2709 static void
2710 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2711 VkPipelineBindPoint bind_point,
2712 struct radv_descriptor_set *set, unsigned idx)
2713 {
2714 struct radeon_winsys *ws = cmd_buffer->device->ws;
2715
2716 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2717
2718 assert(set);
2719 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2720
2721 if (!cmd_buffer->device->use_global_bo_list) {
2722 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2723 if (set->descriptors[j])
2724 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2725 }
2726
2727 if(set->bo)
2728 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2729 }
2730
2731 void radv_CmdBindDescriptorSets(
2732 VkCommandBuffer commandBuffer,
2733 VkPipelineBindPoint pipelineBindPoint,
2734 VkPipelineLayout _layout,
2735 uint32_t firstSet,
2736 uint32_t descriptorSetCount,
2737 const VkDescriptorSet* pDescriptorSets,
2738 uint32_t dynamicOffsetCount,
2739 const uint32_t* pDynamicOffsets)
2740 {
2741 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2742 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2743 unsigned dyn_idx = 0;
2744
2745 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2746 struct radv_descriptor_state *descriptors_state =
2747 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2748
2749 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2750 unsigned idx = i + firstSet;
2751 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2752 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2753
2754 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2755 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2756 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2757 assert(dyn_idx < dynamicOffsetCount);
2758
2759 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2760 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2761 dst[0] = va;
2762 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2763 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2764 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2765 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2766 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2767 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2768 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2769 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2770 cmd_buffer->push_constant_stages |=
2771 set->layout->dynamic_shader_stages;
2772 }
2773 }
2774 }
2775
2776 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2777 struct radv_descriptor_set *set,
2778 struct radv_descriptor_set_layout *layout,
2779 VkPipelineBindPoint bind_point)
2780 {
2781 struct radv_descriptor_state *descriptors_state =
2782 radv_get_descriptors_state(cmd_buffer, bind_point);
2783 set->size = layout->size;
2784 set->layout = layout;
2785
2786 if (descriptors_state->push_set.capacity < set->size) {
2787 size_t new_size = MAX2(set->size, 1024);
2788 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2789 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2790
2791 free(set->mapped_ptr);
2792 set->mapped_ptr = malloc(new_size);
2793
2794 if (!set->mapped_ptr) {
2795 descriptors_state->push_set.capacity = 0;
2796 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2797 return false;
2798 }
2799
2800 descriptors_state->push_set.capacity = new_size;
2801 }
2802
2803 return true;
2804 }
2805
2806 void radv_meta_push_descriptor_set(
2807 struct radv_cmd_buffer* cmd_buffer,
2808 VkPipelineBindPoint pipelineBindPoint,
2809 VkPipelineLayout _layout,
2810 uint32_t set,
2811 uint32_t descriptorWriteCount,
2812 const VkWriteDescriptorSet* pDescriptorWrites)
2813 {
2814 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2815 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2816 unsigned bo_offset;
2817
2818 assert(set == 0);
2819 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2820
2821 push_set->size = layout->set[set].layout->size;
2822 push_set->layout = layout->set[set].layout;
2823
2824 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2825 &bo_offset,
2826 (void**) &push_set->mapped_ptr))
2827 return;
2828
2829 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2830 push_set->va += bo_offset;
2831
2832 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2833 radv_descriptor_set_to_handle(push_set),
2834 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2835
2836 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2837 }
2838
2839 void radv_CmdPushDescriptorSetKHR(
2840 VkCommandBuffer commandBuffer,
2841 VkPipelineBindPoint pipelineBindPoint,
2842 VkPipelineLayout _layout,
2843 uint32_t set,
2844 uint32_t descriptorWriteCount,
2845 const VkWriteDescriptorSet* pDescriptorWrites)
2846 {
2847 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2848 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2849 struct radv_descriptor_state *descriptors_state =
2850 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2851 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2852
2853 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2854
2855 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2856 layout->set[set].layout,
2857 pipelineBindPoint))
2858 return;
2859
2860 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2861 radv_descriptor_set_to_handle(push_set),
2862 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2863
2864 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2865 descriptors_state->push_dirty = true;
2866 }
2867
2868 void radv_CmdPushDescriptorSetWithTemplateKHR(
2869 VkCommandBuffer commandBuffer,
2870 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2871 VkPipelineLayout _layout,
2872 uint32_t set,
2873 const void* pData)
2874 {
2875 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2876 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2877 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2878 struct radv_descriptor_state *descriptors_state =
2879 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2880 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2881
2882 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2883
2884 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2885 layout->set[set].layout,
2886 templ->bind_point))
2887 return;
2888
2889 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2890 descriptorUpdateTemplate, pData);
2891
2892 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2893 descriptors_state->push_dirty = true;
2894 }
2895
2896 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2897 VkPipelineLayout layout,
2898 VkShaderStageFlags stageFlags,
2899 uint32_t offset,
2900 uint32_t size,
2901 const void* pValues)
2902 {
2903 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2904 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2905 cmd_buffer->push_constant_stages |= stageFlags;
2906 }
2907
2908 VkResult radv_EndCommandBuffer(
2909 VkCommandBuffer commandBuffer)
2910 {
2911 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2912
2913 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2914 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2915 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2916 si_emit_cache_flush(cmd_buffer);
2917 }
2918
2919 /* Make sure CP DMA is idle at the end of IBs because the kernel
2920 * doesn't wait for it.
2921 */
2922 si_cp_dma_wait_for_idle(cmd_buffer);
2923
2924 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2925
2926 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2927 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2928
2929 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2930
2931 return cmd_buffer->record_result;
2932 }
2933
2934 static void
2935 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2936 {
2937 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2938
2939 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2940 return;
2941
2942 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2943
2944 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2945 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2946
2947 cmd_buffer->compute_scratch_size_needed =
2948 MAX2(cmd_buffer->compute_scratch_size_needed,
2949 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2950
2951 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2952 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2953
2954 if (unlikely(cmd_buffer->device->trace_bo))
2955 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2956 }
2957
2958 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2959 VkPipelineBindPoint bind_point)
2960 {
2961 struct radv_descriptor_state *descriptors_state =
2962 radv_get_descriptors_state(cmd_buffer, bind_point);
2963
2964 descriptors_state->dirty |= descriptors_state->valid;
2965 }
2966
2967 void radv_CmdBindPipeline(
2968 VkCommandBuffer commandBuffer,
2969 VkPipelineBindPoint pipelineBindPoint,
2970 VkPipeline _pipeline)
2971 {
2972 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2973 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2974
2975 switch (pipelineBindPoint) {
2976 case VK_PIPELINE_BIND_POINT_COMPUTE:
2977 if (cmd_buffer->state.compute_pipeline == pipeline)
2978 return;
2979 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2980
2981 cmd_buffer->state.compute_pipeline = pipeline;
2982 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2983 break;
2984 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2985 if (cmd_buffer->state.pipeline == pipeline)
2986 return;
2987 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2988
2989 cmd_buffer->state.pipeline = pipeline;
2990 if (!pipeline)
2991 break;
2992
2993 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2994 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2995
2996 /* the new vertex shader might not have the same user regs */
2997 cmd_buffer->state.last_first_instance = -1;
2998 cmd_buffer->state.last_vertex_offset = -1;
2999
3000 /* Prefetch all pipeline shaders at first draw time. */
3001 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3002
3003 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3004 radv_bind_streamout_state(cmd_buffer, pipeline);
3005
3006 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3007 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3008 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3009 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3010
3011 if (radv_pipeline_has_tess(pipeline))
3012 cmd_buffer->tess_rings_needed = true;
3013 break;
3014 default:
3015 assert(!"invalid bind point");
3016 break;
3017 }
3018 }
3019
3020 void radv_CmdSetViewport(
3021 VkCommandBuffer commandBuffer,
3022 uint32_t firstViewport,
3023 uint32_t viewportCount,
3024 const VkViewport* pViewports)
3025 {
3026 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3027 struct radv_cmd_state *state = &cmd_buffer->state;
3028 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3029
3030 assert(firstViewport < MAX_VIEWPORTS);
3031 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3032
3033 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3034 viewportCount * sizeof(*pViewports));
3035
3036 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3037 }
3038
3039 void radv_CmdSetScissor(
3040 VkCommandBuffer commandBuffer,
3041 uint32_t firstScissor,
3042 uint32_t scissorCount,
3043 const VkRect2D* pScissors)
3044 {
3045 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3046 struct radv_cmd_state *state = &cmd_buffer->state;
3047 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3048
3049 assert(firstScissor < MAX_SCISSORS);
3050 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3051
3052 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3053 scissorCount * sizeof(*pScissors));
3054
3055 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3056 }
3057
3058 void radv_CmdSetLineWidth(
3059 VkCommandBuffer commandBuffer,
3060 float lineWidth)
3061 {
3062 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3063 cmd_buffer->state.dynamic.line_width = lineWidth;
3064 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3065 }
3066
3067 void radv_CmdSetDepthBias(
3068 VkCommandBuffer commandBuffer,
3069 float depthBiasConstantFactor,
3070 float depthBiasClamp,
3071 float depthBiasSlopeFactor)
3072 {
3073 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3074
3075 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
3076 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
3077 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
3078
3079 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3080 }
3081
3082 void radv_CmdSetBlendConstants(
3083 VkCommandBuffer commandBuffer,
3084 const float blendConstants[4])
3085 {
3086 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3087
3088 memcpy(cmd_buffer->state.dynamic.blend_constants,
3089 blendConstants, sizeof(float) * 4);
3090
3091 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3092 }
3093
3094 void radv_CmdSetDepthBounds(
3095 VkCommandBuffer commandBuffer,
3096 float minDepthBounds,
3097 float maxDepthBounds)
3098 {
3099 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3100
3101 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
3102 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
3103
3104 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3105 }
3106
3107 void radv_CmdSetStencilCompareMask(
3108 VkCommandBuffer commandBuffer,
3109 VkStencilFaceFlags faceMask,
3110 uint32_t compareMask)
3111 {
3112 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3113
3114 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3115 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
3116 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3117 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
3118
3119 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3120 }
3121
3122 void radv_CmdSetStencilWriteMask(
3123 VkCommandBuffer commandBuffer,
3124 VkStencilFaceFlags faceMask,
3125 uint32_t writeMask)
3126 {
3127 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3128
3129 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3130 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
3131 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3132 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
3133
3134 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3135 }
3136
3137 void radv_CmdSetStencilReference(
3138 VkCommandBuffer commandBuffer,
3139 VkStencilFaceFlags faceMask,
3140 uint32_t reference)
3141 {
3142 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3143
3144 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3145 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3146 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3147 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3148
3149 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3150 }
3151
3152 void radv_CmdSetDiscardRectangleEXT(
3153 VkCommandBuffer commandBuffer,
3154 uint32_t firstDiscardRectangle,
3155 uint32_t discardRectangleCount,
3156 const VkRect2D* pDiscardRectangles)
3157 {
3158 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3159 struct radv_cmd_state *state = &cmd_buffer->state;
3160 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3161
3162 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3163 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3164
3165 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3166 pDiscardRectangles, discardRectangleCount);
3167
3168 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3169 }
3170
3171 void radv_CmdExecuteCommands(
3172 VkCommandBuffer commandBuffer,
3173 uint32_t commandBufferCount,
3174 const VkCommandBuffer* pCmdBuffers)
3175 {
3176 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3177
3178 assert(commandBufferCount > 0);
3179
3180 /* Emit pending flushes on primary prior to executing secondary */
3181 si_emit_cache_flush(primary);
3182
3183 for (uint32_t i = 0; i < commandBufferCount; i++) {
3184 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3185
3186 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3187 secondary->scratch_size_needed);
3188 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3189 secondary->compute_scratch_size_needed);
3190
3191 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3192 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3193 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3194 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3195 if (secondary->tess_rings_needed)
3196 primary->tess_rings_needed = true;
3197 if (secondary->sample_positions_needed)
3198 primary->sample_positions_needed = true;
3199
3200 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3201
3202
3203 /* When the secondary command buffer is compute only we don't
3204 * need to re-emit the current graphics pipeline.
3205 */
3206 if (secondary->state.emitted_pipeline) {
3207 primary->state.emitted_pipeline =
3208 secondary->state.emitted_pipeline;
3209 }
3210
3211 /* When the secondary command buffer is graphics only we don't
3212 * need to re-emit the current compute pipeline.
3213 */
3214 if (secondary->state.emitted_compute_pipeline) {
3215 primary->state.emitted_compute_pipeline =
3216 secondary->state.emitted_compute_pipeline;
3217 }
3218
3219 /* Only re-emit the draw packets when needed. */
3220 if (secondary->state.last_primitive_reset_en != -1) {
3221 primary->state.last_primitive_reset_en =
3222 secondary->state.last_primitive_reset_en;
3223 }
3224
3225 if (secondary->state.last_primitive_reset_index) {
3226 primary->state.last_primitive_reset_index =
3227 secondary->state.last_primitive_reset_index;
3228 }
3229
3230 if (secondary->state.last_ia_multi_vgt_param) {
3231 primary->state.last_ia_multi_vgt_param =
3232 secondary->state.last_ia_multi_vgt_param;
3233 }
3234
3235 primary->state.last_first_instance = secondary->state.last_first_instance;
3236 primary->state.last_num_instances = secondary->state.last_num_instances;
3237 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3238
3239 if (secondary->state.last_index_type != -1) {
3240 primary->state.last_index_type =
3241 secondary->state.last_index_type;
3242 }
3243 }
3244
3245 /* After executing commands from secondary buffers we have to dirty
3246 * some states.
3247 */
3248 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3249 RADV_CMD_DIRTY_INDEX_BUFFER |
3250 RADV_CMD_DIRTY_DYNAMIC_ALL;
3251 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3252 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3253 }
3254
3255 VkResult radv_CreateCommandPool(
3256 VkDevice _device,
3257 const VkCommandPoolCreateInfo* pCreateInfo,
3258 const VkAllocationCallbacks* pAllocator,
3259 VkCommandPool* pCmdPool)
3260 {
3261 RADV_FROM_HANDLE(radv_device, device, _device);
3262 struct radv_cmd_pool *pool;
3263
3264 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3265 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3266 if (pool == NULL)
3267 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3268
3269 if (pAllocator)
3270 pool->alloc = *pAllocator;
3271 else
3272 pool->alloc = device->alloc;
3273
3274 list_inithead(&pool->cmd_buffers);
3275 list_inithead(&pool->free_cmd_buffers);
3276
3277 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3278
3279 *pCmdPool = radv_cmd_pool_to_handle(pool);
3280
3281 return VK_SUCCESS;
3282
3283 }
3284
3285 void radv_DestroyCommandPool(
3286 VkDevice _device,
3287 VkCommandPool commandPool,
3288 const VkAllocationCallbacks* pAllocator)
3289 {
3290 RADV_FROM_HANDLE(radv_device, device, _device);
3291 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3292
3293 if (!pool)
3294 return;
3295
3296 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3297 &pool->cmd_buffers, pool_link) {
3298 radv_cmd_buffer_destroy(cmd_buffer);
3299 }
3300
3301 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3302 &pool->free_cmd_buffers, pool_link) {
3303 radv_cmd_buffer_destroy(cmd_buffer);
3304 }
3305
3306 vk_free2(&device->alloc, pAllocator, pool);
3307 }
3308
3309 VkResult radv_ResetCommandPool(
3310 VkDevice device,
3311 VkCommandPool commandPool,
3312 VkCommandPoolResetFlags flags)
3313 {
3314 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3315 VkResult result;
3316
3317 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3318 &pool->cmd_buffers, pool_link) {
3319 result = radv_reset_cmd_buffer(cmd_buffer);
3320 if (result != VK_SUCCESS)
3321 return result;
3322 }
3323
3324 return VK_SUCCESS;
3325 }
3326
3327 void radv_TrimCommandPool(
3328 VkDevice device,
3329 VkCommandPool commandPool,
3330 VkCommandPoolTrimFlags flags)
3331 {
3332 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3333
3334 if (!pool)
3335 return;
3336
3337 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3338 &pool->free_cmd_buffers, pool_link) {
3339 radv_cmd_buffer_destroy(cmd_buffer);
3340 }
3341 }
3342
3343 void radv_CmdBeginRenderPass(
3344 VkCommandBuffer commandBuffer,
3345 const VkRenderPassBeginInfo* pRenderPassBegin,
3346 VkSubpassContents contents)
3347 {
3348 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3349 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3350 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3351
3352 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3353 cmd_buffer->cs, 2048);
3354 MAYBE_UNUSED VkResult result;
3355
3356 cmd_buffer->state.framebuffer = framebuffer;
3357 cmd_buffer->state.pass = pass;
3358 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3359
3360 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3361 if (result != VK_SUCCESS)
3362 return;
3363
3364 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3365 assert(cmd_buffer->cs->cdw <= cdw_max);
3366
3367 radv_cmd_buffer_clear_subpass(cmd_buffer);
3368 }
3369
3370 void radv_CmdBeginRenderPass2KHR(
3371 VkCommandBuffer commandBuffer,
3372 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3373 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3374 {
3375 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3376 pSubpassBeginInfo->contents);
3377 }
3378
3379 void radv_CmdNextSubpass(
3380 VkCommandBuffer commandBuffer,
3381 VkSubpassContents contents)
3382 {
3383 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3384
3385 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3386
3387 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3388 2048);
3389
3390 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3391 radv_cmd_buffer_clear_subpass(cmd_buffer);
3392 }
3393
3394 void radv_CmdNextSubpass2KHR(
3395 VkCommandBuffer commandBuffer,
3396 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3397 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3398 {
3399 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3400 }
3401
3402 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3403 {
3404 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3405 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3406 if (!radv_get_shader(pipeline, stage))
3407 continue;
3408
3409 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3410 if (loc->sgpr_idx == -1)
3411 continue;
3412 uint32_t base_reg = pipeline->user_data_0[stage];
3413 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3414
3415 }
3416 if (pipeline->gs_copy_shader) {
3417 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3418 if (loc->sgpr_idx != -1) {
3419 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3420 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3421 }
3422 }
3423 }
3424
3425 static void
3426 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3427 uint32_t vertex_count,
3428 bool use_opaque)
3429 {
3430 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3431 radeon_emit(cmd_buffer->cs, vertex_count);
3432 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3433 S_0287F0_USE_OPAQUE(use_opaque));
3434 }
3435
3436 static void
3437 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3438 uint64_t index_va,
3439 uint32_t index_count)
3440 {
3441 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3442 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3443 radeon_emit(cmd_buffer->cs, index_va);
3444 radeon_emit(cmd_buffer->cs, index_va >> 32);
3445 radeon_emit(cmd_buffer->cs, index_count);
3446 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3447 }
3448
3449 static void
3450 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3451 bool indexed,
3452 uint32_t draw_count,
3453 uint64_t count_va,
3454 uint32_t stride)
3455 {
3456 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3457 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3458 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3459 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3460 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3461 bool predicating = cmd_buffer->state.predicating;
3462 assert(base_reg);
3463
3464 /* just reset draw state for vertex data */
3465 cmd_buffer->state.last_first_instance = -1;
3466 cmd_buffer->state.last_num_instances = -1;
3467 cmd_buffer->state.last_vertex_offset = -1;
3468
3469 if (draw_count == 1 && !count_va && !draw_id_enable) {
3470 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3471 PKT3_DRAW_INDIRECT, 3, predicating));
3472 radeon_emit(cs, 0);
3473 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3474 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3475 radeon_emit(cs, di_src_sel);
3476 } else {
3477 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3478 PKT3_DRAW_INDIRECT_MULTI,
3479 8, predicating));
3480 radeon_emit(cs, 0);
3481 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3482 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3483 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3484 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3485 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3486 radeon_emit(cs, draw_count); /* count */
3487 radeon_emit(cs, count_va); /* count_addr */
3488 radeon_emit(cs, count_va >> 32);
3489 radeon_emit(cs, stride); /* stride */
3490 radeon_emit(cs, di_src_sel);
3491 }
3492 }
3493
3494 static void
3495 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3496 const struct radv_draw_info *info)
3497 {
3498 struct radv_cmd_state *state = &cmd_buffer->state;
3499 struct radeon_winsys *ws = cmd_buffer->device->ws;
3500 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3501
3502 if (info->indirect) {
3503 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3504 uint64_t count_va = 0;
3505
3506 va += info->indirect->offset + info->indirect_offset;
3507
3508 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3509
3510 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3511 radeon_emit(cs, 1);
3512 radeon_emit(cs, va);
3513 radeon_emit(cs, va >> 32);
3514
3515 if (info->count_buffer) {
3516 count_va = radv_buffer_get_va(info->count_buffer->bo);
3517 count_va += info->count_buffer->offset +
3518 info->count_buffer_offset;
3519
3520 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3521 }
3522
3523 if (!state->subpass->view_mask) {
3524 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3525 info->indexed,
3526 info->count,
3527 count_va,
3528 info->stride);
3529 } else {
3530 unsigned i;
3531 for_each_bit(i, state->subpass->view_mask) {
3532 radv_emit_view_index(cmd_buffer, i);
3533
3534 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3535 info->indexed,
3536 info->count,
3537 count_va,
3538 info->stride);
3539 }
3540 }
3541 } else {
3542 assert(state->pipeline->graphics.vtx_base_sgpr);
3543
3544 if (info->vertex_offset != state->last_vertex_offset ||
3545 info->first_instance != state->last_first_instance) {
3546 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3547 state->pipeline->graphics.vtx_emit_num);
3548
3549 radeon_emit(cs, info->vertex_offset);
3550 radeon_emit(cs, info->first_instance);
3551 if (state->pipeline->graphics.vtx_emit_num == 3)
3552 radeon_emit(cs, 0);
3553 state->last_first_instance = info->first_instance;
3554 state->last_vertex_offset = info->vertex_offset;
3555 }
3556
3557 if (state->last_num_instances != info->instance_count) {
3558 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3559 radeon_emit(cs, info->instance_count);
3560 state->last_num_instances = info->instance_count;
3561 }
3562
3563 if (info->indexed) {
3564 int index_size = state->index_type ? 4 : 2;
3565 uint64_t index_va;
3566
3567 index_va = state->index_va;
3568 index_va += info->first_index * index_size;
3569
3570 if (!state->subpass->view_mask) {
3571 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3572 index_va,
3573 info->count);
3574 } else {
3575 unsigned i;
3576 for_each_bit(i, state->subpass->view_mask) {
3577 radv_emit_view_index(cmd_buffer, i);
3578
3579 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3580 index_va,
3581 info->count);
3582 }
3583 }
3584 } else {
3585 if (!state->subpass->view_mask) {
3586 radv_cs_emit_draw_packet(cmd_buffer,
3587 info->count,
3588 !!info->strmout_buffer);
3589 } else {
3590 unsigned i;
3591 for_each_bit(i, state->subpass->view_mask) {
3592 radv_emit_view_index(cmd_buffer, i);
3593
3594 radv_cs_emit_draw_packet(cmd_buffer,
3595 info->count,
3596 !!info->strmout_buffer);
3597 }
3598 }
3599 }
3600 }
3601 }
3602
3603 /*
3604 * Vega and raven have a bug which triggers if there are multiple context
3605 * register contexts active at the same time with different scissor values.
3606 *
3607 * There are two possible workarounds:
3608 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3609 * there is only ever 1 active set of scissor values at the same time.
3610 *
3611 * 2) Whenever the hardware switches contexts we have to set the scissor
3612 * registers again even if it is a noop. That way the new context gets
3613 * the correct scissor values.
3614 *
3615 * This implements option 2. radv_need_late_scissor_emission needs to
3616 * return true on affected HW if radv_emit_all_graphics_states sets
3617 * any context registers.
3618 */
3619 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3620 const struct radv_draw_info *info)
3621 {
3622 struct radv_cmd_state *state = &cmd_buffer->state;
3623
3624 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3625 return false;
3626
3627 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
3628 return true;
3629
3630 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3631
3632 /* Index, vertex and streamout buffers don't change context regs, and
3633 * pipeline is handled later.
3634 */
3635 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3636 RADV_CMD_DIRTY_VERTEX_BUFFER |
3637 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3638 RADV_CMD_DIRTY_PIPELINE);
3639
3640 /* Assume all state changes except these two can imply context rolls. */
3641 if (cmd_buffer->state.dirty & used_states)
3642 return true;
3643
3644 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3645 return true;
3646
3647 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
3648 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3649 return true;
3650
3651 return false;
3652 }
3653
3654 static void
3655 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3656 const struct radv_draw_info *info)
3657 {
3658 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info);
3659
3660 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3661 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3662 radv_emit_rbplus_state(cmd_buffer);
3663
3664 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3665 radv_emit_graphics_pipeline(cmd_buffer);
3666
3667 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3668 radv_emit_framebuffer_state(cmd_buffer);
3669
3670 if (info->indexed) {
3671 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3672 radv_emit_index_buffer(cmd_buffer);
3673 } else {
3674 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3675 * so the state must be re-emitted before the next indexed
3676 * draw.
3677 */
3678 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3679 cmd_buffer->state.last_index_type = -1;
3680 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3681 }
3682 }
3683
3684 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3685
3686 radv_emit_draw_registers(cmd_buffer, info);
3687
3688 if (late_scissor_emission)
3689 radv_emit_scissor(cmd_buffer);
3690 }
3691
3692 static void
3693 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3694 const struct radv_draw_info *info)
3695 {
3696 struct radeon_info *rad_info =
3697 &cmd_buffer->device->physical_device->rad_info;
3698 bool has_prefetch =
3699 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3700 bool pipeline_is_dirty =
3701 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3702 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3703
3704 MAYBE_UNUSED unsigned cdw_max =
3705 radeon_check_space(cmd_buffer->device->ws,
3706 cmd_buffer->cs, 4096);
3707
3708 if (likely(!info->indirect)) {
3709 /* SI-CI treat instance_count==0 as instance_count==1. There is
3710 * no workaround for indirect draws, but we can at least skip
3711 * direct draws.
3712 */
3713 if (unlikely(!info->instance_count))
3714 return;
3715
3716 /* Handle count == 0. */
3717 if (unlikely(!info->count && !info->strmout_buffer))
3718 return;
3719 }
3720
3721 /* Use optimal packet order based on whether we need to sync the
3722 * pipeline.
3723 */
3724 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3725 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3726 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3727 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3728 /* If we have to wait for idle, set all states first, so that
3729 * all SET packets are processed in parallel with previous draw
3730 * calls. Then upload descriptors, set shader pointers, and
3731 * draw, and prefetch at the end. This ensures that the time
3732 * the CUs are idle is very short. (there are only SET_SH
3733 * packets between the wait and the draw)
3734 */
3735 radv_emit_all_graphics_states(cmd_buffer, info);
3736 si_emit_cache_flush(cmd_buffer);
3737 /* <-- CUs are idle here --> */
3738
3739 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3740
3741 radv_emit_draw_packets(cmd_buffer, info);
3742 /* <-- CUs are busy here --> */
3743
3744 /* Start prefetches after the draw has been started. Both will
3745 * run in parallel, but starting the draw first is more
3746 * important.
3747 */
3748 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3749 radv_emit_prefetch_L2(cmd_buffer,
3750 cmd_buffer->state.pipeline, false);
3751 }
3752 } else {
3753 /* If we don't wait for idle, start prefetches first, then set
3754 * states, and draw at the end.
3755 */
3756 si_emit_cache_flush(cmd_buffer);
3757
3758 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3759 /* Only prefetch the vertex shader and VBO descriptors
3760 * in order to start the draw as soon as possible.
3761 */
3762 radv_emit_prefetch_L2(cmd_buffer,
3763 cmd_buffer->state.pipeline, true);
3764 }
3765
3766 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3767
3768 radv_emit_all_graphics_states(cmd_buffer, info);
3769 radv_emit_draw_packets(cmd_buffer, info);
3770
3771 /* Prefetch the remaining shaders after the draw has been
3772 * started.
3773 */
3774 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3775 radv_emit_prefetch_L2(cmd_buffer,
3776 cmd_buffer->state.pipeline, false);
3777 }
3778 }
3779
3780 /* Workaround for a VGT hang when streamout is enabled.
3781 * It must be done after drawing.
3782 */
3783 if (cmd_buffer->state.streamout.streamout_enabled &&
3784 (rad_info->family == CHIP_HAWAII ||
3785 rad_info->family == CHIP_TONGA ||
3786 rad_info->family == CHIP_FIJI)) {
3787 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3788 }
3789
3790 assert(cmd_buffer->cs->cdw <= cdw_max);
3791 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3792 }
3793
3794 void radv_CmdDraw(
3795 VkCommandBuffer commandBuffer,
3796 uint32_t vertexCount,
3797 uint32_t instanceCount,
3798 uint32_t firstVertex,
3799 uint32_t firstInstance)
3800 {
3801 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3802 struct radv_draw_info info = {};
3803
3804 info.count = vertexCount;
3805 info.instance_count = instanceCount;
3806 info.first_instance = firstInstance;
3807 info.vertex_offset = firstVertex;
3808
3809 radv_draw(cmd_buffer, &info);
3810 }
3811
3812 void radv_CmdDrawIndexed(
3813 VkCommandBuffer commandBuffer,
3814 uint32_t indexCount,
3815 uint32_t instanceCount,
3816 uint32_t firstIndex,
3817 int32_t vertexOffset,
3818 uint32_t firstInstance)
3819 {
3820 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3821 struct radv_draw_info info = {};
3822
3823 info.indexed = true;
3824 info.count = indexCount;
3825 info.instance_count = instanceCount;
3826 info.first_index = firstIndex;
3827 info.vertex_offset = vertexOffset;
3828 info.first_instance = firstInstance;
3829
3830 radv_draw(cmd_buffer, &info);
3831 }
3832
3833 void radv_CmdDrawIndirect(
3834 VkCommandBuffer commandBuffer,
3835 VkBuffer _buffer,
3836 VkDeviceSize offset,
3837 uint32_t drawCount,
3838 uint32_t stride)
3839 {
3840 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3841 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3842 struct radv_draw_info info = {};
3843
3844 info.count = drawCount;
3845 info.indirect = buffer;
3846 info.indirect_offset = offset;
3847 info.stride = stride;
3848
3849 radv_draw(cmd_buffer, &info);
3850 }
3851
3852 void radv_CmdDrawIndexedIndirect(
3853 VkCommandBuffer commandBuffer,
3854 VkBuffer _buffer,
3855 VkDeviceSize offset,
3856 uint32_t drawCount,
3857 uint32_t stride)
3858 {
3859 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3860 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3861 struct radv_draw_info info = {};
3862
3863 info.indexed = true;
3864 info.count = drawCount;
3865 info.indirect = buffer;
3866 info.indirect_offset = offset;
3867 info.stride = stride;
3868
3869 radv_draw(cmd_buffer, &info);
3870 }
3871
3872 void radv_CmdDrawIndirectCountAMD(
3873 VkCommandBuffer commandBuffer,
3874 VkBuffer _buffer,
3875 VkDeviceSize offset,
3876 VkBuffer _countBuffer,
3877 VkDeviceSize countBufferOffset,
3878 uint32_t maxDrawCount,
3879 uint32_t stride)
3880 {
3881 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3882 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3883 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3884 struct radv_draw_info info = {};
3885
3886 info.count = maxDrawCount;
3887 info.indirect = buffer;
3888 info.indirect_offset = offset;
3889 info.count_buffer = count_buffer;
3890 info.count_buffer_offset = countBufferOffset;
3891 info.stride = stride;
3892
3893 radv_draw(cmd_buffer, &info);
3894 }
3895
3896 void radv_CmdDrawIndexedIndirectCountAMD(
3897 VkCommandBuffer commandBuffer,
3898 VkBuffer _buffer,
3899 VkDeviceSize offset,
3900 VkBuffer _countBuffer,
3901 VkDeviceSize countBufferOffset,
3902 uint32_t maxDrawCount,
3903 uint32_t stride)
3904 {
3905 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3906 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3907 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3908 struct radv_draw_info info = {};
3909
3910 info.indexed = true;
3911 info.count = maxDrawCount;
3912 info.indirect = buffer;
3913 info.indirect_offset = offset;
3914 info.count_buffer = count_buffer;
3915 info.count_buffer_offset = countBufferOffset;
3916 info.stride = stride;
3917
3918 radv_draw(cmd_buffer, &info);
3919 }
3920
3921 void radv_CmdDrawIndirectCountKHR(
3922 VkCommandBuffer commandBuffer,
3923 VkBuffer _buffer,
3924 VkDeviceSize offset,
3925 VkBuffer _countBuffer,
3926 VkDeviceSize countBufferOffset,
3927 uint32_t maxDrawCount,
3928 uint32_t stride)
3929 {
3930 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3931 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3932 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3933 struct radv_draw_info info = {};
3934
3935 info.count = maxDrawCount;
3936 info.indirect = buffer;
3937 info.indirect_offset = offset;
3938 info.count_buffer = count_buffer;
3939 info.count_buffer_offset = countBufferOffset;
3940 info.stride = stride;
3941
3942 radv_draw(cmd_buffer, &info);
3943 }
3944
3945 void radv_CmdDrawIndexedIndirectCountKHR(
3946 VkCommandBuffer commandBuffer,
3947 VkBuffer _buffer,
3948 VkDeviceSize offset,
3949 VkBuffer _countBuffer,
3950 VkDeviceSize countBufferOffset,
3951 uint32_t maxDrawCount,
3952 uint32_t stride)
3953 {
3954 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3955 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3956 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3957 struct radv_draw_info info = {};
3958
3959 info.indexed = true;
3960 info.count = maxDrawCount;
3961 info.indirect = buffer;
3962 info.indirect_offset = offset;
3963 info.count_buffer = count_buffer;
3964 info.count_buffer_offset = countBufferOffset;
3965 info.stride = stride;
3966
3967 radv_draw(cmd_buffer, &info);
3968 }
3969
3970 struct radv_dispatch_info {
3971 /**
3972 * Determine the layout of the grid (in block units) to be used.
3973 */
3974 uint32_t blocks[3];
3975
3976 /**
3977 * A starting offset for the grid. If unaligned is set, the offset
3978 * must still be aligned.
3979 */
3980 uint32_t offsets[3];
3981 /**
3982 * Whether it's an unaligned compute dispatch.
3983 */
3984 bool unaligned;
3985
3986 /**
3987 * Indirect compute parameters resource.
3988 */
3989 struct radv_buffer *indirect;
3990 uint64_t indirect_offset;
3991 };
3992
3993 static void
3994 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3995 const struct radv_dispatch_info *info)
3996 {
3997 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3998 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3999 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4000 struct radeon_winsys *ws = cmd_buffer->device->ws;
4001 bool predicating = cmd_buffer->state.predicating;
4002 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4003 struct radv_userdata_info *loc;
4004
4005 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4006 AC_UD_CS_GRID_SIZE);
4007
4008 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4009
4010 if (info->indirect) {
4011 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4012
4013 va += info->indirect->offset + info->indirect_offset;
4014
4015 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4016
4017 if (loc->sgpr_idx != -1) {
4018 for (unsigned i = 0; i < 3; ++i) {
4019 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4020 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4021 COPY_DATA_DST_SEL(COPY_DATA_REG));
4022 radeon_emit(cs, (va + 4 * i));
4023 radeon_emit(cs, (va + 4 * i) >> 32);
4024 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4025 + loc->sgpr_idx * 4) >> 2) + i);
4026 radeon_emit(cs, 0);
4027 }
4028 }
4029
4030 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4031 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4032 PKT3_SHADER_TYPE_S(1));
4033 radeon_emit(cs, va);
4034 radeon_emit(cs, va >> 32);
4035 radeon_emit(cs, dispatch_initiator);
4036 } else {
4037 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4038 PKT3_SHADER_TYPE_S(1));
4039 radeon_emit(cs, 1);
4040 radeon_emit(cs, va);
4041 radeon_emit(cs, va >> 32);
4042
4043 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4044 PKT3_SHADER_TYPE_S(1));
4045 radeon_emit(cs, 0);
4046 radeon_emit(cs, dispatch_initiator);
4047 }
4048 } else {
4049 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4050 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4051
4052 if (info->unaligned) {
4053 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4054 unsigned remainder[3];
4055
4056 /* If aligned, these should be an entire block size,
4057 * not 0.
4058 */
4059 remainder[0] = blocks[0] + cs_block_size[0] -
4060 align_u32_npot(blocks[0], cs_block_size[0]);
4061 remainder[1] = blocks[1] + cs_block_size[1] -
4062 align_u32_npot(blocks[1], cs_block_size[1]);
4063 remainder[2] = blocks[2] + cs_block_size[2] -
4064 align_u32_npot(blocks[2], cs_block_size[2]);
4065
4066 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4067 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4068 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4069
4070 for(unsigned i = 0; i < 3; ++i) {
4071 assert(offsets[i] % cs_block_size[i] == 0);
4072 offsets[i] /= cs_block_size[i];
4073 }
4074
4075 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4076 radeon_emit(cs,
4077 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4078 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4079 radeon_emit(cs,
4080 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4081 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4082 radeon_emit(cs,
4083 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4084 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4085
4086 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4087 }
4088
4089 if (loc->sgpr_idx != -1) {
4090 assert(!loc->indirect);
4091 assert(loc->num_sgprs == 3);
4092
4093 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4094 loc->sgpr_idx * 4, 3);
4095 radeon_emit(cs, blocks[0]);
4096 radeon_emit(cs, blocks[1]);
4097 radeon_emit(cs, blocks[2]);
4098 }
4099
4100 if (offsets[0] || offsets[1] || offsets[2]) {
4101 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4102 radeon_emit(cs, offsets[0]);
4103 radeon_emit(cs, offsets[1]);
4104 radeon_emit(cs, offsets[2]);
4105
4106 /* The blocks in the packet are not counts but end values. */
4107 for (unsigned i = 0; i < 3; ++i)
4108 blocks[i] += offsets[i];
4109 } else {
4110 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4111 }
4112
4113 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4114 PKT3_SHADER_TYPE_S(1));
4115 radeon_emit(cs, blocks[0]);
4116 radeon_emit(cs, blocks[1]);
4117 radeon_emit(cs, blocks[2]);
4118 radeon_emit(cs, dispatch_initiator);
4119 }
4120
4121 assert(cmd_buffer->cs->cdw <= cdw_max);
4122 }
4123
4124 static void
4125 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4126 {
4127 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4128 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4129 }
4130
4131 static void
4132 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4133 const struct radv_dispatch_info *info)
4134 {
4135 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4136 bool has_prefetch =
4137 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4138 bool pipeline_is_dirty = pipeline &&
4139 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4140
4141 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4142 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4143 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4144 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4145 /* If we have to wait for idle, set all states first, so that
4146 * all SET packets are processed in parallel with previous draw
4147 * calls. Then upload descriptors, set shader pointers, and
4148 * dispatch, and prefetch at the end. This ensures that the
4149 * time the CUs are idle is very short. (there are only SET_SH
4150 * packets between the wait and the draw)
4151 */
4152 radv_emit_compute_pipeline(cmd_buffer);
4153 si_emit_cache_flush(cmd_buffer);
4154 /* <-- CUs are idle here --> */
4155
4156 radv_upload_compute_shader_descriptors(cmd_buffer);
4157
4158 radv_emit_dispatch_packets(cmd_buffer, info);
4159 /* <-- CUs are busy here --> */
4160
4161 /* Start prefetches after the dispatch has been started. Both
4162 * will run in parallel, but starting the dispatch first is
4163 * more important.
4164 */
4165 if (has_prefetch && pipeline_is_dirty) {
4166 radv_emit_shader_prefetch(cmd_buffer,
4167 pipeline->shaders[MESA_SHADER_COMPUTE]);
4168 }
4169 } else {
4170 /* If we don't wait for idle, start prefetches first, then set
4171 * states, and dispatch at the end.
4172 */
4173 si_emit_cache_flush(cmd_buffer);
4174
4175 if (has_prefetch && pipeline_is_dirty) {
4176 radv_emit_shader_prefetch(cmd_buffer,
4177 pipeline->shaders[MESA_SHADER_COMPUTE]);
4178 }
4179
4180 radv_upload_compute_shader_descriptors(cmd_buffer);
4181
4182 radv_emit_compute_pipeline(cmd_buffer);
4183 radv_emit_dispatch_packets(cmd_buffer, info);
4184 }
4185
4186 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4187 }
4188
4189 void radv_CmdDispatchBase(
4190 VkCommandBuffer commandBuffer,
4191 uint32_t base_x,
4192 uint32_t base_y,
4193 uint32_t base_z,
4194 uint32_t x,
4195 uint32_t y,
4196 uint32_t z)
4197 {
4198 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4199 struct radv_dispatch_info info = {};
4200
4201 info.blocks[0] = x;
4202 info.blocks[1] = y;
4203 info.blocks[2] = z;
4204
4205 info.offsets[0] = base_x;
4206 info.offsets[1] = base_y;
4207 info.offsets[2] = base_z;
4208 radv_dispatch(cmd_buffer, &info);
4209 }
4210
4211 void radv_CmdDispatch(
4212 VkCommandBuffer commandBuffer,
4213 uint32_t x,
4214 uint32_t y,
4215 uint32_t z)
4216 {
4217 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4218 }
4219
4220 void radv_CmdDispatchIndirect(
4221 VkCommandBuffer commandBuffer,
4222 VkBuffer _buffer,
4223 VkDeviceSize offset)
4224 {
4225 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4226 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4227 struct radv_dispatch_info info = {};
4228
4229 info.indirect = buffer;
4230 info.indirect_offset = offset;
4231
4232 radv_dispatch(cmd_buffer, &info);
4233 }
4234
4235 void radv_unaligned_dispatch(
4236 struct radv_cmd_buffer *cmd_buffer,
4237 uint32_t x,
4238 uint32_t y,
4239 uint32_t z)
4240 {
4241 struct radv_dispatch_info info = {};
4242
4243 info.blocks[0] = x;
4244 info.blocks[1] = y;
4245 info.blocks[2] = z;
4246 info.unaligned = 1;
4247
4248 radv_dispatch(cmd_buffer, &info);
4249 }
4250
4251 void radv_CmdEndRenderPass(
4252 VkCommandBuffer commandBuffer)
4253 {
4254 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4255
4256 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4257
4258 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4259
4260 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4261 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4262 radv_handle_subpass_image_transition(cmd_buffer,
4263 (struct radv_subpass_attachment){i, layout});
4264 }
4265
4266 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4267
4268 cmd_buffer->state.pass = NULL;
4269 cmd_buffer->state.subpass = NULL;
4270 cmd_buffer->state.attachments = NULL;
4271 cmd_buffer->state.framebuffer = NULL;
4272 }
4273
4274 void radv_CmdEndRenderPass2KHR(
4275 VkCommandBuffer commandBuffer,
4276 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4277 {
4278 radv_CmdEndRenderPass(commandBuffer);
4279 }
4280
4281 /*
4282 * For HTILE we have the following interesting clear words:
4283 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4284 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4285 * 0xfffffff0: Clear depth to 1.0
4286 * 0x00000000: Clear depth to 0.0
4287 */
4288 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4289 struct radv_image *image,
4290 const VkImageSubresourceRange *range,
4291 uint32_t clear_word)
4292 {
4293 assert(range->baseMipLevel == 0);
4294 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4295 unsigned layer_count = radv_get_layerCount(image, range);
4296 uint64_t size = image->surface.htile_slice_size * layer_count;
4297 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4298 uint64_t offset = image->offset + image->htile_offset +
4299 image->surface.htile_slice_size * range->baseArrayLayer;
4300 struct radv_cmd_state *state = &cmd_buffer->state;
4301 VkClearDepthStencilValue value = {};
4302
4303 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4304 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4305
4306 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4307 size, clear_word);
4308
4309 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4310
4311 if (vk_format_is_stencil(image->vk_format))
4312 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4313
4314 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4315
4316 if (radv_image_is_tc_compat_htile(image)) {
4317 /* Initialize the TC-compat metada value to 0 because by
4318 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4319 * need have to conditionally update its value when performing
4320 * a fast depth clear.
4321 */
4322 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4323 }
4324 }
4325
4326 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4327 struct radv_image *image,
4328 VkImageLayout src_layout,
4329 VkImageLayout dst_layout,
4330 unsigned src_queue_mask,
4331 unsigned dst_queue_mask,
4332 const VkImageSubresourceRange *range)
4333 {
4334 if (!radv_image_has_htile(image))
4335 return;
4336
4337 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4338 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4339 /* TODO: merge with the clear if applicable */
4340 radv_initialize_htile(cmd_buffer, image, range, 0);
4341 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4342 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4343 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4344 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4345 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4346 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4347 VkImageSubresourceRange local_range = *range;
4348 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4349 local_range.baseMipLevel = 0;
4350 local_range.levelCount = 1;
4351
4352 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4353 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4354
4355 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4356
4357 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4358 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4359 }
4360 }
4361
4362 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4363 struct radv_image *image, uint32_t value)
4364 {
4365 struct radv_cmd_state *state = &cmd_buffer->state;
4366
4367 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4368 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4369
4370 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4371
4372 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4373 }
4374
4375 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4376 struct radv_image *image)
4377 {
4378 struct radv_cmd_state *state = &cmd_buffer->state;
4379 static const uint32_t fmask_clear_values[4] = {
4380 0x00000000,
4381 0x02020202,
4382 0xE4E4E4E4,
4383 0x76543210
4384 };
4385 uint32_t log2_samples = util_logbase2(image->info.samples);
4386 uint32_t value = fmask_clear_values[log2_samples];
4387
4388 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4389 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4390
4391 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4392
4393 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4394 }
4395
4396 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4397 struct radv_image *image, uint32_t value)
4398 {
4399 struct radv_cmd_state *state = &cmd_buffer->state;
4400
4401 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4402 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4403
4404 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4405
4406 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4407 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4408 }
4409
4410 /**
4411 * Initialize DCC/FMASK/CMASK metadata for a color image.
4412 */
4413 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4414 struct radv_image *image,
4415 VkImageLayout src_layout,
4416 VkImageLayout dst_layout,
4417 unsigned src_queue_mask,
4418 unsigned dst_queue_mask)
4419 {
4420 if (radv_image_has_cmask(image)) {
4421 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4422
4423 /* TODO: clarify this. */
4424 if (radv_image_has_fmask(image)) {
4425 value = 0xccccccccu;
4426 }
4427
4428 radv_initialise_cmask(cmd_buffer, image, value);
4429 }
4430
4431 if (radv_image_has_fmask(image)) {
4432 radv_initialize_fmask(cmd_buffer, image);
4433 }
4434
4435 if (radv_image_has_dcc(image)) {
4436 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4437 bool need_decompress_pass = false;
4438
4439 if (radv_layout_dcc_compressed(image, dst_layout,
4440 dst_queue_mask)) {
4441 value = 0x20202020u;
4442 need_decompress_pass = true;
4443 }
4444
4445 radv_initialize_dcc(cmd_buffer, image, value);
4446
4447 radv_update_fce_metadata(cmd_buffer, image,
4448 need_decompress_pass);
4449 }
4450
4451 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4452 uint32_t color_values[2] = {};
4453 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4454 }
4455 }
4456
4457 /**
4458 * Handle color image transitions for DCC/FMASK/CMASK.
4459 */
4460 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4461 struct radv_image *image,
4462 VkImageLayout src_layout,
4463 VkImageLayout dst_layout,
4464 unsigned src_queue_mask,
4465 unsigned dst_queue_mask,
4466 const VkImageSubresourceRange *range)
4467 {
4468 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4469 radv_init_color_image_metadata(cmd_buffer, image,
4470 src_layout, dst_layout,
4471 src_queue_mask, dst_queue_mask);
4472 return;
4473 }
4474
4475 if (radv_image_has_dcc(image)) {
4476 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4477 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4478 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4479 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4480 radv_decompress_dcc(cmd_buffer, image, range);
4481 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4482 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4483 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4484 }
4485 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4486 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4487 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4488 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4489 }
4490
4491 if (radv_image_has_fmask(image)) {
4492 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
4493 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
4494 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
4495 }
4496 }
4497 }
4498 }
4499
4500 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4501 struct radv_image *image,
4502 VkImageLayout src_layout,
4503 VkImageLayout dst_layout,
4504 uint32_t src_family,
4505 uint32_t dst_family,
4506 const VkImageSubresourceRange *range)
4507 {
4508 if (image->exclusive && src_family != dst_family) {
4509 /* This is an acquire or a release operation and there will be
4510 * a corresponding release/acquire. Do the transition in the
4511 * most flexible queue. */
4512
4513 assert(src_family == cmd_buffer->queue_family_index ||
4514 dst_family == cmd_buffer->queue_family_index);
4515
4516 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4517 return;
4518
4519 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4520 (src_family == RADV_QUEUE_GENERAL ||
4521 dst_family == RADV_QUEUE_GENERAL))
4522 return;
4523 }
4524
4525 unsigned src_queue_mask =
4526 radv_image_queue_family_mask(image, src_family,
4527 cmd_buffer->queue_family_index);
4528 unsigned dst_queue_mask =
4529 radv_image_queue_family_mask(image, dst_family,
4530 cmd_buffer->queue_family_index);
4531
4532 if (vk_format_is_depth(image->vk_format)) {
4533 radv_handle_depth_image_transition(cmd_buffer, image,
4534 src_layout, dst_layout,
4535 src_queue_mask, dst_queue_mask,
4536 range);
4537 } else {
4538 radv_handle_color_image_transition(cmd_buffer, image,
4539 src_layout, dst_layout,
4540 src_queue_mask, dst_queue_mask,
4541 range);
4542 }
4543 }
4544
4545 struct radv_barrier_info {
4546 uint32_t eventCount;
4547 const VkEvent *pEvents;
4548 VkPipelineStageFlags srcStageMask;
4549 };
4550
4551 static void
4552 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4553 uint32_t memoryBarrierCount,
4554 const VkMemoryBarrier *pMemoryBarriers,
4555 uint32_t bufferMemoryBarrierCount,
4556 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4557 uint32_t imageMemoryBarrierCount,
4558 const VkImageMemoryBarrier *pImageMemoryBarriers,
4559 const struct radv_barrier_info *info)
4560 {
4561 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4562 enum radv_cmd_flush_bits src_flush_bits = 0;
4563 enum radv_cmd_flush_bits dst_flush_bits = 0;
4564
4565 for (unsigned i = 0; i < info->eventCount; ++i) {
4566 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4567 uint64_t va = radv_buffer_get_va(event->bo);
4568
4569 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4570
4571 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4572
4573 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4574 assert(cmd_buffer->cs->cdw <= cdw_max);
4575 }
4576
4577 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4578 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4579 NULL);
4580 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4581 NULL);
4582 }
4583
4584 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4585 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4586 NULL);
4587 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4588 NULL);
4589 }
4590
4591 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4592 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4593
4594 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4595 image);
4596 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4597 image);
4598 }
4599
4600 radv_stage_flush(cmd_buffer, info->srcStageMask);
4601 cmd_buffer->state.flush_bits |= src_flush_bits;
4602
4603 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4604 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4605 radv_handle_image_transition(cmd_buffer, image,
4606 pImageMemoryBarriers[i].oldLayout,
4607 pImageMemoryBarriers[i].newLayout,
4608 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4609 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4610 &pImageMemoryBarriers[i].subresourceRange);
4611 }
4612
4613 /* Make sure CP DMA is idle because the driver might have performed a
4614 * DMA operation for copying or filling buffers/images.
4615 */
4616 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4617 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4618 si_cp_dma_wait_for_idle(cmd_buffer);
4619
4620 cmd_buffer->state.flush_bits |= dst_flush_bits;
4621 }
4622
4623 void radv_CmdPipelineBarrier(
4624 VkCommandBuffer commandBuffer,
4625 VkPipelineStageFlags srcStageMask,
4626 VkPipelineStageFlags destStageMask,
4627 VkBool32 byRegion,
4628 uint32_t memoryBarrierCount,
4629 const VkMemoryBarrier* pMemoryBarriers,
4630 uint32_t bufferMemoryBarrierCount,
4631 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4632 uint32_t imageMemoryBarrierCount,
4633 const VkImageMemoryBarrier* pImageMemoryBarriers)
4634 {
4635 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4636 struct radv_barrier_info info;
4637
4638 info.eventCount = 0;
4639 info.pEvents = NULL;
4640 info.srcStageMask = srcStageMask;
4641
4642 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4643 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4644 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4645 }
4646
4647
4648 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4649 struct radv_event *event,
4650 VkPipelineStageFlags stageMask,
4651 unsigned value)
4652 {
4653 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4654 uint64_t va = radv_buffer_get_va(event->bo);
4655
4656 si_emit_cache_flush(cmd_buffer);
4657
4658 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4659
4660 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4661
4662 /* Flags that only require a top-of-pipe event. */
4663 VkPipelineStageFlags top_of_pipe_flags =
4664 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4665
4666 /* Flags that only require a post-index-fetch event. */
4667 VkPipelineStageFlags post_index_fetch_flags =
4668 top_of_pipe_flags |
4669 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4670 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4671
4672 /* Make sure CP DMA is idle because the driver might have performed a
4673 * DMA operation for copying or filling buffers/images.
4674 */
4675 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4676 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4677 si_cp_dma_wait_for_idle(cmd_buffer);
4678
4679 /* TODO: Emit EOS events for syncing PS/CS stages. */
4680
4681 if (!(stageMask & ~top_of_pipe_flags)) {
4682 /* Just need to sync the PFP engine. */
4683 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4684 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4685 S_370_WR_CONFIRM(1) |
4686 S_370_ENGINE_SEL(V_370_PFP));
4687 radeon_emit(cs, va);
4688 radeon_emit(cs, va >> 32);
4689 radeon_emit(cs, value);
4690 } else if (!(stageMask & ~post_index_fetch_flags)) {
4691 /* Sync ME because PFP reads index and indirect buffers. */
4692 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4693 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4694 S_370_WR_CONFIRM(1) |
4695 S_370_ENGINE_SEL(V_370_ME));
4696 radeon_emit(cs, va);
4697 radeon_emit(cs, va >> 32);
4698 radeon_emit(cs, value);
4699 } else {
4700 /* Otherwise, sync all prior GPU work using an EOP event. */
4701 si_cs_emit_write_event_eop(cs,
4702 cmd_buffer->device->physical_device->rad_info.chip_class,
4703 radv_cmd_buffer_uses_mec(cmd_buffer),
4704 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4705 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4706 cmd_buffer->gfx9_eop_bug_va);
4707 }
4708
4709 assert(cmd_buffer->cs->cdw <= cdw_max);
4710 }
4711
4712 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4713 VkEvent _event,
4714 VkPipelineStageFlags stageMask)
4715 {
4716 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4717 RADV_FROM_HANDLE(radv_event, event, _event);
4718
4719 write_event(cmd_buffer, event, stageMask, 1);
4720 }
4721
4722 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4723 VkEvent _event,
4724 VkPipelineStageFlags stageMask)
4725 {
4726 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4727 RADV_FROM_HANDLE(radv_event, event, _event);
4728
4729 write_event(cmd_buffer, event, stageMask, 0);
4730 }
4731
4732 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4733 uint32_t eventCount,
4734 const VkEvent* pEvents,
4735 VkPipelineStageFlags srcStageMask,
4736 VkPipelineStageFlags dstStageMask,
4737 uint32_t memoryBarrierCount,
4738 const VkMemoryBarrier* pMemoryBarriers,
4739 uint32_t bufferMemoryBarrierCount,
4740 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4741 uint32_t imageMemoryBarrierCount,
4742 const VkImageMemoryBarrier* pImageMemoryBarriers)
4743 {
4744 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4745 struct radv_barrier_info info;
4746
4747 info.eventCount = eventCount;
4748 info.pEvents = pEvents;
4749 info.srcStageMask = 0;
4750
4751 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4752 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4753 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4754 }
4755
4756
4757 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4758 uint32_t deviceMask)
4759 {
4760 /* No-op */
4761 }
4762
4763 /* VK_EXT_conditional_rendering */
4764 void radv_CmdBeginConditionalRenderingEXT(
4765 VkCommandBuffer commandBuffer,
4766 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4767 {
4768 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4769 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4770 bool draw_visible = true;
4771 uint64_t va;
4772
4773 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4774
4775 /* By default, if the 32-bit value at offset in buffer memory is zero,
4776 * then the rendering commands are discarded, otherwise they are
4777 * executed as normal. If the inverted flag is set, all commands are
4778 * discarded if the value is non zero.
4779 */
4780 if (pConditionalRenderingBegin->flags &
4781 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4782 draw_visible = false;
4783 }
4784
4785 si_emit_cache_flush(cmd_buffer);
4786
4787 /* Enable predication for this command buffer. */
4788 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4789 cmd_buffer->state.predicating = true;
4790
4791 /* Store conditional rendering user info. */
4792 cmd_buffer->state.predication_type = draw_visible;
4793 cmd_buffer->state.predication_va = va;
4794 }
4795
4796 void radv_CmdEndConditionalRenderingEXT(
4797 VkCommandBuffer commandBuffer)
4798 {
4799 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4800
4801 /* Disable predication for this command buffer. */
4802 si_emit_set_predication_state(cmd_buffer, false, 0);
4803 cmd_buffer->state.predicating = false;
4804
4805 /* Reset conditional rendering user info. */
4806 cmd_buffer->state.predication_type = -1;
4807 cmd_buffer->state.predication_va = 0;
4808 }
4809
4810 /* VK_EXT_transform_feedback */
4811 void radv_CmdBindTransformFeedbackBuffersEXT(
4812 VkCommandBuffer commandBuffer,
4813 uint32_t firstBinding,
4814 uint32_t bindingCount,
4815 const VkBuffer* pBuffers,
4816 const VkDeviceSize* pOffsets,
4817 const VkDeviceSize* pSizes)
4818 {
4819 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4820 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4821 uint8_t enabled_mask = 0;
4822
4823 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4824 for (uint32_t i = 0; i < bindingCount; i++) {
4825 uint32_t idx = firstBinding + i;
4826
4827 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4828 sb[idx].offset = pOffsets[i];
4829 sb[idx].size = pSizes[i];
4830
4831 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4832 sb[idx].buffer->bo);
4833
4834 enabled_mask |= 1 << idx;
4835 }
4836
4837 cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4838
4839 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4840 }
4841
4842 static void
4843 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4844 {
4845 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4846 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4847
4848 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
4849 radeon_emit(cs,
4850 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
4851 S_028B94_RAST_STREAM(0) |
4852 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
4853 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
4854 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
4855 radeon_emit(cs, so->hw_enabled_mask &
4856 so->enabled_stream_buffers_mask);
4857
4858 cmd_buffer->state.context_roll_without_scissor_emitted = true;
4859 }
4860
4861 static void
4862 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
4863 {
4864 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4865 bool old_streamout_enabled = so->streamout_enabled;
4866 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
4867
4868 so->streamout_enabled = enable;
4869
4870 so->hw_enabled_mask = so->enabled_mask |
4871 (so->enabled_mask << 4) |
4872 (so->enabled_mask << 8) |
4873 (so->enabled_mask << 12);
4874
4875 if ((old_streamout_enabled != so->streamout_enabled) ||
4876 (old_hw_enabled_mask != so->hw_enabled_mask))
4877 radv_emit_streamout_enable(cmd_buffer);
4878 }
4879
4880 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
4881 {
4882 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4883 unsigned reg_strmout_cntl;
4884
4885 /* The register is at different places on different ASICs. */
4886 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
4887 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
4888 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
4889 } else {
4890 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
4891 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
4892 }
4893
4894 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4895 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
4896
4897 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
4898 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
4899 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
4900 radeon_emit(cs, 0);
4901 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4902 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4903 radeon_emit(cs, 4); /* poll interval */
4904 }
4905
4906 void radv_CmdBeginTransformFeedbackEXT(
4907 VkCommandBuffer commandBuffer,
4908 uint32_t firstCounterBuffer,
4909 uint32_t counterBufferCount,
4910 const VkBuffer* pCounterBuffers,
4911 const VkDeviceSize* pCounterBufferOffsets)
4912 {
4913 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4914 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4915 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4916 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4917 uint32_t i;
4918
4919 radv_flush_vgt_streamout(cmd_buffer);
4920
4921 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4922 for_each_bit(i, so->enabled_mask) {
4923 int32_t counter_buffer_idx = i - firstCounterBuffer;
4924 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
4925 counter_buffer_idx = -1;
4926
4927 /* SI binds streamout buffers as shader resources.
4928 * VGT only counts primitives and tells the shader through
4929 * SGPRs what to do.
4930 */
4931 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
4932 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
4933 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
4934
4935 cmd_buffer->state.context_roll_without_scissor_emitted = true;
4936
4937 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
4938 /* The array of counter buffers is optional. */
4939 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
4940 uint64_t va = radv_buffer_get_va(buffer->bo);
4941
4942 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
4943
4944 /* Append */
4945 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4946 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4947 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4948 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
4949 radeon_emit(cs, 0); /* unused */
4950 radeon_emit(cs, 0); /* unused */
4951 radeon_emit(cs, va); /* src address lo */
4952 radeon_emit(cs, va >> 32); /* src address hi */
4953
4954 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4955 } else {
4956 /* Start from the beginning. */
4957 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4958 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4959 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4960 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
4961 radeon_emit(cs, 0); /* unused */
4962 radeon_emit(cs, 0); /* unused */
4963 radeon_emit(cs, 0); /* unused */
4964 radeon_emit(cs, 0); /* unused */
4965 }
4966 }
4967
4968 radv_set_streamout_enable(cmd_buffer, true);
4969 }
4970
4971 void radv_CmdEndTransformFeedbackEXT(
4972 VkCommandBuffer commandBuffer,
4973 uint32_t firstCounterBuffer,
4974 uint32_t counterBufferCount,
4975 const VkBuffer* pCounterBuffers,
4976 const VkDeviceSize* pCounterBufferOffsets)
4977 {
4978 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4979 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4980 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4981 uint32_t i;
4982
4983 radv_flush_vgt_streamout(cmd_buffer);
4984
4985 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4986 for_each_bit(i, so->enabled_mask) {
4987 int32_t counter_buffer_idx = i - firstCounterBuffer;
4988 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
4989 counter_buffer_idx = -1;
4990
4991 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
4992 /* The array of counters buffer is optional. */
4993 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
4994 uint64_t va = radv_buffer_get_va(buffer->bo);
4995
4996 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
4997
4998 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4999 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5000 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5001 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5002 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5003 radeon_emit(cs, va); /* dst address lo */
5004 radeon_emit(cs, va >> 32); /* dst address hi */
5005 radeon_emit(cs, 0); /* unused */
5006 radeon_emit(cs, 0); /* unused */
5007
5008 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5009 }
5010
5011 /* Deactivate transform feedback by zeroing the buffer size.
5012 * The counters (primitives generated, primitives emitted) may
5013 * be enabled even if there is not buffer bound. This ensures
5014 * that the primitives-emitted query won't increment.
5015 */
5016 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5017
5018 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5019 }
5020
5021 radv_set_streamout_enable(cmd_buffer, false);
5022 }
5023
5024 void radv_CmdDrawIndirectByteCountEXT(
5025 VkCommandBuffer commandBuffer,
5026 uint32_t instanceCount,
5027 uint32_t firstInstance,
5028 VkBuffer _counterBuffer,
5029 VkDeviceSize counterBufferOffset,
5030 uint32_t counterOffset,
5031 uint32_t vertexStride)
5032 {
5033 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5034 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5035 struct radv_draw_info info = {};
5036
5037 info.instance_count = instanceCount;
5038 info.first_instance = firstInstance;
5039 info.strmout_buffer = counterBuffer;
5040 info.strmout_buffer_offset = counterBufferOffset;
5041 info.stride = vertexStride;
5042
5043 radv_draw(cmd_buffer, &info);
5044 }