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radv: use indirect buffer for initial gfx state.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 uint32_t src_family,
42 uint32_t dst_family,
43 VkImageSubresourceRange range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static bool
191 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
192 uint64_t min_needed)
193 {
194 uint64_t new_size;
195 struct radeon_winsys_bo *bo;
196 struct radv_cmd_buffer_upload *upload;
197 struct radv_device *device = cmd_buffer->device;
198
199 new_size = MAX2(min_needed, 16 * 1024);
200 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
201
202 bo = device->ws->buffer_create(device->ws,
203 new_size, 4096,
204 RADEON_DOMAIN_GTT,
205 RADEON_FLAG_CPU_ACCESS);
206
207 if (!bo) {
208 cmd_buffer->record_fail = true;
209 return false;
210 }
211
212 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
213 if (cmd_buffer->upload.upload_bo) {
214 upload = malloc(sizeof(*upload));
215
216 if (!upload) {
217 cmd_buffer->record_fail = true;
218 device->ws->buffer_destroy(bo);
219 return false;
220 }
221
222 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
223 list_add(&upload->list, &cmd_buffer->upload.list);
224 }
225
226 cmd_buffer->upload.upload_bo = bo;
227 cmd_buffer->upload.size = new_size;
228 cmd_buffer->upload.offset = 0;
229 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
230
231 if (!cmd_buffer->upload.map) {
232 cmd_buffer->record_fail = true;
233 return false;
234 }
235
236 return true;
237 }
238
239 bool
240 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
241 unsigned size,
242 unsigned alignment,
243 unsigned *out_offset,
244 void **ptr)
245 {
246 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
247 if (offset + size > cmd_buffer->upload.size) {
248 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
249 return false;
250 offset = 0;
251 }
252
253 *out_offset = offset;
254 *ptr = cmd_buffer->upload.map + offset;
255
256 cmd_buffer->upload.offset = offset + size;
257 return true;
258 }
259
260 bool
261 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
262 unsigned size, unsigned alignment,
263 const void *data, unsigned *out_offset)
264 {
265 uint8_t *ptr;
266
267 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
268 out_offset, (void **)&ptr))
269 return false;
270
271 if (ptr)
272 memcpy(ptr, data, size);
273
274 return true;
275 }
276
277 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
278 {
279 struct radv_device *device = cmd_buffer->device;
280 struct radeon_winsys_cs *cs = cmd_buffer->cs;
281 uint64_t va;
282
283 if (!device->trace_bo)
284 return;
285
286 va = device->ws->buffer_get_va(device->trace_bo);
287
288 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
289
290 ++cmd_buffer->state.trace_id;
291 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
292 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
293 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
294 S_370_WR_CONFIRM(1) |
295 S_370_ENGINE_SEL(V_370_ME));
296 radeon_emit(cs, va);
297 radeon_emit(cs, va >> 32);
298 radeon_emit(cs, cmd_buffer->state.trace_id);
299 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
300 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
301 }
302
303 static void
304 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
305 struct radv_pipeline *pipeline)
306 {
307 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
308 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
309 8);
310 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
311 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
312 }
313
314 static void
315 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
316 struct radv_pipeline *pipeline)
317 {
318 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
319 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
320 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
321
322 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
323 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
324 }
325
326 /* 12.4 fixed-point */
327 static unsigned radv_pack_float_12p4(float x)
328 {
329 return x <= 0 ? 0 :
330 x >= 4096 ? 0xffff : x * 16;
331 }
332
333 static uint32_t
334 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs)
335 {
336 switch (stage) {
337 case MESA_SHADER_FRAGMENT:
338 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
339 case MESA_SHADER_VERTEX:
340 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
341 case MESA_SHADER_GEOMETRY:
342 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
343 case MESA_SHADER_COMPUTE:
344 return R_00B900_COMPUTE_USER_DATA_0;
345 default:
346 unreachable("unknown shader");
347 }
348 }
349
350 static struct ac_userdata_info *
351 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
352 gl_shader_stage stage,
353 int idx)
354 {
355 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
356 }
357
358 static void
359 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
360 struct radv_pipeline *pipeline,
361 gl_shader_stage stage,
362 int idx, uint64_t va)
363 {
364 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
365 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline));
366 if (loc->sgpr_idx == -1)
367 return;
368 assert(loc->num_sgprs == 2);
369 assert(!loc->indirect);
370 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
371 radeon_emit(cmd_buffer->cs, va);
372 radeon_emit(cmd_buffer->cs, va >> 32);
373 }
374
375 static void
376 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
377 struct radv_pipeline *pipeline)
378 {
379 int num_samples = pipeline->graphics.ms.num_samples;
380 struct radv_multisample_state *ms = &pipeline->graphics.ms;
381 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
382
383 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
384 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
385 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
386
387 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
388 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
389
390 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
391 return;
392
393 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
394 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
395 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
396
397 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
398
399 uint32_t samples_offset;
400 void *samples_ptr;
401 void *src;
402 radv_cmd_buffer_upload_alloc(cmd_buffer, num_samples * 4 * 2, 256, &samples_offset,
403 &samples_ptr);
404 switch (num_samples) {
405 case 1:
406 src = cmd_buffer->device->sample_locations_1x;
407 break;
408 case 2:
409 src = cmd_buffer->device->sample_locations_2x;
410 break;
411 case 4:
412 src = cmd_buffer->device->sample_locations_4x;
413 break;
414 case 8:
415 src = cmd_buffer->device->sample_locations_8x;
416 break;
417 case 16:
418 src = cmd_buffer->device->sample_locations_16x;
419 break;
420 default:
421 unreachable("unknown number of samples");
422 }
423 memcpy(samples_ptr, src, num_samples * 4 * 2);
424
425 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
426 va += samples_offset;
427
428 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
429 AC_UD_PS_SAMPLE_POS, va);
430 }
431
432 static void
433 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
434 struct radv_pipeline *pipeline)
435 {
436 struct radv_raster_state *raster = &pipeline->graphics.raster;
437
438 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
439 raster->pa_cl_clip_cntl);
440
441 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
442 raster->spi_interp_control);
443
444 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
445 unsigned tmp = (unsigned)(1.0 * 8.0);
446 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
447 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
448 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
449
450 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
451 raster->pa_su_vtx_cntl);
452
453 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
454 raster->pa_su_sc_mode_cntl);
455 }
456
457 static void
458 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
459 struct radv_pipeline *pipeline,
460 struct radv_shader_variant *shader)
461 {
462 struct radeon_winsys *ws = cmd_buffer->device->ws;
463 uint64_t va = ws->buffer_get_va(shader->bo);
464 unsigned export_count;
465
466 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
467
468 export_count = MAX2(1, shader->info.vs.param_exports);
469 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
470 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
471
472 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
473 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
474 S_02870C_POS1_EXPORT_FORMAT(shader->info.vs.pos_exports > 1 ?
475 V_02870C_SPI_SHADER_4COMP :
476 V_02870C_SPI_SHADER_NONE) |
477 S_02870C_POS2_EXPORT_FORMAT(shader->info.vs.pos_exports > 2 ?
478 V_02870C_SPI_SHADER_4COMP :
479 V_02870C_SPI_SHADER_NONE) |
480 S_02870C_POS3_EXPORT_FORMAT(shader->info.vs.pos_exports > 3 ?
481 V_02870C_SPI_SHADER_4COMP :
482 V_02870C_SPI_SHADER_NONE));
483
484
485 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
486 radeon_emit(cmd_buffer->cs, va >> 8);
487 radeon_emit(cmd_buffer->cs, va >> 40);
488 radeon_emit(cmd_buffer->cs, shader->rsrc1);
489 radeon_emit(cmd_buffer->cs, shader->rsrc2);
490
491 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
492 S_028818_VTX_W0_FMT(1) |
493 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
494 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
495 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
496
497 unsigned clip_dist_mask, cull_dist_mask, total_mask;
498 clip_dist_mask = shader->info.vs.clip_dist_mask;
499 cull_dist_mask = shader->info.vs.cull_dist_mask;
500 total_mask = clip_dist_mask | cull_dist_mask;
501
502 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
503 S_02881C_USE_VTX_POINT_SIZE(shader->info.vs.writes_pointsize) |
504 S_02881C_USE_VTX_RENDER_TARGET_INDX(shader->info.vs.writes_layer) |
505 S_02881C_USE_VTX_VIEWPORT_INDX(shader->info.vs.writes_viewport_index) |
506 S_02881C_VS_OUT_MISC_VEC_ENA(shader->info.vs.writes_pointsize ||
507 shader->info.vs.writes_layer ||
508 shader->info.vs.writes_viewport_index) |
509 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
510 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
511 pipeline->graphics.raster.pa_cl_vs_out_cntl |
512 cull_dist_mask << 8 |
513 clip_dist_mask);
514
515 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
516 S_028AB4_REUSE_OFF(shader->info.vs.writes_viewport_index));
517 }
518
519 static void
520 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
521 struct radv_shader_variant *shader)
522 {
523 struct radeon_winsys *ws = cmd_buffer->device->ws;
524 uint64_t va = ws->buffer_get_va(shader->bo);
525
526 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
527
528 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
529 shader->info.vs.esgs_itemsize / 4);
530 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
531 radeon_emit(cmd_buffer->cs, va >> 8);
532 radeon_emit(cmd_buffer->cs, va >> 40);
533 radeon_emit(cmd_buffer->cs, shader->rsrc1);
534 radeon_emit(cmd_buffer->cs, shader->rsrc2);
535 }
536
537 static void
538 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
539 struct radv_pipeline *pipeline)
540 {
541 struct radv_shader_variant *vs;
542
543 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
544
545 vs = pipeline->shaders[MESA_SHADER_VERTEX];
546
547 if (vs->info.vs.as_es)
548 radv_emit_hw_es(cmd_buffer, vs);
549 else
550 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
551
552 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
553 }
554
555 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
556 {
557 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
558 unsigned cut_mode;
559
560 if (gs_max_vert_out <= 128) {
561 cut_mode = V_028A40_GS_CUT_128;
562 } else if (gs_max_vert_out <= 256) {
563 cut_mode = V_028A40_GS_CUT_256;
564 } else if (gs_max_vert_out <= 512) {
565 cut_mode = V_028A40_GS_CUT_512;
566 } else {
567 assert(gs_max_vert_out <= 1024);
568 cut_mode = V_028A40_GS_CUT_1024;
569 }
570
571 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
572 S_028A40_CUT_MODE(cut_mode)|
573 S_028A40_ES_WRITE_OPTIMIZE(1) |
574 S_028A40_GS_WRITE_OPTIMIZE(1);
575 }
576
577 static void
578 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
579 struct radv_pipeline *pipeline)
580 {
581 struct radeon_winsys *ws = cmd_buffer->device->ws;
582 struct radv_shader_variant *gs;
583 uint64_t va;
584
585 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
586 if (!gs) {
587 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, 0);
588 return;
589 }
590
591 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
592
593 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
594
595 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
596 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
597 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
598 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
599
600 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
601
602 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
603
604 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
605 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
606 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
607 radeon_emit(cmd_buffer->cs, 0);
608 radeon_emit(cmd_buffer->cs, 0);
609 radeon_emit(cmd_buffer->cs, 0);
610
611 uint32_t gs_num_invocations = gs->info.gs.invocations;
612 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
613 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
614 S_028B90_ENABLE(gs_num_invocations > 0));
615
616 va = ws->buffer_get_va(gs->bo);
617 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
618 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
619 radeon_emit(cmd_buffer->cs, va >> 8);
620 radeon_emit(cmd_buffer->cs, va >> 40);
621 radeon_emit(cmd_buffer->cs, gs->rsrc1);
622 radeon_emit(cmd_buffer->cs, gs->rsrc2);
623
624 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
625
626 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
627 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
628 if (loc->sgpr_idx != -1) {
629 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
630 uint32_t num_entries = 64;
631 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
632
633 if (is_vi)
634 num_entries *= stride;
635
636 stride = S_008F04_STRIDE(stride);
637 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
638 radeon_emit(cmd_buffer->cs, stride);
639 radeon_emit(cmd_buffer->cs, num_entries);
640 }
641 }
642
643 static void
644 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
645 struct radv_pipeline *pipeline)
646 {
647 struct radeon_winsys *ws = cmd_buffer->device->ws;
648 struct radv_shader_variant *ps, *vs;
649 uint64_t va;
650 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
651 struct radv_blend_state *blend = &pipeline->graphics.blend;
652 unsigned ps_offset = 0;
653 unsigned z_order;
654 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
655
656 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
657 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : pipeline->shaders[MESA_SHADER_VERTEX];
658 va = ws->buffer_get_va(ps->bo);
659 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
660
661 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
662 radeon_emit(cmd_buffer->cs, va >> 8);
663 radeon_emit(cmd_buffer->cs, va >> 40);
664 radeon_emit(cmd_buffer->cs, ps->rsrc1);
665 radeon_emit(cmd_buffer->cs, ps->rsrc2);
666
667 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
668 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
669 else
670 z_order = V_02880C_LATE_Z;
671
672
673 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
674 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
675 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
676 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
677 S_02880C_Z_ORDER(z_order) |
678 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
679 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
680 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory));
681
682 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
683 ps->config.spi_ps_input_ena);
684
685 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
686 ps->config.spi_ps_input_addr);
687
688 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(0);
689 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
690 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
691
692 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
693
694 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
695 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
696 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
697 V_028710_SPI_SHADER_ZERO);
698
699 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
700
701 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
702 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
703
704 if (ps->info.fs.has_pcoord) {
705 unsigned val;
706 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
707 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
708 ps_offset++;
709 }
710
711 if (ps->info.fs.prim_id_input && (vs->info.vs.prim_id_output != 0xffffffff)) {
712 unsigned vs_offset, flat_shade;
713 unsigned val;
714 vs_offset = vs->info.vs.prim_id_output;
715 flat_shade = true;
716 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
717 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
718 ++ps_offset;
719 }
720
721 if (ps->info.fs.layer_input && (vs->info.vs.layer_output != 0xffffffff)) {
722 unsigned vs_offset, flat_shade;
723 unsigned val;
724 vs_offset = vs->info.vs.layer_output;
725 flat_shade = true;
726 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
727 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
728 ++ps_offset;
729 }
730
731 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
732 unsigned vs_offset, flat_shade;
733 unsigned val;
734
735 if (!(ps->info.fs.input_mask & (1u << i)))
736 continue;
737
738
739 if (!(vs->info.vs.export_mask & (1u << i))) {
740 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset,
741 S_028644_OFFSET(0x20));
742 ++ps_offset;
743 continue;
744 }
745
746 vs_offset = util_bitcount(vs->info.vs.export_mask & ((1u << i) - 1));
747 if (vs->info.vs.prim_id_output != 0xffffffff) {
748 if (vs_offset >= vs->info.vs.prim_id_output)
749 vs_offset++;
750 }
751 if (vs->info.vs.layer_output != 0xffffffff) {
752 if (vs_offset >= vs->info.vs.layer_output)
753 vs_offset++;
754 }
755 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
756
757 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
758 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
759 ++ps_offset;
760 }
761 }
762
763 static void
764 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
765 struct radv_pipeline *pipeline)
766 {
767 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
768 return;
769
770 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
771 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
772 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
773 radv_update_multisample_state(cmd_buffer, pipeline);
774 radv_emit_vertex_shader(cmd_buffer, pipeline);
775 radv_emit_geometry_shader(cmd_buffer, pipeline);
776 radv_emit_fragment_shader(cmd_buffer, pipeline);
777
778 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
779 pipeline->graphics.prim_restart_enable);
780
781 cmd_buffer->scratch_size_needed =
782 MAX2(cmd_buffer->scratch_size_needed,
783 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
784
785 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
786 S_0286E8_WAVES(pipeline->max_waves) |
787 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
788 cmd_buffer->state.emitted_pipeline = pipeline;
789 }
790
791 static void
792 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
793 {
794 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
795 cmd_buffer->state.dynamic.viewport.viewports);
796 }
797
798 static void
799 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
800 {
801 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
802 si_write_scissors(cmd_buffer->cs, 0, count,
803 cmd_buffer->state.dynamic.scissor.scissors);
804 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
805 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
806 }
807
808 static void
809 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
810 int index,
811 struct radv_color_buffer_info *cb)
812 {
813 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
814 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
815 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
816 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
817 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
818 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
819 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
820 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
821 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
822 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
823 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
824 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
825 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
826
827 if (is_vi) { /* DCC BASE */
828 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
829 }
830 }
831
832 static void
833 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
834 struct radv_ds_buffer_info *ds,
835 struct radv_image *image,
836 VkImageLayout layout)
837 {
838 uint32_t db_z_info = ds->db_z_info;
839
840 if (!radv_layout_has_htile(image, layout))
841 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
842
843 if (!radv_layout_can_expclear(image, layout))
844 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
845
846 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
847 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
848
849 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
850 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
851 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
852 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
853 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
854 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
855 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
856 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
857 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
858 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
859
860 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
861 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
862 ds->pa_su_poly_offset_db_fmt_cntl);
863 }
864
865 /*
866 * To hw resolve multisample images both src and dst need to have the same
867 * micro tiling mode. However we don't always know in advance when creating
868 * the images. This function gets called if we have a resolve attachment,
869 * and tests if the attachment image has the same tiling mode, then it
870 * checks if the generated framebuffer data has the same tiling mode, and
871 * updates it if not.
872 */
873 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
874 struct radv_attachment_info *att,
875 uint32_t micro_tile_mode)
876 {
877 struct radv_image *image = att->attachment->image;
878 uint32_t tile_mode_index;
879 if (image->surface.nsamples <= 1)
880 return;
881
882 if (image->surface.micro_tile_mode != micro_tile_mode) {
883 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
884 }
885
886 if (att->cb.micro_tile_mode != micro_tile_mode) {
887 tile_mode_index = image->surface.tiling_index[0];
888
889 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
890 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
891 att->cb.micro_tile_mode = micro_tile_mode;
892 }
893 }
894
895 void
896 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
897 struct radv_image *image,
898 VkClearDepthStencilValue ds_clear_value,
899 VkImageAspectFlags aspects)
900 {
901 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
902 va += image->offset + image->clear_value_offset;
903 unsigned reg_offset = 0, reg_count = 0;
904
905 if (!image->htile.size || !aspects)
906 return;
907
908 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
909 ++reg_count;
910 } else {
911 ++reg_offset;
912 va += 4;
913 }
914 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
915 ++reg_count;
916
917 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
918
919 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
920 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
921 S_370_WR_CONFIRM(1) |
922 S_370_ENGINE_SEL(V_370_PFP));
923 radeon_emit(cmd_buffer->cs, va);
924 radeon_emit(cmd_buffer->cs, va >> 32);
925 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
926 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
927 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
928 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
929
930 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
931 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
932 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
933 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
934 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
935 }
936
937 static void
938 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
939 struct radv_image *image)
940 {
941 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
942 va += image->offset + image->clear_value_offset;
943
944 if (!image->htile.size)
945 return;
946
947 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
948
949 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
950 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
951 COPY_DATA_DST_SEL(COPY_DATA_REG) |
952 COPY_DATA_COUNT_SEL);
953 radeon_emit(cmd_buffer->cs, va);
954 radeon_emit(cmd_buffer->cs, va >> 32);
955 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
956 radeon_emit(cmd_buffer->cs, 0);
957
958 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
959 radeon_emit(cmd_buffer->cs, 0);
960 }
961
962 void
963 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
964 struct radv_image *image,
965 int idx,
966 uint32_t color_values[2])
967 {
968 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
969 va += image->offset + image->clear_value_offset;
970
971 if (!image->cmask.size && !image->surface.dcc_size)
972 return;
973
974 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
975
976 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
977 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
978 S_370_WR_CONFIRM(1) |
979 S_370_ENGINE_SEL(V_370_PFP));
980 radeon_emit(cmd_buffer->cs, va);
981 radeon_emit(cmd_buffer->cs, va >> 32);
982 radeon_emit(cmd_buffer->cs, color_values[0]);
983 radeon_emit(cmd_buffer->cs, color_values[1]);
984
985 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
986 radeon_emit(cmd_buffer->cs, color_values[0]);
987 radeon_emit(cmd_buffer->cs, color_values[1]);
988 }
989
990 static void
991 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
992 struct radv_image *image,
993 int idx)
994 {
995 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
996 va += image->offset + image->clear_value_offset;
997
998 if (!image->cmask.size && !image->surface.dcc_size)
999 return;
1000
1001 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1002 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1003
1004 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1005 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1006 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1007 COPY_DATA_COUNT_SEL);
1008 radeon_emit(cmd_buffer->cs, va);
1009 radeon_emit(cmd_buffer->cs, va >> 32);
1010 radeon_emit(cmd_buffer->cs, reg >> 2);
1011 radeon_emit(cmd_buffer->cs, 0);
1012
1013 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1014 radeon_emit(cmd_buffer->cs, 0);
1015 }
1016
1017 void
1018 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1019 {
1020 int i;
1021 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1022 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1023 int dst_resolve_micro_tile_mode = -1;
1024
1025 if (subpass->has_resolve) {
1026 uint32_t a = subpass->resolve_attachments[0].attachment;
1027 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
1028 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
1029 }
1030 for (i = 0; i < subpass->color_count; ++i) {
1031 int idx = subpass->color_attachments[i].attachment;
1032 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1033
1034 if (dst_resolve_micro_tile_mode != -1) {
1035 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
1036 att, dst_resolve_micro_tile_mode);
1037 }
1038 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1039
1040 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1041 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1042
1043 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1044 }
1045
1046 for (i = subpass->color_count; i < 8; i++)
1047 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1048 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1049
1050 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1051 int idx = subpass->depth_stencil_attachment.attachment;
1052 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1053 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1054 struct radv_image *image = att->attachment->image;
1055 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1056
1057 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1058
1059 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1060 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1061 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1062 }
1063 radv_load_depth_clear_regs(cmd_buffer, image);
1064 } else {
1065 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1066 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1067 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1068 }
1069 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1070 S_028208_BR_X(framebuffer->width) |
1071 S_028208_BR_Y(framebuffer->height));
1072 }
1073
1074 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1075 {
1076 uint32_t db_count_control;
1077
1078 if(!cmd_buffer->state.active_occlusion_queries) {
1079 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1080 db_count_control = 0;
1081 } else {
1082 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1083 }
1084 } else {
1085 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1086 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1087 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1088 S_028004_ZPASS_ENABLE(1) |
1089 S_028004_SLICE_EVEN_ENABLE(1) |
1090 S_028004_SLICE_ODD_ENABLE(1);
1091 } else {
1092 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1093 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1094 }
1095 }
1096
1097 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1098 }
1099
1100 static void
1101 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1102 {
1103 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1104
1105 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1106 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1107 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1108 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1109 }
1110
1111 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1112 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1113 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1114 }
1115
1116 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1117 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1118 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1119 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1120 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1121 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1122 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1123 S_028430_STENCILOPVAL(1));
1124 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1125 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1126 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1127 S_028434_STENCILOPVAL_BF(1));
1128 }
1129
1130 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1131 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1132 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1133 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1134 }
1135
1136 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1137 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1138 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1139 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1140 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1141
1142 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1143 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1144 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1145 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1146 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1147 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1148 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1149 }
1150 }
1151
1152 cmd_buffer->state.dirty = 0;
1153 }
1154
1155 static void
1156 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1157 struct radv_pipeline *pipeline,
1158 int idx,
1159 uint64_t va,
1160 gl_shader_stage stage)
1161 {
1162 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1163 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline));
1164
1165 if (desc_set_loc->sgpr_idx == -1)
1166 return;
1167
1168 assert(!desc_set_loc->indirect);
1169 assert(desc_set_loc->num_sgprs == 2);
1170 radeon_set_sh_reg_seq(cmd_buffer->cs,
1171 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1172 radeon_emit(cmd_buffer->cs, va);
1173 radeon_emit(cmd_buffer->cs, va >> 32);
1174 }
1175
1176 static void
1177 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1178 struct radv_pipeline *pipeline,
1179 VkShaderStageFlags stages,
1180 struct radv_descriptor_set *set,
1181 unsigned idx)
1182 {
1183 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1184 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1185 idx, set->va,
1186 MESA_SHADER_FRAGMENT);
1187
1188 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1189 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1190 idx, set->va,
1191 MESA_SHADER_VERTEX);
1192
1193 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1194 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1195 idx, set->va,
1196 MESA_SHADER_GEOMETRY);
1197
1198 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1199 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1200 idx, set->va,
1201 MESA_SHADER_COMPUTE);
1202 }
1203
1204 static void
1205 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1206 struct radv_pipeline *pipeline,
1207 VkShaderStageFlags stages)
1208 {
1209 unsigned i;
1210 if (!cmd_buffer->state.descriptors_dirty)
1211 return;
1212
1213 for (i = 0; i < MAX_SETS; i++) {
1214 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1215 continue;
1216 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1217 if (!set)
1218 continue;
1219
1220 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1221 }
1222 cmd_buffer->state.descriptors_dirty = 0;
1223 }
1224
1225 static void
1226 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1227 struct radv_pipeline *pipeline,
1228 VkShaderStageFlags stages)
1229 {
1230 struct radv_pipeline_layout *layout = pipeline->layout;
1231 unsigned offset;
1232 void *ptr;
1233 uint64_t va;
1234
1235 stages &= cmd_buffer->push_constant_stages;
1236 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1237 return;
1238
1239 radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1240 16 * layout->dynamic_offset_count,
1241 256, &offset, &ptr);
1242
1243 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1244 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1245 16 * layout->dynamic_offset_count);
1246
1247 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1248 va += offset;
1249
1250 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1251 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1252 AC_UD_PUSH_CONSTANTS, va);
1253
1254 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1255 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1256 AC_UD_PUSH_CONSTANTS, va);
1257
1258 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1259 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1260 AC_UD_PUSH_CONSTANTS, va);
1261
1262 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1263 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1264 AC_UD_PUSH_CONSTANTS, va);
1265
1266 cmd_buffer->push_constant_stages &= ~stages;
1267 }
1268
1269 static void
1270 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer)
1271 {
1272 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1273 struct radv_device *device = cmd_buffer->device;
1274 uint32_t ia_multi_vgt_param;
1275 uint32_t ls_hs_config = 0;
1276
1277 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1278 cmd_buffer->cs, 4096);
1279
1280 cmd_buffer->no_draws = false;
1281 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1282 cmd_buffer->state.pipeline->num_vertex_attribs) {
1283 unsigned vb_offset;
1284 void *vb_ptr;
1285 uint32_t i = 0;
1286 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1287 uint64_t va;
1288
1289 /* allocate some descriptor state for vertex buffers */
1290 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1291 &vb_offset, &vb_ptr);
1292
1293 for (i = 0; i < num_attribs; i++) {
1294 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1295 uint32_t offset;
1296 int vb = cmd_buffer->state.pipeline->va_binding[i];
1297 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1298 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1299
1300 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1301 va = device->ws->buffer_get_va(buffer->bo);
1302
1303 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1304 va += offset + buffer->offset;
1305 desc[0] = va;
1306 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1307 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1308 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1309 else
1310 desc[2] = buffer->size - offset;
1311 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1312 }
1313
1314 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1315 va += vb_offset;
1316
1317 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1318 AC_UD_VS_VERTEX_BUFFERS, va);
1319 }
1320
1321 cmd_buffer->state.vertex_descriptors_dirty = false;
1322 cmd_buffer->state.vb_dirty = 0;
1323 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1324 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1325
1326 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1327 radv_emit_framebuffer_state(cmd_buffer);
1328
1329 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1330 radv_emit_viewport(cmd_buffer);
1331
1332 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR))
1333 radv_emit_scissor(cmd_buffer);
1334
1335 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1336 uint32_t stages = 0;
1337
1338 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1339 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1340 S_028B54_GS_EN(1) |
1341 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1342
1343 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, stages);
1344 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer);
1345
1346 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1347 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1348 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
1349 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1350 } else {
1351 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1352 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1353 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
1354 }
1355 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1356 }
1357
1358 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1359
1360 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1361 VK_SHADER_STAGE_ALL_GRAPHICS);
1362 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1363 VK_SHADER_STAGE_ALL_GRAPHICS);
1364
1365 assert(cmd_buffer->cs->cdw <= cdw_max);
1366
1367 si_emit_cache_flush(cmd_buffer);
1368 }
1369
1370 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1371 VkPipelineStageFlags src_stage_mask)
1372 {
1373 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1374 VK_PIPELINE_STAGE_TRANSFER_BIT |
1375 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1376 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1377 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1378 }
1379
1380 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1381 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1382 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1383 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1384 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1385 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1386 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1387 VK_PIPELINE_STAGE_TRANSFER_BIT |
1388 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1389 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1390 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1391 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1392 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1393 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1394 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1395 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1396 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1397 }
1398 }
1399
1400 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1401 {
1402 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1403
1404 /* TODO: actual cache flushes */
1405 }
1406
1407 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1408 VkAttachmentReference att)
1409 {
1410 unsigned idx = att.attachment;
1411 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1412 VkImageSubresourceRange range;
1413 range.aspectMask = 0;
1414 range.baseMipLevel = view->base_mip;
1415 range.levelCount = 1;
1416 range.baseArrayLayer = view->base_layer;
1417 range.layerCount = cmd_buffer->state.framebuffer->layers;
1418
1419 radv_handle_image_transition(cmd_buffer,
1420 view->image,
1421 cmd_buffer->state.attachments[idx].current_layout,
1422 att.layout, 0, 0, range,
1423 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1424
1425 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1426
1427
1428 }
1429
1430 void
1431 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1432 const struct radv_subpass *subpass, bool transitions)
1433 {
1434 if (transitions) {
1435 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1436
1437 for (unsigned i = 0; i < subpass->color_count; ++i) {
1438 radv_handle_subpass_image_transition(cmd_buffer,
1439 subpass->color_attachments[i]);
1440 }
1441
1442 for (unsigned i = 0; i < subpass->input_count; ++i) {
1443 radv_handle_subpass_image_transition(cmd_buffer,
1444 subpass->input_attachments[i]);
1445 }
1446
1447 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1448 radv_handle_subpass_image_transition(cmd_buffer,
1449 subpass->depth_stencil_attachment);
1450 }
1451 }
1452
1453 cmd_buffer->state.subpass = subpass;
1454
1455 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1456 }
1457
1458 static void
1459 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1460 struct radv_render_pass *pass,
1461 const VkRenderPassBeginInfo *info)
1462 {
1463 struct radv_cmd_state *state = &cmd_buffer->state;
1464
1465 if (pass->attachment_count == 0) {
1466 state->attachments = NULL;
1467 return;
1468 }
1469
1470 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1471 pass->attachment_count *
1472 sizeof(state->attachments[0]),
1473 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1474 if (state->attachments == NULL) {
1475 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1476 abort();
1477 }
1478
1479 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1480 struct radv_render_pass_attachment *att = &pass->attachments[i];
1481 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1482 VkImageAspectFlags clear_aspects = 0;
1483
1484 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1485 /* color attachment */
1486 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1487 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1488 }
1489 } else {
1490 /* depthstencil attachment */
1491 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1492 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1493 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1494 }
1495 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1496 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1497 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1498 }
1499 }
1500
1501 state->attachments[i].pending_clear_aspects = clear_aspects;
1502 if (clear_aspects && info) {
1503 assert(info->clearValueCount > i);
1504 state->attachments[i].clear_value = info->pClearValues[i];
1505 }
1506
1507 state->attachments[i].current_layout = att->initial_layout;
1508 }
1509 }
1510
1511 VkResult radv_AllocateCommandBuffers(
1512 VkDevice _device,
1513 const VkCommandBufferAllocateInfo *pAllocateInfo,
1514 VkCommandBuffer *pCommandBuffers)
1515 {
1516 RADV_FROM_HANDLE(radv_device, device, _device);
1517 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1518
1519 VkResult result = VK_SUCCESS;
1520 uint32_t i;
1521
1522 memset(pCommandBuffers, 0,
1523 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1524
1525 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1526 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1527 &pCommandBuffers[i]);
1528 if (result != VK_SUCCESS)
1529 break;
1530 }
1531
1532 if (result != VK_SUCCESS)
1533 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1534 i, pCommandBuffers);
1535
1536 return result;
1537 }
1538
1539 static void
1540 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
1541 {
1542 list_del(&cmd_buffer->pool_link);
1543
1544 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1545 &cmd_buffer->upload.list, list) {
1546 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1547 list_del(&up->list);
1548 free(up);
1549 }
1550
1551 if (cmd_buffer->upload.upload_bo)
1552 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
1553 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
1554 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1555 }
1556
1557 void radv_FreeCommandBuffers(
1558 VkDevice device,
1559 VkCommandPool commandPool,
1560 uint32_t commandBufferCount,
1561 const VkCommandBuffer *pCommandBuffers)
1562 {
1563 for (uint32_t i = 0; i < commandBufferCount; i++) {
1564 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1565
1566 if (cmd_buffer)
1567 radv_cmd_buffer_destroy(cmd_buffer);
1568 }
1569 }
1570
1571 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
1572 {
1573
1574 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
1575
1576 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1577 &cmd_buffer->upload.list, list) {
1578 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1579 list_del(&up->list);
1580 free(up);
1581 }
1582
1583 cmd_buffer->scratch_size_needed = 0;
1584 cmd_buffer->compute_scratch_size_needed = 0;
1585 cmd_buffer->esgs_ring_size_needed = 0;
1586 cmd_buffer->gsvs_ring_size_needed = 0;
1587
1588 if (cmd_buffer->upload.upload_bo)
1589 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
1590 cmd_buffer->upload.upload_bo, 8);
1591 cmd_buffer->upload.offset = 0;
1592
1593 cmd_buffer->record_fail = false;
1594
1595 cmd_buffer->ring_offsets_idx = -1;
1596 cmd_buffer->no_draws = true;
1597 }
1598
1599 VkResult radv_ResetCommandBuffer(
1600 VkCommandBuffer commandBuffer,
1601 VkCommandBufferResetFlags flags)
1602 {
1603 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1604 radv_reset_cmd_buffer(cmd_buffer);
1605 return VK_SUCCESS;
1606 }
1607
1608 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1609 {
1610 struct radv_device *device = cmd_buffer->device;
1611 if (device->gfx_init) {
1612 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1613 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1614 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1615 radeon_emit(cmd_buffer->cs, va);
1616 radeon_emit(cmd_buffer->cs, (va >> 32) & 0xffff);
1617 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1618 } else
1619 si_init_config(cmd_buffer);
1620 }
1621
1622 VkResult radv_BeginCommandBuffer(
1623 VkCommandBuffer commandBuffer,
1624 const VkCommandBufferBeginInfo *pBeginInfo)
1625 {
1626 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1627 radv_reset_cmd_buffer(cmd_buffer);
1628
1629 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1630
1631 /* setup initial configuration into command buffer */
1632 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1633 switch (cmd_buffer->queue_family_index) {
1634 case RADV_QUEUE_GENERAL:
1635 /* Flush read caches at the beginning of CS not flushed by the kernel. */
1636 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_ICACHE |
1637 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1638 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1639 RADV_CMD_FLAG_INV_VMEM_L1 |
1640 RADV_CMD_FLAG_INV_SMEM_L1 |
1641 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
1642 RADV_CMD_FLAG_INV_GLOBAL_L2;
1643 emit_gfx_buffer_state(cmd_buffer);
1644 radv_set_db_count_control(cmd_buffer);
1645 si_emit_cache_flush(cmd_buffer);
1646 break;
1647 case RADV_QUEUE_COMPUTE:
1648 cmd_buffer->state.flush_bits = RADV_CMD_FLAG_INV_ICACHE |
1649 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1650 RADV_CMD_FLAG_INV_VMEM_L1 |
1651 RADV_CMD_FLAG_INV_SMEM_L1 |
1652 RADV_CMD_FLAG_INV_GLOBAL_L2;
1653 si_init_compute(cmd_buffer);
1654 si_emit_cache_flush(cmd_buffer);
1655 break;
1656 case RADV_QUEUE_TRANSFER:
1657 default:
1658 break;
1659 }
1660 }
1661
1662 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1663 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1664 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1665
1666 struct radv_subpass *subpass =
1667 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1668
1669 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1670 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1671 }
1672
1673 return VK_SUCCESS;
1674 }
1675
1676 void radv_CmdBindVertexBuffers(
1677 VkCommandBuffer commandBuffer,
1678 uint32_t firstBinding,
1679 uint32_t bindingCount,
1680 const VkBuffer* pBuffers,
1681 const VkDeviceSize* pOffsets)
1682 {
1683 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1684 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1685
1686 /* We have to defer setting up vertex buffer since we need the buffer
1687 * stride from the pipeline. */
1688
1689 assert(firstBinding + bindingCount < MAX_VBS);
1690 for (uint32_t i = 0; i < bindingCount; i++) {
1691 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1692 vb[firstBinding + i].offset = pOffsets[i];
1693 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1694 }
1695 }
1696
1697 void radv_CmdBindIndexBuffer(
1698 VkCommandBuffer commandBuffer,
1699 VkBuffer buffer,
1700 VkDeviceSize offset,
1701 VkIndexType indexType)
1702 {
1703 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1704
1705 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1706 cmd_buffer->state.index_offset = offset;
1707 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1708 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1709 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1710 }
1711
1712
1713 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1714 struct radv_descriptor_set *set,
1715 unsigned idx)
1716 {
1717 struct radeon_winsys *ws = cmd_buffer->device->ws;
1718
1719 cmd_buffer->state.descriptors[idx] = set;
1720 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1721 if (!set)
1722 return;
1723
1724 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1725 if (set->descriptors[j])
1726 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1727
1728 if(set->bo)
1729 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1730 }
1731
1732 void radv_CmdBindDescriptorSets(
1733 VkCommandBuffer commandBuffer,
1734 VkPipelineBindPoint pipelineBindPoint,
1735 VkPipelineLayout _layout,
1736 uint32_t firstSet,
1737 uint32_t descriptorSetCount,
1738 const VkDescriptorSet* pDescriptorSets,
1739 uint32_t dynamicOffsetCount,
1740 const uint32_t* pDynamicOffsets)
1741 {
1742 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1743 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1744 unsigned dyn_idx = 0;
1745
1746 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1747 cmd_buffer->cs, MAX_SETS * 4 * 6);
1748
1749 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1750 unsigned idx = i + firstSet;
1751 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1752 radv_bind_descriptor_set(cmd_buffer, set, idx);
1753
1754 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1755 unsigned idx = j + layout->set[i].dynamic_offset_start;
1756 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1757 assert(dyn_idx < dynamicOffsetCount);
1758
1759 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1760 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1761 dst[0] = va;
1762 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1763 dst[2] = range->size;
1764 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1765 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1766 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1767 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1768 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1769 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1770 cmd_buffer->push_constant_stages |=
1771 set->layout->dynamic_shader_stages;
1772 }
1773 }
1774
1775 assert(cmd_buffer->cs->cdw <= cdw_max);
1776 }
1777
1778 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1779 VkPipelineLayout layout,
1780 VkShaderStageFlags stageFlags,
1781 uint32_t offset,
1782 uint32_t size,
1783 const void* pValues)
1784 {
1785 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1786 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1787 cmd_buffer->push_constant_stages |= stageFlags;
1788 }
1789
1790 VkResult radv_EndCommandBuffer(
1791 VkCommandBuffer commandBuffer)
1792 {
1793 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1794
1795 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
1796 si_emit_cache_flush(cmd_buffer);
1797
1798 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1799 cmd_buffer->record_fail)
1800 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1801 return VK_SUCCESS;
1802 }
1803
1804 static void
1805 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1806 {
1807 struct radeon_winsys *ws = cmd_buffer->device->ws;
1808 struct radv_shader_variant *compute_shader;
1809 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1810 uint64_t va;
1811
1812 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1813 return;
1814
1815 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1816
1817 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1818 va = ws->buffer_get_va(compute_shader->bo);
1819
1820 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1821
1822 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1823 cmd_buffer->cs, 16);
1824
1825 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1826 radeon_emit(cmd_buffer->cs, va >> 8);
1827 radeon_emit(cmd_buffer->cs, va >> 40);
1828
1829 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1830 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1831 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1832
1833
1834 cmd_buffer->compute_scratch_size_needed =
1835 MAX2(cmd_buffer->compute_scratch_size_needed,
1836 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1837
1838 /* change these once we have scratch support */
1839 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1840 S_00B860_WAVES(pipeline->max_waves) |
1841 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1842
1843 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1844 radeon_emit(cmd_buffer->cs,
1845 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1846 radeon_emit(cmd_buffer->cs,
1847 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1848 radeon_emit(cmd_buffer->cs,
1849 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1850
1851 assert(cmd_buffer->cs->cdw <= cdw_max);
1852 }
1853
1854
1855 void radv_CmdBindPipeline(
1856 VkCommandBuffer commandBuffer,
1857 VkPipelineBindPoint pipelineBindPoint,
1858 VkPipeline _pipeline)
1859 {
1860 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1861 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1862
1863 for (unsigned i = 0; i < MAX_SETS; i++) {
1864 if (cmd_buffer->state.descriptors[i])
1865 cmd_buffer->state.descriptors_dirty |= (1 << i);
1866 }
1867
1868 switch (pipelineBindPoint) {
1869 case VK_PIPELINE_BIND_POINT_COMPUTE:
1870 cmd_buffer->state.compute_pipeline = pipeline;
1871 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
1872 break;
1873 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1874 cmd_buffer->state.pipeline = pipeline;
1875 cmd_buffer->state.vertex_descriptors_dirty = true;
1876 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1877 cmd_buffer->push_constant_stages |= pipeline->active_stages;
1878
1879 /* Apply the dynamic state from the pipeline */
1880 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
1881 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
1882 &pipeline->dynamic_state,
1883 pipeline->dynamic_state_mask);
1884
1885 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
1886 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
1887 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
1888 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
1889
1890 if (radv_pipeline_has_gs(pipeline)) {
1891 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1892 AC_UD_SCRATCH_RING_OFFSETS);
1893 if (cmd_buffer->ring_offsets_idx == -1)
1894 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
1895 else if (loc->sgpr_idx != -1)
1896 assert(loc->sgpr_idx != cmd_buffer->ring_offsets_idx);
1897 }
1898 break;
1899 default:
1900 assert(!"invalid bind point");
1901 break;
1902 }
1903 }
1904
1905 void radv_CmdSetViewport(
1906 VkCommandBuffer commandBuffer,
1907 uint32_t firstViewport,
1908 uint32_t viewportCount,
1909 const VkViewport* pViewports)
1910 {
1911 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1912
1913 const uint32_t total_count = firstViewport + viewportCount;
1914 if (cmd_buffer->state.dynamic.viewport.count < total_count)
1915 cmd_buffer->state.dynamic.viewport.count = total_count;
1916
1917 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
1918 pViewports, viewportCount * sizeof(*pViewports));
1919
1920 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
1921 }
1922
1923 void radv_CmdSetScissor(
1924 VkCommandBuffer commandBuffer,
1925 uint32_t firstScissor,
1926 uint32_t scissorCount,
1927 const VkRect2D* pScissors)
1928 {
1929 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1930
1931 const uint32_t total_count = firstScissor + scissorCount;
1932 if (cmd_buffer->state.dynamic.scissor.count < total_count)
1933 cmd_buffer->state.dynamic.scissor.count = total_count;
1934
1935 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
1936 pScissors, scissorCount * sizeof(*pScissors));
1937 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1938 }
1939
1940 void radv_CmdSetLineWidth(
1941 VkCommandBuffer commandBuffer,
1942 float lineWidth)
1943 {
1944 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1945 cmd_buffer->state.dynamic.line_width = lineWidth;
1946 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1947 }
1948
1949 void radv_CmdSetDepthBias(
1950 VkCommandBuffer commandBuffer,
1951 float depthBiasConstantFactor,
1952 float depthBiasClamp,
1953 float depthBiasSlopeFactor)
1954 {
1955 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1956
1957 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
1958 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
1959 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
1960
1961 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1962 }
1963
1964 void radv_CmdSetBlendConstants(
1965 VkCommandBuffer commandBuffer,
1966 const float blendConstants[4])
1967 {
1968 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1969
1970 memcpy(cmd_buffer->state.dynamic.blend_constants,
1971 blendConstants, sizeof(float) * 4);
1972
1973 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
1974 }
1975
1976 void radv_CmdSetDepthBounds(
1977 VkCommandBuffer commandBuffer,
1978 float minDepthBounds,
1979 float maxDepthBounds)
1980 {
1981 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1982
1983 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
1984 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
1985
1986 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
1987 }
1988
1989 void radv_CmdSetStencilCompareMask(
1990 VkCommandBuffer commandBuffer,
1991 VkStencilFaceFlags faceMask,
1992 uint32_t compareMask)
1993 {
1994 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1995
1996 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1997 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
1998 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1999 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2000
2001 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2002 }
2003
2004 void radv_CmdSetStencilWriteMask(
2005 VkCommandBuffer commandBuffer,
2006 VkStencilFaceFlags faceMask,
2007 uint32_t writeMask)
2008 {
2009 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2010
2011 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2012 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2013 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2014 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2015
2016 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2017 }
2018
2019 void radv_CmdSetStencilReference(
2020 VkCommandBuffer commandBuffer,
2021 VkStencilFaceFlags faceMask,
2022 uint32_t reference)
2023 {
2024 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2025
2026 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2027 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2028 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2029 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2030
2031 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2032 }
2033
2034
2035 void radv_CmdExecuteCommands(
2036 VkCommandBuffer commandBuffer,
2037 uint32_t commandBufferCount,
2038 const VkCommandBuffer* pCmdBuffers)
2039 {
2040 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2041
2042 for (uint32_t i = 0; i < commandBufferCount; i++) {
2043 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2044
2045 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2046 secondary->scratch_size_needed);
2047 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2048 secondary->compute_scratch_size_needed);
2049
2050 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2051 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2052 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2053 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2054
2055 if (secondary->ring_offsets_idx != -1) {
2056 if (primary->ring_offsets_idx == -1)
2057 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2058 else
2059 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2060 }
2061 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2062 }
2063
2064 /* if we execute secondary we need to re-emit out pipelines */
2065 if (commandBufferCount) {
2066 primary->state.emitted_pipeline = NULL;
2067 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2068 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2069 }
2070 }
2071
2072 VkResult radv_CreateCommandPool(
2073 VkDevice _device,
2074 const VkCommandPoolCreateInfo* pCreateInfo,
2075 const VkAllocationCallbacks* pAllocator,
2076 VkCommandPool* pCmdPool)
2077 {
2078 RADV_FROM_HANDLE(radv_device, device, _device);
2079 struct radv_cmd_pool *pool;
2080
2081 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2082 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2083 if (pool == NULL)
2084 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2085
2086 if (pAllocator)
2087 pool->alloc = *pAllocator;
2088 else
2089 pool->alloc = device->alloc;
2090
2091 list_inithead(&pool->cmd_buffers);
2092
2093 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2094
2095 *pCmdPool = radv_cmd_pool_to_handle(pool);
2096
2097 return VK_SUCCESS;
2098
2099 }
2100
2101 void radv_DestroyCommandPool(
2102 VkDevice _device,
2103 VkCommandPool commandPool,
2104 const VkAllocationCallbacks* pAllocator)
2105 {
2106 RADV_FROM_HANDLE(radv_device, device, _device);
2107 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2108
2109 if (!pool)
2110 return;
2111
2112 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2113 &pool->cmd_buffers, pool_link) {
2114 radv_cmd_buffer_destroy(cmd_buffer);
2115 }
2116
2117 vk_free2(&device->alloc, pAllocator, pool);
2118 }
2119
2120 VkResult radv_ResetCommandPool(
2121 VkDevice device,
2122 VkCommandPool commandPool,
2123 VkCommandPoolResetFlags flags)
2124 {
2125 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2126
2127 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2128 &pool->cmd_buffers, pool_link) {
2129 radv_reset_cmd_buffer(cmd_buffer);
2130 }
2131
2132 return VK_SUCCESS;
2133 }
2134
2135 void radv_TrimCommandPoolKHR(
2136 VkDevice device,
2137 VkCommandPool commandPool,
2138 VkCommandPoolTrimFlagsKHR flags)
2139 {
2140 }
2141
2142 void radv_CmdBeginRenderPass(
2143 VkCommandBuffer commandBuffer,
2144 const VkRenderPassBeginInfo* pRenderPassBegin,
2145 VkSubpassContents contents)
2146 {
2147 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2148 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2149 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2150
2151 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2152 cmd_buffer->cs, 2048);
2153
2154 cmd_buffer->state.framebuffer = framebuffer;
2155 cmd_buffer->state.pass = pass;
2156 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2157 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2158
2159 si_emit_cache_flush(cmd_buffer);
2160
2161 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2162 assert(cmd_buffer->cs->cdw <= cdw_max);
2163
2164 radv_cmd_buffer_clear_subpass(cmd_buffer);
2165 }
2166
2167 void radv_CmdNextSubpass(
2168 VkCommandBuffer commandBuffer,
2169 VkSubpassContents contents)
2170 {
2171 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2172
2173 si_emit_cache_flush(cmd_buffer);
2174 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2175
2176 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2177 2048);
2178
2179 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2180 radv_cmd_buffer_clear_subpass(cmd_buffer);
2181 }
2182
2183 void radv_CmdDraw(
2184 VkCommandBuffer commandBuffer,
2185 uint32_t vertexCount,
2186 uint32_t instanceCount,
2187 uint32_t firstVertex,
2188 uint32_t firstInstance)
2189 {
2190 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2191 radv_cmd_buffer_flush_state(cmd_buffer);
2192
2193 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2194
2195 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2196 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2197 if (loc->sgpr_idx != -1) {
2198 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2199 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2200 radeon_emit(cmd_buffer->cs, firstVertex);
2201 radeon_emit(cmd_buffer->cs, firstInstance);
2202 radeon_emit(cmd_buffer->cs, 0);
2203 }
2204 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2205 radeon_emit(cmd_buffer->cs, instanceCount);
2206
2207 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2208 radeon_emit(cmd_buffer->cs, vertexCount);
2209 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2210 S_0287F0_USE_OPAQUE(0));
2211
2212 assert(cmd_buffer->cs->cdw <= cdw_max);
2213
2214 radv_cmd_buffer_trace_emit(cmd_buffer);
2215 }
2216
2217 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2218 {
2219 uint32_t primitive_reset_index = cmd_buffer->state.last_primitive_reset_index ? 0xffffffffu : 0xffffu;
2220
2221 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
2222 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
2223 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
2224 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2225 primitive_reset_index);
2226 }
2227 }
2228
2229 void radv_CmdDrawIndexed(
2230 VkCommandBuffer commandBuffer,
2231 uint32_t indexCount,
2232 uint32_t instanceCount,
2233 uint32_t firstIndex,
2234 int32_t vertexOffset,
2235 uint32_t firstInstance)
2236 {
2237 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2238 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2239 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2240 uint64_t index_va;
2241
2242 radv_cmd_buffer_flush_state(cmd_buffer);
2243 radv_emit_primitive_reset_index(cmd_buffer);
2244
2245 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2246
2247 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2248 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2249
2250 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2251 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2252 if (loc->sgpr_idx != -1) {
2253 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2254 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2255 radeon_emit(cmd_buffer->cs, vertexOffset);
2256 radeon_emit(cmd_buffer->cs, firstInstance);
2257 radeon_emit(cmd_buffer->cs, 0);
2258 }
2259 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2260 radeon_emit(cmd_buffer->cs, instanceCount);
2261
2262 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2263 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2264 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2265 radeon_emit(cmd_buffer->cs, index_max_size);
2266 radeon_emit(cmd_buffer->cs, index_va);
2267 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2268 radeon_emit(cmd_buffer->cs, indexCount);
2269 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2270
2271 assert(cmd_buffer->cs->cdw <= cdw_max);
2272 radv_cmd_buffer_trace_emit(cmd_buffer);
2273 }
2274
2275 static void
2276 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2277 VkBuffer _buffer,
2278 VkDeviceSize offset,
2279 VkBuffer _count_buffer,
2280 VkDeviceSize count_offset,
2281 uint32_t draw_count,
2282 uint32_t stride,
2283 bool indexed)
2284 {
2285 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2286 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2287 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2288 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2289 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2290 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2291 indirect_va += offset + buffer->offset;
2292 uint64_t count_va = 0;
2293
2294 if (count_buffer) {
2295 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2296 count_va += count_offset + count_buffer->offset;
2297 }
2298
2299 if (!draw_count)
2300 return;
2301
2302 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2303
2304 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2305 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2306 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline));
2307 assert(loc->sgpr_idx != -1);
2308 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2309 radeon_emit(cs, 1);
2310 radeon_emit(cs, indirect_va);
2311 radeon_emit(cs, indirect_va >> 32);
2312
2313 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2314 PKT3_DRAW_INDIRECT_MULTI,
2315 8, false));
2316 radeon_emit(cs, 0);
2317 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2318 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2319 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2320 S_2C3_DRAW_INDEX_ENABLE(1) |
2321 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2322 radeon_emit(cs, draw_count); /* count */
2323 radeon_emit(cs, count_va); /* count_addr */
2324 radeon_emit(cs, count_va >> 32);
2325 radeon_emit(cs, stride); /* stride */
2326 radeon_emit(cs, di_src_sel);
2327 radv_cmd_buffer_trace_emit(cmd_buffer);
2328 }
2329
2330 static void
2331 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2332 VkBuffer buffer,
2333 VkDeviceSize offset,
2334 VkBuffer countBuffer,
2335 VkDeviceSize countBufferOffset,
2336 uint32_t maxDrawCount,
2337 uint32_t stride)
2338 {
2339 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2340 radv_cmd_buffer_flush_state(cmd_buffer);
2341
2342 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2343 cmd_buffer->cs, 14);
2344
2345 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2346 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2347
2348 assert(cmd_buffer->cs->cdw <= cdw_max);
2349 }
2350
2351 static void
2352 radv_cmd_draw_indexed_indirect_count(
2353 VkCommandBuffer commandBuffer,
2354 VkBuffer buffer,
2355 VkDeviceSize offset,
2356 VkBuffer countBuffer,
2357 VkDeviceSize countBufferOffset,
2358 uint32_t maxDrawCount,
2359 uint32_t stride)
2360 {
2361 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2362 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2363 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2364 uint64_t index_va;
2365 radv_cmd_buffer_flush_state(cmd_buffer);
2366 radv_emit_primitive_reset_index(cmd_buffer);
2367
2368 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2369 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2370
2371 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2372
2373 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2374 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2375
2376 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2377 radeon_emit(cmd_buffer->cs, index_va);
2378 radeon_emit(cmd_buffer->cs, index_va >> 32);
2379
2380 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2381 radeon_emit(cmd_buffer->cs, index_max_size);
2382
2383 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2384 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2385
2386 assert(cmd_buffer->cs->cdw <= cdw_max);
2387 }
2388
2389 void radv_CmdDrawIndirect(
2390 VkCommandBuffer commandBuffer,
2391 VkBuffer buffer,
2392 VkDeviceSize offset,
2393 uint32_t drawCount,
2394 uint32_t stride)
2395 {
2396 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2397 VK_NULL_HANDLE, 0, drawCount, stride);
2398 }
2399
2400 void radv_CmdDrawIndexedIndirect(
2401 VkCommandBuffer commandBuffer,
2402 VkBuffer buffer,
2403 VkDeviceSize offset,
2404 uint32_t drawCount,
2405 uint32_t stride)
2406 {
2407 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2408 VK_NULL_HANDLE, 0, drawCount, stride);
2409 }
2410
2411 void radv_CmdDrawIndirectCountAMD(
2412 VkCommandBuffer commandBuffer,
2413 VkBuffer buffer,
2414 VkDeviceSize offset,
2415 VkBuffer countBuffer,
2416 VkDeviceSize countBufferOffset,
2417 uint32_t maxDrawCount,
2418 uint32_t stride)
2419 {
2420 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2421 countBuffer, countBufferOffset,
2422 maxDrawCount, stride);
2423 }
2424
2425 void radv_CmdDrawIndexedIndirectCountAMD(
2426 VkCommandBuffer commandBuffer,
2427 VkBuffer buffer,
2428 VkDeviceSize offset,
2429 VkBuffer countBuffer,
2430 VkDeviceSize countBufferOffset,
2431 uint32_t maxDrawCount,
2432 uint32_t stride)
2433 {
2434 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2435 countBuffer, countBufferOffset,
2436 maxDrawCount, stride);
2437 }
2438
2439 static void
2440 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2441 {
2442 cmd_buffer->no_draws = false;
2443 radv_emit_compute_pipeline(cmd_buffer);
2444 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2445 VK_SHADER_STAGE_COMPUTE_BIT);
2446 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2447 VK_SHADER_STAGE_COMPUTE_BIT);
2448 si_emit_cache_flush(cmd_buffer);
2449 }
2450
2451 void radv_CmdDispatch(
2452 VkCommandBuffer commandBuffer,
2453 uint32_t x,
2454 uint32_t y,
2455 uint32_t z)
2456 {
2457 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2458
2459 radv_flush_compute_state(cmd_buffer);
2460
2461 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2462
2463 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2464 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2465 if (loc->sgpr_idx != -1) {
2466 assert(!loc->indirect);
2467 assert(loc->num_sgprs == 3);
2468 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2469 radeon_emit(cmd_buffer->cs, x);
2470 radeon_emit(cmd_buffer->cs, y);
2471 radeon_emit(cmd_buffer->cs, z);
2472 }
2473
2474 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2475 PKT3_SHADER_TYPE_S(1));
2476 radeon_emit(cmd_buffer->cs, x);
2477 radeon_emit(cmd_buffer->cs, y);
2478 radeon_emit(cmd_buffer->cs, z);
2479 radeon_emit(cmd_buffer->cs, 1);
2480
2481 assert(cmd_buffer->cs->cdw <= cdw_max);
2482 radv_cmd_buffer_trace_emit(cmd_buffer);
2483 }
2484
2485 void radv_CmdDispatchIndirect(
2486 VkCommandBuffer commandBuffer,
2487 VkBuffer _buffer,
2488 VkDeviceSize offset)
2489 {
2490 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2491 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2492 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2493 va += buffer->offset + offset;
2494
2495 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2496
2497 radv_flush_compute_state(cmd_buffer);
2498
2499 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2500 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2501 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2502 if (loc->sgpr_idx != -1) {
2503 for (unsigned i = 0; i < 3; ++i) {
2504 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2505 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2506 COPY_DATA_DST_SEL(COPY_DATA_REG));
2507 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2508 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2509 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2510 radeon_emit(cmd_buffer->cs, 0);
2511 }
2512 }
2513
2514 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2515 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2516 PKT3_SHADER_TYPE_S(1));
2517 radeon_emit(cmd_buffer->cs, va);
2518 radeon_emit(cmd_buffer->cs, va >> 32);
2519 radeon_emit(cmd_buffer->cs, 1);
2520 } else {
2521 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2522 PKT3_SHADER_TYPE_S(1));
2523 radeon_emit(cmd_buffer->cs, 1);
2524 radeon_emit(cmd_buffer->cs, va);
2525 radeon_emit(cmd_buffer->cs, va >> 32);
2526
2527 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2528 PKT3_SHADER_TYPE_S(1));
2529 radeon_emit(cmd_buffer->cs, 0);
2530 radeon_emit(cmd_buffer->cs, 1);
2531 }
2532
2533 assert(cmd_buffer->cs->cdw <= cdw_max);
2534 radv_cmd_buffer_trace_emit(cmd_buffer);
2535 }
2536
2537 void radv_unaligned_dispatch(
2538 struct radv_cmd_buffer *cmd_buffer,
2539 uint32_t x,
2540 uint32_t y,
2541 uint32_t z)
2542 {
2543 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2544 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2545 uint32_t blocks[3], remainder[3];
2546
2547 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2548 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2549 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2550
2551 /* If aligned, these should be an entire block size, not 0 */
2552 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2553 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2554 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2555
2556 radv_flush_compute_state(cmd_buffer);
2557
2558 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2559
2560 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2561 radeon_emit(cmd_buffer->cs,
2562 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2563 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2564 radeon_emit(cmd_buffer->cs,
2565 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2566 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2567 radeon_emit(cmd_buffer->cs,
2568 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2569 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2570
2571 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2572 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2573 if (loc->sgpr_idx != -1) {
2574 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2575 radeon_emit(cmd_buffer->cs, blocks[0]);
2576 radeon_emit(cmd_buffer->cs, blocks[1]);
2577 radeon_emit(cmd_buffer->cs, blocks[2]);
2578 }
2579 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2580 PKT3_SHADER_TYPE_S(1));
2581 radeon_emit(cmd_buffer->cs, blocks[0]);
2582 radeon_emit(cmd_buffer->cs, blocks[1]);
2583 radeon_emit(cmd_buffer->cs, blocks[2]);
2584 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2585 S_00B800_PARTIAL_TG_EN(1));
2586
2587 assert(cmd_buffer->cs->cdw <= cdw_max);
2588 radv_cmd_buffer_trace_emit(cmd_buffer);
2589 }
2590
2591 void radv_CmdEndRenderPass(
2592 VkCommandBuffer commandBuffer)
2593 {
2594 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2595
2596 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2597
2598 si_emit_cache_flush(cmd_buffer);
2599 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2600
2601 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2602 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2603 radv_handle_subpass_image_transition(cmd_buffer,
2604 (VkAttachmentReference){i, layout});
2605 }
2606
2607 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2608
2609 cmd_buffer->state.pass = NULL;
2610 cmd_buffer->state.subpass = NULL;
2611 cmd_buffer->state.attachments = NULL;
2612 cmd_buffer->state.framebuffer = NULL;
2613 }
2614
2615
2616 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2617 struct radv_image *image)
2618 {
2619
2620 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2621 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2622
2623 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->htile.offset,
2624 image->htile.size, 0xffffffff);
2625
2626 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2627 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2628 RADV_CMD_FLAG_INV_VMEM_L1 |
2629 RADV_CMD_FLAG_INV_GLOBAL_L2;
2630 }
2631
2632 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2633 struct radv_image *image,
2634 VkImageLayout src_layout,
2635 VkImageLayout dst_layout,
2636 VkImageSubresourceRange range,
2637 VkImageAspectFlags pending_clears)
2638 {
2639 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2640 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2641 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2642 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2643 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2644 /* The clear will initialize htile. */
2645 return;
2646 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2647 radv_layout_has_htile(image, dst_layout)) {
2648 /* TODO: merge with the clear if applicable */
2649 radv_initialize_htile(cmd_buffer, image);
2650 } else if (!radv_layout_has_htile(image, src_layout) &&
2651 radv_layout_has_htile(image, dst_layout)) {
2652 radv_initialize_htile(cmd_buffer, image);
2653 } else if ((radv_layout_has_htile(image, src_layout) &&
2654 !radv_layout_has_htile(image, dst_layout)) ||
2655 (radv_layout_is_htile_compressed(image, src_layout) &&
2656 !radv_layout_is_htile_compressed(image, dst_layout))) {
2657
2658 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2659 range.baseMipLevel = 0;
2660 range.levelCount = 1;
2661
2662 radv_decompress_depth_image_inplace(cmd_buffer, image, &range);
2663 }
2664 }
2665
2666 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2667 struct radv_image *image, uint32_t value)
2668 {
2669 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2670 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2671
2672 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2673 image->cmask.size, value);
2674
2675 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2676 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2677 RADV_CMD_FLAG_INV_VMEM_L1 |
2678 RADV_CMD_FLAG_INV_GLOBAL_L2;
2679 }
2680
2681 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2682 struct radv_image *image,
2683 VkImageLayout src_layout,
2684 VkImageLayout dst_layout,
2685 unsigned src_queue_mask,
2686 unsigned dst_queue_mask,
2687 VkImageSubresourceRange range,
2688 VkImageAspectFlags pending_clears)
2689 {
2690 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2691 if (image->fmask.size)
2692 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2693 else
2694 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2695 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2696 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2697 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2698 }
2699 }
2700
2701 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2702 struct radv_image *image, uint32_t value)
2703 {
2704
2705 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2706 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2707
2708 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2709 image->surface.dcc_size, value);
2710
2711 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2712 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2713 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2714 RADV_CMD_FLAG_INV_VMEM_L1 |
2715 RADV_CMD_FLAG_INV_GLOBAL_L2;
2716 }
2717
2718 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2719 struct radv_image *image,
2720 VkImageLayout src_layout,
2721 VkImageLayout dst_layout,
2722 unsigned src_queue_mask,
2723 unsigned dst_queue_mask,
2724 VkImageSubresourceRange range,
2725 VkImageAspectFlags pending_clears)
2726 {
2727 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2728 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2729 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2730 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2731 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2732 }
2733 }
2734
2735 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2736 struct radv_image *image,
2737 VkImageLayout src_layout,
2738 VkImageLayout dst_layout,
2739 uint32_t src_family,
2740 uint32_t dst_family,
2741 VkImageSubresourceRange range,
2742 VkImageAspectFlags pending_clears)
2743 {
2744 if (image->exclusive && src_family != dst_family) {
2745 /* This is an acquire or a release operation and there will be
2746 * a corresponding release/acquire. Do the transition in the
2747 * most flexible queue. */
2748
2749 assert(src_family == cmd_buffer->queue_family_index ||
2750 dst_family == cmd_buffer->queue_family_index);
2751
2752 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
2753 return;
2754
2755 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
2756 (src_family == RADV_QUEUE_GENERAL ||
2757 dst_family == RADV_QUEUE_GENERAL))
2758 return;
2759 }
2760
2761 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
2762 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
2763
2764 if (image->htile.size)
2765 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2766 dst_layout, range, pending_clears);
2767
2768 if (image->cmask.size)
2769 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2770 dst_layout, src_queue_mask,
2771 dst_queue_mask, range,
2772 pending_clears);
2773
2774 if (image->surface.dcc_size)
2775 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2776 dst_layout, src_queue_mask,
2777 dst_queue_mask, range,
2778 pending_clears);
2779 }
2780
2781 void radv_CmdPipelineBarrier(
2782 VkCommandBuffer commandBuffer,
2783 VkPipelineStageFlags srcStageMask,
2784 VkPipelineStageFlags destStageMask,
2785 VkBool32 byRegion,
2786 uint32_t memoryBarrierCount,
2787 const VkMemoryBarrier* pMemoryBarriers,
2788 uint32_t bufferMemoryBarrierCount,
2789 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2790 uint32_t imageMemoryBarrierCount,
2791 const VkImageMemoryBarrier* pImageMemoryBarriers)
2792 {
2793 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2794 VkAccessFlags src_flags = 0;
2795 VkAccessFlags dst_flags = 0;
2796 uint32_t b;
2797 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2798 src_flags |= pMemoryBarriers[i].srcAccessMask;
2799 dst_flags |= pMemoryBarriers[i].dstAccessMask;
2800 }
2801
2802 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2803 src_flags |= pBufferMemoryBarriers[i].srcAccessMask;
2804 dst_flags |= pBufferMemoryBarriers[i].dstAccessMask;
2805 }
2806
2807 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2808 src_flags |= pImageMemoryBarriers[i].srcAccessMask;
2809 dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
2810 }
2811
2812 enum radv_cmd_flush_bits flush_bits = 0;
2813 for_each_bit(b, src_flags) {
2814 switch ((VkAccessFlagBits)(1 << b)) {
2815 case VK_ACCESS_SHADER_WRITE_BIT:
2816 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2817 break;
2818 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2819 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2820 break;
2821 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2822 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2823 break;
2824 case VK_ACCESS_TRANSFER_WRITE_BIT:
2825 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2826 break;
2827 default:
2828 break;
2829 }
2830 }
2831 cmd_buffer->state.flush_bits |= flush_bits;
2832
2833 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2834 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2835 radv_handle_image_transition(cmd_buffer, image,
2836 pImageMemoryBarriers[i].oldLayout,
2837 pImageMemoryBarriers[i].newLayout,
2838 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2839 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2840 pImageMemoryBarriers[i].subresourceRange,
2841 0);
2842 }
2843
2844 flush_bits = 0;
2845
2846 for_each_bit(b, dst_flags) {
2847 switch ((VkAccessFlagBits)(1 << b)) {
2848 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2849 case VK_ACCESS_INDEX_READ_BIT:
2850 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2851 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2852 break;
2853 case VK_ACCESS_UNIFORM_READ_BIT:
2854 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2855 break;
2856 case VK_ACCESS_SHADER_READ_BIT:
2857 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2858 break;
2859 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2860 case VK_ACCESS_TRANSFER_READ_BIT:
2861 case VK_ACCESS_TRANSFER_WRITE_BIT:
2862 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2863 flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER | RADV_CMD_FLAG_INV_GLOBAL_L2;
2864 default:
2865 break;
2866 }
2867 }
2868
2869 flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2870 RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2871
2872 cmd_buffer->state.flush_bits |= flush_bits;
2873 }
2874
2875
2876 static void write_event(struct radv_cmd_buffer *cmd_buffer,
2877 struct radv_event *event,
2878 VkPipelineStageFlags stageMask,
2879 unsigned value)
2880 {
2881 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2882 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2883
2884 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2885
2886 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
2887
2888 /* TODO: this is overkill. Probably should figure something out from
2889 * the stage mask. */
2890
2891 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
2892 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2893 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2894 EVENT_INDEX(5));
2895 radeon_emit(cs, va);
2896 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2897 radeon_emit(cs, 2);
2898 radeon_emit(cs, 0);
2899 }
2900
2901 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2902 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2903 EVENT_INDEX(5));
2904 radeon_emit(cs, va);
2905 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2906 radeon_emit(cs, value);
2907 radeon_emit(cs, 0);
2908
2909 assert(cmd_buffer->cs->cdw <= cdw_max);
2910 }
2911
2912 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
2913 VkEvent _event,
2914 VkPipelineStageFlags stageMask)
2915 {
2916 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2917 RADV_FROM_HANDLE(radv_event, event, _event);
2918
2919 write_event(cmd_buffer, event, stageMask, 1);
2920 }
2921
2922 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
2923 VkEvent _event,
2924 VkPipelineStageFlags stageMask)
2925 {
2926 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2927 RADV_FROM_HANDLE(radv_event, event, _event);
2928
2929 write_event(cmd_buffer, event, stageMask, 0);
2930 }
2931
2932 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
2933 uint32_t eventCount,
2934 const VkEvent* pEvents,
2935 VkPipelineStageFlags srcStageMask,
2936 VkPipelineStageFlags dstStageMask,
2937 uint32_t memoryBarrierCount,
2938 const VkMemoryBarrier* pMemoryBarriers,
2939 uint32_t bufferMemoryBarrierCount,
2940 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2941 uint32_t imageMemoryBarrierCount,
2942 const VkImageMemoryBarrier* pImageMemoryBarriers)
2943 {
2944 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2945 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2946
2947 for (unsigned i = 0; i < eventCount; ++i) {
2948 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
2949 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2950
2951 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2952
2953 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
2954
2955 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
2956 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
2957 radeon_emit(cs, va);
2958 radeon_emit(cs, va >> 32);
2959 radeon_emit(cs, 1); /* reference value */
2960 radeon_emit(cs, 0xffffffff); /* mask */
2961 radeon_emit(cs, 4); /* poll interval */
2962
2963 assert(cmd_buffer->cs->cdw <= cdw_max);
2964 }
2965
2966
2967 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2968 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2969
2970 radv_handle_image_transition(cmd_buffer, image,
2971 pImageMemoryBarriers[i].oldLayout,
2972 pImageMemoryBarriers[i].newLayout,
2973 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2974 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2975 pImageMemoryBarriers[i].subresourceRange,
2976 0);
2977 }
2978
2979 /* TODO: figure out how to do memory barriers without waiting */
2980 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
2981 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2982 RADV_CMD_FLAG_INV_VMEM_L1 |
2983 RADV_CMD_FLAG_INV_SMEM_L1;
2984 }