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radv: fix error code when resizing the upload BO
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "gfx9d.h"
33 #include "vk_format.h"
34 #include "radv_meta.h"
35
36 #include "ac_debug.h"
37
38 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
39 struct radv_image *image,
40 VkImageLayout src_layout,
41 VkImageLayout dst_layout,
42 uint32_t src_family,
43 uint32_t dst_family,
44 const VkImageSubresourceRange *range,
45 VkImageAspectFlags pending_clears);
46
47 const struct radv_dynamic_state default_dynamic_state = {
48 .viewport = {
49 .count = 0,
50 },
51 .scissor = {
52 .count = 0,
53 },
54 .line_width = 1.0f,
55 .depth_bias = {
56 .bias = 0.0f,
57 .clamp = 0.0f,
58 .slope = 0.0f,
59 },
60 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
61 .depth_bounds = {
62 .min = 0.0f,
63 .max = 1.0f,
64 },
65 .stencil_compare_mask = {
66 .front = ~0u,
67 .back = ~0u,
68 },
69 .stencil_write_mask = {
70 .front = ~0u,
71 .back = ~0u,
72 },
73 .stencil_reference = {
74 .front = 0u,
75 .back = 0u,
76 },
77 };
78
79 void
80 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
81 const struct radv_dynamic_state *src,
82 uint32_t copy_mask)
83 {
84 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
85 dest->viewport.count = src->viewport.count;
86 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
87 src->viewport.count);
88 }
89
90 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
91 dest->scissor.count = src->scissor.count;
92 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
93 src->scissor.count);
94 }
95
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
97 dest->line_width = src->line_width;
98
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
100 dest->depth_bias = src->depth_bias;
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
103 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
106 dest->depth_bounds = src->depth_bounds;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
109 dest->stencil_compare_mask = src->stencil_compare_mask;
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
112 dest->stencil_write_mask = src->stencil_write_mask;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
115 dest->stencil_reference = src->stencil_reference;
116 }
117
118 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
119 {
120 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
121 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
122 }
123
124 enum ring_type radv_queue_family_to_ring(int f) {
125 switch (f) {
126 case RADV_QUEUE_GENERAL:
127 return RING_GFX;
128 case RADV_QUEUE_COMPUTE:
129 return RING_COMPUTE;
130 case RADV_QUEUE_TRANSFER:
131 return RING_DMA;
132 default:
133 unreachable("Unknown queue family");
134 }
135 }
136
137 static VkResult radv_create_cmd_buffer(
138 struct radv_device * device,
139 struct radv_cmd_pool * pool,
140 VkCommandBufferLevel level,
141 VkCommandBuffer* pCommandBuffer)
142 {
143 struct radv_cmd_buffer *cmd_buffer;
144 VkResult result;
145 unsigned ring;
146 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
147 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
148 if (cmd_buffer == NULL)
149 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
150
151 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
152 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
153 cmd_buffer->device = device;
154 cmd_buffer->pool = pool;
155 cmd_buffer->level = level;
156
157 if (pool) {
158 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
159 cmd_buffer->queue_family_index = pool->queue_family_index;
160
161 } else {
162 /* Init the pool_link so we can safefly call list_del when we destroy
163 * the command buffer
164 */
165 list_inithead(&cmd_buffer->pool_link);
166 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
167 }
168
169 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
170
171 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
172 if (!cmd_buffer->cs) {
173 result = VK_ERROR_OUT_OF_HOST_MEMORY;
174 goto fail;
175 }
176
177 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
178
179 cmd_buffer->upload.offset = 0;
180 cmd_buffer->upload.size = 0;
181 list_inithead(&cmd_buffer->upload.list);
182
183 return VK_SUCCESS;
184
185 fail:
186 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
187
188 return result;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
211 {
212
213 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
214
215 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
216 &cmd_buffer->upload.list, list) {
217 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
218 list_del(&up->list);
219 free(up);
220 }
221
222 cmd_buffer->scratch_size_needed = 0;
223 cmd_buffer->compute_scratch_size_needed = 0;
224 cmd_buffer->esgs_ring_size_needed = 0;
225 cmd_buffer->gsvs_ring_size_needed = 0;
226 cmd_buffer->tess_rings_needed = false;
227 cmd_buffer->sample_positions_needed = false;
228
229 if (cmd_buffer->upload.upload_bo)
230 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
231 cmd_buffer->upload.upload_bo, 8);
232 cmd_buffer->upload.offset = 0;
233
234 cmd_buffer->record_result = VK_SUCCESS;
235
236 cmd_buffer->ring_offsets_idx = -1;
237
238 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
239 void *fence_ptr;
240 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
241 &cmd_buffer->gfx9_fence_offset,
242 &fence_ptr);
243 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
244 }
245 }
246
247 static bool
248 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
249 uint64_t min_needed)
250 {
251 uint64_t new_size;
252 struct radeon_winsys_bo *bo;
253 struct radv_cmd_buffer_upload *upload;
254 struct radv_device *device = cmd_buffer->device;
255
256 new_size = MAX2(min_needed, 16 * 1024);
257 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
258
259 bo = device->ws->buffer_create(device->ws,
260 new_size, 4096,
261 RADEON_DOMAIN_GTT,
262 RADEON_FLAG_CPU_ACCESS);
263
264 if (!bo) {
265 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
266 return false;
267 }
268
269 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
270 if (cmd_buffer->upload.upload_bo) {
271 upload = malloc(sizeof(*upload));
272
273 if (!upload) {
274 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
275 device->ws->buffer_destroy(bo);
276 return false;
277 }
278
279 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
280 list_add(&upload->list, &cmd_buffer->upload.list);
281 }
282
283 cmd_buffer->upload.upload_bo = bo;
284 cmd_buffer->upload.size = new_size;
285 cmd_buffer->upload.offset = 0;
286 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
287
288 if (!cmd_buffer->upload.map) {
289 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
290 return false;
291 }
292
293 return true;
294 }
295
296 bool
297 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
298 unsigned size,
299 unsigned alignment,
300 unsigned *out_offset,
301 void **ptr)
302 {
303 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
304 if (offset + size > cmd_buffer->upload.size) {
305 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
306 return false;
307 offset = 0;
308 }
309
310 *out_offset = offset;
311 *ptr = cmd_buffer->upload.map + offset;
312
313 cmd_buffer->upload.offset = offset + size;
314 return true;
315 }
316
317 bool
318 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
319 unsigned size, unsigned alignment,
320 const void *data, unsigned *out_offset)
321 {
322 uint8_t *ptr;
323
324 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
325 out_offset, (void **)&ptr))
326 return false;
327
328 if (ptr)
329 memcpy(ptr, data, size);
330
331 return true;
332 }
333
334 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
335 {
336 struct radv_device *device = cmd_buffer->device;
337 struct radeon_winsys_cs *cs = cmd_buffer->cs;
338 uint64_t va;
339
340 if (!device->trace_bo)
341 return;
342
343 va = device->ws->buffer_get_va(device->trace_bo);
344 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
345 va += 4;
346
347 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
348
349 ++cmd_buffer->state.trace_id;
350 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
351 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
352 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
353 S_370_WR_CONFIRM(1) |
354 S_370_ENGINE_SEL(V_370_ME));
355 radeon_emit(cs, va);
356 radeon_emit(cs, va >> 32);
357 radeon_emit(cs, cmd_buffer->state.trace_id);
358 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
359 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
360 }
361
362 static void
363 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
364 struct radv_pipeline *pipeline)
365 {
366 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
367 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
368 8);
369 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
370 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
371
372 if (cmd_buffer->device->physical_device->has_rbplus) {
373
374 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
375 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
376
377 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
378 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
379 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
380 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
381 }
382 }
383
384 static void
385 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
386 struct radv_pipeline *pipeline)
387 {
388 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
389 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
390 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
391
392 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
393 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
394 }
395
396 /* 12.4 fixed-point */
397 static unsigned radv_pack_float_12p4(float x)
398 {
399 return x <= 0 ? 0 :
400 x >= 4096 ? 0xffff : x * 16;
401 }
402
403 uint32_t
404 radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
405 {
406 switch (stage) {
407 case MESA_SHADER_FRAGMENT:
408 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
409 case MESA_SHADER_VERTEX:
410 if (has_tess)
411 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
412 else
413 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
414 case MESA_SHADER_GEOMETRY:
415 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
416 case MESA_SHADER_COMPUTE:
417 return R_00B900_COMPUTE_USER_DATA_0;
418 case MESA_SHADER_TESS_CTRL:
419 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
420 case MESA_SHADER_TESS_EVAL:
421 if (has_gs)
422 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
423 else
424 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
425 default:
426 unreachable("unknown shader");
427 }
428 }
429
430 struct ac_userdata_info *
431 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
432 gl_shader_stage stage,
433 int idx)
434 {
435 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
436 }
437
438 static void
439 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
440 struct radv_pipeline *pipeline,
441 gl_shader_stage stage,
442 int idx, uint64_t va)
443 {
444 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
445 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
446 if (loc->sgpr_idx == -1)
447 return;
448 assert(loc->num_sgprs == 2);
449 assert(!loc->indirect);
450 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
451 radeon_emit(cmd_buffer->cs, va);
452 radeon_emit(cmd_buffer->cs, va >> 32);
453 }
454
455 static void
456 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
457 struct radv_pipeline *pipeline)
458 {
459 int num_samples = pipeline->graphics.ms.num_samples;
460 struct radv_multisample_state *ms = &pipeline->graphics.ms;
461 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
462
463 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
464 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
465 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
466
467 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
468 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
469
470 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
471 return;
472
473 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
474 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
475 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
476
477 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
478
479 /* GFX9: Flush DFSM when the AA mode changes. */
480 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
481 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
482 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
483 }
484 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
485 uint32_t offset;
486 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
487 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
488 if (loc->sgpr_idx == -1)
489 return;
490 assert(loc->num_sgprs == 1);
491 assert(!loc->indirect);
492 switch (num_samples) {
493 default:
494 offset = 0;
495 break;
496 case 2:
497 offset = 1;
498 break;
499 case 4:
500 offset = 3;
501 break;
502 case 8:
503 offset = 7;
504 break;
505 case 16:
506 offset = 15;
507 break;
508 }
509
510 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
511 cmd_buffer->sample_positions_needed = true;
512 }
513 }
514
515 static void
516 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
517 struct radv_pipeline *pipeline)
518 {
519 struct radv_raster_state *raster = &pipeline->graphics.raster;
520
521 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
522 raster->pa_cl_clip_cntl);
523
524 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
525 raster->spi_interp_control);
526
527 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
528 unsigned tmp = (unsigned)(1.0 * 8.0);
529 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
530 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
531 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
532
533 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
534 raster->pa_su_vtx_cntl);
535
536 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
537 raster->pa_su_sc_mode_cntl);
538 }
539
540 static inline void
541 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
542 unsigned size)
543 {
544 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
545 si_cp_dma_prefetch(cmd_buffer, va, size);
546 }
547
548 static void
549 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
550 struct radv_pipeline *pipeline,
551 struct radv_shader_variant *shader,
552 struct ac_vs_output_info *outinfo)
553 {
554 struct radeon_winsys *ws = cmd_buffer->device->ws;
555 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
556 unsigned export_count;
557
558 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
559 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
560
561 export_count = MAX2(1, outinfo->param_exports);
562 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
563 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
564
565 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
566 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
567 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
568 V_02870C_SPI_SHADER_4COMP :
569 V_02870C_SPI_SHADER_NONE) |
570 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
571 V_02870C_SPI_SHADER_4COMP :
572 V_02870C_SPI_SHADER_NONE) |
573 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
574 V_02870C_SPI_SHADER_4COMP :
575 V_02870C_SPI_SHADER_NONE));
576
577
578 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
579 radeon_emit(cmd_buffer->cs, va >> 8);
580 radeon_emit(cmd_buffer->cs, va >> 40);
581 radeon_emit(cmd_buffer->cs, shader->rsrc1);
582 radeon_emit(cmd_buffer->cs, shader->rsrc2);
583
584 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
585 S_028818_VTX_W0_FMT(1) |
586 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
587 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
588 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
589
590
591 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
592 pipeline->graphics.pa_cl_vs_out_cntl);
593
594 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
595 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
596 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
597 }
598
599 static void
600 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
601 struct radv_shader_variant *shader,
602 struct ac_es_output_info *outinfo)
603 {
604 struct radeon_winsys *ws = cmd_buffer->device->ws;
605 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
606
607 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
608 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
609
610 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
611 outinfo->esgs_itemsize / 4);
612 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
613 radeon_emit(cmd_buffer->cs, va >> 8);
614 radeon_emit(cmd_buffer->cs, va >> 40);
615 radeon_emit(cmd_buffer->cs, shader->rsrc1);
616 radeon_emit(cmd_buffer->cs, shader->rsrc2);
617 }
618
619 static void
620 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
621 struct radv_shader_variant *shader)
622 {
623 struct radeon_winsys *ws = cmd_buffer->device->ws;
624 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
625 uint32_t rsrc2 = shader->rsrc2;
626
627 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
628 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
629
630 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
631 radeon_emit(cmd_buffer->cs, va >> 8);
632 radeon_emit(cmd_buffer->cs, va >> 40);
633
634 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
635 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
636 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
637 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
638
639 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
640 radeon_emit(cmd_buffer->cs, shader->rsrc1);
641 radeon_emit(cmd_buffer->cs, rsrc2);
642 }
643
644 static void
645 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
646 struct radv_shader_variant *shader)
647 {
648 struct radeon_winsys *ws = cmd_buffer->device->ws;
649 uint64_t va = ws->buffer_get_va(shader->bo) + shader->bo_offset;
650
651 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
652 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
653
654 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
655 radeon_emit(cmd_buffer->cs, va >> 8);
656 radeon_emit(cmd_buffer->cs, va >> 40);
657 radeon_emit(cmd_buffer->cs, shader->rsrc1);
658 radeon_emit(cmd_buffer->cs, shader->rsrc2);
659 }
660
661 static void
662 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
663 struct radv_pipeline *pipeline)
664 {
665 struct radv_shader_variant *vs;
666
667 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
668
669 vs = pipeline->shaders[MESA_SHADER_VERTEX];
670
671 if (vs->info.vs.as_ls)
672 radv_emit_hw_ls(cmd_buffer, vs);
673 else if (vs->info.vs.as_es)
674 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
675 else
676 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
677
678 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
679 }
680
681
682 static void
683 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
684 struct radv_pipeline *pipeline)
685 {
686 if (!radv_pipeline_has_tess(pipeline))
687 return;
688
689 struct radv_shader_variant *tes, *tcs;
690
691 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
692 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
693
694 if (tes->info.tes.as_es)
695 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
696 else
697 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
698
699 radv_emit_hw_hs(cmd_buffer, tcs);
700
701 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
702 pipeline->graphics.tess.tf_param);
703
704 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
705 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
706 pipeline->graphics.tess.ls_hs_config);
707 else
708 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
709 pipeline->graphics.tess.ls_hs_config);
710
711 struct ac_userdata_info *loc;
712
713 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
714 if (loc->sgpr_idx != -1) {
715 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
716 assert(loc->num_sgprs == 4);
717 assert(!loc->indirect);
718 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
719 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
720 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
721 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
722 pipeline->graphics.tess.num_tcs_input_cp << 26);
723 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
724 }
725
726 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
727 if (loc->sgpr_idx != -1) {
728 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
729 assert(loc->num_sgprs == 1);
730 assert(!loc->indirect);
731
732 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
733 pipeline->graphics.tess.offchip_layout);
734 }
735
736 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
737 if (loc->sgpr_idx != -1) {
738 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
739 assert(loc->num_sgprs == 1);
740 assert(!loc->indirect);
741
742 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
743 pipeline->graphics.tess.tcs_in_layout);
744 }
745 }
746
747 static void
748 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
749 struct radv_pipeline *pipeline)
750 {
751 struct radeon_winsys *ws = cmd_buffer->device->ws;
752 struct radv_shader_variant *gs;
753 uint64_t va;
754
755 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
756
757 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
758 if (!gs)
759 return;
760
761 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
762
763 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
764 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
765 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
766 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
767
768 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
769
770 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
771
772 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
773 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
774 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
775 radeon_emit(cmd_buffer->cs, 0);
776 radeon_emit(cmd_buffer->cs, 0);
777 radeon_emit(cmd_buffer->cs, 0);
778
779 uint32_t gs_num_invocations = gs->info.gs.invocations;
780 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
781 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
782 S_028B90_ENABLE(gs_num_invocations > 0));
783
784 va = ws->buffer_get_va(gs->bo) + gs->bo_offset;
785 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
786 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
787
788 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
789 radeon_emit(cmd_buffer->cs, va >> 8);
790 radeon_emit(cmd_buffer->cs, va >> 40);
791 radeon_emit(cmd_buffer->cs, gs->rsrc1);
792 radeon_emit(cmd_buffer->cs, gs->rsrc2);
793
794 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
795
796 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
797 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
798 if (loc->sgpr_idx != -1) {
799 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
800 uint32_t num_entries = 64;
801 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
802
803 if (is_vi)
804 num_entries *= stride;
805
806 stride = S_008F04_STRIDE(stride);
807 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
808 radeon_emit(cmd_buffer->cs, stride);
809 radeon_emit(cmd_buffer->cs, num_entries);
810 }
811 }
812
813 static void
814 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
815 struct radv_pipeline *pipeline)
816 {
817 struct radeon_winsys *ws = cmd_buffer->device->ws;
818 struct radv_shader_variant *ps;
819 uint64_t va;
820 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
821 struct radv_blend_state *blend = &pipeline->graphics.blend;
822 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
823
824 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
825 va = ws->buffer_get_va(ps->bo) + ps->bo_offset;
826 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
827 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
828
829 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
830 radeon_emit(cmd_buffer->cs, va >> 8);
831 radeon_emit(cmd_buffer->cs, va >> 40);
832 radeon_emit(cmd_buffer->cs, ps->rsrc1);
833 radeon_emit(cmd_buffer->cs, ps->rsrc2);
834
835 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
836 pipeline->graphics.db_shader_control);
837
838 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
839 ps->config.spi_ps_input_ena);
840
841 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
842 ps->config.spi_ps_input_addr);
843
844 if (ps->info.info.ps.force_persample)
845 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
846
847 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
848 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
849
850 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
851
852 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
853 pipeline->graphics.shader_z_format);
854
855 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
856
857 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
858 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
859
860 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
861 /* optimise this? */
862 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
863 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
864 }
865
866 if (pipeline->graphics.ps_input_cntl_num) {
867 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
868 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
869 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
870 }
871 }
872 }
873
874 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
875 struct radv_pipeline *pipeline)
876 {
877 uint32_t vtx_reuse_depth = 30;
878 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
879 return;
880
881 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
882 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
883 vtx_reuse_depth = 14;
884 }
885 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
886 vtx_reuse_depth);
887 }
888
889 static void
890 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
891 struct radv_pipeline *pipeline)
892 {
893 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
894 return;
895
896 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
897 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
898 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
899 radv_update_multisample_state(cmd_buffer, pipeline);
900 radv_emit_vertex_shader(cmd_buffer, pipeline);
901 radv_emit_tess_shaders(cmd_buffer, pipeline);
902 radv_emit_geometry_shader(cmd_buffer, pipeline);
903 radv_emit_fragment_shader(cmd_buffer, pipeline);
904 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
905
906 cmd_buffer->scratch_size_needed =
907 MAX2(cmd_buffer->scratch_size_needed,
908 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
909
910 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
911 S_0286E8_WAVES(pipeline->max_waves) |
912 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
913
914 if (!cmd_buffer->state.emitted_pipeline ||
915 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
916 pipeline->graphics.can_use_guardband)
917 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
918
919 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
920
921 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
922 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
923 } else {
924 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
925 }
926 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
927
928 cmd_buffer->state.emitted_pipeline = pipeline;
929 }
930
931 static void
932 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
933 {
934 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
935 cmd_buffer->state.dynamic.viewport.viewports);
936 }
937
938 static void
939 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
940 {
941 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
942 si_write_scissors(cmd_buffer->cs, 0, count,
943 cmd_buffer->state.dynamic.scissor.scissors,
944 cmd_buffer->state.dynamic.viewport.viewports,
945 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
946 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
947 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
948 }
949
950 static void
951 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
952 int index,
953 struct radv_color_buffer_info *cb)
954 {
955 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
956
957 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
958 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
959 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
960 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
961 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
962 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
963 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
964 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
965 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
966 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
967 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
968 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
969 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
970
971 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
972 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
973 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
974
975 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
976 cb->gfx9_epitch);
977 } else {
978 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
979 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
980 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
981 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
982 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
983 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
984 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
985 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
986 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
987 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
988 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
989 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
990
991 if (is_vi) { /* DCC BASE */
992 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
993 }
994 }
995 }
996
997 static void
998 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
999 struct radv_ds_buffer_info *ds,
1000 struct radv_image *image,
1001 VkImageLayout layout)
1002 {
1003 uint32_t db_z_info = ds->db_z_info;
1004 uint32_t db_stencil_info = ds->db_stencil_info;
1005
1006 if (!radv_layout_has_htile(image, layout,
1007 radv_image_queue_family_mask(image,
1008 cmd_buffer->queue_family_index,
1009 cmd_buffer->queue_family_index))) {
1010 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1011 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1012 }
1013
1014 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1015 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1016
1017
1018 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1019 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1020 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1021 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1022 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1023
1024 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1025 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1026 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1027 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1028 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1029 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1030 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1031 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1032 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1033 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1034 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1035
1036 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1037 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1038 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1039 } else {
1040 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1041
1042 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1043 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1044 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1045 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1046 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1047 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1048 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1049 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1050 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1051 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1052
1053 }
1054
1055 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1056 ds->pa_su_poly_offset_db_fmt_cntl);
1057 }
1058
1059 void
1060 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1061 struct radv_image *image,
1062 VkClearDepthStencilValue ds_clear_value,
1063 VkImageAspectFlags aspects)
1064 {
1065 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1066 va += image->offset + image->clear_value_offset;
1067 unsigned reg_offset = 0, reg_count = 0;
1068
1069 if (!image->surface.htile_size || !aspects)
1070 return;
1071
1072 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1073 ++reg_count;
1074 } else {
1075 ++reg_offset;
1076 va += 4;
1077 }
1078 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1079 ++reg_count;
1080
1081 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1082
1083 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1084 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1085 S_370_WR_CONFIRM(1) |
1086 S_370_ENGINE_SEL(V_370_PFP));
1087 radeon_emit(cmd_buffer->cs, va);
1088 radeon_emit(cmd_buffer->cs, va >> 32);
1089 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1090 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1091 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1092 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1093
1094 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1095 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1096 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1097 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1098 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1099 }
1100
1101 static void
1102 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1103 struct radv_image *image)
1104 {
1105 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1106 va += image->offset + image->clear_value_offset;
1107
1108 if (!image->surface.htile_size)
1109 return;
1110
1111 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1112
1113 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1114 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1115 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1116 COPY_DATA_COUNT_SEL);
1117 radeon_emit(cmd_buffer->cs, va);
1118 radeon_emit(cmd_buffer->cs, va >> 32);
1119 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1120 radeon_emit(cmd_buffer->cs, 0);
1121
1122 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1123 radeon_emit(cmd_buffer->cs, 0);
1124 }
1125
1126 /*
1127 *with DCC some colors don't require CMASK elimiation before being
1128 * used as a texture. This sets a predicate value to determine if the
1129 * cmask eliminate is required.
1130 */
1131 void
1132 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1133 struct radv_image *image,
1134 bool value)
1135 {
1136 uint64_t pred_val = value;
1137 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1138 va += image->offset + image->dcc_pred_offset;
1139
1140 if (!image->surface.dcc_size)
1141 return;
1142
1143 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1144
1145 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1146 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1147 S_370_WR_CONFIRM(1) |
1148 S_370_ENGINE_SEL(V_370_PFP));
1149 radeon_emit(cmd_buffer->cs, va);
1150 radeon_emit(cmd_buffer->cs, va >> 32);
1151 radeon_emit(cmd_buffer->cs, pred_val);
1152 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1153 }
1154
1155 void
1156 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1157 struct radv_image *image,
1158 int idx,
1159 uint32_t color_values[2])
1160 {
1161 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1162 va += image->offset + image->clear_value_offset;
1163
1164 if (!image->cmask.size && !image->surface.dcc_size)
1165 return;
1166
1167 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1168
1169 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1170 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1171 S_370_WR_CONFIRM(1) |
1172 S_370_ENGINE_SEL(V_370_PFP));
1173 radeon_emit(cmd_buffer->cs, va);
1174 radeon_emit(cmd_buffer->cs, va >> 32);
1175 radeon_emit(cmd_buffer->cs, color_values[0]);
1176 radeon_emit(cmd_buffer->cs, color_values[1]);
1177
1178 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1179 radeon_emit(cmd_buffer->cs, color_values[0]);
1180 radeon_emit(cmd_buffer->cs, color_values[1]);
1181 }
1182
1183 static void
1184 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1185 struct radv_image *image,
1186 int idx)
1187 {
1188 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1189 va += image->offset + image->clear_value_offset;
1190
1191 if (!image->cmask.size && !image->surface.dcc_size)
1192 return;
1193
1194 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1195 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1196
1197 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1198 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1199 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1200 COPY_DATA_COUNT_SEL);
1201 radeon_emit(cmd_buffer->cs, va);
1202 radeon_emit(cmd_buffer->cs, va >> 32);
1203 radeon_emit(cmd_buffer->cs, reg >> 2);
1204 radeon_emit(cmd_buffer->cs, 0);
1205
1206 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1207 radeon_emit(cmd_buffer->cs, 0);
1208 }
1209
1210 void
1211 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1212 {
1213 int i;
1214 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1215 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1216
1217 /* this may happen for inherited secondary recording */
1218 if (!framebuffer)
1219 return;
1220
1221 for (i = 0; i < 8; ++i) {
1222 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1223 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1224 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1225 continue;
1226 }
1227
1228 int idx = subpass->color_attachments[i].attachment;
1229 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1230
1231 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1232
1233 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1234 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1235
1236 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1237 }
1238
1239 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1240 int idx = subpass->depth_stencil_attachment.attachment;
1241 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1242 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1243 struct radv_image *image = att->attachment->image;
1244 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1245 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1246 cmd_buffer->queue_family_index,
1247 cmd_buffer->queue_family_index);
1248 /* We currently don't support writing decompressed HTILE */
1249 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1250 radv_layout_is_htile_compressed(image, layout, queue_mask));
1251
1252 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1253
1254 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1255 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1256 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1257 }
1258 radv_load_depth_clear_regs(cmd_buffer, image);
1259 } else {
1260 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1261 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1262 else
1263 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1264
1265 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1266 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1267 }
1268 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1269 S_028208_BR_X(framebuffer->width) |
1270 S_028208_BR_Y(framebuffer->height));
1271
1272 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1273 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1274 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1275 }
1276 }
1277
1278 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1279 {
1280 uint32_t db_count_control;
1281
1282 if(!cmd_buffer->state.active_occlusion_queries) {
1283 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1284 db_count_control = 0;
1285 } else {
1286 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1287 }
1288 } else {
1289 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1290 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1291 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1292 S_028004_ZPASS_ENABLE(1) |
1293 S_028004_SLICE_EVEN_ENABLE(1) |
1294 S_028004_SLICE_ODD_ENABLE(1);
1295 } else {
1296 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1297 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1298 }
1299 }
1300
1301 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1302 }
1303
1304 static void
1305 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1306 {
1307 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1308
1309 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1310 return;
1311
1312 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1313 radv_emit_viewport(cmd_buffer);
1314
1315 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1316 radv_emit_scissor(cmd_buffer);
1317
1318 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1319 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1320 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1321 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1322 }
1323
1324 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1325 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1326 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1327 }
1328
1329 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1330 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1331 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1332 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1333 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1334 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1335 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1336 S_028430_STENCILOPVAL(1));
1337 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1338 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1339 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1340 S_028434_STENCILOPVAL_BF(1));
1341 }
1342
1343 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1344 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1345 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1346 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1347 }
1348
1349 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1350 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1351 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1352 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1353 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1354
1355 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1356 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1357 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1358 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1359 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1360 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1361 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1362 }
1363 }
1364
1365 cmd_buffer->state.dirty = 0;
1366 }
1367
1368 static void
1369 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1370 struct radv_pipeline *pipeline,
1371 int idx,
1372 uint64_t va,
1373 gl_shader_stage stage)
1374 {
1375 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1376 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1377
1378 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1379 return;
1380
1381 assert(!desc_set_loc->indirect);
1382 assert(desc_set_loc->num_sgprs == 2);
1383 radeon_set_sh_reg_seq(cmd_buffer->cs,
1384 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1385 radeon_emit(cmd_buffer->cs, va);
1386 radeon_emit(cmd_buffer->cs, va >> 32);
1387 }
1388
1389 static void
1390 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1391 VkShaderStageFlags stages,
1392 struct radv_descriptor_set *set,
1393 unsigned idx)
1394 {
1395 if (cmd_buffer->state.pipeline) {
1396 radv_foreach_stage(stage, stages) {
1397 if (cmd_buffer->state.pipeline->shaders[stage])
1398 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1399 idx, set->va,
1400 stage);
1401 }
1402 }
1403
1404 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1405 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1406 idx, set->va,
1407 MESA_SHADER_COMPUTE);
1408 }
1409
1410 static void
1411 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1412 {
1413 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1414 uint32_t *ptr = NULL;
1415 unsigned bo_offset;
1416
1417 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1418 &bo_offset,
1419 (void**) &ptr))
1420 return;
1421
1422 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1423 set->va += bo_offset;
1424
1425 memcpy(ptr, set->mapped_ptr, set->size);
1426 }
1427
1428 static void
1429 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1430 {
1431 uint32_t size = MAX_SETS * 2 * 4;
1432 uint32_t offset;
1433 void *ptr;
1434
1435 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1436 256, &offset, &ptr))
1437 return;
1438
1439 for (unsigned i = 0; i < MAX_SETS; i++) {
1440 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1441 uint64_t set_va = 0;
1442 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1443 if (set)
1444 set_va = set->va;
1445 uptr[0] = set_va & 0xffffffff;
1446 uptr[1] = set_va >> 32;
1447 }
1448
1449 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1450 va += offset;
1451
1452 if (cmd_buffer->state.pipeline) {
1453 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1454 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1455 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1456
1457 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1458 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1459 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1460
1461 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1462 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1463 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1464
1465 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1466 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1467 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1468
1469 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1470 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1471 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1472 }
1473
1474 if (cmd_buffer->state.compute_pipeline)
1475 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1476 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1477 }
1478
1479 static void
1480 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1481 VkShaderStageFlags stages)
1482 {
1483 unsigned i;
1484
1485 if (!cmd_buffer->state.descriptors_dirty)
1486 return;
1487
1488 if (cmd_buffer->state.push_descriptors_dirty)
1489 radv_flush_push_descriptors(cmd_buffer);
1490
1491 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1492 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1493 radv_flush_indirect_descriptor_sets(cmd_buffer);
1494 }
1495
1496 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1497 cmd_buffer->cs,
1498 MAX_SETS * MESA_SHADER_STAGES * 4);
1499
1500 for (i = 0; i < MAX_SETS; i++) {
1501 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1502 continue;
1503 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1504 if (!set)
1505 continue;
1506
1507 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1508 }
1509 cmd_buffer->state.descriptors_dirty = 0;
1510 cmd_buffer->state.push_descriptors_dirty = false;
1511 assert(cmd_buffer->cs->cdw <= cdw_max);
1512 }
1513
1514 static void
1515 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1516 struct radv_pipeline *pipeline,
1517 VkShaderStageFlags stages)
1518 {
1519 struct radv_pipeline_layout *layout = pipeline->layout;
1520 unsigned offset;
1521 void *ptr;
1522 uint64_t va;
1523
1524 stages &= cmd_buffer->push_constant_stages;
1525 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1526 return;
1527
1528 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1529 16 * layout->dynamic_offset_count,
1530 256, &offset, &ptr))
1531 return;
1532
1533 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1534 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1535 16 * layout->dynamic_offset_count);
1536
1537 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1538 va += offset;
1539
1540 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1541 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1542
1543 radv_foreach_stage(stage, stages) {
1544 if (pipeline->shaders[stage]) {
1545 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1546 AC_UD_PUSH_CONSTANTS, va);
1547 }
1548 }
1549
1550 cmd_buffer->push_constant_stages &= ~stages;
1551 assert(cmd_buffer->cs->cdw <= cdw_max);
1552 }
1553
1554 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1555 bool indexed_draw)
1556 {
1557 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1558
1559 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1560 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1561 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1562 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1563 primitive_reset_en);
1564 } else {
1565 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1566 primitive_reset_en);
1567 }
1568 }
1569
1570 if (primitive_reset_en) {
1571 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1572
1573 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1574 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1575 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1576 primitive_reset_index);
1577 }
1578 }
1579 }
1580
1581 static void
1582 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1583 {
1584 struct radv_device *device = cmd_buffer->device;
1585
1586 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1587 cmd_buffer->state.pipeline->num_vertex_attribs &&
1588 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1589 unsigned vb_offset;
1590 void *vb_ptr;
1591 uint32_t i = 0;
1592 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1593 uint64_t va;
1594
1595 /* allocate some descriptor state for vertex buffers */
1596 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1597 &vb_offset, &vb_ptr);
1598
1599 for (i = 0; i < num_attribs; i++) {
1600 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1601 uint32_t offset;
1602 int vb = cmd_buffer->state.pipeline->va_binding[i];
1603 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1604 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1605
1606 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1607 va = device->ws->buffer_get_va(buffer->bo);
1608
1609 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1610 va += offset + buffer->offset;
1611 desc[0] = va;
1612 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1613 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1614 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1615 else
1616 desc[2] = buffer->size - offset;
1617 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1618 }
1619
1620 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1621 va += vb_offset;
1622
1623 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1624 AC_UD_VS_VERTEX_BUFFERS, va);
1625 }
1626 cmd_buffer->state.vb_dirty = 0;
1627 }
1628
1629 static void
1630 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1631 bool indexed_draw, bool instanced_draw,
1632 bool indirect_draw,
1633 uint32_t draw_vertex_count)
1634 {
1635 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1636 uint32_t ia_multi_vgt_param;
1637
1638 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1639 cmd_buffer->cs, 4096);
1640
1641 radv_cmd_buffer_update_vertex_descriptors(cmd_buffer);
1642
1643 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1644 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1645
1646 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1647 radv_emit_framebuffer_state(cmd_buffer);
1648
1649 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1650 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1651 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1652 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1653 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1654 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1655 else
1656 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1657 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1658 }
1659
1660 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1661
1662 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1663
1664 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1665 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1666 VK_SHADER_STAGE_ALL_GRAPHICS);
1667
1668 assert(cmd_buffer->cs->cdw <= cdw_max);
1669
1670 si_emit_cache_flush(cmd_buffer);
1671 }
1672
1673 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1674 VkPipelineStageFlags src_stage_mask)
1675 {
1676 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1677 VK_PIPELINE_STAGE_TRANSFER_BIT |
1678 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1679 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1680 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1681 }
1682
1683 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1684 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1685 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1686 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1687 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1688 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1689 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1690 VK_PIPELINE_STAGE_TRANSFER_BIT |
1691 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1692 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1693 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1694 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1695 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1696 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1697 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1698 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1699 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1700 }
1701 }
1702
1703 static enum radv_cmd_flush_bits
1704 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1705 VkAccessFlags src_flags)
1706 {
1707 enum radv_cmd_flush_bits flush_bits = 0;
1708 uint32_t b;
1709 for_each_bit(b, src_flags) {
1710 switch ((VkAccessFlagBits)(1 << b)) {
1711 case VK_ACCESS_SHADER_WRITE_BIT:
1712 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1713 break;
1714 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1715 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1716 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1717 break;
1718 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1719 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1720 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1721 break;
1722 case VK_ACCESS_TRANSFER_WRITE_BIT:
1723 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1724 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1725 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1726 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1727 RADV_CMD_FLAG_INV_GLOBAL_L2;
1728 break;
1729 default:
1730 break;
1731 }
1732 }
1733 return flush_bits;
1734 }
1735
1736 static enum radv_cmd_flush_bits
1737 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1738 VkAccessFlags dst_flags,
1739 struct radv_image *image)
1740 {
1741 enum radv_cmd_flush_bits flush_bits = 0;
1742 uint32_t b;
1743 for_each_bit(b, dst_flags) {
1744 switch ((VkAccessFlagBits)(1 << b)) {
1745 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1746 case VK_ACCESS_INDEX_READ_BIT:
1747 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1748 break;
1749 case VK_ACCESS_UNIFORM_READ_BIT:
1750 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1751 break;
1752 case VK_ACCESS_SHADER_READ_BIT:
1753 case VK_ACCESS_TRANSFER_READ_BIT:
1754 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1755 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1756 RADV_CMD_FLAG_INV_GLOBAL_L2;
1757 break;
1758 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1759 /* TODO: change to image && when the image gets passed
1760 * through from the subpass. */
1761 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1762 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1763 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1764 break;
1765 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1766 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1767 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1768 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1769 break;
1770 default:
1771 break;
1772 }
1773 }
1774 return flush_bits;
1775 }
1776
1777 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1778 {
1779 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1780 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1781 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1782 NULL);
1783 }
1784
1785 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1786 VkAttachmentReference att)
1787 {
1788 unsigned idx = att.attachment;
1789 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1790 VkImageSubresourceRange range;
1791 range.aspectMask = 0;
1792 range.baseMipLevel = view->base_mip;
1793 range.levelCount = 1;
1794 range.baseArrayLayer = view->base_layer;
1795 range.layerCount = cmd_buffer->state.framebuffer->layers;
1796
1797 radv_handle_image_transition(cmd_buffer,
1798 view->image,
1799 cmd_buffer->state.attachments[idx].current_layout,
1800 att.layout, 0, 0, &range,
1801 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1802
1803 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1804
1805
1806 }
1807
1808 void
1809 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1810 const struct radv_subpass *subpass, bool transitions)
1811 {
1812 if (transitions) {
1813 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1814
1815 for (unsigned i = 0; i < subpass->color_count; ++i) {
1816 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1817 radv_handle_subpass_image_transition(cmd_buffer,
1818 subpass->color_attachments[i]);
1819 }
1820
1821 for (unsigned i = 0; i < subpass->input_count; ++i) {
1822 radv_handle_subpass_image_transition(cmd_buffer,
1823 subpass->input_attachments[i]);
1824 }
1825
1826 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1827 radv_handle_subpass_image_transition(cmd_buffer,
1828 subpass->depth_stencil_attachment);
1829 }
1830 }
1831
1832 cmd_buffer->state.subpass = subpass;
1833
1834 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1835 }
1836
1837 static VkResult
1838 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1839 struct radv_render_pass *pass,
1840 const VkRenderPassBeginInfo *info)
1841 {
1842 struct radv_cmd_state *state = &cmd_buffer->state;
1843
1844 if (pass->attachment_count == 0) {
1845 state->attachments = NULL;
1846 return VK_SUCCESS;
1847 }
1848
1849 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1850 pass->attachment_count *
1851 sizeof(state->attachments[0]),
1852 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1853 if (state->attachments == NULL) {
1854 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1855 return cmd_buffer->record_result;
1856 }
1857
1858 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1859 struct radv_render_pass_attachment *att = &pass->attachments[i];
1860 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1861 VkImageAspectFlags clear_aspects = 0;
1862
1863 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1864 /* color attachment */
1865 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1866 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1867 }
1868 } else {
1869 /* depthstencil attachment */
1870 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1871 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1872 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1873 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1874 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1875 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1876 }
1877 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1878 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1879 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1880 }
1881 }
1882
1883 state->attachments[i].pending_clear_aspects = clear_aspects;
1884 state->attachments[i].cleared_views = 0;
1885 if (clear_aspects && info) {
1886 assert(info->clearValueCount > i);
1887 state->attachments[i].clear_value = info->pClearValues[i];
1888 }
1889
1890 state->attachments[i].current_layout = att->initial_layout;
1891 }
1892
1893 return VK_SUCCESS;
1894 }
1895
1896 VkResult radv_AllocateCommandBuffers(
1897 VkDevice _device,
1898 const VkCommandBufferAllocateInfo *pAllocateInfo,
1899 VkCommandBuffer *pCommandBuffers)
1900 {
1901 RADV_FROM_HANDLE(radv_device, device, _device);
1902 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1903
1904 VkResult result = VK_SUCCESS;
1905 uint32_t i;
1906
1907 memset(pCommandBuffers, 0,
1908 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1909
1910 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1911
1912 if (!list_empty(&pool->free_cmd_buffers)) {
1913 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1914
1915 list_del(&cmd_buffer->pool_link);
1916 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1917
1918 radv_reset_cmd_buffer(cmd_buffer);
1919 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1920 cmd_buffer->level = pAllocateInfo->level;
1921
1922 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1923 result = VK_SUCCESS;
1924 } else {
1925 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1926 &pCommandBuffers[i]);
1927 }
1928 if (result != VK_SUCCESS)
1929 break;
1930 }
1931
1932 if (result != VK_SUCCESS)
1933 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1934 i, pCommandBuffers);
1935
1936 return result;
1937 }
1938
1939 void radv_FreeCommandBuffers(
1940 VkDevice device,
1941 VkCommandPool commandPool,
1942 uint32_t commandBufferCount,
1943 const VkCommandBuffer *pCommandBuffers)
1944 {
1945 for (uint32_t i = 0; i < commandBufferCount; i++) {
1946 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1947
1948 if (cmd_buffer) {
1949 if (cmd_buffer->pool) {
1950 list_del(&cmd_buffer->pool_link);
1951 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1952 } else
1953 radv_cmd_buffer_destroy(cmd_buffer);
1954
1955 }
1956 }
1957 }
1958
1959 VkResult radv_ResetCommandBuffer(
1960 VkCommandBuffer commandBuffer,
1961 VkCommandBufferResetFlags flags)
1962 {
1963 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1964 radv_reset_cmd_buffer(cmd_buffer);
1965 return VK_SUCCESS;
1966 }
1967
1968 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1969 {
1970 struct radv_device *device = cmd_buffer->device;
1971 if (device->gfx_init) {
1972 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1973 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1974 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1975 radeon_emit(cmd_buffer->cs, va);
1976 radeon_emit(cmd_buffer->cs, va >> 32);
1977 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1978 } else
1979 si_init_config(cmd_buffer);
1980 }
1981
1982 VkResult radv_BeginCommandBuffer(
1983 VkCommandBuffer commandBuffer,
1984 const VkCommandBufferBeginInfo *pBeginInfo)
1985 {
1986 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1987 VkResult result = VK_SUCCESS;
1988
1989 radv_reset_cmd_buffer(cmd_buffer);
1990
1991 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1992 cmd_buffer->state.last_primitive_reset_en = -1;
1993 cmd_buffer->usage_flags = pBeginInfo->flags;
1994
1995 /* setup initial configuration into command buffer */
1996 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1997 switch (cmd_buffer->queue_family_index) {
1998 case RADV_QUEUE_GENERAL:
1999 emit_gfx_buffer_state(cmd_buffer);
2000 radv_set_db_count_control(cmd_buffer);
2001 break;
2002 case RADV_QUEUE_COMPUTE:
2003 si_init_compute(cmd_buffer);
2004 break;
2005 case RADV_QUEUE_TRANSFER:
2006 default:
2007 break;
2008 }
2009 }
2010
2011 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2012 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2013 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2014
2015 struct radv_subpass *subpass =
2016 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2017
2018 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2019 if (result != VK_SUCCESS)
2020 return result;
2021
2022 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2023 }
2024
2025 radv_cmd_buffer_trace_emit(cmd_buffer);
2026 return result;
2027 }
2028
2029 void radv_CmdBindVertexBuffers(
2030 VkCommandBuffer commandBuffer,
2031 uint32_t firstBinding,
2032 uint32_t bindingCount,
2033 const VkBuffer* pBuffers,
2034 const VkDeviceSize* pOffsets)
2035 {
2036 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2037 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2038
2039 /* We have to defer setting up vertex buffer since we need the buffer
2040 * stride from the pipeline. */
2041
2042 assert(firstBinding + bindingCount <= MAX_VBS);
2043 for (uint32_t i = 0; i < bindingCount; i++) {
2044 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2045 vb[firstBinding + i].offset = pOffsets[i];
2046 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
2047 }
2048 }
2049
2050 void radv_CmdBindIndexBuffer(
2051 VkCommandBuffer commandBuffer,
2052 VkBuffer buffer,
2053 VkDeviceSize offset,
2054 VkIndexType indexType)
2055 {
2056 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2057 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2058
2059 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2060 cmd_buffer->state.index_va = cmd_buffer->device->ws->buffer_get_va(index_buffer->bo);
2061 cmd_buffer->state.index_va += index_buffer->offset + offset;
2062
2063 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2064 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2065 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2066 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2067 }
2068
2069
2070 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2071 struct radv_descriptor_set *set,
2072 unsigned idx)
2073 {
2074 struct radeon_winsys *ws = cmd_buffer->device->ws;
2075
2076 cmd_buffer->state.descriptors[idx] = set;
2077 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2078 if (!set)
2079 return;
2080
2081 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2082
2083 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2084 if (set->descriptors[j])
2085 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2086
2087 if(set->bo)
2088 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2089 }
2090
2091 void radv_CmdBindDescriptorSets(
2092 VkCommandBuffer commandBuffer,
2093 VkPipelineBindPoint pipelineBindPoint,
2094 VkPipelineLayout _layout,
2095 uint32_t firstSet,
2096 uint32_t descriptorSetCount,
2097 const VkDescriptorSet* pDescriptorSets,
2098 uint32_t dynamicOffsetCount,
2099 const uint32_t* pDynamicOffsets)
2100 {
2101 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2102 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2103 unsigned dyn_idx = 0;
2104
2105 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2106 unsigned idx = i + firstSet;
2107 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2108 radv_bind_descriptor_set(cmd_buffer, set, idx);
2109
2110 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2111 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2112 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2113 assert(dyn_idx < dynamicOffsetCount);
2114
2115 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2116 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2117 dst[0] = va;
2118 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2119 dst[2] = range->size;
2120 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2121 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2122 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2123 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2124 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2125 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2126 cmd_buffer->push_constant_stages |=
2127 set->layout->dynamic_shader_stages;
2128 }
2129 }
2130 }
2131
2132 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2133 struct radv_descriptor_set *set,
2134 struct radv_descriptor_set_layout *layout)
2135 {
2136 set->size = layout->size;
2137 set->layout = layout;
2138
2139 if (cmd_buffer->push_descriptors.capacity < set->size) {
2140 size_t new_size = MAX2(set->size, 1024);
2141 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2142 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2143
2144 free(set->mapped_ptr);
2145 set->mapped_ptr = malloc(new_size);
2146
2147 if (!set->mapped_ptr) {
2148 cmd_buffer->push_descriptors.capacity = 0;
2149 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2150 return false;
2151 }
2152
2153 cmd_buffer->push_descriptors.capacity = new_size;
2154 }
2155
2156 return true;
2157 }
2158
2159 void radv_meta_push_descriptor_set(
2160 struct radv_cmd_buffer* cmd_buffer,
2161 VkPipelineBindPoint pipelineBindPoint,
2162 VkPipelineLayout _layout,
2163 uint32_t set,
2164 uint32_t descriptorWriteCount,
2165 const VkWriteDescriptorSet* pDescriptorWrites)
2166 {
2167 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2168 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2169 unsigned bo_offset;
2170
2171 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2172
2173 push_set->size = layout->set[set].layout->size;
2174 push_set->layout = layout->set[set].layout;
2175
2176 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2177 &bo_offset,
2178 (void**) &push_set->mapped_ptr))
2179 return;
2180
2181 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2182 push_set->va += bo_offset;
2183
2184 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2185 radv_descriptor_set_to_handle(push_set),
2186 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2187
2188 cmd_buffer->state.descriptors[set] = push_set;
2189 cmd_buffer->state.descriptors_dirty |= (1u << set);
2190 }
2191
2192 void radv_CmdPushDescriptorSetKHR(
2193 VkCommandBuffer commandBuffer,
2194 VkPipelineBindPoint pipelineBindPoint,
2195 VkPipelineLayout _layout,
2196 uint32_t set,
2197 uint32_t descriptorWriteCount,
2198 const VkWriteDescriptorSet* pDescriptorWrites)
2199 {
2200 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2201 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2202 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2203
2204 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2205
2206 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2207 return;
2208
2209 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2210 radv_descriptor_set_to_handle(push_set),
2211 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2212
2213 cmd_buffer->state.descriptors[set] = push_set;
2214 cmd_buffer->state.descriptors_dirty |= (1u << set);
2215 cmd_buffer->state.push_descriptors_dirty = true;
2216 }
2217
2218 void radv_CmdPushDescriptorSetWithTemplateKHR(
2219 VkCommandBuffer commandBuffer,
2220 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2221 VkPipelineLayout _layout,
2222 uint32_t set,
2223 const void* pData)
2224 {
2225 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2226 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2227 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2228
2229 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2230
2231 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2232 return;
2233
2234 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2235 descriptorUpdateTemplate, pData);
2236
2237 cmd_buffer->state.descriptors[set] = push_set;
2238 cmd_buffer->state.descriptors_dirty |= (1u << set);
2239 cmd_buffer->state.push_descriptors_dirty = true;
2240 }
2241
2242 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2243 VkPipelineLayout layout,
2244 VkShaderStageFlags stageFlags,
2245 uint32_t offset,
2246 uint32_t size,
2247 const void* pValues)
2248 {
2249 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2250 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2251 cmd_buffer->push_constant_stages |= stageFlags;
2252 }
2253
2254 VkResult radv_EndCommandBuffer(
2255 VkCommandBuffer commandBuffer)
2256 {
2257 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2258
2259 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2260 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2261 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2262 si_emit_cache_flush(cmd_buffer);
2263 }
2264
2265 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2266 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2267
2268 return cmd_buffer->record_result;
2269 }
2270
2271 static void
2272 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2273 {
2274 struct radeon_winsys *ws = cmd_buffer->device->ws;
2275 struct radv_shader_variant *compute_shader;
2276 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2277 uint64_t va;
2278
2279 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2280 return;
2281
2282 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2283
2284 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2285 va = ws->buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2286
2287 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2288 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2289
2290 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2291 cmd_buffer->cs, 16);
2292
2293 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2294 radeon_emit(cmd_buffer->cs, va >> 8);
2295 radeon_emit(cmd_buffer->cs, va >> 40);
2296
2297 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2298 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2299 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2300
2301
2302 cmd_buffer->compute_scratch_size_needed =
2303 MAX2(cmd_buffer->compute_scratch_size_needed,
2304 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2305
2306 /* change these once we have scratch support */
2307 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2308 S_00B860_WAVES(pipeline->max_waves) |
2309 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2310
2311 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2312 radeon_emit(cmd_buffer->cs,
2313 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2314 radeon_emit(cmd_buffer->cs,
2315 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2316 radeon_emit(cmd_buffer->cs,
2317 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2318
2319 assert(cmd_buffer->cs->cdw <= cdw_max);
2320 }
2321
2322 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2323 {
2324 for (unsigned i = 0; i < MAX_SETS; i++) {
2325 if (cmd_buffer->state.descriptors[i])
2326 cmd_buffer->state.descriptors_dirty |= (1u << i);
2327 }
2328 }
2329
2330 void radv_CmdBindPipeline(
2331 VkCommandBuffer commandBuffer,
2332 VkPipelineBindPoint pipelineBindPoint,
2333 VkPipeline _pipeline)
2334 {
2335 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2336 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2337
2338 radv_mark_descriptor_sets_dirty(cmd_buffer);
2339
2340 switch (pipelineBindPoint) {
2341 case VK_PIPELINE_BIND_POINT_COMPUTE:
2342 cmd_buffer->state.compute_pipeline = pipeline;
2343 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2344 break;
2345 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2346 cmd_buffer->state.pipeline = pipeline;
2347 if (!pipeline)
2348 break;
2349
2350 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2351 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2352
2353 /* Apply the dynamic state from the pipeline */
2354 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2355 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2356 &pipeline->dynamic_state,
2357 pipeline->dynamic_state_mask);
2358
2359 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2360 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2361 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2362 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2363
2364 if (radv_pipeline_has_tess(pipeline))
2365 cmd_buffer->tess_rings_needed = true;
2366
2367 if (radv_pipeline_has_gs(pipeline)) {
2368 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2369 AC_UD_SCRATCH_RING_OFFSETS);
2370 if (cmd_buffer->ring_offsets_idx == -1)
2371 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2372 else if (loc->sgpr_idx != -1)
2373 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2374 }
2375 break;
2376 default:
2377 assert(!"invalid bind point");
2378 break;
2379 }
2380 }
2381
2382 void radv_CmdSetViewport(
2383 VkCommandBuffer commandBuffer,
2384 uint32_t firstViewport,
2385 uint32_t viewportCount,
2386 const VkViewport* pViewports)
2387 {
2388 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2389
2390 const uint32_t total_count = firstViewport + viewportCount;
2391 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2392 cmd_buffer->state.dynamic.viewport.count = total_count;
2393
2394 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2395 pViewports, viewportCount * sizeof(*pViewports));
2396
2397 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2398 }
2399
2400 void radv_CmdSetScissor(
2401 VkCommandBuffer commandBuffer,
2402 uint32_t firstScissor,
2403 uint32_t scissorCount,
2404 const VkRect2D* pScissors)
2405 {
2406 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2407
2408 const uint32_t total_count = firstScissor + scissorCount;
2409 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2410 cmd_buffer->state.dynamic.scissor.count = total_count;
2411
2412 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2413 pScissors, scissorCount * sizeof(*pScissors));
2414 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2415 }
2416
2417 void radv_CmdSetLineWidth(
2418 VkCommandBuffer commandBuffer,
2419 float lineWidth)
2420 {
2421 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2422 cmd_buffer->state.dynamic.line_width = lineWidth;
2423 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2424 }
2425
2426 void radv_CmdSetDepthBias(
2427 VkCommandBuffer commandBuffer,
2428 float depthBiasConstantFactor,
2429 float depthBiasClamp,
2430 float depthBiasSlopeFactor)
2431 {
2432 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2433
2434 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2435 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2436 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2437
2438 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2439 }
2440
2441 void radv_CmdSetBlendConstants(
2442 VkCommandBuffer commandBuffer,
2443 const float blendConstants[4])
2444 {
2445 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2446
2447 memcpy(cmd_buffer->state.dynamic.blend_constants,
2448 blendConstants, sizeof(float) * 4);
2449
2450 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2451 }
2452
2453 void radv_CmdSetDepthBounds(
2454 VkCommandBuffer commandBuffer,
2455 float minDepthBounds,
2456 float maxDepthBounds)
2457 {
2458 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2459
2460 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2461 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2462
2463 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2464 }
2465
2466 void radv_CmdSetStencilCompareMask(
2467 VkCommandBuffer commandBuffer,
2468 VkStencilFaceFlags faceMask,
2469 uint32_t compareMask)
2470 {
2471 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2472
2473 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2474 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2475 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2476 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2477
2478 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2479 }
2480
2481 void radv_CmdSetStencilWriteMask(
2482 VkCommandBuffer commandBuffer,
2483 VkStencilFaceFlags faceMask,
2484 uint32_t writeMask)
2485 {
2486 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2487
2488 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2489 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2490 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2491 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2492
2493 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2494 }
2495
2496 void radv_CmdSetStencilReference(
2497 VkCommandBuffer commandBuffer,
2498 VkStencilFaceFlags faceMask,
2499 uint32_t reference)
2500 {
2501 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2502
2503 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2504 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2505 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2506 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2507
2508 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2509 }
2510
2511 void radv_CmdExecuteCommands(
2512 VkCommandBuffer commandBuffer,
2513 uint32_t commandBufferCount,
2514 const VkCommandBuffer* pCmdBuffers)
2515 {
2516 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2517
2518 /* Emit pending flushes on primary prior to executing secondary */
2519 si_emit_cache_flush(primary);
2520
2521 for (uint32_t i = 0; i < commandBufferCount; i++) {
2522 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2523
2524 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2525 secondary->scratch_size_needed);
2526 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2527 secondary->compute_scratch_size_needed);
2528
2529 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2530 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2531 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2532 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2533 if (secondary->tess_rings_needed)
2534 primary->tess_rings_needed = true;
2535 if (secondary->sample_positions_needed)
2536 primary->sample_positions_needed = true;
2537
2538 if (secondary->ring_offsets_idx != -1) {
2539 if (primary->ring_offsets_idx == -1)
2540 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2541 else
2542 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2543 }
2544 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2545 }
2546
2547 /* if we execute secondary we need to re-emit out pipelines */
2548 if (commandBufferCount) {
2549 primary->state.emitted_pipeline = NULL;
2550 primary->state.emitted_compute_pipeline = NULL;
2551 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2552 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2553 primary->state.last_primitive_reset_en = -1;
2554 primary->state.last_primitive_reset_index = 0;
2555 radv_mark_descriptor_sets_dirty(primary);
2556 }
2557 }
2558
2559 VkResult radv_CreateCommandPool(
2560 VkDevice _device,
2561 const VkCommandPoolCreateInfo* pCreateInfo,
2562 const VkAllocationCallbacks* pAllocator,
2563 VkCommandPool* pCmdPool)
2564 {
2565 RADV_FROM_HANDLE(radv_device, device, _device);
2566 struct radv_cmd_pool *pool;
2567
2568 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2569 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2570 if (pool == NULL)
2571 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2572
2573 if (pAllocator)
2574 pool->alloc = *pAllocator;
2575 else
2576 pool->alloc = device->alloc;
2577
2578 list_inithead(&pool->cmd_buffers);
2579 list_inithead(&pool->free_cmd_buffers);
2580
2581 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2582
2583 *pCmdPool = radv_cmd_pool_to_handle(pool);
2584
2585 return VK_SUCCESS;
2586
2587 }
2588
2589 void radv_DestroyCommandPool(
2590 VkDevice _device,
2591 VkCommandPool commandPool,
2592 const VkAllocationCallbacks* pAllocator)
2593 {
2594 RADV_FROM_HANDLE(radv_device, device, _device);
2595 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2596
2597 if (!pool)
2598 return;
2599
2600 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2601 &pool->cmd_buffers, pool_link) {
2602 radv_cmd_buffer_destroy(cmd_buffer);
2603 }
2604
2605 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2606 &pool->free_cmd_buffers, pool_link) {
2607 radv_cmd_buffer_destroy(cmd_buffer);
2608 }
2609
2610 vk_free2(&device->alloc, pAllocator, pool);
2611 }
2612
2613 VkResult radv_ResetCommandPool(
2614 VkDevice device,
2615 VkCommandPool commandPool,
2616 VkCommandPoolResetFlags flags)
2617 {
2618 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2619
2620 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2621 &pool->cmd_buffers, pool_link) {
2622 radv_reset_cmd_buffer(cmd_buffer);
2623 }
2624
2625 return VK_SUCCESS;
2626 }
2627
2628 void radv_TrimCommandPoolKHR(
2629 VkDevice device,
2630 VkCommandPool commandPool,
2631 VkCommandPoolTrimFlagsKHR flags)
2632 {
2633 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2634
2635 if (!pool)
2636 return;
2637
2638 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2639 &pool->free_cmd_buffers, pool_link) {
2640 radv_cmd_buffer_destroy(cmd_buffer);
2641 }
2642 }
2643
2644 void radv_CmdBeginRenderPass(
2645 VkCommandBuffer commandBuffer,
2646 const VkRenderPassBeginInfo* pRenderPassBegin,
2647 VkSubpassContents contents)
2648 {
2649 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2650 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2651 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2652
2653 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2654 cmd_buffer->cs, 2048);
2655 MAYBE_UNUSED VkResult result;
2656
2657 cmd_buffer->state.framebuffer = framebuffer;
2658 cmd_buffer->state.pass = pass;
2659 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2660 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2661 if (result != VK_SUCCESS)
2662 cmd_buffer->record_result = result;
2663
2664 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2665 assert(cmd_buffer->cs->cdw <= cdw_max);
2666
2667 radv_cmd_buffer_clear_subpass(cmd_buffer);
2668 }
2669
2670 void radv_CmdNextSubpass(
2671 VkCommandBuffer commandBuffer,
2672 VkSubpassContents contents)
2673 {
2674 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2675
2676 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2677
2678 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2679 2048);
2680
2681 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2682 radv_cmd_buffer_clear_subpass(cmd_buffer);
2683 }
2684
2685 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2686 {
2687 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2688 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2689 if (!pipeline->shaders[stage])
2690 continue;
2691 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2692 if (loc->sgpr_idx == -1)
2693 continue;
2694 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2695 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2696
2697 }
2698 if (pipeline->gs_copy_shader) {
2699 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2700 if (loc->sgpr_idx != -1) {
2701 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2702 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2703 }
2704 }
2705 }
2706
2707 static void
2708 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2709 uint32_t vertex_count)
2710 {
2711 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2712 radeon_emit(cmd_buffer->cs, vertex_count);
2713 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2714 S_0287F0_USE_OPAQUE(0));
2715 }
2716
2717 void radv_CmdDraw(
2718 VkCommandBuffer commandBuffer,
2719 uint32_t vertexCount,
2720 uint32_t instanceCount,
2721 uint32_t firstVertex,
2722 uint32_t firstInstance)
2723 {
2724 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2725
2726 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2727
2728 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 20 * MAX_VIEWS);
2729
2730 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2731 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2732 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2733 radeon_emit(cmd_buffer->cs, firstVertex);
2734 radeon_emit(cmd_buffer->cs, firstInstance);
2735 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2736 radeon_emit(cmd_buffer->cs, 0);
2737
2738 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
2739 radeon_emit(cmd_buffer->cs, instanceCount);
2740
2741 if (!cmd_buffer->state.subpass->view_mask) {
2742 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2743 } else {
2744 unsigned i;
2745 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2746 radv_emit_view_index(cmd_buffer, i);
2747
2748 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2749 }
2750 }
2751
2752 assert(cmd_buffer->cs->cdw <= cdw_max);
2753
2754 radv_cmd_buffer_trace_emit(cmd_buffer);
2755 }
2756
2757
2758 static void
2759 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2760 uint64_t index_va,
2761 uint32_t index_count)
2762 {
2763 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2764 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2765 radeon_emit(cmd_buffer->cs, index_va);
2766 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2767 radeon_emit(cmd_buffer->cs, index_count);
2768 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2769 }
2770
2771 void radv_CmdDrawIndexed(
2772 VkCommandBuffer commandBuffer,
2773 uint32_t indexCount,
2774 uint32_t instanceCount,
2775 uint32_t firstIndex,
2776 int32_t vertexOffset,
2777 uint32_t firstInstance)
2778 {
2779 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2780 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2781 uint64_t index_va;
2782
2783 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2784
2785 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 26 * MAX_VIEWS);
2786
2787 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2788 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
2789 2, cmd_buffer->state.index_type);
2790 } else {
2791 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2792 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2793 }
2794
2795 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2796 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2797 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2798 radeon_emit(cmd_buffer->cs, vertexOffset);
2799 radeon_emit(cmd_buffer->cs, firstInstance);
2800 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2801 radeon_emit(cmd_buffer->cs, 0);
2802
2803 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2804 radeon_emit(cmd_buffer->cs, instanceCount);
2805
2806 index_va = cmd_buffer->state.index_va;
2807 index_va += firstIndex * index_size;
2808 if (!cmd_buffer->state.subpass->view_mask) {
2809 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2810 } else {
2811 unsigned i;
2812 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2813 radv_emit_view_index(cmd_buffer, i);
2814
2815 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2816 }
2817 }
2818
2819 assert(cmd_buffer->cs->cdw <= cdw_max);
2820 radv_cmd_buffer_trace_emit(cmd_buffer);
2821 }
2822
2823 static void
2824 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2825 bool indexed,
2826 uint32_t draw_count,
2827 uint64_t count_va,
2828 uint32_t stride)
2829 {
2830 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2831 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2832 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2833 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2834 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2835 assert(base_reg);
2836
2837 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2838 PKT3_DRAW_INDIRECT_MULTI,
2839 8, false));
2840 radeon_emit(cs, 0);
2841 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2842 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2843 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2844 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2845 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2846 radeon_emit(cs, draw_count); /* count */
2847 radeon_emit(cs, count_va); /* count_addr */
2848 radeon_emit(cs, count_va >> 32);
2849 radeon_emit(cs, stride); /* stride */
2850 radeon_emit(cs, di_src_sel);
2851 }
2852
2853 static void
2854 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2855 VkBuffer _buffer,
2856 VkDeviceSize offset,
2857 VkBuffer _count_buffer,
2858 VkDeviceSize count_offset,
2859 uint32_t draw_count,
2860 uint32_t stride,
2861 bool indexed)
2862 {
2863 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2864 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2865 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2866
2867 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2868 indirect_va += offset + buffer->offset;
2869 uint64_t count_va = 0;
2870
2871 if (count_buffer) {
2872 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2873 count_va += count_offset + count_buffer->offset;
2874 }
2875
2876 if (!draw_count)
2877 return;
2878
2879 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2880
2881 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2882 radeon_emit(cs, 1);
2883 radeon_emit(cs, indirect_va);
2884 radeon_emit(cs, indirect_va >> 32);
2885
2886 if (!cmd_buffer->state.subpass->view_mask) {
2887 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
2888 } else {
2889 unsigned i;
2890 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2891 radv_emit_view_index(cmd_buffer, i);
2892
2893 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
2894 }
2895 }
2896 radv_cmd_buffer_trace_emit(cmd_buffer);
2897 }
2898
2899 static void
2900 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2901 VkBuffer buffer,
2902 VkDeviceSize offset,
2903 VkBuffer countBuffer,
2904 VkDeviceSize countBufferOffset,
2905 uint32_t maxDrawCount,
2906 uint32_t stride)
2907 {
2908 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2909 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2910
2911 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2912 cmd_buffer->cs, 24 * MAX_VIEWS);
2913
2914 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2915 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2916
2917 assert(cmd_buffer->cs->cdw <= cdw_max);
2918 }
2919
2920 static void
2921 radv_cmd_draw_indexed_indirect_count(
2922 VkCommandBuffer commandBuffer,
2923 VkBuffer buffer,
2924 VkDeviceSize offset,
2925 VkBuffer countBuffer,
2926 VkDeviceSize countBufferOffset,
2927 uint32_t maxDrawCount,
2928 uint32_t stride)
2929 {
2930 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2931 uint64_t index_va;
2932 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2933
2934 index_va = cmd_buffer->state.index_va;
2935
2936 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 31 * MAX_VIEWS);
2937
2938 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2939 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2940
2941 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2942 radeon_emit(cmd_buffer->cs, index_va);
2943 radeon_emit(cmd_buffer->cs, index_va >> 32);
2944
2945 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2946 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2947
2948 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2949 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2950
2951 assert(cmd_buffer->cs->cdw <= cdw_max);
2952 }
2953
2954 void radv_CmdDrawIndirect(
2955 VkCommandBuffer commandBuffer,
2956 VkBuffer buffer,
2957 VkDeviceSize offset,
2958 uint32_t drawCount,
2959 uint32_t stride)
2960 {
2961 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2962 VK_NULL_HANDLE, 0, drawCount, stride);
2963 }
2964
2965 void radv_CmdDrawIndexedIndirect(
2966 VkCommandBuffer commandBuffer,
2967 VkBuffer buffer,
2968 VkDeviceSize offset,
2969 uint32_t drawCount,
2970 uint32_t stride)
2971 {
2972 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2973 VK_NULL_HANDLE, 0, drawCount, stride);
2974 }
2975
2976 void radv_CmdDrawIndirectCountAMD(
2977 VkCommandBuffer commandBuffer,
2978 VkBuffer buffer,
2979 VkDeviceSize offset,
2980 VkBuffer countBuffer,
2981 VkDeviceSize countBufferOffset,
2982 uint32_t maxDrawCount,
2983 uint32_t stride)
2984 {
2985 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2986 countBuffer, countBufferOffset,
2987 maxDrawCount, stride);
2988 }
2989
2990 void radv_CmdDrawIndexedIndirectCountAMD(
2991 VkCommandBuffer commandBuffer,
2992 VkBuffer buffer,
2993 VkDeviceSize offset,
2994 VkBuffer countBuffer,
2995 VkDeviceSize countBufferOffset,
2996 uint32_t maxDrawCount,
2997 uint32_t stride)
2998 {
2999 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3000 countBuffer, countBufferOffset,
3001 maxDrawCount, stride);
3002 }
3003
3004 static void
3005 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
3006 {
3007 radv_emit_compute_pipeline(cmd_buffer);
3008 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3009 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3010 VK_SHADER_STAGE_COMPUTE_BIT);
3011 si_emit_cache_flush(cmd_buffer);
3012 }
3013
3014 void radv_CmdDispatch(
3015 VkCommandBuffer commandBuffer,
3016 uint32_t x,
3017 uint32_t y,
3018 uint32_t z)
3019 {
3020 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3021
3022 radv_flush_compute_state(cmd_buffer);
3023
3024 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
3025
3026 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3027 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3028 if (loc->sgpr_idx != -1) {
3029 assert(!loc->indirect);
3030 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3031 assert(loc->num_sgprs == grid_used);
3032 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
3033 radeon_emit(cmd_buffer->cs, x);
3034 if (grid_used > 1)
3035 radeon_emit(cmd_buffer->cs, y);
3036 if (grid_used > 2)
3037 radeon_emit(cmd_buffer->cs, z);
3038 }
3039
3040 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3041 PKT3_SHADER_TYPE_S(1));
3042 radeon_emit(cmd_buffer->cs, x);
3043 radeon_emit(cmd_buffer->cs, y);
3044 radeon_emit(cmd_buffer->cs, z);
3045 radeon_emit(cmd_buffer->cs, 1);
3046
3047 assert(cmd_buffer->cs->cdw <= cdw_max);
3048 radv_cmd_buffer_trace_emit(cmd_buffer);
3049 }
3050
3051 void radv_CmdDispatchIndirect(
3052 VkCommandBuffer commandBuffer,
3053 VkBuffer _buffer,
3054 VkDeviceSize offset)
3055 {
3056 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3057 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3058 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
3059 va += buffer->offset + offset;
3060
3061 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
3062
3063 radv_flush_compute_state(cmd_buffer);
3064
3065 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
3066 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3067 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3068 if (loc->sgpr_idx != -1) {
3069 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3070 for (unsigned i = 0; i < grid_used; ++i) {
3071 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
3072 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3073 COPY_DATA_DST_SEL(COPY_DATA_REG));
3074 radeon_emit(cmd_buffer->cs, (va + 4 * i));
3075 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
3076 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
3077 radeon_emit(cmd_buffer->cs, 0);
3078 }
3079 }
3080
3081 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3082 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3083 PKT3_SHADER_TYPE_S(1));
3084 radeon_emit(cmd_buffer->cs, va);
3085 radeon_emit(cmd_buffer->cs, va >> 32);
3086 radeon_emit(cmd_buffer->cs, 1);
3087 } else {
3088 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
3089 PKT3_SHADER_TYPE_S(1));
3090 radeon_emit(cmd_buffer->cs, 1);
3091 radeon_emit(cmd_buffer->cs, va);
3092 radeon_emit(cmd_buffer->cs, va >> 32);
3093
3094 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3095 PKT3_SHADER_TYPE_S(1));
3096 radeon_emit(cmd_buffer->cs, 0);
3097 radeon_emit(cmd_buffer->cs, 1);
3098 }
3099
3100 assert(cmd_buffer->cs->cdw <= cdw_max);
3101 radv_cmd_buffer_trace_emit(cmd_buffer);
3102 }
3103
3104 void radv_unaligned_dispatch(
3105 struct radv_cmd_buffer *cmd_buffer,
3106 uint32_t x,
3107 uint32_t y,
3108 uint32_t z)
3109 {
3110 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3111 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3112 uint32_t blocks[3], remainder[3];
3113
3114 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
3115 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
3116 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
3117
3118 /* If aligned, these should be an entire block size, not 0 */
3119 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
3120 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
3121 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
3122
3123 radv_flush_compute_state(cmd_buffer);
3124
3125 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
3126
3127 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3128 radeon_emit(cmd_buffer->cs,
3129 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
3130 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3131 radeon_emit(cmd_buffer->cs,
3132 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
3133 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3134 radeon_emit(cmd_buffer->cs,
3135 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
3136 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3137
3138 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
3139 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
3140 if (loc->sgpr_idx != -1) {
3141 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
3142 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
3143 radeon_emit(cmd_buffer->cs, blocks[0]);
3144 if (grid_used > 1)
3145 radeon_emit(cmd_buffer->cs, blocks[1]);
3146 if (grid_used > 2)
3147 radeon_emit(cmd_buffer->cs, blocks[2]);
3148 }
3149 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3150 PKT3_SHADER_TYPE_S(1));
3151 radeon_emit(cmd_buffer->cs, blocks[0]);
3152 radeon_emit(cmd_buffer->cs, blocks[1]);
3153 radeon_emit(cmd_buffer->cs, blocks[2]);
3154 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
3155 S_00B800_PARTIAL_TG_EN(1));
3156
3157 assert(cmd_buffer->cs->cdw <= cdw_max);
3158 radv_cmd_buffer_trace_emit(cmd_buffer);
3159 }
3160
3161 void radv_CmdEndRenderPass(
3162 VkCommandBuffer commandBuffer)
3163 {
3164 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3165
3166 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3167
3168 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3169
3170 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3171 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3172 radv_handle_subpass_image_transition(cmd_buffer,
3173 (VkAttachmentReference){i, layout});
3174 }
3175
3176 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3177
3178 cmd_buffer->state.pass = NULL;
3179 cmd_buffer->state.subpass = NULL;
3180 cmd_buffer->state.attachments = NULL;
3181 cmd_buffer->state.framebuffer = NULL;
3182 }
3183
3184 /*
3185 * For HTILE we have the following interesting clear words:
3186 * 0x0000030f: Uncompressed.
3187 * 0xfffffff0: Clear depth to 1.0
3188 * 0x00000000: Clear depth to 0.0
3189 */
3190 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3191 struct radv_image *image,
3192 const VkImageSubresourceRange *range,
3193 uint32_t clear_word)
3194 {
3195 assert(range->baseMipLevel == 0);
3196 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3197 unsigned layer_count = radv_get_layerCount(image, range);
3198 uint64_t size = image->surface.htile_slice_size * layer_count;
3199 uint64_t offset = image->offset + image->htile_offset +
3200 image->surface.htile_slice_size * range->baseArrayLayer;
3201
3202 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3203 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3204
3205 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3206
3207 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3208 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3209 RADV_CMD_FLAG_INV_VMEM_L1 |
3210 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3211 }
3212
3213 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3214 struct radv_image *image,
3215 VkImageLayout src_layout,
3216 VkImageLayout dst_layout,
3217 unsigned src_queue_mask,
3218 unsigned dst_queue_mask,
3219 const VkImageSubresourceRange *range,
3220 VkImageAspectFlags pending_clears)
3221 {
3222 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3223 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3224 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3225 cmd_buffer->state.render_area.extent.width == image->info.width &&
3226 cmd_buffer->state.render_area.extent.height == image->info.height) {
3227 /* The clear will initialize htile. */
3228 return;
3229 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3230 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3231 /* TODO: merge with the clear if applicable */
3232 radv_initialize_htile(cmd_buffer, image, range, 0);
3233 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3234 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3235 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3236 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3237 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3238 VkImageSubresourceRange local_range = *range;
3239 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3240 local_range.baseMipLevel = 0;
3241 local_range.levelCount = 1;
3242
3243 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3244 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3245
3246 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3247
3248 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3249 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3250 }
3251 }
3252
3253 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3254 struct radv_image *image, uint32_t value)
3255 {
3256 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3257 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3258
3259 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3260 image->cmask.size, value);
3261
3262 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3263 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3264 RADV_CMD_FLAG_INV_VMEM_L1 |
3265 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3266 }
3267
3268 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3269 struct radv_image *image,
3270 VkImageLayout src_layout,
3271 VkImageLayout dst_layout,
3272 unsigned src_queue_mask,
3273 unsigned dst_queue_mask,
3274 const VkImageSubresourceRange *range,
3275 VkImageAspectFlags pending_clears)
3276 {
3277 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3278 if (image->fmask.size)
3279 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3280 else
3281 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3282 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3283 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3284 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3285 }
3286 }
3287
3288 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3289 struct radv_image *image, uint32_t value)
3290 {
3291
3292 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3293 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3294
3295 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3296 image->surface.dcc_size, value);
3297
3298 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3299 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3300 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3301 RADV_CMD_FLAG_INV_VMEM_L1 |
3302 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3303 }
3304
3305 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3306 struct radv_image *image,
3307 VkImageLayout src_layout,
3308 VkImageLayout dst_layout,
3309 unsigned src_queue_mask,
3310 unsigned dst_queue_mask,
3311 const VkImageSubresourceRange *range,
3312 VkImageAspectFlags pending_clears)
3313 {
3314 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3315 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3316 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3317 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3318 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3319 }
3320 }
3321
3322 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3323 struct radv_image *image,
3324 VkImageLayout src_layout,
3325 VkImageLayout dst_layout,
3326 uint32_t src_family,
3327 uint32_t dst_family,
3328 const VkImageSubresourceRange *range,
3329 VkImageAspectFlags pending_clears)
3330 {
3331 if (image->exclusive && src_family != dst_family) {
3332 /* This is an acquire or a release operation and there will be
3333 * a corresponding release/acquire. Do the transition in the
3334 * most flexible queue. */
3335
3336 assert(src_family == cmd_buffer->queue_family_index ||
3337 dst_family == cmd_buffer->queue_family_index);
3338
3339 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3340 return;
3341
3342 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3343 (src_family == RADV_QUEUE_GENERAL ||
3344 dst_family == RADV_QUEUE_GENERAL))
3345 return;
3346 }
3347
3348 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3349 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3350
3351 if (image->surface.htile_size)
3352 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3353 dst_layout, src_queue_mask,
3354 dst_queue_mask, range,
3355 pending_clears);
3356
3357 if (image->cmask.size)
3358 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3359 dst_layout, src_queue_mask,
3360 dst_queue_mask, range,
3361 pending_clears);
3362
3363 if (image->surface.dcc_size)
3364 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3365 dst_layout, src_queue_mask,
3366 dst_queue_mask, range,
3367 pending_clears);
3368 }
3369
3370 void radv_CmdPipelineBarrier(
3371 VkCommandBuffer commandBuffer,
3372 VkPipelineStageFlags srcStageMask,
3373 VkPipelineStageFlags destStageMask,
3374 VkBool32 byRegion,
3375 uint32_t memoryBarrierCount,
3376 const VkMemoryBarrier* pMemoryBarriers,
3377 uint32_t bufferMemoryBarrierCount,
3378 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3379 uint32_t imageMemoryBarrierCount,
3380 const VkImageMemoryBarrier* pImageMemoryBarriers)
3381 {
3382 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3383 enum radv_cmd_flush_bits src_flush_bits = 0;
3384 enum radv_cmd_flush_bits dst_flush_bits = 0;
3385
3386 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3387 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3388 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3389 NULL);
3390 }
3391
3392 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3393 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3394 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3395 NULL);
3396 }
3397
3398 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3399 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3400 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3401 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3402 image);
3403 }
3404
3405 radv_stage_flush(cmd_buffer, srcStageMask);
3406 cmd_buffer->state.flush_bits |= src_flush_bits;
3407
3408 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3409 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3410 radv_handle_image_transition(cmd_buffer, image,
3411 pImageMemoryBarriers[i].oldLayout,
3412 pImageMemoryBarriers[i].newLayout,
3413 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3414 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3415 &pImageMemoryBarriers[i].subresourceRange,
3416 0);
3417 }
3418
3419 cmd_buffer->state.flush_bits |= dst_flush_bits;
3420 }
3421
3422
3423 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3424 struct radv_event *event,
3425 VkPipelineStageFlags stageMask,
3426 unsigned value)
3427 {
3428 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3429 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3430
3431 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3432
3433 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3434
3435 /* TODO: this is overkill. Probably should figure something out from
3436 * the stage mask. */
3437
3438 si_cs_emit_write_event_eop(cs,
3439 cmd_buffer->state.predicating,
3440 cmd_buffer->device->physical_device->rad_info.chip_class,
3441 false,
3442 EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
3443 1, va, 2, value);
3444
3445 assert(cmd_buffer->cs->cdw <= cdw_max);
3446 }
3447
3448 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3449 VkEvent _event,
3450 VkPipelineStageFlags stageMask)
3451 {
3452 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3453 RADV_FROM_HANDLE(radv_event, event, _event);
3454
3455 write_event(cmd_buffer, event, stageMask, 1);
3456 }
3457
3458 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3459 VkEvent _event,
3460 VkPipelineStageFlags stageMask)
3461 {
3462 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3463 RADV_FROM_HANDLE(radv_event, event, _event);
3464
3465 write_event(cmd_buffer, event, stageMask, 0);
3466 }
3467
3468 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3469 uint32_t eventCount,
3470 const VkEvent* pEvents,
3471 VkPipelineStageFlags srcStageMask,
3472 VkPipelineStageFlags dstStageMask,
3473 uint32_t memoryBarrierCount,
3474 const VkMemoryBarrier* pMemoryBarriers,
3475 uint32_t bufferMemoryBarrierCount,
3476 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3477 uint32_t imageMemoryBarrierCount,
3478 const VkImageMemoryBarrier* pImageMemoryBarriers)
3479 {
3480 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3481 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3482
3483 for (unsigned i = 0; i < eventCount; ++i) {
3484 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3485 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3486
3487 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3488
3489 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3490
3491 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3492 assert(cmd_buffer->cs->cdw <= cdw_max);
3493 }
3494
3495
3496 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3497 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3498
3499 radv_handle_image_transition(cmd_buffer, image,
3500 pImageMemoryBarriers[i].oldLayout,
3501 pImageMemoryBarriers[i].newLayout,
3502 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3503 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3504 &pImageMemoryBarriers[i].subresourceRange,
3505 0);
3506 }
3507
3508 /* TODO: figure out how to do memory barriers without waiting */
3509 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3510 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3511 RADV_CMD_FLAG_INV_VMEM_L1 |
3512 RADV_CMD_FLAG_INV_SMEM_L1;
3513 }