2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
33 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
57 VkImageLayout dst_layout
,
60 const VkImageSubresourceRange
*range
,
61 struct radv_sample_locations_state
*sample_locs
);
63 const struct radv_dynamic_state default_dynamic_state
= {
76 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
81 .stencil_compare_mask
= {
85 .stencil_write_mask
= {
89 .stencil_reference
= {
96 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
97 const struct radv_dynamic_state
*src
)
99 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
100 uint32_t copy_mask
= src
->mask
;
101 uint32_t dest_mask
= 0;
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
106 dest
->viewport
.count
= src
->viewport
.count
;
107 dest
->scissor
.count
= src
->scissor
.count
;
108 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
109 dest
->sample_location
.count
= src
->sample_location
.count
;
111 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
112 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
113 src
->viewport
.count
* sizeof(VkViewport
))) {
114 typed_memcpy(dest
->viewport
.viewports
,
115 src
->viewport
.viewports
,
116 src
->viewport
.count
);
117 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
121 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
122 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
123 src
->scissor
.count
* sizeof(VkRect2D
))) {
124 typed_memcpy(dest
->scissor
.scissors
,
125 src
->scissor
.scissors
, src
->scissor
.count
);
126 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
130 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
131 if (dest
->line_width
!= src
->line_width
) {
132 dest
->line_width
= src
->line_width
;
133 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
137 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
138 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
139 sizeof(src
->depth_bias
))) {
140 dest
->depth_bias
= src
->depth_bias
;
141 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
145 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
146 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
147 sizeof(src
->blend_constants
))) {
148 typed_memcpy(dest
->blend_constants
,
149 src
->blend_constants
, 4);
150 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
154 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
155 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
156 sizeof(src
->depth_bounds
))) {
157 dest
->depth_bounds
= src
->depth_bounds
;
158 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
162 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
163 if (memcmp(&dest
->stencil_compare_mask
,
164 &src
->stencil_compare_mask
,
165 sizeof(src
->stencil_compare_mask
))) {
166 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
167 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
171 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
172 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
173 sizeof(src
->stencil_write_mask
))) {
174 dest
->stencil_write_mask
= src
->stencil_write_mask
;
175 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
179 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
180 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
181 sizeof(src
->stencil_reference
))) {
182 dest
->stencil_reference
= src
->stencil_reference
;
183 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
187 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
188 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
189 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
190 typed_memcpy(dest
->discard_rectangle
.rectangles
,
191 src
->discard_rectangle
.rectangles
,
192 src
->discard_rectangle
.count
);
193 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
197 if (copy_mask
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
198 if (dest
->sample_location
.per_pixel
!= src
->sample_location
.per_pixel
||
199 dest
->sample_location
.grid_size
.width
!= src
->sample_location
.grid_size
.width
||
200 dest
->sample_location
.grid_size
.height
!= src
->sample_location
.grid_size
.height
||
201 memcmp(&dest
->sample_location
.locations
,
202 &src
->sample_location
.locations
,
203 src
->sample_location
.count
* sizeof(VkSampleLocationEXT
))) {
204 dest
->sample_location
.per_pixel
= src
->sample_location
.per_pixel
;
205 dest
->sample_location
.grid_size
= src
->sample_location
.grid_size
;
206 typed_memcpy(dest
->sample_location
.locations
,
207 src
->sample_location
.locations
,
208 src
->sample_location
.count
);
209 dest_mask
|= RADV_DYNAMIC_SAMPLE_LOCATIONS
;
213 cmd_buffer
->state
.dirty
|= dest_mask
;
217 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
218 struct radv_pipeline
*pipeline
)
220 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
221 struct radv_shader_info
*info
;
223 if (!pipeline
->streamout_shader
)
226 info
= &pipeline
->streamout_shader
->info
.info
;
227 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
228 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
230 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
235 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
236 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
239 enum ring_type
radv_queue_family_to_ring(int f
) {
241 case RADV_QUEUE_GENERAL
:
243 case RADV_QUEUE_COMPUTE
:
245 case RADV_QUEUE_TRANSFER
:
248 unreachable("Unknown queue family");
252 static VkResult
radv_create_cmd_buffer(
253 struct radv_device
* device
,
254 struct radv_cmd_pool
* pool
,
255 VkCommandBufferLevel level
,
256 VkCommandBuffer
* pCommandBuffer
)
258 struct radv_cmd_buffer
*cmd_buffer
;
260 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
262 if (cmd_buffer
== NULL
)
263 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
265 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
266 cmd_buffer
->device
= device
;
267 cmd_buffer
->pool
= pool
;
268 cmd_buffer
->level
= level
;
271 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
272 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
275 /* Init the pool_link so we can safely call list_del when we destroy
278 list_inithead(&cmd_buffer
->pool_link
);
279 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
282 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
284 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
285 if (!cmd_buffer
->cs
) {
286 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
287 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
290 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
292 list_inithead(&cmd_buffer
->upload
.list
);
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
300 list_del(&cmd_buffer
->pool_link
);
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
303 &cmd_buffer
->upload
.list
, list
) {
304 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
309 if (cmd_buffer
->upload
.upload_bo
)
310 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
311 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
313 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
314 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
316 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
320 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
322 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
325 &cmd_buffer
->upload
.list
, list
) {
326 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
331 cmd_buffer
->push_constant_stages
= 0;
332 cmd_buffer
->scratch_size_needed
= 0;
333 cmd_buffer
->compute_scratch_size_needed
= 0;
334 cmd_buffer
->esgs_ring_size_needed
= 0;
335 cmd_buffer
->gsvs_ring_size_needed
= 0;
336 cmd_buffer
->tess_rings_needed
= false;
337 cmd_buffer
->sample_positions_needed
= false;
339 if (cmd_buffer
->upload
.upload_bo
)
340 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
341 cmd_buffer
->upload
.upload_bo
);
342 cmd_buffer
->upload
.offset
= 0;
344 cmd_buffer
->record_result
= VK_SUCCESS
;
346 memset(cmd_buffer
->vertex_bindings
, 0, sizeof(cmd_buffer
->vertex_bindings
));
348 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
349 cmd_buffer
->descriptors
[i
].dirty
= 0;
350 cmd_buffer
->descriptors
[i
].valid
= 0;
351 cmd_buffer
->descriptors
[i
].push_dirty
= false;
354 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
355 cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
356 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
357 unsigned fence_offset
, eop_bug_offset
;
360 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 8, &fence_offset
,
363 cmd_buffer
->gfx9_fence_va
=
364 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
365 cmd_buffer
->gfx9_fence_va
+= fence_offset
;
367 /* Allocate a buffer for the EOP bug on GFX9. */
368 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 8,
369 &eop_bug_offset
, &fence_ptr
);
370 cmd_buffer
->gfx9_eop_bug_va
=
371 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
372 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
375 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
377 return cmd_buffer
->record_result
;
381 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
385 struct radeon_winsys_bo
*bo
;
386 struct radv_cmd_buffer_upload
*upload
;
387 struct radv_device
*device
= cmd_buffer
->device
;
389 new_size
= MAX2(min_needed
, 16 * 1024);
390 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
392 bo
= device
->ws
->buffer_create(device
->ws
,
395 RADEON_FLAG_CPU_ACCESS
|
396 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
398 RADV_BO_PRIORITY_UPLOAD_BUFFER
);
401 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
405 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
406 if (cmd_buffer
->upload
.upload_bo
) {
407 upload
= malloc(sizeof(*upload
));
410 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
411 device
->ws
->buffer_destroy(bo
);
415 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
416 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
419 cmd_buffer
->upload
.upload_bo
= bo
;
420 cmd_buffer
->upload
.size
= new_size
;
421 cmd_buffer
->upload
.offset
= 0;
422 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
424 if (!cmd_buffer
->upload
.map
) {
425 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
433 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
436 unsigned *out_offset
,
439 assert(util_is_power_of_two_nonzero(alignment
));
441 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
442 if (offset
+ size
> cmd_buffer
->upload
.size
) {
443 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
448 *out_offset
= offset
;
449 *ptr
= cmd_buffer
->upload
.map
+ offset
;
451 cmd_buffer
->upload
.offset
= offset
+ size
;
456 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
457 unsigned size
, unsigned alignment
,
458 const void *data
, unsigned *out_offset
)
462 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
463 out_offset
, (void **)&ptr
))
467 memcpy(ptr
, data
, size
);
473 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
474 unsigned count
, const uint32_t *data
)
476 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
478 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
480 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
481 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
482 S_370_WR_CONFIRM(1) |
483 S_370_ENGINE_SEL(V_370_ME
));
485 radeon_emit(cs
, va
>> 32);
486 radeon_emit_array(cs
, data
, count
);
489 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
491 struct radv_device
*device
= cmd_buffer
->device
;
492 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
495 va
= radv_buffer_get_va(device
->trace_bo
);
496 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
499 ++cmd_buffer
->state
.trace_id
;
500 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
501 &cmd_buffer
->state
.trace_id
);
503 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
505 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
506 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
510 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
511 enum radv_cmd_flush_bits flags
)
513 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
514 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
515 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
517 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
519 /* Force wait for graphics or compute engines to be idle. */
520 si_cs_emit_cache_flush(cmd_buffer
->cs
,
521 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
522 &cmd_buffer
->gfx9_fence_idx
,
523 cmd_buffer
->gfx9_fence_va
,
524 radv_cmd_buffer_uses_mec(cmd_buffer
),
525 flags
, cmd_buffer
->gfx9_eop_bug_va
);
528 if (unlikely(cmd_buffer
->device
->trace_bo
))
529 radv_cmd_buffer_trace_emit(cmd_buffer
);
533 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
534 struct radv_pipeline
*pipeline
, enum ring_type ring
)
536 struct radv_device
*device
= cmd_buffer
->device
;
540 va
= radv_buffer_get_va(device
->trace_bo
);
550 assert(!"invalid ring type");
553 data
[0] = (uintptr_t)pipeline
;
554 data
[1] = (uintptr_t)pipeline
>> 32;
556 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
559 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
560 VkPipelineBindPoint bind_point
,
561 struct radv_descriptor_set
*set
,
564 struct radv_descriptor_state
*descriptors_state
=
565 radv_get_descriptors_state(cmd_buffer
, bind_point
);
567 descriptors_state
->sets
[idx
] = set
;
569 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
570 descriptors_state
->dirty
|= (1u << idx
);
574 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
575 VkPipelineBindPoint bind_point
)
577 struct radv_descriptor_state
*descriptors_state
=
578 radv_get_descriptors_state(cmd_buffer
, bind_point
);
579 struct radv_device
*device
= cmd_buffer
->device
;
580 uint32_t data
[MAX_SETS
* 2] = {};
583 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
585 for_each_bit(i
, descriptors_state
->valid
) {
586 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
587 data
[i
* 2] = (uint64_t)(uintptr_t)set
;
588 data
[i
* 2 + 1] = (uint64_t)(uintptr_t)set
>> 32;
591 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
594 struct radv_userdata_info
*
595 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
596 gl_shader_stage stage
,
599 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
600 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
604 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
605 struct radv_pipeline
*pipeline
,
606 gl_shader_stage stage
,
607 int idx
, uint64_t va
)
609 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
610 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
611 if (loc
->sgpr_idx
== -1)
614 assert(loc
->num_sgprs
== 1);
616 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
617 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
621 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
622 struct radv_pipeline
*pipeline
,
623 struct radv_descriptor_state
*descriptors_state
,
624 gl_shader_stage stage
)
626 struct radv_device
*device
= cmd_buffer
->device
;
627 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
628 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
629 struct radv_userdata_locations
*locs
=
630 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
631 unsigned mask
= locs
->descriptor_sets_enabled
;
633 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
638 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
640 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
641 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
643 radv_emit_shader_pointer_head(cs
, sh_offset
, count
, true);
644 for (int i
= 0; i
< count
; i
++) {
645 struct radv_descriptor_set
*set
=
646 descriptors_state
->sets
[start
+ i
];
648 radv_emit_shader_pointer_body(device
, cs
, set
->va
, true);
654 * Convert the user sample locations to hardware sample locations (the values
655 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
658 radv_convert_user_sample_locs(struct radv_sample_locations_state
*state
,
659 uint32_t x
, uint32_t y
, VkOffset2D
*sample_locs
)
661 uint32_t x_offset
= x
% state
->grid_size
.width
;
662 uint32_t y_offset
= y
% state
->grid_size
.height
;
663 uint32_t num_samples
= (uint32_t)state
->per_pixel
;
664 VkSampleLocationEXT
*user_locs
;
665 uint32_t pixel_offset
;
667 pixel_offset
= (x_offset
+ y_offset
* state
->grid_size
.width
) * num_samples
;
669 assert(pixel_offset
<= MAX_SAMPLE_LOCATIONS
);
670 user_locs
= &state
->locations
[pixel_offset
];
672 for (uint32_t i
= 0; i
< num_samples
; i
++) {
673 float shifted_pos_x
= user_locs
[i
].x
- 0.5;
674 float shifted_pos_y
= user_locs
[i
].y
- 0.5;
676 int32_t scaled_pos_x
= floor(shifted_pos_x
* 16);
677 int32_t scaled_pos_y
= floor(shifted_pos_y
* 16);
679 sample_locs
[i
].x
= CLAMP(scaled_pos_x
, -8, 7);
680 sample_locs
[i
].y
= CLAMP(scaled_pos_y
, -8, 7);
685 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
689 radv_compute_sample_locs_pixel(uint32_t num_samples
, VkOffset2D
*sample_locs
,
690 uint32_t *sample_locs_pixel
)
692 for (uint32_t i
= 0; i
< num_samples
; i
++) {
693 uint32_t sample_reg_idx
= i
/ 4;
694 uint32_t sample_loc_idx
= i
% 4;
695 int32_t pos_x
= sample_locs
[i
].x
;
696 int32_t pos_y
= sample_locs
[i
].y
;
698 uint32_t shift_x
= 8 * sample_loc_idx
;
699 uint32_t shift_y
= shift_x
+ 4;
701 sample_locs_pixel
[sample_reg_idx
] |= (pos_x
& 0xf) << shift_x
;
702 sample_locs_pixel
[sample_reg_idx
] |= (pos_y
& 0xf) << shift_y
;
707 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
711 radv_compute_centroid_priority(struct radv_cmd_buffer
*cmd_buffer
,
712 VkOffset2D
*sample_locs
,
713 uint32_t num_samples
)
715 uint32_t centroid_priorities
[num_samples
];
716 uint32_t sample_mask
= num_samples
- 1;
717 uint32_t distances
[num_samples
];
718 uint64_t centroid_priority
= 0;
720 /* Compute the distances from center for each sample. */
721 for (int i
= 0; i
< num_samples
; i
++) {
722 distances
[i
] = (sample_locs
[i
].x
* sample_locs
[i
].x
) +
723 (sample_locs
[i
].y
* sample_locs
[i
].y
);
726 /* Compute the centroid priorities by looking at the distances array. */
727 for (int i
= 0; i
< num_samples
; i
++) {
728 uint32_t min_idx
= 0;
730 for (int j
= 1; j
< num_samples
; j
++) {
731 if (distances
[j
] < distances
[min_idx
])
735 centroid_priorities
[i
] = min_idx
;
736 distances
[min_idx
] = 0xffffffff;
739 /* Compute the final centroid priority. */
740 for (int i
= 0; i
< 8; i
++) {
742 centroid_priorities
[i
& sample_mask
] << (i
* 4);
745 return centroid_priority
<< 32 | centroid_priority
;
749 * Emit the sample locations that are specified with VK_EXT_sample_locations.
752 radv_emit_sample_locations(struct radv_cmd_buffer
*cmd_buffer
)
754 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
755 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
756 struct radv_sample_locations_state
*sample_location
=
757 &cmd_buffer
->state
.dynamic
.sample_location
;
758 uint32_t num_samples
= (uint32_t)sample_location
->per_pixel
;
759 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
760 uint32_t sample_locs_pixel
[4][2] = {};
761 VkOffset2D sample_locs
[4][8]; /* 8 is the max. sample count supported */
762 uint32_t max_sample_dist
= 0;
763 uint64_t centroid_priority
;
765 if (!cmd_buffer
->state
.dynamic
.sample_location
.count
)
768 /* Convert the user sample locations to hardware sample locations. */
769 radv_convert_user_sample_locs(sample_location
, 0, 0, sample_locs
[0]);
770 radv_convert_user_sample_locs(sample_location
, 1, 0, sample_locs
[1]);
771 radv_convert_user_sample_locs(sample_location
, 0, 1, sample_locs
[2]);
772 radv_convert_user_sample_locs(sample_location
, 1, 1, sample_locs
[3]);
774 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
775 for (uint32_t i
= 0; i
< 4; i
++) {
776 radv_compute_sample_locs_pixel(num_samples
, sample_locs
[i
],
777 sample_locs_pixel
[i
]);
780 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
782 radv_compute_centroid_priority(cmd_buffer
, sample_locs
[0],
785 /* Compute the maximum sample distance from the specified locations. */
786 for (uint32_t i
= 0; i
< num_samples
; i
++) {
787 VkOffset2D offset
= sample_locs
[0][i
];
788 max_sample_dist
= MAX2(max_sample_dist
,
789 MAX2(abs(offset
.x
), abs(offset
.y
)));
792 /* Emit the specified user sample locations. */
793 switch (num_samples
) {
796 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
797 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
798 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
799 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
802 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
803 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
804 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
805 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
806 radeon_set_context_reg(cs
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, sample_locs_pixel
[0][1]);
807 radeon_set_context_reg(cs
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, sample_locs_pixel
[1][1]);
808 radeon_set_context_reg(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, sample_locs_pixel
[2][1]);
809 radeon_set_context_reg(cs
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, sample_locs_pixel
[3][1]);
812 unreachable("invalid number of samples");
815 /* Emit the maximum sample distance and the centroid priority. */
816 uint32_t pa_sc_aa_config
= ms
->pa_sc_aa_config
;
818 pa_sc_aa_config
&= C_028BE0_MAX_SAMPLE_DIST
;
819 pa_sc_aa_config
|= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist
);
821 radeon_set_context_reg_seq(cs
, R_028BE0_PA_SC_AA_CONFIG
, 1);
822 radeon_emit(cs
, pa_sc_aa_config
);
824 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
825 radeon_emit(cs
, centroid_priority
);
826 radeon_emit(cs
, centroid_priority
>> 32);
828 /* GFX9: Flush DFSM when the AA mode changes. */
829 if (cmd_buffer
->device
->dfsm_allowed
) {
830 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
831 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
834 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
838 radv_emit_inline_push_consts(struct radv_cmd_buffer
*cmd_buffer
,
839 struct radv_pipeline
*pipeline
,
840 gl_shader_stage stage
,
841 int idx
, int count
, uint32_t *values
)
843 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
844 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
845 if (loc
->sgpr_idx
== -1)
848 assert(loc
->num_sgprs
== count
);
850 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, count
);
851 radeon_emit_array(cmd_buffer
->cs
, values
, count
);
855 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
856 struct radv_pipeline
*pipeline
)
858 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
859 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
860 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
862 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
)
863 cmd_buffer
->sample_positions_needed
= true;
865 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
868 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
869 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
870 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
872 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
874 radv_emit_default_sample_locations(cmd_buffer
->cs
, num_samples
);
876 /* GFX9: Flush DFSM when the AA mode changes. */
877 if (cmd_buffer
->device
->dfsm_allowed
) {
878 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
879 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
882 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
886 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
887 struct radv_shader_variant
*shader
)
894 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
896 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
900 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
901 struct radv_pipeline
*pipeline
,
902 bool vertex_stage_only
)
904 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
905 uint32_t mask
= state
->prefetch_L2_mask
;
907 if (vertex_stage_only
) {
908 /* Fast prefetch path for starting draws as soon as possible.
910 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
911 RADV_PREFETCH_VBO_DESCRIPTORS
);
914 if (mask
& RADV_PREFETCH_VS
)
915 radv_emit_shader_prefetch(cmd_buffer
,
916 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
918 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
919 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
921 if (mask
& RADV_PREFETCH_TCS
)
922 radv_emit_shader_prefetch(cmd_buffer
,
923 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
925 if (mask
& RADV_PREFETCH_TES
)
926 radv_emit_shader_prefetch(cmd_buffer
,
927 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
929 if (mask
& RADV_PREFETCH_GS
) {
930 radv_emit_shader_prefetch(cmd_buffer
,
931 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
932 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
935 if (mask
& RADV_PREFETCH_PS
)
936 radv_emit_shader_prefetch(cmd_buffer
,
937 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
939 state
->prefetch_L2_mask
&= ~mask
;
943 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
945 if (!cmd_buffer
->device
->physical_device
->rbplus_allowed
)
948 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
949 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
950 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
952 unsigned sx_ps_downconvert
= 0;
953 unsigned sx_blend_opt_epsilon
= 0;
954 unsigned sx_blend_opt_control
= 0;
956 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
957 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
958 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
959 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
963 int idx
= subpass
->color_attachments
[i
].attachment
;
964 struct radv_color_buffer_info
*cb
= &framebuffer
->attachments
[idx
].cb
;
966 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
967 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
968 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
969 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
971 bool has_alpha
, has_rgb
;
973 /* Set if RGB and A are present. */
974 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
976 if (format
== V_028C70_COLOR_8
||
977 format
== V_028C70_COLOR_16
||
978 format
== V_028C70_COLOR_32
)
979 has_rgb
= !has_alpha
;
983 /* Check the colormask and export format. */
984 if (!(colormask
& 0x7))
986 if (!(colormask
& 0x8))
989 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
994 /* Disable value checking for disabled channels. */
996 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
998 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1000 /* Enable down-conversion for 32bpp and smaller formats. */
1002 case V_028C70_COLOR_8
:
1003 case V_028C70_COLOR_8_8
:
1004 case V_028C70_COLOR_8_8_8_8
:
1005 /* For 1 and 2-channel formats, use the superset thereof. */
1006 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
1007 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1008 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1009 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
1010 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
1014 case V_028C70_COLOR_5_6_5
:
1015 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1016 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
1017 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
1021 case V_028C70_COLOR_1_5_5_5
:
1022 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1023 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
1024 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
1028 case V_028C70_COLOR_4_4_4_4
:
1029 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1030 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
1031 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
1035 case V_028C70_COLOR_32
:
1036 if (swap
== V_028C70_SWAP_STD
&&
1037 spi_format
== V_028714_SPI_SHADER_32_R
)
1038 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
1039 else if (swap
== V_028C70_SWAP_ALT_REV
&&
1040 spi_format
== V_028714_SPI_SHADER_32_AR
)
1041 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
1044 case V_028C70_COLOR_16
:
1045 case V_028C70_COLOR_16_16
:
1046 /* For 1-channel formats, use the superset thereof. */
1047 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
1048 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
1049 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1050 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1051 if (swap
== V_028C70_SWAP_STD
||
1052 swap
== V_028C70_SWAP_STD_REV
)
1053 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
1055 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
1059 case V_028C70_COLOR_10_11_11
:
1060 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1061 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
1062 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
1066 case V_028C70_COLOR_2_10_10_10
:
1067 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1068 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
1069 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
1075 for (unsigned i
= subpass
->color_count
; i
< 8; ++i
) {
1076 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1077 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1079 /* TODO: avoid redundantly setting context registers */
1080 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
1081 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
1082 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
1083 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
1085 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1089 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1091 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1093 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
1096 radv_update_multisample_state(cmd_buffer
, pipeline
);
1098 cmd_buffer
->scratch_size_needed
=
1099 MAX2(cmd_buffer
->scratch_size_needed
,
1100 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
1102 if (!cmd_buffer
->state
.emitted_pipeline
||
1103 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1104 pipeline
->graphics
.can_use_guardband
)
1105 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1107 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
1109 if (!cmd_buffer
->state
.emitted_pipeline
||
1110 cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.cdw
!= pipeline
->ctx_cs
.cdw
||
1111 cmd_buffer
->state
.emitted_pipeline
->ctx_cs_hash
!= pipeline
->ctx_cs_hash
||
1112 memcmp(cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.buf
,
1113 pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
* 4)) {
1114 radeon_emit_array(cmd_buffer
->cs
, pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
);
1115 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1118 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
1119 if (!pipeline
->shaders
[i
])
1122 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1123 pipeline
->shaders
[i
]->bo
);
1126 if (radv_pipeline_has_gs(pipeline
))
1127 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1128 pipeline
->gs_copy_shader
->bo
);
1130 if (unlikely(cmd_buffer
->device
->trace_bo
))
1131 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1133 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1135 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1139 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1141 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1142 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1146 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1148 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1150 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1151 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1152 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1153 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1155 cmd_buffer
->state
.context_roll_without_scissor_emitted
= false;
1159 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
1161 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
1164 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
1165 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
1166 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
1167 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
1168 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
1169 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
1170 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
1175 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1177 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1179 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1180 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1184 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1186 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1188 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1189 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1193 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1195 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1197 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1198 R_028430_DB_STENCILREFMASK
, 2);
1199 radeon_emit(cmd_buffer
->cs
,
1200 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1201 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1202 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1203 S_028430_STENCILOPVAL(1));
1204 radeon_emit(cmd_buffer
->cs
,
1205 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1206 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1207 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1208 S_028434_STENCILOPVAL_BF(1));
1212 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1214 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1216 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1217 fui(d
->depth_bounds
.min
));
1218 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1219 fui(d
->depth_bounds
.max
));
1223 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
1225 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1226 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1227 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1230 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1231 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1232 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1233 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1234 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1235 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1236 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1240 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1242 struct radv_attachment_info
*att
,
1243 struct radv_image
*image
,
1244 VkImageLayout layout
)
1246 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
;
1247 struct radv_color_buffer_info
*cb
= &att
->cb
;
1248 uint32_t cb_color_info
= cb
->cb_color_info
;
1250 if (!radv_layout_dcc_compressed(image
, layout
,
1251 radv_image_queue_family_mask(image
,
1252 cmd_buffer
->queue_family_index
,
1253 cmd_buffer
->queue_family_index
))) {
1254 cb_color_info
&= C_028C70_DCC_ENABLE
;
1257 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1258 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1259 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1260 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1261 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1262 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1263 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1264 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1265 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1266 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1267 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1268 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1269 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1271 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1272 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1273 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1275 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1278 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1279 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1280 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1281 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1282 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1283 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1284 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1285 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1286 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1287 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1288 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1289 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1291 if (is_vi
) { /* DCC BASE */
1292 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1296 if (radv_image_has_dcc(image
)) {
1297 /* Drawing with DCC enabled also compresses colorbuffers. */
1298 radv_update_dcc_metadata(cmd_buffer
, image
, true);
1303 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1304 struct radv_ds_buffer_info
*ds
,
1305 struct radv_image
*image
, VkImageLayout layout
,
1306 bool requires_cond_exec
)
1308 uint32_t db_z_info
= ds
->db_z_info
;
1309 uint32_t db_z_info_reg
;
1311 if (!radv_image_is_tc_compat_htile(image
))
1314 if (!radv_layout_has_htile(image
, layout
,
1315 radv_image_queue_family_mask(image
,
1316 cmd_buffer
->queue_family_index
,
1317 cmd_buffer
->queue_family_index
))) {
1318 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1321 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1323 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1324 db_z_info_reg
= R_028038_DB_Z_INFO
;
1326 db_z_info_reg
= R_028040_DB_Z_INFO
;
1329 /* When we don't know the last fast clear value we need to emit a
1330 * conditional packet that will eventually skip the following
1331 * SET_CONTEXT_REG packet.
1333 if (requires_cond_exec
) {
1334 uint64_t va
= radv_buffer_get_va(image
->bo
);
1335 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1337 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_EXEC
, 3, 0));
1338 radeon_emit(cmd_buffer
->cs
, va
);
1339 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1340 radeon_emit(cmd_buffer
->cs
, 0);
1341 radeon_emit(cmd_buffer
->cs
, 3); /* SET_CONTEXT_REG size */
1344 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1348 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1349 struct radv_ds_buffer_info
*ds
,
1350 struct radv_image
*image
,
1351 VkImageLayout layout
)
1353 uint32_t db_z_info
= ds
->db_z_info
;
1354 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1356 if (!radv_layout_has_htile(image
, layout
,
1357 radv_image_queue_family_mask(image
,
1358 cmd_buffer
->queue_family_index
,
1359 cmd_buffer
->queue_family_index
))) {
1360 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1361 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1364 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1365 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1368 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1369 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1370 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1371 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1372 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1374 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1375 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1376 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1377 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1378 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1379 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1380 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1381 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1382 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1383 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1384 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1386 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1387 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1388 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1390 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1392 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1393 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1394 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1395 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1396 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1397 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1398 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1399 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1400 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1401 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1405 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1406 radv_update_zrange_precision(cmd_buffer
, ds
, image
, layout
, true);
1408 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1409 ds
->pa_su_poly_offset_db_fmt_cntl
);
1413 * Update the fast clear depth/stencil values if the image is bound as a
1414 * depth/stencil buffer.
1417 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1418 struct radv_image
*image
,
1419 VkClearDepthStencilValue ds_clear_value
,
1420 VkImageAspectFlags aspects
)
1422 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1423 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1424 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1425 struct radv_attachment_info
*att
;
1428 if (!framebuffer
|| !subpass
)
1431 if (!subpass
->depth_stencil_attachment
)
1434 att_idx
= subpass
->depth_stencil_attachment
->attachment
;
1435 att
= &framebuffer
->attachments
[att_idx
];
1436 if (att
->attachment
->image
!= image
)
1439 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1440 radeon_emit(cs
, ds_clear_value
.stencil
);
1441 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1443 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1444 * only needed when clearing Z to 0.0.
1446 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1447 ds_clear_value
.depth
== 0.0) {
1448 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1450 radv_update_zrange_precision(cmd_buffer
, &att
->ds
, image
,
1454 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1458 * Set the clear depth/stencil values to the image's metadata.
1461 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1462 struct radv_image
*image
,
1463 VkClearDepthStencilValue ds_clear_value
,
1464 VkImageAspectFlags aspects
)
1466 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1467 uint64_t va
= radv_buffer_get_va(image
->bo
);
1468 unsigned reg_offset
= 0, reg_count
= 0;
1470 va
+= image
->offset
+ image
->clear_value_offset
;
1472 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1478 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1481 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, cmd_buffer
->state
.predicating
));
1482 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1483 S_370_WR_CONFIRM(1) |
1484 S_370_ENGINE_SEL(V_370_PFP
));
1485 radeon_emit(cs
, va
);
1486 radeon_emit(cs
, va
>> 32);
1487 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1488 radeon_emit(cs
, ds_clear_value
.stencil
);
1489 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1490 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1494 * Update the TC-compat metadata value for this image.
1497 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1498 struct radv_image
*image
,
1501 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1502 uint64_t va
= radv_buffer_get_va(image
->bo
);
1503 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1505 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, cmd_buffer
->state
.predicating
));
1506 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1507 S_370_WR_CONFIRM(1) |
1508 S_370_ENGINE_SEL(V_370_PFP
));
1509 radeon_emit(cs
, va
);
1510 radeon_emit(cs
, va
>> 32);
1511 radeon_emit(cs
, value
);
1515 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1516 struct radv_image
*image
,
1517 VkClearDepthStencilValue ds_clear_value
)
1519 uint64_t va
= radv_buffer_get_va(image
->bo
);
1520 va
+= image
->offset
+ image
->tc_compat_zrange_offset
;
1523 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1524 * depth clear value is 0.0f.
1526 cond_val
= ds_clear_value
.depth
== 0.0f
? UINT_MAX
: 0;
1528 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, cond_val
);
1532 * Update the clear depth/stencil values for this image.
1535 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1536 struct radv_image
*image
,
1537 VkClearDepthStencilValue ds_clear_value
,
1538 VkImageAspectFlags aspects
)
1540 assert(radv_image_has_htile(image
));
1542 radv_set_ds_clear_metadata(cmd_buffer
, image
, ds_clear_value
, aspects
);
1544 if (radv_image_is_tc_compat_htile(image
) &&
1545 (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
1546 radv_update_tc_compat_zrange_metadata(cmd_buffer
, image
,
1550 radv_update_bound_fast_clear_ds(cmd_buffer
, image
, ds_clear_value
,
1555 * Load the clear depth/stencil values from the image's metadata.
1558 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1559 struct radv_image
*image
)
1561 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1562 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1563 uint64_t va
= radv_buffer_get_va(image
->bo
);
1564 unsigned reg_offset
= 0, reg_count
= 0;
1566 va
+= image
->offset
+ image
->clear_value_offset
;
1568 if (!radv_image_has_htile(image
))
1571 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1577 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1580 uint32_t reg
= R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
;
1582 if (cmd_buffer
->device
->physical_device
->has_load_ctx_reg_pkt
) {
1583 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, 0));
1584 radeon_emit(cs
, va
);
1585 radeon_emit(cs
, va
>> 32);
1586 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1587 radeon_emit(cs
, reg_count
);
1589 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1590 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1591 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1592 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1593 radeon_emit(cs
, va
);
1594 radeon_emit(cs
, va
>> 32);
1595 radeon_emit(cs
, reg
>> 2);
1598 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1604 * With DCC some colors don't require CMASK elimination before being
1605 * used as a texture. This sets a predicate value to determine if the
1606 * cmask eliminate is required.
1609 radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1610 struct radv_image
*image
, bool value
)
1612 uint64_t pred_val
= value
;
1613 uint64_t va
= radv_buffer_get_va(image
->bo
);
1614 va
+= image
->offset
+ image
->fce_pred_offset
;
1616 assert(radv_image_has_dcc(image
));
1618 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1619 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1620 S_370_WR_CONFIRM(1) |
1621 S_370_ENGINE_SEL(V_370_PFP
));
1622 radeon_emit(cmd_buffer
->cs
, va
);
1623 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1624 radeon_emit(cmd_buffer
->cs
, pred_val
);
1625 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1629 * Update the DCC predicate to reflect the compression state.
1632 radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1633 struct radv_image
*image
, bool value
)
1635 uint64_t pred_val
= value
;
1636 uint64_t va
= radv_buffer_get_va(image
->bo
);
1637 va
+= image
->offset
+ image
->dcc_pred_offset
;
1639 assert(radv_image_has_dcc(image
));
1641 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1642 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
1643 S_370_WR_CONFIRM(1) |
1644 S_370_ENGINE_SEL(V_370_PFP
));
1645 radeon_emit(cmd_buffer
->cs
, va
);
1646 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1647 radeon_emit(cmd_buffer
->cs
, pred_val
);
1648 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1652 * Update the fast clear color values if the image is bound as a color buffer.
1655 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1656 struct radv_image
*image
,
1658 uint32_t color_values
[2])
1660 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1661 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1662 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1663 struct radv_attachment_info
*att
;
1666 if (!framebuffer
|| !subpass
)
1669 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
1670 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1673 att
= &framebuffer
->attachments
[att_idx
];
1674 if (att
->attachment
->image
!= image
)
1677 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
1678 radeon_emit(cs
, color_values
[0]);
1679 radeon_emit(cs
, color_values
[1]);
1681 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1685 * Set the clear color values to the image's metadata.
1688 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1689 struct radv_image
*image
,
1690 uint32_t color_values
[2])
1692 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1693 uint64_t va
= radv_buffer_get_va(image
->bo
);
1695 va
+= image
->offset
+ image
->clear_value_offset
;
1697 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1699 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 4, cmd_buffer
->state
.predicating
));
1700 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1701 S_370_WR_CONFIRM(1) |
1702 S_370_ENGINE_SEL(V_370_PFP
));
1703 radeon_emit(cs
, va
);
1704 radeon_emit(cs
, va
>> 32);
1705 radeon_emit(cs
, color_values
[0]);
1706 radeon_emit(cs
, color_values
[1]);
1710 * Update the clear color values for this image.
1713 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1714 struct radv_image
*image
,
1716 uint32_t color_values
[2])
1718 assert(radv_image_has_cmask(image
) || radv_image_has_dcc(image
));
1720 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
1722 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
1727 * Load the clear color values from the image's metadata.
1730 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1731 struct radv_image
*image
,
1734 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1735 uint64_t va
= radv_buffer_get_va(image
->bo
);
1737 va
+= image
->offset
+ image
->clear_value_offset
;
1739 if (!radv_image_has_cmask(image
) && !radv_image_has_dcc(image
))
1742 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
1744 if (cmd_buffer
->device
->physical_device
->has_load_ctx_reg_pkt
) {
1745 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG
, 3, cmd_buffer
->state
.predicating
));
1746 radeon_emit(cs
, va
);
1747 radeon_emit(cs
, va
>> 32);
1748 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
1751 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1752 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1753 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1754 COPY_DATA_COUNT_SEL
);
1755 radeon_emit(cs
, va
);
1756 radeon_emit(cs
, va
>> 32);
1757 radeon_emit(cs
, reg
>> 2);
1760 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1766 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1769 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1770 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1771 unsigned num_bpp64_colorbufs
= 0;
1773 /* this may happen for inherited secondary recording */
1777 for (i
= 0; i
< 8; ++i
) {
1778 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1779 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1780 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1784 int idx
= subpass
->color_attachments
[i
].attachment
;
1785 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1786 struct radv_image
*image
= att
->attachment
->image
;
1787 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
1789 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1791 assert(att
->attachment
->aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
| VK_IMAGE_ASPECT_PLANE_0_BIT
|
1792 VK_IMAGE_ASPECT_PLANE_1_BIT
| VK_IMAGE_ASPECT_PLANE_2_BIT
));
1793 radv_emit_fb_color_state(cmd_buffer
, i
, att
, image
, layout
);
1795 radv_load_color_clear_metadata(cmd_buffer
, image
, i
);
1797 if (image
->planes
[0].surface
.bpe
>= 8)
1798 num_bpp64_colorbufs
++;
1801 if (subpass
->depth_stencil_attachment
) {
1802 int idx
= subpass
->depth_stencil_attachment
->attachment
;
1803 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1804 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1805 struct radv_image
*image
= att
->attachment
->image
;
1806 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
);
1807 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1808 cmd_buffer
->queue_family_index
,
1809 cmd_buffer
->queue_family_index
);
1810 /* We currently don't support writing decompressed HTILE */
1811 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1812 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1814 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1816 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1817 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1818 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1820 radv_load_ds_clear_metadata(cmd_buffer
, image
);
1822 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1823 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1825 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1827 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1828 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1830 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1831 S_028208_BR_X(framebuffer
->width
) |
1832 S_028208_BR_Y(framebuffer
->height
));
1834 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
) {
1835 uint8_t watermark
= 4; /* Default value for GFX8. */
1837 /* For optimal DCC performance. */
1838 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1839 if (num_bpp64_colorbufs
>= 5) {
1846 radeon_set_context_reg(cmd_buffer
->cs
, R_028424_CB_DCC_CONTROL
,
1847 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1848 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
));
1851 if (cmd_buffer
->device
->dfsm_allowed
) {
1852 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1853 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1856 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
1860 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1862 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1863 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1865 if (state
->index_type
!= state
->last_index_type
) {
1866 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1867 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
1868 2, state
->index_type
);
1870 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1871 radeon_emit(cs
, state
->index_type
);
1874 state
->last_index_type
= state
->index_type
;
1877 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
1878 radeon_emit(cs
, state
->index_va
);
1879 radeon_emit(cs
, state
->index_va
>> 32);
1881 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1882 radeon_emit(cs
, state
->max_index_count
);
1884 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
1887 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1889 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
1890 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1891 uint32_t pa_sc_mode_cntl_1
=
1892 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
1893 uint32_t db_count_control
;
1895 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1896 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1897 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1898 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1899 has_perfect_queries
) {
1900 /* Re-enable out-of-order rasterization if the
1901 * bound pipeline supports it and if it's has
1902 * been disabled before starting any perfect
1903 * occlusion queries.
1905 radeon_set_context_reg(cmd_buffer
->cs
,
1906 R_028A4C_PA_SC_MODE_CNTL_1
,
1910 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1912 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1913 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
1915 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1917 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries
) |
1918 S_028004_SAMPLE_RATE(sample_rate
) |
1919 S_028004_ZPASS_ENABLE(1) |
1920 S_028004_SLICE_EVEN_ENABLE(1) |
1921 S_028004_SLICE_ODD_ENABLE(1);
1923 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
1924 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
1925 has_perfect_queries
) {
1926 /* If the bound pipeline has enabled
1927 * out-of-order rasterization, we should
1928 * disable it before starting any perfect
1929 * occlusion queries.
1931 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
1933 radeon_set_context_reg(cmd_buffer
->cs
,
1934 R_028A4C_PA_SC_MODE_CNTL_1
,
1938 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1939 S_028004_SAMPLE_RATE(sample_rate
);
1943 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1945 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1949 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1951 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
1953 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1954 radv_emit_viewport(cmd_buffer
);
1956 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
1957 !cmd_buffer
->device
->physical_device
->has_scissor_bug
)
1958 radv_emit_scissor(cmd_buffer
);
1960 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
1961 radv_emit_line_width(cmd_buffer
);
1963 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1964 radv_emit_blend_constants(cmd_buffer
);
1966 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1967 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1968 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
1969 radv_emit_stencil(cmd_buffer
);
1971 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
1972 radv_emit_depth_bounds(cmd_buffer
);
1974 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
1975 radv_emit_depth_bias(cmd_buffer
);
1977 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
1978 radv_emit_discard_rectangle(cmd_buffer
);
1980 if (states
& RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
)
1981 radv_emit_sample_locations(cmd_buffer
);
1983 cmd_buffer
->state
.dirty
&= ~states
;
1987 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1988 VkPipelineBindPoint bind_point
)
1990 struct radv_descriptor_state
*descriptors_state
=
1991 radv_get_descriptors_state(cmd_buffer
, bind_point
);
1992 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
1995 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
2000 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2001 set
->va
+= bo_offset
;
2005 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
2006 VkPipelineBindPoint bind_point
)
2008 struct radv_descriptor_state
*descriptors_state
=
2009 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2010 uint32_t size
= MAX_SETS
* 4;
2014 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
2015 256, &offset
, &ptr
))
2018 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2019 uint32_t *uptr
= ((uint32_t *)ptr
) + i
;
2020 uint64_t set_va
= 0;
2021 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
2022 if (descriptors_state
->valid
& (1u << i
))
2024 uptr
[0] = set_va
& 0xffffffff;
2027 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2030 if (cmd_buffer
->state
.pipeline
) {
2031 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
2032 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2033 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2035 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
2036 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
2037 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2039 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
2040 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2041 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2043 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2044 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
2045 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2047 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2048 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
2049 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2052 if (cmd_buffer
->state
.compute_pipeline
)
2053 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
2054 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2058 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2059 VkShaderStageFlags stages
)
2061 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2062 VK_PIPELINE_BIND_POINT_COMPUTE
:
2063 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2064 struct radv_descriptor_state
*descriptors_state
=
2065 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2066 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2067 bool flush_indirect_descriptors
;
2069 if (!descriptors_state
->dirty
)
2072 if (descriptors_state
->push_dirty
)
2073 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
2075 flush_indirect_descriptors
=
2076 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
2077 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
2078 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
2079 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
2081 if (flush_indirect_descriptors
)
2082 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
2084 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2086 MAX_SETS
* MESA_SHADER_STAGES
* 4);
2088 if (cmd_buffer
->state
.pipeline
) {
2089 radv_foreach_stage(stage
, stages
) {
2090 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
2093 radv_emit_descriptor_pointers(cmd_buffer
,
2094 cmd_buffer
->state
.pipeline
,
2095 descriptors_state
, stage
);
2099 if (cmd_buffer
->state
.compute_pipeline
&&
2100 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
2101 radv_emit_descriptor_pointers(cmd_buffer
,
2102 cmd_buffer
->state
.compute_pipeline
,
2104 MESA_SHADER_COMPUTE
);
2107 descriptors_state
->dirty
= 0;
2108 descriptors_state
->push_dirty
= false;
2110 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2112 if (unlikely(cmd_buffer
->device
->trace_bo
))
2113 radv_save_descriptors(cmd_buffer
, bind_point
);
2117 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
2118 VkShaderStageFlags stages
)
2120 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
2121 ? cmd_buffer
->state
.compute_pipeline
2122 : cmd_buffer
->state
.pipeline
;
2123 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2124 VK_PIPELINE_BIND_POINT_COMPUTE
:
2125 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2126 struct radv_descriptor_state
*descriptors_state
=
2127 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2128 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
2129 struct radv_shader_variant
*shader
, *prev_shader
;
2130 bool need_push_constants
= false;
2135 stages
&= cmd_buffer
->push_constant_stages
;
2137 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
2140 radv_foreach_stage(stage
, stages
) {
2141 if (!pipeline
->shaders
[stage
])
2144 need_push_constants
|= pipeline
->shaders
[stage
]->info
.info
.loads_push_constants
;
2145 need_push_constants
|= pipeline
->shaders
[stage
]->info
.info
.loads_dynamic_offsets
;
2147 uint8_t base
= pipeline
->shaders
[stage
]->info
.info
.base_inline_push_consts
;
2148 uint8_t count
= pipeline
->shaders
[stage
]->info
.info
.num_inline_push_consts
;
2150 radv_emit_inline_push_consts(cmd_buffer
, pipeline
, stage
,
2151 AC_UD_INLINE_PUSH_CONSTANTS
,
2153 (uint32_t *)&cmd_buffer
->push_constants
[base
* 4]);
2156 if (need_push_constants
) {
2157 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
2158 16 * layout
->dynamic_offset_count
,
2159 256, &offset
, &ptr
))
2162 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
2163 memcpy((char*)ptr
+ layout
->push_constant_size
,
2164 descriptors_state
->dynamic_buffers
,
2165 16 * layout
->dynamic_offset_count
);
2167 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2170 MAYBE_UNUSED
unsigned cdw_max
=
2171 radeon_check_space(cmd_buffer
->device
->ws
,
2172 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
2175 radv_foreach_stage(stage
, stages
) {
2176 shader
= radv_get_shader(pipeline
, stage
);
2178 /* Avoid redundantly emitting the address for merged stages. */
2179 if (shader
&& shader
!= prev_shader
) {
2180 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
2181 AC_UD_PUSH_CONSTANTS
, va
);
2183 prev_shader
= shader
;
2186 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2189 cmd_buffer
->push_constant_stages
&= ~stages
;
2193 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2194 bool pipeline_is_dirty
)
2196 if ((pipeline_is_dirty
||
2197 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
2198 cmd_buffer
->state
.pipeline
->num_vertex_bindings
&&
2199 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.has_vertex_buffers
) {
2200 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
2204 uint32_t count
= cmd_buffer
->state
.pipeline
->num_vertex_bindings
;
2207 /* allocate some descriptor state for vertex buffers */
2208 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
2209 &vb_offset
, &vb_ptr
))
2212 for (i
= 0; i
< count
; i
++) {
2213 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
2215 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[i
].buffer
;
2216 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[i
];
2221 va
= radv_buffer_get_va(buffer
->bo
);
2223 offset
= cmd_buffer
->vertex_bindings
[i
].offset
;
2224 va
+= offset
+ buffer
->offset
;
2226 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
2227 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= GFX7
&& stride
)
2228 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
2230 desc
[2] = buffer
->size
- offset
;
2231 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2232 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2233 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2234 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2235 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
2236 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2239 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2242 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2243 AC_UD_VS_VERTEX_BUFFERS
, va
);
2245 cmd_buffer
->state
.vb_va
= va
;
2246 cmd_buffer
->state
.vb_size
= count
* 16;
2247 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
2249 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
2253 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
2255 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2256 struct radv_userdata_info
*loc
;
2259 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2260 if (!radv_get_shader(pipeline
, stage
))
2263 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
2264 AC_UD_STREAMOUT_BUFFERS
);
2265 if (loc
->sgpr_idx
== -1)
2268 base_reg
= pipeline
->user_data_0
[stage
];
2270 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2271 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2274 if (pipeline
->gs_copy_shader
) {
2275 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
2276 if (loc
->sgpr_idx
!= -1) {
2277 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2279 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2280 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2286 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
2288 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
2289 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
2290 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
2295 /* Allocate some descriptor state for streamout buffers. */
2296 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
2297 MAX_SO_BUFFERS
* 16, 256,
2298 &so_offset
, &so_ptr
))
2301 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
2302 struct radv_buffer
*buffer
= sb
[i
].buffer
;
2303 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
2305 if (!(so
->enabled_mask
& (1 << i
)))
2308 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
2312 /* Set the descriptor.
2314 * On GFX8, the format must be non-INVALID, otherwise
2315 * the buffer will be considered not bound and store
2316 * instructions will be no-ops.
2319 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2320 desc
[2] = 0xffffffff;
2321 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2322 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2323 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2324 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2325 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2328 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2331 radv_emit_streamout_buffers(cmd_buffer
, va
);
2334 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
2338 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
2340 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
2341 radv_flush_streamout_descriptors(cmd_buffer
);
2342 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2343 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2346 struct radv_draw_info
{
2348 * Number of vertices.
2353 * Index of the first vertex.
2355 int32_t vertex_offset
;
2358 * First instance id.
2360 uint32_t first_instance
;
2363 * Number of instances.
2365 uint32_t instance_count
;
2368 * First index (indexed draws only).
2370 uint32_t first_index
;
2373 * Whether it's an indexed draw.
2378 * Indirect draw parameters resource.
2380 struct radv_buffer
*indirect
;
2381 uint64_t indirect_offset
;
2385 * Draw count parameters resource.
2387 struct radv_buffer
*count_buffer
;
2388 uint64_t count_buffer_offset
;
2391 * Stream output parameters resource.
2393 struct radv_buffer
*strmout_buffer
;
2394 uint64_t strmout_buffer_offset
;
2398 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
,
2399 const struct radv_draw_info
*draw_info
)
2401 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2402 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2403 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2404 uint32_t ia_multi_vgt_param
;
2405 int32_t primitive_reset_en
;
2408 ia_multi_vgt_param
=
2409 si_get_ia_multi_vgt_param(cmd_buffer
, draw_info
->instance_count
> 1,
2410 draw_info
->indirect
,
2411 !!draw_info
->strmout_buffer
,
2412 draw_info
->indirect
? 0 : draw_info
->count
);
2414 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2415 if (info
->chip_class
>= GFX9
) {
2416 radeon_set_uconfig_reg_idx(cs
,
2417 R_030960_IA_MULTI_VGT_PARAM
,
2418 4, ia_multi_vgt_param
);
2419 } else if (info
->chip_class
>= GFX7
) {
2420 radeon_set_context_reg_idx(cs
,
2421 R_028AA8_IA_MULTI_VGT_PARAM
,
2422 1, ia_multi_vgt_param
);
2424 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2425 ia_multi_vgt_param
);
2427 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
2430 /* Primitive restart. */
2431 primitive_reset_en
=
2432 draw_info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
;
2434 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
2435 state
->last_primitive_reset_en
= primitive_reset_en
;
2436 if (info
->chip_class
>= GFX9
) {
2437 radeon_set_uconfig_reg(cs
,
2438 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
2439 primitive_reset_en
);
2441 radeon_set_context_reg(cs
,
2442 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
2443 primitive_reset_en
);
2447 if (primitive_reset_en
) {
2448 uint32_t primitive_reset_index
=
2449 state
->index_type
? 0xffffffffu
: 0xffffu
;
2451 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
2452 radeon_set_context_reg(cs
,
2453 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
2454 primitive_reset_index
);
2455 state
->last_primitive_reset_index
= primitive_reset_index
;
2459 if (draw_info
->strmout_buffer
) {
2460 uint64_t va
= radv_buffer_get_va(draw_info
->strmout_buffer
->bo
);
2462 va
+= draw_info
->strmout_buffer
->offset
+
2463 draw_info
->strmout_buffer_offset
;
2465 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
2468 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2469 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2470 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2471 COPY_DATA_WR_CONFIRM
);
2472 radeon_emit(cs
, va
);
2473 radeon_emit(cs
, va
>> 32);
2474 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
2475 radeon_emit(cs
, 0); /* unused */
2477 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, draw_info
->strmout_buffer
->bo
);
2481 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
2482 VkPipelineStageFlags src_stage_mask
)
2484 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
2485 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2486 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2487 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2488 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
2491 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
2492 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
2493 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
2494 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
2495 VK_PIPELINE_STAGE_TRANSFER_BIT
|
2496 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
2497 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
2498 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
2499 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
2500 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
2501 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
2502 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
2503 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
2504 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
2505 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
2506 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
2507 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
2511 static enum radv_cmd_flush_bits
2512 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2513 VkAccessFlags src_flags
,
2514 struct radv_image
*image
)
2516 bool flush_CB_meta
= true, flush_DB_meta
= true;
2517 enum radv_cmd_flush_bits flush_bits
= 0;
2521 if (!radv_image_has_CB_metadata(image
))
2522 flush_CB_meta
= false;
2523 if (!radv_image_has_htile(image
))
2524 flush_DB_meta
= false;
2527 for_each_bit(b
, src_flags
) {
2528 switch ((VkAccessFlagBits
)(1 << b
)) {
2529 case VK_ACCESS_SHADER_WRITE_BIT
:
2530 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
2531 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2532 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2534 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2535 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2537 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2539 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2540 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2542 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2544 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2545 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2546 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2547 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2550 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2552 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2561 static enum radv_cmd_flush_bits
2562 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2563 VkAccessFlags dst_flags
,
2564 struct radv_image
*image
)
2566 bool flush_CB_meta
= true, flush_DB_meta
= true;
2567 enum radv_cmd_flush_bits flush_bits
= 0;
2568 bool flush_CB
= true, flush_DB
= true;
2569 bool image_is_coherent
= false;
2573 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
2578 if (!radv_image_has_CB_metadata(image
))
2579 flush_CB_meta
= false;
2580 if (!radv_image_has_htile(image
))
2581 flush_DB_meta
= false;
2583 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2584 if (image
->info
.samples
== 1 &&
2585 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
2586 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
2587 !vk_format_is_stencil(image
->vk_format
)) {
2588 /* Single-sample color and single-sample depth
2589 * (not stencil) are coherent with shaders on
2592 image_is_coherent
= true;
2597 for_each_bit(b
, dst_flags
) {
2598 switch ((VkAccessFlagBits
)(1 << b
)) {
2599 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2600 case VK_ACCESS_INDEX_READ_BIT
:
2601 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
2603 case VK_ACCESS_UNIFORM_READ_BIT
:
2604 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
2606 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2607 case VK_ACCESS_TRANSFER_READ_BIT
:
2608 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2609 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
2610 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2612 case VK_ACCESS_SHADER_READ_BIT
:
2613 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
;
2615 if (!image_is_coherent
)
2616 flush_bits
|= RADV_CMD_FLAG_INV_GLOBAL_L2
;
2618 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2620 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
2622 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2624 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2626 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2628 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2637 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2638 const struct radv_subpass_barrier
*barrier
)
2640 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
2642 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2643 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2648 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
)
2650 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2651 uint32_t subpass_id
= state
->subpass
- state
->pass
->subpasses
;
2653 /* The id of this subpass shouldn't exceed the number of subpasses in
2654 * this render pass minus 1.
2656 assert(subpass_id
< state
->pass
->subpass_count
);
2660 static struct radv_sample_locations_state
*
2661 radv_get_attachment_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
2665 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2666 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
2667 struct radv_image_view
*view
= state
->framebuffer
->attachments
[att_idx
].attachment
;
2669 if (view
->image
->info
.samples
== 1)
2672 if (state
->pass
->attachments
[att_idx
].first_subpass_idx
== subpass_id
) {
2673 /* Return the initial sample locations if this is the initial
2674 * layout transition of the given subpass attachemnt.
2676 if (state
->attachments
[att_idx
].sample_location
.count
> 0)
2677 return &state
->attachments
[att_idx
].sample_location
;
2679 /* Otherwise return the subpass sample locations if defined. */
2680 if (state
->subpass_sample_locs
) {
2681 /* Because the driver sets the current subpass before
2682 * initial layout transitions, we should use the sample
2683 * locations from the previous subpass to avoid an
2684 * off-by-one problem. Otherwise, use the sample
2685 * locations for the current subpass for final layout
2691 for (uint32_t i
= 0; i
< state
->num_subpass_sample_locs
; i
++) {
2692 if (state
->subpass_sample_locs
[i
].subpass_idx
== subpass_id
)
2693 return &state
->subpass_sample_locs
[i
].sample_location
;
2701 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2702 struct radv_subpass_attachment att
,
2705 unsigned idx
= att
.attachment
;
2706 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
2707 struct radv_sample_locations_state
*sample_locs
;
2708 VkImageSubresourceRange range
;
2709 range
.aspectMask
= 0;
2710 range
.baseMipLevel
= view
->base_mip
;
2711 range
.levelCount
= 1;
2712 range
.baseArrayLayer
= view
->base_layer
;
2713 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2715 if (cmd_buffer
->state
.subpass
->view_mask
) {
2716 /* If the current subpass uses multiview, the driver might have
2717 * performed a fast color/depth clear to the whole image
2718 * (including all layers). To make sure the driver will
2719 * decompress the image correctly (if needed), we have to
2720 * account for the "real" number of layers. If the view mask is
2721 * sparse, this will decompress more layers than needed.
2723 range
.layerCount
= util_last_bit(cmd_buffer
->state
.subpass
->view_mask
);
2726 /* Get the subpass sample locations for the given attachment, if NULL
2727 * is returned the driver will use the default HW locations.
2729 sample_locs
= radv_get_attachment_sample_locations(cmd_buffer
, idx
,
2732 radv_handle_image_transition(cmd_buffer
,
2734 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2735 att
.layout
, 0, 0, &range
, sample_locs
);
2737 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2743 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2744 const struct radv_subpass
*subpass
)
2746 cmd_buffer
->state
.subpass
= subpass
;
2748 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2752 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
2753 struct radv_render_pass
*pass
,
2754 const VkRenderPassBeginInfo
*info
)
2756 const struct VkRenderPassSampleLocationsBeginInfoEXT
*sample_locs
=
2757 vk_find_struct_const(info
->pNext
,
2758 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT
);
2759 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2760 struct radv_framebuffer
*framebuffer
= state
->framebuffer
;
2763 state
->subpass_sample_locs
= NULL
;
2767 for (uint32_t i
= 0; i
< sample_locs
->attachmentInitialSampleLocationsCount
; i
++) {
2768 const VkAttachmentSampleLocationsEXT
*att_sample_locs
=
2769 &sample_locs
->pAttachmentInitialSampleLocations
[i
];
2770 uint32_t att_idx
= att_sample_locs
->attachmentIndex
;
2771 struct radv_attachment_info
*att
= &framebuffer
->attachments
[att_idx
];
2772 struct radv_image
*image
= att
->attachment
->image
;
2774 assert(vk_format_is_depth_or_stencil(image
->vk_format
));
2776 /* From the Vulkan spec 1.1.108:
2778 * "If the image referenced by the framebuffer attachment at
2779 * index attachmentIndex was not created with
2780 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2781 * then the values specified in sampleLocationsInfo are
2784 if (!(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
))
2787 const VkSampleLocationsInfoEXT
*sample_locs_info
=
2788 &att_sample_locs
->sampleLocationsInfo
;
2790 state
->attachments
[att_idx
].sample_location
.per_pixel
=
2791 sample_locs_info
->sampleLocationsPerPixel
;
2792 state
->attachments
[att_idx
].sample_location
.grid_size
=
2793 sample_locs_info
->sampleLocationGridSize
;
2794 state
->attachments
[att_idx
].sample_location
.count
=
2795 sample_locs_info
->sampleLocationsCount
;
2796 typed_memcpy(&state
->attachments
[att_idx
].sample_location
.locations
[0],
2797 sample_locs_info
->pSampleLocations
,
2798 sample_locs_info
->sampleLocationsCount
);
2801 state
->subpass_sample_locs
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2802 sample_locs
->postSubpassSampleLocationsCount
*
2803 sizeof(state
->subpass_sample_locs
[0]),
2804 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2805 if (state
->subpass_sample_locs
== NULL
) {
2806 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2807 return cmd_buffer
->record_result
;
2810 state
->num_subpass_sample_locs
= sample_locs
->postSubpassSampleLocationsCount
;
2812 for (uint32_t i
= 0; i
< sample_locs
->postSubpassSampleLocationsCount
; i
++) {
2813 const VkSubpassSampleLocationsEXT
*subpass_sample_locs_info
=
2814 &sample_locs
->pPostSubpassSampleLocations
[i
];
2815 const VkSampleLocationsInfoEXT
*sample_locs_info
=
2816 &subpass_sample_locs_info
->sampleLocationsInfo
;
2818 state
->subpass_sample_locs
[i
].subpass_idx
=
2819 subpass_sample_locs_info
->subpassIndex
;
2820 state
->subpass_sample_locs
[i
].sample_location
.per_pixel
=
2821 sample_locs_info
->sampleLocationsPerPixel
;
2822 state
->subpass_sample_locs
[i
].sample_location
.grid_size
=
2823 sample_locs_info
->sampleLocationGridSize
;
2824 state
->subpass_sample_locs
[i
].sample_location
.count
=
2825 sample_locs_info
->sampleLocationsCount
;
2826 typed_memcpy(&state
->subpass_sample_locs
[i
].sample_location
.locations
[0],
2827 sample_locs_info
->pSampleLocations
,
2828 sample_locs_info
->sampleLocationsCount
);
2835 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
2836 struct radv_render_pass
*pass
,
2837 const VkRenderPassBeginInfo
*info
)
2839 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2841 if (pass
->attachment_count
== 0) {
2842 state
->attachments
= NULL
;
2846 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2847 pass
->attachment_count
*
2848 sizeof(state
->attachments
[0]),
2849 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2850 if (state
->attachments
== NULL
) {
2851 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2852 return cmd_buffer
->record_result
;
2855 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
2856 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
2857 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
2858 VkImageAspectFlags clear_aspects
= 0;
2860 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2861 /* color attachment */
2862 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2863 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
2866 /* depthstencil attachment */
2867 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2868 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2869 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
2870 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2871 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
2872 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2874 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2875 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2876 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2880 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
2881 state
->attachments
[i
].cleared_views
= 0;
2882 if (clear_aspects
&& info
) {
2883 assert(info
->clearValueCount
> i
);
2884 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
2887 state
->attachments
[i
].current_layout
= att
->initial_layout
;
2888 state
->attachments
[i
].sample_location
.count
= 0;
2894 VkResult
radv_AllocateCommandBuffers(
2896 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
2897 VkCommandBuffer
*pCommandBuffers
)
2899 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2900 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
2902 VkResult result
= VK_SUCCESS
;
2905 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
2907 if (!list_empty(&pool
->free_cmd_buffers
)) {
2908 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
2910 list_del(&cmd_buffer
->pool_link
);
2911 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
2913 result
= radv_reset_cmd_buffer(cmd_buffer
);
2914 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2915 cmd_buffer
->level
= pAllocateInfo
->level
;
2917 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
2919 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
2920 &pCommandBuffers
[i
]);
2922 if (result
!= VK_SUCCESS
)
2926 if (result
!= VK_SUCCESS
) {
2927 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
2928 i
, pCommandBuffers
);
2930 /* From the Vulkan 1.0.66 spec:
2932 * "vkAllocateCommandBuffers can be used to create multiple
2933 * command buffers. If the creation of any of those command
2934 * buffers fails, the implementation must destroy all
2935 * successfully created command buffer objects from this
2936 * command, set all entries of the pCommandBuffers array to
2937 * NULL and return the error."
2939 memset(pCommandBuffers
, 0,
2940 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
2946 void radv_FreeCommandBuffers(
2948 VkCommandPool commandPool
,
2949 uint32_t commandBufferCount
,
2950 const VkCommandBuffer
*pCommandBuffers
)
2952 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2953 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
2956 if (cmd_buffer
->pool
) {
2957 list_del(&cmd_buffer
->pool_link
);
2958 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
2960 radv_cmd_buffer_destroy(cmd_buffer
);
2966 VkResult
radv_ResetCommandBuffer(
2967 VkCommandBuffer commandBuffer
,
2968 VkCommandBufferResetFlags flags
)
2970 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2971 return radv_reset_cmd_buffer(cmd_buffer
);
2974 VkResult
radv_BeginCommandBuffer(
2975 VkCommandBuffer commandBuffer
,
2976 const VkCommandBufferBeginInfo
*pBeginInfo
)
2978 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2979 VkResult result
= VK_SUCCESS
;
2981 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
2982 /* If the command buffer has already been resetted with
2983 * vkResetCommandBuffer, no need to do it again.
2985 result
= radv_reset_cmd_buffer(cmd_buffer
);
2986 if (result
!= VK_SUCCESS
)
2990 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
2991 cmd_buffer
->state
.last_primitive_reset_en
= -1;
2992 cmd_buffer
->state
.last_index_type
= -1;
2993 cmd_buffer
->state
.last_num_instances
= -1;
2994 cmd_buffer
->state
.last_vertex_offset
= -1;
2995 cmd_buffer
->state
.last_first_instance
= -1;
2996 cmd_buffer
->state
.predication_type
= -1;
2997 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
2999 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
3000 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
3001 assert(pBeginInfo
->pInheritanceInfo
);
3002 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
3003 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
3005 struct radv_subpass
*subpass
=
3006 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
3008 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
3009 if (result
!= VK_SUCCESS
)
3012 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
3015 if (unlikely(cmd_buffer
->device
->trace_bo
)) {
3016 struct radv_device
*device
= cmd_buffer
->device
;
3018 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
,
3021 radv_cmd_buffer_trace_emit(cmd_buffer
);
3024 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
3029 void radv_CmdBindVertexBuffers(
3030 VkCommandBuffer commandBuffer
,
3031 uint32_t firstBinding
,
3032 uint32_t bindingCount
,
3033 const VkBuffer
* pBuffers
,
3034 const VkDeviceSize
* pOffsets
)
3036 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3037 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
3038 bool changed
= false;
3040 /* We have to defer setting up vertex buffer since we need the buffer
3041 * stride from the pipeline. */
3043 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
3044 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
3045 uint32_t idx
= firstBinding
+ i
;
3048 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
3049 vb
[idx
].offset
!= pOffsets
[i
])) {
3053 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
3054 vb
[idx
].offset
= pOffsets
[i
];
3056 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3057 vb
[idx
].buffer
->bo
);
3061 /* No state changes. */
3065 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
3068 void radv_CmdBindIndexBuffer(
3069 VkCommandBuffer commandBuffer
,
3071 VkDeviceSize offset
,
3072 VkIndexType indexType
)
3074 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3075 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
3077 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
3078 cmd_buffer
->state
.index_offset
== offset
&&
3079 cmd_buffer
->state
.index_type
== indexType
) {
3080 /* No state changes. */
3084 cmd_buffer
->state
.index_buffer
= index_buffer
;
3085 cmd_buffer
->state
.index_offset
= offset
;
3086 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
3087 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
3088 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
3090 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
3091 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
3092 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3093 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
3098 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3099 VkPipelineBindPoint bind_point
,
3100 struct radv_descriptor_set
*set
, unsigned idx
)
3102 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3104 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
3107 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
3109 if (!cmd_buffer
->device
->use_global_bo_list
) {
3110 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
3111 if (set
->descriptors
[j
])
3112 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
3116 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
3119 void radv_CmdBindDescriptorSets(
3120 VkCommandBuffer commandBuffer
,
3121 VkPipelineBindPoint pipelineBindPoint
,
3122 VkPipelineLayout _layout
,
3124 uint32_t descriptorSetCount
,
3125 const VkDescriptorSet
* pDescriptorSets
,
3126 uint32_t dynamicOffsetCount
,
3127 const uint32_t* pDynamicOffsets
)
3129 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3130 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3131 unsigned dyn_idx
= 0;
3133 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
3134 struct radv_descriptor_state
*descriptors_state
=
3135 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3137 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
3138 unsigned idx
= i
+ firstSet
;
3139 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
3140 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
3142 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
3143 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
3144 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
3145 assert(dyn_idx
< dynamicOffsetCount
);
3147 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
3148 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
3150 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
3151 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
3152 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3153 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3154 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3155 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3156 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3157 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3158 cmd_buffer
->push_constant_stages
|=
3159 set
->layout
->dynamic_shader_stages
;
3164 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3165 struct radv_descriptor_set
*set
,
3166 struct radv_descriptor_set_layout
*layout
,
3167 VkPipelineBindPoint bind_point
)
3169 struct radv_descriptor_state
*descriptors_state
=
3170 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3171 set
->size
= layout
->size
;
3172 set
->layout
= layout
;
3174 if (descriptors_state
->push_set
.capacity
< set
->size
) {
3175 size_t new_size
= MAX2(set
->size
, 1024);
3176 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
3177 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
3179 free(set
->mapped_ptr
);
3180 set
->mapped_ptr
= malloc(new_size
);
3182 if (!set
->mapped_ptr
) {
3183 descriptors_state
->push_set
.capacity
= 0;
3184 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3188 descriptors_state
->push_set
.capacity
= new_size
;
3194 void radv_meta_push_descriptor_set(
3195 struct radv_cmd_buffer
* cmd_buffer
,
3196 VkPipelineBindPoint pipelineBindPoint
,
3197 VkPipelineLayout _layout
,
3199 uint32_t descriptorWriteCount
,
3200 const VkWriteDescriptorSet
* pDescriptorWrites
)
3202 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3203 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
3207 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3209 push_set
->size
= layout
->set
[set
].layout
->size
;
3210 push_set
->layout
= layout
->set
[set
].layout
;
3212 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
3214 (void**) &push_set
->mapped_ptr
))
3217 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
3218 push_set
->va
+= bo_offset
;
3220 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3221 radv_descriptor_set_to_handle(push_set
),
3222 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3224 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3227 void radv_CmdPushDescriptorSetKHR(
3228 VkCommandBuffer commandBuffer
,
3229 VkPipelineBindPoint pipelineBindPoint
,
3230 VkPipelineLayout _layout
,
3232 uint32_t descriptorWriteCount
,
3233 const VkWriteDescriptorSet
* pDescriptorWrites
)
3235 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3236 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3237 struct radv_descriptor_state
*descriptors_state
=
3238 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3239 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3241 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3243 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3244 layout
->set
[set
].layout
,
3248 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3249 * because it is invalid, according to Vulkan spec.
3251 for (int i
= 0; i
< descriptorWriteCount
; i
++) {
3252 MAYBE_UNUSED
const VkWriteDescriptorSet
*writeset
= &pDescriptorWrites
[i
];
3253 assert(writeset
->descriptorType
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
);
3256 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3257 radv_descriptor_set_to_handle(push_set
),
3258 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3260 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3261 descriptors_state
->push_dirty
= true;
3264 void radv_CmdPushDescriptorSetWithTemplateKHR(
3265 VkCommandBuffer commandBuffer
,
3266 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
3267 VkPipelineLayout _layout
,
3271 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3272 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3273 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
3274 struct radv_descriptor_state
*descriptors_state
=
3275 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
3276 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3278 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3280 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3281 layout
->set
[set
].layout
,
3285 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
3286 descriptorUpdateTemplate
, pData
);
3288 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
3289 descriptors_state
->push_dirty
= true;
3292 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
3293 VkPipelineLayout layout
,
3294 VkShaderStageFlags stageFlags
,
3297 const void* pValues
)
3299 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3300 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
3301 cmd_buffer
->push_constant_stages
|= stageFlags
;
3304 VkResult
radv_EndCommandBuffer(
3305 VkCommandBuffer commandBuffer
)
3307 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3309 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
3310 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX6
)
3311 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3313 /* Make sure to sync all pending active queries at the end of
3316 cmd_buffer
->state
.flush_bits
|= cmd_buffer
->active_query_flush_bits
;
3318 si_emit_cache_flush(cmd_buffer
);
3321 /* Make sure CP DMA is idle at the end of IBs because the kernel
3322 * doesn't wait for it.
3324 si_cp_dma_wait_for_idle(cmd_buffer
);
3326 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3327 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
3329 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
3330 return vk_error(cmd_buffer
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3332 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
3334 return cmd_buffer
->record_result
;
3338 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
3340 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3342 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
3345 assert(!pipeline
->ctx_cs
.cdw
);
3347 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
3349 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
3350 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
3352 cmd_buffer
->compute_scratch_size_needed
=
3353 MAX2(cmd_buffer
->compute_scratch_size_needed
,
3354 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
3356 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3357 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
3359 if (unlikely(cmd_buffer
->device
->trace_bo
))
3360 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
3363 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
3364 VkPipelineBindPoint bind_point
)
3366 struct radv_descriptor_state
*descriptors_state
=
3367 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3369 descriptors_state
->dirty
|= descriptors_state
->valid
;
3372 void radv_CmdBindPipeline(
3373 VkCommandBuffer commandBuffer
,
3374 VkPipelineBindPoint pipelineBindPoint
,
3375 VkPipeline _pipeline
)
3377 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3378 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
3380 switch (pipelineBindPoint
) {
3381 case VK_PIPELINE_BIND_POINT_COMPUTE
:
3382 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
3384 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3386 cmd_buffer
->state
.compute_pipeline
= pipeline
;
3387 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3389 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
3390 if (cmd_buffer
->state
.pipeline
== pipeline
)
3392 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
3394 cmd_buffer
->state
.pipeline
= pipeline
;
3398 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
3399 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
3401 /* the new vertex shader might not have the same user regs */
3402 cmd_buffer
->state
.last_first_instance
= -1;
3403 cmd_buffer
->state
.last_vertex_offset
= -1;
3405 /* Prefetch all pipeline shaders at first draw time. */
3406 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
3408 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
3409 radv_bind_streamout_state(cmd_buffer
, pipeline
);
3411 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
3412 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
3413 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
3414 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
3416 if (radv_pipeline_has_tess(pipeline
))
3417 cmd_buffer
->tess_rings_needed
= true;
3420 assert(!"invalid bind point");
3425 void radv_CmdSetViewport(
3426 VkCommandBuffer commandBuffer
,
3427 uint32_t firstViewport
,
3428 uint32_t viewportCount
,
3429 const VkViewport
* pViewports
)
3431 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3432 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3433 MAYBE_UNUSED
const uint32_t total_count
= firstViewport
+ viewportCount
;
3435 assert(firstViewport
< MAX_VIEWPORTS
);
3436 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
3438 if (!memcmp(state
->dynamic
.viewport
.viewports
+ firstViewport
,
3439 pViewports
, viewportCount
* sizeof(*pViewports
))) {
3443 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
3444 viewportCount
* sizeof(*pViewports
));
3446 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
3449 void radv_CmdSetScissor(
3450 VkCommandBuffer commandBuffer
,
3451 uint32_t firstScissor
,
3452 uint32_t scissorCount
,
3453 const VkRect2D
* pScissors
)
3455 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3456 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3457 MAYBE_UNUSED
const uint32_t total_count
= firstScissor
+ scissorCount
;
3459 assert(firstScissor
< MAX_SCISSORS
);
3460 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
3462 if (!memcmp(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3463 scissorCount
* sizeof(*pScissors
))) {
3467 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
3468 scissorCount
* sizeof(*pScissors
));
3470 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
3473 void radv_CmdSetLineWidth(
3474 VkCommandBuffer commandBuffer
,
3477 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3479 if (cmd_buffer
->state
.dynamic
.line_width
== lineWidth
)
3482 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
3483 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
3486 void radv_CmdSetDepthBias(
3487 VkCommandBuffer commandBuffer
,
3488 float depthBiasConstantFactor
,
3489 float depthBiasClamp
,
3490 float depthBiasSlopeFactor
)
3492 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3493 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3495 if (state
->dynamic
.depth_bias
.bias
== depthBiasConstantFactor
&&
3496 state
->dynamic
.depth_bias
.clamp
== depthBiasClamp
&&
3497 state
->dynamic
.depth_bias
.slope
== depthBiasSlopeFactor
) {
3501 state
->dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
3502 state
->dynamic
.depth_bias
.clamp
= depthBiasClamp
;
3503 state
->dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
3505 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
3508 void radv_CmdSetBlendConstants(
3509 VkCommandBuffer commandBuffer
,
3510 const float blendConstants
[4])
3512 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3513 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3515 if (!memcmp(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4))
3518 memcpy(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4);
3520 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
3523 void radv_CmdSetDepthBounds(
3524 VkCommandBuffer commandBuffer
,
3525 float minDepthBounds
,
3526 float maxDepthBounds
)
3528 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3529 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3531 if (state
->dynamic
.depth_bounds
.min
== minDepthBounds
&&
3532 state
->dynamic
.depth_bounds
.max
== maxDepthBounds
) {
3536 state
->dynamic
.depth_bounds
.min
= minDepthBounds
;
3537 state
->dynamic
.depth_bounds
.max
= maxDepthBounds
;
3539 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
3542 void radv_CmdSetStencilCompareMask(
3543 VkCommandBuffer commandBuffer
,
3544 VkStencilFaceFlags faceMask
,
3545 uint32_t compareMask
)
3547 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3548 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3549 bool front_same
= state
->dynamic
.stencil_compare_mask
.front
== compareMask
;
3550 bool back_same
= state
->dynamic
.stencil_compare_mask
.back
== compareMask
;
3552 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3553 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3557 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3558 state
->dynamic
.stencil_compare_mask
.front
= compareMask
;
3559 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3560 state
->dynamic
.stencil_compare_mask
.back
= compareMask
;
3562 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
3565 void radv_CmdSetStencilWriteMask(
3566 VkCommandBuffer commandBuffer
,
3567 VkStencilFaceFlags faceMask
,
3570 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3571 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3572 bool front_same
= state
->dynamic
.stencil_write_mask
.front
== writeMask
;
3573 bool back_same
= state
->dynamic
.stencil_write_mask
.back
== writeMask
;
3575 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3576 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3580 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3581 state
->dynamic
.stencil_write_mask
.front
= writeMask
;
3582 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3583 state
->dynamic
.stencil_write_mask
.back
= writeMask
;
3585 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
3588 void radv_CmdSetStencilReference(
3589 VkCommandBuffer commandBuffer
,
3590 VkStencilFaceFlags faceMask
,
3593 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3594 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3595 bool front_same
= state
->dynamic
.stencil_reference
.front
== reference
;
3596 bool back_same
= state
->dynamic
.stencil_reference
.back
== reference
;
3598 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
3599 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
3603 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
3604 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
3605 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
3606 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
3608 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
3611 void radv_CmdSetDiscardRectangleEXT(
3612 VkCommandBuffer commandBuffer
,
3613 uint32_t firstDiscardRectangle
,
3614 uint32_t discardRectangleCount
,
3615 const VkRect2D
* pDiscardRectangles
)
3617 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3618 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3619 MAYBE_UNUSED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
3621 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
3622 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
3624 if (!memcmp(state
->dynamic
.discard_rectangle
.rectangles
+ firstDiscardRectangle
,
3625 pDiscardRectangles
, discardRectangleCount
* sizeof(*pDiscardRectangles
))) {
3629 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
3630 pDiscardRectangles
, discardRectangleCount
);
3632 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
3635 void radv_CmdSetSampleLocationsEXT(
3636 VkCommandBuffer commandBuffer
,
3637 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
3639 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3640 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3642 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
3644 state
->dynamic
.sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
3645 state
->dynamic
.sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
3646 state
->dynamic
.sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
3647 typed_memcpy(&state
->dynamic
.sample_location
.locations
[0],
3648 pSampleLocationsInfo
->pSampleLocations
,
3649 pSampleLocationsInfo
->sampleLocationsCount
);
3651 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
;
3654 void radv_CmdExecuteCommands(
3655 VkCommandBuffer commandBuffer
,
3656 uint32_t commandBufferCount
,
3657 const VkCommandBuffer
* pCmdBuffers
)
3659 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
3661 assert(commandBufferCount
> 0);
3663 /* Emit pending flushes on primary prior to executing secondary */
3664 si_emit_cache_flush(primary
);
3666 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3667 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
3669 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
3670 secondary
->scratch_size_needed
);
3671 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
3672 secondary
->compute_scratch_size_needed
);
3674 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
3675 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
3676 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
3677 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
3678 if (secondary
->tess_rings_needed
)
3679 primary
->tess_rings_needed
= true;
3680 if (secondary
->sample_positions_needed
)
3681 primary
->sample_positions_needed
= true;
3683 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
3686 /* When the secondary command buffer is compute only we don't
3687 * need to re-emit the current graphics pipeline.
3689 if (secondary
->state
.emitted_pipeline
) {
3690 primary
->state
.emitted_pipeline
=
3691 secondary
->state
.emitted_pipeline
;
3694 /* When the secondary command buffer is graphics only we don't
3695 * need to re-emit the current compute pipeline.
3697 if (secondary
->state
.emitted_compute_pipeline
) {
3698 primary
->state
.emitted_compute_pipeline
=
3699 secondary
->state
.emitted_compute_pipeline
;
3702 /* Only re-emit the draw packets when needed. */
3703 if (secondary
->state
.last_primitive_reset_en
!= -1) {
3704 primary
->state
.last_primitive_reset_en
=
3705 secondary
->state
.last_primitive_reset_en
;
3708 if (secondary
->state
.last_primitive_reset_index
) {
3709 primary
->state
.last_primitive_reset_index
=
3710 secondary
->state
.last_primitive_reset_index
;
3713 if (secondary
->state
.last_ia_multi_vgt_param
) {
3714 primary
->state
.last_ia_multi_vgt_param
=
3715 secondary
->state
.last_ia_multi_vgt_param
;
3718 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
3719 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
3720 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
3722 if (secondary
->state
.last_index_type
!= -1) {
3723 primary
->state
.last_index_type
=
3724 secondary
->state
.last_index_type
;
3728 /* After executing commands from secondary buffers we have to dirty
3731 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
3732 RADV_CMD_DIRTY_INDEX_BUFFER
|
3733 RADV_CMD_DIRTY_DYNAMIC_ALL
;
3734 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
3735 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
3738 VkResult
radv_CreateCommandPool(
3740 const VkCommandPoolCreateInfo
* pCreateInfo
,
3741 const VkAllocationCallbacks
* pAllocator
,
3742 VkCommandPool
* pCmdPool
)
3744 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3745 struct radv_cmd_pool
*pool
;
3747 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
3748 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3750 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3753 pool
->alloc
= *pAllocator
;
3755 pool
->alloc
= device
->alloc
;
3757 list_inithead(&pool
->cmd_buffers
);
3758 list_inithead(&pool
->free_cmd_buffers
);
3760 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
3762 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
3768 void radv_DestroyCommandPool(
3770 VkCommandPool commandPool
,
3771 const VkAllocationCallbacks
* pAllocator
)
3773 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3774 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3779 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3780 &pool
->cmd_buffers
, pool_link
) {
3781 radv_cmd_buffer_destroy(cmd_buffer
);
3784 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3785 &pool
->free_cmd_buffers
, pool_link
) {
3786 radv_cmd_buffer_destroy(cmd_buffer
);
3789 vk_free2(&device
->alloc
, pAllocator
, pool
);
3792 VkResult
radv_ResetCommandPool(
3794 VkCommandPool commandPool
,
3795 VkCommandPoolResetFlags flags
)
3797 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3800 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
3801 &pool
->cmd_buffers
, pool_link
) {
3802 result
= radv_reset_cmd_buffer(cmd_buffer
);
3803 if (result
!= VK_SUCCESS
)
3810 void radv_TrimCommandPool(
3812 VkCommandPool commandPool
,
3813 VkCommandPoolTrimFlags flags
)
3815 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3820 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3821 &pool
->free_cmd_buffers
, pool_link
) {
3822 radv_cmd_buffer_destroy(cmd_buffer
);
3827 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer
*cmd_buffer
,
3828 uint32_t subpass_id
)
3830 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3831 struct radv_subpass
*subpass
= &state
->pass
->subpasses
[subpass_id
];
3833 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
3834 cmd_buffer
->cs
, 4096);
3836 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
3838 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
3840 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3841 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3842 if (a
== VK_ATTACHMENT_UNUSED
)
3845 radv_handle_subpass_image_transition(cmd_buffer
,
3846 subpass
->attachments
[i
],
3850 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3852 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3856 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer
*cmd_buffer
)
3858 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3859 const struct radv_subpass
*subpass
= state
->subpass
;
3860 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
3862 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3864 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3865 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3866 if (a
== VK_ATTACHMENT_UNUSED
)
3869 if (state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
3872 VkImageLayout layout
= state
->pass
->attachments
[a
].final_layout
;
3873 struct radv_subpass_attachment att
= { a
, layout
};
3874 radv_handle_subpass_image_transition(cmd_buffer
, att
, false);
3878 void radv_CmdBeginRenderPass(
3879 VkCommandBuffer commandBuffer
,
3880 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3881 VkSubpassContents contents
)
3883 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3884 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3885 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3888 cmd_buffer
->state
.framebuffer
= framebuffer
;
3889 cmd_buffer
->state
.pass
= pass
;
3890 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3892 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
3893 if (result
!= VK_SUCCESS
)
3896 result
= radv_cmd_state_setup_sample_locations(cmd_buffer
, pass
, pRenderPassBegin
);
3897 if (result
!= VK_SUCCESS
)
3900 radv_cmd_buffer_begin_subpass(cmd_buffer
, 0);
3903 void radv_CmdBeginRenderPass2KHR(
3904 VkCommandBuffer commandBuffer
,
3905 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
3906 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
3908 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
3909 pSubpassBeginInfo
->contents
);
3912 void radv_CmdNextSubpass(
3913 VkCommandBuffer commandBuffer
,
3914 VkSubpassContents contents
)
3916 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3918 uint32_t prev_subpass
= radv_get_subpass_id(cmd_buffer
);
3919 radv_cmd_buffer_end_subpass(cmd_buffer
);
3920 radv_cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
3923 void radv_CmdNextSubpass2KHR(
3924 VkCommandBuffer commandBuffer
,
3925 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
3926 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3928 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
3931 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
3933 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
3934 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
3935 if (!radv_get_shader(pipeline
, stage
))
3938 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
3939 if (loc
->sgpr_idx
== -1)
3941 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
3942 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3945 if (pipeline
->gs_copy_shader
) {
3946 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
3947 if (loc
->sgpr_idx
!= -1) {
3948 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3949 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3955 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3956 uint32_t vertex_count
,
3959 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
3960 radeon_emit(cmd_buffer
->cs
, vertex_count
);
3961 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
3962 S_0287F0_USE_OPAQUE(use_opaque
));
3966 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
3968 uint32_t index_count
)
3970 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
3971 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
3972 radeon_emit(cmd_buffer
->cs
, index_va
);
3973 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
3974 radeon_emit(cmd_buffer
->cs
, index_count
);
3975 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
3979 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3981 uint32_t draw_count
,
3985 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3986 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
3987 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
3988 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
;
3989 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
3990 bool predicating
= cmd_buffer
->state
.predicating
;
3993 /* just reset draw state for vertex data */
3994 cmd_buffer
->state
.last_first_instance
= -1;
3995 cmd_buffer
->state
.last_num_instances
= -1;
3996 cmd_buffer
->state
.last_vertex_offset
= -1;
3998 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
3999 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
4000 PKT3_DRAW_INDIRECT
, 3, predicating
));
4002 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4003 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4004 radeon_emit(cs
, di_src_sel
);
4006 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
4007 PKT3_DRAW_INDIRECT_MULTI
,
4010 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
4011 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
4012 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
4013 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
4014 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
4015 radeon_emit(cs
, draw_count
); /* count */
4016 radeon_emit(cs
, count_va
); /* count_addr */
4017 radeon_emit(cs
, count_va
>> 32);
4018 radeon_emit(cs
, stride
); /* stride */
4019 radeon_emit(cs
, di_src_sel
);
4024 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
4025 const struct radv_draw_info
*info
)
4027 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4028 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4029 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4031 if (info
->indirect
) {
4032 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4033 uint64_t count_va
= 0;
4035 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4037 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4039 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
4041 radeon_emit(cs
, va
);
4042 radeon_emit(cs
, va
>> 32);
4044 if (info
->count_buffer
) {
4045 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
4046 count_va
+= info
->count_buffer
->offset
+
4047 info
->count_buffer_offset
;
4049 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
4052 if (!state
->subpass
->view_mask
) {
4053 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4060 for_each_bit(i
, state
->subpass
->view_mask
) {
4061 radv_emit_view_index(cmd_buffer
, i
);
4063 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
4071 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
4073 if (info
->vertex_offset
!= state
->last_vertex_offset
||
4074 info
->first_instance
!= state
->last_first_instance
) {
4075 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
4076 state
->pipeline
->graphics
.vtx_emit_num
);
4078 radeon_emit(cs
, info
->vertex_offset
);
4079 radeon_emit(cs
, info
->first_instance
);
4080 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
4082 state
->last_first_instance
= info
->first_instance
;
4083 state
->last_vertex_offset
= info
->vertex_offset
;
4086 if (state
->last_num_instances
!= info
->instance_count
) {
4087 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
4088 radeon_emit(cs
, info
->instance_count
);
4089 state
->last_num_instances
= info
->instance_count
;
4092 if (info
->indexed
) {
4093 int index_size
= state
->index_type
? 4 : 2;
4096 index_va
= state
->index_va
;
4097 index_va
+= info
->first_index
* index_size
;
4099 if (!state
->subpass
->view_mask
) {
4100 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4105 for_each_bit(i
, state
->subpass
->view_mask
) {
4106 radv_emit_view_index(cmd_buffer
, i
);
4108 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
4114 if (!state
->subpass
->view_mask
) {
4115 radv_cs_emit_draw_packet(cmd_buffer
,
4117 !!info
->strmout_buffer
);
4120 for_each_bit(i
, state
->subpass
->view_mask
) {
4121 radv_emit_view_index(cmd_buffer
, i
);
4123 radv_cs_emit_draw_packet(cmd_buffer
,
4125 !!info
->strmout_buffer
);
4133 * Vega and raven have a bug which triggers if there are multiple context
4134 * register contexts active at the same time with different scissor values.
4136 * There are two possible workarounds:
4137 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4138 * there is only ever 1 active set of scissor values at the same time.
4140 * 2) Whenever the hardware switches contexts we have to set the scissor
4141 * registers again even if it is a noop. That way the new context gets
4142 * the correct scissor values.
4144 * This implements option 2. radv_need_late_scissor_emission needs to
4145 * return true on affected HW if radv_emit_all_graphics_states sets
4146 * any context registers.
4148 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
4149 const struct radv_draw_info
*info
)
4151 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4153 if (!cmd_buffer
->device
->physical_device
->has_scissor_bug
)
4156 if (cmd_buffer
->state
.context_roll_without_scissor_emitted
|| info
->strmout_buffer
)
4159 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
4161 /* Index, vertex and streamout buffers don't change context regs, and
4162 * pipeline is already handled.
4164 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
|
4165 RADV_CMD_DIRTY_VERTEX_BUFFER
|
4166 RADV_CMD_DIRTY_STREAMOUT_BUFFER
|
4167 RADV_CMD_DIRTY_PIPELINE
);
4169 if (cmd_buffer
->state
.dirty
& used_states
)
4172 if (info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
&&
4173 (state
->index_type
? 0xffffffffu
: 0xffffu
) != state
->last_primitive_reset_index
)
4180 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
4181 const struct radv_draw_info
*info
)
4183 bool late_scissor_emission
;
4185 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
4186 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
4187 radv_emit_rbplus_state(cmd_buffer
);
4189 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
4190 radv_emit_graphics_pipeline(cmd_buffer
);
4192 /* This should be before the cmd_buffer->state.dirty is cleared
4193 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4194 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4195 late_scissor_emission
=
4196 radv_need_late_scissor_emission(cmd_buffer
, info
);
4198 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
4199 radv_emit_framebuffer_state(cmd_buffer
);
4201 if (info
->indexed
) {
4202 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
4203 radv_emit_index_buffer(cmd_buffer
);
4205 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4206 * so the state must be re-emitted before the next indexed
4209 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4210 cmd_buffer
->state
.last_index_type
= -1;
4211 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
4215 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
4217 radv_emit_draw_registers(cmd_buffer
, info
);
4219 if (late_scissor_emission
)
4220 radv_emit_scissor(cmd_buffer
);
4224 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
4225 const struct radv_draw_info
*info
)
4227 struct radeon_info
*rad_info
=
4228 &cmd_buffer
->device
->physical_device
->rad_info
;
4230 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4231 bool pipeline_is_dirty
=
4232 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
4233 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
4235 MAYBE_UNUSED
unsigned cdw_max
=
4236 radeon_check_space(cmd_buffer
->device
->ws
,
4237 cmd_buffer
->cs
, 4096);
4239 if (likely(!info
->indirect
)) {
4240 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4241 * no workaround for indirect draws, but we can at least skip
4244 if (unlikely(!info
->instance_count
))
4247 /* Handle count == 0. */
4248 if (unlikely(!info
->count
&& !info
->strmout_buffer
))
4252 /* Use optimal packet order based on whether we need to sync the
4255 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4256 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4257 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4258 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4259 /* If we have to wait for idle, set all states first, so that
4260 * all SET packets are processed in parallel with previous draw
4261 * calls. Then upload descriptors, set shader pointers, and
4262 * draw, and prefetch at the end. This ensures that the time
4263 * the CUs are idle is very short. (there are only SET_SH
4264 * packets between the wait and the draw)
4266 radv_emit_all_graphics_states(cmd_buffer
, info
);
4267 si_emit_cache_flush(cmd_buffer
);
4268 /* <-- CUs are idle here --> */
4270 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4272 radv_emit_draw_packets(cmd_buffer
, info
);
4273 /* <-- CUs are busy here --> */
4275 /* Start prefetches after the draw has been started. Both will
4276 * run in parallel, but starting the draw first is more
4279 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4280 radv_emit_prefetch_L2(cmd_buffer
,
4281 cmd_buffer
->state
.pipeline
, false);
4284 /* If we don't wait for idle, start prefetches first, then set
4285 * states, and draw at the end.
4287 si_emit_cache_flush(cmd_buffer
);
4289 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4290 /* Only prefetch the vertex shader and VBO descriptors
4291 * in order to start the draw as soon as possible.
4293 radv_emit_prefetch_L2(cmd_buffer
,
4294 cmd_buffer
->state
.pipeline
, true);
4297 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
4299 radv_emit_all_graphics_states(cmd_buffer
, info
);
4300 radv_emit_draw_packets(cmd_buffer
, info
);
4302 /* Prefetch the remaining shaders after the draw has been
4305 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
4306 radv_emit_prefetch_L2(cmd_buffer
,
4307 cmd_buffer
->state
.pipeline
, false);
4311 /* Workaround for a VGT hang when streamout is enabled.
4312 * It must be done after drawing.
4314 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
4315 (rad_info
->family
== CHIP_HAWAII
||
4316 rad_info
->family
== CHIP_TONGA
||
4317 rad_info
->family
== CHIP_FIJI
)) {
4318 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
4321 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4322 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
4326 VkCommandBuffer commandBuffer
,
4327 uint32_t vertexCount
,
4328 uint32_t instanceCount
,
4329 uint32_t firstVertex
,
4330 uint32_t firstInstance
)
4332 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4333 struct radv_draw_info info
= {};
4335 info
.count
= vertexCount
;
4336 info
.instance_count
= instanceCount
;
4337 info
.first_instance
= firstInstance
;
4338 info
.vertex_offset
= firstVertex
;
4340 radv_draw(cmd_buffer
, &info
);
4343 void radv_CmdDrawIndexed(
4344 VkCommandBuffer commandBuffer
,
4345 uint32_t indexCount
,
4346 uint32_t instanceCount
,
4347 uint32_t firstIndex
,
4348 int32_t vertexOffset
,
4349 uint32_t firstInstance
)
4351 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4352 struct radv_draw_info info
= {};
4354 info
.indexed
= true;
4355 info
.count
= indexCount
;
4356 info
.instance_count
= instanceCount
;
4357 info
.first_index
= firstIndex
;
4358 info
.vertex_offset
= vertexOffset
;
4359 info
.first_instance
= firstInstance
;
4361 radv_draw(cmd_buffer
, &info
);
4364 void radv_CmdDrawIndirect(
4365 VkCommandBuffer commandBuffer
,
4367 VkDeviceSize offset
,
4371 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4372 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4373 struct radv_draw_info info
= {};
4375 info
.count
= drawCount
;
4376 info
.indirect
= buffer
;
4377 info
.indirect_offset
= offset
;
4378 info
.stride
= stride
;
4380 radv_draw(cmd_buffer
, &info
);
4383 void radv_CmdDrawIndexedIndirect(
4384 VkCommandBuffer commandBuffer
,
4386 VkDeviceSize offset
,
4390 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4391 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4392 struct radv_draw_info info
= {};
4394 info
.indexed
= true;
4395 info
.count
= drawCount
;
4396 info
.indirect
= buffer
;
4397 info
.indirect_offset
= offset
;
4398 info
.stride
= stride
;
4400 radv_draw(cmd_buffer
, &info
);
4403 void radv_CmdDrawIndirectCountKHR(
4404 VkCommandBuffer commandBuffer
,
4406 VkDeviceSize offset
,
4407 VkBuffer _countBuffer
,
4408 VkDeviceSize countBufferOffset
,
4409 uint32_t maxDrawCount
,
4412 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4413 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4414 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4415 struct radv_draw_info info
= {};
4417 info
.count
= maxDrawCount
;
4418 info
.indirect
= buffer
;
4419 info
.indirect_offset
= offset
;
4420 info
.count_buffer
= count_buffer
;
4421 info
.count_buffer_offset
= countBufferOffset
;
4422 info
.stride
= stride
;
4424 radv_draw(cmd_buffer
, &info
);
4427 void radv_CmdDrawIndexedIndirectCountKHR(
4428 VkCommandBuffer commandBuffer
,
4430 VkDeviceSize offset
,
4431 VkBuffer _countBuffer
,
4432 VkDeviceSize countBufferOffset
,
4433 uint32_t maxDrawCount
,
4436 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4437 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4438 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
4439 struct radv_draw_info info
= {};
4441 info
.indexed
= true;
4442 info
.count
= maxDrawCount
;
4443 info
.indirect
= buffer
;
4444 info
.indirect_offset
= offset
;
4445 info
.count_buffer
= count_buffer
;
4446 info
.count_buffer_offset
= countBufferOffset
;
4447 info
.stride
= stride
;
4449 radv_draw(cmd_buffer
, &info
);
4452 struct radv_dispatch_info
{
4454 * Determine the layout of the grid (in block units) to be used.
4459 * A starting offset for the grid. If unaligned is set, the offset
4460 * must still be aligned.
4462 uint32_t offsets
[3];
4464 * Whether it's an unaligned compute dispatch.
4469 * Indirect compute parameters resource.
4471 struct radv_buffer
*indirect
;
4472 uint64_t indirect_offset
;
4476 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
4477 const struct radv_dispatch_info
*info
)
4479 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4480 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4481 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
4482 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
4483 bool predicating
= cmd_buffer
->state
.predicating
;
4484 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
4485 struct radv_userdata_info
*loc
;
4487 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
4488 AC_UD_CS_GRID_SIZE
);
4490 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
4492 if (info
->indirect
) {
4493 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
4495 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
4497 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
4499 if (loc
->sgpr_idx
!= -1) {
4500 for (unsigned i
= 0; i
< 3; ++i
) {
4501 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
4502 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
4503 COPY_DATA_DST_SEL(COPY_DATA_REG
));
4504 radeon_emit(cs
, (va
+ 4 * i
));
4505 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
4506 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
4507 + loc
->sgpr_idx
* 4) >> 2) + i
);
4512 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
4513 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
4514 PKT3_SHADER_TYPE_S(1));
4515 radeon_emit(cs
, va
);
4516 radeon_emit(cs
, va
>> 32);
4517 radeon_emit(cs
, dispatch_initiator
);
4519 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
4520 PKT3_SHADER_TYPE_S(1));
4522 radeon_emit(cs
, va
);
4523 radeon_emit(cs
, va
>> 32);
4525 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
4526 PKT3_SHADER_TYPE_S(1));
4528 radeon_emit(cs
, dispatch_initiator
);
4531 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
4532 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
4534 if (info
->unaligned
) {
4535 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
4536 unsigned remainder
[3];
4538 /* If aligned, these should be an entire block size,
4541 remainder
[0] = blocks
[0] + cs_block_size
[0] -
4542 align_u32_npot(blocks
[0], cs_block_size
[0]);
4543 remainder
[1] = blocks
[1] + cs_block_size
[1] -
4544 align_u32_npot(blocks
[1], cs_block_size
[1]);
4545 remainder
[2] = blocks
[2] + cs_block_size
[2] -
4546 align_u32_npot(blocks
[2], cs_block_size
[2]);
4548 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
4549 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
4550 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
4552 for(unsigned i
= 0; i
< 3; ++i
) {
4553 assert(offsets
[i
] % cs_block_size
[i
] == 0);
4554 offsets
[i
] /= cs_block_size
[i
];
4557 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
4559 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
4560 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
4562 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
4563 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
4565 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
4566 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
4568 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
4571 if (loc
->sgpr_idx
!= -1) {
4572 assert(loc
->num_sgprs
== 3);
4574 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
4575 loc
->sgpr_idx
* 4, 3);
4576 radeon_emit(cs
, blocks
[0]);
4577 radeon_emit(cs
, blocks
[1]);
4578 radeon_emit(cs
, blocks
[2]);
4581 if (offsets
[0] || offsets
[1] || offsets
[2]) {
4582 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
4583 radeon_emit(cs
, offsets
[0]);
4584 radeon_emit(cs
, offsets
[1]);
4585 radeon_emit(cs
, offsets
[2]);
4587 /* The blocks in the packet are not counts but end values. */
4588 for (unsigned i
= 0; i
< 3; ++i
)
4589 blocks
[i
] += offsets
[i
];
4591 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
4594 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
4595 PKT3_SHADER_TYPE_S(1));
4596 radeon_emit(cs
, blocks
[0]);
4597 radeon_emit(cs
, blocks
[1]);
4598 radeon_emit(cs
, blocks
[2]);
4599 radeon_emit(cs
, dispatch_initiator
);
4602 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4606 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
4608 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4609 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
4613 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
4614 const struct radv_dispatch_info
*info
)
4616 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4618 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
4619 bool pipeline_is_dirty
= pipeline
&&
4620 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
4622 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4623 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4624 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
4625 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
4626 /* If we have to wait for idle, set all states first, so that
4627 * all SET packets are processed in parallel with previous draw
4628 * calls. Then upload descriptors, set shader pointers, and
4629 * dispatch, and prefetch at the end. This ensures that the
4630 * time the CUs are idle is very short. (there are only SET_SH
4631 * packets between the wait and the draw)
4633 radv_emit_compute_pipeline(cmd_buffer
);
4634 si_emit_cache_flush(cmd_buffer
);
4635 /* <-- CUs are idle here --> */
4637 radv_upload_compute_shader_descriptors(cmd_buffer
);
4639 radv_emit_dispatch_packets(cmd_buffer
, info
);
4640 /* <-- CUs are busy here --> */
4642 /* Start prefetches after the dispatch has been started. Both
4643 * will run in parallel, but starting the dispatch first is
4646 if (has_prefetch
&& pipeline_is_dirty
) {
4647 radv_emit_shader_prefetch(cmd_buffer
,
4648 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4651 /* If we don't wait for idle, start prefetches first, then set
4652 * states, and dispatch at the end.
4654 si_emit_cache_flush(cmd_buffer
);
4656 if (has_prefetch
&& pipeline_is_dirty
) {
4657 radv_emit_shader_prefetch(cmd_buffer
,
4658 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
4661 radv_upload_compute_shader_descriptors(cmd_buffer
);
4663 radv_emit_compute_pipeline(cmd_buffer
);
4664 radv_emit_dispatch_packets(cmd_buffer
, info
);
4667 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
4670 void radv_CmdDispatchBase(
4671 VkCommandBuffer commandBuffer
,
4679 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4680 struct radv_dispatch_info info
= {};
4686 info
.offsets
[0] = base_x
;
4687 info
.offsets
[1] = base_y
;
4688 info
.offsets
[2] = base_z
;
4689 radv_dispatch(cmd_buffer
, &info
);
4692 void radv_CmdDispatch(
4693 VkCommandBuffer commandBuffer
,
4698 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
4701 void radv_CmdDispatchIndirect(
4702 VkCommandBuffer commandBuffer
,
4704 VkDeviceSize offset
)
4706 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4707 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4708 struct radv_dispatch_info info
= {};
4710 info
.indirect
= buffer
;
4711 info
.indirect_offset
= offset
;
4713 radv_dispatch(cmd_buffer
, &info
);
4716 void radv_unaligned_dispatch(
4717 struct radv_cmd_buffer
*cmd_buffer
,
4722 struct radv_dispatch_info info
= {};
4729 radv_dispatch(cmd_buffer
, &info
);
4732 void radv_CmdEndRenderPass(
4733 VkCommandBuffer commandBuffer
)
4735 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4737 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
4739 radv_cmd_buffer_end_subpass(cmd_buffer
);
4741 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
4742 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
4744 cmd_buffer
->state
.pass
= NULL
;
4745 cmd_buffer
->state
.subpass
= NULL
;
4746 cmd_buffer
->state
.attachments
= NULL
;
4747 cmd_buffer
->state
.framebuffer
= NULL
;
4748 cmd_buffer
->state
.subpass_sample_locs
= NULL
;
4751 void radv_CmdEndRenderPass2KHR(
4752 VkCommandBuffer commandBuffer
,
4753 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4755 radv_CmdEndRenderPass(commandBuffer
);
4759 * For HTILE we have the following interesting clear words:
4760 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4761 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4762 * 0xfffffff0: Clear depth to 1.0
4763 * 0x00000000: Clear depth to 0.0
4765 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
4766 struct radv_image
*image
,
4767 const VkImageSubresourceRange
*range
,
4768 uint32_t clear_word
)
4770 assert(range
->baseMipLevel
== 0);
4771 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
4772 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4773 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4774 VkClearDepthStencilValue value
= {};
4776 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4777 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4779 state
->flush_bits
|= radv_clear_htile(cmd_buffer
, image
, range
, clear_word
);
4781 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4783 if (vk_format_is_stencil(image
->vk_format
))
4784 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
4786 radv_set_ds_clear_metadata(cmd_buffer
, image
, value
, aspects
);
4788 if (radv_image_is_tc_compat_htile(image
)) {
4789 /* Initialize the TC-compat metada value to 0 because by
4790 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4791 * need have to conditionally update its value when performing
4792 * a fast depth clear.
4794 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, 0);
4798 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4799 struct radv_image
*image
,
4800 VkImageLayout src_layout
,
4801 VkImageLayout dst_layout
,
4802 unsigned src_queue_mask
,
4803 unsigned dst_queue_mask
,
4804 const VkImageSubresourceRange
*range
,
4805 struct radv_sample_locations_state
*sample_locs
)
4807 if (!radv_image_has_htile(image
))
4810 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
4811 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
4813 if (radv_layout_is_htile_compressed(image
, dst_layout
,
4818 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
4819 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4820 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4821 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
4822 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
4823 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
4824 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
4825 VkImageSubresourceRange local_range
= *range
;
4826 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
4827 local_range
.baseMipLevel
= 0;
4828 local_range
.levelCount
= 1;
4830 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4831 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4833 radv_decompress_depth_image_inplace(cmd_buffer
, image
,
4834 &local_range
, sample_locs
);
4836 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
4837 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
4841 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
4842 struct radv_image
*image
, uint32_t value
)
4844 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4846 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4847 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4849 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, value
);
4851 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4854 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
4855 struct radv_image
*image
)
4857 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4858 static const uint32_t fmask_clear_values
[4] = {
4864 uint32_t log2_samples
= util_logbase2(image
->info
.samples
);
4865 uint32_t value
= fmask_clear_values
[log2_samples
];
4867 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4868 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4870 state
->flush_bits
|= radv_clear_fmask(cmd_buffer
, image
, value
);
4872 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4875 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
4876 struct radv_image
*image
, uint32_t value
)
4878 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4880 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4881 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4883 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, value
);
4885 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
4886 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
4890 * Initialize DCC/FMASK/CMASK metadata for a color image.
4892 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
4893 struct radv_image
*image
,
4894 VkImageLayout src_layout
,
4895 VkImageLayout dst_layout
,
4896 unsigned src_queue_mask
,
4897 unsigned dst_queue_mask
)
4899 if (radv_image_has_cmask(image
)) {
4900 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4902 /* TODO: clarify this. */
4903 if (radv_image_has_fmask(image
)) {
4904 value
= 0xccccccccu
;
4907 radv_initialise_cmask(cmd_buffer
, image
, value
);
4910 if (radv_image_has_fmask(image
)) {
4911 radv_initialize_fmask(cmd_buffer
, image
);
4914 if (radv_image_has_dcc(image
)) {
4915 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
4916 bool need_decompress_pass
= false;
4918 if (radv_layout_dcc_compressed(image
, dst_layout
,
4920 value
= 0x20202020u
;
4921 need_decompress_pass
= true;
4924 radv_initialize_dcc(cmd_buffer
, image
, value
);
4926 radv_update_fce_metadata(cmd_buffer
, image
,
4927 need_decompress_pass
);
4930 if (radv_image_has_cmask(image
) || radv_image_has_dcc(image
)) {
4931 uint32_t color_values
[2] = {};
4932 radv_set_color_clear_metadata(cmd_buffer
, image
, color_values
);
4937 * Handle color image transitions for DCC/FMASK/CMASK.
4939 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4940 struct radv_image
*image
,
4941 VkImageLayout src_layout
,
4942 VkImageLayout dst_layout
,
4943 unsigned src_queue_mask
,
4944 unsigned dst_queue_mask
,
4945 const VkImageSubresourceRange
*range
)
4947 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
4948 radv_init_color_image_metadata(cmd_buffer
, image
,
4949 src_layout
, dst_layout
,
4950 src_queue_mask
, dst_queue_mask
);
4954 if (radv_image_has_dcc(image
)) {
4955 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
4956 radv_initialize_dcc(cmd_buffer
, image
, 0xffffffffu
);
4957 } else if (radv_layout_dcc_compressed(image
, src_layout
, src_queue_mask
) &&
4958 !radv_layout_dcc_compressed(image
, dst_layout
, dst_queue_mask
)) {
4959 radv_decompress_dcc(cmd_buffer
, image
, range
);
4960 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4961 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4962 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4964 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
4965 bool fce_eliminate
= false, fmask_expand
= false;
4967 if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
4968 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
4969 fce_eliminate
= true;
4972 if (radv_image_has_fmask(image
)) {
4973 if (src_layout
!= VK_IMAGE_LAYOUT_GENERAL
&&
4974 dst_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
4975 /* A FMASK decompress is required before doing
4976 * a MSAA decompress using FMASK.
4978 fmask_expand
= true;
4982 if (fce_eliminate
|| fmask_expand
)
4983 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
4986 radv_expand_fmask_image_inplace(cmd_buffer
, image
, range
);
4990 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
4991 struct radv_image
*image
,
4992 VkImageLayout src_layout
,
4993 VkImageLayout dst_layout
,
4994 uint32_t src_family
,
4995 uint32_t dst_family
,
4996 const VkImageSubresourceRange
*range
,
4997 struct radv_sample_locations_state
*sample_locs
)
4999 if (image
->exclusive
&& src_family
!= dst_family
) {
5000 /* This is an acquire or a release operation and there will be
5001 * a corresponding release/acquire. Do the transition in the
5002 * most flexible queue. */
5004 assert(src_family
== cmd_buffer
->queue_family_index
||
5005 dst_family
== cmd_buffer
->queue_family_index
);
5007 if (src_family
== VK_QUEUE_FAMILY_EXTERNAL
)
5010 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
5013 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
5014 (src_family
== RADV_QUEUE_GENERAL
||
5015 dst_family
== RADV_QUEUE_GENERAL
))
5019 if (src_layout
== dst_layout
)
5022 unsigned src_queue_mask
=
5023 radv_image_queue_family_mask(image
, src_family
,
5024 cmd_buffer
->queue_family_index
);
5025 unsigned dst_queue_mask
=
5026 radv_image_queue_family_mask(image
, dst_family
,
5027 cmd_buffer
->queue_family_index
);
5029 if (vk_format_is_depth(image
->vk_format
)) {
5030 radv_handle_depth_image_transition(cmd_buffer
, image
,
5031 src_layout
, dst_layout
,
5032 src_queue_mask
, dst_queue_mask
,
5033 range
, sample_locs
);
5035 radv_handle_color_image_transition(cmd_buffer
, image
,
5036 src_layout
, dst_layout
,
5037 src_queue_mask
, dst_queue_mask
,
5042 struct radv_barrier_info
{
5043 uint32_t eventCount
;
5044 const VkEvent
*pEvents
;
5045 VkPipelineStageFlags srcStageMask
;
5046 VkPipelineStageFlags dstStageMask
;
5050 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
5051 uint32_t memoryBarrierCount
,
5052 const VkMemoryBarrier
*pMemoryBarriers
,
5053 uint32_t bufferMemoryBarrierCount
,
5054 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
5055 uint32_t imageMemoryBarrierCount
,
5056 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
5057 const struct radv_barrier_info
*info
)
5059 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5060 enum radv_cmd_flush_bits src_flush_bits
= 0;
5061 enum radv_cmd_flush_bits dst_flush_bits
= 0;
5063 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
5064 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
5065 uint64_t va
= radv_buffer_get_va(event
->bo
);
5067 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5069 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
5071 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
5072 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5075 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
5076 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
5078 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
5082 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
5083 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
5085 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
5089 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5090 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5092 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
5094 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
5098 /* The Vulkan spec 1.1.98 says:
5100 * "An execution dependency with only
5101 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5102 * will only prevent that stage from executing in subsequently
5103 * submitted commands. As this stage does not perform any actual
5104 * execution, this is not observable - in effect, it does not delay
5105 * processing of subsequent commands. Similarly an execution dependency
5106 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5107 * will effectively not wait for any prior commands to complete."
5109 if (info
->dstStageMask
!= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
)
5110 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
5111 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
5113 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
5114 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
5116 const struct VkSampleLocationsInfoEXT
*sample_locs_info
=
5117 vk_find_struct_const(pImageMemoryBarriers
[i
].pNext
,
5118 SAMPLE_LOCATIONS_INFO_EXT
);
5119 struct radv_sample_locations_state sample_locations
= {};
5121 if (sample_locs_info
) {
5122 assert(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
);
5123 sample_locations
.per_pixel
= sample_locs_info
->sampleLocationsPerPixel
;
5124 sample_locations
.grid_size
= sample_locs_info
->sampleLocationGridSize
;
5125 sample_locations
.count
= sample_locs_info
->sampleLocationsCount
;
5126 typed_memcpy(&sample_locations
.locations
[0],
5127 sample_locs_info
->pSampleLocations
,
5128 sample_locs_info
->sampleLocationsCount
);
5131 radv_handle_image_transition(cmd_buffer
, image
,
5132 pImageMemoryBarriers
[i
].oldLayout
,
5133 pImageMemoryBarriers
[i
].newLayout
,
5134 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
5135 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
5136 &pImageMemoryBarriers
[i
].subresourceRange
,
5137 sample_locs_info
? &sample_locations
: NULL
);
5140 /* Make sure CP DMA is idle because the driver might have performed a
5141 * DMA operation for copying or filling buffers/images.
5143 if (info
->srcStageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5144 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5145 si_cp_dma_wait_for_idle(cmd_buffer
);
5147 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
5150 void radv_CmdPipelineBarrier(
5151 VkCommandBuffer commandBuffer
,
5152 VkPipelineStageFlags srcStageMask
,
5153 VkPipelineStageFlags destStageMask
,
5155 uint32_t memoryBarrierCount
,
5156 const VkMemoryBarrier
* pMemoryBarriers
,
5157 uint32_t bufferMemoryBarrierCount
,
5158 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5159 uint32_t imageMemoryBarrierCount
,
5160 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5162 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5163 struct radv_barrier_info info
;
5165 info
.eventCount
= 0;
5166 info
.pEvents
= NULL
;
5167 info
.srcStageMask
= srcStageMask
;
5168 info
.dstStageMask
= destStageMask
;
5170 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5171 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5172 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5176 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
5177 struct radv_event
*event
,
5178 VkPipelineStageFlags stageMask
,
5181 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5182 uint64_t va
= radv_buffer_get_va(event
->bo
);
5184 si_emit_cache_flush(cmd_buffer
);
5186 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
5188 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 21);
5190 /* Flags that only require a top-of-pipe event. */
5191 VkPipelineStageFlags top_of_pipe_flags
=
5192 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
5194 /* Flags that only require a post-index-fetch event. */
5195 VkPipelineStageFlags post_index_fetch_flags
=
5197 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
5198 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
5200 /* Make sure CP DMA is idle because the driver might have performed a
5201 * DMA operation for copying or filling buffers/images.
5203 if (stageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
5204 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
5205 si_cp_dma_wait_for_idle(cmd_buffer
);
5207 /* TODO: Emit EOS events for syncing PS/CS stages. */
5209 if (!(stageMask
& ~top_of_pipe_flags
)) {
5210 /* Just need to sync the PFP engine. */
5211 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5212 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5213 S_370_WR_CONFIRM(1) |
5214 S_370_ENGINE_SEL(V_370_PFP
));
5215 radeon_emit(cs
, va
);
5216 radeon_emit(cs
, va
>> 32);
5217 radeon_emit(cs
, value
);
5218 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
5219 /* Sync ME because PFP reads index and indirect buffers. */
5220 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
5221 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
5222 S_370_WR_CONFIRM(1) |
5223 S_370_ENGINE_SEL(V_370_ME
));
5224 radeon_emit(cs
, va
);
5225 radeon_emit(cs
, va
>> 32);
5226 radeon_emit(cs
, value
);
5228 /* Otherwise, sync all prior GPU work using an EOP event. */
5229 si_cs_emit_write_event_eop(cs
,
5230 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
5231 radv_cmd_buffer_uses_mec(cmd_buffer
),
5232 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
5233 EOP_DATA_SEL_VALUE_32BIT
, va
, value
,
5234 cmd_buffer
->gfx9_eop_bug_va
);
5237 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5240 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
5242 VkPipelineStageFlags stageMask
)
5244 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5245 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5247 write_event(cmd_buffer
, event
, stageMask
, 1);
5250 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
5252 VkPipelineStageFlags stageMask
)
5254 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5255 RADV_FROM_HANDLE(radv_event
, event
, _event
);
5257 write_event(cmd_buffer
, event
, stageMask
, 0);
5260 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
5261 uint32_t eventCount
,
5262 const VkEvent
* pEvents
,
5263 VkPipelineStageFlags srcStageMask
,
5264 VkPipelineStageFlags dstStageMask
,
5265 uint32_t memoryBarrierCount
,
5266 const VkMemoryBarrier
* pMemoryBarriers
,
5267 uint32_t bufferMemoryBarrierCount
,
5268 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5269 uint32_t imageMemoryBarrierCount
,
5270 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5272 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5273 struct radv_barrier_info info
;
5275 info
.eventCount
= eventCount
;
5276 info
.pEvents
= pEvents
;
5277 info
.srcStageMask
= 0;
5279 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
5280 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5281 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
5285 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
5286 uint32_t deviceMask
)
5291 /* VK_EXT_conditional_rendering */
5292 void radv_CmdBeginConditionalRenderingEXT(
5293 VkCommandBuffer commandBuffer
,
5294 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5296 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5297 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5298 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5299 bool draw_visible
= true;
5300 uint64_t pred_value
= 0;
5301 uint64_t va
, new_va
;
5302 unsigned pred_offset
;
5304 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
5306 /* By default, if the 32-bit value at offset in buffer memory is zero,
5307 * then the rendering commands are discarded, otherwise they are
5308 * executed as normal. If the inverted flag is set, all commands are
5309 * discarded if the value is non zero.
5311 if (pConditionalRenderingBegin
->flags
&
5312 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
5313 draw_visible
= false;
5316 si_emit_cache_flush(cmd_buffer
);
5318 /* From the Vulkan spec 1.1.107:
5320 * "If the 32-bit value at offset in buffer memory is zero, then the
5321 * rendering commands are discarded, otherwise they are executed as
5322 * normal. If the value of the predicate in buffer memory changes while
5323 * conditional rendering is active, the rendering commands may be
5324 * discarded in an implementation-dependent way. Some implementations
5325 * may latch the value of the predicate upon beginning conditional
5326 * rendering while others may read it before every rendering command."
5328 * But, the AMD hardware treats the predicate as a 64-bit value which
5329 * means we need a workaround in the driver. Luckily, it's not required
5330 * to support if the value changes when predication is active.
5332 * The workaround is as follows:
5333 * 1) allocate a 64-value in the upload BO and initialize it to 0
5334 * 2) copy the 32-bit predicate value to the upload BO
5335 * 3) use the new allocated VA address for predication
5337 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5338 * in ME (+ sync PFP) instead of PFP.
5340 radv_cmd_buffer_upload_data(cmd_buffer
, 8, 16, &pred_value
, &pred_offset
);
5342 new_va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
) + pred_offset
;
5344 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5345 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
5346 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
5347 COPY_DATA_WR_CONFIRM
);
5348 radeon_emit(cs
, va
);
5349 radeon_emit(cs
, va
>> 32);
5350 radeon_emit(cs
, new_va
);
5351 radeon_emit(cs
, new_va
>> 32);
5353 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
5356 /* Enable predication for this command buffer. */
5357 si_emit_set_predication_state(cmd_buffer
, draw_visible
, new_va
);
5358 cmd_buffer
->state
.predicating
= true;
5360 /* Store conditional rendering user info. */
5361 cmd_buffer
->state
.predication_type
= draw_visible
;
5362 cmd_buffer
->state
.predication_va
= new_va
;
5365 void radv_CmdEndConditionalRenderingEXT(
5366 VkCommandBuffer commandBuffer
)
5368 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5370 /* Disable predication for this command buffer. */
5371 si_emit_set_predication_state(cmd_buffer
, false, 0);
5372 cmd_buffer
->state
.predicating
= false;
5374 /* Reset conditional rendering user info. */
5375 cmd_buffer
->state
.predication_type
= -1;
5376 cmd_buffer
->state
.predication_va
= 0;
5379 /* VK_EXT_transform_feedback */
5380 void radv_CmdBindTransformFeedbackBuffersEXT(
5381 VkCommandBuffer commandBuffer
,
5382 uint32_t firstBinding
,
5383 uint32_t bindingCount
,
5384 const VkBuffer
* pBuffers
,
5385 const VkDeviceSize
* pOffsets
,
5386 const VkDeviceSize
* pSizes
)
5388 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5389 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5390 uint8_t enabled_mask
= 0;
5392 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
5393 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
5394 uint32_t idx
= firstBinding
+ i
;
5396 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
5397 sb
[idx
].offset
= pOffsets
[i
];
5398 sb
[idx
].size
= pSizes
[i
];
5400 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
5401 sb
[idx
].buffer
->bo
);
5403 enabled_mask
|= 1 << idx
;
5406 cmd_buffer
->state
.streamout
.enabled_mask
|= enabled_mask
;
5408 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
5412 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
5414 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5415 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5417 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
5419 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
5420 S_028B94_RAST_STREAM(0) |
5421 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
5422 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
5423 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
5424 radeon_emit(cs
, so
->hw_enabled_mask
&
5425 so
->enabled_stream_buffers_mask
);
5427 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5431 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
5433 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5434 bool old_streamout_enabled
= so
->streamout_enabled
;
5435 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
5437 so
->streamout_enabled
= enable
;
5439 so
->hw_enabled_mask
= so
->enabled_mask
|
5440 (so
->enabled_mask
<< 4) |
5441 (so
->enabled_mask
<< 8) |
5442 (so
->enabled_mask
<< 12);
5444 if ((old_streamout_enabled
!= so
->streamout_enabled
) ||
5445 (old_hw_enabled_mask
!= so
->hw_enabled_mask
))
5446 radv_emit_streamout_enable(cmd_buffer
);
5449 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
5451 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5452 unsigned reg_strmout_cntl
;
5454 /* The register is at different places on different ASICs. */
5455 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
5456 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
5457 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
5459 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
5460 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
5463 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
5464 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
5466 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
5467 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
5468 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
5470 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5471 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5472 radeon_emit(cs
, 4); /* poll interval */
5475 void radv_CmdBeginTransformFeedbackEXT(
5476 VkCommandBuffer commandBuffer
,
5477 uint32_t firstCounterBuffer
,
5478 uint32_t counterBufferCount
,
5479 const VkBuffer
* pCounterBuffers
,
5480 const VkDeviceSize
* pCounterBufferOffsets
)
5482 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5483 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
5484 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5485 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5488 radv_flush_vgt_streamout(cmd_buffer
);
5490 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5491 for_each_bit(i
, so
->enabled_mask
) {
5492 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5493 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5494 counter_buffer_idx
= -1;
5496 /* AMD GCN binds streamout buffers as shader resources.
5497 * VGT only counts primitives and tells the shader through
5500 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
5501 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
5502 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
5504 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5506 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
5507 /* The array of counter buffers is optional. */
5508 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5509 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
5511 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5514 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5515 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5516 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5517 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
5518 radeon_emit(cs
, 0); /* unused */
5519 radeon_emit(cs
, 0); /* unused */
5520 radeon_emit(cs
, va
); /* src address lo */
5521 radeon_emit(cs
, va
>> 32); /* src address hi */
5523 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5525 /* Start from the beginning. */
5526 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5527 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5528 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5529 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
5530 radeon_emit(cs
, 0); /* unused */
5531 radeon_emit(cs
, 0); /* unused */
5532 radeon_emit(cs
, 0); /* unused */
5533 radeon_emit(cs
, 0); /* unused */
5537 radv_set_streamout_enable(cmd_buffer
, true);
5540 void radv_CmdEndTransformFeedbackEXT(
5541 VkCommandBuffer commandBuffer
,
5542 uint32_t firstCounterBuffer
,
5543 uint32_t counterBufferCount
,
5544 const VkBuffer
* pCounterBuffers
,
5545 const VkDeviceSize
* pCounterBufferOffsets
)
5547 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5548 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
5549 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5552 radv_flush_vgt_streamout(cmd_buffer
);
5554 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
5555 for_each_bit(i
, so
->enabled_mask
) {
5556 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
5557 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
5558 counter_buffer_idx
= -1;
5560 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
5561 /* The array of counters buffer is optional. */
5562 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
5563 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
5565 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
5567 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
5568 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
5569 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5570 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
5571 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
5572 radeon_emit(cs
, va
); /* dst address lo */
5573 radeon_emit(cs
, va
>> 32); /* dst address hi */
5574 radeon_emit(cs
, 0); /* unused */
5575 radeon_emit(cs
, 0); /* unused */
5577 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
5580 /* Deactivate transform feedback by zeroing the buffer size.
5581 * The counters (primitives generated, primitives emitted) may
5582 * be enabled even if there is not buffer bound. This ensures
5583 * that the primitives-emitted query won't increment.
5585 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
5587 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
5590 radv_set_streamout_enable(cmd_buffer
, false);
5593 void radv_CmdDrawIndirectByteCountEXT(
5594 VkCommandBuffer commandBuffer
,
5595 uint32_t instanceCount
,
5596 uint32_t firstInstance
,
5597 VkBuffer _counterBuffer
,
5598 VkDeviceSize counterBufferOffset
,
5599 uint32_t counterOffset
,
5600 uint32_t vertexStride
)
5602 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5603 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
5604 struct radv_draw_info info
= {};
5606 info
.instance_count
= instanceCount
;
5607 info
.first_instance
= firstInstance
;
5608 info
.strmout_buffer
= counterBuffer
;
5609 info
.strmout_buffer_offset
= counterBufferOffset
;
5610 info
.stride
= vertexStride
;
5612 radv_draw(cmd_buffer
, &info
);