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radv: Implement alternate GFX9 scissor workaround.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safely call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo, 8);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 cmd_buffer->ring_offsets_idx = -1;
314
315 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
316 cmd_buffer->descriptors[i].dirty = 0;
317 cmd_buffer->descriptors[i].valid = 0;
318 cmd_buffer->descriptors[i].push_dirty = false;
319 }
320
321 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
322 void *fence_ptr;
323 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
324 &cmd_buffer->gfx9_fence_offset,
325 &fence_ptr);
326 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
327 }
328
329 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
330
331 return cmd_buffer->record_result;
332 }
333
334 static bool
335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
336 uint64_t min_needed)
337 {
338 uint64_t new_size;
339 struct radeon_winsys_bo *bo;
340 struct radv_cmd_buffer_upload *upload;
341 struct radv_device *device = cmd_buffer->device;
342
343 new_size = MAX2(min_needed, 16 * 1024);
344 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
345
346 bo = device->ws->buffer_create(device->ws,
347 new_size, 4096,
348 RADEON_DOMAIN_GTT,
349 RADEON_FLAG_CPU_ACCESS|
350 RADEON_FLAG_NO_INTERPROCESS_SHARING |
351 RADEON_FLAG_32BIT);
352
353 if (!bo) {
354 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
355 return false;
356 }
357
358 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
359 if (cmd_buffer->upload.upload_bo) {
360 upload = malloc(sizeof(*upload));
361
362 if (!upload) {
363 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
364 device->ws->buffer_destroy(bo);
365 return false;
366 }
367
368 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
369 list_add(&upload->list, &cmd_buffer->upload.list);
370 }
371
372 cmd_buffer->upload.upload_bo = bo;
373 cmd_buffer->upload.size = new_size;
374 cmd_buffer->upload.offset = 0;
375 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
376
377 if (!cmd_buffer->upload.map) {
378 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
379 return false;
380 }
381
382 return true;
383 }
384
385 bool
386 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
387 unsigned size,
388 unsigned alignment,
389 unsigned *out_offset,
390 void **ptr)
391 {
392 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
393 if (offset + size > cmd_buffer->upload.size) {
394 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
395 return false;
396 offset = 0;
397 }
398
399 *out_offset = offset;
400 *ptr = cmd_buffer->upload.map + offset;
401
402 cmd_buffer->upload.offset = offset + size;
403 return true;
404 }
405
406 bool
407 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
408 unsigned size, unsigned alignment,
409 const void *data, unsigned *out_offset)
410 {
411 uint8_t *ptr;
412
413 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
414 out_offset, (void **)&ptr))
415 return false;
416
417 if (ptr)
418 memcpy(ptr, data, size);
419
420 return true;
421 }
422
423 static void
424 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
425 unsigned count, const uint32_t *data)
426 {
427 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
428 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
429 S_370_WR_CONFIRM(1) |
430 S_370_ENGINE_SEL(V_370_ME));
431 radeon_emit(cs, va);
432 radeon_emit(cs, va >> 32);
433 radeon_emit_array(cs, data, count);
434 }
435
436 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
437 {
438 struct radv_device *device = cmd_buffer->device;
439 struct radeon_winsys_cs *cs = cmd_buffer->cs;
440 uint64_t va;
441
442 va = radv_buffer_get_va(device->trace_bo);
443 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
444 va += 4;
445
446 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
447
448 ++cmd_buffer->state.trace_id;
449 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
450 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
451 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
452 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
453 }
454
455 static void
456 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
457 enum radv_cmd_flush_bits flags)
458 {
459 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
460 uint32_t *ptr = NULL;
461 uint64_t va = 0;
462
463 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
464 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
465
466 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
467 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
468 cmd_buffer->gfx9_fence_offset;
469 ptr = &cmd_buffer->gfx9_fence_idx;
470 }
471
472 /* Force wait for graphics or compute engines to be idle. */
473 si_cs_emit_cache_flush(cmd_buffer->cs,
474 cmd_buffer->device->physical_device->rad_info.chip_class,
475 ptr, va,
476 radv_cmd_buffer_uses_mec(cmd_buffer),
477 flags);
478 }
479
480 if (unlikely(cmd_buffer->device->trace_bo))
481 radv_cmd_buffer_trace_emit(cmd_buffer);
482 }
483
484 static void
485 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
486 struct radv_pipeline *pipeline, enum ring_type ring)
487 {
488 struct radv_device *device = cmd_buffer->device;
489 struct radeon_winsys_cs *cs = cmd_buffer->cs;
490 uint32_t data[2];
491 uint64_t va;
492
493 va = radv_buffer_get_va(device->trace_bo);
494
495 switch (ring) {
496 case RING_GFX:
497 va += 8;
498 break;
499 case RING_COMPUTE:
500 va += 16;
501 break;
502 default:
503 assert(!"invalid ring type");
504 }
505
506 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
507 cmd_buffer->cs, 6);
508
509 data[0] = (uintptr_t)pipeline;
510 data[1] = (uintptr_t)pipeline >> 32;
511
512 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
513 radv_emit_write_data_packet(cs, va, 2, data);
514 }
515
516 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
517 VkPipelineBindPoint bind_point,
518 struct radv_descriptor_set *set,
519 unsigned idx)
520 {
521 struct radv_descriptor_state *descriptors_state =
522 radv_get_descriptors_state(cmd_buffer, bind_point);
523
524 descriptors_state->sets[idx] = set;
525 if (set)
526 descriptors_state->valid |= (1u << idx);
527 else
528 descriptors_state->valid &= ~(1u << idx);
529 descriptors_state->dirty |= (1u << idx);
530 }
531
532 static void
533 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
534 VkPipelineBindPoint bind_point)
535 {
536 struct radv_descriptor_state *descriptors_state =
537 radv_get_descriptors_state(cmd_buffer, bind_point);
538 struct radv_device *device = cmd_buffer->device;
539 struct radeon_winsys_cs *cs = cmd_buffer->cs;
540 uint32_t data[MAX_SETS * 2] = {};
541 uint64_t va;
542 unsigned i;
543 va = radv_buffer_get_va(device->trace_bo) + 24;
544
545 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
546 cmd_buffer->cs, 4 + MAX_SETS * 2);
547
548 for_each_bit(i, descriptors_state->valid) {
549 struct radv_descriptor_set *set = descriptors_state->sets[i];
550 data[i * 2] = (uintptr_t)set;
551 data[i * 2 + 1] = (uintptr_t)set >> 32;
552 }
553
554 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
555 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
556 }
557
558 struct radv_userdata_info *
559 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
560 gl_shader_stage stage,
561 int idx)
562 {
563 if (stage == MESA_SHADER_VERTEX) {
564 if (pipeline->shaders[MESA_SHADER_VERTEX])
565 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
566 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
567 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
568 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
569 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
570 } else if (stage == MESA_SHADER_TESS_EVAL) {
571 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
572 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
573 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
574 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
575 }
576 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
577 }
578
579 static void
580 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
581 struct radv_pipeline *pipeline,
582 gl_shader_stage stage,
583 int idx, uint64_t va)
584 {
585 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
586 uint32_t base_reg = pipeline->user_data_0[stage];
587 if (loc->sgpr_idx == -1)
588 return;
589
590 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
591 assert(!loc->indirect);
592
593 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
594 base_reg + loc->sgpr_idx * 4, va, false);
595 }
596
597 static void
598 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
599 struct radv_pipeline *pipeline)
600 {
601 int num_samples = pipeline->graphics.ms.num_samples;
602 struct radv_multisample_state *ms = &pipeline->graphics.ms;
603 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
604
605 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
606 cmd_buffer->sample_positions_needed = true;
607
608 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
609 return;
610
611 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
612 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
613 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
614
615 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
616
617 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
618
619 /* GFX9: Flush DFSM when the AA mode changes. */
620 if (cmd_buffer->device->dfsm_allowed) {
621 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
622 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
623 }
624 }
625
626 static void
627 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
628 struct radv_shader_variant *shader)
629 {
630 uint64_t va;
631
632 if (!shader)
633 return;
634
635 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
636
637 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
638 }
639
640 static void
641 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
642 struct radv_pipeline *pipeline,
643 bool vertex_stage_only)
644 {
645 struct radv_cmd_state *state = &cmd_buffer->state;
646 uint32_t mask = state->prefetch_L2_mask;
647
648 if (vertex_stage_only) {
649 /* Fast prefetch path for starting draws as soon as possible.
650 */
651 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
652 RADV_PREFETCH_VBO_DESCRIPTORS);
653 }
654
655 if (mask & RADV_PREFETCH_VS)
656 radv_emit_shader_prefetch(cmd_buffer,
657 pipeline->shaders[MESA_SHADER_VERTEX]);
658
659 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
660 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
661
662 if (mask & RADV_PREFETCH_TCS)
663 radv_emit_shader_prefetch(cmd_buffer,
664 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
665
666 if (mask & RADV_PREFETCH_TES)
667 radv_emit_shader_prefetch(cmd_buffer,
668 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
669
670 if (mask & RADV_PREFETCH_GS) {
671 radv_emit_shader_prefetch(cmd_buffer,
672 pipeline->shaders[MESA_SHADER_GEOMETRY]);
673 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
674 }
675
676 if (mask & RADV_PREFETCH_PS)
677 radv_emit_shader_prefetch(cmd_buffer,
678 pipeline->shaders[MESA_SHADER_FRAGMENT]);
679
680 state->prefetch_L2_mask &= ~mask;
681 }
682
683 static void
684 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
685 {
686 if (!cmd_buffer->device->physical_device->rbplus_allowed)
687 return;
688
689 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
690 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
691 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
692
693 unsigned sx_ps_downconvert = 0;
694 unsigned sx_blend_opt_epsilon = 0;
695 unsigned sx_blend_opt_control = 0;
696
697 for (unsigned i = 0; i < subpass->color_count; ++i) {
698 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
699 continue;
700
701 int idx = subpass->color_attachments[i].attachment;
702 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
703
704 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
705 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
706 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
707 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
708
709 bool has_alpha, has_rgb;
710
711 /* Set if RGB and A are present. */
712 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
713
714 if (format == V_028C70_COLOR_8 ||
715 format == V_028C70_COLOR_16 ||
716 format == V_028C70_COLOR_32)
717 has_rgb = !has_alpha;
718 else
719 has_rgb = true;
720
721 /* Check the colormask and export format. */
722 if (!(colormask & 0x7))
723 has_rgb = false;
724 if (!(colormask & 0x8))
725 has_alpha = false;
726
727 if (spi_format == V_028714_SPI_SHADER_ZERO) {
728 has_rgb = false;
729 has_alpha = false;
730 }
731
732 /* Disable value checking for disabled channels. */
733 if (!has_rgb)
734 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
735 if (!has_alpha)
736 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
737
738 /* Enable down-conversion for 32bpp and smaller formats. */
739 switch (format) {
740 case V_028C70_COLOR_8:
741 case V_028C70_COLOR_8_8:
742 case V_028C70_COLOR_8_8_8_8:
743 /* For 1 and 2-channel formats, use the superset thereof. */
744 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
745 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
746 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
747 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
748 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
749 }
750 break;
751
752 case V_028C70_COLOR_5_6_5:
753 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
754 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
755 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
756 }
757 break;
758
759 case V_028C70_COLOR_1_5_5_5:
760 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
761 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
762 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
763 }
764 break;
765
766 case V_028C70_COLOR_4_4_4_4:
767 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
768 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
769 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
770 }
771 break;
772
773 case V_028C70_COLOR_32:
774 if (swap == V_028C70_SWAP_STD &&
775 spi_format == V_028714_SPI_SHADER_32_R)
776 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
777 else if (swap == V_028C70_SWAP_ALT_REV &&
778 spi_format == V_028714_SPI_SHADER_32_AR)
779 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
780 break;
781
782 case V_028C70_COLOR_16:
783 case V_028C70_COLOR_16_16:
784 /* For 1-channel formats, use the superset thereof. */
785 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
786 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
787 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
788 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
789 if (swap == V_028C70_SWAP_STD ||
790 swap == V_028C70_SWAP_STD_REV)
791 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
792 else
793 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
794 }
795 break;
796
797 case V_028C70_COLOR_10_11_11:
798 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
799 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
800 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
801 }
802 break;
803
804 case V_028C70_COLOR_2_10_10_10:
805 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
806 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
807 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
808 }
809 break;
810 }
811 }
812
813 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
814 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
815 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
816 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
817 }
818
819 static void
820 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
821 {
822 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
823
824 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
825 return;
826
827 radv_update_multisample_state(cmd_buffer, pipeline);
828
829 cmd_buffer->scratch_size_needed =
830 MAX2(cmd_buffer->scratch_size_needed,
831 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
832
833 if (!cmd_buffer->state.emitted_pipeline ||
834 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
835 pipeline->graphics.can_use_guardband)
836 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
837
838 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
839
840 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
841 if (!pipeline->shaders[i])
842 continue;
843
844 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
845 pipeline->shaders[i]->bo, 8);
846 }
847
848 if (radv_pipeline_has_gs(pipeline))
849 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
850 pipeline->gs_copy_shader->bo, 8);
851
852 if (unlikely(cmd_buffer->device->trace_bo))
853 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
854
855 cmd_buffer->state.emitted_pipeline = pipeline;
856
857 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
858 }
859
860 static void
861 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
862 {
863 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
864 cmd_buffer->state.dynamic.viewport.viewports);
865 }
866
867 static void
868 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
869 {
870 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
871
872 si_write_scissors(cmd_buffer->cs, 0, count,
873 cmd_buffer->state.dynamic.scissor.scissors,
874 cmd_buffer->state.dynamic.viewport.viewports,
875 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
876 }
877
878 static void
879 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
880 {
881 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
882 return;
883
884 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
885 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
886 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
887 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
888 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
889 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
890 S_028214_BR_Y(rect.offset.y + rect.extent.height));
891 }
892 }
893
894 static void
895 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
896 {
897 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
898
899 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
900 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
901 }
902
903 static void
904 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
905 {
906 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
907
908 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
909 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
910 }
911
912 static void
913 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
914 {
915 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
916
917 radeon_set_context_reg_seq(cmd_buffer->cs,
918 R_028430_DB_STENCILREFMASK, 2);
919 radeon_emit(cmd_buffer->cs,
920 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
921 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
922 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
923 S_028430_STENCILOPVAL(1));
924 radeon_emit(cmd_buffer->cs,
925 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
926 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
927 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
928 S_028434_STENCILOPVAL_BF(1));
929 }
930
931 static void
932 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
933 {
934 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
935
936 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
937 fui(d->depth_bounds.min));
938 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
939 fui(d->depth_bounds.max));
940 }
941
942 static void
943 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
944 {
945 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
946 unsigned slope = fui(d->depth_bias.slope * 16.0f);
947 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
948
949
950 radeon_set_context_reg_seq(cmd_buffer->cs,
951 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
952 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
953 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
954 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
955 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
956 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
957 }
958
959 static void
960 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
961 int index,
962 struct radv_attachment_info *att,
963 struct radv_image *image,
964 VkImageLayout layout)
965 {
966 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
967 struct radv_color_buffer_info *cb = &att->cb;
968 uint32_t cb_color_info = cb->cb_color_info;
969
970 if (!radv_layout_dcc_compressed(image, layout,
971 radv_image_queue_family_mask(image,
972 cmd_buffer->queue_family_index,
973 cmd_buffer->queue_family_index))) {
974 cb_color_info &= C_028C70_DCC_ENABLE;
975 }
976
977 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
978 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
979 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
980 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
981 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
982 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
983 radeon_emit(cmd_buffer->cs, cb_color_info);
984 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
985 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
986 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
987 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
988 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
989 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
990
991 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
992 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
993 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
994
995 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
996 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
997 } else {
998 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
999 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1000 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1001 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1002 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1003 radeon_emit(cmd_buffer->cs, cb_color_info);
1004 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1005 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1006 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1007 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1008 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1009 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1010
1011 if (is_vi) { /* DCC BASE */
1012 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1013 }
1014 }
1015 }
1016
1017 static void
1018 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1019 struct radv_ds_buffer_info *ds,
1020 struct radv_image *image,
1021 VkImageLayout layout)
1022 {
1023 uint32_t db_z_info = ds->db_z_info;
1024 uint32_t db_stencil_info = ds->db_stencil_info;
1025
1026 if (!radv_layout_has_htile(image, layout,
1027 radv_image_queue_family_mask(image,
1028 cmd_buffer->queue_family_index,
1029 cmd_buffer->queue_family_index))) {
1030 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1031 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1032 }
1033
1034 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1035 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1036
1037
1038 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1039 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1040 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1041 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1042 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1043
1044 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1045 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1046 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1047 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1048 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1049 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1050 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1051 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1052 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1053 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1054 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1055
1056 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1057 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1058 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1059 } else {
1060 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1061
1062 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1063 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1064 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1065 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1066 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1067 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1068 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1069 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1070 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1071 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1072
1073 }
1074
1075 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1076 ds->pa_su_poly_offset_db_fmt_cntl);
1077 }
1078
1079 void
1080 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1081 struct radv_image *image,
1082 VkClearDepthStencilValue ds_clear_value,
1083 VkImageAspectFlags aspects)
1084 {
1085 uint64_t va = radv_buffer_get_va(image->bo);
1086 va += image->offset + image->clear_value_offset;
1087 unsigned reg_offset = 0, reg_count = 0;
1088
1089 assert(radv_image_has_htile(image));
1090
1091 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1092 ++reg_count;
1093 } else {
1094 ++reg_offset;
1095 va += 4;
1096 }
1097 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1098 ++reg_count;
1099
1100 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1101 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1102 S_370_WR_CONFIRM(1) |
1103 S_370_ENGINE_SEL(V_370_PFP));
1104 radeon_emit(cmd_buffer->cs, va);
1105 radeon_emit(cmd_buffer->cs, va >> 32);
1106 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1107 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1108 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1109 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1110
1111 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1112 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1113 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1114 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1115 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1116 }
1117
1118 static void
1119 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1120 struct radv_image *image)
1121 {
1122 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1123 uint64_t va = radv_buffer_get_va(image->bo);
1124 va += image->offset + image->clear_value_offset;
1125 unsigned reg_offset = 0, reg_count = 0;
1126
1127 if (!radv_image_has_htile(image))
1128 return;
1129
1130 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1131 ++reg_count;
1132 } else {
1133 ++reg_offset;
1134 va += 4;
1135 }
1136 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1137 ++reg_count;
1138
1139 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1140 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1141 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1142 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1143 radeon_emit(cmd_buffer->cs, va);
1144 radeon_emit(cmd_buffer->cs, va >> 32);
1145 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1146 radeon_emit(cmd_buffer->cs, 0);
1147
1148 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1149 radeon_emit(cmd_buffer->cs, 0);
1150 }
1151
1152 /*
1153 * With DCC some colors don't require CMASK elimination before being
1154 * used as a texture. This sets a predicate value to determine if the
1155 * cmask eliminate is required.
1156 */
1157 void
1158 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1159 struct radv_image *image,
1160 bool value)
1161 {
1162 uint64_t pred_val = value;
1163 uint64_t va = radv_buffer_get_va(image->bo);
1164 va += image->offset + image->dcc_pred_offset;
1165
1166 assert(radv_image_has_dcc(image));
1167
1168 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1169 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1170 S_370_WR_CONFIRM(1) |
1171 S_370_ENGINE_SEL(V_370_PFP));
1172 radeon_emit(cmd_buffer->cs, va);
1173 radeon_emit(cmd_buffer->cs, va >> 32);
1174 radeon_emit(cmd_buffer->cs, pred_val);
1175 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1176 }
1177
1178 void
1179 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1180 struct radv_image *image,
1181 int idx,
1182 uint32_t color_values[2])
1183 {
1184 uint64_t va = radv_buffer_get_va(image->bo);
1185 va += image->offset + image->clear_value_offset;
1186
1187 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1188
1189 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1190 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1191 S_370_WR_CONFIRM(1) |
1192 S_370_ENGINE_SEL(V_370_PFP));
1193 radeon_emit(cmd_buffer->cs, va);
1194 radeon_emit(cmd_buffer->cs, va >> 32);
1195 radeon_emit(cmd_buffer->cs, color_values[0]);
1196 radeon_emit(cmd_buffer->cs, color_values[1]);
1197
1198 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1199 radeon_emit(cmd_buffer->cs, color_values[0]);
1200 radeon_emit(cmd_buffer->cs, color_values[1]);
1201 }
1202
1203 static void
1204 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1205 struct radv_image *image,
1206 int idx)
1207 {
1208 uint64_t va = radv_buffer_get_va(image->bo);
1209 va += image->offset + image->clear_value_offset;
1210
1211 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1212 return;
1213
1214 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1215
1216 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1217 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1218 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1219 COPY_DATA_COUNT_SEL);
1220 radeon_emit(cmd_buffer->cs, va);
1221 radeon_emit(cmd_buffer->cs, va >> 32);
1222 radeon_emit(cmd_buffer->cs, reg >> 2);
1223 radeon_emit(cmd_buffer->cs, 0);
1224
1225 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1226 radeon_emit(cmd_buffer->cs, 0);
1227 }
1228
1229 static void
1230 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1231 {
1232 int i;
1233 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1234 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1235
1236 /* this may happen for inherited secondary recording */
1237 if (!framebuffer)
1238 return;
1239
1240 for (i = 0; i < 8; ++i) {
1241 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1242 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1243 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1244 continue;
1245 }
1246
1247 int idx = subpass->color_attachments[i].attachment;
1248 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1249 struct radv_image *image = att->attachment->image;
1250 VkImageLayout layout = subpass->color_attachments[i].layout;
1251
1252 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1253
1254 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1255 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1256
1257 radv_load_color_clear_regs(cmd_buffer, image, i);
1258 }
1259
1260 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1261 int idx = subpass->depth_stencil_attachment.attachment;
1262 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1263 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1264 struct radv_image *image = att->attachment->image;
1265 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1266 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1267 cmd_buffer->queue_family_index,
1268 cmd_buffer->queue_family_index);
1269 /* We currently don't support writing decompressed HTILE */
1270 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1271 radv_layout_is_htile_compressed(image, layout, queue_mask));
1272
1273 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1274
1275 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1276 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1277 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1278 }
1279 radv_load_depth_clear_regs(cmd_buffer, image);
1280 } else {
1281 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1282 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1283 else
1284 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1285
1286 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1287 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1288 }
1289 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1290 S_028208_BR_X(framebuffer->width) |
1291 S_028208_BR_Y(framebuffer->height));
1292
1293 if (cmd_buffer->device->dfsm_allowed) {
1294 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1295 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1296 }
1297
1298 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1299 }
1300
1301 static void
1302 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1303 {
1304 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1305 struct radv_cmd_state *state = &cmd_buffer->state;
1306
1307 if (state->index_type != state->last_index_type) {
1308 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1309 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1310 2, state->index_type);
1311 } else {
1312 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1313 radeon_emit(cs, state->index_type);
1314 }
1315
1316 state->last_index_type = state->index_type;
1317 }
1318
1319 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1320 radeon_emit(cs, state->index_va);
1321 radeon_emit(cs, state->index_va >> 32);
1322
1323 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1324 radeon_emit(cs, state->max_index_count);
1325
1326 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1327 }
1328
1329 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1330 {
1331 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1332 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1333 uint32_t pa_sc_mode_cntl_1 =
1334 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1335 uint32_t db_count_control;
1336
1337 if(!cmd_buffer->state.active_occlusion_queries) {
1338 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1339 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1340 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1341 has_perfect_queries) {
1342 /* Re-enable out-of-order rasterization if the
1343 * bound pipeline supports it and if it's has
1344 * been disabled before starting any perfect
1345 * occlusion queries.
1346 */
1347 radeon_set_context_reg(cmd_buffer->cs,
1348 R_028A4C_PA_SC_MODE_CNTL_1,
1349 pa_sc_mode_cntl_1);
1350 }
1351 db_count_control = 0;
1352 } else {
1353 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1354 }
1355 } else {
1356 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1357 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1358
1359 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1360 db_count_control =
1361 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1362 S_028004_SAMPLE_RATE(sample_rate) |
1363 S_028004_ZPASS_ENABLE(1) |
1364 S_028004_SLICE_EVEN_ENABLE(1) |
1365 S_028004_SLICE_ODD_ENABLE(1);
1366
1367 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1368 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1369 has_perfect_queries) {
1370 /* If the bound pipeline has enabled
1371 * out-of-order rasterization, we should
1372 * disable it before starting any perfect
1373 * occlusion queries.
1374 */
1375 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1376
1377 radeon_set_context_reg(cmd_buffer->cs,
1378 R_028A4C_PA_SC_MODE_CNTL_1,
1379 pa_sc_mode_cntl_1);
1380 }
1381 } else {
1382 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1383 S_028004_SAMPLE_RATE(sample_rate);
1384 }
1385 }
1386
1387 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1388 }
1389
1390 static void
1391 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1392 {
1393 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1394
1395 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1396 radv_emit_viewport(cmd_buffer);
1397
1398 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1399 !cmd_buffer->device->physical_device->has_scissor_bug)
1400 radv_emit_scissor(cmd_buffer);
1401
1402 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1403 radv_emit_line_width(cmd_buffer);
1404
1405 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1406 radv_emit_blend_constants(cmd_buffer);
1407
1408 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1409 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1410 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1411 radv_emit_stencil(cmd_buffer);
1412
1413 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1414 radv_emit_depth_bounds(cmd_buffer);
1415
1416 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1417 radv_emit_depth_bias(cmd_buffer);
1418
1419 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1420 radv_emit_discard_rectangle(cmd_buffer);
1421
1422 cmd_buffer->state.dirty &= ~states;
1423 }
1424
1425 static void
1426 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1427 struct radv_pipeline *pipeline,
1428 int idx,
1429 uint64_t va,
1430 gl_shader_stage stage)
1431 {
1432 struct radv_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1433 uint32_t base_reg = pipeline->user_data_0[stage];
1434
1435 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1436 return;
1437
1438 assert(!desc_set_loc->indirect);
1439 assert(desc_set_loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
1440
1441 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1442 base_reg + desc_set_loc->sgpr_idx * 4, va, false);
1443 }
1444
1445 static void
1446 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1447 VkShaderStageFlags stages,
1448 struct radv_descriptor_set *set,
1449 unsigned idx)
1450 {
1451 if (cmd_buffer->state.pipeline) {
1452 radv_foreach_stage(stage, stages) {
1453 if (cmd_buffer->state.pipeline->shaders[stage])
1454 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1455 idx, set->va,
1456 stage);
1457 }
1458 }
1459
1460 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1461 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1462 idx, set->va,
1463 MESA_SHADER_COMPUTE);
1464 }
1465
1466 static void
1467 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1468 VkPipelineBindPoint bind_point)
1469 {
1470 struct radv_descriptor_state *descriptors_state =
1471 radv_get_descriptors_state(cmd_buffer, bind_point);
1472 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1473 unsigned bo_offset;
1474
1475 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1476 set->mapped_ptr,
1477 &bo_offset))
1478 return;
1479
1480 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1481 set->va += bo_offset;
1482 }
1483
1484 static void
1485 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1486 VkPipelineBindPoint bind_point)
1487 {
1488 struct radv_descriptor_state *descriptors_state =
1489 radv_get_descriptors_state(cmd_buffer, bind_point);
1490 uint32_t size = MAX_SETS * 2 * 4;
1491 uint32_t offset;
1492 void *ptr;
1493
1494 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1495 256, &offset, &ptr))
1496 return;
1497
1498 for (unsigned i = 0; i < MAX_SETS; i++) {
1499 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1500 uint64_t set_va = 0;
1501 struct radv_descriptor_set *set = descriptors_state->sets[i];
1502 if (descriptors_state->valid & (1u << i))
1503 set_va = set->va;
1504 uptr[0] = set_va & 0xffffffff;
1505 uptr[1] = set_va >> 32;
1506 }
1507
1508 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1509 va += offset;
1510
1511 if (cmd_buffer->state.pipeline) {
1512 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1513 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1514 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1515
1516 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1517 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1518 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1519
1520 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1521 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1522 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1523
1524 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1525 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1526 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1527
1528 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1529 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1530 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1531 }
1532
1533 if (cmd_buffer->state.compute_pipeline)
1534 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1535 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1536 }
1537
1538 static void
1539 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1540 VkShaderStageFlags stages)
1541 {
1542 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1543 VK_PIPELINE_BIND_POINT_COMPUTE :
1544 VK_PIPELINE_BIND_POINT_GRAPHICS;
1545 struct radv_descriptor_state *descriptors_state =
1546 radv_get_descriptors_state(cmd_buffer, bind_point);
1547 unsigned i;
1548
1549 if (!descriptors_state->dirty)
1550 return;
1551
1552 if (descriptors_state->push_dirty)
1553 radv_flush_push_descriptors(cmd_buffer, bind_point);
1554
1555 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1556 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1557 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1558 }
1559
1560 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1561 cmd_buffer->cs,
1562 MAX_SETS * MESA_SHADER_STAGES * 4);
1563
1564 for_each_bit(i, descriptors_state->dirty) {
1565 struct radv_descriptor_set *set = descriptors_state->sets[i];
1566 if (!(descriptors_state->valid & (1u << i)))
1567 continue;
1568
1569 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1570 }
1571 descriptors_state->dirty = 0;
1572 descriptors_state->push_dirty = false;
1573
1574 if (unlikely(cmd_buffer->device->trace_bo))
1575 radv_save_descriptors(cmd_buffer, bind_point);
1576
1577 assert(cmd_buffer->cs->cdw <= cdw_max);
1578 }
1579
1580 static void
1581 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1582 VkShaderStageFlags stages)
1583 {
1584 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1585 ? cmd_buffer->state.compute_pipeline
1586 : cmd_buffer->state.pipeline;
1587 struct radv_pipeline_layout *layout = pipeline->layout;
1588 unsigned offset;
1589 void *ptr;
1590 uint64_t va;
1591
1592 stages &= cmd_buffer->push_constant_stages;
1593 if (!stages ||
1594 (!layout->push_constant_size && !layout->dynamic_offset_count))
1595 return;
1596
1597 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1598 16 * layout->dynamic_offset_count,
1599 256, &offset, &ptr))
1600 return;
1601
1602 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1603 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1604 16 * layout->dynamic_offset_count);
1605
1606 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1607 va += offset;
1608
1609 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1610 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1611
1612 radv_foreach_stage(stage, stages) {
1613 if (pipeline->shaders[stage]) {
1614 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1615 AC_UD_PUSH_CONSTANTS, va);
1616 }
1617 }
1618
1619 cmd_buffer->push_constant_stages &= ~stages;
1620 assert(cmd_buffer->cs->cdw <= cdw_max);
1621 }
1622
1623 static void
1624 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1625 bool pipeline_is_dirty)
1626 {
1627 if ((pipeline_is_dirty ||
1628 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1629 cmd_buffer->state.pipeline->vertex_elements.count &&
1630 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1631 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1632 unsigned vb_offset;
1633 void *vb_ptr;
1634 uint32_t i = 0;
1635 uint32_t count = velems->count;
1636 uint64_t va;
1637
1638 /* allocate some descriptor state for vertex buffers */
1639 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1640 &vb_offset, &vb_ptr))
1641 return;
1642
1643 for (i = 0; i < count; i++) {
1644 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1645 uint32_t offset;
1646 int vb = velems->binding[i];
1647 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1648 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1649
1650 va = radv_buffer_get_va(buffer->bo);
1651
1652 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1653 va += offset + buffer->offset;
1654 desc[0] = va;
1655 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1656 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1657 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1658 else
1659 desc[2] = buffer->size - offset;
1660 desc[3] = velems->rsrc_word3[i];
1661 }
1662
1663 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1664 va += vb_offset;
1665
1666 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1667 AC_UD_VS_VERTEX_BUFFERS, va);
1668
1669 cmd_buffer->state.vb_va = va;
1670 cmd_buffer->state.vb_size = count * 16;
1671 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1672 }
1673 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1674 }
1675
1676 static void
1677 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1678 {
1679 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1680 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1681 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1682 }
1683
1684 static void
1685 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1686 bool instanced_draw, bool indirect_draw,
1687 uint32_t draw_vertex_count)
1688 {
1689 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1690 struct radv_cmd_state *state = &cmd_buffer->state;
1691 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1692 uint32_t ia_multi_vgt_param;
1693 int32_t primitive_reset_en;
1694
1695 /* Draw state. */
1696 ia_multi_vgt_param =
1697 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1698 indirect_draw, draw_vertex_count);
1699
1700 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1701 if (info->chip_class >= GFX9) {
1702 radeon_set_uconfig_reg_idx(cs,
1703 R_030960_IA_MULTI_VGT_PARAM,
1704 4, ia_multi_vgt_param);
1705 } else if (info->chip_class >= CIK) {
1706 radeon_set_context_reg_idx(cs,
1707 R_028AA8_IA_MULTI_VGT_PARAM,
1708 1, ia_multi_vgt_param);
1709 } else {
1710 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1711 ia_multi_vgt_param);
1712 }
1713 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1714 }
1715
1716 /* Primitive restart. */
1717 primitive_reset_en =
1718 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1719
1720 if (primitive_reset_en != state->last_primitive_reset_en) {
1721 state->last_primitive_reset_en = primitive_reset_en;
1722 if (info->chip_class >= GFX9) {
1723 radeon_set_uconfig_reg(cs,
1724 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1725 primitive_reset_en);
1726 } else {
1727 radeon_set_context_reg(cs,
1728 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1729 primitive_reset_en);
1730 }
1731 }
1732
1733 if (primitive_reset_en) {
1734 uint32_t primitive_reset_index =
1735 state->index_type ? 0xffffffffu : 0xffffu;
1736
1737 if (primitive_reset_index != state->last_primitive_reset_index) {
1738 radeon_set_context_reg(cs,
1739 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1740 primitive_reset_index);
1741 state->last_primitive_reset_index = primitive_reset_index;
1742 }
1743 }
1744 }
1745
1746 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1747 VkPipelineStageFlags src_stage_mask)
1748 {
1749 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1750 VK_PIPELINE_STAGE_TRANSFER_BIT |
1751 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1752 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1753 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1754 }
1755
1756 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1757 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1758 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1759 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1760 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1761 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1762 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1763 VK_PIPELINE_STAGE_TRANSFER_BIT |
1764 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1765 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1766 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1767 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1768 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1769 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1770 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1771 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1772 }
1773 }
1774
1775 static enum radv_cmd_flush_bits
1776 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1777 VkAccessFlags src_flags)
1778 {
1779 enum radv_cmd_flush_bits flush_bits = 0;
1780 uint32_t b;
1781 for_each_bit(b, src_flags) {
1782 switch ((VkAccessFlagBits)(1 << b)) {
1783 case VK_ACCESS_SHADER_WRITE_BIT:
1784 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1785 break;
1786 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1787 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1788 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1789 break;
1790 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1791 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1792 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1793 break;
1794 case VK_ACCESS_TRANSFER_WRITE_BIT:
1795 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1796 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1797 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1798 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1799 RADV_CMD_FLAG_INV_GLOBAL_L2;
1800 break;
1801 default:
1802 break;
1803 }
1804 }
1805 return flush_bits;
1806 }
1807
1808 static enum radv_cmd_flush_bits
1809 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1810 VkAccessFlags dst_flags,
1811 struct radv_image *image)
1812 {
1813 enum radv_cmd_flush_bits flush_bits = 0;
1814 uint32_t b;
1815 for_each_bit(b, dst_flags) {
1816 switch ((VkAccessFlagBits)(1 << b)) {
1817 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1818 case VK_ACCESS_INDEX_READ_BIT:
1819 break;
1820 case VK_ACCESS_UNIFORM_READ_BIT:
1821 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1822 break;
1823 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1824 case VK_ACCESS_SHADER_READ_BIT:
1825 case VK_ACCESS_TRANSFER_READ_BIT:
1826 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1827 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1828 RADV_CMD_FLAG_INV_GLOBAL_L2;
1829 break;
1830 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1831 /* TODO: change to image && when the image gets passed
1832 * through from the subpass. */
1833 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1834 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1835 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1836 break;
1837 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1838 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1839 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1840 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1841 break;
1842 default:
1843 break;
1844 }
1845 }
1846 return flush_bits;
1847 }
1848
1849 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1850 {
1851 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1852 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1853 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1854 NULL);
1855 }
1856
1857 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1858 VkAttachmentReference att)
1859 {
1860 unsigned idx = att.attachment;
1861 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1862 VkImageSubresourceRange range;
1863 range.aspectMask = 0;
1864 range.baseMipLevel = view->base_mip;
1865 range.levelCount = 1;
1866 range.baseArrayLayer = view->base_layer;
1867 range.layerCount = cmd_buffer->state.framebuffer->layers;
1868
1869 radv_handle_image_transition(cmd_buffer,
1870 view->image,
1871 cmd_buffer->state.attachments[idx].current_layout,
1872 att.layout, 0, 0, &range,
1873 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1874
1875 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1876
1877
1878 }
1879
1880 void
1881 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1882 const struct radv_subpass *subpass, bool transitions)
1883 {
1884 if (transitions) {
1885 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1886
1887 for (unsigned i = 0; i < subpass->color_count; ++i) {
1888 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1889 radv_handle_subpass_image_transition(cmd_buffer,
1890 subpass->color_attachments[i]);
1891 }
1892
1893 for (unsigned i = 0; i < subpass->input_count; ++i) {
1894 radv_handle_subpass_image_transition(cmd_buffer,
1895 subpass->input_attachments[i]);
1896 }
1897
1898 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1899 radv_handle_subpass_image_transition(cmd_buffer,
1900 subpass->depth_stencil_attachment);
1901 }
1902 }
1903
1904 cmd_buffer->state.subpass = subpass;
1905
1906 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
1907 }
1908
1909 static VkResult
1910 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1911 struct radv_render_pass *pass,
1912 const VkRenderPassBeginInfo *info)
1913 {
1914 struct radv_cmd_state *state = &cmd_buffer->state;
1915
1916 if (pass->attachment_count == 0) {
1917 state->attachments = NULL;
1918 return VK_SUCCESS;
1919 }
1920
1921 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1922 pass->attachment_count *
1923 sizeof(state->attachments[0]),
1924 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1925 if (state->attachments == NULL) {
1926 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1927 return cmd_buffer->record_result;
1928 }
1929
1930 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1931 struct radv_render_pass_attachment *att = &pass->attachments[i];
1932 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1933 VkImageAspectFlags clear_aspects = 0;
1934
1935 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1936 /* color attachment */
1937 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1938 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1939 }
1940 } else {
1941 /* depthstencil attachment */
1942 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1943 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1944 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1945 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1946 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1947 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1948 }
1949 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1950 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1951 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1952 }
1953 }
1954
1955 state->attachments[i].pending_clear_aspects = clear_aspects;
1956 state->attachments[i].cleared_views = 0;
1957 if (clear_aspects && info) {
1958 assert(info->clearValueCount > i);
1959 state->attachments[i].clear_value = info->pClearValues[i];
1960 }
1961
1962 state->attachments[i].current_layout = att->initial_layout;
1963 }
1964
1965 return VK_SUCCESS;
1966 }
1967
1968 VkResult radv_AllocateCommandBuffers(
1969 VkDevice _device,
1970 const VkCommandBufferAllocateInfo *pAllocateInfo,
1971 VkCommandBuffer *pCommandBuffers)
1972 {
1973 RADV_FROM_HANDLE(radv_device, device, _device);
1974 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1975
1976 VkResult result = VK_SUCCESS;
1977 uint32_t i;
1978
1979 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1980
1981 if (!list_empty(&pool->free_cmd_buffers)) {
1982 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1983
1984 list_del(&cmd_buffer->pool_link);
1985 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1986
1987 result = radv_reset_cmd_buffer(cmd_buffer);
1988 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1989 cmd_buffer->level = pAllocateInfo->level;
1990
1991 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1992 } else {
1993 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1994 &pCommandBuffers[i]);
1995 }
1996 if (result != VK_SUCCESS)
1997 break;
1998 }
1999
2000 if (result != VK_SUCCESS) {
2001 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2002 i, pCommandBuffers);
2003
2004 /* From the Vulkan 1.0.66 spec:
2005 *
2006 * "vkAllocateCommandBuffers can be used to create multiple
2007 * command buffers. If the creation of any of those command
2008 * buffers fails, the implementation must destroy all
2009 * successfully created command buffer objects from this
2010 * command, set all entries of the pCommandBuffers array to
2011 * NULL and return the error."
2012 */
2013 memset(pCommandBuffers, 0,
2014 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2015 }
2016
2017 return result;
2018 }
2019
2020 void radv_FreeCommandBuffers(
2021 VkDevice device,
2022 VkCommandPool commandPool,
2023 uint32_t commandBufferCount,
2024 const VkCommandBuffer *pCommandBuffers)
2025 {
2026 for (uint32_t i = 0; i < commandBufferCount; i++) {
2027 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2028
2029 if (cmd_buffer) {
2030 if (cmd_buffer->pool) {
2031 list_del(&cmd_buffer->pool_link);
2032 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2033 } else
2034 radv_cmd_buffer_destroy(cmd_buffer);
2035
2036 }
2037 }
2038 }
2039
2040 VkResult radv_ResetCommandBuffer(
2041 VkCommandBuffer commandBuffer,
2042 VkCommandBufferResetFlags flags)
2043 {
2044 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2045 return radv_reset_cmd_buffer(cmd_buffer);
2046 }
2047
2048 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2049 {
2050 struct radv_device *device = cmd_buffer->device;
2051 if (device->gfx_init) {
2052 uint64_t va = radv_buffer_get_va(device->gfx_init);
2053 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2054 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2055 radeon_emit(cmd_buffer->cs, va);
2056 radeon_emit(cmd_buffer->cs, va >> 32);
2057 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2058 } else
2059 si_init_config(cmd_buffer);
2060 }
2061
2062 VkResult radv_BeginCommandBuffer(
2063 VkCommandBuffer commandBuffer,
2064 const VkCommandBufferBeginInfo *pBeginInfo)
2065 {
2066 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2067 VkResult result = VK_SUCCESS;
2068
2069 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2070 /* If the command buffer has already been resetted with
2071 * vkResetCommandBuffer, no need to do it again.
2072 */
2073 result = radv_reset_cmd_buffer(cmd_buffer);
2074 if (result != VK_SUCCESS)
2075 return result;
2076 }
2077
2078 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2079 cmd_buffer->state.last_primitive_reset_en = -1;
2080 cmd_buffer->state.last_index_type = -1;
2081 cmd_buffer->state.last_num_instances = -1;
2082 cmd_buffer->state.last_vertex_offset = -1;
2083 cmd_buffer->state.last_first_instance = -1;
2084 cmd_buffer->usage_flags = pBeginInfo->flags;
2085
2086 /* setup initial configuration into command buffer */
2087 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2088 switch (cmd_buffer->queue_family_index) {
2089 case RADV_QUEUE_GENERAL:
2090 emit_gfx_buffer_state(cmd_buffer);
2091 break;
2092 case RADV_QUEUE_COMPUTE:
2093 si_init_compute(cmd_buffer);
2094 break;
2095 case RADV_QUEUE_TRANSFER:
2096 default:
2097 break;
2098 }
2099 }
2100
2101 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2102 assert(pBeginInfo->pInheritanceInfo);
2103 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2104 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2105
2106 struct radv_subpass *subpass =
2107 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2108
2109 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2110 if (result != VK_SUCCESS)
2111 return result;
2112
2113 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2114 }
2115
2116 if (unlikely(cmd_buffer->device->trace_bo))
2117 radv_cmd_buffer_trace_emit(cmd_buffer);
2118
2119 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2120
2121 return result;
2122 }
2123
2124 void radv_CmdBindVertexBuffers(
2125 VkCommandBuffer commandBuffer,
2126 uint32_t firstBinding,
2127 uint32_t bindingCount,
2128 const VkBuffer* pBuffers,
2129 const VkDeviceSize* pOffsets)
2130 {
2131 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2132 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2133 bool changed = false;
2134
2135 /* We have to defer setting up vertex buffer since we need the buffer
2136 * stride from the pipeline. */
2137
2138 assert(firstBinding + bindingCount <= MAX_VBS);
2139 for (uint32_t i = 0; i < bindingCount; i++) {
2140 uint32_t idx = firstBinding + i;
2141
2142 if (!changed &&
2143 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2144 vb[idx].offset != pOffsets[i])) {
2145 changed = true;
2146 }
2147
2148 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2149 vb[idx].offset = pOffsets[i];
2150
2151 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2152 vb[idx].buffer->bo, 8);
2153 }
2154
2155 if (!changed) {
2156 /* No state changes. */
2157 return;
2158 }
2159
2160 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2161 }
2162
2163 void radv_CmdBindIndexBuffer(
2164 VkCommandBuffer commandBuffer,
2165 VkBuffer buffer,
2166 VkDeviceSize offset,
2167 VkIndexType indexType)
2168 {
2169 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2170 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2171
2172 if (cmd_buffer->state.index_buffer == index_buffer &&
2173 cmd_buffer->state.index_offset == offset &&
2174 cmd_buffer->state.index_type == indexType) {
2175 /* No state changes. */
2176 return;
2177 }
2178
2179 cmd_buffer->state.index_buffer = index_buffer;
2180 cmd_buffer->state.index_offset = offset;
2181 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2182 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2183 cmd_buffer->state.index_va += index_buffer->offset + offset;
2184
2185 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2186 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2187 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2188 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2189 }
2190
2191
2192 static void
2193 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2194 VkPipelineBindPoint bind_point,
2195 struct radv_descriptor_set *set, unsigned idx)
2196 {
2197 struct radeon_winsys *ws = cmd_buffer->device->ws;
2198
2199 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2200 if (!set)
2201 return;
2202
2203 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2204
2205 if (!cmd_buffer->device->use_global_bo_list) {
2206 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2207 if (set->descriptors[j])
2208 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2209 }
2210
2211 if(set->bo)
2212 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2213 }
2214
2215 void radv_CmdBindDescriptorSets(
2216 VkCommandBuffer commandBuffer,
2217 VkPipelineBindPoint pipelineBindPoint,
2218 VkPipelineLayout _layout,
2219 uint32_t firstSet,
2220 uint32_t descriptorSetCount,
2221 const VkDescriptorSet* pDescriptorSets,
2222 uint32_t dynamicOffsetCount,
2223 const uint32_t* pDynamicOffsets)
2224 {
2225 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2226 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2227 unsigned dyn_idx = 0;
2228
2229 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2230
2231 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2232 unsigned idx = i + firstSet;
2233 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2234 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2235
2236 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2237 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2238 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2239 assert(dyn_idx < dynamicOffsetCount);
2240
2241 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2242 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2243 dst[0] = va;
2244 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2245 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2246 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2247 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2248 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2249 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2250 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2251 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2252 cmd_buffer->push_constant_stages |=
2253 set->layout->dynamic_shader_stages;
2254 }
2255 }
2256 }
2257
2258 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2259 struct radv_descriptor_set *set,
2260 struct radv_descriptor_set_layout *layout,
2261 VkPipelineBindPoint bind_point)
2262 {
2263 struct radv_descriptor_state *descriptors_state =
2264 radv_get_descriptors_state(cmd_buffer, bind_point);
2265 set->size = layout->size;
2266 set->layout = layout;
2267
2268 if (descriptors_state->push_set.capacity < set->size) {
2269 size_t new_size = MAX2(set->size, 1024);
2270 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2271 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2272
2273 free(set->mapped_ptr);
2274 set->mapped_ptr = malloc(new_size);
2275
2276 if (!set->mapped_ptr) {
2277 descriptors_state->push_set.capacity = 0;
2278 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2279 return false;
2280 }
2281
2282 descriptors_state->push_set.capacity = new_size;
2283 }
2284
2285 return true;
2286 }
2287
2288 void radv_meta_push_descriptor_set(
2289 struct radv_cmd_buffer* cmd_buffer,
2290 VkPipelineBindPoint pipelineBindPoint,
2291 VkPipelineLayout _layout,
2292 uint32_t set,
2293 uint32_t descriptorWriteCount,
2294 const VkWriteDescriptorSet* pDescriptorWrites)
2295 {
2296 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2297 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2298 unsigned bo_offset;
2299
2300 assert(set == 0);
2301 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2302
2303 push_set->size = layout->set[set].layout->size;
2304 push_set->layout = layout->set[set].layout;
2305
2306 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2307 &bo_offset,
2308 (void**) &push_set->mapped_ptr))
2309 return;
2310
2311 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2312 push_set->va += bo_offset;
2313
2314 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2315 radv_descriptor_set_to_handle(push_set),
2316 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2317
2318 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2319 }
2320
2321 void radv_CmdPushDescriptorSetKHR(
2322 VkCommandBuffer commandBuffer,
2323 VkPipelineBindPoint pipelineBindPoint,
2324 VkPipelineLayout _layout,
2325 uint32_t set,
2326 uint32_t descriptorWriteCount,
2327 const VkWriteDescriptorSet* pDescriptorWrites)
2328 {
2329 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2330 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2331 struct radv_descriptor_state *descriptors_state =
2332 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2333 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2334
2335 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2336
2337 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2338 layout->set[set].layout,
2339 pipelineBindPoint))
2340 return;
2341
2342 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2343 radv_descriptor_set_to_handle(push_set),
2344 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2345
2346 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2347 descriptors_state->push_dirty = true;
2348 }
2349
2350 void radv_CmdPushDescriptorSetWithTemplateKHR(
2351 VkCommandBuffer commandBuffer,
2352 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2353 VkPipelineLayout _layout,
2354 uint32_t set,
2355 const void* pData)
2356 {
2357 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2358 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2359 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2360 struct radv_descriptor_state *descriptors_state =
2361 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2362 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2363
2364 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2365
2366 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2367 layout->set[set].layout,
2368 templ->bind_point))
2369 return;
2370
2371 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2372 descriptorUpdateTemplate, pData);
2373
2374 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2375 descriptors_state->push_dirty = true;
2376 }
2377
2378 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2379 VkPipelineLayout layout,
2380 VkShaderStageFlags stageFlags,
2381 uint32_t offset,
2382 uint32_t size,
2383 const void* pValues)
2384 {
2385 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2386 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2387 cmd_buffer->push_constant_stages |= stageFlags;
2388 }
2389
2390 VkResult radv_EndCommandBuffer(
2391 VkCommandBuffer commandBuffer)
2392 {
2393 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2394
2395 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2396 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2397 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2398 si_emit_cache_flush(cmd_buffer);
2399 }
2400
2401 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2402
2403 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2404 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2405
2406 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2407
2408 return cmd_buffer->record_result;
2409 }
2410
2411 static void
2412 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2413 {
2414 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2415
2416 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2417 return;
2418
2419 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2420
2421 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2422 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2423
2424 cmd_buffer->compute_scratch_size_needed =
2425 MAX2(cmd_buffer->compute_scratch_size_needed,
2426 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2427
2428 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2429 pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
2430
2431 if (unlikely(cmd_buffer->device->trace_bo))
2432 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2433 }
2434
2435 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2436 VkPipelineBindPoint bind_point)
2437 {
2438 struct radv_descriptor_state *descriptors_state =
2439 radv_get_descriptors_state(cmd_buffer, bind_point);
2440
2441 descriptors_state->dirty |= descriptors_state->valid;
2442 }
2443
2444 void radv_CmdBindPipeline(
2445 VkCommandBuffer commandBuffer,
2446 VkPipelineBindPoint pipelineBindPoint,
2447 VkPipeline _pipeline)
2448 {
2449 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2450 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2451
2452 switch (pipelineBindPoint) {
2453 case VK_PIPELINE_BIND_POINT_COMPUTE:
2454 if (cmd_buffer->state.compute_pipeline == pipeline)
2455 return;
2456 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2457
2458 cmd_buffer->state.compute_pipeline = pipeline;
2459 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2460 break;
2461 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2462 if (cmd_buffer->state.pipeline == pipeline)
2463 return;
2464 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2465
2466 cmd_buffer->state.pipeline = pipeline;
2467 if (!pipeline)
2468 break;
2469
2470 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2471 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2472
2473 /* the new vertex shader might not have the same user regs */
2474 cmd_buffer->state.last_first_instance = -1;
2475 cmd_buffer->state.last_vertex_offset = -1;
2476
2477 /* Prefetch all pipeline shaders at first draw time. */
2478 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2479
2480 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2481
2482 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2483 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2484 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2485 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2486
2487 if (radv_pipeline_has_tess(pipeline))
2488 cmd_buffer->tess_rings_needed = true;
2489
2490 if (radv_pipeline_has_gs(pipeline)) {
2491 struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2492 AC_UD_SCRATCH_RING_OFFSETS);
2493 if (cmd_buffer->ring_offsets_idx == -1)
2494 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2495 else if (loc->sgpr_idx != -1)
2496 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2497 }
2498 break;
2499 default:
2500 assert(!"invalid bind point");
2501 break;
2502 }
2503 }
2504
2505 void radv_CmdSetViewport(
2506 VkCommandBuffer commandBuffer,
2507 uint32_t firstViewport,
2508 uint32_t viewportCount,
2509 const VkViewport* pViewports)
2510 {
2511 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2512 struct radv_cmd_state *state = &cmd_buffer->state;
2513 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2514
2515 assert(firstViewport < MAX_VIEWPORTS);
2516 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2517
2518 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2519 viewportCount * sizeof(*pViewports));
2520
2521 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2522 }
2523
2524 void radv_CmdSetScissor(
2525 VkCommandBuffer commandBuffer,
2526 uint32_t firstScissor,
2527 uint32_t scissorCount,
2528 const VkRect2D* pScissors)
2529 {
2530 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2531 struct radv_cmd_state *state = &cmd_buffer->state;
2532 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2533
2534 assert(firstScissor < MAX_SCISSORS);
2535 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2536
2537 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2538 scissorCount * sizeof(*pScissors));
2539
2540 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2541 }
2542
2543 void radv_CmdSetLineWidth(
2544 VkCommandBuffer commandBuffer,
2545 float lineWidth)
2546 {
2547 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2548 cmd_buffer->state.dynamic.line_width = lineWidth;
2549 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2550 }
2551
2552 void radv_CmdSetDepthBias(
2553 VkCommandBuffer commandBuffer,
2554 float depthBiasConstantFactor,
2555 float depthBiasClamp,
2556 float depthBiasSlopeFactor)
2557 {
2558 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2559
2560 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2561 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2562 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2563
2564 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2565 }
2566
2567 void radv_CmdSetBlendConstants(
2568 VkCommandBuffer commandBuffer,
2569 const float blendConstants[4])
2570 {
2571 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2572
2573 memcpy(cmd_buffer->state.dynamic.blend_constants,
2574 blendConstants, sizeof(float) * 4);
2575
2576 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2577 }
2578
2579 void radv_CmdSetDepthBounds(
2580 VkCommandBuffer commandBuffer,
2581 float minDepthBounds,
2582 float maxDepthBounds)
2583 {
2584 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2585
2586 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2587 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2588
2589 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2590 }
2591
2592 void radv_CmdSetStencilCompareMask(
2593 VkCommandBuffer commandBuffer,
2594 VkStencilFaceFlags faceMask,
2595 uint32_t compareMask)
2596 {
2597 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2598
2599 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2600 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2601 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2602 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2603
2604 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2605 }
2606
2607 void radv_CmdSetStencilWriteMask(
2608 VkCommandBuffer commandBuffer,
2609 VkStencilFaceFlags faceMask,
2610 uint32_t writeMask)
2611 {
2612 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2613
2614 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2615 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2616 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2617 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2618
2619 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2620 }
2621
2622 void radv_CmdSetStencilReference(
2623 VkCommandBuffer commandBuffer,
2624 VkStencilFaceFlags faceMask,
2625 uint32_t reference)
2626 {
2627 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2628
2629 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2630 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2631 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2632 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2633
2634 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2635 }
2636
2637 void radv_CmdSetDiscardRectangleEXT(
2638 VkCommandBuffer commandBuffer,
2639 uint32_t firstDiscardRectangle,
2640 uint32_t discardRectangleCount,
2641 const VkRect2D* pDiscardRectangles)
2642 {
2643 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2644 struct radv_cmd_state *state = &cmd_buffer->state;
2645 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2646
2647 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2648 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2649
2650 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2651 pDiscardRectangles, discardRectangleCount);
2652
2653 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2654 }
2655
2656 void radv_CmdExecuteCommands(
2657 VkCommandBuffer commandBuffer,
2658 uint32_t commandBufferCount,
2659 const VkCommandBuffer* pCmdBuffers)
2660 {
2661 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2662
2663 assert(commandBufferCount > 0);
2664
2665 /* Emit pending flushes on primary prior to executing secondary */
2666 si_emit_cache_flush(primary);
2667
2668 for (uint32_t i = 0; i < commandBufferCount; i++) {
2669 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2670
2671 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2672 secondary->scratch_size_needed);
2673 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2674 secondary->compute_scratch_size_needed);
2675
2676 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2677 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2678 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2679 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2680 if (secondary->tess_rings_needed)
2681 primary->tess_rings_needed = true;
2682 if (secondary->sample_positions_needed)
2683 primary->sample_positions_needed = true;
2684
2685 if (secondary->ring_offsets_idx != -1) {
2686 if (primary->ring_offsets_idx == -1)
2687 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2688 else
2689 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2690 }
2691 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2692
2693
2694 /* When the secondary command buffer is compute only we don't
2695 * need to re-emit the current graphics pipeline.
2696 */
2697 if (secondary->state.emitted_pipeline) {
2698 primary->state.emitted_pipeline =
2699 secondary->state.emitted_pipeline;
2700 }
2701
2702 /* When the secondary command buffer is graphics only we don't
2703 * need to re-emit the current compute pipeline.
2704 */
2705 if (secondary->state.emitted_compute_pipeline) {
2706 primary->state.emitted_compute_pipeline =
2707 secondary->state.emitted_compute_pipeline;
2708 }
2709
2710 /* Only re-emit the draw packets when needed. */
2711 if (secondary->state.last_primitive_reset_en != -1) {
2712 primary->state.last_primitive_reset_en =
2713 secondary->state.last_primitive_reset_en;
2714 }
2715
2716 if (secondary->state.last_primitive_reset_index) {
2717 primary->state.last_primitive_reset_index =
2718 secondary->state.last_primitive_reset_index;
2719 }
2720
2721 if (secondary->state.last_ia_multi_vgt_param) {
2722 primary->state.last_ia_multi_vgt_param =
2723 secondary->state.last_ia_multi_vgt_param;
2724 }
2725
2726 primary->state.last_first_instance = secondary->state.last_first_instance;
2727 primary->state.last_num_instances = secondary->state.last_num_instances;
2728 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2729
2730 if (secondary->state.last_index_type != -1) {
2731 primary->state.last_index_type =
2732 secondary->state.last_index_type;
2733 }
2734 }
2735
2736 /* After executing commands from secondary buffers we have to dirty
2737 * some states.
2738 */
2739 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2740 RADV_CMD_DIRTY_INDEX_BUFFER |
2741 RADV_CMD_DIRTY_DYNAMIC_ALL;
2742 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2743 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2744 }
2745
2746 VkResult radv_CreateCommandPool(
2747 VkDevice _device,
2748 const VkCommandPoolCreateInfo* pCreateInfo,
2749 const VkAllocationCallbacks* pAllocator,
2750 VkCommandPool* pCmdPool)
2751 {
2752 RADV_FROM_HANDLE(radv_device, device, _device);
2753 struct radv_cmd_pool *pool;
2754
2755 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2756 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2757 if (pool == NULL)
2758 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2759
2760 if (pAllocator)
2761 pool->alloc = *pAllocator;
2762 else
2763 pool->alloc = device->alloc;
2764
2765 list_inithead(&pool->cmd_buffers);
2766 list_inithead(&pool->free_cmd_buffers);
2767
2768 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2769
2770 *pCmdPool = radv_cmd_pool_to_handle(pool);
2771
2772 return VK_SUCCESS;
2773
2774 }
2775
2776 void radv_DestroyCommandPool(
2777 VkDevice _device,
2778 VkCommandPool commandPool,
2779 const VkAllocationCallbacks* pAllocator)
2780 {
2781 RADV_FROM_HANDLE(radv_device, device, _device);
2782 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2783
2784 if (!pool)
2785 return;
2786
2787 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2788 &pool->cmd_buffers, pool_link) {
2789 radv_cmd_buffer_destroy(cmd_buffer);
2790 }
2791
2792 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2793 &pool->free_cmd_buffers, pool_link) {
2794 radv_cmd_buffer_destroy(cmd_buffer);
2795 }
2796
2797 vk_free2(&device->alloc, pAllocator, pool);
2798 }
2799
2800 VkResult radv_ResetCommandPool(
2801 VkDevice device,
2802 VkCommandPool commandPool,
2803 VkCommandPoolResetFlags flags)
2804 {
2805 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2806 VkResult result;
2807
2808 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2809 &pool->cmd_buffers, pool_link) {
2810 result = radv_reset_cmd_buffer(cmd_buffer);
2811 if (result != VK_SUCCESS)
2812 return result;
2813 }
2814
2815 return VK_SUCCESS;
2816 }
2817
2818 void radv_TrimCommandPool(
2819 VkDevice device,
2820 VkCommandPool commandPool,
2821 VkCommandPoolTrimFlagsKHR flags)
2822 {
2823 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2824
2825 if (!pool)
2826 return;
2827
2828 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2829 &pool->free_cmd_buffers, pool_link) {
2830 radv_cmd_buffer_destroy(cmd_buffer);
2831 }
2832 }
2833
2834 void radv_CmdBeginRenderPass(
2835 VkCommandBuffer commandBuffer,
2836 const VkRenderPassBeginInfo* pRenderPassBegin,
2837 VkSubpassContents contents)
2838 {
2839 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2840 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2841 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2842
2843 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2844 cmd_buffer->cs, 2048);
2845 MAYBE_UNUSED VkResult result;
2846
2847 cmd_buffer->state.framebuffer = framebuffer;
2848 cmd_buffer->state.pass = pass;
2849 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2850
2851 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2852 if (result != VK_SUCCESS)
2853 return;
2854
2855 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2856 assert(cmd_buffer->cs->cdw <= cdw_max);
2857
2858 radv_cmd_buffer_clear_subpass(cmd_buffer);
2859 }
2860
2861 void radv_CmdNextSubpass(
2862 VkCommandBuffer commandBuffer,
2863 VkSubpassContents contents)
2864 {
2865 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2866
2867 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2868
2869 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2870 2048);
2871
2872 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2873 radv_cmd_buffer_clear_subpass(cmd_buffer);
2874 }
2875
2876 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2877 {
2878 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2879 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2880 if (!pipeline->shaders[stage])
2881 continue;
2882 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2883 if (loc->sgpr_idx == -1)
2884 continue;
2885 uint32_t base_reg = pipeline->user_data_0[stage];
2886 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2887
2888 }
2889 if (pipeline->gs_copy_shader) {
2890 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2891 if (loc->sgpr_idx != -1) {
2892 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2893 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2894 }
2895 }
2896 }
2897
2898 static void
2899 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2900 uint32_t vertex_count)
2901 {
2902 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2903 radeon_emit(cmd_buffer->cs, vertex_count);
2904 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2905 S_0287F0_USE_OPAQUE(0));
2906 }
2907
2908 static void
2909 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2910 uint64_t index_va,
2911 uint32_t index_count)
2912 {
2913 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2914 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2915 radeon_emit(cmd_buffer->cs, index_va);
2916 radeon_emit(cmd_buffer->cs, index_va >> 32);
2917 radeon_emit(cmd_buffer->cs, index_count);
2918 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2919 }
2920
2921 static void
2922 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2923 bool indexed,
2924 uint32_t draw_count,
2925 uint64_t count_va,
2926 uint32_t stride)
2927 {
2928 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2929 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2930 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2931 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
2932 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2933 assert(base_reg);
2934
2935 /* just reset draw state for vertex data */
2936 cmd_buffer->state.last_first_instance = -1;
2937 cmd_buffer->state.last_num_instances = -1;
2938 cmd_buffer->state.last_vertex_offset = -1;
2939
2940 if (draw_count == 1 && !count_va && !draw_id_enable) {
2941 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2942 PKT3_DRAW_INDIRECT, 3, false));
2943 radeon_emit(cs, 0);
2944 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2945 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2946 radeon_emit(cs, di_src_sel);
2947 } else {
2948 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2949 PKT3_DRAW_INDIRECT_MULTI,
2950 8, false));
2951 radeon_emit(cs, 0);
2952 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2953 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2954 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2955 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2956 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2957 radeon_emit(cs, draw_count); /* count */
2958 radeon_emit(cs, count_va); /* count_addr */
2959 radeon_emit(cs, count_va >> 32);
2960 radeon_emit(cs, stride); /* stride */
2961 radeon_emit(cs, di_src_sel);
2962 }
2963 }
2964
2965 struct radv_draw_info {
2966 /**
2967 * Number of vertices.
2968 */
2969 uint32_t count;
2970
2971 /**
2972 * Index of the first vertex.
2973 */
2974 int32_t vertex_offset;
2975
2976 /**
2977 * First instance id.
2978 */
2979 uint32_t first_instance;
2980
2981 /**
2982 * Number of instances.
2983 */
2984 uint32_t instance_count;
2985
2986 /**
2987 * First index (indexed draws only).
2988 */
2989 uint32_t first_index;
2990
2991 /**
2992 * Whether it's an indexed draw.
2993 */
2994 bool indexed;
2995
2996 /**
2997 * Indirect draw parameters resource.
2998 */
2999 struct radv_buffer *indirect;
3000 uint64_t indirect_offset;
3001 uint32_t stride;
3002
3003 /**
3004 * Draw count parameters resource.
3005 */
3006 struct radv_buffer *count_buffer;
3007 uint64_t count_buffer_offset;
3008 };
3009
3010 static void
3011 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3012 const struct radv_draw_info *info)
3013 {
3014 struct radv_cmd_state *state = &cmd_buffer->state;
3015 struct radeon_winsys *ws = cmd_buffer->device->ws;
3016 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3017
3018 if (info->indirect) {
3019 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3020 uint64_t count_va = 0;
3021
3022 va += info->indirect->offset + info->indirect_offset;
3023
3024 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3025
3026 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3027 radeon_emit(cs, 1);
3028 radeon_emit(cs, va);
3029 radeon_emit(cs, va >> 32);
3030
3031 if (info->count_buffer) {
3032 count_va = radv_buffer_get_va(info->count_buffer->bo);
3033 count_va += info->count_buffer->offset +
3034 info->count_buffer_offset;
3035
3036 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3037 }
3038
3039 if (!state->subpass->view_mask) {
3040 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3041 info->indexed,
3042 info->count,
3043 count_va,
3044 info->stride);
3045 } else {
3046 unsigned i;
3047 for_each_bit(i, state->subpass->view_mask) {
3048 radv_emit_view_index(cmd_buffer, i);
3049
3050 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3051 info->indexed,
3052 info->count,
3053 count_va,
3054 info->stride);
3055 }
3056 }
3057 } else {
3058 assert(state->pipeline->graphics.vtx_base_sgpr);
3059
3060 if (info->vertex_offset != state->last_vertex_offset ||
3061 info->first_instance != state->last_first_instance) {
3062 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3063 state->pipeline->graphics.vtx_emit_num);
3064
3065 radeon_emit(cs, info->vertex_offset);
3066 radeon_emit(cs, info->first_instance);
3067 if (state->pipeline->graphics.vtx_emit_num == 3)
3068 radeon_emit(cs, 0);
3069 state->last_first_instance = info->first_instance;
3070 state->last_vertex_offset = info->vertex_offset;
3071 }
3072
3073 if (state->last_num_instances != info->instance_count) {
3074 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3075 radeon_emit(cs, info->instance_count);
3076 state->last_num_instances = info->instance_count;
3077 }
3078
3079 if (info->indexed) {
3080 int index_size = state->index_type ? 4 : 2;
3081 uint64_t index_va;
3082
3083 index_va = state->index_va;
3084 index_va += info->first_index * index_size;
3085
3086 if (!state->subpass->view_mask) {
3087 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3088 index_va,
3089 info->count);
3090 } else {
3091 unsigned i;
3092 for_each_bit(i, state->subpass->view_mask) {
3093 radv_emit_view_index(cmd_buffer, i);
3094
3095 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3096 index_va,
3097 info->count);
3098 }
3099 }
3100 } else {
3101 if (!state->subpass->view_mask) {
3102 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3103 } else {
3104 unsigned i;
3105 for_each_bit(i, state->subpass->view_mask) {
3106 radv_emit_view_index(cmd_buffer, i);
3107
3108 radv_cs_emit_draw_packet(cmd_buffer,
3109 info->count);
3110 }
3111 }
3112 }
3113 }
3114 }
3115
3116 /*
3117 * Vega and raven have a bug which triggers if there are multiple context
3118 * register contexts active at the same time with different scissor values.
3119 *
3120 * There are two possible workarounds:
3121 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3122 * there is only ever 1 active set of scissor values at the same time.
3123 *
3124 * 2) Whenever the hardware switches contexts we have to set the scissor
3125 * registers again even if it is a noop. That way the new context gets
3126 * the correct scissor values.
3127 *
3128 * This implements option 2. radv_need_late_scissor_emission needs to
3129 * return true on affected HW if radv_emit_all_graphics_states sets
3130 * any context registers.
3131 */
3132 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3133 bool indexed_draw)
3134 {
3135 struct radv_cmd_state *state = &cmd_buffer->state;
3136
3137 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3138 return false;
3139
3140 /* Assume all state changes except these two can imply context rolls. */
3141 if (cmd_buffer->state.dirty & ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3142 RADV_CMD_DIRTY_VERTEX_BUFFER |
3143 RADV_CMD_DIRTY_PIPELINE))
3144 return true;
3145
3146 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3147 return true;
3148
3149 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3150 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3151 return true;
3152
3153 return false;
3154 }
3155
3156 static void
3157 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3158 const struct radv_draw_info *info)
3159 {
3160 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3161
3162 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3163 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3164 radv_emit_rbplus_state(cmd_buffer);
3165
3166 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3167 radv_emit_graphics_pipeline(cmd_buffer);
3168
3169 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3170 radv_emit_framebuffer_state(cmd_buffer);
3171
3172 if (info->indexed) {
3173 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3174 radv_emit_index_buffer(cmd_buffer);
3175 } else {
3176 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3177 * so the state must be re-emitted before the next indexed
3178 * draw.
3179 */
3180 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3181 cmd_buffer->state.last_index_type = -1;
3182 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3183 }
3184 }
3185
3186 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3187
3188 radv_emit_draw_registers(cmd_buffer, info->indexed,
3189 info->instance_count > 1, info->indirect,
3190 info->indirect ? 0 : info->count);
3191
3192 if (late_scissor_emission)
3193 radv_emit_scissor(cmd_buffer);
3194 }
3195
3196 static void
3197 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3198 const struct radv_draw_info *info)
3199 {
3200 bool has_prefetch =
3201 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3202 bool pipeline_is_dirty =
3203 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3204 cmd_buffer->state.pipeline &&
3205 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3206
3207 MAYBE_UNUSED unsigned cdw_max =
3208 radeon_check_space(cmd_buffer->device->ws,
3209 cmd_buffer->cs, 4096);
3210
3211 /* Use optimal packet order based on whether we need to sync the
3212 * pipeline.
3213 */
3214 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3215 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3216 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3217 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3218 /* If we have to wait for idle, set all states first, so that
3219 * all SET packets are processed in parallel with previous draw
3220 * calls. Then upload descriptors, set shader pointers, and
3221 * draw, and prefetch at the end. This ensures that the time
3222 * the CUs are idle is very short. (there are only SET_SH
3223 * packets between the wait and the draw)
3224 */
3225 radv_emit_all_graphics_states(cmd_buffer, info);
3226 si_emit_cache_flush(cmd_buffer);
3227 /* <-- CUs are idle here --> */
3228
3229 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3230
3231 radv_emit_draw_packets(cmd_buffer, info);
3232 /* <-- CUs are busy here --> */
3233
3234 /* Start prefetches after the draw has been started. Both will
3235 * run in parallel, but starting the draw first is more
3236 * important.
3237 */
3238 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3239 radv_emit_prefetch_L2(cmd_buffer,
3240 cmd_buffer->state.pipeline, false);
3241 }
3242 } else {
3243 /* If we don't wait for idle, start prefetches first, then set
3244 * states, and draw at the end.
3245 */
3246 si_emit_cache_flush(cmd_buffer);
3247
3248 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3249 /* Only prefetch the vertex shader and VBO descriptors
3250 * in order to start the draw as soon as possible.
3251 */
3252 radv_emit_prefetch_L2(cmd_buffer,
3253 cmd_buffer->state.pipeline, true);
3254 }
3255
3256 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3257
3258 radv_emit_all_graphics_states(cmd_buffer, info);
3259 radv_emit_draw_packets(cmd_buffer, info);
3260
3261 /* Prefetch the remaining shaders after the draw has been
3262 * started.
3263 */
3264 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3265 radv_emit_prefetch_L2(cmd_buffer,
3266 cmd_buffer->state.pipeline, false);
3267 }
3268 }
3269
3270 assert(cmd_buffer->cs->cdw <= cdw_max);
3271 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3272 }
3273
3274 void radv_CmdDraw(
3275 VkCommandBuffer commandBuffer,
3276 uint32_t vertexCount,
3277 uint32_t instanceCount,
3278 uint32_t firstVertex,
3279 uint32_t firstInstance)
3280 {
3281 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3282 struct radv_draw_info info = {};
3283
3284 info.count = vertexCount;
3285 info.instance_count = instanceCount;
3286 info.first_instance = firstInstance;
3287 info.vertex_offset = firstVertex;
3288
3289 radv_draw(cmd_buffer, &info);
3290 }
3291
3292 void radv_CmdDrawIndexed(
3293 VkCommandBuffer commandBuffer,
3294 uint32_t indexCount,
3295 uint32_t instanceCount,
3296 uint32_t firstIndex,
3297 int32_t vertexOffset,
3298 uint32_t firstInstance)
3299 {
3300 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3301 struct radv_draw_info info = {};
3302
3303 info.indexed = true;
3304 info.count = indexCount;
3305 info.instance_count = instanceCount;
3306 info.first_index = firstIndex;
3307 info.vertex_offset = vertexOffset;
3308 info.first_instance = firstInstance;
3309
3310 radv_draw(cmd_buffer, &info);
3311 }
3312
3313 void radv_CmdDrawIndirect(
3314 VkCommandBuffer commandBuffer,
3315 VkBuffer _buffer,
3316 VkDeviceSize offset,
3317 uint32_t drawCount,
3318 uint32_t stride)
3319 {
3320 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3321 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3322 struct radv_draw_info info = {};
3323
3324 info.count = drawCount;
3325 info.indirect = buffer;
3326 info.indirect_offset = offset;
3327 info.stride = stride;
3328
3329 radv_draw(cmd_buffer, &info);
3330 }
3331
3332 void radv_CmdDrawIndexedIndirect(
3333 VkCommandBuffer commandBuffer,
3334 VkBuffer _buffer,
3335 VkDeviceSize offset,
3336 uint32_t drawCount,
3337 uint32_t stride)
3338 {
3339 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3340 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3341 struct radv_draw_info info = {};
3342
3343 info.indexed = true;
3344 info.count = drawCount;
3345 info.indirect = buffer;
3346 info.indirect_offset = offset;
3347 info.stride = stride;
3348
3349 radv_draw(cmd_buffer, &info);
3350 }
3351
3352 void radv_CmdDrawIndirectCountAMD(
3353 VkCommandBuffer commandBuffer,
3354 VkBuffer _buffer,
3355 VkDeviceSize offset,
3356 VkBuffer _countBuffer,
3357 VkDeviceSize countBufferOffset,
3358 uint32_t maxDrawCount,
3359 uint32_t stride)
3360 {
3361 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3362 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3363 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3364 struct radv_draw_info info = {};
3365
3366 info.count = maxDrawCount;
3367 info.indirect = buffer;
3368 info.indirect_offset = offset;
3369 info.count_buffer = count_buffer;
3370 info.count_buffer_offset = countBufferOffset;
3371 info.stride = stride;
3372
3373 radv_draw(cmd_buffer, &info);
3374 }
3375
3376 void radv_CmdDrawIndexedIndirectCountAMD(
3377 VkCommandBuffer commandBuffer,
3378 VkBuffer _buffer,
3379 VkDeviceSize offset,
3380 VkBuffer _countBuffer,
3381 VkDeviceSize countBufferOffset,
3382 uint32_t maxDrawCount,
3383 uint32_t stride)
3384 {
3385 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3386 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3387 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3388 struct radv_draw_info info = {};
3389
3390 info.indexed = true;
3391 info.count = maxDrawCount;
3392 info.indirect = buffer;
3393 info.indirect_offset = offset;
3394 info.count_buffer = count_buffer;
3395 info.count_buffer_offset = countBufferOffset;
3396 info.stride = stride;
3397
3398 radv_draw(cmd_buffer, &info);
3399 }
3400
3401 struct radv_dispatch_info {
3402 /**
3403 * Determine the layout of the grid (in block units) to be used.
3404 */
3405 uint32_t blocks[3];
3406
3407 /**
3408 * A starting offset for the grid. If unaligned is set, the offset
3409 * must still be aligned.
3410 */
3411 uint32_t offsets[3];
3412 /**
3413 * Whether it's an unaligned compute dispatch.
3414 */
3415 bool unaligned;
3416
3417 /**
3418 * Indirect compute parameters resource.
3419 */
3420 struct radv_buffer *indirect;
3421 uint64_t indirect_offset;
3422 };
3423
3424 static void
3425 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3426 const struct radv_dispatch_info *info)
3427 {
3428 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3429 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3430 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3431 struct radeon_winsys *ws = cmd_buffer->device->ws;
3432 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3433 struct radv_userdata_info *loc;
3434
3435 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3436 AC_UD_CS_GRID_SIZE);
3437
3438 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3439
3440 if (info->indirect) {
3441 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3442
3443 va += info->indirect->offset + info->indirect_offset;
3444
3445 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3446
3447 if (loc->sgpr_idx != -1) {
3448 for (unsigned i = 0; i < 3; ++i) {
3449 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3450 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3451 COPY_DATA_DST_SEL(COPY_DATA_REG));
3452 radeon_emit(cs, (va + 4 * i));
3453 radeon_emit(cs, (va + 4 * i) >> 32);
3454 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3455 + loc->sgpr_idx * 4) >> 2) + i);
3456 radeon_emit(cs, 0);
3457 }
3458 }
3459
3460 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3461 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3462 PKT3_SHADER_TYPE_S(1));
3463 radeon_emit(cs, va);
3464 radeon_emit(cs, va >> 32);
3465 radeon_emit(cs, dispatch_initiator);
3466 } else {
3467 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3468 PKT3_SHADER_TYPE_S(1));
3469 radeon_emit(cs, 1);
3470 radeon_emit(cs, va);
3471 radeon_emit(cs, va >> 32);
3472
3473 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3474 PKT3_SHADER_TYPE_S(1));
3475 radeon_emit(cs, 0);
3476 radeon_emit(cs, dispatch_initiator);
3477 }
3478 } else {
3479 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3480 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3481
3482 if (info->unaligned) {
3483 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3484 unsigned remainder[3];
3485
3486 /* If aligned, these should be an entire block size,
3487 * not 0.
3488 */
3489 remainder[0] = blocks[0] + cs_block_size[0] -
3490 align_u32_npot(blocks[0], cs_block_size[0]);
3491 remainder[1] = blocks[1] + cs_block_size[1] -
3492 align_u32_npot(blocks[1], cs_block_size[1]);
3493 remainder[2] = blocks[2] + cs_block_size[2] -
3494 align_u32_npot(blocks[2], cs_block_size[2]);
3495
3496 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3497 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3498 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3499
3500 for(unsigned i = 0; i < 3; ++i) {
3501 assert(offsets[i] % cs_block_size[i] == 0);
3502 offsets[i] /= cs_block_size[i];
3503 }
3504
3505 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3506 radeon_emit(cs,
3507 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3508 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3509 radeon_emit(cs,
3510 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3511 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3512 radeon_emit(cs,
3513 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3514 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3515
3516 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3517 }
3518
3519 if (loc->sgpr_idx != -1) {
3520 assert(!loc->indirect);
3521 assert(loc->num_sgprs == 3);
3522
3523 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3524 loc->sgpr_idx * 4, 3);
3525 radeon_emit(cs, blocks[0]);
3526 radeon_emit(cs, blocks[1]);
3527 radeon_emit(cs, blocks[2]);
3528 }
3529
3530 if (offsets[0] || offsets[1] || offsets[2]) {
3531 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3532 radeon_emit(cs, offsets[0]);
3533 radeon_emit(cs, offsets[1]);
3534 radeon_emit(cs, offsets[2]);
3535
3536 /* The blocks in the packet are not counts but end values. */
3537 for (unsigned i = 0; i < 3; ++i)
3538 blocks[i] += offsets[i];
3539 } else {
3540 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3541 }
3542
3543 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3544 PKT3_SHADER_TYPE_S(1));
3545 radeon_emit(cs, blocks[0]);
3546 radeon_emit(cs, blocks[1]);
3547 radeon_emit(cs, blocks[2]);
3548 radeon_emit(cs, dispatch_initiator);
3549 }
3550
3551 assert(cmd_buffer->cs->cdw <= cdw_max);
3552 }
3553
3554 static void
3555 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3556 {
3557 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3558 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3559 }
3560
3561 static void
3562 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3563 const struct radv_dispatch_info *info)
3564 {
3565 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3566 bool has_prefetch =
3567 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3568 bool pipeline_is_dirty = pipeline &&
3569 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3570
3571 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3572 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3573 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3574 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3575 /* If we have to wait for idle, set all states first, so that
3576 * all SET packets are processed in parallel with previous draw
3577 * calls. Then upload descriptors, set shader pointers, and
3578 * dispatch, and prefetch at the end. This ensures that the
3579 * time the CUs are idle is very short. (there are only SET_SH
3580 * packets between the wait and the draw)
3581 */
3582 radv_emit_compute_pipeline(cmd_buffer);
3583 si_emit_cache_flush(cmd_buffer);
3584 /* <-- CUs are idle here --> */
3585
3586 radv_upload_compute_shader_descriptors(cmd_buffer);
3587
3588 radv_emit_dispatch_packets(cmd_buffer, info);
3589 /* <-- CUs are busy here --> */
3590
3591 /* Start prefetches after the dispatch has been started. Both
3592 * will run in parallel, but starting the dispatch first is
3593 * more important.
3594 */
3595 if (has_prefetch && pipeline_is_dirty) {
3596 radv_emit_shader_prefetch(cmd_buffer,
3597 pipeline->shaders[MESA_SHADER_COMPUTE]);
3598 }
3599 } else {
3600 /* If we don't wait for idle, start prefetches first, then set
3601 * states, and dispatch at the end.
3602 */
3603 si_emit_cache_flush(cmd_buffer);
3604
3605 if (has_prefetch && pipeline_is_dirty) {
3606 radv_emit_shader_prefetch(cmd_buffer,
3607 pipeline->shaders[MESA_SHADER_COMPUTE]);
3608 }
3609
3610 radv_upload_compute_shader_descriptors(cmd_buffer);
3611
3612 radv_emit_compute_pipeline(cmd_buffer);
3613 radv_emit_dispatch_packets(cmd_buffer, info);
3614 }
3615
3616 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3617 }
3618
3619 void radv_CmdDispatchBase(
3620 VkCommandBuffer commandBuffer,
3621 uint32_t base_x,
3622 uint32_t base_y,
3623 uint32_t base_z,
3624 uint32_t x,
3625 uint32_t y,
3626 uint32_t z)
3627 {
3628 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3629 struct radv_dispatch_info info = {};
3630
3631 info.blocks[0] = x;
3632 info.blocks[1] = y;
3633 info.blocks[2] = z;
3634
3635 info.offsets[0] = base_x;
3636 info.offsets[1] = base_y;
3637 info.offsets[2] = base_z;
3638 radv_dispatch(cmd_buffer, &info);
3639 }
3640
3641 void radv_CmdDispatch(
3642 VkCommandBuffer commandBuffer,
3643 uint32_t x,
3644 uint32_t y,
3645 uint32_t z)
3646 {
3647 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3648 }
3649
3650 void radv_CmdDispatchIndirect(
3651 VkCommandBuffer commandBuffer,
3652 VkBuffer _buffer,
3653 VkDeviceSize offset)
3654 {
3655 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3656 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3657 struct radv_dispatch_info info = {};
3658
3659 info.indirect = buffer;
3660 info.indirect_offset = offset;
3661
3662 radv_dispatch(cmd_buffer, &info);
3663 }
3664
3665 void radv_unaligned_dispatch(
3666 struct radv_cmd_buffer *cmd_buffer,
3667 uint32_t x,
3668 uint32_t y,
3669 uint32_t z)
3670 {
3671 struct radv_dispatch_info info = {};
3672
3673 info.blocks[0] = x;
3674 info.blocks[1] = y;
3675 info.blocks[2] = z;
3676 info.unaligned = 1;
3677
3678 radv_dispatch(cmd_buffer, &info);
3679 }
3680
3681 void radv_CmdEndRenderPass(
3682 VkCommandBuffer commandBuffer)
3683 {
3684 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3685
3686 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3687
3688 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3689
3690 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3691 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3692 radv_handle_subpass_image_transition(cmd_buffer,
3693 (VkAttachmentReference){i, layout});
3694 }
3695
3696 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3697
3698 cmd_buffer->state.pass = NULL;
3699 cmd_buffer->state.subpass = NULL;
3700 cmd_buffer->state.attachments = NULL;
3701 cmd_buffer->state.framebuffer = NULL;
3702 }
3703
3704 /*
3705 * For HTILE we have the following interesting clear words:
3706 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3707 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3708 * 0xfffffff0: Clear depth to 1.0
3709 * 0x00000000: Clear depth to 0.0
3710 */
3711 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3712 struct radv_image *image,
3713 const VkImageSubresourceRange *range,
3714 uint32_t clear_word)
3715 {
3716 assert(range->baseMipLevel == 0);
3717 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3718 unsigned layer_count = radv_get_layerCount(image, range);
3719 uint64_t size = image->surface.htile_slice_size * layer_count;
3720 uint64_t offset = image->offset + image->htile_offset +
3721 image->surface.htile_slice_size * range->baseArrayLayer;
3722 struct radv_cmd_state *state = &cmd_buffer->state;
3723
3724 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3725 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3726
3727 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3728 size, clear_word);
3729
3730 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3731 }
3732
3733 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3734 struct radv_image *image,
3735 VkImageLayout src_layout,
3736 VkImageLayout dst_layout,
3737 unsigned src_queue_mask,
3738 unsigned dst_queue_mask,
3739 const VkImageSubresourceRange *range,
3740 VkImageAspectFlags pending_clears)
3741 {
3742 if (!radv_image_has_htile(image))
3743 return;
3744
3745 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3746 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3747 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3748 cmd_buffer->state.render_area.extent.width == image->info.width &&
3749 cmd_buffer->state.render_area.extent.height == image->info.height) {
3750 /* The clear will initialize htile. */
3751 return;
3752 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3753 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3754 /* TODO: merge with the clear if applicable */
3755 radv_initialize_htile(cmd_buffer, image, range, 0);
3756 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3757 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3758 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3759 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3760 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3761 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3762 VkImageSubresourceRange local_range = *range;
3763 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3764 local_range.baseMipLevel = 0;
3765 local_range.levelCount = 1;
3766
3767 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3768 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3769
3770 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3771
3772 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3773 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3774 }
3775 }
3776
3777 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3778 struct radv_image *image, uint32_t value)
3779 {
3780 struct radv_cmd_state *state = &cmd_buffer->state;
3781
3782 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3783 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3784
3785 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
3786
3787 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3788 }
3789
3790 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3791 struct radv_image *image, uint32_t value)
3792 {
3793 struct radv_cmd_state *state = &cmd_buffer->state;
3794
3795 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3796 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3797
3798 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
3799
3800 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3801 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3802 }
3803
3804 /**
3805 * Initialize DCC/FMASK/CMASK metadata for a color image.
3806 */
3807 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
3808 struct radv_image *image,
3809 VkImageLayout src_layout,
3810 VkImageLayout dst_layout,
3811 unsigned src_queue_mask,
3812 unsigned dst_queue_mask)
3813 {
3814 if (radv_image_has_cmask(image)) {
3815 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
3816
3817 /* TODO: clarify this. */
3818 if (radv_image_has_fmask(image)) {
3819 value = 0xccccccccu;
3820 }
3821
3822 radv_initialise_cmask(cmd_buffer, image, value);
3823 }
3824
3825 if (radv_image_has_dcc(image)) {
3826 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
3827
3828 if (radv_layout_dcc_compressed(image, dst_layout,
3829 dst_queue_mask)) {
3830 value = 0x20202020u;
3831 }
3832
3833 radv_initialize_dcc(cmd_buffer, image, value);
3834 }
3835 }
3836
3837 /**
3838 * Handle color image transitions for DCC/FMASK/CMASK.
3839 */
3840 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
3841 struct radv_image *image,
3842 VkImageLayout src_layout,
3843 VkImageLayout dst_layout,
3844 unsigned src_queue_mask,
3845 unsigned dst_queue_mask,
3846 const VkImageSubresourceRange *range)
3847 {
3848 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3849 radv_init_color_image_metadata(cmd_buffer, image,
3850 src_layout, dst_layout,
3851 src_queue_mask, dst_queue_mask);
3852 return;
3853 }
3854
3855 if (radv_image_has_dcc(image)) {
3856 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
3857 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
3858 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3859 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3860 radv_decompress_dcc(cmd_buffer, image, range);
3861 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3862 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3863 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3864 }
3865 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
3866 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3867 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3868 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3869 }
3870 }
3871 }
3872
3873 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3874 struct radv_image *image,
3875 VkImageLayout src_layout,
3876 VkImageLayout dst_layout,
3877 uint32_t src_family,
3878 uint32_t dst_family,
3879 const VkImageSubresourceRange *range,
3880 VkImageAspectFlags pending_clears)
3881 {
3882 if (image->exclusive && src_family != dst_family) {
3883 /* This is an acquire or a release operation and there will be
3884 * a corresponding release/acquire. Do the transition in the
3885 * most flexible queue. */
3886
3887 assert(src_family == cmd_buffer->queue_family_index ||
3888 dst_family == cmd_buffer->queue_family_index);
3889
3890 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3891 return;
3892
3893 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3894 (src_family == RADV_QUEUE_GENERAL ||
3895 dst_family == RADV_QUEUE_GENERAL))
3896 return;
3897 }
3898
3899 unsigned src_queue_mask =
3900 radv_image_queue_family_mask(image, src_family,
3901 cmd_buffer->queue_family_index);
3902 unsigned dst_queue_mask =
3903 radv_image_queue_family_mask(image, dst_family,
3904 cmd_buffer->queue_family_index);
3905
3906 if (vk_format_is_depth(image->vk_format)) {
3907 radv_handle_depth_image_transition(cmd_buffer, image,
3908 src_layout, dst_layout,
3909 src_queue_mask, dst_queue_mask,
3910 range, pending_clears);
3911 } else {
3912 radv_handle_color_image_transition(cmd_buffer, image,
3913 src_layout, dst_layout,
3914 src_queue_mask, dst_queue_mask,
3915 range);
3916 }
3917 }
3918
3919 void radv_CmdPipelineBarrier(
3920 VkCommandBuffer commandBuffer,
3921 VkPipelineStageFlags srcStageMask,
3922 VkPipelineStageFlags destStageMask,
3923 VkBool32 byRegion,
3924 uint32_t memoryBarrierCount,
3925 const VkMemoryBarrier* pMemoryBarriers,
3926 uint32_t bufferMemoryBarrierCount,
3927 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3928 uint32_t imageMemoryBarrierCount,
3929 const VkImageMemoryBarrier* pImageMemoryBarriers)
3930 {
3931 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3932 enum radv_cmd_flush_bits src_flush_bits = 0;
3933 enum radv_cmd_flush_bits dst_flush_bits = 0;
3934
3935 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3936 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3937 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3938 NULL);
3939 }
3940
3941 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3942 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3943 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3944 NULL);
3945 }
3946
3947 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3948 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3949 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3950 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3951 image);
3952 }
3953
3954 radv_stage_flush(cmd_buffer, srcStageMask);
3955 cmd_buffer->state.flush_bits |= src_flush_bits;
3956
3957 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3958 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3959 radv_handle_image_transition(cmd_buffer, image,
3960 pImageMemoryBarriers[i].oldLayout,
3961 pImageMemoryBarriers[i].newLayout,
3962 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3963 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3964 &pImageMemoryBarriers[i].subresourceRange,
3965 0);
3966 }
3967
3968 cmd_buffer->state.flush_bits |= dst_flush_bits;
3969 }
3970
3971
3972 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3973 struct radv_event *event,
3974 VkPipelineStageFlags stageMask,
3975 unsigned value)
3976 {
3977 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3978 uint64_t va = radv_buffer_get_va(event->bo);
3979
3980 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3981
3982 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3983
3984 /* TODO: this is overkill. Probably should figure something out from
3985 * the stage mask. */
3986
3987 si_cs_emit_write_event_eop(cs,
3988 cmd_buffer->state.predicating,
3989 cmd_buffer->device->physical_device->rad_info.chip_class,
3990 radv_cmd_buffer_uses_mec(cmd_buffer),
3991 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3992 1, va, 2, value);
3993
3994 assert(cmd_buffer->cs->cdw <= cdw_max);
3995 }
3996
3997 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3998 VkEvent _event,
3999 VkPipelineStageFlags stageMask)
4000 {
4001 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4002 RADV_FROM_HANDLE(radv_event, event, _event);
4003
4004 write_event(cmd_buffer, event, stageMask, 1);
4005 }
4006
4007 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4008 VkEvent _event,
4009 VkPipelineStageFlags stageMask)
4010 {
4011 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4012 RADV_FROM_HANDLE(radv_event, event, _event);
4013
4014 write_event(cmd_buffer, event, stageMask, 0);
4015 }
4016
4017 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4018 uint32_t eventCount,
4019 const VkEvent* pEvents,
4020 VkPipelineStageFlags srcStageMask,
4021 VkPipelineStageFlags dstStageMask,
4022 uint32_t memoryBarrierCount,
4023 const VkMemoryBarrier* pMemoryBarriers,
4024 uint32_t bufferMemoryBarrierCount,
4025 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4026 uint32_t imageMemoryBarrierCount,
4027 const VkImageMemoryBarrier* pImageMemoryBarriers)
4028 {
4029 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4030 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4031
4032 for (unsigned i = 0; i < eventCount; ++i) {
4033 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4034 uint64_t va = radv_buffer_get_va(event->bo);
4035
4036 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4037
4038 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4039
4040 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4041 assert(cmd_buffer->cs->cdw <= cdw_max);
4042 }
4043
4044
4045 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4046 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4047
4048 radv_handle_image_transition(cmd_buffer, image,
4049 pImageMemoryBarriers[i].oldLayout,
4050 pImageMemoryBarriers[i].newLayout,
4051 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4052 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4053 &pImageMemoryBarriers[i].subresourceRange,
4054 0);
4055 }
4056
4057 /* TODO: figure out how to do memory barriers without waiting */
4058 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4059 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4060 RADV_CMD_FLAG_INV_VMEM_L1 |
4061 RADV_CMD_FLAG_INV_SMEM_L1;
4062 }
4063
4064
4065 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4066 uint32_t deviceMask)
4067 {
4068 /* No-op */
4069 }