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radv: add support for writing layer/viewport index (v2)
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 int src_family,
42 int dst_family,
43 VkImageSubresourceRange range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static bool
191 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
192 uint64_t min_needed)
193 {
194 uint64_t new_size;
195 struct radeon_winsys_bo *bo;
196 struct radv_cmd_buffer_upload *upload;
197 struct radv_device *device = cmd_buffer->device;
198
199 new_size = MAX2(min_needed, 16 * 1024);
200 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
201
202 bo = device->ws->buffer_create(device->ws,
203 new_size, 4096,
204 RADEON_DOMAIN_GTT,
205 RADEON_FLAG_CPU_ACCESS);
206
207 if (!bo) {
208 cmd_buffer->record_fail = true;
209 return false;
210 }
211
212 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
213 if (cmd_buffer->upload.upload_bo) {
214 upload = malloc(sizeof(*upload));
215
216 if (!upload) {
217 cmd_buffer->record_fail = true;
218 device->ws->buffer_destroy(bo);
219 return false;
220 }
221
222 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
223 list_add(&upload->list, &cmd_buffer->upload.list);
224 }
225
226 cmd_buffer->upload.upload_bo = bo;
227 cmd_buffer->upload.size = new_size;
228 cmd_buffer->upload.offset = 0;
229 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
230
231 if (!cmd_buffer->upload.map) {
232 cmd_buffer->record_fail = true;
233 return false;
234 }
235
236 return true;
237 }
238
239 bool
240 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
241 unsigned size,
242 unsigned alignment,
243 unsigned *out_offset,
244 void **ptr)
245 {
246 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
247 if (offset + size > cmd_buffer->upload.size) {
248 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
249 return false;
250 offset = 0;
251 }
252
253 *out_offset = offset;
254 *ptr = cmd_buffer->upload.map + offset;
255
256 cmd_buffer->upload.offset = offset + size;
257 return true;
258 }
259
260 bool
261 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
262 unsigned size, unsigned alignment,
263 const void *data, unsigned *out_offset)
264 {
265 uint8_t *ptr;
266
267 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
268 out_offset, (void **)&ptr))
269 return false;
270
271 if (ptr)
272 memcpy(ptr, data, size);
273
274 return true;
275 }
276
277 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
278 {
279 struct radv_device *device = cmd_buffer->device;
280 struct radeon_winsys_cs *cs = cmd_buffer->cs;
281 uint64_t va;
282
283 if (!device->trace_bo)
284 return;
285
286 va = device->ws->buffer_get_va(device->trace_bo);
287
288 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
289
290 ++cmd_buffer->state.trace_id;
291 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
292 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
293 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
294 S_370_WR_CONFIRM(1) |
295 S_370_ENGINE_SEL(V_370_ME));
296 radeon_emit(cs, va);
297 radeon_emit(cs, va >> 32);
298 radeon_emit(cs, cmd_buffer->state.trace_id);
299 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
300 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
301 }
302
303 static void
304 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
305 struct radv_pipeline *pipeline)
306 {
307 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
308 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
309 8);
310 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
311 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
312 }
313
314 static void
315 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
316 struct radv_pipeline *pipeline)
317 {
318 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
319 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
320 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
321
322 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
323 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
324 }
325
326 /* 12.4 fixed-point */
327 static unsigned radv_pack_float_12p4(float x)
328 {
329 return x <= 0 ? 0 :
330 x >= 4096 ? 0xffff : x * 16;
331 }
332
333 static uint32_t
334 shader_stage_to_user_data_0(gl_shader_stage stage)
335 {
336 switch (stage) {
337 case MESA_SHADER_FRAGMENT:
338 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
339 case MESA_SHADER_VERTEX:
340 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
341 case MESA_SHADER_COMPUTE:
342 return R_00B900_COMPUTE_USER_DATA_0;
343 default:
344 unreachable("unknown shader");
345 }
346 }
347
348 static struct ac_userdata_info *
349 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
350 gl_shader_stage stage,
351 int idx)
352 {
353 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
354 }
355
356 static void
357 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
358 struct radv_pipeline *pipeline,
359 gl_shader_stage stage,
360 int idx, uint64_t va)
361 {
362 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
363 uint32_t base_reg = shader_stage_to_user_data_0(stage);
364 if (loc->sgpr_idx == -1)
365 return;
366 assert(loc->num_sgprs == 2);
367 assert(!loc->indirect);
368 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
369 radeon_emit(cmd_buffer->cs, va);
370 radeon_emit(cmd_buffer->cs, va >> 32);
371 }
372
373 static void
374 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
375 struct radv_pipeline *pipeline)
376 {
377 int num_samples = pipeline->graphics.ms.num_samples;
378 struct radv_multisample_state *ms = &pipeline->graphics.ms;
379 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
380
381 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
382 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
383 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
384
385 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
386 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
387
388 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
389 return;
390
391 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
392 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
393 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
394
395 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
396
397 uint32_t samples_offset;
398 void *samples_ptr;
399 void *src;
400 radv_cmd_buffer_upload_alloc(cmd_buffer, num_samples * 4 * 2, 256, &samples_offset,
401 &samples_ptr);
402 switch (num_samples) {
403 case 1:
404 src = cmd_buffer->device->sample_locations_1x;
405 break;
406 case 2:
407 src = cmd_buffer->device->sample_locations_2x;
408 break;
409 case 4:
410 src = cmd_buffer->device->sample_locations_4x;
411 break;
412 case 8:
413 src = cmd_buffer->device->sample_locations_8x;
414 break;
415 case 16:
416 src = cmd_buffer->device->sample_locations_16x;
417 break;
418 }
419 memcpy(samples_ptr, src, num_samples * 4 * 2);
420
421 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
422 va += samples_offset;
423
424 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
425 AC_UD_PS_SAMPLE_POS, va);
426 }
427
428 static void
429 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
430 struct radv_pipeline *pipeline)
431 {
432 struct radv_raster_state *raster = &pipeline->graphics.raster;
433
434 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
435 raster->pa_cl_clip_cntl);
436
437 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
438 raster->spi_interp_control);
439
440 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
441 radeon_emit(cmd_buffer->cs, 0);
442 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
443 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
444
445 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
446 raster->pa_su_vtx_cntl);
447
448 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
449 raster->pa_su_sc_mode_cntl);
450 }
451
452 static void
453 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
454 struct radv_pipeline *pipeline)
455 {
456 struct radeon_winsys *ws = cmd_buffer->device->ws;
457 struct radv_shader_variant *vs;
458 uint64_t va;
459 unsigned export_count;
460 unsigned clip_dist_mask, cull_dist_mask, total_mask;
461
462 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
463
464 vs = pipeline->shaders[MESA_SHADER_VERTEX];
465 va = ws->buffer_get_va(vs->bo);
466 ws->cs_add_buffer(cmd_buffer->cs, vs->bo, 8);
467
468 clip_dist_mask = vs->info.vs.clip_dist_mask;
469 cull_dist_mask = vs->info.vs.cull_dist_mask;
470 total_mask = clip_dist_mask | cull_dist_mask;
471 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, 0);
472 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
473
474 export_count = MAX2(1, vs->info.vs.param_exports);
475 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
476 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
477 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
478 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
479 S_02870C_POS1_EXPORT_FORMAT(vs->info.vs.pos_exports > 1 ?
480 V_02870C_SPI_SHADER_4COMP :
481 V_02870C_SPI_SHADER_NONE) |
482 S_02870C_POS2_EXPORT_FORMAT(vs->info.vs.pos_exports > 2 ?
483 V_02870C_SPI_SHADER_4COMP :
484 V_02870C_SPI_SHADER_NONE) |
485 S_02870C_POS3_EXPORT_FORMAT(vs->info.vs.pos_exports > 3 ?
486 V_02870C_SPI_SHADER_4COMP :
487 V_02870C_SPI_SHADER_NONE));
488
489 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
490 radeon_emit(cmd_buffer->cs, va >> 8);
491 radeon_emit(cmd_buffer->cs, va >> 40);
492 radeon_emit(cmd_buffer->cs, vs->rsrc1);
493 radeon_emit(cmd_buffer->cs, vs->rsrc2);
494
495 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
496 S_028818_VTX_W0_FMT(1) |
497 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
498 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
499 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
500
501 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
502 S_02881C_USE_VTX_POINT_SIZE(vs->info.vs.writes_pointsize) |
503 S_02881C_USE_VTX_RENDER_TARGET_INDX(vs->info.vs.writes_layer) |
504 S_02881C_USE_VTX_VIEWPORT_INDX(vs->info.vs.writes_viewport_index) |
505 S_02881C_VS_OUT_MISC_VEC_ENA(vs->info.vs.writes_pointsize ||
506 vs->info.vs.writes_layer ||
507 vs->info.vs.writes_viewport_index) |
508 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
509 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
510 pipeline->graphics.raster.pa_cl_vs_out_cntl |
511 cull_dist_mask << 8 |
512 clip_dist_mask);
513
514 }
515
516
517
518 static void
519 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
520 struct radv_pipeline *pipeline)
521 {
522 struct radeon_winsys *ws = cmd_buffer->device->ws;
523 struct radv_shader_variant *ps, *vs;
524 uint64_t va;
525 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
526 struct radv_blend_state *blend = &pipeline->graphics.blend;
527 unsigned ps_offset = 0;
528 unsigned z_order;
529 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
530
531 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
532 vs = pipeline->shaders[MESA_SHADER_VERTEX];
533 va = ws->buffer_get_va(ps->bo);
534 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
535
536 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
537 radeon_emit(cmd_buffer->cs, va >> 8);
538 radeon_emit(cmd_buffer->cs, va >> 40);
539 radeon_emit(cmd_buffer->cs, ps->rsrc1);
540 radeon_emit(cmd_buffer->cs, ps->rsrc2);
541
542 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
543 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
544 else
545 z_order = V_02880C_LATE_Z;
546
547
548 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
549 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
550 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
551 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
552 S_02880C_Z_ORDER(z_order) |
553 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
554 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
555 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory));
556
557 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
558 ps->config.spi_ps_input_ena);
559
560 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
561 ps->config.spi_ps_input_addr);
562
563 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(0);
564 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
565 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
566
567 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
568
569 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
570 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
571 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
572 V_028710_SPI_SHADER_ZERO);
573
574 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
575
576 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
577 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
578
579 if (ps->info.fs.has_pcoord) {
580 unsigned val;
581 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
582 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
583 ps_offset = 1;
584 }
585
586 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
587 unsigned vs_offset, flat_shade;
588 unsigned val;
589
590 if (!(ps->info.fs.input_mask & (1u << i)))
591 continue;
592
593
594 if (!(vs->info.vs.export_mask & (1u << i))) {
595 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset,
596 S_028644_OFFSET(0x20));
597 ++ps_offset;
598 continue;
599 }
600
601 vs_offset = util_bitcount(vs->info.vs.export_mask & ((1u << i) - 1));
602 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
603
604 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
605 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
606 ++ps_offset;
607 }
608 }
609
610 static void
611 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
612 struct radv_pipeline *pipeline)
613 {
614 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
615 return;
616
617 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
618 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
619 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
620 radv_update_multisample_state(cmd_buffer, pipeline);
621 radv_emit_vertex_shader(cmd_buffer, pipeline);
622 radv_emit_fragment_shader(cmd_buffer, pipeline);
623
624 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
625 pipeline->graphics.prim_restart_enable);
626
627 cmd_buffer->state.emitted_pipeline = pipeline;
628 }
629
630 static void
631 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
632 {
633 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
634 cmd_buffer->state.dynamic.viewport.viewports);
635 }
636
637 static void
638 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
639 {
640 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
641 si_write_scissors(cmd_buffer->cs, 0, count,
642 cmd_buffer->state.dynamic.scissor.scissors);
643 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
644 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
645 }
646
647 static void
648 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
649 int index,
650 struct radv_color_buffer_info *cb)
651 {
652 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
653 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
654 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
655 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
656 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
657 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
658 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
659 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
660 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
661 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
662 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
663 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
664 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
665
666 if (is_vi) { /* DCC BASE */
667 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
668 }
669 }
670
671 static void
672 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
673 struct radv_ds_buffer_info *ds,
674 struct radv_image *image,
675 VkImageLayout layout)
676 {
677 uint32_t db_z_info = ds->db_z_info;
678
679 if (!radv_layout_has_htile(image, layout))
680 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
681
682 if (!radv_layout_can_expclear(image, layout))
683 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
684
685 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
686 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
687
688 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
689 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
690 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
691 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
692 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
693 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
694 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
695 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
696 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
697 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
698
699 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
700 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
701 ds->pa_su_poly_offset_db_fmt_cntl);
702 }
703
704 /*
705 * To hw resolve multisample images both src and dst need to have the same
706 * micro tiling mode. However we don't always know in advance when creating
707 * the images. This function gets called if we have a resolve attachment,
708 * and tests if the attachment image has the same tiling mode, then it
709 * checks if the generated framebuffer data has the same tiling mode, and
710 * updates it if not.
711 */
712 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
713 struct radv_attachment_info *att,
714 uint32_t micro_tile_mode)
715 {
716 struct radv_image *image = att->attachment->image;
717 uint32_t tile_mode_index;
718 if (image->surface.nsamples <= 1)
719 return;
720
721 if (image->surface.micro_tile_mode != micro_tile_mode) {
722 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
723 }
724
725 if (att->cb.micro_tile_mode != micro_tile_mode) {
726 tile_mode_index = image->surface.tiling_index[0];
727
728 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
729 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
730 att->cb.micro_tile_mode = micro_tile_mode;
731 }
732 }
733
734 void
735 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
736 struct radv_image *image,
737 VkClearDepthStencilValue ds_clear_value,
738 VkImageAspectFlags aspects)
739 {
740 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
741 va += image->offset + image->clear_value_offset;
742 unsigned reg_offset = 0, reg_count = 0;
743
744 if (!image->htile.size || !aspects)
745 return;
746
747 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
748 ++reg_count;
749 } else {
750 ++reg_offset;
751 va += 4;
752 }
753 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
754 ++reg_count;
755
756 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
757
758 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
759 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
760 S_370_WR_CONFIRM(1) |
761 S_370_ENGINE_SEL(V_370_PFP));
762 radeon_emit(cmd_buffer->cs, va);
763 radeon_emit(cmd_buffer->cs, va >> 32);
764 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
765 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
766 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
767 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
768
769 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
770 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
771 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
772 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
773 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
774 }
775
776 static void
777 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
778 struct radv_image *image)
779 {
780 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
781 va += image->offset + image->clear_value_offset;
782
783 if (!image->htile.size)
784 return;
785
786 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
787
788 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
789 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
790 COPY_DATA_DST_SEL(COPY_DATA_REG) |
791 COPY_DATA_COUNT_SEL);
792 radeon_emit(cmd_buffer->cs, va);
793 radeon_emit(cmd_buffer->cs, va >> 32);
794 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
795 radeon_emit(cmd_buffer->cs, 0);
796
797 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
798 radeon_emit(cmd_buffer->cs, 0);
799 }
800
801 void
802 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
803 struct radv_image *image,
804 int idx,
805 uint32_t color_values[2])
806 {
807 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
808 va += image->offset + image->clear_value_offset;
809
810 if (!image->cmask.size && !image->surface.dcc_size)
811 return;
812
813 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
814
815 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
816 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
817 S_370_WR_CONFIRM(1) |
818 S_370_ENGINE_SEL(V_370_PFP));
819 radeon_emit(cmd_buffer->cs, va);
820 radeon_emit(cmd_buffer->cs, va >> 32);
821 radeon_emit(cmd_buffer->cs, color_values[0]);
822 radeon_emit(cmd_buffer->cs, color_values[1]);
823
824 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
825 radeon_emit(cmd_buffer->cs, color_values[0]);
826 radeon_emit(cmd_buffer->cs, color_values[1]);
827 }
828
829 static void
830 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
831 struct radv_image *image,
832 int idx)
833 {
834 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
835 va += image->offset + image->clear_value_offset;
836
837 if (!image->cmask.size && !image->surface.dcc_size)
838 return;
839
840 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
841 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
842
843 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
844 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
845 COPY_DATA_DST_SEL(COPY_DATA_REG) |
846 COPY_DATA_COUNT_SEL);
847 radeon_emit(cmd_buffer->cs, va);
848 radeon_emit(cmd_buffer->cs, va >> 32);
849 radeon_emit(cmd_buffer->cs, reg >> 2);
850 radeon_emit(cmd_buffer->cs, 0);
851
852 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
853 radeon_emit(cmd_buffer->cs, 0);
854 }
855
856 void
857 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
858 {
859 int i;
860 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
861 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
862 int dst_resolve_micro_tile_mode = -1;
863
864 if (subpass->has_resolve) {
865 uint32_t a = subpass->resolve_attachments[0].attachment;
866 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
867 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
868 }
869 for (i = 0; i < subpass->color_count; ++i) {
870 int idx = subpass->color_attachments[i].attachment;
871 struct radv_attachment_info *att = &framebuffer->attachments[idx];
872
873 if (dst_resolve_micro_tile_mode != -1) {
874 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
875 att, dst_resolve_micro_tile_mode);
876 }
877 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
878
879 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
880 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
881
882 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
883 }
884
885 for (i = subpass->color_count; i < 8; i++)
886 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
887 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
888
889 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
890 int idx = subpass->depth_stencil_attachment.attachment;
891 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
892 struct radv_attachment_info *att = &framebuffer->attachments[idx];
893 struct radv_image *image = att->attachment->image;
894 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
895
896 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
897
898 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
899 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
900 cmd_buffer->state.offset_scale = att->ds.offset_scale;
901 }
902 radv_load_depth_clear_regs(cmd_buffer, image);
903 } else {
904 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
905 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
906 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
907 }
908 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
909 S_028208_BR_X(framebuffer->width) |
910 S_028208_BR_Y(framebuffer->height));
911 }
912
913 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
914 {
915 uint32_t db_count_control;
916
917 if(!cmd_buffer->state.active_occlusion_queries) {
918 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
919 db_count_control = 0;
920 } else {
921 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
922 }
923 } else {
924 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
925 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
926 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
927 S_028004_ZPASS_ENABLE(1) |
928 S_028004_SLICE_EVEN_ENABLE(1) |
929 S_028004_SLICE_ODD_ENABLE(1);
930 } else {
931 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
932 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
933 }
934 }
935
936 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
937 }
938
939 static void
940 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
941 {
942 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
943
944 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
945 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
946 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
947 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
948 }
949
950 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
951 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
952 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
953 }
954
955 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
956 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
957 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
958 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
959 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
960 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
961 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
962 S_028430_STENCILOPVAL(1));
963 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
964 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
965 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
966 S_028434_STENCILOPVAL_BF(1));
967 }
968
969 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
970 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
971 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
972 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
973 }
974
975 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
976 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
977 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
978 unsigned slope = fui(d->depth_bias.slope * 16.0f);
979 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
980
981 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
982 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
983 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
984 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
985 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
986 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
987 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
988 }
989 }
990
991 cmd_buffer->state.dirty = 0;
992 }
993
994 static void
995 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
996 struct radv_pipeline *pipeline,
997 int idx,
998 uint64_t va,
999 gl_shader_stage stage)
1000 {
1001 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1002 uint32_t base_reg = shader_stage_to_user_data_0(stage);
1003
1004 if (desc_set_loc->sgpr_idx == -1)
1005 return;
1006
1007 assert(!desc_set_loc->indirect);
1008 assert(desc_set_loc->num_sgprs == 2);
1009 radeon_set_sh_reg_seq(cmd_buffer->cs,
1010 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1011 radeon_emit(cmd_buffer->cs, va);
1012 radeon_emit(cmd_buffer->cs, va >> 32);
1013 }
1014
1015 static void
1016 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1017 struct radv_pipeline *pipeline,
1018 VkShaderStageFlags stages,
1019 struct radv_descriptor_set *set,
1020 unsigned idx)
1021 {
1022 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1023 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1024 idx, set->va,
1025 MESA_SHADER_FRAGMENT);
1026
1027 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1028 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1029 idx, set->va,
1030 MESA_SHADER_VERTEX);
1031
1032 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1033 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1034 idx, set->va,
1035 MESA_SHADER_COMPUTE);
1036 }
1037
1038 static void
1039 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1040 struct radv_pipeline *pipeline,
1041 VkShaderStageFlags stages)
1042 {
1043 unsigned i;
1044 if (!cmd_buffer->state.descriptors_dirty)
1045 return;
1046
1047 for (i = 0; i < MAX_SETS; i++) {
1048 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1049 continue;
1050 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1051 if (!set)
1052 continue;
1053
1054 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1055 }
1056 cmd_buffer->state.descriptors_dirty = 0;
1057 }
1058
1059 static void
1060 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1061 struct radv_pipeline *pipeline,
1062 VkShaderStageFlags stages)
1063 {
1064 struct radv_pipeline_layout *layout = pipeline->layout;
1065 unsigned offset;
1066 void *ptr;
1067 uint64_t va;
1068
1069 stages &= cmd_buffer->push_constant_stages;
1070 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1071 return;
1072
1073 radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1074 16 * layout->dynamic_offset_count,
1075 256, &offset, &ptr);
1076
1077 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1078 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1079 16 * layout->dynamic_offset_count);
1080
1081 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1082 va += offset;
1083
1084 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1085 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1086 AC_UD_PUSH_CONSTANTS, va);
1087
1088 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1089 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1090 AC_UD_PUSH_CONSTANTS, va);
1091
1092 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1093 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1094 AC_UD_PUSH_CONSTANTS, va);
1095
1096 cmd_buffer->push_constant_stages &= ~stages;
1097 }
1098
1099 static void
1100 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer)
1101 {
1102 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1103 struct radv_device *device = cmd_buffer->device;
1104 uint32_t ia_multi_vgt_param;
1105 uint32_t ls_hs_config = 0;
1106
1107 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1108 cmd_buffer->cs, 4096);
1109
1110 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1111 cmd_buffer->state.pipeline->num_vertex_attribs) {
1112 unsigned vb_offset;
1113 void *vb_ptr;
1114 uint32_t i = 0;
1115 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1116 uint64_t va;
1117
1118 /* allocate some descriptor state for vertex buffers */
1119 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1120 &vb_offset, &vb_ptr);
1121
1122 for (i = 0; i < num_attribs; i++) {
1123 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1124 uint32_t offset;
1125 int vb = cmd_buffer->state.pipeline->va_binding[i];
1126 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1127 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1128
1129 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1130 va = device->ws->buffer_get_va(buffer->bo);
1131
1132 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1133 va += offset + buffer->offset;
1134 desc[0] = va;
1135 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1136 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1137 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1138 else
1139 desc[2] = buffer->size - offset;
1140 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1141 }
1142
1143 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1144 va += vb_offset;
1145
1146 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1147 AC_UD_VS_VERTEX_BUFFERS, va);
1148 }
1149
1150 cmd_buffer->state.vertex_descriptors_dirty = false;
1151 cmd_buffer->state.vb_dirty = 0;
1152 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1153 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1154
1155 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1156 radv_emit_framebuffer_state(cmd_buffer);
1157
1158 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1159 radv_emit_viewport(cmd_buffer);
1160
1161 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR))
1162 radv_emit_scissor(cmd_buffer);
1163
1164 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1165 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, 0);
1166 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer);
1167
1168 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1169 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1170 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
1171 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1172 } else {
1173 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1174 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1175 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
1176 }
1177 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1178 }
1179
1180 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1181
1182 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1183 VK_SHADER_STAGE_ALL_GRAPHICS);
1184 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1185 VK_SHADER_STAGE_ALL_GRAPHICS);
1186
1187 assert(cmd_buffer->cs->cdw <= cdw_max);
1188
1189 si_emit_cache_flush(cmd_buffer);
1190 }
1191
1192 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1193 VkPipelineStageFlags src_stage_mask)
1194 {
1195 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1196 VK_PIPELINE_STAGE_TRANSFER_BIT |
1197 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1198 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1199 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1200 }
1201
1202 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1203 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1204 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1205 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1206 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1207 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1208 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1209 VK_PIPELINE_STAGE_TRANSFER_BIT |
1210 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1211 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1212 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1213 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1214 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1215 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1216 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1217 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1218 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1219 }
1220 }
1221
1222 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1223 {
1224 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1225
1226 /* TODO: actual cache flushes */
1227 }
1228
1229 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1230 VkAttachmentReference att)
1231 {
1232 unsigned idx = att.attachment;
1233 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1234 VkImageSubresourceRange range;
1235 range.aspectMask = 0;
1236 range.baseMipLevel = view->base_mip;
1237 range.levelCount = 1;
1238 range.baseArrayLayer = view->base_layer;
1239 range.layerCount = cmd_buffer->state.framebuffer->layers;
1240
1241 radv_handle_image_transition(cmd_buffer,
1242 view->image,
1243 cmd_buffer->state.attachments[idx].current_layout,
1244 att.layout, 0, 0, range,
1245 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1246
1247 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1248
1249
1250 }
1251
1252 void
1253 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1254 const struct radv_subpass *subpass, bool transitions)
1255 {
1256 if (transitions) {
1257 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1258
1259 for (unsigned i = 0; i < subpass->color_count; ++i) {
1260 radv_handle_subpass_image_transition(cmd_buffer,
1261 subpass->color_attachments[i]);
1262 }
1263
1264 for (unsigned i = 0; i < subpass->input_count; ++i) {
1265 radv_handle_subpass_image_transition(cmd_buffer,
1266 subpass->input_attachments[i]);
1267 }
1268
1269 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1270 radv_handle_subpass_image_transition(cmd_buffer,
1271 subpass->depth_stencil_attachment);
1272 }
1273 }
1274
1275 cmd_buffer->state.subpass = subpass;
1276
1277 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1278 }
1279
1280 static void
1281 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1282 struct radv_render_pass *pass,
1283 const VkRenderPassBeginInfo *info)
1284 {
1285 struct radv_cmd_state *state = &cmd_buffer->state;
1286
1287 if (pass->attachment_count == 0) {
1288 state->attachments = NULL;
1289 return;
1290 }
1291
1292 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1293 pass->attachment_count *
1294 sizeof(state->attachments[0]),
1295 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1296 if (state->attachments == NULL) {
1297 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1298 abort();
1299 }
1300
1301 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1302 struct radv_render_pass_attachment *att = &pass->attachments[i];
1303 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1304 VkImageAspectFlags clear_aspects = 0;
1305
1306 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1307 /* color attachment */
1308 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1309 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1310 }
1311 } else {
1312 /* depthstencil attachment */
1313 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1314 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1315 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1316 }
1317 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1318 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1319 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1320 }
1321 }
1322
1323 state->attachments[i].pending_clear_aspects = clear_aspects;
1324 if (clear_aspects && info) {
1325 assert(info->clearValueCount > i);
1326 state->attachments[i].clear_value = info->pClearValues[i];
1327 }
1328
1329 state->attachments[i].current_layout = att->initial_layout;
1330 }
1331 }
1332
1333 VkResult radv_AllocateCommandBuffers(
1334 VkDevice _device,
1335 const VkCommandBufferAllocateInfo *pAllocateInfo,
1336 VkCommandBuffer *pCommandBuffers)
1337 {
1338 RADV_FROM_HANDLE(radv_device, device, _device);
1339 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1340
1341 VkResult result = VK_SUCCESS;
1342 uint32_t i;
1343
1344 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1345 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1346 &pCommandBuffers[i]);
1347 if (result != VK_SUCCESS)
1348 break;
1349 }
1350
1351 if (result != VK_SUCCESS)
1352 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1353 i, pCommandBuffers);
1354
1355 return result;
1356 }
1357
1358 static void
1359 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
1360 {
1361 list_del(&cmd_buffer->pool_link);
1362
1363 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1364 &cmd_buffer->upload.list, list) {
1365 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1366 list_del(&up->list);
1367 free(up);
1368 }
1369
1370 if (cmd_buffer->upload.upload_bo)
1371 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
1372 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
1373 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1374 }
1375
1376 void radv_FreeCommandBuffers(
1377 VkDevice device,
1378 VkCommandPool commandPool,
1379 uint32_t commandBufferCount,
1380 const VkCommandBuffer *pCommandBuffers)
1381 {
1382 for (uint32_t i = 0; i < commandBufferCount; i++) {
1383 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1384
1385 if (cmd_buffer)
1386 radv_cmd_buffer_destroy(cmd_buffer);
1387 }
1388 }
1389
1390 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
1391 {
1392
1393 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
1394
1395 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1396 &cmd_buffer->upload.list, list) {
1397 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1398 list_del(&up->list);
1399 free(up);
1400 }
1401
1402 if (cmd_buffer->upload.upload_bo)
1403 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
1404 cmd_buffer->upload.upload_bo, 8);
1405 cmd_buffer->upload.offset = 0;
1406
1407 cmd_buffer->record_fail = false;
1408 }
1409
1410 VkResult radv_ResetCommandBuffer(
1411 VkCommandBuffer commandBuffer,
1412 VkCommandBufferResetFlags flags)
1413 {
1414 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1415 radv_reset_cmd_buffer(cmd_buffer);
1416 return VK_SUCCESS;
1417 }
1418
1419 VkResult radv_BeginCommandBuffer(
1420 VkCommandBuffer commandBuffer,
1421 const VkCommandBufferBeginInfo *pBeginInfo)
1422 {
1423 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1424 radv_reset_cmd_buffer(cmd_buffer);
1425
1426 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1427
1428 /* setup initial configuration into command buffer */
1429 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1430 switch (cmd_buffer->queue_family_index) {
1431 case RADV_QUEUE_GENERAL:
1432 /* Flush read caches at the beginning of CS not flushed by the kernel. */
1433 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_ICACHE |
1434 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1435 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1436 RADV_CMD_FLAG_INV_VMEM_L1 |
1437 RADV_CMD_FLAG_INV_SMEM_L1 |
1438 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
1439 RADV_CMD_FLAG_INV_GLOBAL_L2;
1440 si_init_config(cmd_buffer->device->physical_device, cmd_buffer);
1441 radv_set_db_count_control(cmd_buffer);
1442 si_emit_cache_flush(cmd_buffer);
1443 break;
1444 case RADV_QUEUE_COMPUTE:
1445 cmd_buffer->state.flush_bits = RADV_CMD_FLAG_INV_ICACHE |
1446 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1447 RADV_CMD_FLAG_INV_VMEM_L1 |
1448 RADV_CMD_FLAG_INV_SMEM_L1 |
1449 RADV_CMD_FLAG_INV_GLOBAL_L2;
1450 si_init_compute(cmd_buffer->device->physical_device, cmd_buffer);
1451 si_emit_cache_flush(cmd_buffer);
1452 break;
1453 case RADV_QUEUE_TRANSFER:
1454 default:
1455 break;
1456 }
1457 }
1458
1459 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1460 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1461 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1462
1463 struct radv_subpass *subpass =
1464 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1465
1466 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1467 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1468 }
1469
1470 return VK_SUCCESS;
1471 }
1472
1473 void radv_CmdBindVertexBuffers(
1474 VkCommandBuffer commandBuffer,
1475 uint32_t firstBinding,
1476 uint32_t bindingCount,
1477 const VkBuffer* pBuffers,
1478 const VkDeviceSize* pOffsets)
1479 {
1480 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1481 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1482
1483 /* We have to defer setting up vertex buffer since we need the buffer
1484 * stride from the pipeline. */
1485
1486 assert(firstBinding + bindingCount < MAX_VBS);
1487 for (uint32_t i = 0; i < bindingCount; i++) {
1488 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1489 vb[firstBinding + i].offset = pOffsets[i];
1490 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1491 }
1492 }
1493
1494 void radv_CmdBindIndexBuffer(
1495 VkCommandBuffer commandBuffer,
1496 VkBuffer buffer,
1497 VkDeviceSize offset,
1498 VkIndexType indexType)
1499 {
1500 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1501
1502 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1503 cmd_buffer->state.index_offset = offset;
1504 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1505 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1506 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1507 }
1508
1509
1510 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1511 struct radv_descriptor_set *set,
1512 unsigned idx)
1513 {
1514 struct radeon_winsys *ws = cmd_buffer->device->ws;
1515
1516 cmd_buffer->state.descriptors[idx] = set;
1517 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1518 if (!set)
1519 return;
1520
1521 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1522 if (set->descriptors[j])
1523 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1524
1525 if(set->bo)
1526 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1527 }
1528
1529 void radv_CmdBindDescriptorSets(
1530 VkCommandBuffer commandBuffer,
1531 VkPipelineBindPoint pipelineBindPoint,
1532 VkPipelineLayout _layout,
1533 uint32_t firstSet,
1534 uint32_t descriptorSetCount,
1535 const VkDescriptorSet* pDescriptorSets,
1536 uint32_t dynamicOffsetCount,
1537 const uint32_t* pDynamicOffsets)
1538 {
1539 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1540 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1541 unsigned dyn_idx = 0;
1542
1543 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1544 cmd_buffer->cs, MAX_SETS * 4 * 6);
1545
1546 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1547 unsigned idx = i + firstSet;
1548 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1549 radv_bind_descriptor_set(cmd_buffer, set, idx);
1550
1551 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1552 unsigned idx = j + layout->set[i].dynamic_offset_start;
1553 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1554 assert(dyn_idx < dynamicOffsetCount);
1555
1556 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1557 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1558 dst[0] = va;
1559 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1560 dst[2] = range->size;
1561 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1562 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1563 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1564 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1565 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1566 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1567 cmd_buffer->push_constant_stages |=
1568 set->layout->dynamic_shader_stages;
1569 }
1570 }
1571
1572 assert(cmd_buffer->cs->cdw <= cdw_max);
1573 }
1574
1575 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1576 VkPipelineLayout layout,
1577 VkShaderStageFlags stageFlags,
1578 uint32_t offset,
1579 uint32_t size,
1580 const void* pValues)
1581 {
1582 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1583 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1584 cmd_buffer->push_constant_stages |= stageFlags;
1585 }
1586
1587 VkResult radv_EndCommandBuffer(
1588 VkCommandBuffer commandBuffer)
1589 {
1590 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1591
1592 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
1593 si_emit_cache_flush(cmd_buffer);
1594 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1595 cmd_buffer->record_fail)
1596 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1597 return VK_SUCCESS;
1598 }
1599
1600 static void
1601 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1602 {
1603 struct radeon_winsys *ws = cmd_buffer->device->ws;
1604 struct radv_shader_variant *compute_shader;
1605 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1606 uint64_t va;
1607
1608 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1609 return;
1610
1611 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1612
1613 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1614 va = ws->buffer_get_va(compute_shader->bo);
1615
1616 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1617
1618 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1619 cmd_buffer->cs, 16);
1620
1621 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1622 radeon_emit(cmd_buffer->cs, va >> 8);
1623 radeon_emit(cmd_buffer->cs, va >> 40);
1624
1625 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1626 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1627 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1628
1629 /* change these once we have scratch support */
1630 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1631 S_00B860_WAVES(32) | S_00B860_WAVESIZE(0));
1632
1633 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1634 radeon_emit(cmd_buffer->cs,
1635 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1636 radeon_emit(cmd_buffer->cs,
1637 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1638 radeon_emit(cmd_buffer->cs,
1639 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1640
1641 assert(cmd_buffer->cs->cdw <= cdw_max);
1642 }
1643
1644
1645 void radv_CmdBindPipeline(
1646 VkCommandBuffer commandBuffer,
1647 VkPipelineBindPoint pipelineBindPoint,
1648 VkPipeline _pipeline)
1649 {
1650 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1651 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1652
1653 for (unsigned i = 0; i < MAX_SETS; i++) {
1654 if (cmd_buffer->state.descriptors[i])
1655 cmd_buffer->state.descriptors_dirty |= (1 << i);
1656 }
1657
1658 switch (pipelineBindPoint) {
1659 case VK_PIPELINE_BIND_POINT_COMPUTE:
1660 cmd_buffer->state.compute_pipeline = pipeline;
1661 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
1662 break;
1663 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1664 cmd_buffer->state.pipeline = pipeline;
1665 cmd_buffer->state.vertex_descriptors_dirty = true;
1666 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1667 cmd_buffer->push_constant_stages |= pipeline->active_stages;
1668
1669 /* Apply the dynamic state from the pipeline */
1670 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
1671 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
1672 &pipeline->dynamic_state,
1673 pipeline->dynamic_state_mask);
1674 break;
1675 default:
1676 assert(!"invalid bind point");
1677 break;
1678 }
1679 }
1680
1681 void radv_CmdSetViewport(
1682 VkCommandBuffer commandBuffer,
1683 uint32_t firstViewport,
1684 uint32_t viewportCount,
1685 const VkViewport* pViewports)
1686 {
1687 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1688
1689 const uint32_t total_count = firstViewport + viewportCount;
1690 if (cmd_buffer->state.dynamic.viewport.count < total_count)
1691 cmd_buffer->state.dynamic.viewport.count = total_count;
1692
1693 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
1694 pViewports, viewportCount * sizeof(*pViewports));
1695
1696 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
1697 }
1698
1699 void radv_CmdSetScissor(
1700 VkCommandBuffer commandBuffer,
1701 uint32_t firstScissor,
1702 uint32_t scissorCount,
1703 const VkRect2D* pScissors)
1704 {
1705 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1706
1707 const uint32_t total_count = firstScissor + scissorCount;
1708 if (cmd_buffer->state.dynamic.scissor.count < total_count)
1709 cmd_buffer->state.dynamic.scissor.count = total_count;
1710
1711 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
1712 pScissors, scissorCount * sizeof(*pScissors));
1713 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1714 }
1715
1716 void radv_CmdSetLineWidth(
1717 VkCommandBuffer commandBuffer,
1718 float lineWidth)
1719 {
1720 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1721 cmd_buffer->state.dynamic.line_width = lineWidth;
1722 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1723 }
1724
1725 void radv_CmdSetDepthBias(
1726 VkCommandBuffer commandBuffer,
1727 float depthBiasConstantFactor,
1728 float depthBiasClamp,
1729 float depthBiasSlopeFactor)
1730 {
1731 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1732
1733 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
1734 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
1735 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
1736
1737 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1738 }
1739
1740 void radv_CmdSetBlendConstants(
1741 VkCommandBuffer commandBuffer,
1742 const float blendConstants[4])
1743 {
1744 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1745
1746 memcpy(cmd_buffer->state.dynamic.blend_constants,
1747 blendConstants, sizeof(float) * 4);
1748
1749 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
1750 }
1751
1752 void radv_CmdSetDepthBounds(
1753 VkCommandBuffer commandBuffer,
1754 float minDepthBounds,
1755 float maxDepthBounds)
1756 {
1757 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1758
1759 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
1760 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
1761
1762 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
1763 }
1764
1765 void radv_CmdSetStencilCompareMask(
1766 VkCommandBuffer commandBuffer,
1767 VkStencilFaceFlags faceMask,
1768 uint32_t compareMask)
1769 {
1770 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1771
1772 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1773 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
1774 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1775 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
1776
1777 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1778 }
1779
1780 void radv_CmdSetStencilWriteMask(
1781 VkCommandBuffer commandBuffer,
1782 VkStencilFaceFlags faceMask,
1783 uint32_t writeMask)
1784 {
1785 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1786
1787 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1788 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
1789 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1790 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
1791
1792 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1793 }
1794
1795 void radv_CmdSetStencilReference(
1796 VkCommandBuffer commandBuffer,
1797 VkStencilFaceFlags faceMask,
1798 uint32_t reference)
1799 {
1800 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1801
1802 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1803 cmd_buffer->state.dynamic.stencil_reference.front = reference;
1804 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1805 cmd_buffer->state.dynamic.stencil_reference.back = reference;
1806
1807 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1808 }
1809
1810
1811 void radv_CmdExecuteCommands(
1812 VkCommandBuffer commandBuffer,
1813 uint32_t commandBufferCount,
1814 const VkCommandBuffer* pCmdBuffers)
1815 {
1816 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
1817
1818 for (uint32_t i = 0; i < commandBufferCount; i++) {
1819 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
1820
1821 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
1822 }
1823
1824 /* if we execute secondary we need to re-emit out pipelines */
1825 if (commandBufferCount) {
1826 primary->state.emitted_pipeline = NULL;
1827 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1828 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
1829 }
1830 }
1831
1832 VkResult radv_CreateCommandPool(
1833 VkDevice _device,
1834 const VkCommandPoolCreateInfo* pCreateInfo,
1835 const VkAllocationCallbacks* pAllocator,
1836 VkCommandPool* pCmdPool)
1837 {
1838 RADV_FROM_HANDLE(radv_device, device, _device);
1839 struct radv_cmd_pool *pool;
1840
1841 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
1842 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1843 if (pool == NULL)
1844 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1845
1846 if (pAllocator)
1847 pool->alloc = *pAllocator;
1848 else
1849 pool->alloc = device->alloc;
1850
1851 list_inithead(&pool->cmd_buffers);
1852
1853 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
1854
1855 *pCmdPool = radv_cmd_pool_to_handle(pool);
1856
1857 return VK_SUCCESS;
1858
1859 }
1860
1861 void radv_DestroyCommandPool(
1862 VkDevice _device,
1863 VkCommandPool commandPool,
1864 const VkAllocationCallbacks* pAllocator)
1865 {
1866 RADV_FROM_HANDLE(radv_device, device, _device);
1867 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
1868
1869 if (!pool)
1870 return;
1871
1872 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
1873 &pool->cmd_buffers, pool_link) {
1874 radv_cmd_buffer_destroy(cmd_buffer);
1875 }
1876
1877 vk_free2(&device->alloc, pAllocator, pool);
1878 }
1879
1880 VkResult radv_ResetCommandPool(
1881 VkDevice device,
1882 VkCommandPool commandPool,
1883 VkCommandPoolResetFlags flags)
1884 {
1885 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
1886
1887 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
1888 &pool->cmd_buffers, pool_link) {
1889 radv_reset_cmd_buffer(cmd_buffer);
1890 }
1891
1892 return VK_SUCCESS;
1893 }
1894
1895 void radv_CmdBeginRenderPass(
1896 VkCommandBuffer commandBuffer,
1897 const VkRenderPassBeginInfo* pRenderPassBegin,
1898 VkSubpassContents contents)
1899 {
1900 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1901 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
1902 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
1903
1904 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1905 cmd_buffer->cs, 2048);
1906
1907 cmd_buffer->state.framebuffer = framebuffer;
1908 cmd_buffer->state.pass = pass;
1909 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
1910 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
1911
1912 si_emit_cache_flush(cmd_buffer);
1913
1914 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
1915 assert(cmd_buffer->cs->cdw <= cdw_max);
1916
1917 radv_cmd_buffer_clear_subpass(cmd_buffer);
1918 }
1919
1920 void radv_CmdNextSubpass(
1921 VkCommandBuffer commandBuffer,
1922 VkSubpassContents contents)
1923 {
1924 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1925
1926 si_emit_cache_flush(cmd_buffer);
1927 radv_cmd_buffer_resolve_subpass(cmd_buffer);
1928
1929 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
1930 2048);
1931
1932 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
1933 radv_cmd_buffer_clear_subpass(cmd_buffer);
1934 }
1935
1936 void radv_CmdDraw(
1937 VkCommandBuffer commandBuffer,
1938 uint32_t vertexCount,
1939 uint32_t instanceCount,
1940 uint32_t firstVertex,
1941 uint32_t firstInstance)
1942 {
1943 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1944 radv_cmd_buffer_flush_state(cmd_buffer);
1945
1946 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1947
1948 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1949 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
1950 if (loc->sgpr_idx != -1) {
1951 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4, 2);
1952 radeon_emit(cmd_buffer->cs, firstVertex);
1953 radeon_emit(cmd_buffer->cs, firstInstance);
1954 }
1955 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
1956 radeon_emit(cmd_buffer->cs, instanceCount);
1957
1958 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
1959 radeon_emit(cmd_buffer->cs, vertexCount);
1960 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1961 S_0287F0_USE_OPAQUE(0));
1962
1963 assert(cmd_buffer->cs->cdw <= cdw_max);
1964
1965 radv_cmd_buffer_trace_emit(cmd_buffer);
1966 }
1967
1968 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
1969 {
1970 uint32_t primitive_reset_index = cmd_buffer->state.last_primitive_reset_index ? 0xffffffffu : 0xffffu;
1971
1972 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
1973 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1974 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1975 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1976 primitive_reset_index);
1977 }
1978 }
1979
1980 void radv_CmdDrawIndexed(
1981 VkCommandBuffer commandBuffer,
1982 uint32_t indexCount,
1983 uint32_t instanceCount,
1984 uint32_t firstIndex,
1985 int32_t vertexOffset,
1986 uint32_t firstInstance)
1987 {
1988 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1989 int index_size = cmd_buffer->state.index_type ? 4 : 2;
1990 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
1991 uint64_t index_va;
1992
1993 radv_cmd_buffer_flush_state(cmd_buffer);
1994 radv_emit_primitive_reset_index(cmd_buffer);
1995
1996 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 14);
1997
1998 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1999 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2000
2001 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2002 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2003 if (loc->sgpr_idx != -1) {
2004 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4, 2);
2005 radeon_emit(cmd_buffer->cs, vertexOffset);
2006 radeon_emit(cmd_buffer->cs, firstInstance);
2007 }
2008 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2009 radeon_emit(cmd_buffer->cs, instanceCount);
2010
2011 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2012 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2013 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2014 radeon_emit(cmd_buffer->cs, index_max_size);
2015 radeon_emit(cmd_buffer->cs, index_va);
2016 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2017 radeon_emit(cmd_buffer->cs, indexCount);
2018 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2019
2020 assert(cmd_buffer->cs->cdw <= cdw_max);
2021 radv_cmd_buffer_trace_emit(cmd_buffer);
2022 }
2023
2024 static void
2025 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2026 VkBuffer _buffer,
2027 VkDeviceSize offset,
2028 VkBuffer _count_buffer,
2029 VkDeviceSize count_offset,
2030 uint32_t draw_count,
2031 uint32_t stride,
2032 bool indexed)
2033 {
2034 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2035 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2036 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2037 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2038 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2039 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2040 indirect_va += offset + buffer->offset;
2041 uint64_t count_va = 0;
2042
2043 if (count_buffer) {
2044 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2045 count_va += count_offset + count_buffer->offset;
2046 }
2047
2048 if (!draw_count)
2049 return;
2050
2051 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2052
2053 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2054 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2055 assert(loc->sgpr_idx != -1);
2056 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2057 radeon_emit(cs, 1);
2058 radeon_emit(cs, indirect_va);
2059 radeon_emit(cs, indirect_va >> 32);
2060
2061 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2062 PKT3_DRAW_INDIRECT_MULTI,
2063 8, false));
2064 radeon_emit(cs, 0);
2065 radeon_emit(cs, ((R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2066 radeon_emit(cs, ((R_00B130_SPI_SHADER_USER_DATA_VS_0 + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2067 radeon_emit(cs, S_2C3_COUNT_INDIRECT_ENABLE(!!count_va)); /* draw_index and count_indirect enable */
2068 radeon_emit(cs, draw_count); /* count */
2069 radeon_emit(cs, count_va); /* count_addr */
2070 radeon_emit(cs, count_va >> 32);
2071 radeon_emit(cs, stride); /* stride */
2072 radeon_emit(cs, di_src_sel);
2073 radv_cmd_buffer_trace_emit(cmd_buffer);
2074 }
2075
2076 static void
2077 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2078 VkBuffer buffer,
2079 VkDeviceSize offset,
2080 VkBuffer countBuffer,
2081 VkDeviceSize countBufferOffset,
2082 uint32_t maxDrawCount,
2083 uint32_t stride)
2084 {
2085 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2086 radv_cmd_buffer_flush_state(cmd_buffer);
2087
2088 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2089 cmd_buffer->cs, 14);
2090
2091 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2092 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2093
2094 assert(cmd_buffer->cs->cdw <= cdw_max);
2095 }
2096
2097 static void
2098 radv_cmd_draw_indexed_indirect_count(
2099 VkCommandBuffer commandBuffer,
2100 VkBuffer buffer,
2101 VkDeviceSize offset,
2102 VkBuffer countBuffer,
2103 VkDeviceSize countBufferOffset,
2104 uint32_t maxDrawCount,
2105 uint32_t stride)
2106 {
2107 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2108 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2109 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2110 uint64_t index_va;
2111 radv_cmd_buffer_flush_state(cmd_buffer);
2112 radv_emit_primitive_reset_index(cmd_buffer);
2113
2114 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2115 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2116
2117 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2118
2119 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2120 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2121
2122 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2123 radeon_emit(cmd_buffer->cs, index_va);
2124 radeon_emit(cmd_buffer->cs, index_va >> 32);
2125
2126 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2127 radeon_emit(cmd_buffer->cs, index_max_size);
2128
2129 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2130 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2131
2132 assert(cmd_buffer->cs->cdw <= cdw_max);
2133 }
2134
2135 void radv_CmdDrawIndirect(
2136 VkCommandBuffer commandBuffer,
2137 VkBuffer buffer,
2138 VkDeviceSize offset,
2139 uint32_t drawCount,
2140 uint32_t stride)
2141 {
2142 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2143 VK_NULL_HANDLE, 0, drawCount, stride);
2144 }
2145
2146 void radv_CmdDrawIndexedIndirect(
2147 VkCommandBuffer commandBuffer,
2148 VkBuffer buffer,
2149 VkDeviceSize offset,
2150 uint32_t drawCount,
2151 uint32_t stride)
2152 {
2153 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2154 VK_NULL_HANDLE, 0, drawCount, stride);
2155 }
2156
2157 void radv_CmdDrawIndirectCountAMD(
2158 VkCommandBuffer commandBuffer,
2159 VkBuffer buffer,
2160 VkDeviceSize offset,
2161 VkBuffer countBuffer,
2162 VkDeviceSize countBufferOffset,
2163 uint32_t maxDrawCount,
2164 uint32_t stride)
2165 {
2166 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2167 countBuffer, countBufferOffset,
2168 maxDrawCount, stride);
2169 }
2170
2171 void radv_CmdDrawIndexedIndirectCountAMD(
2172 VkCommandBuffer commandBuffer,
2173 VkBuffer buffer,
2174 VkDeviceSize offset,
2175 VkBuffer countBuffer,
2176 VkDeviceSize countBufferOffset,
2177 uint32_t maxDrawCount,
2178 uint32_t stride)
2179 {
2180 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2181 countBuffer, countBufferOffset,
2182 maxDrawCount, stride);
2183 }
2184
2185 static void
2186 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2187 {
2188 radv_emit_compute_pipeline(cmd_buffer);
2189 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2190 VK_SHADER_STAGE_COMPUTE_BIT);
2191 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2192 VK_SHADER_STAGE_COMPUTE_BIT);
2193 si_emit_cache_flush(cmd_buffer);
2194 }
2195
2196 void radv_CmdDispatch(
2197 VkCommandBuffer commandBuffer,
2198 uint32_t x,
2199 uint32_t y,
2200 uint32_t z)
2201 {
2202 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2203
2204 radv_flush_compute_state(cmd_buffer);
2205
2206 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2207
2208 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2209 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2210 if (loc->sgpr_idx != -1) {
2211 assert(!loc->indirect);
2212 assert(loc->num_sgprs == 3);
2213 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2214 radeon_emit(cmd_buffer->cs, x);
2215 radeon_emit(cmd_buffer->cs, y);
2216 radeon_emit(cmd_buffer->cs, z);
2217 }
2218
2219 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2220 PKT3_SHADER_TYPE_S(1));
2221 radeon_emit(cmd_buffer->cs, x);
2222 radeon_emit(cmd_buffer->cs, y);
2223 radeon_emit(cmd_buffer->cs, z);
2224 radeon_emit(cmd_buffer->cs, 1);
2225
2226 assert(cmd_buffer->cs->cdw <= cdw_max);
2227 radv_cmd_buffer_trace_emit(cmd_buffer);
2228 }
2229
2230 void radv_CmdDispatchIndirect(
2231 VkCommandBuffer commandBuffer,
2232 VkBuffer _buffer,
2233 VkDeviceSize offset)
2234 {
2235 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2236 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2237 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2238 va += buffer->offset + offset;
2239
2240 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2241
2242 radv_flush_compute_state(cmd_buffer);
2243
2244 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2245 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2246 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2247 if (loc->sgpr_idx != -1) {
2248 for (unsigned i = 0; i < 3; ++i) {
2249 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2250 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2251 COPY_DATA_DST_SEL(COPY_DATA_REG));
2252 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2253 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2254 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2255 radeon_emit(cmd_buffer->cs, 0);
2256 }
2257 }
2258
2259 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2260 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2261 PKT3_SHADER_TYPE_S(1));
2262 radeon_emit(cmd_buffer->cs, va);
2263 radeon_emit(cmd_buffer->cs, va >> 32);
2264 radeon_emit(cmd_buffer->cs, 1);
2265 } else {
2266 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2267 PKT3_SHADER_TYPE_S(1));
2268 radeon_emit(cmd_buffer->cs, 1);
2269 radeon_emit(cmd_buffer->cs, va);
2270 radeon_emit(cmd_buffer->cs, va >> 32);
2271
2272 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2273 PKT3_SHADER_TYPE_S(1));
2274 radeon_emit(cmd_buffer->cs, 0);
2275 radeon_emit(cmd_buffer->cs, 1);
2276 }
2277
2278 assert(cmd_buffer->cs->cdw <= cdw_max);
2279 radv_cmd_buffer_trace_emit(cmd_buffer);
2280 }
2281
2282 void radv_unaligned_dispatch(
2283 struct radv_cmd_buffer *cmd_buffer,
2284 uint32_t x,
2285 uint32_t y,
2286 uint32_t z)
2287 {
2288 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2289 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2290 uint32_t blocks[3], remainder[3];
2291
2292 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2293 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2294 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2295
2296 /* If aligned, these should be an entire block size, not 0 */
2297 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2298 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2299 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2300
2301 radv_flush_compute_state(cmd_buffer);
2302
2303 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2304
2305 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2306 radeon_emit(cmd_buffer->cs,
2307 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2308 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2309 radeon_emit(cmd_buffer->cs,
2310 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2311 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2312 radeon_emit(cmd_buffer->cs,
2313 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2314 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2315
2316 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2317 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2318 if (loc->sgpr_idx != -1) {
2319 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2320 radeon_emit(cmd_buffer->cs, blocks[0]);
2321 radeon_emit(cmd_buffer->cs, blocks[1]);
2322 radeon_emit(cmd_buffer->cs, blocks[2]);
2323 }
2324 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2325 PKT3_SHADER_TYPE_S(1));
2326 radeon_emit(cmd_buffer->cs, blocks[0]);
2327 radeon_emit(cmd_buffer->cs, blocks[1]);
2328 radeon_emit(cmd_buffer->cs, blocks[2]);
2329 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2330 S_00B800_PARTIAL_TG_EN(1));
2331
2332 assert(cmd_buffer->cs->cdw <= cdw_max);
2333 radv_cmd_buffer_trace_emit(cmd_buffer);
2334 }
2335
2336 void radv_CmdEndRenderPass(
2337 VkCommandBuffer commandBuffer)
2338 {
2339 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2340
2341 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2342
2343 si_emit_cache_flush(cmd_buffer);
2344 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2345
2346 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2347 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2348 radv_handle_subpass_image_transition(cmd_buffer,
2349 (VkAttachmentReference){i, layout});
2350 }
2351
2352 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2353
2354 cmd_buffer->state.pass = NULL;
2355 cmd_buffer->state.subpass = NULL;
2356 cmd_buffer->state.attachments = NULL;
2357 cmd_buffer->state.framebuffer = NULL;
2358 }
2359
2360
2361 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2362 struct radv_image *image)
2363 {
2364
2365 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2366 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2367
2368 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->htile.offset,
2369 image->htile.size, 0xffffffff);
2370
2371 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2372 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2373 RADV_CMD_FLAG_INV_VMEM_L1 |
2374 RADV_CMD_FLAG_INV_GLOBAL_L2;
2375 }
2376
2377 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2378 struct radv_image *image,
2379 VkImageLayout src_layout,
2380 VkImageLayout dst_layout,
2381 VkImageSubresourceRange range,
2382 VkImageAspectFlags pending_clears)
2383 {
2384 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2385 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2386 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2387 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2388 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2389 /* The clear will initialize htile. */
2390 return;
2391 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2392 radv_layout_has_htile(image, dst_layout)) {
2393 /* TODO: merge with the clear if applicable */
2394 radv_initialize_htile(cmd_buffer, image);
2395 } else if (!radv_layout_has_htile(image, src_layout) &&
2396 radv_layout_has_htile(image, dst_layout)) {
2397 radv_initialize_htile(cmd_buffer, image);
2398 } else if ((radv_layout_has_htile(image, src_layout) &&
2399 !radv_layout_has_htile(image, dst_layout)) ||
2400 (radv_layout_is_htile_compressed(image, src_layout) &&
2401 !radv_layout_is_htile_compressed(image, dst_layout))) {
2402
2403 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2404 range.baseMipLevel = 0;
2405 range.levelCount = 1;
2406
2407 radv_decompress_depth_image_inplace(cmd_buffer, image, &range);
2408 }
2409 }
2410
2411 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2412 struct radv_image *image, uint32_t value)
2413 {
2414 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2415 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2416
2417 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2418 image->cmask.size, value);
2419
2420 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2421 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2422 RADV_CMD_FLAG_INV_VMEM_L1 |
2423 RADV_CMD_FLAG_INV_GLOBAL_L2;
2424 }
2425
2426 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2427 struct radv_image *image,
2428 VkImageLayout src_layout,
2429 VkImageLayout dst_layout,
2430 unsigned src_queue_mask,
2431 unsigned dst_queue_mask,
2432 VkImageSubresourceRange range,
2433 VkImageAspectFlags pending_clears)
2434 {
2435 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2436 if (image->fmask.size)
2437 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2438 else
2439 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2440 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2441 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2442 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2443 }
2444 }
2445
2446 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2447 struct radv_image *image, uint32_t value)
2448 {
2449
2450 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2451 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2452
2453 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2454 image->surface.dcc_size, value);
2455
2456 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2457 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2458 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2459 RADV_CMD_FLAG_INV_VMEM_L1 |
2460 RADV_CMD_FLAG_INV_GLOBAL_L2;
2461 }
2462
2463 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2464 struct radv_image *image,
2465 VkImageLayout src_layout,
2466 VkImageLayout dst_layout,
2467 unsigned src_queue_mask,
2468 unsigned dst_queue_mask,
2469 VkImageSubresourceRange range,
2470 VkImageAspectFlags pending_clears)
2471 {
2472 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2473 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2474 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2475 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2476 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2477 }
2478 }
2479
2480 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2481 struct radv_image *image,
2482 VkImageLayout src_layout,
2483 VkImageLayout dst_layout,
2484 int src_family,
2485 int dst_family,
2486 VkImageSubresourceRange range,
2487 VkImageAspectFlags pending_clears)
2488 {
2489 if (image->exclusive && src_family != dst_family) {
2490 /* This is an acquire or a release operation and there will be
2491 * a corresponding release/acquire. Do the transition in the
2492 * most flexible queue. */
2493
2494 assert(src_family == cmd_buffer->queue_family_index ||
2495 dst_family == cmd_buffer->queue_family_index);
2496
2497 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
2498 return;
2499
2500 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
2501 (src_family == RADV_QUEUE_GENERAL ||
2502 dst_family == RADV_QUEUE_GENERAL))
2503 return;
2504 }
2505
2506 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family);
2507 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family);
2508
2509 if (image->htile.size)
2510 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2511 dst_layout, range, pending_clears);
2512
2513 if (image->cmask.size)
2514 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2515 dst_layout, src_queue_mask,
2516 dst_queue_mask, range,
2517 pending_clears);
2518
2519 if (image->surface.dcc_size)
2520 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2521 dst_layout, src_queue_mask,
2522 dst_queue_mask, range,
2523 pending_clears);
2524 }
2525
2526 void radv_CmdPipelineBarrier(
2527 VkCommandBuffer commandBuffer,
2528 VkPipelineStageFlags srcStageMask,
2529 VkPipelineStageFlags destStageMask,
2530 VkBool32 byRegion,
2531 uint32_t memoryBarrierCount,
2532 const VkMemoryBarrier* pMemoryBarriers,
2533 uint32_t bufferMemoryBarrierCount,
2534 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2535 uint32_t imageMemoryBarrierCount,
2536 const VkImageMemoryBarrier* pImageMemoryBarriers)
2537 {
2538 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2539 VkAccessFlags src_flags = 0;
2540 VkAccessFlags dst_flags = 0;
2541 uint32_t b;
2542 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2543 src_flags |= pMemoryBarriers[i].srcAccessMask;
2544 dst_flags |= pMemoryBarriers[i].dstAccessMask;
2545 }
2546
2547 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2548 src_flags |= pBufferMemoryBarriers[i].srcAccessMask;
2549 dst_flags |= pBufferMemoryBarriers[i].dstAccessMask;
2550 }
2551
2552 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2553 src_flags |= pImageMemoryBarriers[i].srcAccessMask;
2554 dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
2555 }
2556
2557 enum radv_cmd_flush_bits flush_bits = 0;
2558 for_each_bit(b, src_flags) {
2559 switch ((VkAccessFlagBits)(1 << b)) {
2560 case VK_ACCESS_SHADER_WRITE_BIT:
2561 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2562 break;
2563 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2564 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2565 break;
2566 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2567 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2568 break;
2569 case VK_ACCESS_TRANSFER_WRITE_BIT:
2570 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2571 break;
2572 default:
2573 break;
2574 }
2575 }
2576 cmd_buffer->state.flush_bits |= flush_bits;
2577
2578 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2579 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2580 radv_handle_image_transition(cmd_buffer, image,
2581 pImageMemoryBarriers[i].oldLayout,
2582 pImageMemoryBarriers[i].newLayout,
2583 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2584 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2585 pImageMemoryBarriers[i].subresourceRange,
2586 0);
2587 }
2588
2589 flush_bits = 0;
2590
2591 for_each_bit(b, dst_flags) {
2592 switch ((VkAccessFlagBits)(1 << b)) {
2593 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2594 case VK_ACCESS_INDEX_READ_BIT:
2595 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2596 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2597 break;
2598 case VK_ACCESS_UNIFORM_READ_BIT:
2599 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2600 break;
2601 case VK_ACCESS_SHADER_READ_BIT:
2602 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2603 break;
2604 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2605 case VK_ACCESS_TRANSFER_READ_BIT:
2606 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2607 flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER | RADV_CMD_FLAG_INV_GLOBAL_L2;
2608 default:
2609 break;
2610 }
2611 }
2612
2613 flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2614 RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2615
2616 cmd_buffer->state.flush_bits |= flush_bits;
2617 }
2618
2619
2620 static void write_event(struct radv_cmd_buffer *cmd_buffer,
2621 struct radv_event *event,
2622 VkPipelineStageFlags stageMask,
2623 unsigned value)
2624 {
2625 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2626 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2627
2628 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2629
2630 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
2631
2632 /* TODO: this is overkill. Probably should figure something out from
2633 * the stage mask. */
2634
2635 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
2636 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2637 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2638 EVENT_INDEX(5));
2639 radeon_emit(cs, va);
2640 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2641 radeon_emit(cs, 2);
2642 radeon_emit(cs, 0);
2643 }
2644
2645 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2646 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2647 EVENT_INDEX(5));
2648 radeon_emit(cs, va);
2649 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2650 radeon_emit(cs, value);
2651 radeon_emit(cs, 0);
2652
2653 assert(cmd_buffer->cs->cdw <= cdw_max);
2654 }
2655
2656 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
2657 VkEvent _event,
2658 VkPipelineStageFlags stageMask)
2659 {
2660 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2661 RADV_FROM_HANDLE(radv_event, event, _event);
2662
2663 write_event(cmd_buffer, event, stageMask, 1);
2664 }
2665
2666 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
2667 VkEvent _event,
2668 VkPipelineStageFlags stageMask)
2669 {
2670 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2671 RADV_FROM_HANDLE(radv_event, event, _event);
2672
2673 write_event(cmd_buffer, event, stageMask, 0);
2674 }
2675
2676 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
2677 uint32_t eventCount,
2678 const VkEvent* pEvents,
2679 VkPipelineStageFlags srcStageMask,
2680 VkPipelineStageFlags dstStageMask,
2681 uint32_t memoryBarrierCount,
2682 const VkMemoryBarrier* pMemoryBarriers,
2683 uint32_t bufferMemoryBarrierCount,
2684 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2685 uint32_t imageMemoryBarrierCount,
2686 const VkImageMemoryBarrier* pImageMemoryBarriers)
2687 {
2688 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2689 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2690
2691 for (unsigned i = 0; i < eventCount; ++i) {
2692 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
2693 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2694
2695 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2696
2697 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
2698
2699 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
2700 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
2701 radeon_emit(cs, va);
2702 radeon_emit(cs, va >> 32);
2703 radeon_emit(cs, 1); /* reference value */
2704 radeon_emit(cs, 0xffffffff); /* mask */
2705 radeon_emit(cs, 4); /* poll interval */
2706
2707 assert(cmd_buffer->cs->cdw <= cdw_max);
2708 }
2709
2710
2711 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2712 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2713
2714 radv_handle_image_transition(cmd_buffer, image,
2715 pImageMemoryBarriers[i].oldLayout,
2716 pImageMemoryBarriers[i].newLayout,
2717 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2718 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2719 pImageMemoryBarriers[i].subresourceRange,
2720 0);
2721 }
2722
2723 /* TODO: figure out how to do memory barriers without waiting */
2724 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
2725 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2726 RADV_CMD_FLAG_INV_VMEM_L1 |
2727 RADV_CMD_FLAG_INV_SMEM_L1;
2728 }