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radv: update ZRANGE_PRECISION in radv_update_bound_fast_clear_ds()
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safely call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo, 8);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 cmd_buffer->ring_offsets_idx = -1;
314
315 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
316 cmd_buffer->descriptors[i].dirty = 0;
317 cmd_buffer->descriptors[i].valid = 0;
318 cmd_buffer->descriptors[i].push_dirty = false;
319 }
320
321 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
322 void *fence_ptr;
323 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
324 &cmd_buffer->gfx9_fence_offset,
325 &fence_ptr);
326 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
327 }
328
329 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
330
331 return cmd_buffer->record_result;
332 }
333
334 static bool
335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
336 uint64_t min_needed)
337 {
338 uint64_t new_size;
339 struct radeon_winsys_bo *bo;
340 struct radv_cmd_buffer_upload *upload;
341 struct radv_device *device = cmd_buffer->device;
342
343 new_size = MAX2(min_needed, 16 * 1024);
344 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
345
346 bo = device->ws->buffer_create(device->ws,
347 new_size, 4096,
348 RADEON_DOMAIN_GTT,
349 RADEON_FLAG_CPU_ACCESS|
350 RADEON_FLAG_NO_INTERPROCESS_SHARING |
351 RADEON_FLAG_32BIT);
352
353 if (!bo) {
354 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
355 return false;
356 }
357
358 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
359 if (cmd_buffer->upload.upload_bo) {
360 upload = malloc(sizeof(*upload));
361
362 if (!upload) {
363 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
364 device->ws->buffer_destroy(bo);
365 return false;
366 }
367
368 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
369 list_add(&upload->list, &cmd_buffer->upload.list);
370 }
371
372 cmd_buffer->upload.upload_bo = bo;
373 cmd_buffer->upload.size = new_size;
374 cmd_buffer->upload.offset = 0;
375 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
376
377 if (!cmd_buffer->upload.map) {
378 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
379 return false;
380 }
381
382 return true;
383 }
384
385 bool
386 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
387 unsigned size,
388 unsigned alignment,
389 unsigned *out_offset,
390 void **ptr)
391 {
392 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
393 if (offset + size > cmd_buffer->upload.size) {
394 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
395 return false;
396 offset = 0;
397 }
398
399 *out_offset = offset;
400 *ptr = cmd_buffer->upload.map + offset;
401
402 cmd_buffer->upload.offset = offset + size;
403 return true;
404 }
405
406 bool
407 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
408 unsigned size, unsigned alignment,
409 const void *data, unsigned *out_offset)
410 {
411 uint8_t *ptr;
412
413 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
414 out_offset, (void **)&ptr))
415 return false;
416
417 if (ptr)
418 memcpy(ptr, data, size);
419
420 return true;
421 }
422
423 static void
424 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
425 unsigned count, const uint32_t *data)
426 {
427 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
428 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
429 S_370_WR_CONFIRM(1) |
430 S_370_ENGINE_SEL(V_370_ME));
431 radeon_emit(cs, va);
432 radeon_emit(cs, va >> 32);
433 radeon_emit_array(cs, data, count);
434 }
435
436 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
437 {
438 struct radv_device *device = cmd_buffer->device;
439 struct radeon_winsys_cs *cs = cmd_buffer->cs;
440 uint64_t va;
441
442 va = radv_buffer_get_va(device->trace_bo);
443 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
444 va += 4;
445
446 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
447
448 ++cmd_buffer->state.trace_id;
449 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
450 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
451 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
452 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
453 }
454
455 static void
456 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
457 enum radv_cmd_flush_bits flags)
458 {
459 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
460 uint32_t *ptr = NULL;
461 uint64_t va = 0;
462
463 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
464 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
465
466 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
467 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
468 cmd_buffer->gfx9_fence_offset;
469 ptr = &cmd_buffer->gfx9_fence_idx;
470 }
471
472 /* Force wait for graphics or compute engines to be idle. */
473 si_cs_emit_cache_flush(cmd_buffer->cs,
474 cmd_buffer->device->physical_device->rad_info.chip_class,
475 ptr, va,
476 radv_cmd_buffer_uses_mec(cmd_buffer),
477 flags);
478 }
479
480 if (unlikely(cmd_buffer->device->trace_bo))
481 radv_cmd_buffer_trace_emit(cmd_buffer);
482 }
483
484 static void
485 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
486 struct radv_pipeline *pipeline, enum ring_type ring)
487 {
488 struct radv_device *device = cmd_buffer->device;
489 struct radeon_winsys_cs *cs = cmd_buffer->cs;
490 uint32_t data[2];
491 uint64_t va;
492
493 va = radv_buffer_get_va(device->trace_bo);
494
495 switch (ring) {
496 case RING_GFX:
497 va += 8;
498 break;
499 case RING_COMPUTE:
500 va += 16;
501 break;
502 default:
503 assert(!"invalid ring type");
504 }
505
506 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
507 cmd_buffer->cs, 6);
508
509 data[0] = (uintptr_t)pipeline;
510 data[1] = (uintptr_t)pipeline >> 32;
511
512 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
513 radv_emit_write_data_packet(cs, va, 2, data);
514 }
515
516 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
517 VkPipelineBindPoint bind_point,
518 struct radv_descriptor_set *set,
519 unsigned idx)
520 {
521 struct radv_descriptor_state *descriptors_state =
522 radv_get_descriptors_state(cmd_buffer, bind_point);
523
524 descriptors_state->sets[idx] = set;
525 if (set)
526 descriptors_state->valid |= (1u << idx);
527 else
528 descriptors_state->valid &= ~(1u << idx);
529 descriptors_state->dirty |= (1u << idx);
530 }
531
532 static void
533 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
534 VkPipelineBindPoint bind_point)
535 {
536 struct radv_descriptor_state *descriptors_state =
537 radv_get_descriptors_state(cmd_buffer, bind_point);
538 struct radv_device *device = cmd_buffer->device;
539 struct radeon_winsys_cs *cs = cmd_buffer->cs;
540 uint32_t data[MAX_SETS * 2] = {};
541 uint64_t va;
542 unsigned i;
543 va = radv_buffer_get_va(device->trace_bo) + 24;
544
545 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
546 cmd_buffer->cs, 4 + MAX_SETS * 2);
547
548 for_each_bit(i, descriptors_state->valid) {
549 struct radv_descriptor_set *set = descriptors_state->sets[i];
550 data[i * 2] = (uintptr_t)set;
551 data[i * 2 + 1] = (uintptr_t)set >> 32;
552 }
553
554 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
555 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
556 }
557
558 struct radv_userdata_info *
559 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
560 gl_shader_stage stage,
561 int idx)
562 {
563 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
564 return &shader->info.user_sgprs_locs.shader_data[idx];
565 }
566
567 static void
568 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
569 struct radv_pipeline *pipeline,
570 gl_shader_stage stage,
571 int idx, uint64_t va)
572 {
573 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
574 uint32_t base_reg = pipeline->user_data_0[stage];
575 if (loc->sgpr_idx == -1)
576 return;
577
578 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
579 assert(!loc->indirect);
580
581 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
582 base_reg + loc->sgpr_idx * 4, va, false);
583 }
584
585 static void
586 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
587 struct radv_pipeline *pipeline,
588 struct radv_descriptor_state *descriptors_state,
589 gl_shader_stage stage)
590 {
591 struct radv_device *device = cmd_buffer->device;
592 struct radeon_winsys_cs *cs = cmd_buffer->cs;
593 uint32_t sh_base = pipeline->user_data_0[stage];
594 struct radv_userdata_locations *locs =
595 &pipeline->shaders[stage]->info.user_sgprs_locs;
596 unsigned mask;
597
598 mask = descriptors_state->dirty & descriptors_state->valid;
599
600 for (int i = 0; i < MAX_SETS; i++) {
601 struct radv_userdata_info *loc = &locs->descriptor_sets[i];
602 if (loc->sgpr_idx != -1 && !loc->indirect)
603 continue;
604 mask &= ~(1 << i);
605 }
606
607 while (mask) {
608 int start, count;
609
610 u_bit_scan_consecutive_range(&mask, &start, &count);
611
612 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
613 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
614
615 radv_emit_shader_pointer_head(cs, sh_offset, count,
616 HAVE_32BIT_POINTERS);
617 for (int i = 0; i < count; i++) {
618 struct radv_descriptor_set *set =
619 descriptors_state->sets[start + i];
620
621 radv_emit_shader_pointer_body(device, cs, set->va,
622 HAVE_32BIT_POINTERS);
623 }
624 }
625 }
626
627 static void
628 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
629 struct radv_pipeline *pipeline)
630 {
631 int num_samples = pipeline->graphics.ms.num_samples;
632 struct radv_multisample_state *ms = &pipeline->graphics.ms;
633 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
634
635 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
636 cmd_buffer->sample_positions_needed = true;
637
638 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
639 return;
640
641 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
642 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
643 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
644
645 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
646
647 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
648
649 /* GFX9: Flush DFSM when the AA mode changes. */
650 if (cmd_buffer->device->dfsm_allowed) {
651 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
652 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
653 }
654 }
655
656 static void
657 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
658 struct radv_shader_variant *shader)
659 {
660 uint64_t va;
661
662 if (!shader)
663 return;
664
665 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
666
667 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
668 }
669
670 static void
671 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
672 struct radv_pipeline *pipeline,
673 bool vertex_stage_only)
674 {
675 struct radv_cmd_state *state = &cmd_buffer->state;
676 uint32_t mask = state->prefetch_L2_mask;
677
678 if (vertex_stage_only) {
679 /* Fast prefetch path for starting draws as soon as possible.
680 */
681 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
682 RADV_PREFETCH_VBO_DESCRIPTORS);
683 }
684
685 if (mask & RADV_PREFETCH_VS)
686 radv_emit_shader_prefetch(cmd_buffer,
687 pipeline->shaders[MESA_SHADER_VERTEX]);
688
689 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
690 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
691
692 if (mask & RADV_PREFETCH_TCS)
693 radv_emit_shader_prefetch(cmd_buffer,
694 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
695
696 if (mask & RADV_PREFETCH_TES)
697 radv_emit_shader_prefetch(cmd_buffer,
698 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
699
700 if (mask & RADV_PREFETCH_GS) {
701 radv_emit_shader_prefetch(cmd_buffer,
702 pipeline->shaders[MESA_SHADER_GEOMETRY]);
703 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
704 }
705
706 if (mask & RADV_PREFETCH_PS)
707 radv_emit_shader_prefetch(cmd_buffer,
708 pipeline->shaders[MESA_SHADER_FRAGMENT]);
709
710 state->prefetch_L2_mask &= ~mask;
711 }
712
713 static void
714 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
715 {
716 if (!cmd_buffer->device->physical_device->rbplus_allowed)
717 return;
718
719 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
720 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
721 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
722
723 unsigned sx_ps_downconvert = 0;
724 unsigned sx_blend_opt_epsilon = 0;
725 unsigned sx_blend_opt_control = 0;
726
727 for (unsigned i = 0; i < subpass->color_count; ++i) {
728 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
729 continue;
730
731 int idx = subpass->color_attachments[i].attachment;
732 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
733
734 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
735 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
736 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
737 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
738
739 bool has_alpha, has_rgb;
740
741 /* Set if RGB and A are present. */
742 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
743
744 if (format == V_028C70_COLOR_8 ||
745 format == V_028C70_COLOR_16 ||
746 format == V_028C70_COLOR_32)
747 has_rgb = !has_alpha;
748 else
749 has_rgb = true;
750
751 /* Check the colormask and export format. */
752 if (!(colormask & 0x7))
753 has_rgb = false;
754 if (!(colormask & 0x8))
755 has_alpha = false;
756
757 if (spi_format == V_028714_SPI_SHADER_ZERO) {
758 has_rgb = false;
759 has_alpha = false;
760 }
761
762 /* Disable value checking for disabled channels. */
763 if (!has_rgb)
764 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
765 if (!has_alpha)
766 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
767
768 /* Enable down-conversion for 32bpp and smaller formats. */
769 switch (format) {
770 case V_028C70_COLOR_8:
771 case V_028C70_COLOR_8_8:
772 case V_028C70_COLOR_8_8_8_8:
773 /* For 1 and 2-channel formats, use the superset thereof. */
774 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
775 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
776 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
777 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
778 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
779 }
780 break;
781
782 case V_028C70_COLOR_5_6_5:
783 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
784 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
785 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
786 }
787 break;
788
789 case V_028C70_COLOR_1_5_5_5:
790 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
791 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
792 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
793 }
794 break;
795
796 case V_028C70_COLOR_4_4_4_4:
797 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
798 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
799 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
800 }
801 break;
802
803 case V_028C70_COLOR_32:
804 if (swap == V_028C70_SWAP_STD &&
805 spi_format == V_028714_SPI_SHADER_32_R)
806 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
807 else if (swap == V_028C70_SWAP_ALT_REV &&
808 spi_format == V_028714_SPI_SHADER_32_AR)
809 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
810 break;
811
812 case V_028C70_COLOR_16:
813 case V_028C70_COLOR_16_16:
814 /* For 1-channel formats, use the superset thereof. */
815 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
816 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
817 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
818 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
819 if (swap == V_028C70_SWAP_STD ||
820 swap == V_028C70_SWAP_STD_REV)
821 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
822 else
823 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
824 }
825 break;
826
827 case V_028C70_COLOR_10_11_11:
828 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
829 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
830 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
831 }
832 break;
833
834 case V_028C70_COLOR_2_10_10_10:
835 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
836 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
837 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
838 }
839 break;
840 }
841 }
842
843 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
844 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
845 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
846 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
847 }
848
849 static void
850 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
851 {
852 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
853
854 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
855 return;
856
857 radv_update_multisample_state(cmd_buffer, pipeline);
858
859 cmd_buffer->scratch_size_needed =
860 MAX2(cmd_buffer->scratch_size_needed,
861 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
862
863 if (!cmd_buffer->state.emitted_pipeline ||
864 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
865 pipeline->graphics.can_use_guardband)
866 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
867
868 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
869
870 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
871 if (!pipeline->shaders[i])
872 continue;
873
874 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
875 pipeline->shaders[i]->bo, 8);
876 }
877
878 if (radv_pipeline_has_gs(pipeline))
879 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
880 pipeline->gs_copy_shader->bo, 8);
881
882 if (unlikely(cmd_buffer->device->trace_bo))
883 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
884
885 cmd_buffer->state.emitted_pipeline = pipeline;
886
887 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
888 }
889
890 static void
891 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
892 {
893 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
894 cmd_buffer->state.dynamic.viewport.viewports);
895 }
896
897 static void
898 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
899 {
900 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
901
902 si_write_scissors(cmd_buffer->cs, 0, count,
903 cmd_buffer->state.dynamic.scissor.scissors,
904 cmd_buffer->state.dynamic.viewport.viewports,
905 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
906 }
907
908 static void
909 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
910 {
911 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
912 return;
913
914 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
915 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
916 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
917 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
918 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
919 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
920 S_028214_BR_Y(rect.offset.y + rect.extent.height));
921 }
922 }
923
924 static void
925 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
926 {
927 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
928
929 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
930 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
931 }
932
933 static void
934 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
935 {
936 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
937
938 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
939 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
940 }
941
942 static void
943 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
944 {
945 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
946
947 radeon_set_context_reg_seq(cmd_buffer->cs,
948 R_028430_DB_STENCILREFMASK, 2);
949 radeon_emit(cmd_buffer->cs,
950 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
951 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
952 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
953 S_028430_STENCILOPVAL(1));
954 radeon_emit(cmd_buffer->cs,
955 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
956 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
957 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
958 S_028434_STENCILOPVAL_BF(1));
959 }
960
961 static void
962 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
963 {
964 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
965
966 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
967 fui(d->depth_bounds.min));
968 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
969 fui(d->depth_bounds.max));
970 }
971
972 static void
973 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
974 {
975 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
976 unsigned slope = fui(d->depth_bias.slope * 16.0f);
977 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
978
979
980 radeon_set_context_reg_seq(cmd_buffer->cs,
981 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
982 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
983 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
984 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
985 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
986 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
987 }
988
989 static void
990 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
991 int index,
992 struct radv_attachment_info *att,
993 struct radv_image *image,
994 VkImageLayout layout)
995 {
996 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
997 struct radv_color_buffer_info *cb = &att->cb;
998 uint32_t cb_color_info = cb->cb_color_info;
999
1000 if (!radv_layout_dcc_compressed(image, layout,
1001 radv_image_queue_family_mask(image,
1002 cmd_buffer->queue_family_index,
1003 cmd_buffer->queue_family_index))) {
1004 cb_color_info &= C_028C70_DCC_ENABLE;
1005 }
1006
1007 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1008 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1009 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1010 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1011 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1012 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1013 radeon_emit(cmd_buffer->cs, cb_color_info);
1014 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1015 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1016 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1017 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1018 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1019 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1020
1021 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1022 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1023 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1024
1025 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1026 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1027 } else {
1028 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1029 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1030 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1031 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1032 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1033 radeon_emit(cmd_buffer->cs, cb_color_info);
1034 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1035 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1036 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1037 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1038 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1039 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1040
1041 if (is_vi) { /* DCC BASE */
1042 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1043 }
1044 }
1045 }
1046
1047 static void
1048 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1049 struct radv_ds_buffer_info *ds,
1050 struct radv_image *image, VkImageLayout layout,
1051 bool requires_cond_write)
1052 {
1053 uint32_t db_z_info = ds->db_z_info;
1054 uint32_t db_z_info_reg;
1055
1056 if (!radv_image_is_tc_compat_htile(image))
1057 return;
1058
1059 if (!radv_layout_has_htile(image, layout,
1060 radv_image_queue_family_mask(image,
1061 cmd_buffer->queue_family_index,
1062 cmd_buffer->queue_family_index))) {
1063 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1064 }
1065
1066 db_z_info &= C_028040_ZRANGE_PRECISION;
1067
1068 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1069 db_z_info_reg = R_028038_DB_Z_INFO;
1070 } else {
1071 db_z_info_reg = R_028040_DB_Z_INFO;
1072 }
1073
1074 /* When we don't know the last fast clear value we need to emit a
1075 * conditional packet, otherwise we can update DB_Z_INFO directly.
1076 */
1077 if (requires_cond_write) {
1078 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1079
1080 const uint32_t write_space = 0 << 8; /* register */
1081 const uint32_t poll_space = 1 << 4; /* memory */
1082 const uint32_t function = 3 << 0; /* equal to the reference */
1083 const uint32_t options = write_space | poll_space | function;
1084 radeon_emit(cmd_buffer->cs, options);
1085
1086 /* poll address - location of the depth clear value */
1087 uint64_t va = radv_buffer_get_va(image->bo);
1088 va += image->offset + image->clear_value_offset;
1089
1090 /* In presence of stencil format, we have to adjust the base
1091 * address because the first value is the stencil clear value.
1092 */
1093 if (vk_format_is_stencil(image->vk_format))
1094 va += 4;
1095
1096 radeon_emit(cmd_buffer->cs, va);
1097 radeon_emit(cmd_buffer->cs, va >> 32);
1098
1099 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1100 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1101 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1102 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1103 radeon_emit(cmd_buffer->cs, db_z_info);
1104 } else {
1105 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1106 }
1107 }
1108
1109 static void
1110 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1111 struct radv_ds_buffer_info *ds,
1112 struct radv_image *image,
1113 VkImageLayout layout)
1114 {
1115 uint32_t db_z_info = ds->db_z_info;
1116 uint32_t db_stencil_info = ds->db_stencil_info;
1117
1118 if (!radv_layout_has_htile(image, layout,
1119 radv_image_queue_family_mask(image,
1120 cmd_buffer->queue_family_index,
1121 cmd_buffer->queue_family_index))) {
1122 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1123 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1124 }
1125
1126 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1127 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1128
1129
1130 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1131 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1132 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1133 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1134 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1135
1136 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1137 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1138 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1139 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1140 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1141 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1142 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1143 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1144 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1145 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1146 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1147
1148 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1149 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1150 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1151 } else {
1152 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1153
1154 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1155 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1156 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1157 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1158 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1159 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1160 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1161 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1162 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1163 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1164
1165 }
1166
1167 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1168 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1169
1170 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1171 ds->pa_su_poly_offset_db_fmt_cntl);
1172 }
1173
1174 /**
1175 * Update the fast clear depth/stencil values if the image is bound as a
1176 * depth/stencil buffer.
1177 */
1178 static void
1179 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1180 struct radv_image *image,
1181 VkClearDepthStencilValue ds_clear_value,
1182 VkImageAspectFlags aspects)
1183 {
1184 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1185 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1186 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1187 struct radv_attachment_info *att;
1188 uint32_t att_idx;
1189
1190 if (!framebuffer || !subpass)
1191 return;
1192
1193 att_idx = subpass->depth_stencil_attachment.attachment;
1194 if (att_idx == VK_ATTACHMENT_UNUSED)
1195 return;
1196
1197 att = &framebuffer->attachments[att_idx];
1198 if (att->attachment->image != image)
1199 return;
1200
1201 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1202 radeon_emit(cs, ds_clear_value.stencil);
1203 radeon_emit(cs, fui(ds_clear_value.depth));
1204
1205 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1206 * only needed when clearing Z to 0.0.
1207 */
1208 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1209 ds_clear_value.depth == 0.0) {
1210 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1211
1212 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1213 layout, false);
1214 }
1215 }
1216
1217 /**
1218 * Set the clear depth/stencil values to the image's metadata.
1219 */
1220 void
1221 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1222 struct radv_image *image,
1223 VkClearDepthStencilValue ds_clear_value,
1224 VkImageAspectFlags aspects)
1225 {
1226 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1227 uint64_t va = radv_buffer_get_va(image->bo);
1228
1229 va += image->offset + image->clear_value_offset;
1230
1231 assert(radv_image_has_htile(image));
1232
1233 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1234 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1235 S_370_WR_CONFIRM(1) |
1236 S_370_ENGINE_SEL(V_370_PFP));
1237 radeon_emit(cs, va);
1238 radeon_emit(cs, va >> 32);
1239 radeon_emit(cs, ds_clear_value.stencil);
1240 radeon_emit(cs, fui(ds_clear_value.depth));
1241
1242 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1243 aspects);
1244 }
1245
1246 /**
1247 * Load the clear depth/stencil values from the image's metadata.
1248 */
1249 static void
1250 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1251 struct radv_image *image)
1252 {
1253 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1254 uint64_t va = radv_buffer_get_va(image->bo);
1255
1256 va += image->offset + image->clear_value_offset;
1257
1258 if (!radv_image_has_htile(image))
1259 return;
1260
1261 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1262 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1263 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1264 COPY_DATA_COUNT_SEL);
1265 radeon_emit(cs, va);
1266 radeon_emit(cs, va >> 32);
1267 radeon_emit(cs, R_028028_DB_STENCIL_CLEAR >> 2);
1268 radeon_emit(cs, 0);
1269
1270 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1271 radeon_emit(cs, 0);
1272 }
1273
1274 /*
1275 * With DCC some colors don't require CMASK elimination before being
1276 * used as a texture. This sets a predicate value to determine if the
1277 * cmask eliminate is required.
1278 */
1279 void
1280 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1281 struct radv_image *image,
1282 bool value)
1283 {
1284 uint64_t pred_val = value;
1285 uint64_t va = radv_buffer_get_va(image->bo);
1286 va += image->offset + image->dcc_pred_offset;
1287
1288 assert(radv_image_has_dcc(image));
1289
1290 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1291 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1292 S_370_WR_CONFIRM(1) |
1293 S_370_ENGINE_SEL(V_370_PFP));
1294 radeon_emit(cmd_buffer->cs, va);
1295 radeon_emit(cmd_buffer->cs, va >> 32);
1296 radeon_emit(cmd_buffer->cs, pred_val);
1297 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1298 }
1299
1300 /**
1301 * Update the fast clear color values if the image is bound as a color buffer.
1302 */
1303 static void
1304 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1305 struct radv_image *image,
1306 int cb_idx,
1307 uint32_t color_values[2])
1308 {
1309 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1310 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1311 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1312 struct radv_attachment_info *att;
1313 uint32_t att_idx;
1314
1315 if (!framebuffer || !subpass)
1316 return;
1317
1318 att_idx = subpass->color_attachments[cb_idx].attachment;
1319 if (att_idx == VK_ATTACHMENT_UNUSED)
1320 return;
1321
1322 att = &framebuffer->attachments[att_idx];
1323 if (att->attachment->image != image)
1324 return;
1325
1326 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1327 radeon_emit(cs, color_values[0]);
1328 radeon_emit(cs, color_values[1]);
1329 }
1330
1331 /**
1332 * Set the clear color values to the image's metadata.
1333 */
1334 void
1335 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1336 struct radv_image *image,
1337 int cb_idx,
1338 uint32_t color_values[2])
1339 {
1340 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1341 uint64_t va = radv_buffer_get_va(image->bo);
1342
1343 va += image->offset + image->clear_value_offset;
1344
1345 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1346
1347 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1348 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1349 S_370_WR_CONFIRM(1) |
1350 S_370_ENGINE_SEL(V_370_PFP));
1351 radeon_emit(cs, va);
1352 radeon_emit(cs, va >> 32);
1353 radeon_emit(cs, color_values[0]);
1354 radeon_emit(cs, color_values[1]);
1355
1356 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1357 color_values);
1358 }
1359
1360 /**
1361 * Load the clear color values from the image's metadata.
1362 */
1363 static void
1364 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1365 struct radv_image *image,
1366 int cb_idx)
1367 {
1368 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1369 uint64_t va = radv_buffer_get_va(image->bo);
1370
1371 va += image->offset + image->clear_value_offset;
1372
1373 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1374 return;
1375
1376 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1377
1378 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1379 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1380 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1381 COPY_DATA_COUNT_SEL);
1382 radeon_emit(cs, va);
1383 radeon_emit(cs, va >> 32);
1384 radeon_emit(cs, reg >> 2);
1385 radeon_emit(cs, 0);
1386
1387 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1388 radeon_emit(cs, 0);
1389 }
1390
1391 static void
1392 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1393 {
1394 int i;
1395 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1396 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1397
1398 /* this may happen for inherited secondary recording */
1399 if (!framebuffer)
1400 return;
1401
1402 for (i = 0; i < 8; ++i) {
1403 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1404 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1405 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1406 continue;
1407 }
1408
1409 int idx = subpass->color_attachments[i].attachment;
1410 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1411 struct radv_image *image = att->attachment->image;
1412 VkImageLayout layout = subpass->color_attachments[i].layout;
1413
1414 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1415
1416 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1417 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1418
1419 radv_load_color_clear_metadata(cmd_buffer, image, i);
1420 }
1421
1422 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1423 int idx = subpass->depth_stencil_attachment.attachment;
1424 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1425 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1426 struct radv_image *image = att->attachment->image;
1427 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1428 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1429 cmd_buffer->queue_family_index,
1430 cmd_buffer->queue_family_index);
1431 /* We currently don't support writing decompressed HTILE */
1432 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1433 radv_layout_is_htile_compressed(image, layout, queue_mask));
1434
1435 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1436
1437 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1438 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1439 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1440 }
1441 radv_load_ds_clear_metadata(cmd_buffer, image);
1442 } else {
1443 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1444 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1445 else
1446 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1447
1448 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1449 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1450 }
1451 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1452 S_028208_BR_X(framebuffer->width) |
1453 S_028208_BR_Y(framebuffer->height));
1454
1455 if (cmd_buffer->device->dfsm_allowed) {
1456 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1457 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1458 }
1459
1460 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1461 }
1462
1463 static void
1464 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1465 {
1466 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1467 struct radv_cmd_state *state = &cmd_buffer->state;
1468
1469 if (state->index_type != state->last_index_type) {
1470 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1471 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1472 2, state->index_type);
1473 } else {
1474 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1475 radeon_emit(cs, state->index_type);
1476 }
1477
1478 state->last_index_type = state->index_type;
1479 }
1480
1481 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1482 radeon_emit(cs, state->index_va);
1483 radeon_emit(cs, state->index_va >> 32);
1484
1485 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1486 radeon_emit(cs, state->max_index_count);
1487
1488 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1489 }
1490
1491 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1492 {
1493 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1494 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1495 uint32_t pa_sc_mode_cntl_1 =
1496 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1497 uint32_t db_count_control;
1498
1499 if(!cmd_buffer->state.active_occlusion_queries) {
1500 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1501 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1502 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1503 has_perfect_queries) {
1504 /* Re-enable out-of-order rasterization if the
1505 * bound pipeline supports it and if it's has
1506 * been disabled before starting any perfect
1507 * occlusion queries.
1508 */
1509 radeon_set_context_reg(cmd_buffer->cs,
1510 R_028A4C_PA_SC_MODE_CNTL_1,
1511 pa_sc_mode_cntl_1);
1512 }
1513 db_count_control = 0;
1514 } else {
1515 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1516 }
1517 } else {
1518 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1519 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1520
1521 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1522 db_count_control =
1523 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1524 S_028004_SAMPLE_RATE(sample_rate) |
1525 S_028004_ZPASS_ENABLE(1) |
1526 S_028004_SLICE_EVEN_ENABLE(1) |
1527 S_028004_SLICE_ODD_ENABLE(1);
1528
1529 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1530 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1531 has_perfect_queries) {
1532 /* If the bound pipeline has enabled
1533 * out-of-order rasterization, we should
1534 * disable it before starting any perfect
1535 * occlusion queries.
1536 */
1537 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1538
1539 radeon_set_context_reg(cmd_buffer->cs,
1540 R_028A4C_PA_SC_MODE_CNTL_1,
1541 pa_sc_mode_cntl_1);
1542 }
1543 } else {
1544 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1545 S_028004_SAMPLE_RATE(sample_rate);
1546 }
1547 }
1548
1549 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1550 }
1551
1552 static void
1553 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1554 {
1555 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1556
1557 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1558 radv_emit_viewport(cmd_buffer);
1559
1560 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1561 !cmd_buffer->device->physical_device->has_scissor_bug)
1562 radv_emit_scissor(cmd_buffer);
1563
1564 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1565 radv_emit_line_width(cmd_buffer);
1566
1567 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1568 radv_emit_blend_constants(cmd_buffer);
1569
1570 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1571 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1572 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1573 radv_emit_stencil(cmd_buffer);
1574
1575 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1576 radv_emit_depth_bounds(cmd_buffer);
1577
1578 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1579 radv_emit_depth_bias(cmd_buffer);
1580
1581 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1582 radv_emit_discard_rectangle(cmd_buffer);
1583
1584 cmd_buffer->state.dirty &= ~states;
1585 }
1586
1587 static void
1588 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1589 VkPipelineBindPoint bind_point)
1590 {
1591 struct radv_descriptor_state *descriptors_state =
1592 radv_get_descriptors_state(cmd_buffer, bind_point);
1593 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1594 unsigned bo_offset;
1595
1596 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1597 set->mapped_ptr,
1598 &bo_offset))
1599 return;
1600
1601 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1602 set->va += bo_offset;
1603 }
1604
1605 static void
1606 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1607 VkPipelineBindPoint bind_point)
1608 {
1609 struct radv_descriptor_state *descriptors_state =
1610 radv_get_descriptors_state(cmd_buffer, bind_point);
1611 uint32_t size = MAX_SETS * 2 * 4;
1612 uint32_t offset;
1613 void *ptr;
1614
1615 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1616 256, &offset, &ptr))
1617 return;
1618
1619 for (unsigned i = 0; i < MAX_SETS; i++) {
1620 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1621 uint64_t set_va = 0;
1622 struct radv_descriptor_set *set = descriptors_state->sets[i];
1623 if (descriptors_state->valid & (1u << i))
1624 set_va = set->va;
1625 uptr[0] = set_va & 0xffffffff;
1626 uptr[1] = set_va >> 32;
1627 }
1628
1629 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1630 va += offset;
1631
1632 if (cmd_buffer->state.pipeline) {
1633 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1634 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1635 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1636
1637 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1638 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1639 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1640
1641 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1642 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1643 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1644
1645 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1646 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1647 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1648
1649 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1650 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1651 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1652 }
1653
1654 if (cmd_buffer->state.compute_pipeline)
1655 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1656 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1657 }
1658
1659 static void
1660 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1661 VkShaderStageFlags stages)
1662 {
1663 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1664 VK_PIPELINE_BIND_POINT_COMPUTE :
1665 VK_PIPELINE_BIND_POINT_GRAPHICS;
1666 struct radv_descriptor_state *descriptors_state =
1667 radv_get_descriptors_state(cmd_buffer, bind_point);
1668
1669 if (!descriptors_state->dirty)
1670 return;
1671
1672 if (descriptors_state->push_dirty)
1673 radv_flush_push_descriptors(cmd_buffer, bind_point);
1674
1675 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1676 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1677 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1678 }
1679
1680 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1681 cmd_buffer->cs,
1682 MAX_SETS * MESA_SHADER_STAGES * 4);
1683
1684 if (cmd_buffer->state.pipeline) {
1685 radv_foreach_stage(stage, stages) {
1686 if (!cmd_buffer->state.pipeline->shaders[stage])
1687 continue;
1688
1689 radv_emit_descriptor_pointers(cmd_buffer,
1690 cmd_buffer->state.pipeline,
1691 descriptors_state, stage);
1692 }
1693 }
1694
1695 if (cmd_buffer->state.compute_pipeline &&
1696 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1697 radv_emit_descriptor_pointers(cmd_buffer,
1698 cmd_buffer->state.compute_pipeline,
1699 descriptors_state,
1700 MESA_SHADER_COMPUTE);
1701 }
1702
1703 descriptors_state->dirty = 0;
1704 descriptors_state->push_dirty = false;
1705
1706 if (unlikely(cmd_buffer->device->trace_bo))
1707 radv_save_descriptors(cmd_buffer, bind_point);
1708
1709 assert(cmd_buffer->cs->cdw <= cdw_max);
1710 }
1711
1712 static void
1713 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1714 VkShaderStageFlags stages)
1715 {
1716 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1717 ? cmd_buffer->state.compute_pipeline
1718 : cmd_buffer->state.pipeline;
1719 struct radv_pipeline_layout *layout = pipeline->layout;
1720 struct radv_shader_variant *shader, *prev_shader;
1721 unsigned offset;
1722 void *ptr;
1723 uint64_t va;
1724
1725 stages &= cmd_buffer->push_constant_stages;
1726 if (!stages ||
1727 (!layout->push_constant_size && !layout->dynamic_offset_count))
1728 return;
1729
1730 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1731 16 * layout->dynamic_offset_count,
1732 256, &offset, &ptr))
1733 return;
1734
1735 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1736 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1737 16 * layout->dynamic_offset_count);
1738
1739 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1740 va += offset;
1741
1742 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1743 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1744
1745 prev_shader = NULL;
1746 radv_foreach_stage(stage, stages) {
1747 shader = radv_get_shader(pipeline, stage);
1748
1749 /* Avoid redundantly emitting the address for merged stages. */
1750 if (shader && shader != prev_shader) {
1751 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1752 AC_UD_PUSH_CONSTANTS, va);
1753
1754 prev_shader = shader;
1755 }
1756 }
1757
1758 cmd_buffer->push_constant_stages &= ~stages;
1759 assert(cmd_buffer->cs->cdw <= cdw_max);
1760 }
1761
1762 static void
1763 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1764 bool pipeline_is_dirty)
1765 {
1766 if ((pipeline_is_dirty ||
1767 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1768 cmd_buffer->state.pipeline->vertex_elements.count &&
1769 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1770 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1771 unsigned vb_offset;
1772 void *vb_ptr;
1773 uint32_t i = 0;
1774 uint32_t count = velems->count;
1775 uint64_t va;
1776
1777 /* allocate some descriptor state for vertex buffers */
1778 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1779 &vb_offset, &vb_ptr))
1780 return;
1781
1782 for (i = 0; i < count; i++) {
1783 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1784 uint32_t offset;
1785 int vb = velems->binding[i];
1786 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1787 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1788
1789 va = radv_buffer_get_va(buffer->bo);
1790
1791 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1792 va += offset + buffer->offset;
1793 desc[0] = va;
1794 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1795 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1796 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1797 else
1798 desc[2] = buffer->size - offset;
1799 desc[3] = velems->rsrc_word3[i];
1800 }
1801
1802 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1803 va += vb_offset;
1804
1805 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1806 AC_UD_VS_VERTEX_BUFFERS, va);
1807
1808 cmd_buffer->state.vb_va = va;
1809 cmd_buffer->state.vb_size = count * 16;
1810 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1811 }
1812 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1813 }
1814
1815 static void
1816 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1817 {
1818 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1819 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1820 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1821 }
1822
1823 static void
1824 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1825 bool instanced_draw, bool indirect_draw,
1826 uint32_t draw_vertex_count)
1827 {
1828 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1829 struct radv_cmd_state *state = &cmd_buffer->state;
1830 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1831 uint32_t ia_multi_vgt_param;
1832 int32_t primitive_reset_en;
1833
1834 /* Draw state. */
1835 ia_multi_vgt_param =
1836 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1837 indirect_draw, draw_vertex_count);
1838
1839 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1840 if (info->chip_class >= GFX9) {
1841 radeon_set_uconfig_reg_idx(cs,
1842 R_030960_IA_MULTI_VGT_PARAM,
1843 4, ia_multi_vgt_param);
1844 } else if (info->chip_class >= CIK) {
1845 radeon_set_context_reg_idx(cs,
1846 R_028AA8_IA_MULTI_VGT_PARAM,
1847 1, ia_multi_vgt_param);
1848 } else {
1849 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1850 ia_multi_vgt_param);
1851 }
1852 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1853 }
1854
1855 /* Primitive restart. */
1856 primitive_reset_en =
1857 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1858
1859 if (primitive_reset_en != state->last_primitive_reset_en) {
1860 state->last_primitive_reset_en = primitive_reset_en;
1861 if (info->chip_class >= GFX9) {
1862 radeon_set_uconfig_reg(cs,
1863 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1864 primitive_reset_en);
1865 } else {
1866 radeon_set_context_reg(cs,
1867 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1868 primitive_reset_en);
1869 }
1870 }
1871
1872 if (primitive_reset_en) {
1873 uint32_t primitive_reset_index =
1874 state->index_type ? 0xffffffffu : 0xffffu;
1875
1876 if (primitive_reset_index != state->last_primitive_reset_index) {
1877 radeon_set_context_reg(cs,
1878 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1879 primitive_reset_index);
1880 state->last_primitive_reset_index = primitive_reset_index;
1881 }
1882 }
1883 }
1884
1885 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1886 VkPipelineStageFlags src_stage_mask)
1887 {
1888 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1889 VK_PIPELINE_STAGE_TRANSFER_BIT |
1890 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1891 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1892 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1893 }
1894
1895 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1896 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1897 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1898 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1899 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1900 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1901 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1902 VK_PIPELINE_STAGE_TRANSFER_BIT |
1903 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1904 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1905 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1906 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1907 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1908 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1909 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1910 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1911 }
1912 }
1913
1914 static enum radv_cmd_flush_bits
1915 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1916 VkAccessFlags src_flags)
1917 {
1918 enum radv_cmd_flush_bits flush_bits = 0;
1919 uint32_t b;
1920 for_each_bit(b, src_flags) {
1921 switch ((VkAccessFlagBits)(1 << b)) {
1922 case VK_ACCESS_SHADER_WRITE_BIT:
1923 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1924 break;
1925 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1926 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1927 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1928 break;
1929 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1930 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1931 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1932 break;
1933 case VK_ACCESS_TRANSFER_WRITE_BIT:
1934 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1935 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1936 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1937 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1938 RADV_CMD_FLAG_INV_GLOBAL_L2;
1939 break;
1940 default:
1941 break;
1942 }
1943 }
1944 return flush_bits;
1945 }
1946
1947 static enum radv_cmd_flush_bits
1948 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1949 VkAccessFlags dst_flags,
1950 struct radv_image *image)
1951 {
1952 enum radv_cmd_flush_bits flush_bits = 0;
1953 uint32_t b;
1954 for_each_bit(b, dst_flags) {
1955 switch ((VkAccessFlagBits)(1 << b)) {
1956 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1957 case VK_ACCESS_INDEX_READ_BIT:
1958 break;
1959 case VK_ACCESS_UNIFORM_READ_BIT:
1960 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1961 break;
1962 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1963 case VK_ACCESS_SHADER_READ_BIT:
1964 case VK_ACCESS_TRANSFER_READ_BIT:
1965 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1966 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1967 RADV_CMD_FLAG_INV_GLOBAL_L2;
1968 break;
1969 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1970 /* TODO: change to image && when the image gets passed
1971 * through from the subpass. */
1972 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1973 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1974 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1975 break;
1976 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1977 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1978 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1979 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1980 break;
1981 default:
1982 break;
1983 }
1984 }
1985 return flush_bits;
1986 }
1987
1988 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1989 {
1990 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1991 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1992 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1993 NULL);
1994 }
1995
1996 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1997 VkAttachmentReference att)
1998 {
1999 unsigned idx = att.attachment;
2000 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2001 VkImageSubresourceRange range;
2002 range.aspectMask = 0;
2003 range.baseMipLevel = view->base_mip;
2004 range.levelCount = 1;
2005 range.baseArrayLayer = view->base_layer;
2006 range.layerCount = cmd_buffer->state.framebuffer->layers;
2007
2008 radv_handle_image_transition(cmd_buffer,
2009 view->image,
2010 cmd_buffer->state.attachments[idx].current_layout,
2011 att.layout, 0, 0, &range,
2012 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2013
2014 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2015
2016
2017 }
2018
2019 void
2020 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2021 const struct radv_subpass *subpass, bool transitions)
2022 {
2023 if (transitions) {
2024 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2025
2026 for (unsigned i = 0; i < subpass->color_count; ++i) {
2027 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2028 radv_handle_subpass_image_transition(cmd_buffer,
2029 subpass->color_attachments[i]);
2030 }
2031
2032 for (unsigned i = 0; i < subpass->input_count; ++i) {
2033 radv_handle_subpass_image_transition(cmd_buffer,
2034 subpass->input_attachments[i]);
2035 }
2036
2037 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2038 radv_handle_subpass_image_transition(cmd_buffer,
2039 subpass->depth_stencil_attachment);
2040 }
2041 }
2042
2043 cmd_buffer->state.subpass = subpass;
2044
2045 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2046 }
2047
2048 static VkResult
2049 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2050 struct radv_render_pass *pass,
2051 const VkRenderPassBeginInfo *info)
2052 {
2053 struct radv_cmd_state *state = &cmd_buffer->state;
2054
2055 if (pass->attachment_count == 0) {
2056 state->attachments = NULL;
2057 return VK_SUCCESS;
2058 }
2059
2060 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2061 pass->attachment_count *
2062 sizeof(state->attachments[0]),
2063 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2064 if (state->attachments == NULL) {
2065 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2066 return cmd_buffer->record_result;
2067 }
2068
2069 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2070 struct radv_render_pass_attachment *att = &pass->attachments[i];
2071 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2072 VkImageAspectFlags clear_aspects = 0;
2073
2074 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2075 /* color attachment */
2076 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2077 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2078 }
2079 } else {
2080 /* depthstencil attachment */
2081 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2082 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2083 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2084 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2085 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2086 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2087 }
2088 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2089 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2090 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2091 }
2092 }
2093
2094 state->attachments[i].pending_clear_aspects = clear_aspects;
2095 state->attachments[i].cleared_views = 0;
2096 if (clear_aspects && info) {
2097 assert(info->clearValueCount > i);
2098 state->attachments[i].clear_value = info->pClearValues[i];
2099 }
2100
2101 state->attachments[i].current_layout = att->initial_layout;
2102 }
2103
2104 return VK_SUCCESS;
2105 }
2106
2107 VkResult radv_AllocateCommandBuffers(
2108 VkDevice _device,
2109 const VkCommandBufferAllocateInfo *pAllocateInfo,
2110 VkCommandBuffer *pCommandBuffers)
2111 {
2112 RADV_FROM_HANDLE(radv_device, device, _device);
2113 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2114
2115 VkResult result = VK_SUCCESS;
2116 uint32_t i;
2117
2118 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2119
2120 if (!list_empty(&pool->free_cmd_buffers)) {
2121 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2122
2123 list_del(&cmd_buffer->pool_link);
2124 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2125
2126 result = radv_reset_cmd_buffer(cmd_buffer);
2127 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2128 cmd_buffer->level = pAllocateInfo->level;
2129
2130 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2131 } else {
2132 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2133 &pCommandBuffers[i]);
2134 }
2135 if (result != VK_SUCCESS)
2136 break;
2137 }
2138
2139 if (result != VK_SUCCESS) {
2140 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2141 i, pCommandBuffers);
2142
2143 /* From the Vulkan 1.0.66 spec:
2144 *
2145 * "vkAllocateCommandBuffers can be used to create multiple
2146 * command buffers. If the creation of any of those command
2147 * buffers fails, the implementation must destroy all
2148 * successfully created command buffer objects from this
2149 * command, set all entries of the pCommandBuffers array to
2150 * NULL and return the error."
2151 */
2152 memset(pCommandBuffers, 0,
2153 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2154 }
2155
2156 return result;
2157 }
2158
2159 void radv_FreeCommandBuffers(
2160 VkDevice device,
2161 VkCommandPool commandPool,
2162 uint32_t commandBufferCount,
2163 const VkCommandBuffer *pCommandBuffers)
2164 {
2165 for (uint32_t i = 0; i < commandBufferCount; i++) {
2166 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2167
2168 if (cmd_buffer) {
2169 if (cmd_buffer->pool) {
2170 list_del(&cmd_buffer->pool_link);
2171 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2172 } else
2173 radv_cmd_buffer_destroy(cmd_buffer);
2174
2175 }
2176 }
2177 }
2178
2179 VkResult radv_ResetCommandBuffer(
2180 VkCommandBuffer commandBuffer,
2181 VkCommandBufferResetFlags flags)
2182 {
2183 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2184 return radv_reset_cmd_buffer(cmd_buffer);
2185 }
2186
2187 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2188 {
2189 struct radv_device *device = cmd_buffer->device;
2190 if (device->gfx_init) {
2191 uint64_t va = radv_buffer_get_va(device->gfx_init);
2192 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2193 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2194 radeon_emit(cmd_buffer->cs, va);
2195 radeon_emit(cmd_buffer->cs, va >> 32);
2196 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2197 } else
2198 si_init_config(cmd_buffer);
2199 }
2200
2201 VkResult radv_BeginCommandBuffer(
2202 VkCommandBuffer commandBuffer,
2203 const VkCommandBufferBeginInfo *pBeginInfo)
2204 {
2205 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2206 VkResult result = VK_SUCCESS;
2207
2208 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2209 /* If the command buffer has already been resetted with
2210 * vkResetCommandBuffer, no need to do it again.
2211 */
2212 result = radv_reset_cmd_buffer(cmd_buffer);
2213 if (result != VK_SUCCESS)
2214 return result;
2215 }
2216
2217 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2218 cmd_buffer->state.last_primitive_reset_en = -1;
2219 cmd_buffer->state.last_index_type = -1;
2220 cmd_buffer->state.last_num_instances = -1;
2221 cmd_buffer->state.last_vertex_offset = -1;
2222 cmd_buffer->state.last_first_instance = -1;
2223 cmd_buffer->usage_flags = pBeginInfo->flags;
2224
2225 /* setup initial configuration into command buffer */
2226 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2227 switch (cmd_buffer->queue_family_index) {
2228 case RADV_QUEUE_GENERAL:
2229 emit_gfx_buffer_state(cmd_buffer);
2230 break;
2231 case RADV_QUEUE_COMPUTE:
2232 si_init_compute(cmd_buffer);
2233 break;
2234 case RADV_QUEUE_TRANSFER:
2235 default:
2236 break;
2237 }
2238 }
2239
2240 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2241 assert(pBeginInfo->pInheritanceInfo);
2242 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2243 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2244
2245 struct radv_subpass *subpass =
2246 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2247
2248 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2249 if (result != VK_SUCCESS)
2250 return result;
2251
2252 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2253 }
2254
2255 if (unlikely(cmd_buffer->device->trace_bo))
2256 radv_cmd_buffer_trace_emit(cmd_buffer);
2257
2258 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2259
2260 return result;
2261 }
2262
2263 void radv_CmdBindVertexBuffers(
2264 VkCommandBuffer commandBuffer,
2265 uint32_t firstBinding,
2266 uint32_t bindingCount,
2267 const VkBuffer* pBuffers,
2268 const VkDeviceSize* pOffsets)
2269 {
2270 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2271 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2272 bool changed = false;
2273
2274 /* We have to defer setting up vertex buffer since we need the buffer
2275 * stride from the pipeline. */
2276
2277 assert(firstBinding + bindingCount <= MAX_VBS);
2278 for (uint32_t i = 0; i < bindingCount; i++) {
2279 uint32_t idx = firstBinding + i;
2280
2281 if (!changed &&
2282 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2283 vb[idx].offset != pOffsets[i])) {
2284 changed = true;
2285 }
2286
2287 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2288 vb[idx].offset = pOffsets[i];
2289
2290 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2291 vb[idx].buffer->bo, 8);
2292 }
2293
2294 if (!changed) {
2295 /* No state changes. */
2296 return;
2297 }
2298
2299 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2300 }
2301
2302 void radv_CmdBindIndexBuffer(
2303 VkCommandBuffer commandBuffer,
2304 VkBuffer buffer,
2305 VkDeviceSize offset,
2306 VkIndexType indexType)
2307 {
2308 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2309 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2310
2311 if (cmd_buffer->state.index_buffer == index_buffer &&
2312 cmd_buffer->state.index_offset == offset &&
2313 cmd_buffer->state.index_type == indexType) {
2314 /* No state changes. */
2315 return;
2316 }
2317
2318 cmd_buffer->state.index_buffer = index_buffer;
2319 cmd_buffer->state.index_offset = offset;
2320 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2321 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2322 cmd_buffer->state.index_va += index_buffer->offset + offset;
2323
2324 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2325 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2326 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2327 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2328 }
2329
2330
2331 static void
2332 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2333 VkPipelineBindPoint bind_point,
2334 struct radv_descriptor_set *set, unsigned idx)
2335 {
2336 struct radeon_winsys *ws = cmd_buffer->device->ws;
2337
2338 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2339 if (!set)
2340 return;
2341
2342 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2343
2344 if (!cmd_buffer->device->use_global_bo_list) {
2345 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2346 if (set->descriptors[j])
2347 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2348 }
2349
2350 if(set->bo)
2351 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2352 }
2353
2354 void radv_CmdBindDescriptorSets(
2355 VkCommandBuffer commandBuffer,
2356 VkPipelineBindPoint pipelineBindPoint,
2357 VkPipelineLayout _layout,
2358 uint32_t firstSet,
2359 uint32_t descriptorSetCount,
2360 const VkDescriptorSet* pDescriptorSets,
2361 uint32_t dynamicOffsetCount,
2362 const uint32_t* pDynamicOffsets)
2363 {
2364 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2365 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2366 unsigned dyn_idx = 0;
2367
2368 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2369
2370 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2371 unsigned idx = i + firstSet;
2372 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2373 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2374
2375 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2376 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2377 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2378 assert(dyn_idx < dynamicOffsetCount);
2379
2380 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2381 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2382 dst[0] = va;
2383 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2384 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2385 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2386 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2387 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2388 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2389 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2390 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2391 cmd_buffer->push_constant_stages |=
2392 set->layout->dynamic_shader_stages;
2393 }
2394 }
2395 }
2396
2397 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2398 struct radv_descriptor_set *set,
2399 struct radv_descriptor_set_layout *layout,
2400 VkPipelineBindPoint bind_point)
2401 {
2402 struct radv_descriptor_state *descriptors_state =
2403 radv_get_descriptors_state(cmd_buffer, bind_point);
2404 set->size = layout->size;
2405 set->layout = layout;
2406
2407 if (descriptors_state->push_set.capacity < set->size) {
2408 size_t new_size = MAX2(set->size, 1024);
2409 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2410 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2411
2412 free(set->mapped_ptr);
2413 set->mapped_ptr = malloc(new_size);
2414
2415 if (!set->mapped_ptr) {
2416 descriptors_state->push_set.capacity = 0;
2417 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2418 return false;
2419 }
2420
2421 descriptors_state->push_set.capacity = new_size;
2422 }
2423
2424 return true;
2425 }
2426
2427 void radv_meta_push_descriptor_set(
2428 struct radv_cmd_buffer* cmd_buffer,
2429 VkPipelineBindPoint pipelineBindPoint,
2430 VkPipelineLayout _layout,
2431 uint32_t set,
2432 uint32_t descriptorWriteCount,
2433 const VkWriteDescriptorSet* pDescriptorWrites)
2434 {
2435 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2436 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2437 unsigned bo_offset;
2438
2439 assert(set == 0);
2440 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2441
2442 push_set->size = layout->set[set].layout->size;
2443 push_set->layout = layout->set[set].layout;
2444
2445 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2446 &bo_offset,
2447 (void**) &push_set->mapped_ptr))
2448 return;
2449
2450 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2451 push_set->va += bo_offset;
2452
2453 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2454 radv_descriptor_set_to_handle(push_set),
2455 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2456
2457 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2458 }
2459
2460 void radv_CmdPushDescriptorSetKHR(
2461 VkCommandBuffer commandBuffer,
2462 VkPipelineBindPoint pipelineBindPoint,
2463 VkPipelineLayout _layout,
2464 uint32_t set,
2465 uint32_t descriptorWriteCount,
2466 const VkWriteDescriptorSet* pDescriptorWrites)
2467 {
2468 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2469 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2470 struct radv_descriptor_state *descriptors_state =
2471 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2472 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2473
2474 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2475
2476 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2477 layout->set[set].layout,
2478 pipelineBindPoint))
2479 return;
2480
2481 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2482 radv_descriptor_set_to_handle(push_set),
2483 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2484
2485 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2486 descriptors_state->push_dirty = true;
2487 }
2488
2489 void radv_CmdPushDescriptorSetWithTemplateKHR(
2490 VkCommandBuffer commandBuffer,
2491 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2492 VkPipelineLayout _layout,
2493 uint32_t set,
2494 const void* pData)
2495 {
2496 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2497 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2498 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2499 struct radv_descriptor_state *descriptors_state =
2500 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2501 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2502
2503 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2504
2505 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2506 layout->set[set].layout,
2507 templ->bind_point))
2508 return;
2509
2510 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2511 descriptorUpdateTemplate, pData);
2512
2513 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2514 descriptors_state->push_dirty = true;
2515 }
2516
2517 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2518 VkPipelineLayout layout,
2519 VkShaderStageFlags stageFlags,
2520 uint32_t offset,
2521 uint32_t size,
2522 const void* pValues)
2523 {
2524 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2525 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2526 cmd_buffer->push_constant_stages |= stageFlags;
2527 }
2528
2529 VkResult radv_EndCommandBuffer(
2530 VkCommandBuffer commandBuffer)
2531 {
2532 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2533
2534 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2535 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2536 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2537 si_emit_cache_flush(cmd_buffer);
2538 }
2539
2540 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2541
2542 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2543 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2544
2545 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2546
2547 return cmd_buffer->record_result;
2548 }
2549
2550 static void
2551 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2552 {
2553 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2554
2555 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2556 return;
2557
2558 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2559
2560 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2561 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2562
2563 cmd_buffer->compute_scratch_size_needed =
2564 MAX2(cmd_buffer->compute_scratch_size_needed,
2565 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2566
2567 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2568 pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
2569
2570 if (unlikely(cmd_buffer->device->trace_bo))
2571 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2572 }
2573
2574 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2575 VkPipelineBindPoint bind_point)
2576 {
2577 struct radv_descriptor_state *descriptors_state =
2578 radv_get_descriptors_state(cmd_buffer, bind_point);
2579
2580 descriptors_state->dirty |= descriptors_state->valid;
2581 }
2582
2583 void radv_CmdBindPipeline(
2584 VkCommandBuffer commandBuffer,
2585 VkPipelineBindPoint pipelineBindPoint,
2586 VkPipeline _pipeline)
2587 {
2588 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2589 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2590
2591 switch (pipelineBindPoint) {
2592 case VK_PIPELINE_BIND_POINT_COMPUTE:
2593 if (cmd_buffer->state.compute_pipeline == pipeline)
2594 return;
2595 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2596
2597 cmd_buffer->state.compute_pipeline = pipeline;
2598 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2599 break;
2600 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2601 if (cmd_buffer->state.pipeline == pipeline)
2602 return;
2603 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2604
2605 cmd_buffer->state.pipeline = pipeline;
2606 if (!pipeline)
2607 break;
2608
2609 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2610 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2611
2612 /* the new vertex shader might not have the same user regs */
2613 cmd_buffer->state.last_first_instance = -1;
2614 cmd_buffer->state.last_vertex_offset = -1;
2615
2616 /* Prefetch all pipeline shaders at first draw time. */
2617 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2618
2619 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2620
2621 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2622 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2623 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2624 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2625
2626 if (radv_pipeline_has_tess(pipeline))
2627 cmd_buffer->tess_rings_needed = true;
2628
2629 if (radv_pipeline_has_gs(pipeline)) {
2630 struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2631 AC_UD_SCRATCH_RING_OFFSETS);
2632 if (cmd_buffer->ring_offsets_idx == -1)
2633 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2634 else if (loc->sgpr_idx != -1)
2635 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2636 }
2637 break;
2638 default:
2639 assert(!"invalid bind point");
2640 break;
2641 }
2642 }
2643
2644 void radv_CmdSetViewport(
2645 VkCommandBuffer commandBuffer,
2646 uint32_t firstViewport,
2647 uint32_t viewportCount,
2648 const VkViewport* pViewports)
2649 {
2650 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2651 struct radv_cmd_state *state = &cmd_buffer->state;
2652 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2653
2654 assert(firstViewport < MAX_VIEWPORTS);
2655 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2656
2657 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2658 viewportCount * sizeof(*pViewports));
2659
2660 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2661 }
2662
2663 void radv_CmdSetScissor(
2664 VkCommandBuffer commandBuffer,
2665 uint32_t firstScissor,
2666 uint32_t scissorCount,
2667 const VkRect2D* pScissors)
2668 {
2669 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2670 struct radv_cmd_state *state = &cmd_buffer->state;
2671 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2672
2673 assert(firstScissor < MAX_SCISSORS);
2674 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2675
2676 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2677 scissorCount * sizeof(*pScissors));
2678
2679 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2680 }
2681
2682 void radv_CmdSetLineWidth(
2683 VkCommandBuffer commandBuffer,
2684 float lineWidth)
2685 {
2686 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2687 cmd_buffer->state.dynamic.line_width = lineWidth;
2688 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2689 }
2690
2691 void radv_CmdSetDepthBias(
2692 VkCommandBuffer commandBuffer,
2693 float depthBiasConstantFactor,
2694 float depthBiasClamp,
2695 float depthBiasSlopeFactor)
2696 {
2697 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2698
2699 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2700 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2701 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2702
2703 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2704 }
2705
2706 void radv_CmdSetBlendConstants(
2707 VkCommandBuffer commandBuffer,
2708 const float blendConstants[4])
2709 {
2710 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2711
2712 memcpy(cmd_buffer->state.dynamic.blend_constants,
2713 blendConstants, sizeof(float) * 4);
2714
2715 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2716 }
2717
2718 void radv_CmdSetDepthBounds(
2719 VkCommandBuffer commandBuffer,
2720 float minDepthBounds,
2721 float maxDepthBounds)
2722 {
2723 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2724
2725 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2726 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2727
2728 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2729 }
2730
2731 void radv_CmdSetStencilCompareMask(
2732 VkCommandBuffer commandBuffer,
2733 VkStencilFaceFlags faceMask,
2734 uint32_t compareMask)
2735 {
2736 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2737
2738 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2739 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2740 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2741 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2742
2743 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2744 }
2745
2746 void radv_CmdSetStencilWriteMask(
2747 VkCommandBuffer commandBuffer,
2748 VkStencilFaceFlags faceMask,
2749 uint32_t writeMask)
2750 {
2751 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2752
2753 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2754 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2755 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2756 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2757
2758 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2759 }
2760
2761 void radv_CmdSetStencilReference(
2762 VkCommandBuffer commandBuffer,
2763 VkStencilFaceFlags faceMask,
2764 uint32_t reference)
2765 {
2766 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2767
2768 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2769 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2770 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2771 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2772
2773 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2774 }
2775
2776 void radv_CmdSetDiscardRectangleEXT(
2777 VkCommandBuffer commandBuffer,
2778 uint32_t firstDiscardRectangle,
2779 uint32_t discardRectangleCount,
2780 const VkRect2D* pDiscardRectangles)
2781 {
2782 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2783 struct radv_cmd_state *state = &cmd_buffer->state;
2784 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2785
2786 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2787 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2788
2789 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2790 pDiscardRectangles, discardRectangleCount);
2791
2792 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2793 }
2794
2795 void radv_CmdExecuteCommands(
2796 VkCommandBuffer commandBuffer,
2797 uint32_t commandBufferCount,
2798 const VkCommandBuffer* pCmdBuffers)
2799 {
2800 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2801
2802 assert(commandBufferCount > 0);
2803
2804 /* Emit pending flushes on primary prior to executing secondary */
2805 si_emit_cache_flush(primary);
2806
2807 for (uint32_t i = 0; i < commandBufferCount; i++) {
2808 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2809
2810 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2811 secondary->scratch_size_needed);
2812 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2813 secondary->compute_scratch_size_needed);
2814
2815 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2816 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2817 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2818 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2819 if (secondary->tess_rings_needed)
2820 primary->tess_rings_needed = true;
2821 if (secondary->sample_positions_needed)
2822 primary->sample_positions_needed = true;
2823
2824 if (secondary->ring_offsets_idx != -1) {
2825 if (primary->ring_offsets_idx == -1)
2826 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2827 else
2828 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2829 }
2830 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2831
2832
2833 /* When the secondary command buffer is compute only we don't
2834 * need to re-emit the current graphics pipeline.
2835 */
2836 if (secondary->state.emitted_pipeline) {
2837 primary->state.emitted_pipeline =
2838 secondary->state.emitted_pipeline;
2839 }
2840
2841 /* When the secondary command buffer is graphics only we don't
2842 * need to re-emit the current compute pipeline.
2843 */
2844 if (secondary->state.emitted_compute_pipeline) {
2845 primary->state.emitted_compute_pipeline =
2846 secondary->state.emitted_compute_pipeline;
2847 }
2848
2849 /* Only re-emit the draw packets when needed. */
2850 if (secondary->state.last_primitive_reset_en != -1) {
2851 primary->state.last_primitive_reset_en =
2852 secondary->state.last_primitive_reset_en;
2853 }
2854
2855 if (secondary->state.last_primitive_reset_index) {
2856 primary->state.last_primitive_reset_index =
2857 secondary->state.last_primitive_reset_index;
2858 }
2859
2860 if (secondary->state.last_ia_multi_vgt_param) {
2861 primary->state.last_ia_multi_vgt_param =
2862 secondary->state.last_ia_multi_vgt_param;
2863 }
2864
2865 primary->state.last_first_instance = secondary->state.last_first_instance;
2866 primary->state.last_num_instances = secondary->state.last_num_instances;
2867 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2868
2869 if (secondary->state.last_index_type != -1) {
2870 primary->state.last_index_type =
2871 secondary->state.last_index_type;
2872 }
2873 }
2874
2875 /* After executing commands from secondary buffers we have to dirty
2876 * some states.
2877 */
2878 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2879 RADV_CMD_DIRTY_INDEX_BUFFER |
2880 RADV_CMD_DIRTY_DYNAMIC_ALL;
2881 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2882 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2883 }
2884
2885 VkResult radv_CreateCommandPool(
2886 VkDevice _device,
2887 const VkCommandPoolCreateInfo* pCreateInfo,
2888 const VkAllocationCallbacks* pAllocator,
2889 VkCommandPool* pCmdPool)
2890 {
2891 RADV_FROM_HANDLE(radv_device, device, _device);
2892 struct radv_cmd_pool *pool;
2893
2894 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2895 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2896 if (pool == NULL)
2897 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2898
2899 if (pAllocator)
2900 pool->alloc = *pAllocator;
2901 else
2902 pool->alloc = device->alloc;
2903
2904 list_inithead(&pool->cmd_buffers);
2905 list_inithead(&pool->free_cmd_buffers);
2906
2907 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2908
2909 *pCmdPool = radv_cmd_pool_to_handle(pool);
2910
2911 return VK_SUCCESS;
2912
2913 }
2914
2915 void radv_DestroyCommandPool(
2916 VkDevice _device,
2917 VkCommandPool commandPool,
2918 const VkAllocationCallbacks* pAllocator)
2919 {
2920 RADV_FROM_HANDLE(radv_device, device, _device);
2921 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2922
2923 if (!pool)
2924 return;
2925
2926 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2927 &pool->cmd_buffers, pool_link) {
2928 radv_cmd_buffer_destroy(cmd_buffer);
2929 }
2930
2931 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2932 &pool->free_cmd_buffers, pool_link) {
2933 radv_cmd_buffer_destroy(cmd_buffer);
2934 }
2935
2936 vk_free2(&device->alloc, pAllocator, pool);
2937 }
2938
2939 VkResult radv_ResetCommandPool(
2940 VkDevice device,
2941 VkCommandPool commandPool,
2942 VkCommandPoolResetFlags flags)
2943 {
2944 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2945 VkResult result;
2946
2947 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2948 &pool->cmd_buffers, pool_link) {
2949 result = radv_reset_cmd_buffer(cmd_buffer);
2950 if (result != VK_SUCCESS)
2951 return result;
2952 }
2953
2954 return VK_SUCCESS;
2955 }
2956
2957 void radv_TrimCommandPool(
2958 VkDevice device,
2959 VkCommandPool commandPool,
2960 VkCommandPoolTrimFlagsKHR flags)
2961 {
2962 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2963
2964 if (!pool)
2965 return;
2966
2967 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2968 &pool->free_cmd_buffers, pool_link) {
2969 radv_cmd_buffer_destroy(cmd_buffer);
2970 }
2971 }
2972
2973 void radv_CmdBeginRenderPass(
2974 VkCommandBuffer commandBuffer,
2975 const VkRenderPassBeginInfo* pRenderPassBegin,
2976 VkSubpassContents contents)
2977 {
2978 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2979 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2980 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2981
2982 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2983 cmd_buffer->cs, 2048);
2984 MAYBE_UNUSED VkResult result;
2985
2986 cmd_buffer->state.framebuffer = framebuffer;
2987 cmd_buffer->state.pass = pass;
2988 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2989
2990 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2991 if (result != VK_SUCCESS)
2992 return;
2993
2994 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2995 assert(cmd_buffer->cs->cdw <= cdw_max);
2996
2997 radv_cmd_buffer_clear_subpass(cmd_buffer);
2998 }
2999
3000 void radv_CmdNextSubpass(
3001 VkCommandBuffer commandBuffer,
3002 VkSubpassContents contents)
3003 {
3004 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3005
3006 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3007
3008 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3009 2048);
3010
3011 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3012 radv_cmd_buffer_clear_subpass(cmd_buffer);
3013 }
3014
3015 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3016 {
3017 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3018 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3019 if (!pipeline->shaders[stage])
3020 continue;
3021 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3022 if (loc->sgpr_idx == -1)
3023 continue;
3024 uint32_t base_reg = pipeline->user_data_0[stage];
3025 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3026
3027 }
3028 if (pipeline->gs_copy_shader) {
3029 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3030 if (loc->sgpr_idx != -1) {
3031 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3032 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3033 }
3034 }
3035 }
3036
3037 static void
3038 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3039 uint32_t vertex_count)
3040 {
3041 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3042 radeon_emit(cmd_buffer->cs, vertex_count);
3043 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3044 S_0287F0_USE_OPAQUE(0));
3045 }
3046
3047 static void
3048 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3049 uint64_t index_va,
3050 uint32_t index_count)
3051 {
3052 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3053 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3054 radeon_emit(cmd_buffer->cs, index_va);
3055 radeon_emit(cmd_buffer->cs, index_va >> 32);
3056 radeon_emit(cmd_buffer->cs, index_count);
3057 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3058 }
3059
3060 static void
3061 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3062 bool indexed,
3063 uint32_t draw_count,
3064 uint64_t count_va,
3065 uint32_t stride)
3066 {
3067 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3068 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3069 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3070 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3071 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3072 assert(base_reg);
3073
3074 /* just reset draw state for vertex data */
3075 cmd_buffer->state.last_first_instance = -1;
3076 cmd_buffer->state.last_num_instances = -1;
3077 cmd_buffer->state.last_vertex_offset = -1;
3078
3079 if (draw_count == 1 && !count_va && !draw_id_enable) {
3080 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3081 PKT3_DRAW_INDIRECT, 3, false));
3082 radeon_emit(cs, 0);
3083 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3084 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3085 radeon_emit(cs, di_src_sel);
3086 } else {
3087 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3088 PKT3_DRAW_INDIRECT_MULTI,
3089 8, false));
3090 radeon_emit(cs, 0);
3091 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3092 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3093 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3094 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3095 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3096 radeon_emit(cs, draw_count); /* count */
3097 radeon_emit(cs, count_va); /* count_addr */
3098 radeon_emit(cs, count_va >> 32);
3099 radeon_emit(cs, stride); /* stride */
3100 radeon_emit(cs, di_src_sel);
3101 }
3102 }
3103
3104 struct radv_draw_info {
3105 /**
3106 * Number of vertices.
3107 */
3108 uint32_t count;
3109
3110 /**
3111 * Index of the first vertex.
3112 */
3113 int32_t vertex_offset;
3114
3115 /**
3116 * First instance id.
3117 */
3118 uint32_t first_instance;
3119
3120 /**
3121 * Number of instances.
3122 */
3123 uint32_t instance_count;
3124
3125 /**
3126 * First index (indexed draws only).
3127 */
3128 uint32_t first_index;
3129
3130 /**
3131 * Whether it's an indexed draw.
3132 */
3133 bool indexed;
3134
3135 /**
3136 * Indirect draw parameters resource.
3137 */
3138 struct radv_buffer *indirect;
3139 uint64_t indirect_offset;
3140 uint32_t stride;
3141
3142 /**
3143 * Draw count parameters resource.
3144 */
3145 struct radv_buffer *count_buffer;
3146 uint64_t count_buffer_offset;
3147 };
3148
3149 static void
3150 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3151 const struct radv_draw_info *info)
3152 {
3153 struct radv_cmd_state *state = &cmd_buffer->state;
3154 struct radeon_winsys *ws = cmd_buffer->device->ws;
3155 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3156
3157 if (info->indirect) {
3158 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3159 uint64_t count_va = 0;
3160
3161 va += info->indirect->offset + info->indirect_offset;
3162
3163 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3164
3165 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3166 radeon_emit(cs, 1);
3167 radeon_emit(cs, va);
3168 radeon_emit(cs, va >> 32);
3169
3170 if (info->count_buffer) {
3171 count_va = radv_buffer_get_va(info->count_buffer->bo);
3172 count_va += info->count_buffer->offset +
3173 info->count_buffer_offset;
3174
3175 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3176 }
3177
3178 if (!state->subpass->view_mask) {
3179 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3180 info->indexed,
3181 info->count,
3182 count_va,
3183 info->stride);
3184 } else {
3185 unsigned i;
3186 for_each_bit(i, state->subpass->view_mask) {
3187 radv_emit_view_index(cmd_buffer, i);
3188
3189 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3190 info->indexed,
3191 info->count,
3192 count_va,
3193 info->stride);
3194 }
3195 }
3196 } else {
3197 assert(state->pipeline->graphics.vtx_base_sgpr);
3198
3199 if (info->vertex_offset != state->last_vertex_offset ||
3200 info->first_instance != state->last_first_instance) {
3201 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3202 state->pipeline->graphics.vtx_emit_num);
3203
3204 radeon_emit(cs, info->vertex_offset);
3205 radeon_emit(cs, info->first_instance);
3206 if (state->pipeline->graphics.vtx_emit_num == 3)
3207 radeon_emit(cs, 0);
3208 state->last_first_instance = info->first_instance;
3209 state->last_vertex_offset = info->vertex_offset;
3210 }
3211
3212 if (state->last_num_instances != info->instance_count) {
3213 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3214 radeon_emit(cs, info->instance_count);
3215 state->last_num_instances = info->instance_count;
3216 }
3217
3218 if (info->indexed) {
3219 int index_size = state->index_type ? 4 : 2;
3220 uint64_t index_va;
3221
3222 index_va = state->index_va;
3223 index_va += info->first_index * index_size;
3224
3225 if (!state->subpass->view_mask) {
3226 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3227 index_va,
3228 info->count);
3229 } else {
3230 unsigned i;
3231 for_each_bit(i, state->subpass->view_mask) {
3232 radv_emit_view_index(cmd_buffer, i);
3233
3234 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3235 index_va,
3236 info->count);
3237 }
3238 }
3239 } else {
3240 if (!state->subpass->view_mask) {
3241 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3242 } else {
3243 unsigned i;
3244 for_each_bit(i, state->subpass->view_mask) {
3245 radv_emit_view_index(cmd_buffer, i);
3246
3247 radv_cs_emit_draw_packet(cmd_buffer,
3248 info->count);
3249 }
3250 }
3251 }
3252 }
3253 }
3254
3255 /*
3256 * Vega and raven have a bug which triggers if there are multiple context
3257 * register contexts active at the same time with different scissor values.
3258 *
3259 * There are two possible workarounds:
3260 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3261 * there is only ever 1 active set of scissor values at the same time.
3262 *
3263 * 2) Whenever the hardware switches contexts we have to set the scissor
3264 * registers again even if it is a noop. That way the new context gets
3265 * the correct scissor values.
3266 *
3267 * This implements option 2. radv_need_late_scissor_emission needs to
3268 * return true on affected HW if radv_emit_all_graphics_states sets
3269 * any context registers.
3270 */
3271 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3272 bool indexed_draw)
3273 {
3274 struct radv_cmd_state *state = &cmd_buffer->state;
3275
3276 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3277 return false;
3278
3279 /* Assume all state changes except these two can imply context rolls. */
3280 if (cmd_buffer->state.dirty & ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3281 RADV_CMD_DIRTY_VERTEX_BUFFER |
3282 RADV_CMD_DIRTY_PIPELINE))
3283 return true;
3284
3285 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3286 return true;
3287
3288 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3289 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3290 return true;
3291
3292 return false;
3293 }
3294
3295 static void
3296 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3297 const struct radv_draw_info *info)
3298 {
3299 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3300
3301 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3302 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3303 radv_emit_rbplus_state(cmd_buffer);
3304
3305 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3306 radv_emit_graphics_pipeline(cmd_buffer);
3307
3308 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3309 radv_emit_framebuffer_state(cmd_buffer);
3310
3311 if (info->indexed) {
3312 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3313 radv_emit_index_buffer(cmd_buffer);
3314 } else {
3315 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3316 * so the state must be re-emitted before the next indexed
3317 * draw.
3318 */
3319 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3320 cmd_buffer->state.last_index_type = -1;
3321 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3322 }
3323 }
3324
3325 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3326
3327 radv_emit_draw_registers(cmd_buffer, info->indexed,
3328 info->instance_count > 1, info->indirect,
3329 info->indirect ? 0 : info->count);
3330
3331 if (late_scissor_emission)
3332 radv_emit_scissor(cmd_buffer);
3333 }
3334
3335 static void
3336 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3337 const struct radv_draw_info *info)
3338 {
3339 bool has_prefetch =
3340 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3341 bool pipeline_is_dirty =
3342 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3343 cmd_buffer->state.pipeline &&
3344 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3345
3346 MAYBE_UNUSED unsigned cdw_max =
3347 radeon_check_space(cmd_buffer->device->ws,
3348 cmd_buffer->cs, 4096);
3349
3350 /* Use optimal packet order based on whether we need to sync the
3351 * pipeline.
3352 */
3353 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3354 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3355 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3356 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3357 /* If we have to wait for idle, set all states first, so that
3358 * all SET packets are processed in parallel with previous draw
3359 * calls. Then upload descriptors, set shader pointers, and
3360 * draw, and prefetch at the end. This ensures that the time
3361 * the CUs are idle is very short. (there are only SET_SH
3362 * packets between the wait and the draw)
3363 */
3364 radv_emit_all_graphics_states(cmd_buffer, info);
3365 si_emit_cache_flush(cmd_buffer);
3366 /* <-- CUs are idle here --> */
3367
3368 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3369
3370 radv_emit_draw_packets(cmd_buffer, info);
3371 /* <-- CUs are busy here --> */
3372
3373 /* Start prefetches after the draw has been started. Both will
3374 * run in parallel, but starting the draw first is more
3375 * important.
3376 */
3377 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3378 radv_emit_prefetch_L2(cmd_buffer,
3379 cmd_buffer->state.pipeline, false);
3380 }
3381 } else {
3382 /* If we don't wait for idle, start prefetches first, then set
3383 * states, and draw at the end.
3384 */
3385 si_emit_cache_flush(cmd_buffer);
3386
3387 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3388 /* Only prefetch the vertex shader and VBO descriptors
3389 * in order to start the draw as soon as possible.
3390 */
3391 radv_emit_prefetch_L2(cmd_buffer,
3392 cmd_buffer->state.pipeline, true);
3393 }
3394
3395 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3396
3397 radv_emit_all_graphics_states(cmd_buffer, info);
3398 radv_emit_draw_packets(cmd_buffer, info);
3399
3400 /* Prefetch the remaining shaders after the draw has been
3401 * started.
3402 */
3403 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3404 radv_emit_prefetch_L2(cmd_buffer,
3405 cmd_buffer->state.pipeline, false);
3406 }
3407 }
3408
3409 assert(cmd_buffer->cs->cdw <= cdw_max);
3410 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3411 }
3412
3413 void radv_CmdDraw(
3414 VkCommandBuffer commandBuffer,
3415 uint32_t vertexCount,
3416 uint32_t instanceCount,
3417 uint32_t firstVertex,
3418 uint32_t firstInstance)
3419 {
3420 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3421 struct radv_draw_info info = {};
3422
3423 info.count = vertexCount;
3424 info.instance_count = instanceCount;
3425 info.first_instance = firstInstance;
3426 info.vertex_offset = firstVertex;
3427
3428 radv_draw(cmd_buffer, &info);
3429 }
3430
3431 void radv_CmdDrawIndexed(
3432 VkCommandBuffer commandBuffer,
3433 uint32_t indexCount,
3434 uint32_t instanceCount,
3435 uint32_t firstIndex,
3436 int32_t vertexOffset,
3437 uint32_t firstInstance)
3438 {
3439 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3440 struct radv_draw_info info = {};
3441
3442 info.indexed = true;
3443 info.count = indexCount;
3444 info.instance_count = instanceCount;
3445 info.first_index = firstIndex;
3446 info.vertex_offset = vertexOffset;
3447 info.first_instance = firstInstance;
3448
3449 radv_draw(cmd_buffer, &info);
3450 }
3451
3452 void radv_CmdDrawIndirect(
3453 VkCommandBuffer commandBuffer,
3454 VkBuffer _buffer,
3455 VkDeviceSize offset,
3456 uint32_t drawCount,
3457 uint32_t stride)
3458 {
3459 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3460 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3461 struct radv_draw_info info = {};
3462
3463 info.count = drawCount;
3464 info.indirect = buffer;
3465 info.indirect_offset = offset;
3466 info.stride = stride;
3467
3468 radv_draw(cmd_buffer, &info);
3469 }
3470
3471 void radv_CmdDrawIndexedIndirect(
3472 VkCommandBuffer commandBuffer,
3473 VkBuffer _buffer,
3474 VkDeviceSize offset,
3475 uint32_t drawCount,
3476 uint32_t stride)
3477 {
3478 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3479 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3480 struct radv_draw_info info = {};
3481
3482 info.indexed = true;
3483 info.count = drawCount;
3484 info.indirect = buffer;
3485 info.indirect_offset = offset;
3486 info.stride = stride;
3487
3488 radv_draw(cmd_buffer, &info);
3489 }
3490
3491 void radv_CmdDrawIndirectCountAMD(
3492 VkCommandBuffer commandBuffer,
3493 VkBuffer _buffer,
3494 VkDeviceSize offset,
3495 VkBuffer _countBuffer,
3496 VkDeviceSize countBufferOffset,
3497 uint32_t maxDrawCount,
3498 uint32_t stride)
3499 {
3500 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3501 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3502 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3503 struct radv_draw_info info = {};
3504
3505 info.count = maxDrawCount;
3506 info.indirect = buffer;
3507 info.indirect_offset = offset;
3508 info.count_buffer = count_buffer;
3509 info.count_buffer_offset = countBufferOffset;
3510 info.stride = stride;
3511
3512 radv_draw(cmd_buffer, &info);
3513 }
3514
3515 void radv_CmdDrawIndexedIndirectCountAMD(
3516 VkCommandBuffer commandBuffer,
3517 VkBuffer _buffer,
3518 VkDeviceSize offset,
3519 VkBuffer _countBuffer,
3520 VkDeviceSize countBufferOffset,
3521 uint32_t maxDrawCount,
3522 uint32_t stride)
3523 {
3524 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3525 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3526 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3527 struct radv_draw_info info = {};
3528
3529 info.indexed = true;
3530 info.count = maxDrawCount;
3531 info.indirect = buffer;
3532 info.indirect_offset = offset;
3533 info.count_buffer = count_buffer;
3534 info.count_buffer_offset = countBufferOffset;
3535 info.stride = stride;
3536
3537 radv_draw(cmd_buffer, &info);
3538 }
3539
3540 void radv_CmdDrawIndirectCountKHR(
3541 VkCommandBuffer commandBuffer,
3542 VkBuffer _buffer,
3543 VkDeviceSize offset,
3544 VkBuffer _countBuffer,
3545 VkDeviceSize countBufferOffset,
3546 uint32_t maxDrawCount,
3547 uint32_t stride)
3548 {
3549 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3550 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3551 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3552 struct radv_draw_info info = {};
3553
3554 info.count = maxDrawCount;
3555 info.indirect = buffer;
3556 info.indirect_offset = offset;
3557 info.count_buffer = count_buffer;
3558 info.count_buffer_offset = countBufferOffset;
3559 info.stride = stride;
3560
3561 radv_draw(cmd_buffer, &info);
3562 }
3563
3564 void radv_CmdDrawIndexedIndirectCountKHR(
3565 VkCommandBuffer commandBuffer,
3566 VkBuffer _buffer,
3567 VkDeviceSize offset,
3568 VkBuffer _countBuffer,
3569 VkDeviceSize countBufferOffset,
3570 uint32_t maxDrawCount,
3571 uint32_t stride)
3572 {
3573 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3574 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3575 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3576 struct radv_draw_info info = {};
3577
3578 info.indexed = true;
3579 info.count = maxDrawCount;
3580 info.indirect = buffer;
3581 info.indirect_offset = offset;
3582 info.count_buffer = count_buffer;
3583 info.count_buffer_offset = countBufferOffset;
3584 info.stride = stride;
3585
3586 radv_draw(cmd_buffer, &info);
3587 }
3588
3589 struct radv_dispatch_info {
3590 /**
3591 * Determine the layout of the grid (in block units) to be used.
3592 */
3593 uint32_t blocks[3];
3594
3595 /**
3596 * A starting offset for the grid. If unaligned is set, the offset
3597 * must still be aligned.
3598 */
3599 uint32_t offsets[3];
3600 /**
3601 * Whether it's an unaligned compute dispatch.
3602 */
3603 bool unaligned;
3604
3605 /**
3606 * Indirect compute parameters resource.
3607 */
3608 struct radv_buffer *indirect;
3609 uint64_t indirect_offset;
3610 };
3611
3612 static void
3613 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3614 const struct radv_dispatch_info *info)
3615 {
3616 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3617 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3618 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3619 struct radeon_winsys *ws = cmd_buffer->device->ws;
3620 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3621 struct radv_userdata_info *loc;
3622
3623 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3624 AC_UD_CS_GRID_SIZE);
3625
3626 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3627
3628 if (info->indirect) {
3629 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3630
3631 va += info->indirect->offset + info->indirect_offset;
3632
3633 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3634
3635 if (loc->sgpr_idx != -1) {
3636 for (unsigned i = 0; i < 3; ++i) {
3637 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3638 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3639 COPY_DATA_DST_SEL(COPY_DATA_REG));
3640 radeon_emit(cs, (va + 4 * i));
3641 radeon_emit(cs, (va + 4 * i) >> 32);
3642 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3643 + loc->sgpr_idx * 4) >> 2) + i);
3644 radeon_emit(cs, 0);
3645 }
3646 }
3647
3648 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3649 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3650 PKT3_SHADER_TYPE_S(1));
3651 radeon_emit(cs, va);
3652 radeon_emit(cs, va >> 32);
3653 radeon_emit(cs, dispatch_initiator);
3654 } else {
3655 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3656 PKT3_SHADER_TYPE_S(1));
3657 radeon_emit(cs, 1);
3658 radeon_emit(cs, va);
3659 radeon_emit(cs, va >> 32);
3660
3661 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3662 PKT3_SHADER_TYPE_S(1));
3663 radeon_emit(cs, 0);
3664 radeon_emit(cs, dispatch_initiator);
3665 }
3666 } else {
3667 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3668 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3669
3670 if (info->unaligned) {
3671 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3672 unsigned remainder[3];
3673
3674 /* If aligned, these should be an entire block size,
3675 * not 0.
3676 */
3677 remainder[0] = blocks[0] + cs_block_size[0] -
3678 align_u32_npot(blocks[0], cs_block_size[0]);
3679 remainder[1] = blocks[1] + cs_block_size[1] -
3680 align_u32_npot(blocks[1], cs_block_size[1]);
3681 remainder[2] = blocks[2] + cs_block_size[2] -
3682 align_u32_npot(blocks[2], cs_block_size[2]);
3683
3684 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3685 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3686 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3687
3688 for(unsigned i = 0; i < 3; ++i) {
3689 assert(offsets[i] % cs_block_size[i] == 0);
3690 offsets[i] /= cs_block_size[i];
3691 }
3692
3693 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3694 radeon_emit(cs,
3695 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3696 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3697 radeon_emit(cs,
3698 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3699 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3700 radeon_emit(cs,
3701 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3702 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3703
3704 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3705 }
3706
3707 if (loc->sgpr_idx != -1) {
3708 assert(!loc->indirect);
3709 assert(loc->num_sgprs == 3);
3710
3711 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3712 loc->sgpr_idx * 4, 3);
3713 radeon_emit(cs, blocks[0]);
3714 radeon_emit(cs, blocks[1]);
3715 radeon_emit(cs, blocks[2]);
3716 }
3717
3718 if (offsets[0] || offsets[1] || offsets[2]) {
3719 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3720 radeon_emit(cs, offsets[0]);
3721 radeon_emit(cs, offsets[1]);
3722 radeon_emit(cs, offsets[2]);
3723
3724 /* The blocks in the packet are not counts but end values. */
3725 for (unsigned i = 0; i < 3; ++i)
3726 blocks[i] += offsets[i];
3727 } else {
3728 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3729 }
3730
3731 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3732 PKT3_SHADER_TYPE_S(1));
3733 radeon_emit(cs, blocks[0]);
3734 radeon_emit(cs, blocks[1]);
3735 radeon_emit(cs, blocks[2]);
3736 radeon_emit(cs, dispatch_initiator);
3737 }
3738
3739 assert(cmd_buffer->cs->cdw <= cdw_max);
3740 }
3741
3742 static void
3743 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3744 {
3745 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3746 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3747 }
3748
3749 static void
3750 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3751 const struct radv_dispatch_info *info)
3752 {
3753 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3754 bool has_prefetch =
3755 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3756 bool pipeline_is_dirty = pipeline &&
3757 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3758
3759 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3760 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3761 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3762 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3763 /* If we have to wait for idle, set all states first, so that
3764 * all SET packets are processed in parallel with previous draw
3765 * calls. Then upload descriptors, set shader pointers, and
3766 * dispatch, and prefetch at the end. This ensures that the
3767 * time the CUs are idle is very short. (there are only SET_SH
3768 * packets between the wait and the draw)
3769 */
3770 radv_emit_compute_pipeline(cmd_buffer);
3771 si_emit_cache_flush(cmd_buffer);
3772 /* <-- CUs are idle here --> */
3773
3774 radv_upload_compute_shader_descriptors(cmd_buffer);
3775
3776 radv_emit_dispatch_packets(cmd_buffer, info);
3777 /* <-- CUs are busy here --> */
3778
3779 /* Start prefetches after the dispatch has been started. Both
3780 * will run in parallel, but starting the dispatch first is
3781 * more important.
3782 */
3783 if (has_prefetch && pipeline_is_dirty) {
3784 radv_emit_shader_prefetch(cmd_buffer,
3785 pipeline->shaders[MESA_SHADER_COMPUTE]);
3786 }
3787 } else {
3788 /* If we don't wait for idle, start prefetches first, then set
3789 * states, and dispatch at the end.
3790 */
3791 si_emit_cache_flush(cmd_buffer);
3792
3793 if (has_prefetch && pipeline_is_dirty) {
3794 radv_emit_shader_prefetch(cmd_buffer,
3795 pipeline->shaders[MESA_SHADER_COMPUTE]);
3796 }
3797
3798 radv_upload_compute_shader_descriptors(cmd_buffer);
3799
3800 radv_emit_compute_pipeline(cmd_buffer);
3801 radv_emit_dispatch_packets(cmd_buffer, info);
3802 }
3803
3804 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3805 }
3806
3807 void radv_CmdDispatchBase(
3808 VkCommandBuffer commandBuffer,
3809 uint32_t base_x,
3810 uint32_t base_y,
3811 uint32_t base_z,
3812 uint32_t x,
3813 uint32_t y,
3814 uint32_t z)
3815 {
3816 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3817 struct radv_dispatch_info info = {};
3818
3819 info.blocks[0] = x;
3820 info.blocks[1] = y;
3821 info.blocks[2] = z;
3822
3823 info.offsets[0] = base_x;
3824 info.offsets[1] = base_y;
3825 info.offsets[2] = base_z;
3826 radv_dispatch(cmd_buffer, &info);
3827 }
3828
3829 void radv_CmdDispatch(
3830 VkCommandBuffer commandBuffer,
3831 uint32_t x,
3832 uint32_t y,
3833 uint32_t z)
3834 {
3835 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3836 }
3837
3838 void radv_CmdDispatchIndirect(
3839 VkCommandBuffer commandBuffer,
3840 VkBuffer _buffer,
3841 VkDeviceSize offset)
3842 {
3843 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3844 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3845 struct radv_dispatch_info info = {};
3846
3847 info.indirect = buffer;
3848 info.indirect_offset = offset;
3849
3850 radv_dispatch(cmd_buffer, &info);
3851 }
3852
3853 void radv_unaligned_dispatch(
3854 struct radv_cmd_buffer *cmd_buffer,
3855 uint32_t x,
3856 uint32_t y,
3857 uint32_t z)
3858 {
3859 struct radv_dispatch_info info = {};
3860
3861 info.blocks[0] = x;
3862 info.blocks[1] = y;
3863 info.blocks[2] = z;
3864 info.unaligned = 1;
3865
3866 radv_dispatch(cmd_buffer, &info);
3867 }
3868
3869 void radv_CmdEndRenderPass(
3870 VkCommandBuffer commandBuffer)
3871 {
3872 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3873
3874 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3875
3876 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3877
3878 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3879 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3880 radv_handle_subpass_image_transition(cmd_buffer,
3881 (VkAttachmentReference){i, layout});
3882 }
3883
3884 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3885
3886 cmd_buffer->state.pass = NULL;
3887 cmd_buffer->state.subpass = NULL;
3888 cmd_buffer->state.attachments = NULL;
3889 cmd_buffer->state.framebuffer = NULL;
3890 }
3891
3892 /*
3893 * For HTILE we have the following interesting clear words:
3894 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3895 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3896 * 0xfffffff0: Clear depth to 1.0
3897 * 0x00000000: Clear depth to 0.0
3898 */
3899 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3900 struct radv_image *image,
3901 const VkImageSubresourceRange *range,
3902 uint32_t clear_word)
3903 {
3904 assert(range->baseMipLevel == 0);
3905 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3906 unsigned layer_count = radv_get_layerCount(image, range);
3907 uint64_t size = image->surface.htile_slice_size * layer_count;
3908 uint64_t offset = image->offset + image->htile_offset +
3909 image->surface.htile_slice_size * range->baseArrayLayer;
3910 struct radv_cmd_state *state = &cmd_buffer->state;
3911
3912 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3913 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3914
3915 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3916 size, clear_word);
3917
3918 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3919
3920 /* Initialize the depth clear registers and update the ZRANGE_PRECISION
3921 * value for the TC-compat bug (because ZRANGE_PRECISION is 1 by
3922 * default). This is only needed whean clearing Z to 0.0f.
3923 */
3924 if (radv_image_is_tc_compat_htile(image) && clear_word == 0) {
3925 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
3926 VkClearDepthStencilValue value = {};
3927
3928 if (vk_format_is_stencil(image->vk_format))
3929 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3930
3931 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
3932 }
3933 }
3934
3935 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3936 struct radv_image *image,
3937 VkImageLayout src_layout,
3938 VkImageLayout dst_layout,
3939 unsigned src_queue_mask,
3940 unsigned dst_queue_mask,
3941 const VkImageSubresourceRange *range,
3942 VkImageAspectFlags pending_clears)
3943 {
3944 if (!radv_image_has_htile(image))
3945 return;
3946
3947 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3948 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3949 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3950 cmd_buffer->state.render_area.extent.width == image->info.width &&
3951 cmd_buffer->state.render_area.extent.height == image->info.height) {
3952 /* The clear will initialize htile. */
3953 return;
3954 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3955 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3956 /* TODO: merge with the clear if applicable */
3957 radv_initialize_htile(cmd_buffer, image, range, 0);
3958 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3959 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3960 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3961 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3962 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3963 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3964 VkImageSubresourceRange local_range = *range;
3965 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3966 local_range.baseMipLevel = 0;
3967 local_range.levelCount = 1;
3968
3969 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3970 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3971
3972 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3973
3974 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3975 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3976 }
3977 }
3978
3979 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3980 struct radv_image *image, uint32_t value)
3981 {
3982 struct radv_cmd_state *state = &cmd_buffer->state;
3983
3984 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3985 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3986
3987 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
3988
3989 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3990 }
3991
3992 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3993 struct radv_image *image, uint32_t value)
3994 {
3995 struct radv_cmd_state *state = &cmd_buffer->state;
3996
3997 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3998 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3999
4000 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4001
4002 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4003 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4004 }
4005
4006 /**
4007 * Initialize DCC/FMASK/CMASK metadata for a color image.
4008 */
4009 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4010 struct radv_image *image,
4011 VkImageLayout src_layout,
4012 VkImageLayout dst_layout,
4013 unsigned src_queue_mask,
4014 unsigned dst_queue_mask)
4015 {
4016 if (radv_image_has_cmask(image)) {
4017 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4018
4019 /* TODO: clarify this. */
4020 if (radv_image_has_fmask(image)) {
4021 value = 0xccccccccu;
4022 }
4023
4024 radv_initialise_cmask(cmd_buffer, image, value);
4025 }
4026
4027 if (radv_image_has_dcc(image)) {
4028 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4029
4030 if (radv_layout_dcc_compressed(image, dst_layout,
4031 dst_queue_mask)) {
4032 value = 0x20202020u;
4033 }
4034
4035 radv_initialize_dcc(cmd_buffer, image, value);
4036 }
4037 }
4038
4039 /**
4040 * Handle color image transitions for DCC/FMASK/CMASK.
4041 */
4042 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4043 struct radv_image *image,
4044 VkImageLayout src_layout,
4045 VkImageLayout dst_layout,
4046 unsigned src_queue_mask,
4047 unsigned dst_queue_mask,
4048 const VkImageSubresourceRange *range)
4049 {
4050 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4051 radv_init_color_image_metadata(cmd_buffer, image,
4052 src_layout, dst_layout,
4053 src_queue_mask, dst_queue_mask);
4054 return;
4055 }
4056
4057 if (radv_image_has_dcc(image)) {
4058 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4059 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4060 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4061 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4062 radv_decompress_dcc(cmd_buffer, image, range);
4063 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4064 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4065 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4066 }
4067 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4068 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4069 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4070 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4071 }
4072 }
4073 }
4074
4075 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4076 struct radv_image *image,
4077 VkImageLayout src_layout,
4078 VkImageLayout dst_layout,
4079 uint32_t src_family,
4080 uint32_t dst_family,
4081 const VkImageSubresourceRange *range,
4082 VkImageAspectFlags pending_clears)
4083 {
4084 if (image->exclusive && src_family != dst_family) {
4085 /* This is an acquire or a release operation and there will be
4086 * a corresponding release/acquire. Do the transition in the
4087 * most flexible queue. */
4088
4089 assert(src_family == cmd_buffer->queue_family_index ||
4090 dst_family == cmd_buffer->queue_family_index);
4091
4092 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4093 return;
4094
4095 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4096 (src_family == RADV_QUEUE_GENERAL ||
4097 dst_family == RADV_QUEUE_GENERAL))
4098 return;
4099 }
4100
4101 unsigned src_queue_mask =
4102 radv_image_queue_family_mask(image, src_family,
4103 cmd_buffer->queue_family_index);
4104 unsigned dst_queue_mask =
4105 radv_image_queue_family_mask(image, dst_family,
4106 cmd_buffer->queue_family_index);
4107
4108 if (vk_format_is_depth(image->vk_format)) {
4109 radv_handle_depth_image_transition(cmd_buffer, image,
4110 src_layout, dst_layout,
4111 src_queue_mask, dst_queue_mask,
4112 range, pending_clears);
4113 } else {
4114 radv_handle_color_image_transition(cmd_buffer, image,
4115 src_layout, dst_layout,
4116 src_queue_mask, dst_queue_mask,
4117 range);
4118 }
4119 }
4120
4121 void radv_CmdPipelineBarrier(
4122 VkCommandBuffer commandBuffer,
4123 VkPipelineStageFlags srcStageMask,
4124 VkPipelineStageFlags destStageMask,
4125 VkBool32 byRegion,
4126 uint32_t memoryBarrierCount,
4127 const VkMemoryBarrier* pMemoryBarriers,
4128 uint32_t bufferMemoryBarrierCount,
4129 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4130 uint32_t imageMemoryBarrierCount,
4131 const VkImageMemoryBarrier* pImageMemoryBarriers)
4132 {
4133 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4134 enum radv_cmd_flush_bits src_flush_bits = 0;
4135 enum radv_cmd_flush_bits dst_flush_bits = 0;
4136
4137 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4138 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
4139 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4140 NULL);
4141 }
4142
4143 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4144 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
4145 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4146 NULL);
4147 }
4148
4149 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4150 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4151 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
4152 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4153 image);
4154 }
4155
4156 radv_stage_flush(cmd_buffer, srcStageMask);
4157 cmd_buffer->state.flush_bits |= src_flush_bits;
4158
4159 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4160 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4161 radv_handle_image_transition(cmd_buffer, image,
4162 pImageMemoryBarriers[i].oldLayout,
4163 pImageMemoryBarriers[i].newLayout,
4164 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4165 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4166 &pImageMemoryBarriers[i].subresourceRange,
4167 0);
4168 }
4169
4170 cmd_buffer->state.flush_bits |= dst_flush_bits;
4171 }
4172
4173
4174 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4175 struct radv_event *event,
4176 VkPipelineStageFlags stageMask,
4177 unsigned value)
4178 {
4179 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4180 uint64_t va = radv_buffer_get_va(event->bo);
4181
4182 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4183
4184 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4185
4186 /* TODO: this is overkill. Probably should figure something out from
4187 * the stage mask. */
4188
4189 si_cs_emit_write_event_eop(cs,
4190 cmd_buffer->state.predicating,
4191 cmd_buffer->device->physical_device->rad_info.chip_class,
4192 radv_cmd_buffer_uses_mec(cmd_buffer),
4193 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4194 1, va, 2, value);
4195
4196 assert(cmd_buffer->cs->cdw <= cdw_max);
4197 }
4198
4199 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4200 VkEvent _event,
4201 VkPipelineStageFlags stageMask)
4202 {
4203 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4204 RADV_FROM_HANDLE(radv_event, event, _event);
4205
4206 write_event(cmd_buffer, event, stageMask, 1);
4207 }
4208
4209 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4210 VkEvent _event,
4211 VkPipelineStageFlags stageMask)
4212 {
4213 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4214 RADV_FROM_HANDLE(radv_event, event, _event);
4215
4216 write_event(cmd_buffer, event, stageMask, 0);
4217 }
4218
4219 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4220 uint32_t eventCount,
4221 const VkEvent* pEvents,
4222 VkPipelineStageFlags srcStageMask,
4223 VkPipelineStageFlags dstStageMask,
4224 uint32_t memoryBarrierCount,
4225 const VkMemoryBarrier* pMemoryBarriers,
4226 uint32_t bufferMemoryBarrierCount,
4227 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4228 uint32_t imageMemoryBarrierCount,
4229 const VkImageMemoryBarrier* pImageMemoryBarriers)
4230 {
4231 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4232 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4233
4234 for (unsigned i = 0; i < eventCount; ++i) {
4235 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4236 uint64_t va = radv_buffer_get_va(event->bo);
4237
4238 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4239
4240 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4241
4242 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4243 assert(cmd_buffer->cs->cdw <= cdw_max);
4244 }
4245
4246
4247 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4248 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4249
4250 radv_handle_image_transition(cmd_buffer, image,
4251 pImageMemoryBarriers[i].oldLayout,
4252 pImageMemoryBarriers[i].newLayout,
4253 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4254 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4255 &pImageMemoryBarriers[i].subresourceRange,
4256 0);
4257 }
4258
4259 /* TODO: figure out how to do memory barriers without waiting */
4260 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4261 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4262 RADV_CMD_FLAG_INV_VMEM_L1 |
4263 RADV_CMD_FLAG_INV_SMEM_L1;
4264 }
4265
4266
4267 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4268 uint32_t deviceMask)
4269 {
4270 /* No-op */
4271 }