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radv: factor out si_emit_wait_fence code.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 uint32_t src_family,
42 uint32_t dst_family,
43 const VkImageSubresourceRange *range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static void
191 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
192 {
193 list_del(&cmd_buffer->pool_link);
194
195 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
196 &cmd_buffer->upload.list, list) {
197 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
198 list_del(&up->list);
199 free(up);
200 }
201
202 if (cmd_buffer->upload.upload_bo)
203 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
204 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
205 free(cmd_buffer->push_descriptors.set.mapped_ptr);
206 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
207 }
208
209 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
210 {
211
212 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
213
214 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
215 &cmd_buffer->upload.list, list) {
216 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
217 list_del(&up->list);
218 free(up);
219 }
220
221 cmd_buffer->scratch_size_needed = 0;
222 cmd_buffer->compute_scratch_size_needed = 0;
223 cmd_buffer->esgs_ring_size_needed = 0;
224 cmd_buffer->gsvs_ring_size_needed = 0;
225 cmd_buffer->tess_rings_needed = false;
226 cmd_buffer->sample_positions_needed = false;
227
228 if (cmd_buffer->upload.upload_bo)
229 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
230 cmd_buffer->upload.upload_bo, 8);
231 cmd_buffer->upload.offset = 0;
232
233 cmd_buffer->record_fail = false;
234
235 cmd_buffer->ring_offsets_idx = -1;
236 }
237
238 static bool
239 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
240 uint64_t min_needed)
241 {
242 uint64_t new_size;
243 struct radeon_winsys_bo *bo;
244 struct radv_cmd_buffer_upload *upload;
245 struct radv_device *device = cmd_buffer->device;
246
247 new_size = MAX2(min_needed, 16 * 1024);
248 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
249
250 bo = device->ws->buffer_create(device->ws,
251 new_size, 4096,
252 RADEON_DOMAIN_GTT,
253 RADEON_FLAG_CPU_ACCESS);
254
255 if (!bo) {
256 cmd_buffer->record_fail = true;
257 return false;
258 }
259
260 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
261 if (cmd_buffer->upload.upload_bo) {
262 upload = malloc(sizeof(*upload));
263
264 if (!upload) {
265 cmd_buffer->record_fail = true;
266 device->ws->buffer_destroy(bo);
267 return false;
268 }
269
270 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
271 list_add(&upload->list, &cmd_buffer->upload.list);
272 }
273
274 cmd_buffer->upload.upload_bo = bo;
275 cmd_buffer->upload.size = new_size;
276 cmd_buffer->upload.offset = 0;
277 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
278
279 if (!cmd_buffer->upload.map) {
280 cmd_buffer->record_fail = true;
281 return false;
282 }
283
284 return true;
285 }
286
287 bool
288 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
289 unsigned size,
290 unsigned alignment,
291 unsigned *out_offset,
292 void **ptr)
293 {
294 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
295 if (offset + size > cmd_buffer->upload.size) {
296 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
297 return false;
298 offset = 0;
299 }
300
301 *out_offset = offset;
302 *ptr = cmd_buffer->upload.map + offset;
303
304 cmd_buffer->upload.offset = offset + size;
305 return true;
306 }
307
308 bool
309 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
310 unsigned size, unsigned alignment,
311 const void *data, unsigned *out_offset)
312 {
313 uint8_t *ptr;
314
315 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
316 out_offset, (void **)&ptr))
317 return false;
318
319 if (ptr)
320 memcpy(ptr, data, size);
321
322 return true;
323 }
324
325 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
326 {
327 struct radv_device *device = cmd_buffer->device;
328 struct radeon_winsys_cs *cs = cmd_buffer->cs;
329 uint64_t va;
330
331 if (!device->trace_bo)
332 return;
333
334 va = device->ws->buffer_get_va(device->trace_bo);
335
336 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
337
338 ++cmd_buffer->state.trace_id;
339 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
340 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
341 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
342 S_370_WR_CONFIRM(1) |
343 S_370_ENGINE_SEL(V_370_ME));
344 radeon_emit(cs, va);
345 radeon_emit(cs, va >> 32);
346 radeon_emit(cs, cmd_buffer->state.trace_id);
347 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
348 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
349 }
350
351 static void
352 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
353 struct radv_pipeline *pipeline)
354 {
355 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
356 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
357 8);
358 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
359 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
360 }
361
362 static void
363 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
364 struct radv_pipeline *pipeline)
365 {
366 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
367 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
368 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
369
370 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
371 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
372 }
373
374 /* 12.4 fixed-point */
375 static unsigned radv_pack_float_12p4(float x)
376 {
377 return x <= 0 ? 0 :
378 x >= 4096 ? 0xffff : x * 16;
379 }
380
381 static uint32_t
382 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
383 {
384 switch (stage) {
385 case MESA_SHADER_FRAGMENT:
386 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
387 case MESA_SHADER_VERTEX:
388 if (has_tess)
389 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
390 else
391 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
392 case MESA_SHADER_GEOMETRY:
393 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
394 case MESA_SHADER_COMPUTE:
395 return R_00B900_COMPUTE_USER_DATA_0;
396 case MESA_SHADER_TESS_CTRL:
397 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
398 case MESA_SHADER_TESS_EVAL:
399 if (has_gs)
400 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
401 else
402 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
403 default:
404 unreachable("unknown shader");
405 }
406 }
407
408 static struct ac_userdata_info *
409 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
410 gl_shader_stage stage,
411 int idx)
412 {
413 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
414 }
415
416 static void
417 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
418 struct radv_pipeline *pipeline,
419 gl_shader_stage stage,
420 int idx, uint64_t va)
421 {
422 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
423 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
424 if (loc->sgpr_idx == -1)
425 return;
426 assert(loc->num_sgprs == 2);
427 assert(!loc->indirect);
428 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
429 radeon_emit(cmd_buffer->cs, va);
430 radeon_emit(cmd_buffer->cs, va >> 32);
431 }
432
433 static void
434 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
435 struct radv_pipeline *pipeline)
436 {
437 int num_samples = pipeline->graphics.ms.num_samples;
438 struct radv_multisample_state *ms = &pipeline->graphics.ms;
439 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
440
441 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
442 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
443 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
444
445 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
446 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
447
448 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
449 return;
450
451 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
452 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
453 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
454
455 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
456
457 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
458 uint32_t offset;
459 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
460 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
461 if (loc->sgpr_idx == -1)
462 return;
463 assert(loc->num_sgprs == 1);
464 assert(!loc->indirect);
465 switch (num_samples) {
466 default:
467 offset = 0;
468 break;
469 case 2:
470 offset = 1;
471 break;
472 case 4:
473 offset = 3;
474 break;
475 case 8:
476 offset = 7;
477 break;
478 case 16:
479 offset = 15;
480 break;
481 }
482
483 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
484 cmd_buffer->sample_positions_needed = true;
485 }
486 }
487
488 static void
489 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
490 struct radv_pipeline *pipeline)
491 {
492 struct radv_raster_state *raster = &pipeline->graphics.raster;
493
494 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
495 raster->pa_cl_clip_cntl);
496
497 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
498 raster->spi_interp_control);
499
500 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
501 unsigned tmp = (unsigned)(1.0 * 8.0);
502 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
503 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
504 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
505
506 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
507 raster->pa_su_vtx_cntl);
508
509 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
510 raster->pa_su_sc_mode_cntl);
511 }
512
513 static void
514 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
515 struct radv_pipeline *pipeline,
516 struct radv_shader_variant *shader,
517 struct ac_vs_output_info *outinfo)
518 {
519 struct radeon_winsys *ws = cmd_buffer->device->ws;
520 uint64_t va = ws->buffer_get_va(shader->bo);
521 unsigned export_count;
522
523 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
524 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
525
526 export_count = MAX2(1, outinfo->param_exports);
527 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
528 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
529
530 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
531 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
532 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
533 V_02870C_SPI_SHADER_4COMP :
534 V_02870C_SPI_SHADER_NONE) |
535 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
536 V_02870C_SPI_SHADER_4COMP :
537 V_02870C_SPI_SHADER_NONE) |
538 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
539 V_02870C_SPI_SHADER_4COMP :
540 V_02870C_SPI_SHADER_NONE));
541
542
543 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
544 radeon_emit(cmd_buffer->cs, va >> 8);
545 radeon_emit(cmd_buffer->cs, va >> 40);
546 radeon_emit(cmd_buffer->cs, shader->rsrc1);
547 radeon_emit(cmd_buffer->cs, shader->rsrc2);
548
549 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
550 S_028818_VTX_W0_FMT(1) |
551 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
552 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
553 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
554
555
556 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
557 pipeline->graphics.pa_cl_vs_out_cntl);
558
559 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
560 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
561 }
562
563 static void
564 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
565 struct radv_shader_variant *shader,
566 struct ac_es_output_info *outinfo)
567 {
568 struct radeon_winsys *ws = cmd_buffer->device->ws;
569 uint64_t va = ws->buffer_get_va(shader->bo);
570
571 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
572 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
573
574 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
575 outinfo->esgs_itemsize / 4);
576 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
577 radeon_emit(cmd_buffer->cs, va >> 8);
578 radeon_emit(cmd_buffer->cs, va >> 40);
579 radeon_emit(cmd_buffer->cs, shader->rsrc1);
580 radeon_emit(cmd_buffer->cs, shader->rsrc2);
581 }
582
583 static void
584 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
585 struct radv_shader_variant *shader)
586 {
587 struct radeon_winsys *ws = cmd_buffer->device->ws;
588 uint64_t va = ws->buffer_get_va(shader->bo);
589 uint32_t rsrc2 = shader->rsrc2;
590
591 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
592 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
593
594 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
595 radeon_emit(cmd_buffer->cs, va >> 8);
596 radeon_emit(cmd_buffer->cs, va >> 40);
597
598 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
599 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
600 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
601 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
602
603 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
604 radeon_emit(cmd_buffer->cs, shader->rsrc1);
605 radeon_emit(cmd_buffer->cs, rsrc2);
606 }
607
608 static void
609 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
610 struct radv_shader_variant *shader)
611 {
612 struct radeon_winsys *ws = cmd_buffer->device->ws;
613 uint64_t va = ws->buffer_get_va(shader->bo);
614
615 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
616 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
617
618 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
619 radeon_emit(cmd_buffer->cs, va >> 8);
620 radeon_emit(cmd_buffer->cs, va >> 40);
621 radeon_emit(cmd_buffer->cs, shader->rsrc1);
622 radeon_emit(cmd_buffer->cs, shader->rsrc2);
623 }
624
625 static void
626 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
627 struct radv_pipeline *pipeline)
628 {
629 struct radv_shader_variant *vs;
630
631 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
632
633 vs = pipeline->shaders[MESA_SHADER_VERTEX];
634
635 if (vs->info.vs.as_ls)
636 radv_emit_hw_ls(cmd_buffer, vs);
637 else if (vs->info.vs.as_es)
638 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
639 else
640 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
641
642 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
643 }
644
645
646 static void
647 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
648 struct radv_pipeline *pipeline)
649 {
650 if (!radv_pipeline_has_tess(pipeline))
651 return;
652
653 struct radv_shader_variant *tes, *tcs;
654
655 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
656 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
657
658 if (tes->info.tes.as_es)
659 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
660 else
661 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
662
663 radv_emit_hw_hs(cmd_buffer, tcs);
664
665 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
666 pipeline->graphics.tess.tf_param);
667
668 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
669 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
670 pipeline->graphics.tess.ls_hs_config);
671 else
672 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
673 pipeline->graphics.tess.ls_hs_config);
674
675 struct ac_userdata_info *loc;
676
677 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
678 if (loc->sgpr_idx != -1) {
679 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
680 assert(loc->num_sgprs == 4);
681 assert(!loc->indirect);
682 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
683 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
684 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
685 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
686 pipeline->graphics.tess.num_tcs_input_cp << 26);
687 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
688 }
689
690 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
691 if (loc->sgpr_idx != -1) {
692 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
693 assert(loc->num_sgprs == 1);
694 assert(!loc->indirect);
695
696 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
697 pipeline->graphics.tess.offchip_layout);
698 }
699
700 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
701 if (loc->sgpr_idx != -1) {
702 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
703 assert(loc->num_sgprs == 1);
704 assert(!loc->indirect);
705
706 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
707 pipeline->graphics.tess.tcs_in_layout);
708 }
709 }
710
711 static void
712 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
713 struct radv_pipeline *pipeline)
714 {
715 struct radeon_winsys *ws = cmd_buffer->device->ws;
716 struct radv_shader_variant *gs;
717 uint64_t va;
718
719 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
720
721 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
722 if (!gs)
723 return;
724
725 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
726
727 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
728 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
729 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
730 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
731
732 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
733
734 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
735
736 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
737 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
738 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
739 radeon_emit(cmd_buffer->cs, 0);
740 radeon_emit(cmd_buffer->cs, 0);
741 radeon_emit(cmd_buffer->cs, 0);
742
743 uint32_t gs_num_invocations = gs->info.gs.invocations;
744 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
745 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
746 S_028B90_ENABLE(gs_num_invocations > 0));
747
748 va = ws->buffer_get_va(gs->bo);
749 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
750 si_cp_dma_prefetch(cmd_buffer, va, gs->code_size);
751 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
752 radeon_emit(cmd_buffer->cs, va >> 8);
753 radeon_emit(cmd_buffer->cs, va >> 40);
754 radeon_emit(cmd_buffer->cs, gs->rsrc1);
755 radeon_emit(cmd_buffer->cs, gs->rsrc2);
756
757 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
758
759 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
760 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
761 if (loc->sgpr_idx != -1) {
762 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
763 uint32_t num_entries = 64;
764 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
765
766 if (is_vi)
767 num_entries *= stride;
768
769 stride = S_008F04_STRIDE(stride);
770 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
771 radeon_emit(cmd_buffer->cs, stride);
772 radeon_emit(cmd_buffer->cs, num_entries);
773 }
774 }
775
776 static void
777 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
778 struct radv_pipeline *pipeline)
779 {
780 struct radeon_winsys *ws = cmd_buffer->device->ws;
781 struct radv_shader_variant *ps;
782 uint64_t va;
783 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
784 struct radv_blend_state *blend = &pipeline->graphics.blend;
785 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
786
787 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
788
789 va = ws->buffer_get_va(ps->bo);
790 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
791 si_cp_dma_prefetch(cmd_buffer, va, ps->code_size);
792
793 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
794 radeon_emit(cmd_buffer->cs, va >> 8);
795 radeon_emit(cmd_buffer->cs, va >> 40);
796 radeon_emit(cmd_buffer->cs, ps->rsrc1);
797 radeon_emit(cmd_buffer->cs, ps->rsrc2);
798
799 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
800 pipeline->graphics.db_shader_control);
801
802 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
803 ps->config.spi_ps_input_ena);
804
805 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
806 ps->config.spi_ps_input_addr);
807
808 if (ps->info.fs.force_persample)
809 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
810
811 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
812 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
813
814 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
815
816 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
817 pipeline->graphics.shader_z_format);
818
819 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
820
821 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
822 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
823
824 if (pipeline->graphics.ps_input_cntl_num) {
825 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
826 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
827 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
828 }
829 }
830 }
831
832 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
833 struct radv_pipeline *pipeline)
834 {
835 uint32_t vtx_reuse_depth = 30;
836 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
837 return;
838
839 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
840 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
841 vtx_reuse_depth = 14;
842 }
843 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
844 vtx_reuse_depth);
845 }
846
847 static void
848 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
849 struct radv_pipeline *pipeline)
850 {
851 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
852 return;
853
854 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
855 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
856 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
857 radv_update_multisample_state(cmd_buffer, pipeline);
858 radv_emit_vertex_shader(cmd_buffer, pipeline);
859 radv_emit_tess_shaders(cmd_buffer, pipeline);
860 radv_emit_geometry_shader(cmd_buffer, pipeline);
861 radv_emit_fragment_shader(cmd_buffer, pipeline);
862 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
863
864 cmd_buffer->scratch_size_needed =
865 MAX2(cmd_buffer->scratch_size_needed,
866 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
867
868 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
869 S_0286E8_WAVES(pipeline->max_waves) |
870 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
871
872 if (!cmd_buffer->state.emitted_pipeline ||
873 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
874 pipeline->graphics.can_use_guardband)
875 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
876 cmd_buffer->state.emitted_pipeline = pipeline;
877 }
878
879 static void
880 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
881 {
882 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
883 cmd_buffer->state.dynamic.viewport.viewports);
884 }
885
886 static void
887 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
888 {
889 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
890 si_write_scissors(cmd_buffer->cs, 0, count,
891 cmd_buffer->state.dynamic.scissor.scissors,
892 cmd_buffer->state.dynamic.viewport.viewports,
893 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
894 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
895 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
896 }
897
898 static void
899 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
900 int index,
901 struct radv_color_buffer_info *cb)
902 {
903 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
904 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
905 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
906 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
907 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
908 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
909 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
910 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
911 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
912 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
913 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
914 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
915 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
916
917 if (is_vi) { /* DCC BASE */
918 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
919 }
920 }
921
922 static void
923 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
924 struct radv_ds_buffer_info *ds,
925 struct radv_image *image,
926 VkImageLayout layout)
927 {
928 uint32_t db_z_info = ds->db_z_info;
929 uint32_t db_stencil_info = ds->db_stencil_info;
930
931 if (!radv_layout_has_htile(image, layout,
932 radv_image_queue_family_mask(image,
933 cmd_buffer->queue_family_index,
934 cmd_buffer->queue_family_index))) {
935 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
936 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
937 }
938
939 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
940 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
941
942 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
943 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
944 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
945 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
946 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
947 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
948 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
949 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
950 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
951 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
952
953 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
954 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
955 ds->pa_su_poly_offset_db_fmt_cntl);
956 }
957
958 void
959 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
960 struct radv_image *image,
961 VkClearDepthStencilValue ds_clear_value,
962 VkImageAspectFlags aspects)
963 {
964 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
965 va += image->offset + image->clear_value_offset;
966 unsigned reg_offset = 0, reg_count = 0;
967
968 if (!image->surface.htile_size || !aspects)
969 return;
970
971 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
972 ++reg_count;
973 } else {
974 ++reg_offset;
975 va += 4;
976 }
977 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
978 ++reg_count;
979
980 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
981
982 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
983 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
984 S_370_WR_CONFIRM(1) |
985 S_370_ENGINE_SEL(V_370_PFP));
986 radeon_emit(cmd_buffer->cs, va);
987 radeon_emit(cmd_buffer->cs, va >> 32);
988 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
989 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
990 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
991 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
992
993 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
994 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
995 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
996 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
997 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
998 }
999
1000 static void
1001 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1002 struct radv_image *image)
1003 {
1004 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1005 va += image->offset + image->clear_value_offset;
1006
1007 if (!image->surface.htile_size)
1008 return;
1009
1010 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1011
1012 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1013 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1014 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1015 COPY_DATA_COUNT_SEL);
1016 radeon_emit(cmd_buffer->cs, va);
1017 radeon_emit(cmd_buffer->cs, va >> 32);
1018 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1019 radeon_emit(cmd_buffer->cs, 0);
1020
1021 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1022 radeon_emit(cmd_buffer->cs, 0);
1023 }
1024
1025 void
1026 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1027 struct radv_image *image,
1028 int idx,
1029 uint32_t color_values[2])
1030 {
1031 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1032 va += image->offset + image->clear_value_offset;
1033
1034 if (!image->cmask.size && !image->surface.dcc_size)
1035 return;
1036
1037 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1038
1039 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1040 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1041 S_370_WR_CONFIRM(1) |
1042 S_370_ENGINE_SEL(V_370_PFP));
1043 radeon_emit(cmd_buffer->cs, va);
1044 radeon_emit(cmd_buffer->cs, va >> 32);
1045 radeon_emit(cmd_buffer->cs, color_values[0]);
1046 radeon_emit(cmd_buffer->cs, color_values[1]);
1047
1048 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1049 radeon_emit(cmd_buffer->cs, color_values[0]);
1050 radeon_emit(cmd_buffer->cs, color_values[1]);
1051 }
1052
1053 static void
1054 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1055 struct radv_image *image,
1056 int idx)
1057 {
1058 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
1059 va += image->offset + image->clear_value_offset;
1060
1061 if (!image->cmask.size && !image->surface.dcc_size)
1062 return;
1063
1064 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1065 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1066
1067 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1068 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1069 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1070 COPY_DATA_COUNT_SEL);
1071 radeon_emit(cmd_buffer->cs, va);
1072 radeon_emit(cmd_buffer->cs, va >> 32);
1073 radeon_emit(cmd_buffer->cs, reg >> 2);
1074 radeon_emit(cmd_buffer->cs, 0);
1075
1076 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1077 radeon_emit(cmd_buffer->cs, 0);
1078 }
1079
1080 void
1081 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1082 {
1083 int i;
1084 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1085 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1086
1087 for (i = 0; i < subpass->color_count; ++i) {
1088 int idx = subpass->color_attachments[i].attachment;
1089 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1090
1091 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1092
1093 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1094 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1095
1096 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1097 }
1098
1099 for (i = subpass->color_count; i < 8; i++)
1100 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1101 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1102
1103 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1104 int idx = subpass->depth_stencil_attachment.attachment;
1105 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1106 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1107 struct radv_image *image = att->attachment->image;
1108 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1109 uint32_t queue_mask = radv_image_queue_family_mask(image,
1110 cmd_buffer->queue_family_index,
1111 cmd_buffer->queue_family_index);
1112 /* We currently don't support writing decompressed HTILE */
1113 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1114 radv_layout_is_htile_compressed(image, layout, queue_mask));
1115
1116 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1117
1118 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1119 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1120 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1121 }
1122 radv_load_depth_clear_regs(cmd_buffer, image);
1123 } else {
1124 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1125 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1126 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1127 }
1128 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1129 S_028208_BR_X(framebuffer->width) |
1130 S_028208_BR_Y(framebuffer->height));
1131 }
1132
1133 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1134 {
1135 uint32_t db_count_control;
1136
1137 if(!cmd_buffer->state.active_occlusion_queries) {
1138 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1139 db_count_control = 0;
1140 } else {
1141 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1142 }
1143 } else {
1144 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1145 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1146 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1147 S_028004_ZPASS_ENABLE(1) |
1148 S_028004_SLICE_EVEN_ENABLE(1) |
1149 S_028004_SLICE_ODD_ENABLE(1);
1150 } else {
1151 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1152 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1153 }
1154 }
1155
1156 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1157 }
1158
1159 static void
1160 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1161 {
1162 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1163
1164 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1165 return;
1166
1167 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1168 radv_emit_viewport(cmd_buffer);
1169
1170 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1171 radv_emit_scissor(cmd_buffer);
1172
1173 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1174 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1175 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1176 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1177 }
1178
1179 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1180 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1181 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1182 }
1183
1184 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1185 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1186 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1187 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1188 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1189 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1190 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1191 S_028430_STENCILOPVAL(1));
1192 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1193 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1194 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1195 S_028434_STENCILOPVAL_BF(1));
1196 }
1197
1198 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1199 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1200 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1201 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1202 }
1203
1204 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1205 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1206 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1207 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1208 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1209
1210 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1211 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1212 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1213 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1214 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1215 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1216 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1217 }
1218 }
1219
1220 cmd_buffer->state.dirty = 0;
1221 }
1222
1223 static void
1224 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1225 struct radv_pipeline *pipeline,
1226 int idx,
1227 uint64_t va,
1228 gl_shader_stage stage)
1229 {
1230 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1231 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1232
1233 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1234 return;
1235
1236 assert(!desc_set_loc->indirect);
1237 assert(desc_set_loc->num_sgprs == 2);
1238 radeon_set_sh_reg_seq(cmd_buffer->cs,
1239 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1240 radeon_emit(cmd_buffer->cs, va);
1241 radeon_emit(cmd_buffer->cs, va >> 32);
1242 }
1243
1244 static void
1245 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1246 struct radv_pipeline *pipeline,
1247 VkShaderStageFlags stages,
1248 struct radv_descriptor_set *set,
1249 unsigned idx)
1250 {
1251 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1252 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1253 idx, set->va,
1254 MESA_SHADER_FRAGMENT);
1255
1256 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1257 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1258 idx, set->va,
1259 MESA_SHADER_VERTEX);
1260
1261 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1262 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1263 idx, set->va,
1264 MESA_SHADER_GEOMETRY);
1265
1266 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1267 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1268 idx, set->va,
1269 MESA_SHADER_TESS_CTRL);
1270
1271 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1272 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1273 idx, set->va,
1274 MESA_SHADER_TESS_EVAL);
1275
1276 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1277 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1278 idx, set->va,
1279 MESA_SHADER_COMPUTE);
1280 }
1281
1282 static void
1283 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1284 {
1285 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1286 uint32_t *ptr = NULL;
1287 unsigned bo_offset;
1288
1289 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32,
1290 &bo_offset,
1291 (void**) &ptr))
1292 return;
1293
1294 set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1295 set->va += bo_offset;
1296
1297 memcpy(ptr, set->mapped_ptr, set->size);
1298 }
1299
1300 static void
1301 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1302 struct radv_pipeline *pipeline)
1303 {
1304 uint32_t size = MAX_SETS * 2 * 4;
1305 uint32_t offset;
1306 void *ptr;
1307
1308 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1309 256, &offset, &ptr))
1310 return;
1311
1312 for (unsigned i = 0; i < MAX_SETS; i++) {
1313 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1314 uint64_t set_va = 0;
1315 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1316 if (set)
1317 set_va = set->va;
1318 uptr[0] = set_va & 0xffffffff;
1319 uptr[1] = set_va >> 32;
1320 }
1321
1322 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1323 va += offset;
1324
1325 if (pipeline->shaders[MESA_SHADER_VERTEX])
1326 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1327 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1328
1329 if (pipeline->shaders[MESA_SHADER_FRAGMENT])
1330 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1331 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1332
1333 if (radv_pipeline_has_gs(pipeline))
1334 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1335 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1336
1337 if (radv_pipeline_has_tess(pipeline))
1338 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL,
1339 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1340
1341 if (radv_pipeline_has_tess(pipeline))
1342 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL,
1343 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1344
1345 if (pipeline->shaders[MESA_SHADER_COMPUTE])
1346 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1347 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1348 }
1349
1350 static void
1351 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1352 struct radv_pipeline *pipeline,
1353 VkShaderStageFlags stages)
1354 {
1355 unsigned i;
1356
1357 if (!cmd_buffer->state.descriptors_dirty)
1358 return;
1359
1360 if (cmd_buffer->state.push_descriptors_dirty)
1361 radv_flush_push_descriptors(cmd_buffer);
1362
1363 if (pipeline->need_indirect_descriptor_sets) {
1364 radv_flush_indirect_descriptor_sets(cmd_buffer, pipeline);
1365 }
1366
1367 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1368 cmd_buffer->cs,
1369 MAX_SETS * MESA_SHADER_STAGES * 4);
1370
1371 for (i = 0; i < MAX_SETS; i++) {
1372 if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
1373 continue;
1374 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1375 if (!set)
1376 continue;
1377
1378 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1379 }
1380 cmd_buffer->state.descriptors_dirty = 0;
1381 cmd_buffer->state.push_descriptors_dirty = false;
1382 assert(cmd_buffer->cs->cdw <= cdw_max);
1383 }
1384
1385 static void
1386 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1387 struct radv_pipeline *pipeline,
1388 VkShaderStageFlags stages)
1389 {
1390 struct radv_pipeline_layout *layout = pipeline->layout;
1391 unsigned offset;
1392 void *ptr;
1393 uint64_t va;
1394
1395 stages &= cmd_buffer->push_constant_stages;
1396 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1397 return;
1398
1399 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1400 16 * layout->dynamic_offset_count,
1401 256, &offset, &ptr))
1402 return;
1403
1404 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1405 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1406 16 * layout->dynamic_offset_count);
1407
1408 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1409 va += offset;
1410
1411 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1412 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1413 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1414 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1415 AC_UD_PUSH_CONSTANTS, va);
1416
1417 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1418 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1419 AC_UD_PUSH_CONSTANTS, va);
1420
1421 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1422 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1423 AC_UD_PUSH_CONSTANTS, va);
1424
1425 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1426 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL,
1427 AC_UD_PUSH_CONSTANTS, va);
1428
1429 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1430 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL,
1431 AC_UD_PUSH_CONSTANTS, va);
1432
1433 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1434 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1435 AC_UD_PUSH_CONSTANTS, va);
1436
1437 cmd_buffer->push_constant_stages &= ~stages;
1438 assert(cmd_buffer->cs->cdw <= cdw_max);
1439 }
1440
1441 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1442 bool indexed_draw)
1443 {
1444 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1445
1446 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1447 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1448 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1449 primitive_reset_en);
1450 }
1451
1452 if (primitive_reset_en) {
1453 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1454
1455 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1456 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1457 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1458 primitive_reset_index);
1459 }
1460 }
1461 }
1462
1463 static void
1464 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1465 bool indexed_draw, bool instanced_draw,
1466 bool indirect_draw,
1467 uint32_t draw_vertex_count)
1468 {
1469 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1470 struct radv_device *device = cmd_buffer->device;
1471 uint32_t ia_multi_vgt_param;
1472
1473 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1474 cmd_buffer->cs, 4096);
1475
1476 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1477 cmd_buffer->state.pipeline->num_vertex_attribs &&
1478 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1479 unsigned vb_offset;
1480 void *vb_ptr;
1481 uint32_t i = 0;
1482 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1483 uint64_t va;
1484
1485 /* allocate some descriptor state for vertex buffers */
1486 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1487 &vb_offset, &vb_ptr);
1488
1489 for (i = 0; i < num_attribs; i++) {
1490 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1491 uint32_t offset;
1492 int vb = cmd_buffer->state.pipeline->va_binding[i];
1493 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1494 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1495
1496 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1497 va = device->ws->buffer_get_va(buffer->bo);
1498
1499 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1500 va += offset + buffer->offset;
1501 desc[0] = va;
1502 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1503 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1504 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1505 else
1506 desc[2] = buffer->size - offset;
1507 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1508 }
1509
1510 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1511 va += vb_offset;
1512
1513 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1514 AC_UD_VS_VERTEX_BUFFERS, va);
1515 }
1516
1517 cmd_buffer->state.vertex_descriptors_dirty = false;
1518 cmd_buffer->state.vb_dirty = 0;
1519 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1520 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1521
1522 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1523 radv_emit_framebuffer_state(cmd_buffer);
1524
1525 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1526 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1527 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1528 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1529 else
1530 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1531 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1532 }
1533
1534 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1535 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1536
1537 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1538 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1539 } else {
1540 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1541 }
1542 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1543 }
1544
1545 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1546
1547 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1548
1549 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1550 VK_SHADER_STAGE_ALL_GRAPHICS);
1551 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1552 VK_SHADER_STAGE_ALL_GRAPHICS);
1553
1554 assert(cmd_buffer->cs->cdw <= cdw_max);
1555
1556 si_emit_cache_flush(cmd_buffer);
1557 }
1558
1559 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1560 VkPipelineStageFlags src_stage_mask)
1561 {
1562 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1563 VK_PIPELINE_STAGE_TRANSFER_BIT |
1564 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1565 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1566 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1567 }
1568
1569 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1570 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1571 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1572 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1573 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1574 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1575 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1576 VK_PIPELINE_STAGE_TRANSFER_BIT |
1577 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1578 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1579 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1580 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1581 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1582 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1583 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1584 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1585 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1586 }
1587 }
1588
1589 static enum radv_cmd_flush_bits
1590 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1591 VkAccessFlags src_flags)
1592 {
1593 enum radv_cmd_flush_bits flush_bits = 0;
1594 uint32_t b;
1595 for_each_bit(b, src_flags) {
1596 switch ((VkAccessFlagBits)(1 << b)) {
1597 case VK_ACCESS_SHADER_WRITE_BIT:
1598 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1599 break;
1600 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1601 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1602 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1603 break;
1604 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1605 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1606 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1607 break;
1608 case VK_ACCESS_TRANSFER_WRITE_BIT:
1609 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1610 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1611 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1612 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1613 RADV_CMD_FLAG_INV_GLOBAL_L2;
1614 break;
1615 default:
1616 break;
1617 }
1618 }
1619 return flush_bits;
1620 }
1621
1622 static enum radv_cmd_flush_bits
1623 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1624 VkAccessFlags dst_flags,
1625 struct radv_image *image)
1626 {
1627 enum radv_cmd_flush_bits flush_bits = 0;
1628 uint32_t b;
1629 for_each_bit(b, dst_flags) {
1630 switch ((VkAccessFlagBits)(1 << b)) {
1631 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1632 case VK_ACCESS_INDEX_READ_BIT:
1633 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1634 break;
1635 case VK_ACCESS_UNIFORM_READ_BIT:
1636 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1637 break;
1638 case VK_ACCESS_SHADER_READ_BIT:
1639 case VK_ACCESS_TRANSFER_READ_BIT:
1640 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1641 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1642 RADV_CMD_FLAG_INV_GLOBAL_L2;
1643 break;
1644 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1645 /* TODO: change to image && when the image gets passed
1646 * through from the subpass. */
1647 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1648 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1649 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1650 break;
1651 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1652 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1653 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1654 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1655 break;
1656 default:
1657 break;
1658 }
1659 }
1660 return flush_bits;
1661 }
1662
1663 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1664 {
1665 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1666 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1667 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1668 NULL);
1669 }
1670
1671 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1672 VkAttachmentReference att)
1673 {
1674 unsigned idx = att.attachment;
1675 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1676 VkImageSubresourceRange range;
1677 range.aspectMask = 0;
1678 range.baseMipLevel = view->base_mip;
1679 range.levelCount = 1;
1680 range.baseArrayLayer = view->base_layer;
1681 range.layerCount = cmd_buffer->state.framebuffer->layers;
1682
1683 radv_handle_image_transition(cmd_buffer,
1684 view->image,
1685 cmd_buffer->state.attachments[idx].current_layout,
1686 att.layout, 0, 0, &range,
1687 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1688
1689 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1690
1691
1692 }
1693
1694 void
1695 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1696 const struct radv_subpass *subpass, bool transitions)
1697 {
1698 if (transitions) {
1699 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1700
1701 for (unsigned i = 0; i < subpass->color_count; ++i) {
1702 radv_handle_subpass_image_transition(cmd_buffer,
1703 subpass->color_attachments[i]);
1704 }
1705
1706 for (unsigned i = 0; i < subpass->input_count; ++i) {
1707 radv_handle_subpass_image_transition(cmd_buffer,
1708 subpass->input_attachments[i]);
1709 }
1710
1711 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1712 radv_handle_subpass_image_transition(cmd_buffer,
1713 subpass->depth_stencil_attachment);
1714 }
1715 }
1716
1717 cmd_buffer->state.subpass = subpass;
1718
1719 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1720 }
1721
1722 static void
1723 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1724 struct radv_render_pass *pass,
1725 const VkRenderPassBeginInfo *info)
1726 {
1727 struct radv_cmd_state *state = &cmd_buffer->state;
1728
1729 if (pass->attachment_count == 0) {
1730 state->attachments = NULL;
1731 return;
1732 }
1733
1734 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1735 pass->attachment_count *
1736 sizeof(state->attachments[0]),
1737 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1738 if (state->attachments == NULL) {
1739 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1740 abort();
1741 }
1742
1743 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1744 struct radv_render_pass_attachment *att = &pass->attachments[i];
1745 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1746 VkImageAspectFlags clear_aspects = 0;
1747
1748 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1749 /* color attachment */
1750 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1751 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1752 }
1753 } else {
1754 /* depthstencil attachment */
1755 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1756 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1757 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1758 }
1759 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1760 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1761 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1762 }
1763 }
1764
1765 state->attachments[i].pending_clear_aspects = clear_aspects;
1766 if (clear_aspects && info) {
1767 assert(info->clearValueCount > i);
1768 state->attachments[i].clear_value = info->pClearValues[i];
1769 }
1770
1771 state->attachments[i].current_layout = att->initial_layout;
1772 }
1773 }
1774
1775 VkResult radv_AllocateCommandBuffers(
1776 VkDevice _device,
1777 const VkCommandBufferAllocateInfo *pAllocateInfo,
1778 VkCommandBuffer *pCommandBuffers)
1779 {
1780 RADV_FROM_HANDLE(radv_device, device, _device);
1781 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1782
1783 VkResult result = VK_SUCCESS;
1784 uint32_t i;
1785
1786 memset(pCommandBuffers, 0,
1787 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1788
1789 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1790
1791 if (!list_empty(&pool->free_cmd_buffers)) {
1792 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1793
1794 list_del(&cmd_buffer->pool_link);
1795 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1796
1797 radv_reset_cmd_buffer(cmd_buffer);
1798 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1799 cmd_buffer->level = pAllocateInfo->level;
1800
1801 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1802 result = VK_SUCCESS;
1803 } else {
1804 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1805 &pCommandBuffers[i]);
1806 }
1807 if (result != VK_SUCCESS)
1808 break;
1809 }
1810
1811 if (result != VK_SUCCESS)
1812 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1813 i, pCommandBuffers);
1814
1815 return result;
1816 }
1817
1818 void radv_FreeCommandBuffers(
1819 VkDevice device,
1820 VkCommandPool commandPool,
1821 uint32_t commandBufferCount,
1822 const VkCommandBuffer *pCommandBuffers)
1823 {
1824 for (uint32_t i = 0; i < commandBufferCount; i++) {
1825 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1826
1827 if (cmd_buffer) {
1828 if (cmd_buffer->pool) {
1829 list_del(&cmd_buffer->pool_link);
1830 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1831 } else
1832 radv_cmd_buffer_destroy(cmd_buffer);
1833
1834 }
1835 }
1836 }
1837
1838 VkResult radv_ResetCommandBuffer(
1839 VkCommandBuffer commandBuffer,
1840 VkCommandBufferResetFlags flags)
1841 {
1842 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1843 radv_reset_cmd_buffer(cmd_buffer);
1844 return VK_SUCCESS;
1845 }
1846
1847 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1848 {
1849 struct radv_device *device = cmd_buffer->device;
1850 if (device->gfx_init) {
1851 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1852 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1853 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1854 radeon_emit(cmd_buffer->cs, va);
1855 radeon_emit(cmd_buffer->cs, (va >> 32) & 0xffff);
1856 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1857 } else
1858 si_init_config(cmd_buffer);
1859 }
1860
1861 VkResult radv_BeginCommandBuffer(
1862 VkCommandBuffer commandBuffer,
1863 const VkCommandBufferBeginInfo *pBeginInfo)
1864 {
1865 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1866 radv_reset_cmd_buffer(cmd_buffer);
1867
1868 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1869 cmd_buffer->state.last_primitive_reset_en = -1;
1870
1871 /* setup initial configuration into command buffer */
1872 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1873 switch (cmd_buffer->queue_family_index) {
1874 case RADV_QUEUE_GENERAL:
1875 emit_gfx_buffer_state(cmd_buffer);
1876 radv_set_db_count_control(cmd_buffer);
1877 break;
1878 case RADV_QUEUE_COMPUTE:
1879 si_init_compute(cmd_buffer);
1880 break;
1881 case RADV_QUEUE_TRANSFER:
1882 default:
1883 break;
1884 }
1885 }
1886
1887 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1888 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1889 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1890
1891 struct radv_subpass *subpass =
1892 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1893
1894 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1895 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1896 }
1897
1898 radv_cmd_buffer_trace_emit(cmd_buffer);
1899 return VK_SUCCESS;
1900 }
1901
1902 void radv_CmdBindVertexBuffers(
1903 VkCommandBuffer commandBuffer,
1904 uint32_t firstBinding,
1905 uint32_t bindingCount,
1906 const VkBuffer* pBuffers,
1907 const VkDeviceSize* pOffsets)
1908 {
1909 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1910 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1911
1912 /* We have to defer setting up vertex buffer since we need the buffer
1913 * stride from the pipeline. */
1914
1915 assert(firstBinding + bindingCount < MAX_VBS);
1916 for (uint32_t i = 0; i < bindingCount; i++) {
1917 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1918 vb[firstBinding + i].offset = pOffsets[i];
1919 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1920 }
1921 }
1922
1923 void radv_CmdBindIndexBuffer(
1924 VkCommandBuffer commandBuffer,
1925 VkBuffer buffer,
1926 VkDeviceSize offset,
1927 VkIndexType indexType)
1928 {
1929 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1930
1931 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1932 cmd_buffer->state.index_offset = offset;
1933 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1934 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1935 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1936 }
1937
1938
1939 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1940 struct radv_descriptor_set *set,
1941 unsigned idx)
1942 {
1943 struct radeon_winsys *ws = cmd_buffer->device->ws;
1944
1945 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
1946
1947 cmd_buffer->state.descriptors[idx] = set;
1948 cmd_buffer->state.descriptors_dirty |= (1u << idx);
1949 if (!set)
1950 return;
1951
1952 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1953 if (set->descriptors[j])
1954 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1955
1956 if(set->bo)
1957 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1958 }
1959
1960 void radv_CmdBindDescriptorSets(
1961 VkCommandBuffer commandBuffer,
1962 VkPipelineBindPoint pipelineBindPoint,
1963 VkPipelineLayout _layout,
1964 uint32_t firstSet,
1965 uint32_t descriptorSetCount,
1966 const VkDescriptorSet* pDescriptorSets,
1967 uint32_t dynamicOffsetCount,
1968 const uint32_t* pDynamicOffsets)
1969 {
1970 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1971 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1972 unsigned dyn_idx = 0;
1973
1974 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1975 unsigned idx = i + firstSet;
1976 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1977 radv_bind_descriptor_set(cmd_buffer, set, idx);
1978
1979 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1980 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1981 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1982 assert(dyn_idx < dynamicOffsetCount);
1983
1984 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1985 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1986 dst[0] = va;
1987 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1988 dst[2] = range->size;
1989 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1990 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1991 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1992 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1993 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1994 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1995 cmd_buffer->push_constant_stages |=
1996 set->layout->dynamic_shader_stages;
1997 }
1998 }
1999 }
2000
2001 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2002 struct radv_descriptor_set *set,
2003 struct radv_descriptor_set_layout *layout)
2004 {
2005 set->size = layout->size;
2006 set->layout = layout;
2007
2008 if (cmd_buffer->push_descriptors.capacity < set->size) {
2009 size_t new_size = MAX2(set->size, 1024);
2010 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2011 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2012
2013 free(set->mapped_ptr);
2014 set->mapped_ptr = malloc(new_size);
2015
2016 if (!set->mapped_ptr) {
2017 cmd_buffer->push_descriptors.capacity = 0;
2018 cmd_buffer->record_fail = true;
2019 return false;
2020 }
2021
2022 cmd_buffer->push_descriptors.capacity = new_size;
2023 }
2024
2025 return true;
2026 }
2027
2028 void radv_meta_push_descriptor_set(
2029 struct radv_cmd_buffer* cmd_buffer,
2030 VkPipelineBindPoint pipelineBindPoint,
2031 VkPipelineLayout _layout,
2032 uint32_t set,
2033 uint32_t descriptorWriteCount,
2034 const VkWriteDescriptorSet* pDescriptorWrites)
2035 {
2036 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2037 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2038 unsigned bo_offset;
2039
2040 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2041
2042 push_set->size = layout->set[set].layout->size;
2043 push_set->layout = layout->set[set].layout;
2044
2045 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2046 &bo_offset,
2047 (void**) &push_set->mapped_ptr))
2048 return;
2049
2050 push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
2051 push_set->va += bo_offset;
2052
2053 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2054 radv_descriptor_set_to_handle(push_set),
2055 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2056
2057 cmd_buffer->state.descriptors[set] = push_set;
2058 cmd_buffer->state.descriptors_dirty |= (1u << set);
2059 }
2060
2061 void radv_CmdPushDescriptorSetKHR(
2062 VkCommandBuffer commandBuffer,
2063 VkPipelineBindPoint pipelineBindPoint,
2064 VkPipelineLayout _layout,
2065 uint32_t set,
2066 uint32_t descriptorWriteCount,
2067 const VkWriteDescriptorSet* pDescriptorWrites)
2068 {
2069 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2070 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2071 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2072
2073 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2074
2075 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2076 return;
2077
2078 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2079 radv_descriptor_set_to_handle(push_set),
2080 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2081
2082 cmd_buffer->state.descriptors[set] = push_set;
2083 cmd_buffer->state.descriptors_dirty |= (1u << set);
2084 cmd_buffer->state.push_descriptors_dirty = true;
2085 }
2086
2087 void radv_CmdPushDescriptorSetWithTemplateKHR(
2088 VkCommandBuffer commandBuffer,
2089 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2090 VkPipelineLayout _layout,
2091 uint32_t set,
2092 const void* pData)
2093 {
2094 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2095 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2096 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2097
2098 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2099
2100 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2101 return;
2102
2103 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2104 descriptorUpdateTemplate, pData);
2105
2106 cmd_buffer->state.descriptors[set] = push_set;
2107 cmd_buffer->state.descriptors_dirty |= (1u << set);
2108 cmd_buffer->state.push_descriptors_dirty = true;
2109 }
2110
2111 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2112 VkPipelineLayout layout,
2113 VkShaderStageFlags stageFlags,
2114 uint32_t offset,
2115 uint32_t size,
2116 const void* pValues)
2117 {
2118 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2119 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2120 cmd_buffer->push_constant_stages |= stageFlags;
2121 }
2122
2123 VkResult radv_EndCommandBuffer(
2124 VkCommandBuffer commandBuffer)
2125 {
2126 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2127
2128 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
2129 si_emit_cache_flush(cmd_buffer);
2130
2131 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
2132 cmd_buffer->record_fail)
2133 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2134 return VK_SUCCESS;
2135 }
2136
2137 static void
2138 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2139 {
2140 struct radeon_winsys *ws = cmd_buffer->device->ws;
2141 struct radv_shader_variant *compute_shader;
2142 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2143 uint64_t va;
2144
2145 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2146 return;
2147
2148 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2149
2150 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2151 va = ws->buffer_get_va(compute_shader->bo);
2152
2153 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2154 si_cp_dma_prefetch(cmd_buffer, va, compute_shader->code_size);
2155
2156 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2157 cmd_buffer->cs, 16);
2158
2159 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2160 radeon_emit(cmd_buffer->cs, va >> 8);
2161 radeon_emit(cmd_buffer->cs, va >> 40);
2162
2163 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2164 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2165 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2166
2167
2168 cmd_buffer->compute_scratch_size_needed =
2169 MAX2(cmd_buffer->compute_scratch_size_needed,
2170 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2171
2172 /* change these once we have scratch support */
2173 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2174 S_00B860_WAVES(pipeline->max_waves) |
2175 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2176
2177 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2178 radeon_emit(cmd_buffer->cs,
2179 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2180 radeon_emit(cmd_buffer->cs,
2181 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2182 radeon_emit(cmd_buffer->cs,
2183 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2184
2185 assert(cmd_buffer->cs->cdw <= cdw_max);
2186 }
2187
2188
2189 void radv_CmdBindPipeline(
2190 VkCommandBuffer commandBuffer,
2191 VkPipelineBindPoint pipelineBindPoint,
2192 VkPipeline _pipeline)
2193 {
2194 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2195 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2196
2197 for (unsigned i = 0; i < MAX_SETS; i++) {
2198 if (cmd_buffer->state.descriptors[i])
2199 cmd_buffer->state.descriptors_dirty |= (1u << i);
2200 }
2201
2202 switch (pipelineBindPoint) {
2203 case VK_PIPELINE_BIND_POINT_COMPUTE:
2204 cmd_buffer->state.compute_pipeline = pipeline;
2205 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2206 break;
2207 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2208 cmd_buffer->state.pipeline = pipeline;
2209 cmd_buffer->state.vertex_descriptors_dirty = true;
2210 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2211 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2212
2213 /* Apply the dynamic state from the pipeline */
2214 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2215 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2216 &pipeline->dynamic_state,
2217 pipeline->dynamic_state_mask);
2218
2219 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2220 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2221 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2222 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2223
2224 if (radv_pipeline_has_tess(pipeline))
2225 cmd_buffer->tess_rings_needed = true;
2226
2227 if (radv_pipeline_has_gs(pipeline)) {
2228 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2229 AC_UD_SCRATCH_RING_OFFSETS);
2230 if (cmd_buffer->ring_offsets_idx == -1)
2231 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2232 else if (loc->sgpr_idx != -1)
2233 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2234 }
2235 break;
2236 default:
2237 assert(!"invalid bind point");
2238 break;
2239 }
2240 }
2241
2242 void radv_CmdSetViewport(
2243 VkCommandBuffer commandBuffer,
2244 uint32_t firstViewport,
2245 uint32_t viewportCount,
2246 const VkViewport* pViewports)
2247 {
2248 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2249
2250 const uint32_t total_count = firstViewport + viewportCount;
2251 if (cmd_buffer->state.dynamic.viewport.count < total_count)
2252 cmd_buffer->state.dynamic.viewport.count = total_count;
2253
2254 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2255 pViewports, viewportCount * sizeof(*pViewports));
2256
2257 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2258 }
2259
2260 void radv_CmdSetScissor(
2261 VkCommandBuffer commandBuffer,
2262 uint32_t firstScissor,
2263 uint32_t scissorCount,
2264 const VkRect2D* pScissors)
2265 {
2266 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2267
2268 const uint32_t total_count = firstScissor + scissorCount;
2269 if (cmd_buffer->state.dynamic.scissor.count < total_count)
2270 cmd_buffer->state.dynamic.scissor.count = total_count;
2271
2272 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2273 pScissors, scissorCount * sizeof(*pScissors));
2274 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2275 }
2276
2277 void radv_CmdSetLineWidth(
2278 VkCommandBuffer commandBuffer,
2279 float lineWidth)
2280 {
2281 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2282 cmd_buffer->state.dynamic.line_width = lineWidth;
2283 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2284 }
2285
2286 void radv_CmdSetDepthBias(
2287 VkCommandBuffer commandBuffer,
2288 float depthBiasConstantFactor,
2289 float depthBiasClamp,
2290 float depthBiasSlopeFactor)
2291 {
2292 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2293
2294 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2295 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2296 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2297
2298 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2299 }
2300
2301 void radv_CmdSetBlendConstants(
2302 VkCommandBuffer commandBuffer,
2303 const float blendConstants[4])
2304 {
2305 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2306
2307 memcpy(cmd_buffer->state.dynamic.blend_constants,
2308 blendConstants, sizeof(float) * 4);
2309
2310 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2311 }
2312
2313 void radv_CmdSetDepthBounds(
2314 VkCommandBuffer commandBuffer,
2315 float minDepthBounds,
2316 float maxDepthBounds)
2317 {
2318 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2319
2320 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2321 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2322
2323 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2324 }
2325
2326 void radv_CmdSetStencilCompareMask(
2327 VkCommandBuffer commandBuffer,
2328 VkStencilFaceFlags faceMask,
2329 uint32_t compareMask)
2330 {
2331 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2332
2333 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2334 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2335 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2336 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2337
2338 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2339 }
2340
2341 void radv_CmdSetStencilWriteMask(
2342 VkCommandBuffer commandBuffer,
2343 VkStencilFaceFlags faceMask,
2344 uint32_t writeMask)
2345 {
2346 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2347
2348 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2349 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2350 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2351 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2352
2353 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2354 }
2355
2356 void radv_CmdSetStencilReference(
2357 VkCommandBuffer commandBuffer,
2358 VkStencilFaceFlags faceMask,
2359 uint32_t reference)
2360 {
2361 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2362
2363 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2364 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2365 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2366 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2367
2368 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2369 }
2370
2371
2372 void radv_CmdExecuteCommands(
2373 VkCommandBuffer commandBuffer,
2374 uint32_t commandBufferCount,
2375 const VkCommandBuffer* pCmdBuffers)
2376 {
2377 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2378
2379 /* Emit pending flushes on primary prior to executing secondary */
2380 si_emit_cache_flush(primary);
2381
2382 for (uint32_t i = 0; i < commandBufferCount; i++) {
2383 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2384
2385 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2386 secondary->scratch_size_needed);
2387 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2388 secondary->compute_scratch_size_needed);
2389
2390 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2391 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2392 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2393 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2394 if (secondary->tess_rings_needed)
2395 primary->tess_rings_needed = true;
2396 if (secondary->sample_positions_needed)
2397 primary->sample_positions_needed = true;
2398
2399 if (secondary->ring_offsets_idx != -1) {
2400 if (primary->ring_offsets_idx == -1)
2401 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2402 else
2403 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2404 }
2405 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2406 }
2407
2408 /* if we execute secondary we need to re-emit out pipelines */
2409 if (commandBufferCount) {
2410 primary->state.emitted_pipeline = NULL;
2411 primary->state.emitted_compute_pipeline = NULL;
2412 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2413 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2414 primary->state.last_primitive_reset_en = -1;
2415 primary->state.last_primitive_reset_index = 0;
2416 }
2417 }
2418
2419 VkResult radv_CreateCommandPool(
2420 VkDevice _device,
2421 const VkCommandPoolCreateInfo* pCreateInfo,
2422 const VkAllocationCallbacks* pAllocator,
2423 VkCommandPool* pCmdPool)
2424 {
2425 RADV_FROM_HANDLE(radv_device, device, _device);
2426 struct radv_cmd_pool *pool;
2427
2428 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2429 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2430 if (pool == NULL)
2431 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2432
2433 if (pAllocator)
2434 pool->alloc = *pAllocator;
2435 else
2436 pool->alloc = device->alloc;
2437
2438 list_inithead(&pool->cmd_buffers);
2439 list_inithead(&pool->free_cmd_buffers);
2440
2441 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2442
2443 *pCmdPool = radv_cmd_pool_to_handle(pool);
2444
2445 return VK_SUCCESS;
2446
2447 }
2448
2449 void radv_DestroyCommandPool(
2450 VkDevice _device,
2451 VkCommandPool commandPool,
2452 const VkAllocationCallbacks* pAllocator)
2453 {
2454 RADV_FROM_HANDLE(radv_device, device, _device);
2455 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2456
2457 if (!pool)
2458 return;
2459
2460 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2461 &pool->cmd_buffers, pool_link) {
2462 radv_cmd_buffer_destroy(cmd_buffer);
2463 }
2464
2465 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2466 &pool->free_cmd_buffers, pool_link) {
2467 radv_cmd_buffer_destroy(cmd_buffer);
2468 }
2469
2470 vk_free2(&device->alloc, pAllocator, pool);
2471 }
2472
2473 VkResult radv_ResetCommandPool(
2474 VkDevice device,
2475 VkCommandPool commandPool,
2476 VkCommandPoolResetFlags flags)
2477 {
2478 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2479
2480 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2481 &pool->cmd_buffers, pool_link) {
2482 radv_reset_cmd_buffer(cmd_buffer);
2483 }
2484
2485 return VK_SUCCESS;
2486 }
2487
2488 void radv_TrimCommandPoolKHR(
2489 VkDevice device,
2490 VkCommandPool commandPool,
2491 VkCommandPoolTrimFlagsKHR flags)
2492 {
2493 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2494
2495 if (!pool)
2496 return;
2497
2498 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2499 &pool->free_cmd_buffers, pool_link) {
2500 radv_cmd_buffer_destroy(cmd_buffer);
2501 }
2502 }
2503
2504 void radv_CmdBeginRenderPass(
2505 VkCommandBuffer commandBuffer,
2506 const VkRenderPassBeginInfo* pRenderPassBegin,
2507 VkSubpassContents contents)
2508 {
2509 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2510 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2511 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2512
2513 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2514 cmd_buffer->cs, 2048);
2515
2516 cmd_buffer->state.framebuffer = framebuffer;
2517 cmd_buffer->state.pass = pass;
2518 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2519 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2520
2521 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2522 assert(cmd_buffer->cs->cdw <= cdw_max);
2523
2524 radv_cmd_buffer_clear_subpass(cmd_buffer);
2525 }
2526
2527 void radv_CmdNextSubpass(
2528 VkCommandBuffer commandBuffer,
2529 VkSubpassContents contents)
2530 {
2531 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2532
2533 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2534
2535 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2536 2048);
2537
2538 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2539 radv_cmd_buffer_clear_subpass(cmd_buffer);
2540 }
2541
2542 void radv_CmdDraw(
2543 VkCommandBuffer commandBuffer,
2544 uint32_t vertexCount,
2545 uint32_t instanceCount,
2546 uint32_t firstVertex,
2547 uint32_t firstInstance)
2548 {
2549 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2550
2551 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2552
2553 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2554
2555 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2556 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2557 if (loc->sgpr_idx != -1) {
2558 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2559 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2560 int vs_num = 2;
2561 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2562 vs_num = 3;
2563
2564 assert (loc->num_sgprs == vs_num);
2565 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
2566 radeon_emit(cmd_buffer->cs, firstVertex);
2567 radeon_emit(cmd_buffer->cs, firstInstance);
2568 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2569 radeon_emit(cmd_buffer->cs, 0);
2570 }
2571 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2572 radeon_emit(cmd_buffer->cs, instanceCount);
2573
2574 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2575 radeon_emit(cmd_buffer->cs, vertexCount);
2576 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2577 S_0287F0_USE_OPAQUE(0));
2578
2579 assert(cmd_buffer->cs->cdw <= cdw_max);
2580
2581 radv_cmd_buffer_trace_emit(cmd_buffer);
2582 }
2583
2584 void radv_CmdDrawIndexed(
2585 VkCommandBuffer commandBuffer,
2586 uint32_t indexCount,
2587 uint32_t instanceCount,
2588 uint32_t firstIndex,
2589 int32_t vertexOffset,
2590 uint32_t firstInstance)
2591 {
2592 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2593 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2594 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2595 uint64_t index_va;
2596
2597 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2598
2599 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2600
2601 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2602 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2603
2604 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2605 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2606 if (loc->sgpr_idx != -1) {
2607 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2608 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2609 int vs_num = 2;
2610 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2611 vs_num = 3;
2612
2613 assert (loc->num_sgprs == vs_num);
2614 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
2615 radeon_emit(cmd_buffer->cs, vertexOffset);
2616 radeon_emit(cmd_buffer->cs, firstInstance);
2617 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2618 radeon_emit(cmd_buffer->cs, 0);
2619 }
2620 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2621 radeon_emit(cmd_buffer->cs, instanceCount);
2622
2623 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2624 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2625 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2626 radeon_emit(cmd_buffer->cs, index_max_size);
2627 radeon_emit(cmd_buffer->cs, index_va);
2628 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2629 radeon_emit(cmd_buffer->cs, indexCount);
2630 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2631
2632 assert(cmd_buffer->cs->cdw <= cdw_max);
2633 radv_cmd_buffer_trace_emit(cmd_buffer);
2634 }
2635
2636 static void
2637 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2638 VkBuffer _buffer,
2639 VkDeviceSize offset,
2640 VkBuffer _count_buffer,
2641 VkDeviceSize count_offset,
2642 uint32_t draw_count,
2643 uint32_t stride,
2644 bool indexed)
2645 {
2646 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2647 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2648 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2649 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2650 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2651 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2652 indirect_va += offset + buffer->offset;
2653 uint64_t count_va = 0;
2654
2655 if (count_buffer) {
2656 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2657 count_va += count_offset + count_buffer->offset;
2658 }
2659
2660 if (!draw_count)
2661 return;
2662
2663 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2664
2665 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2666 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2667 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2668 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2669 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2670 assert(loc->sgpr_idx != -1);
2671 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2672 radeon_emit(cs, 1);
2673 radeon_emit(cs, indirect_va);
2674 radeon_emit(cs, indirect_va >> 32);
2675
2676 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2677 PKT3_DRAW_INDIRECT_MULTI,
2678 8, false));
2679 radeon_emit(cs, 0);
2680 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2681 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2682 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2683 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2684 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2685 radeon_emit(cs, draw_count); /* count */
2686 radeon_emit(cs, count_va); /* count_addr */
2687 radeon_emit(cs, count_va >> 32);
2688 radeon_emit(cs, stride); /* stride */
2689 radeon_emit(cs, di_src_sel);
2690 radv_cmd_buffer_trace_emit(cmd_buffer);
2691 }
2692
2693 static void
2694 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2695 VkBuffer buffer,
2696 VkDeviceSize offset,
2697 VkBuffer countBuffer,
2698 VkDeviceSize countBufferOffset,
2699 uint32_t maxDrawCount,
2700 uint32_t stride)
2701 {
2702 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2703 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
2704
2705 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2706 cmd_buffer->cs, 14);
2707
2708 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2709 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2710
2711 assert(cmd_buffer->cs->cdw <= cdw_max);
2712 }
2713
2714 static void
2715 radv_cmd_draw_indexed_indirect_count(
2716 VkCommandBuffer commandBuffer,
2717 VkBuffer buffer,
2718 VkDeviceSize offset,
2719 VkBuffer countBuffer,
2720 VkDeviceSize countBufferOffset,
2721 uint32_t maxDrawCount,
2722 uint32_t stride)
2723 {
2724 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2725 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2726 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2727 uint64_t index_va;
2728 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
2729
2730 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2731 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2732
2733 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2734
2735 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2736 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2737
2738 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2739 radeon_emit(cmd_buffer->cs, index_va);
2740 radeon_emit(cmd_buffer->cs, index_va >> 32);
2741
2742 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2743 radeon_emit(cmd_buffer->cs, index_max_size);
2744
2745 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2746 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2747
2748 assert(cmd_buffer->cs->cdw <= cdw_max);
2749 }
2750
2751 void radv_CmdDrawIndirect(
2752 VkCommandBuffer commandBuffer,
2753 VkBuffer buffer,
2754 VkDeviceSize offset,
2755 uint32_t drawCount,
2756 uint32_t stride)
2757 {
2758 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2759 VK_NULL_HANDLE, 0, drawCount, stride);
2760 }
2761
2762 void radv_CmdDrawIndexedIndirect(
2763 VkCommandBuffer commandBuffer,
2764 VkBuffer buffer,
2765 VkDeviceSize offset,
2766 uint32_t drawCount,
2767 uint32_t stride)
2768 {
2769 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2770 VK_NULL_HANDLE, 0, drawCount, stride);
2771 }
2772
2773 void radv_CmdDrawIndirectCountAMD(
2774 VkCommandBuffer commandBuffer,
2775 VkBuffer buffer,
2776 VkDeviceSize offset,
2777 VkBuffer countBuffer,
2778 VkDeviceSize countBufferOffset,
2779 uint32_t maxDrawCount,
2780 uint32_t stride)
2781 {
2782 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2783 countBuffer, countBufferOffset,
2784 maxDrawCount, stride);
2785 }
2786
2787 void radv_CmdDrawIndexedIndirectCountAMD(
2788 VkCommandBuffer commandBuffer,
2789 VkBuffer buffer,
2790 VkDeviceSize offset,
2791 VkBuffer countBuffer,
2792 VkDeviceSize countBufferOffset,
2793 uint32_t maxDrawCount,
2794 uint32_t stride)
2795 {
2796 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2797 countBuffer, countBufferOffset,
2798 maxDrawCount, stride);
2799 }
2800
2801 static void
2802 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2803 {
2804 radv_emit_compute_pipeline(cmd_buffer);
2805 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2806 VK_SHADER_STAGE_COMPUTE_BIT);
2807 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2808 VK_SHADER_STAGE_COMPUTE_BIT);
2809 si_emit_cache_flush(cmd_buffer);
2810 }
2811
2812 void radv_CmdDispatch(
2813 VkCommandBuffer commandBuffer,
2814 uint32_t x,
2815 uint32_t y,
2816 uint32_t z)
2817 {
2818 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2819
2820 radv_flush_compute_state(cmd_buffer);
2821
2822 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2823
2824 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2825 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2826 if (loc->sgpr_idx != -1) {
2827 assert(!loc->indirect);
2828 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2829 assert(loc->num_sgprs == grid_used);
2830 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2831 radeon_emit(cmd_buffer->cs, x);
2832 if (grid_used > 1)
2833 radeon_emit(cmd_buffer->cs, y);
2834 if (grid_used > 2)
2835 radeon_emit(cmd_buffer->cs, z);
2836 }
2837
2838 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2839 PKT3_SHADER_TYPE_S(1));
2840 radeon_emit(cmd_buffer->cs, x);
2841 radeon_emit(cmd_buffer->cs, y);
2842 radeon_emit(cmd_buffer->cs, z);
2843 radeon_emit(cmd_buffer->cs, 1);
2844
2845 assert(cmd_buffer->cs->cdw <= cdw_max);
2846 radv_cmd_buffer_trace_emit(cmd_buffer);
2847 }
2848
2849 void radv_CmdDispatchIndirect(
2850 VkCommandBuffer commandBuffer,
2851 VkBuffer _buffer,
2852 VkDeviceSize offset)
2853 {
2854 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2855 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2856 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2857 va += buffer->offset + offset;
2858
2859 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2860
2861 radv_flush_compute_state(cmd_buffer);
2862
2863 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2864 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2865 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2866 if (loc->sgpr_idx != -1) {
2867 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2868 for (unsigned i = 0; i < grid_used; ++i) {
2869 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2870 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2871 COPY_DATA_DST_SEL(COPY_DATA_REG));
2872 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2873 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2874 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2875 radeon_emit(cmd_buffer->cs, 0);
2876 }
2877 }
2878
2879 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2880 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2881 PKT3_SHADER_TYPE_S(1));
2882 radeon_emit(cmd_buffer->cs, va);
2883 radeon_emit(cmd_buffer->cs, va >> 32);
2884 radeon_emit(cmd_buffer->cs, 1);
2885 } else {
2886 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2887 PKT3_SHADER_TYPE_S(1));
2888 radeon_emit(cmd_buffer->cs, 1);
2889 radeon_emit(cmd_buffer->cs, va);
2890 radeon_emit(cmd_buffer->cs, va >> 32);
2891
2892 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2893 PKT3_SHADER_TYPE_S(1));
2894 radeon_emit(cmd_buffer->cs, 0);
2895 radeon_emit(cmd_buffer->cs, 1);
2896 }
2897
2898 assert(cmd_buffer->cs->cdw <= cdw_max);
2899 radv_cmd_buffer_trace_emit(cmd_buffer);
2900 }
2901
2902 void radv_unaligned_dispatch(
2903 struct radv_cmd_buffer *cmd_buffer,
2904 uint32_t x,
2905 uint32_t y,
2906 uint32_t z)
2907 {
2908 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2909 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2910 uint32_t blocks[3], remainder[3];
2911
2912 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2913 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2914 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2915
2916 /* If aligned, these should be an entire block size, not 0 */
2917 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2918 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2919 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2920
2921 radv_flush_compute_state(cmd_buffer);
2922
2923 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2924
2925 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2926 radeon_emit(cmd_buffer->cs,
2927 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2928 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2929 radeon_emit(cmd_buffer->cs,
2930 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2931 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2932 radeon_emit(cmd_buffer->cs,
2933 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2934 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2935
2936 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2937 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2938 if (loc->sgpr_idx != -1) {
2939 uint8_t grid_used = cmd_buffer->state.compute_pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
2940 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
2941 radeon_emit(cmd_buffer->cs, blocks[0]);
2942 if (grid_used > 1)
2943 radeon_emit(cmd_buffer->cs, blocks[1]);
2944 if (grid_used > 2)
2945 radeon_emit(cmd_buffer->cs, blocks[2]);
2946 }
2947 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2948 PKT3_SHADER_TYPE_S(1));
2949 radeon_emit(cmd_buffer->cs, blocks[0]);
2950 radeon_emit(cmd_buffer->cs, blocks[1]);
2951 radeon_emit(cmd_buffer->cs, blocks[2]);
2952 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2953 S_00B800_PARTIAL_TG_EN(1));
2954
2955 assert(cmd_buffer->cs->cdw <= cdw_max);
2956 radv_cmd_buffer_trace_emit(cmd_buffer);
2957 }
2958
2959 void radv_CmdEndRenderPass(
2960 VkCommandBuffer commandBuffer)
2961 {
2962 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2963
2964 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2965
2966 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2967
2968 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2969 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2970 radv_handle_subpass_image_transition(cmd_buffer,
2971 (VkAttachmentReference){i, layout});
2972 }
2973
2974 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2975
2976 cmd_buffer->state.pass = NULL;
2977 cmd_buffer->state.subpass = NULL;
2978 cmd_buffer->state.attachments = NULL;
2979 cmd_buffer->state.framebuffer = NULL;
2980 }
2981
2982 /*
2983 * For HTILE we have the following interesting clear words:
2984 * 0x0000030f: Uncompressed.
2985 * 0xfffffff0: Clear depth to 1.0
2986 * 0x00000000: Clear depth to 0.0
2987 */
2988 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2989 struct radv_image *image,
2990 const VkImageSubresourceRange *range,
2991 uint32_t clear_word)
2992 {
2993 assert(range->baseMipLevel == 0);
2994 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
2995 unsigned layer_count = radv_get_layerCount(image, range);
2996 uint64_t size = image->surface.htile_slice_size * layer_count;
2997 uint64_t offset = image->offset + image->htile_offset +
2998 image->surface.htile_slice_size * range->baseArrayLayer;
2999
3000 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3001 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3002
3003 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3004
3005 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3006 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3007 RADV_CMD_FLAG_INV_VMEM_L1 |
3008 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3009 }
3010
3011 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3012 struct radv_image *image,
3013 VkImageLayout src_layout,
3014 VkImageLayout dst_layout,
3015 unsigned src_queue_mask,
3016 unsigned dst_queue_mask,
3017 const VkImageSubresourceRange *range,
3018 VkImageAspectFlags pending_clears)
3019 {
3020 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3021 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3022 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3023 cmd_buffer->state.render_area.extent.width == image->info.width &&
3024 cmd_buffer->state.render_area.extent.height == image->info.height) {
3025 /* The clear will initialize htile. */
3026 return;
3027 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3028 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3029 /* TODO: merge with the clear if applicable */
3030 radv_initialize_htile(cmd_buffer, image, range, 0);
3031 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3032 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3033 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3034 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3035 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3036 VkImageSubresourceRange local_range = *range;
3037 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3038 local_range.baseMipLevel = 0;
3039 local_range.levelCount = 1;
3040
3041 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3042 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3043
3044 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3045
3046 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3047 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3048 }
3049 }
3050
3051 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3052 struct radv_image *image, uint32_t value)
3053 {
3054 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3055 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3056
3057 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3058 image->cmask.size, value);
3059
3060 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3061 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3062 RADV_CMD_FLAG_INV_VMEM_L1 |
3063 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3064 }
3065
3066 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3067 struct radv_image *image,
3068 VkImageLayout src_layout,
3069 VkImageLayout dst_layout,
3070 unsigned src_queue_mask,
3071 unsigned dst_queue_mask,
3072 const VkImageSubresourceRange *range,
3073 VkImageAspectFlags pending_clears)
3074 {
3075 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3076 if (image->fmask.size)
3077 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3078 else
3079 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3080 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3081 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3082 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3083 }
3084 }
3085
3086 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3087 struct radv_image *image, uint32_t value)
3088 {
3089
3090 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3091 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3092
3093 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3094 image->surface.dcc_size, value);
3095
3096 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3097 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3098 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3099 RADV_CMD_FLAG_INV_VMEM_L1 |
3100 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3101 }
3102
3103 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3104 struct radv_image *image,
3105 VkImageLayout src_layout,
3106 VkImageLayout dst_layout,
3107 unsigned src_queue_mask,
3108 unsigned dst_queue_mask,
3109 const VkImageSubresourceRange *range,
3110 VkImageAspectFlags pending_clears)
3111 {
3112 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3113 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3114 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3115 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3116 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3117 }
3118 }
3119
3120 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3121 struct radv_image *image,
3122 VkImageLayout src_layout,
3123 VkImageLayout dst_layout,
3124 uint32_t src_family,
3125 uint32_t dst_family,
3126 const VkImageSubresourceRange *range,
3127 VkImageAspectFlags pending_clears)
3128 {
3129 if (image->exclusive && src_family != dst_family) {
3130 /* This is an acquire or a release operation and there will be
3131 * a corresponding release/acquire. Do the transition in the
3132 * most flexible queue. */
3133
3134 assert(src_family == cmd_buffer->queue_family_index ||
3135 dst_family == cmd_buffer->queue_family_index);
3136
3137 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3138 return;
3139
3140 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3141 (src_family == RADV_QUEUE_GENERAL ||
3142 dst_family == RADV_QUEUE_GENERAL))
3143 return;
3144 }
3145
3146 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3147 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3148
3149 if (image->surface.htile_size)
3150 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3151 dst_layout, src_queue_mask,
3152 dst_queue_mask, range,
3153 pending_clears);
3154
3155 if (image->cmask.size)
3156 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3157 dst_layout, src_queue_mask,
3158 dst_queue_mask, range,
3159 pending_clears);
3160
3161 if (image->surface.dcc_size)
3162 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3163 dst_layout, src_queue_mask,
3164 dst_queue_mask, range,
3165 pending_clears);
3166 }
3167
3168 void radv_CmdPipelineBarrier(
3169 VkCommandBuffer commandBuffer,
3170 VkPipelineStageFlags srcStageMask,
3171 VkPipelineStageFlags destStageMask,
3172 VkBool32 byRegion,
3173 uint32_t memoryBarrierCount,
3174 const VkMemoryBarrier* pMemoryBarriers,
3175 uint32_t bufferMemoryBarrierCount,
3176 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3177 uint32_t imageMemoryBarrierCount,
3178 const VkImageMemoryBarrier* pImageMemoryBarriers)
3179 {
3180 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3181 enum radv_cmd_flush_bits src_flush_bits = 0;
3182 enum radv_cmd_flush_bits dst_flush_bits = 0;
3183
3184 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3185 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3186 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3187 NULL);
3188 }
3189
3190 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3191 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3192 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3193 NULL);
3194 }
3195
3196 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3197 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3198 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3199 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3200 image);
3201 }
3202
3203 radv_stage_flush(cmd_buffer, srcStageMask);
3204 cmd_buffer->state.flush_bits |= src_flush_bits;
3205
3206 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3207 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3208 radv_handle_image_transition(cmd_buffer, image,
3209 pImageMemoryBarriers[i].oldLayout,
3210 pImageMemoryBarriers[i].newLayout,
3211 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3212 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3213 &pImageMemoryBarriers[i].subresourceRange,
3214 0);
3215 }
3216
3217 cmd_buffer->state.flush_bits |= dst_flush_bits;
3218 }
3219
3220
3221 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3222 struct radv_event *event,
3223 VkPipelineStageFlags stageMask,
3224 unsigned value)
3225 {
3226 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3227 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3228
3229 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3230
3231 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
3232
3233 /* TODO: this is overkill. Probably should figure something out from
3234 * the stage mask. */
3235
3236 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
3237 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
3238 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
3239 EVENT_INDEX(5));
3240 radeon_emit(cs, va);
3241 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
3242 radeon_emit(cs, 2);
3243 radeon_emit(cs, 0);
3244 }
3245
3246 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
3247 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
3248 EVENT_INDEX(5));
3249 radeon_emit(cs, va);
3250 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
3251 radeon_emit(cs, value);
3252 radeon_emit(cs, 0);
3253
3254 assert(cmd_buffer->cs->cdw <= cdw_max);
3255 }
3256
3257 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3258 VkEvent _event,
3259 VkPipelineStageFlags stageMask)
3260 {
3261 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3262 RADV_FROM_HANDLE(radv_event, event, _event);
3263
3264 write_event(cmd_buffer, event, stageMask, 1);
3265 }
3266
3267 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3268 VkEvent _event,
3269 VkPipelineStageFlags stageMask)
3270 {
3271 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3272 RADV_FROM_HANDLE(radv_event, event, _event);
3273
3274 write_event(cmd_buffer, event, stageMask, 0);
3275 }
3276
3277 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3278 uint32_t eventCount,
3279 const VkEvent* pEvents,
3280 VkPipelineStageFlags srcStageMask,
3281 VkPipelineStageFlags dstStageMask,
3282 uint32_t memoryBarrierCount,
3283 const VkMemoryBarrier* pMemoryBarriers,
3284 uint32_t bufferMemoryBarrierCount,
3285 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3286 uint32_t imageMemoryBarrierCount,
3287 const VkImageMemoryBarrier* pImageMemoryBarriers)
3288 {
3289 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3290 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3291
3292 for (unsigned i = 0; i < eventCount; ++i) {
3293 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3294 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
3295
3296 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3297
3298 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3299
3300 si_emit_wait_fence(cs, va, 1, 0xffffffff);
3301 assert(cmd_buffer->cs->cdw <= cdw_max);
3302 }
3303
3304
3305 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3306 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3307
3308 radv_handle_image_transition(cmd_buffer, image,
3309 pImageMemoryBarriers[i].oldLayout,
3310 pImageMemoryBarriers[i].newLayout,
3311 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3312 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3313 &pImageMemoryBarriers[i].subresourceRange,
3314 0);
3315 }
3316
3317 /* TODO: figure out how to do memory barriers without waiting */
3318 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3319 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3320 RADV_CMD_FLAG_INV_VMEM_L1 |
3321 RADV_CMD_FLAG_INV_SMEM_L1;
3322 }