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radv: remove dependency on addrlib gfx9_enum.h
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range);
61
62 const struct radv_dynamic_state default_dynamic_state = {
63 .viewport = {
64 .count = 0,
65 },
66 .scissor = {
67 .count = 0,
68 },
69 .line_width = 1.0f,
70 .depth_bias = {
71 .bias = 0.0f,
72 .clamp = 0.0f,
73 .slope = 0.0f,
74 },
75 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
76 .depth_bounds = {
77 .min = 0.0f,
78 .max = 1.0f,
79 },
80 .stencil_compare_mask = {
81 .front = ~0u,
82 .back = ~0u,
83 },
84 .stencil_write_mask = {
85 .front = ~0u,
86 .back = ~0u,
87 },
88 .stencil_reference = {
89 .front = 0u,
90 .back = 0u,
91 },
92 };
93
94 static void
95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
96 const struct radv_dynamic_state *src)
97 {
98 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
99 uint32_t copy_mask = src->mask;
100 uint32_t dest_mask = 0;
101
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
104 */
105 dest->viewport.count = src->viewport.count;
106 dest->scissor.count = src->scissor.count;
107 dest->discard_rectangle.count = src->discard_rectangle.count;
108
109 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
110 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
111 src->viewport.count * sizeof(VkViewport))) {
112 typed_memcpy(dest->viewport.viewports,
113 src->viewport.viewports,
114 src->viewport.count);
115 dest_mask |= RADV_DYNAMIC_VIEWPORT;
116 }
117 }
118
119 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
120 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
121 src->scissor.count * sizeof(VkRect2D))) {
122 typed_memcpy(dest->scissor.scissors,
123 src->scissor.scissors, src->scissor.count);
124 dest_mask |= RADV_DYNAMIC_SCISSOR;
125 }
126 }
127
128 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
129 if (dest->line_width != src->line_width) {
130 dest->line_width = src->line_width;
131 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
132 }
133 }
134
135 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
136 if (memcmp(&dest->depth_bias, &src->depth_bias,
137 sizeof(src->depth_bias))) {
138 dest->depth_bias = src->depth_bias;
139 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
144 if (memcmp(&dest->blend_constants, &src->blend_constants,
145 sizeof(src->blend_constants))) {
146 typed_memcpy(dest->blend_constants,
147 src->blend_constants, 4);
148 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
149 }
150 }
151
152 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
153 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
154 sizeof(src->depth_bounds))) {
155 dest->depth_bounds = src->depth_bounds;
156 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
161 if (memcmp(&dest->stencil_compare_mask,
162 &src->stencil_compare_mask,
163 sizeof(src->stencil_compare_mask))) {
164 dest->stencil_compare_mask = src->stencil_compare_mask;
165 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
166 }
167 }
168
169 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
170 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
171 sizeof(src->stencil_write_mask))) {
172 dest->stencil_write_mask = src->stencil_write_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
178 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
179 sizeof(src->stencil_reference))) {
180 dest->stencil_reference = src->stencil_reference;
181 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
186 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
187 src->discard_rectangle.count * sizeof(VkRect2D))) {
188 typed_memcpy(dest->discard_rectangle.rectangles,
189 src->discard_rectangle.rectangles,
190 src->discard_rectangle.count);
191 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
192 }
193 }
194
195 cmd_buffer->state.dirty |= dest_mask;
196 }
197
198 static void
199 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
200 struct radv_pipeline *pipeline)
201 {
202 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
203 struct radv_shader_info *info;
204
205 if (!pipeline->streamout_shader)
206 return;
207
208 info = &pipeline->streamout_shader->info.info;
209 for (int i = 0; i < MAX_SO_BUFFERS; i++)
210 so->stride_in_dw[i] = info->so.strides[i];
211
212 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
213 }
214
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
216 {
217 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
218 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
219 }
220
221 enum ring_type radv_queue_family_to_ring(int f) {
222 switch (f) {
223 case RADV_QUEUE_GENERAL:
224 return RING_GFX;
225 case RADV_QUEUE_COMPUTE:
226 return RING_COMPUTE;
227 case RADV_QUEUE_TRANSFER:
228 return RING_DMA;
229 default:
230 unreachable("Unknown queue family");
231 }
232 }
233
234 static VkResult radv_create_cmd_buffer(
235 struct radv_device * device,
236 struct radv_cmd_pool * pool,
237 VkCommandBufferLevel level,
238 VkCommandBuffer* pCommandBuffer)
239 {
240 struct radv_cmd_buffer *cmd_buffer;
241 unsigned ring;
242 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
244 if (cmd_buffer == NULL)
245 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
246
247 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 cmd_buffer->device = device;
249 cmd_buffer->pool = pool;
250 cmd_buffer->level = level;
251
252 if (pool) {
253 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
254 cmd_buffer->queue_family_index = pool->queue_family_index;
255
256 } else {
257 /* Init the pool_link so we can safely call list_del when we destroy
258 * the command buffer
259 */
260 list_inithead(&cmd_buffer->pool_link);
261 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
262 }
263
264 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
265
266 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
267 if (!cmd_buffer->cs) {
268 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
269 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
270 }
271
272 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
273
274 list_inithead(&cmd_buffer->upload.list);
275
276 return VK_SUCCESS;
277 }
278
279 static void
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
281 {
282 list_del(&cmd_buffer->pool_link);
283
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
285 &cmd_buffer->upload.list, list) {
286 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
287 list_del(&up->list);
288 free(up);
289 }
290
291 if (cmd_buffer->upload.upload_bo)
292 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
293 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
294
295 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
296 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
297
298 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
299 }
300
301 static VkResult
302 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
303 {
304
305 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
306
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
308 &cmd_buffer->upload.list, list) {
309 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
310 list_del(&up->list);
311 free(up);
312 }
313
314 cmd_buffer->push_constant_stages = 0;
315 cmd_buffer->scratch_size_needed = 0;
316 cmd_buffer->compute_scratch_size_needed = 0;
317 cmd_buffer->esgs_ring_size_needed = 0;
318 cmd_buffer->gsvs_ring_size_needed = 0;
319 cmd_buffer->tess_rings_needed = false;
320 cmd_buffer->sample_positions_needed = false;
321
322 if (cmd_buffer->upload.upload_bo)
323 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
324 cmd_buffer->upload.upload_bo);
325 cmd_buffer->upload.offset = 0;
326
327 cmd_buffer->record_result = VK_SUCCESS;
328
329 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
330 cmd_buffer->descriptors[i].dirty = 0;
331 cmd_buffer->descriptors[i].valid = 0;
332 cmd_buffer->descriptors[i].push_dirty = false;
333 }
334
335 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
336 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
337 unsigned eop_bug_offset;
338 void *fence_ptr;
339
340 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
341 &cmd_buffer->gfx9_fence_offset,
342 &fence_ptr);
343 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
344
345 /* Allocate a buffer for the EOP bug on GFX9. */
346 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
347 &eop_bug_offset, &fence_ptr);
348 cmd_buffer->gfx9_eop_bug_va =
349 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
350 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
351 }
352
353 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
354
355 return cmd_buffer->record_result;
356 }
357
358 static bool
359 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
360 uint64_t min_needed)
361 {
362 uint64_t new_size;
363 struct radeon_winsys_bo *bo;
364 struct radv_cmd_buffer_upload *upload;
365 struct radv_device *device = cmd_buffer->device;
366
367 new_size = MAX2(min_needed, 16 * 1024);
368 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
369
370 bo = device->ws->buffer_create(device->ws,
371 new_size, 4096,
372 RADEON_DOMAIN_GTT,
373 RADEON_FLAG_CPU_ACCESS|
374 RADEON_FLAG_NO_INTERPROCESS_SHARING |
375 RADEON_FLAG_32BIT);
376
377 if (!bo) {
378 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
379 return false;
380 }
381
382 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
383 if (cmd_buffer->upload.upload_bo) {
384 upload = malloc(sizeof(*upload));
385
386 if (!upload) {
387 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
388 device->ws->buffer_destroy(bo);
389 return false;
390 }
391
392 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
393 list_add(&upload->list, &cmd_buffer->upload.list);
394 }
395
396 cmd_buffer->upload.upload_bo = bo;
397 cmd_buffer->upload.size = new_size;
398 cmd_buffer->upload.offset = 0;
399 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
400
401 if (!cmd_buffer->upload.map) {
402 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
403 return false;
404 }
405
406 return true;
407 }
408
409 bool
410 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
411 unsigned size,
412 unsigned alignment,
413 unsigned *out_offset,
414 void **ptr)
415 {
416 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
417 if (offset + size > cmd_buffer->upload.size) {
418 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
419 return false;
420 offset = 0;
421 }
422
423 *out_offset = offset;
424 *ptr = cmd_buffer->upload.map + offset;
425
426 cmd_buffer->upload.offset = offset + size;
427 return true;
428 }
429
430 bool
431 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
432 unsigned size, unsigned alignment,
433 const void *data, unsigned *out_offset)
434 {
435 uint8_t *ptr;
436
437 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
438 out_offset, (void **)&ptr))
439 return false;
440
441 if (ptr)
442 memcpy(ptr, data, size);
443
444 return true;
445 }
446
447 static void
448 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
449 unsigned count, const uint32_t *data)
450 {
451 struct radeon_cmdbuf *cs = cmd_buffer->cs;
452
453 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
454
455 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
456 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
457 S_370_WR_CONFIRM(1) |
458 S_370_ENGINE_SEL(V_370_ME));
459 radeon_emit(cs, va);
460 radeon_emit(cs, va >> 32);
461 radeon_emit_array(cs, data, count);
462 }
463
464 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
465 {
466 struct radv_device *device = cmd_buffer->device;
467 struct radeon_cmdbuf *cs = cmd_buffer->cs;
468 uint64_t va;
469
470 va = radv_buffer_get_va(device->trace_bo);
471 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
472 va += 4;
473
474 ++cmd_buffer->state.trace_id;
475 radv_emit_write_data_packet(cmd_buffer, va, 1,
476 &cmd_buffer->state.trace_id);
477
478 radeon_check_space(cmd_buffer->device->ws, cs, 2);
479
480 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
481 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
482 }
483
484 static void
485 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
486 enum radv_cmd_flush_bits flags)
487 {
488 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
489 uint32_t *ptr = NULL;
490 uint64_t va = 0;
491
492 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
493 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
494
495 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
496 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
497 cmd_buffer->gfx9_fence_offset;
498 ptr = &cmd_buffer->gfx9_fence_idx;
499 }
500
501 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
502
503 /* Force wait for graphics or compute engines to be idle. */
504 si_cs_emit_cache_flush(cmd_buffer->cs,
505 cmd_buffer->device->physical_device->rad_info.chip_class,
506 ptr, va,
507 radv_cmd_buffer_uses_mec(cmd_buffer),
508 flags, cmd_buffer->gfx9_eop_bug_va);
509 }
510
511 if (unlikely(cmd_buffer->device->trace_bo))
512 radv_cmd_buffer_trace_emit(cmd_buffer);
513 }
514
515 static void
516 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
517 struct radv_pipeline *pipeline, enum ring_type ring)
518 {
519 struct radv_device *device = cmd_buffer->device;
520 uint32_t data[2];
521 uint64_t va;
522
523 va = radv_buffer_get_va(device->trace_bo);
524
525 switch (ring) {
526 case RING_GFX:
527 va += 8;
528 break;
529 case RING_COMPUTE:
530 va += 16;
531 break;
532 default:
533 assert(!"invalid ring type");
534 }
535
536 data[0] = (uintptr_t)pipeline;
537 data[1] = (uintptr_t)pipeline >> 32;
538
539 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
540 }
541
542 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
543 VkPipelineBindPoint bind_point,
544 struct radv_descriptor_set *set,
545 unsigned idx)
546 {
547 struct radv_descriptor_state *descriptors_state =
548 radv_get_descriptors_state(cmd_buffer, bind_point);
549
550 descriptors_state->sets[idx] = set;
551
552 descriptors_state->valid |= (1u << idx); /* active descriptors */
553 descriptors_state->dirty |= (1u << idx);
554 }
555
556 static void
557 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
558 VkPipelineBindPoint bind_point)
559 {
560 struct radv_descriptor_state *descriptors_state =
561 radv_get_descriptors_state(cmd_buffer, bind_point);
562 struct radv_device *device = cmd_buffer->device;
563 uint32_t data[MAX_SETS * 2] = {};
564 uint64_t va;
565 unsigned i;
566 va = radv_buffer_get_va(device->trace_bo) + 24;
567
568 for_each_bit(i, descriptors_state->valid) {
569 struct radv_descriptor_set *set = descriptors_state->sets[i];
570 data[i * 2] = (uintptr_t)set;
571 data[i * 2 + 1] = (uintptr_t)set >> 32;
572 }
573
574 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
575 }
576
577 struct radv_userdata_info *
578 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
579 gl_shader_stage stage,
580 int idx)
581 {
582 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
583 return &shader->info.user_sgprs_locs.shader_data[idx];
584 }
585
586 static void
587 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
588 struct radv_pipeline *pipeline,
589 gl_shader_stage stage,
590 int idx, uint64_t va)
591 {
592 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
593 uint32_t base_reg = pipeline->user_data_0[stage];
594 if (loc->sgpr_idx == -1)
595 return;
596
597 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
598 assert(!loc->indirect);
599
600 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
601 base_reg + loc->sgpr_idx * 4, va, false);
602 }
603
604 static void
605 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
606 struct radv_pipeline *pipeline,
607 struct radv_descriptor_state *descriptors_state,
608 gl_shader_stage stage)
609 {
610 struct radv_device *device = cmd_buffer->device;
611 struct radeon_cmdbuf *cs = cmd_buffer->cs;
612 uint32_t sh_base = pipeline->user_data_0[stage];
613 struct radv_userdata_locations *locs =
614 &pipeline->shaders[stage]->info.user_sgprs_locs;
615 unsigned mask = locs->descriptor_sets_enabled;
616
617 mask &= descriptors_state->dirty & descriptors_state->valid;
618
619 while (mask) {
620 int start, count;
621
622 u_bit_scan_consecutive_range(&mask, &start, &count);
623
624 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
625 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
626
627 radv_emit_shader_pointer_head(cs, sh_offset, count,
628 HAVE_32BIT_POINTERS);
629 for (int i = 0; i < count; i++) {
630 struct radv_descriptor_set *set =
631 descriptors_state->sets[start + i];
632
633 radv_emit_shader_pointer_body(device, cs, set->va,
634 HAVE_32BIT_POINTERS);
635 }
636 }
637 }
638
639 static void
640 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
641 struct radv_pipeline *pipeline)
642 {
643 int num_samples = pipeline->graphics.ms.num_samples;
644 struct radv_multisample_state *ms = &pipeline->graphics.ms;
645 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
646
647 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
648 cmd_buffer->sample_positions_needed = true;
649
650 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
651 return;
652
653 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
654 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
655 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
656
657 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
658
659 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
660
661 /* GFX9: Flush DFSM when the AA mode changes. */
662 if (cmd_buffer->device->dfsm_allowed) {
663 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
664 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
665 }
666 }
667
668 static void
669 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
670 struct radv_shader_variant *shader)
671 {
672 uint64_t va;
673
674 if (!shader)
675 return;
676
677 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
678
679 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
680 }
681
682 static void
683 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
684 struct radv_pipeline *pipeline,
685 bool vertex_stage_only)
686 {
687 struct radv_cmd_state *state = &cmd_buffer->state;
688 uint32_t mask = state->prefetch_L2_mask;
689
690 if (vertex_stage_only) {
691 /* Fast prefetch path for starting draws as soon as possible.
692 */
693 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
694 RADV_PREFETCH_VBO_DESCRIPTORS);
695 }
696
697 if (mask & RADV_PREFETCH_VS)
698 radv_emit_shader_prefetch(cmd_buffer,
699 pipeline->shaders[MESA_SHADER_VERTEX]);
700
701 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
702 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
703
704 if (mask & RADV_PREFETCH_TCS)
705 radv_emit_shader_prefetch(cmd_buffer,
706 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
707
708 if (mask & RADV_PREFETCH_TES)
709 radv_emit_shader_prefetch(cmd_buffer,
710 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
711
712 if (mask & RADV_PREFETCH_GS) {
713 radv_emit_shader_prefetch(cmd_buffer,
714 pipeline->shaders[MESA_SHADER_GEOMETRY]);
715 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
716 }
717
718 if (mask & RADV_PREFETCH_PS)
719 radv_emit_shader_prefetch(cmd_buffer,
720 pipeline->shaders[MESA_SHADER_FRAGMENT]);
721
722 state->prefetch_L2_mask &= ~mask;
723 }
724
725 static void
726 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
727 {
728 if (!cmd_buffer->device->physical_device->rbplus_allowed)
729 return;
730
731 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
732 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
733 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
734
735 unsigned sx_ps_downconvert = 0;
736 unsigned sx_blend_opt_epsilon = 0;
737 unsigned sx_blend_opt_control = 0;
738
739 for (unsigned i = 0; i < subpass->color_count; ++i) {
740 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
741 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
742 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
743 continue;
744 }
745
746 int idx = subpass->color_attachments[i].attachment;
747 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
748
749 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
750 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
751 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
752 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
753
754 bool has_alpha, has_rgb;
755
756 /* Set if RGB and A are present. */
757 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
758
759 if (format == V_028C70_COLOR_8 ||
760 format == V_028C70_COLOR_16 ||
761 format == V_028C70_COLOR_32)
762 has_rgb = !has_alpha;
763 else
764 has_rgb = true;
765
766 /* Check the colormask and export format. */
767 if (!(colormask & 0x7))
768 has_rgb = false;
769 if (!(colormask & 0x8))
770 has_alpha = false;
771
772 if (spi_format == V_028714_SPI_SHADER_ZERO) {
773 has_rgb = false;
774 has_alpha = false;
775 }
776
777 /* Disable value checking for disabled channels. */
778 if (!has_rgb)
779 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
780 if (!has_alpha)
781 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
782
783 /* Enable down-conversion for 32bpp and smaller formats. */
784 switch (format) {
785 case V_028C70_COLOR_8:
786 case V_028C70_COLOR_8_8:
787 case V_028C70_COLOR_8_8_8_8:
788 /* For 1 and 2-channel formats, use the superset thereof. */
789 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
790 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
791 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
792 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
793 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
794 }
795 break;
796
797 case V_028C70_COLOR_5_6_5:
798 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
799 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
800 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
801 }
802 break;
803
804 case V_028C70_COLOR_1_5_5_5:
805 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
806 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
807 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
808 }
809 break;
810
811 case V_028C70_COLOR_4_4_4_4:
812 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
813 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
814 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
815 }
816 break;
817
818 case V_028C70_COLOR_32:
819 if (swap == V_028C70_SWAP_STD &&
820 spi_format == V_028714_SPI_SHADER_32_R)
821 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
822 else if (swap == V_028C70_SWAP_ALT_REV &&
823 spi_format == V_028714_SPI_SHADER_32_AR)
824 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
825 break;
826
827 case V_028C70_COLOR_16:
828 case V_028C70_COLOR_16_16:
829 /* For 1-channel formats, use the superset thereof. */
830 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
831 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
832 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
833 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
834 if (swap == V_028C70_SWAP_STD ||
835 swap == V_028C70_SWAP_STD_REV)
836 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
837 else
838 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
839 }
840 break;
841
842 case V_028C70_COLOR_10_11_11:
843 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
844 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
845 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
846 }
847 break;
848
849 case V_028C70_COLOR_2_10_10_10:
850 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
851 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
852 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
853 }
854 break;
855 }
856 }
857
858 for (unsigned i = subpass->color_count; i < 8; ++i) {
859 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
860 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
861 }
862 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
863 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
864 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
865 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
866 }
867
868 static void
869 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
870 {
871 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
872
873 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
874 return;
875
876 radv_update_multisample_state(cmd_buffer, pipeline);
877
878 cmd_buffer->scratch_size_needed =
879 MAX2(cmd_buffer->scratch_size_needed,
880 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
881
882 if (!cmd_buffer->state.emitted_pipeline ||
883 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
884 pipeline->graphics.can_use_guardband)
885 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
886
887 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
888
889 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
890 if (!pipeline->shaders[i])
891 continue;
892
893 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
894 pipeline->shaders[i]->bo);
895 }
896
897 if (radv_pipeline_has_gs(pipeline))
898 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
899 pipeline->gs_copy_shader->bo);
900
901 if (unlikely(cmd_buffer->device->trace_bo))
902 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
903
904 cmd_buffer->state.emitted_pipeline = pipeline;
905
906 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
907 }
908
909 static void
910 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
911 {
912 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
913 cmd_buffer->state.dynamic.viewport.viewports);
914 }
915
916 static void
917 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
918 {
919 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
920
921 si_write_scissors(cmd_buffer->cs, 0, count,
922 cmd_buffer->state.dynamic.scissor.scissors,
923 cmd_buffer->state.dynamic.viewport.viewports,
924 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
925 }
926
927 static void
928 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
929 {
930 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
931 return;
932
933 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
934 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
935 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
936 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
937 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
938 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
939 S_028214_BR_Y(rect.offset.y + rect.extent.height));
940 }
941 }
942
943 static void
944 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
945 {
946 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
947
948 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
949 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
950 }
951
952 static void
953 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
954 {
955 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
956
957 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
958 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
959 }
960
961 static void
962 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
963 {
964 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
965
966 radeon_set_context_reg_seq(cmd_buffer->cs,
967 R_028430_DB_STENCILREFMASK, 2);
968 radeon_emit(cmd_buffer->cs,
969 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
970 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
971 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
972 S_028430_STENCILOPVAL(1));
973 radeon_emit(cmd_buffer->cs,
974 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
975 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
976 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
977 S_028434_STENCILOPVAL_BF(1));
978 }
979
980 static void
981 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
982 {
983 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
984
985 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
986 fui(d->depth_bounds.min));
987 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
988 fui(d->depth_bounds.max));
989 }
990
991 static void
992 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
993 {
994 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
995 unsigned slope = fui(d->depth_bias.slope * 16.0f);
996 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
997
998
999 radeon_set_context_reg_seq(cmd_buffer->cs,
1000 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1001 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1002 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1003 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1004 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1005 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1006 }
1007
1008 static void
1009 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1010 int index,
1011 struct radv_attachment_info *att,
1012 struct radv_image *image,
1013 VkImageLayout layout)
1014 {
1015 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1016 struct radv_color_buffer_info *cb = &att->cb;
1017 uint32_t cb_color_info = cb->cb_color_info;
1018
1019 if (!radv_layout_dcc_compressed(image, layout,
1020 radv_image_queue_family_mask(image,
1021 cmd_buffer->queue_family_index,
1022 cmd_buffer->queue_family_index))) {
1023 cb_color_info &= C_028C70_DCC_ENABLE;
1024 }
1025
1026 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1027 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1028 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1029 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1030 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1031 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1032 radeon_emit(cmd_buffer->cs, cb_color_info);
1033 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1034 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1035 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1036 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1037 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1038 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1039
1040 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1041 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1042 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1043
1044 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1045 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1046 } else {
1047 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1048 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1049 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1050 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1051 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1052 radeon_emit(cmd_buffer->cs, cb_color_info);
1053 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1054 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1055 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1056 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1057 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1058 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1059
1060 if (is_vi) { /* DCC BASE */
1061 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1062 }
1063 }
1064 }
1065
1066 static void
1067 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1068 struct radv_ds_buffer_info *ds,
1069 struct radv_image *image, VkImageLayout layout,
1070 bool requires_cond_write)
1071 {
1072 uint32_t db_z_info = ds->db_z_info;
1073 uint32_t db_z_info_reg;
1074
1075 if (!radv_image_is_tc_compat_htile(image))
1076 return;
1077
1078 if (!radv_layout_has_htile(image, layout,
1079 radv_image_queue_family_mask(image,
1080 cmd_buffer->queue_family_index,
1081 cmd_buffer->queue_family_index))) {
1082 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1083 }
1084
1085 db_z_info &= C_028040_ZRANGE_PRECISION;
1086
1087 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1088 db_z_info_reg = R_028038_DB_Z_INFO;
1089 } else {
1090 db_z_info_reg = R_028040_DB_Z_INFO;
1091 }
1092
1093 /* When we don't know the last fast clear value we need to emit a
1094 * conditional packet, otherwise we can update DB_Z_INFO directly.
1095 */
1096 if (requires_cond_write) {
1097 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1098
1099 const uint32_t write_space = 0 << 8; /* register */
1100 const uint32_t poll_space = 1 << 4; /* memory */
1101 const uint32_t function = 3 << 0; /* equal to the reference */
1102 const uint32_t options = write_space | poll_space | function;
1103 radeon_emit(cmd_buffer->cs, options);
1104
1105 /* poll address - location of the depth clear value */
1106 uint64_t va = radv_buffer_get_va(image->bo);
1107 va += image->offset + image->clear_value_offset;
1108
1109 /* In presence of stencil format, we have to adjust the base
1110 * address because the first value is the stencil clear value.
1111 */
1112 if (vk_format_is_stencil(image->vk_format))
1113 va += 4;
1114
1115 radeon_emit(cmd_buffer->cs, va);
1116 radeon_emit(cmd_buffer->cs, va >> 32);
1117
1118 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1119 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1120 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1121 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1122 radeon_emit(cmd_buffer->cs, db_z_info);
1123 } else {
1124 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1125 }
1126 }
1127
1128 static void
1129 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1130 struct radv_ds_buffer_info *ds,
1131 struct radv_image *image,
1132 VkImageLayout layout)
1133 {
1134 uint32_t db_z_info = ds->db_z_info;
1135 uint32_t db_stencil_info = ds->db_stencil_info;
1136
1137 if (!radv_layout_has_htile(image, layout,
1138 radv_image_queue_family_mask(image,
1139 cmd_buffer->queue_family_index,
1140 cmd_buffer->queue_family_index))) {
1141 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1142 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1143 }
1144
1145 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1146 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1147
1148
1149 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1150 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1151 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1152 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1153 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1154
1155 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1156 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1157 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1158 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1159 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1160 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1161 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1162 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1163 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1164 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1165 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1166
1167 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1168 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1169 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1170 } else {
1171 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1172
1173 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1174 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1175 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1176 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1177 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1178 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1179 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1180 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1181 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1182 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1183
1184 }
1185
1186 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1187 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1188
1189 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1190 ds->pa_su_poly_offset_db_fmt_cntl);
1191 }
1192
1193 /**
1194 * Update the fast clear depth/stencil values if the image is bound as a
1195 * depth/stencil buffer.
1196 */
1197 static void
1198 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1199 struct radv_image *image,
1200 VkClearDepthStencilValue ds_clear_value,
1201 VkImageAspectFlags aspects)
1202 {
1203 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1204 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1205 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1206 struct radv_attachment_info *att;
1207 uint32_t att_idx;
1208
1209 if (!framebuffer || !subpass)
1210 return;
1211
1212 att_idx = subpass->depth_stencil_attachment.attachment;
1213 if (att_idx == VK_ATTACHMENT_UNUSED)
1214 return;
1215
1216 att = &framebuffer->attachments[att_idx];
1217 if (att->attachment->image != image)
1218 return;
1219
1220 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1221 radeon_emit(cs, ds_clear_value.stencil);
1222 radeon_emit(cs, fui(ds_clear_value.depth));
1223
1224 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1225 * only needed when clearing Z to 0.0.
1226 */
1227 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1228 ds_clear_value.depth == 0.0) {
1229 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1230
1231 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1232 layout, false);
1233 }
1234 }
1235
1236 /**
1237 * Set the clear depth/stencil values to the image's metadata.
1238 */
1239 static void
1240 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1241 struct radv_image *image,
1242 VkClearDepthStencilValue ds_clear_value,
1243 VkImageAspectFlags aspects)
1244 {
1245 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1246 uint64_t va = radv_buffer_get_va(image->bo);
1247 unsigned reg_offset = 0, reg_count = 0;
1248
1249 va += image->offset + image->clear_value_offset;
1250
1251 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1252 ++reg_count;
1253 } else {
1254 ++reg_offset;
1255 va += 4;
1256 }
1257 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1258 ++reg_count;
1259
1260 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1261 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1262 S_370_WR_CONFIRM(1) |
1263 S_370_ENGINE_SEL(V_370_PFP));
1264 radeon_emit(cs, va);
1265 radeon_emit(cs, va >> 32);
1266 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1267 radeon_emit(cs, ds_clear_value.stencil);
1268 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1269 radeon_emit(cs, fui(ds_clear_value.depth));
1270 }
1271
1272 /**
1273 * Update the clear depth/stencil values for this image.
1274 */
1275 void
1276 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1277 struct radv_image *image,
1278 VkClearDepthStencilValue ds_clear_value,
1279 VkImageAspectFlags aspects)
1280 {
1281 assert(radv_image_has_htile(image));
1282
1283 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1284
1285 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1286 aspects);
1287 }
1288
1289 /**
1290 * Load the clear depth/stencil values from the image's metadata.
1291 */
1292 static void
1293 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1294 struct radv_image *image)
1295 {
1296 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1297 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1298 uint64_t va = radv_buffer_get_va(image->bo);
1299 unsigned reg_offset = 0, reg_count = 0;
1300
1301 va += image->offset + image->clear_value_offset;
1302
1303 if (!radv_image_has_htile(image))
1304 return;
1305
1306 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1307 ++reg_count;
1308 } else {
1309 ++reg_offset;
1310 va += 4;
1311 }
1312 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1313 ++reg_count;
1314
1315 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1316
1317 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1318 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1319 radeon_emit(cs, va);
1320 radeon_emit(cs, va >> 32);
1321 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1322 radeon_emit(cs, reg_count);
1323 } else {
1324 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1325 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1326 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1327 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1328 radeon_emit(cs, va);
1329 radeon_emit(cs, va >> 32);
1330 radeon_emit(cs, reg >> 2);
1331 radeon_emit(cs, 0);
1332
1333 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1334 radeon_emit(cs, 0);
1335 }
1336 }
1337
1338 /*
1339 * With DCC some colors don't require CMASK elimination before being
1340 * used as a texture. This sets a predicate value to determine if the
1341 * cmask eliminate is required.
1342 */
1343 void
1344 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1345 struct radv_image *image, bool value)
1346 {
1347 uint64_t pred_val = value;
1348 uint64_t va = radv_buffer_get_va(image->bo);
1349 va += image->offset + image->fce_pred_offset;
1350
1351 assert(radv_image_has_dcc(image));
1352
1353 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1354 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1355 S_370_WR_CONFIRM(1) |
1356 S_370_ENGINE_SEL(V_370_PFP));
1357 radeon_emit(cmd_buffer->cs, va);
1358 radeon_emit(cmd_buffer->cs, va >> 32);
1359 radeon_emit(cmd_buffer->cs, pred_val);
1360 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1361 }
1362
1363 /**
1364 * Update the fast clear color values if the image is bound as a color buffer.
1365 */
1366 static void
1367 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1368 struct radv_image *image,
1369 int cb_idx,
1370 uint32_t color_values[2])
1371 {
1372 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1373 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1374 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1375 struct radv_attachment_info *att;
1376 uint32_t att_idx;
1377
1378 if (!framebuffer || !subpass)
1379 return;
1380
1381 att_idx = subpass->color_attachments[cb_idx].attachment;
1382 if (att_idx == VK_ATTACHMENT_UNUSED)
1383 return;
1384
1385 att = &framebuffer->attachments[att_idx];
1386 if (att->attachment->image != image)
1387 return;
1388
1389 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1390 radeon_emit(cs, color_values[0]);
1391 radeon_emit(cs, color_values[1]);
1392 }
1393
1394 /**
1395 * Set the clear color values to the image's metadata.
1396 */
1397 static void
1398 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1399 struct radv_image *image,
1400 uint32_t color_values[2])
1401 {
1402 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1403 uint64_t va = radv_buffer_get_va(image->bo);
1404
1405 va += image->offset + image->clear_value_offset;
1406
1407 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1408
1409 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1410 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1411 S_370_WR_CONFIRM(1) |
1412 S_370_ENGINE_SEL(V_370_PFP));
1413 radeon_emit(cs, va);
1414 radeon_emit(cs, va >> 32);
1415 radeon_emit(cs, color_values[0]);
1416 radeon_emit(cs, color_values[1]);
1417 }
1418
1419 /**
1420 * Update the clear color values for this image.
1421 */
1422 void
1423 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1424 struct radv_image *image,
1425 int cb_idx,
1426 uint32_t color_values[2])
1427 {
1428 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1429
1430 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1431
1432 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1433 color_values);
1434 }
1435
1436 /**
1437 * Load the clear color values from the image's metadata.
1438 */
1439 static void
1440 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1441 struct radv_image *image,
1442 int cb_idx)
1443 {
1444 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1445 uint64_t va = radv_buffer_get_va(image->bo);
1446
1447 va += image->offset + image->clear_value_offset;
1448
1449 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1450 return;
1451
1452 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1453
1454 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1455 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1456 radeon_emit(cs, va);
1457 radeon_emit(cs, va >> 32);
1458 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1459 radeon_emit(cs, 2);
1460 } else {
1461 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1462 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1463 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1464 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1465 COPY_DATA_COUNT_SEL);
1466 radeon_emit(cs, va);
1467 radeon_emit(cs, va >> 32);
1468 radeon_emit(cs, reg >> 2);
1469 radeon_emit(cs, 0);
1470
1471 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1472 radeon_emit(cs, 0);
1473 }
1474 }
1475
1476 static void
1477 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1478 {
1479 int i;
1480 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1481 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1482 unsigned num_bpp64_colorbufs = 0;
1483
1484 /* this may happen for inherited secondary recording */
1485 if (!framebuffer)
1486 return;
1487
1488 for (i = 0; i < 8; ++i) {
1489 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1490 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1491 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1492 continue;
1493 }
1494
1495 int idx = subpass->color_attachments[i].attachment;
1496 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1497 struct radv_image *image = att->attachment->image;
1498 VkImageLayout layout = subpass->color_attachments[i].layout;
1499
1500 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1501
1502 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1503 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1504
1505 radv_load_color_clear_metadata(cmd_buffer, image, i);
1506
1507 if (image->surface.bpe >= 8)
1508 num_bpp64_colorbufs++;
1509 }
1510
1511 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1512 int idx = subpass->depth_stencil_attachment.attachment;
1513 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1514 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1515 struct radv_image *image = att->attachment->image;
1516 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1517 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1518 cmd_buffer->queue_family_index,
1519 cmd_buffer->queue_family_index);
1520 /* We currently don't support writing decompressed HTILE */
1521 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1522 radv_layout_is_htile_compressed(image, layout, queue_mask));
1523
1524 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1525
1526 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1527 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1528 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1529 }
1530 radv_load_ds_clear_metadata(cmd_buffer, image);
1531 } else {
1532 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1533 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1534 else
1535 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1536
1537 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1538 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1539 }
1540 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1541 S_028208_BR_X(framebuffer->width) |
1542 S_028208_BR_Y(framebuffer->height));
1543
1544 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1545 uint8_t watermark = 4; /* Default value for VI. */
1546
1547 /* For optimal DCC performance. */
1548 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1549 if (num_bpp64_colorbufs >= 5) {
1550 watermark = 8;
1551 } else {
1552 watermark = 6;
1553 }
1554 }
1555
1556 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1557 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1558 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1559 }
1560
1561 if (cmd_buffer->device->dfsm_allowed) {
1562 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1563 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1564 }
1565
1566 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1567 }
1568
1569 static void
1570 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1571 {
1572 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1573 struct radv_cmd_state *state = &cmd_buffer->state;
1574
1575 if (state->index_type != state->last_index_type) {
1576 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1577 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1578 2, state->index_type);
1579 } else {
1580 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1581 radeon_emit(cs, state->index_type);
1582 }
1583
1584 state->last_index_type = state->index_type;
1585 }
1586
1587 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1588 radeon_emit(cs, state->index_va);
1589 radeon_emit(cs, state->index_va >> 32);
1590
1591 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1592 radeon_emit(cs, state->max_index_count);
1593
1594 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1595 }
1596
1597 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1598 {
1599 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1600 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1601 uint32_t pa_sc_mode_cntl_1 =
1602 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1603 uint32_t db_count_control;
1604
1605 if(!cmd_buffer->state.active_occlusion_queries) {
1606 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1607 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1608 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1609 has_perfect_queries) {
1610 /* Re-enable out-of-order rasterization if the
1611 * bound pipeline supports it and if it's has
1612 * been disabled before starting any perfect
1613 * occlusion queries.
1614 */
1615 radeon_set_context_reg(cmd_buffer->cs,
1616 R_028A4C_PA_SC_MODE_CNTL_1,
1617 pa_sc_mode_cntl_1);
1618 }
1619 }
1620 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1621 } else {
1622 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1623 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1624
1625 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1626 db_count_control =
1627 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1628 S_028004_SAMPLE_RATE(sample_rate) |
1629 S_028004_ZPASS_ENABLE(1) |
1630 S_028004_SLICE_EVEN_ENABLE(1) |
1631 S_028004_SLICE_ODD_ENABLE(1);
1632
1633 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1634 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1635 has_perfect_queries) {
1636 /* If the bound pipeline has enabled
1637 * out-of-order rasterization, we should
1638 * disable it before starting any perfect
1639 * occlusion queries.
1640 */
1641 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1642
1643 radeon_set_context_reg(cmd_buffer->cs,
1644 R_028A4C_PA_SC_MODE_CNTL_1,
1645 pa_sc_mode_cntl_1);
1646 }
1647 } else {
1648 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1649 S_028004_SAMPLE_RATE(sample_rate);
1650 }
1651 }
1652
1653 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1654 }
1655
1656 static void
1657 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1658 {
1659 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1660
1661 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1662 radv_emit_viewport(cmd_buffer);
1663
1664 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1665 !cmd_buffer->device->physical_device->has_scissor_bug)
1666 radv_emit_scissor(cmd_buffer);
1667
1668 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1669 radv_emit_line_width(cmd_buffer);
1670
1671 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1672 radv_emit_blend_constants(cmd_buffer);
1673
1674 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1675 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1676 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1677 radv_emit_stencil(cmd_buffer);
1678
1679 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1680 radv_emit_depth_bounds(cmd_buffer);
1681
1682 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1683 radv_emit_depth_bias(cmd_buffer);
1684
1685 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1686 radv_emit_discard_rectangle(cmd_buffer);
1687
1688 cmd_buffer->state.dirty &= ~states;
1689 }
1690
1691 static void
1692 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1693 VkPipelineBindPoint bind_point)
1694 {
1695 struct radv_descriptor_state *descriptors_state =
1696 radv_get_descriptors_state(cmd_buffer, bind_point);
1697 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1698 unsigned bo_offset;
1699
1700 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1701 set->mapped_ptr,
1702 &bo_offset))
1703 return;
1704
1705 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1706 set->va += bo_offset;
1707 }
1708
1709 static void
1710 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1711 VkPipelineBindPoint bind_point)
1712 {
1713 struct radv_descriptor_state *descriptors_state =
1714 radv_get_descriptors_state(cmd_buffer, bind_point);
1715 uint8_t ptr_size = HAVE_32BIT_POINTERS ? 1 : 2;
1716 uint32_t size = MAX_SETS * 4 * ptr_size;
1717 uint32_t offset;
1718 void *ptr;
1719
1720 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1721 256, &offset, &ptr))
1722 return;
1723
1724 for (unsigned i = 0; i < MAX_SETS; i++) {
1725 uint32_t *uptr = ((uint32_t *)ptr) + i * ptr_size;
1726 uint64_t set_va = 0;
1727 struct radv_descriptor_set *set = descriptors_state->sets[i];
1728 if (descriptors_state->valid & (1u << i))
1729 set_va = set->va;
1730 uptr[0] = set_va & 0xffffffff;
1731 if (ptr_size == 2)
1732 uptr[1] = set_va >> 32;
1733 }
1734
1735 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1736 va += offset;
1737
1738 if (cmd_buffer->state.pipeline) {
1739 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1740 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1741 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1742
1743 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1744 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1745 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1746
1747 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1748 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1749 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1750
1751 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1752 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1753 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1754
1755 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1756 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1757 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1758 }
1759
1760 if (cmd_buffer->state.compute_pipeline)
1761 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1762 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1763 }
1764
1765 static void
1766 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1767 VkShaderStageFlags stages)
1768 {
1769 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1770 VK_PIPELINE_BIND_POINT_COMPUTE :
1771 VK_PIPELINE_BIND_POINT_GRAPHICS;
1772 struct radv_descriptor_state *descriptors_state =
1773 radv_get_descriptors_state(cmd_buffer, bind_point);
1774 struct radv_cmd_state *state = &cmd_buffer->state;
1775 bool flush_indirect_descriptors;
1776
1777 if (!descriptors_state->dirty)
1778 return;
1779
1780 if (descriptors_state->push_dirty)
1781 radv_flush_push_descriptors(cmd_buffer, bind_point);
1782
1783 flush_indirect_descriptors =
1784 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1785 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1786 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1787 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1788
1789 if (flush_indirect_descriptors)
1790 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1791
1792 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1793 cmd_buffer->cs,
1794 MAX_SETS * MESA_SHADER_STAGES * 4);
1795
1796 if (cmd_buffer->state.pipeline) {
1797 radv_foreach_stage(stage, stages) {
1798 if (!cmd_buffer->state.pipeline->shaders[stage])
1799 continue;
1800
1801 radv_emit_descriptor_pointers(cmd_buffer,
1802 cmd_buffer->state.pipeline,
1803 descriptors_state, stage);
1804 }
1805 }
1806
1807 if (cmd_buffer->state.compute_pipeline &&
1808 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1809 radv_emit_descriptor_pointers(cmd_buffer,
1810 cmd_buffer->state.compute_pipeline,
1811 descriptors_state,
1812 MESA_SHADER_COMPUTE);
1813 }
1814
1815 descriptors_state->dirty = 0;
1816 descriptors_state->push_dirty = false;
1817
1818 assert(cmd_buffer->cs->cdw <= cdw_max);
1819
1820 if (unlikely(cmd_buffer->device->trace_bo))
1821 radv_save_descriptors(cmd_buffer, bind_point);
1822 }
1823
1824 static void
1825 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1826 VkShaderStageFlags stages)
1827 {
1828 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1829 ? cmd_buffer->state.compute_pipeline
1830 : cmd_buffer->state.pipeline;
1831 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1832 VK_PIPELINE_BIND_POINT_COMPUTE :
1833 VK_PIPELINE_BIND_POINT_GRAPHICS;
1834 struct radv_descriptor_state *descriptors_state =
1835 radv_get_descriptors_state(cmd_buffer, bind_point);
1836 struct radv_pipeline_layout *layout = pipeline->layout;
1837 struct radv_shader_variant *shader, *prev_shader;
1838 unsigned offset;
1839 void *ptr;
1840 uint64_t va;
1841
1842 stages &= cmd_buffer->push_constant_stages;
1843 if (!stages ||
1844 (!layout->push_constant_size && !layout->dynamic_offset_count))
1845 return;
1846
1847 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1848 16 * layout->dynamic_offset_count,
1849 256, &offset, &ptr))
1850 return;
1851
1852 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1853 memcpy((char*)ptr + layout->push_constant_size,
1854 descriptors_state->dynamic_buffers,
1855 16 * layout->dynamic_offset_count);
1856
1857 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1858 va += offset;
1859
1860 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1861 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1862
1863 prev_shader = NULL;
1864 radv_foreach_stage(stage, stages) {
1865 shader = radv_get_shader(pipeline, stage);
1866
1867 /* Avoid redundantly emitting the address for merged stages. */
1868 if (shader && shader != prev_shader) {
1869 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1870 AC_UD_PUSH_CONSTANTS, va);
1871
1872 prev_shader = shader;
1873 }
1874 }
1875
1876 cmd_buffer->push_constant_stages &= ~stages;
1877 assert(cmd_buffer->cs->cdw <= cdw_max);
1878 }
1879
1880 static void
1881 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1882 bool pipeline_is_dirty)
1883 {
1884 if ((pipeline_is_dirty ||
1885 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1886 cmd_buffer->state.pipeline->vertex_elements.count &&
1887 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1888 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1889 unsigned vb_offset;
1890 void *vb_ptr;
1891 uint32_t i = 0;
1892 uint32_t count = velems->count;
1893 uint64_t va;
1894
1895 /* allocate some descriptor state for vertex buffers */
1896 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1897 &vb_offset, &vb_ptr))
1898 return;
1899
1900 for (i = 0; i < count; i++) {
1901 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1902 uint32_t offset;
1903 int vb = velems->binding[i];
1904 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1905 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1906
1907 va = radv_buffer_get_va(buffer->bo);
1908
1909 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1910 va += offset + buffer->offset;
1911 desc[0] = va;
1912 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1913 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1914 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1915 else
1916 desc[2] = buffer->size - offset;
1917 desc[3] = velems->rsrc_word3[i];
1918 }
1919
1920 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1921 va += vb_offset;
1922
1923 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1924 AC_UD_VS_VERTEX_BUFFERS, va);
1925
1926 cmd_buffer->state.vb_va = va;
1927 cmd_buffer->state.vb_size = count * 16;
1928 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1929 }
1930 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1931 }
1932
1933 static void
1934 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1935 {
1936 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1937 struct radv_userdata_info *loc;
1938 uint32_t base_reg;
1939
1940 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
1941 if (!radv_get_shader(pipeline, stage))
1942 continue;
1943
1944 loc = radv_lookup_user_sgpr(pipeline, stage,
1945 AC_UD_STREAMOUT_BUFFERS);
1946 if (loc->sgpr_idx == -1)
1947 continue;
1948
1949 base_reg = pipeline->user_data_0[stage];
1950
1951 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1952 base_reg + loc->sgpr_idx * 4, va, false);
1953 }
1954
1955 if (pipeline->gs_copy_shader) {
1956 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
1957 if (loc->sgpr_idx != -1) {
1958 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
1959
1960 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1961 base_reg + loc->sgpr_idx * 4, va, false);
1962 }
1963 }
1964 }
1965
1966 static void
1967 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
1968 {
1969 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
1970 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
1971 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
1972 unsigned so_offset;
1973 void *so_ptr;
1974 uint64_t va;
1975
1976 /* Allocate some descriptor state for streamout buffers. */
1977 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
1978 MAX_SO_BUFFERS * 16, 256,
1979 &so_offset, &so_ptr))
1980 return;
1981
1982 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
1983 struct radv_buffer *buffer = sb[i].buffer;
1984 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
1985
1986 if (!(so->enabled_mask & (1 << i)))
1987 continue;
1988
1989 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
1990
1991 va += sb[i].offset;
1992
1993 /* Set the descriptor.
1994 *
1995 * On VI, the format must be non-INVALID, otherwise
1996 * the buffer will be considered not bound and store
1997 * instructions will be no-ops.
1998 */
1999 desc[0] = va;
2000 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2001 desc[2] = 0xffffffff;
2002 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2003 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2004 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2005 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2006 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2007 }
2008
2009 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2010 va += so_offset;
2011
2012 radv_emit_streamout_buffers(cmd_buffer, va);
2013 }
2014
2015 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2016 }
2017
2018 static void
2019 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2020 {
2021 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2022 radv_flush_streamout_descriptors(cmd_buffer);
2023 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2024 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2025 }
2026
2027 static void
2028 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
2029 bool instanced_draw, bool indirect_draw,
2030 uint32_t draw_vertex_count)
2031 {
2032 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2033 struct radv_cmd_state *state = &cmd_buffer->state;
2034 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2035 uint32_t ia_multi_vgt_param;
2036 int32_t primitive_reset_en;
2037
2038 /* Draw state. */
2039 ia_multi_vgt_param =
2040 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2041 indirect_draw, draw_vertex_count);
2042
2043 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2044 if (info->chip_class >= GFX9) {
2045 radeon_set_uconfig_reg_idx(cs,
2046 R_030960_IA_MULTI_VGT_PARAM,
2047 4, ia_multi_vgt_param);
2048 } else if (info->chip_class >= CIK) {
2049 radeon_set_context_reg_idx(cs,
2050 R_028AA8_IA_MULTI_VGT_PARAM,
2051 1, ia_multi_vgt_param);
2052 } else {
2053 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2054 ia_multi_vgt_param);
2055 }
2056 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2057 }
2058
2059 /* Primitive restart. */
2060 primitive_reset_en =
2061 indexed_draw && state->pipeline->graphics.prim_restart_enable;
2062
2063 if (primitive_reset_en != state->last_primitive_reset_en) {
2064 state->last_primitive_reset_en = primitive_reset_en;
2065 if (info->chip_class >= GFX9) {
2066 radeon_set_uconfig_reg(cs,
2067 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2068 primitive_reset_en);
2069 } else {
2070 radeon_set_context_reg(cs,
2071 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2072 primitive_reset_en);
2073 }
2074 }
2075
2076 if (primitive_reset_en) {
2077 uint32_t primitive_reset_index =
2078 state->index_type ? 0xffffffffu : 0xffffu;
2079
2080 if (primitive_reset_index != state->last_primitive_reset_index) {
2081 radeon_set_context_reg(cs,
2082 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2083 primitive_reset_index);
2084 state->last_primitive_reset_index = primitive_reset_index;
2085 }
2086 }
2087 }
2088
2089 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2090 VkPipelineStageFlags src_stage_mask)
2091 {
2092 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2093 VK_PIPELINE_STAGE_TRANSFER_BIT |
2094 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2095 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2096 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2097 }
2098
2099 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2100 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2101 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2102 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2103 VK_PIPELINE_STAGE_TRANSFER_BIT |
2104 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2105 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2106 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2107 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2108 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2109 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2110 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2111 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2112 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2113 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2114 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2115 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2116 }
2117 }
2118
2119 static enum radv_cmd_flush_bits
2120 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2121 VkAccessFlags src_flags,
2122 struct radv_image *image)
2123 {
2124 bool flush_CB_meta = true, flush_DB_meta = true;
2125 enum radv_cmd_flush_bits flush_bits = 0;
2126 uint32_t b;
2127
2128 if (image) {
2129 if (!radv_image_has_CB_metadata(image))
2130 flush_CB_meta = false;
2131 if (!radv_image_has_htile(image))
2132 flush_DB_meta = false;
2133 }
2134
2135 for_each_bit(b, src_flags) {
2136 switch ((VkAccessFlagBits)(1 << b)) {
2137 case VK_ACCESS_SHADER_WRITE_BIT:
2138 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2139 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2140 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2141 break;
2142 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2143 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2144 if (flush_CB_meta)
2145 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2146 break;
2147 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2148 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2149 if (flush_DB_meta)
2150 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2151 break;
2152 case VK_ACCESS_TRANSFER_WRITE_BIT:
2153 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2154 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2155 RADV_CMD_FLAG_INV_GLOBAL_L2;
2156
2157 if (flush_CB_meta)
2158 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2159 if (flush_DB_meta)
2160 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2161 break;
2162 default:
2163 break;
2164 }
2165 }
2166 return flush_bits;
2167 }
2168
2169 static enum radv_cmd_flush_bits
2170 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2171 VkAccessFlags dst_flags,
2172 struct radv_image *image)
2173 {
2174 bool flush_CB_meta = true, flush_DB_meta = true;
2175 enum radv_cmd_flush_bits flush_bits = 0;
2176 bool flush_CB = true, flush_DB = true;
2177 bool image_is_coherent = false;
2178 uint32_t b;
2179
2180 if (image) {
2181 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2182 flush_CB = false;
2183 flush_DB = false;
2184 }
2185
2186 if (!radv_image_has_CB_metadata(image))
2187 flush_CB_meta = false;
2188 if (!radv_image_has_htile(image))
2189 flush_DB_meta = false;
2190
2191 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2192 if (image->info.samples == 1 &&
2193 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2194 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2195 !vk_format_is_stencil(image->vk_format)) {
2196 /* Single-sample color and single-sample depth
2197 * (not stencil) are coherent with shaders on
2198 * GFX9.
2199 */
2200 image_is_coherent = true;
2201 }
2202 }
2203 }
2204
2205 for_each_bit(b, dst_flags) {
2206 switch ((VkAccessFlagBits)(1 << b)) {
2207 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2208 case VK_ACCESS_INDEX_READ_BIT:
2209 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2210 break;
2211 case VK_ACCESS_UNIFORM_READ_BIT:
2212 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2213 break;
2214 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2215 case VK_ACCESS_TRANSFER_READ_BIT:
2216 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2217 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2218 RADV_CMD_FLAG_INV_GLOBAL_L2;
2219 break;
2220 case VK_ACCESS_SHADER_READ_BIT:
2221 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2222
2223 if (!image_is_coherent)
2224 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2225 break;
2226 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2227 if (flush_CB)
2228 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2229 if (flush_CB_meta)
2230 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2231 break;
2232 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2233 if (flush_DB)
2234 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2235 if (flush_DB_meta)
2236 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2237 break;
2238 default:
2239 break;
2240 }
2241 }
2242 return flush_bits;
2243 }
2244
2245 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2246 const struct radv_subpass_barrier *barrier)
2247 {
2248 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2249 NULL);
2250 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2251 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2252 NULL);
2253 }
2254
2255 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2256 struct radv_subpass_attachment att)
2257 {
2258 unsigned idx = att.attachment;
2259 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2260 VkImageSubresourceRange range;
2261 range.aspectMask = 0;
2262 range.baseMipLevel = view->base_mip;
2263 range.levelCount = 1;
2264 range.baseArrayLayer = view->base_layer;
2265 range.layerCount = cmd_buffer->state.framebuffer->layers;
2266
2267 radv_handle_image_transition(cmd_buffer,
2268 view->image,
2269 cmd_buffer->state.attachments[idx].current_layout,
2270 att.layout, 0, 0, &range);
2271
2272 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2273
2274
2275 }
2276
2277 void
2278 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2279 const struct radv_subpass *subpass, bool transitions)
2280 {
2281 if (transitions) {
2282 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2283
2284 for (unsigned i = 0; i < subpass->color_count; ++i) {
2285 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2286 radv_handle_subpass_image_transition(cmd_buffer,
2287 subpass->color_attachments[i]);
2288 }
2289
2290 for (unsigned i = 0; i < subpass->input_count; ++i) {
2291 radv_handle_subpass_image_transition(cmd_buffer,
2292 subpass->input_attachments[i]);
2293 }
2294
2295 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2296 radv_handle_subpass_image_transition(cmd_buffer,
2297 subpass->depth_stencil_attachment);
2298 }
2299 }
2300
2301 cmd_buffer->state.subpass = subpass;
2302
2303 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2304 }
2305
2306 static VkResult
2307 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2308 struct radv_render_pass *pass,
2309 const VkRenderPassBeginInfo *info)
2310 {
2311 struct radv_cmd_state *state = &cmd_buffer->state;
2312
2313 if (pass->attachment_count == 0) {
2314 state->attachments = NULL;
2315 return VK_SUCCESS;
2316 }
2317
2318 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2319 pass->attachment_count *
2320 sizeof(state->attachments[0]),
2321 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2322 if (state->attachments == NULL) {
2323 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2324 return cmd_buffer->record_result;
2325 }
2326
2327 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2328 struct radv_render_pass_attachment *att = &pass->attachments[i];
2329 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2330 VkImageAspectFlags clear_aspects = 0;
2331
2332 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2333 /* color attachment */
2334 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2335 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2336 }
2337 } else {
2338 /* depthstencil attachment */
2339 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2340 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2341 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2342 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2343 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2344 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2345 }
2346 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2347 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2348 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2349 }
2350 }
2351
2352 state->attachments[i].pending_clear_aspects = clear_aspects;
2353 state->attachments[i].cleared_views = 0;
2354 if (clear_aspects && info) {
2355 assert(info->clearValueCount > i);
2356 state->attachments[i].clear_value = info->pClearValues[i];
2357 }
2358
2359 state->attachments[i].current_layout = att->initial_layout;
2360 }
2361
2362 return VK_SUCCESS;
2363 }
2364
2365 VkResult radv_AllocateCommandBuffers(
2366 VkDevice _device,
2367 const VkCommandBufferAllocateInfo *pAllocateInfo,
2368 VkCommandBuffer *pCommandBuffers)
2369 {
2370 RADV_FROM_HANDLE(radv_device, device, _device);
2371 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2372
2373 VkResult result = VK_SUCCESS;
2374 uint32_t i;
2375
2376 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2377
2378 if (!list_empty(&pool->free_cmd_buffers)) {
2379 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2380
2381 list_del(&cmd_buffer->pool_link);
2382 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2383
2384 result = radv_reset_cmd_buffer(cmd_buffer);
2385 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2386 cmd_buffer->level = pAllocateInfo->level;
2387
2388 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2389 } else {
2390 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2391 &pCommandBuffers[i]);
2392 }
2393 if (result != VK_SUCCESS)
2394 break;
2395 }
2396
2397 if (result != VK_SUCCESS) {
2398 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2399 i, pCommandBuffers);
2400
2401 /* From the Vulkan 1.0.66 spec:
2402 *
2403 * "vkAllocateCommandBuffers can be used to create multiple
2404 * command buffers. If the creation of any of those command
2405 * buffers fails, the implementation must destroy all
2406 * successfully created command buffer objects from this
2407 * command, set all entries of the pCommandBuffers array to
2408 * NULL and return the error."
2409 */
2410 memset(pCommandBuffers, 0,
2411 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2412 }
2413
2414 return result;
2415 }
2416
2417 void radv_FreeCommandBuffers(
2418 VkDevice device,
2419 VkCommandPool commandPool,
2420 uint32_t commandBufferCount,
2421 const VkCommandBuffer *pCommandBuffers)
2422 {
2423 for (uint32_t i = 0; i < commandBufferCount; i++) {
2424 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2425
2426 if (cmd_buffer) {
2427 if (cmd_buffer->pool) {
2428 list_del(&cmd_buffer->pool_link);
2429 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2430 } else
2431 radv_cmd_buffer_destroy(cmd_buffer);
2432
2433 }
2434 }
2435 }
2436
2437 VkResult radv_ResetCommandBuffer(
2438 VkCommandBuffer commandBuffer,
2439 VkCommandBufferResetFlags flags)
2440 {
2441 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2442 return radv_reset_cmd_buffer(cmd_buffer);
2443 }
2444
2445 VkResult radv_BeginCommandBuffer(
2446 VkCommandBuffer commandBuffer,
2447 const VkCommandBufferBeginInfo *pBeginInfo)
2448 {
2449 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2450 VkResult result = VK_SUCCESS;
2451
2452 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2453 /* If the command buffer has already been resetted with
2454 * vkResetCommandBuffer, no need to do it again.
2455 */
2456 result = radv_reset_cmd_buffer(cmd_buffer);
2457 if (result != VK_SUCCESS)
2458 return result;
2459 }
2460
2461 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2462 cmd_buffer->state.last_primitive_reset_en = -1;
2463 cmd_buffer->state.last_index_type = -1;
2464 cmd_buffer->state.last_num_instances = -1;
2465 cmd_buffer->state.last_vertex_offset = -1;
2466 cmd_buffer->state.last_first_instance = -1;
2467 cmd_buffer->state.predication_type = -1;
2468 cmd_buffer->usage_flags = pBeginInfo->flags;
2469
2470 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2471 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2472 assert(pBeginInfo->pInheritanceInfo);
2473 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2474 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2475
2476 struct radv_subpass *subpass =
2477 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2478
2479 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2480 if (result != VK_SUCCESS)
2481 return result;
2482
2483 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2484 }
2485
2486 if (unlikely(cmd_buffer->device->trace_bo)) {
2487 struct radv_device *device = cmd_buffer->device;
2488
2489 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2490 device->trace_bo);
2491
2492 radv_cmd_buffer_trace_emit(cmd_buffer);
2493 }
2494
2495 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2496
2497 return result;
2498 }
2499
2500 void radv_CmdBindVertexBuffers(
2501 VkCommandBuffer commandBuffer,
2502 uint32_t firstBinding,
2503 uint32_t bindingCount,
2504 const VkBuffer* pBuffers,
2505 const VkDeviceSize* pOffsets)
2506 {
2507 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2508 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2509 bool changed = false;
2510
2511 /* We have to defer setting up vertex buffer since we need the buffer
2512 * stride from the pipeline. */
2513
2514 assert(firstBinding + bindingCount <= MAX_VBS);
2515 for (uint32_t i = 0; i < bindingCount; i++) {
2516 uint32_t idx = firstBinding + i;
2517
2518 if (!changed &&
2519 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2520 vb[idx].offset != pOffsets[i])) {
2521 changed = true;
2522 }
2523
2524 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2525 vb[idx].offset = pOffsets[i];
2526
2527 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2528 vb[idx].buffer->bo);
2529 }
2530
2531 if (!changed) {
2532 /* No state changes. */
2533 return;
2534 }
2535
2536 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2537 }
2538
2539 void radv_CmdBindIndexBuffer(
2540 VkCommandBuffer commandBuffer,
2541 VkBuffer buffer,
2542 VkDeviceSize offset,
2543 VkIndexType indexType)
2544 {
2545 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2546 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2547
2548 if (cmd_buffer->state.index_buffer == index_buffer &&
2549 cmd_buffer->state.index_offset == offset &&
2550 cmd_buffer->state.index_type == indexType) {
2551 /* No state changes. */
2552 return;
2553 }
2554
2555 cmd_buffer->state.index_buffer = index_buffer;
2556 cmd_buffer->state.index_offset = offset;
2557 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2558 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2559 cmd_buffer->state.index_va += index_buffer->offset + offset;
2560
2561 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2562 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2563 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2564 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2565 }
2566
2567
2568 static void
2569 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2570 VkPipelineBindPoint bind_point,
2571 struct radv_descriptor_set *set, unsigned idx)
2572 {
2573 struct radeon_winsys *ws = cmd_buffer->device->ws;
2574
2575 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2576
2577 assert(set);
2578 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2579
2580 if (!cmd_buffer->device->use_global_bo_list) {
2581 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2582 if (set->descriptors[j])
2583 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2584 }
2585
2586 if(set->bo)
2587 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2588 }
2589
2590 void radv_CmdBindDescriptorSets(
2591 VkCommandBuffer commandBuffer,
2592 VkPipelineBindPoint pipelineBindPoint,
2593 VkPipelineLayout _layout,
2594 uint32_t firstSet,
2595 uint32_t descriptorSetCount,
2596 const VkDescriptorSet* pDescriptorSets,
2597 uint32_t dynamicOffsetCount,
2598 const uint32_t* pDynamicOffsets)
2599 {
2600 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2601 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2602 unsigned dyn_idx = 0;
2603
2604 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2605 struct radv_descriptor_state *descriptors_state =
2606 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2607
2608 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2609 unsigned idx = i + firstSet;
2610 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2611 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2612
2613 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2614 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2615 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2616 assert(dyn_idx < dynamicOffsetCount);
2617
2618 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2619 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2620 dst[0] = va;
2621 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2622 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2623 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2624 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2625 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2626 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2627 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2628 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2629 cmd_buffer->push_constant_stages |=
2630 set->layout->dynamic_shader_stages;
2631 }
2632 }
2633 }
2634
2635 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2636 struct radv_descriptor_set *set,
2637 struct radv_descriptor_set_layout *layout,
2638 VkPipelineBindPoint bind_point)
2639 {
2640 struct radv_descriptor_state *descriptors_state =
2641 radv_get_descriptors_state(cmd_buffer, bind_point);
2642 set->size = layout->size;
2643 set->layout = layout;
2644
2645 if (descriptors_state->push_set.capacity < set->size) {
2646 size_t new_size = MAX2(set->size, 1024);
2647 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2648 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2649
2650 free(set->mapped_ptr);
2651 set->mapped_ptr = malloc(new_size);
2652
2653 if (!set->mapped_ptr) {
2654 descriptors_state->push_set.capacity = 0;
2655 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2656 return false;
2657 }
2658
2659 descriptors_state->push_set.capacity = new_size;
2660 }
2661
2662 return true;
2663 }
2664
2665 void radv_meta_push_descriptor_set(
2666 struct radv_cmd_buffer* cmd_buffer,
2667 VkPipelineBindPoint pipelineBindPoint,
2668 VkPipelineLayout _layout,
2669 uint32_t set,
2670 uint32_t descriptorWriteCount,
2671 const VkWriteDescriptorSet* pDescriptorWrites)
2672 {
2673 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2674 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2675 unsigned bo_offset;
2676
2677 assert(set == 0);
2678 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2679
2680 push_set->size = layout->set[set].layout->size;
2681 push_set->layout = layout->set[set].layout;
2682
2683 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2684 &bo_offset,
2685 (void**) &push_set->mapped_ptr))
2686 return;
2687
2688 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2689 push_set->va += bo_offset;
2690
2691 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2692 radv_descriptor_set_to_handle(push_set),
2693 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2694
2695 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2696 }
2697
2698 void radv_CmdPushDescriptorSetKHR(
2699 VkCommandBuffer commandBuffer,
2700 VkPipelineBindPoint pipelineBindPoint,
2701 VkPipelineLayout _layout,
2702 uint32_t set,
2703 uint32_t descriptorWriteCount,
2704 const VkWriteDescriptorSet* pDescriptorWrites)
2705 {
2706 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2707 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2708 struct radv_descriptor_state *descriptors_state =
2709 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2710 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2711
2712 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2713
2714 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2715 layout->set[set].layout,
2716 pipelineBindPoint))
2717 return;
2718
2719 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2720 radv_descriptor_set_to_handle(push_set),
2721 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2722
2723 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2724 descriptors_state->push_dirty = true;
2725 }
2726
2727 void radv_CmdPushDescriptorSetWithTemplateKHR(
2728 VkCommandBuffer commandBuffer,
2729 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2730 VkPipelineLayout _layout,
2731 uint32_t set,
2732 const void* pData)
2733 {
2734 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2735 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2736 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2737 struct radv_descriptor_state *descriptors_state =
2738 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2739 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2740
2741 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2742
2743 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2744 layout->set[set].layout,
2745 templ->bind_point))
2746 return;
2747
2748 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2749 descriptorUpdateTemplate, pData);
2750
2751 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2752 descriptors_state->push_dirty = true;
2753 }
2754
2755 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2756 VkPipelineLayout layout,
2757 VkShaderStageFlags stageFlags,
2758 uint32_t offset,
2759 uint32_t size,
2760 const void* pValues)
2761 {
2762 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2763 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2764 cmd_buffer->push_constant_stages |= stageFlags;
2765 }
2766
2767 VkResult radv_EndCommandBuffer(
2768 VkCommandBuffer commandBuffer)
2769 {
2770 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2771
2772 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2773 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2774 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2775 si_emit_cache_flush(cmd_buffer);
2776 }
2777
2778 /* Make sure CP DMA is idle at the end of IBs because the kernel
2779 * doesn't wait for it.
2780 */
2781 si_cp_dma_wait_for_idle(cmd_buffer);
2782
2783 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2784
2785 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2786 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2787
2788 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2789
2790 return cmd_buffer->record_result;
2791 }
2792
2793 static void
2794 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2795 {
2796 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2797
2798 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2799 return;
2800
2801 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2802
2803 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2804 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2805
2806 cmd_buffer->compute_scratch_size_needed =
2807 MAX2(cmd_buffer->compute_scratch_size_needed,
2808 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2809
2810 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2811 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2812
2813 if (unlikely(cmd_buffer->device->trace_bo))
2814 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2815 }
2816
2817 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2818 VkPipelineBindPoint bind_point)
2819 {
2820 struct radv_descriptor_state *descriptors_state =
2821 radv_get_descriptors_state(cmd_buffer, bind_point);
2822
2823 descriptors_state->dirty |= descriptors_state->valid;
2824 }
2825
2826 void radv_CmdBindPipeline(
2827 VkCommandBuffer commandBuffer,
2828 VkPipelineBindPoint pipelineBindPoint,
2829 VkPipeline _pipeline)
2830 {
2831 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2832 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2833
2834 switch (pipelineBindPoint) {
2835 case VK_PIPELINE_BIND_POINT_COMPUTE:
2836 if (cmd_buffer->state.compute_pipeline == pipeline)
2837 return;
2838 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2839
2840 cmd_buffer->state.compute_pipeline = pipeline;
2841 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2842 break;
2843 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2844 if (cmd_buffer->state.pipeline == pipeline)
2845 return;
2846 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2847
2848 cmd_buffer->state.pipeline = pipeline;
2849 if (!pipeline)
2850 break;
2851
2852 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2853 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2854
2855 /* the new vertex shader might not have the same user regs */
2856 cmd_buffer->state.last_first_instance = -1;
2857 cmd_buffer->state.last_vertex_offset = -1;
2858
2859 /* Prefetch all pipeline shaders at first draw time. */
2860 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2861
2862 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2863 radv_bind_streamout_state(cmd_buffer, pipeline);
2864
2865 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2866 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2867 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2868 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2869
2870 if (radv_pipeline_has_tess(pipeline))
2871 cmd_buffer->tess_rings_needed = true;
2872 break;
2873 default:
2874 assert(!"invalid bind point");
2875 break;
2876 }
2877 }
2878
2879 void radv_CmdSetViewport(
2880 VkCommandBuffer commandBuffer,
2881 uint32_t firstViewport,
2882 uint32_t viewportCount,
2883 const VkViewport* pViewports)
2884 {
2885 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2886 struct radv_cmd_state *state = &cmd_buffer->state;
2887 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2888
2889 assert(firstViewport < MAX_VIEWPORTS);
2890 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2891
2892 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2893 viewportCount * sizeof(*pViewports));
2894
2895 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2896 }
2897
2898 void radv_CmdSetScissor(
2899 VkCommandBuffer commandBuffer,
2900 uint32_t firstScissor,
2901 uint32_t scissorCount,
2902 const VkRect2D* pScissors)
2903 {
2904 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2905 struct radv_cmd_state *state = &cmd_buffer->state;
2906 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2907
2908 assert(firstScissor < MAX_SCISSORS);
2909 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2910
2911 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2912 scissorCount * sizeof(*pScissors));
2913
2914 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2915 }
2916
2917 void radv_CmdSetLineWidth(
2918 VkCommandBuffer commandBuffer,
2919 float lineWidth)
2920 {
2921 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2922 cmd_buffer->state.dynamic.line_width = lineWidth;
2923 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2924 }
2925
2926 void radv_CmdSetDepthBias(
2927 VkCommandBuffer commandBuffer,
2928 float depthBiasConstantFactor,
2929 float depthBiasClamp,
2930 float depthBiasSlopeFactor)
2931 {
2932 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2933
2934 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2935 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2936 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2937
2938 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2939 }
2940
2941 void radv_CmdSetBlendConstants(
2942 VkCommandBuffer commandBuffer,
2943 const float blendConstants[4])
2944 {
2945 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2946
2947 memcpy(cmd_buffer->state.dynamic.blend_constants,
2948 blendConstants, sizeof(float) * 4);
2949
2950 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2951 }
2952
2953 void radv_CmdSetDepthBounds(
2954 VkCommandBuffer commandBuffer,
2955 float minDepthBounds,
2956 float maxDepthBounds)
2957 {
2958 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2959
2960 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2961 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2962
2963 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2964 }
2965
2966 void radv_CmdSetStencilCompareMask(
2967 VkCommandBuffer commandBuffer,
2968 VkStencilFaceFlags faceMask,
2969 uint32_t compareMask)
2970 {
2971 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2972
2973 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2974 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2975 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2976 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2977
2978 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2979 }
2980
2981 void radv_CmdSetStencilWriteMask(
2982 VkCommandBuffer commandBuffer,
2983 VkStencilFaceFlags faceMask,
2984 uint32_t writeMask)
2985 {
2986 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2987
2988 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2989 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2990 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2991 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2992
2993 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2994 }
2995
2996 void radv_CmdSetStencilReference(
2997 VkCommandBuffer commandBuffer,
2998 VkStencilFaceFlags faceMask,
2999 uint32_t reference)
3000 {
3001 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3002
3003 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3004 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3005 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3006 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3007
3008 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3009 }
3010
3011 void radv_CmdSetDiscardRectangleEXT(
3012 VkCommandBuffer commandBuffer,
3013 uint32_t firstDiscardRectangle,
3014 uint32_t discardRectangleCount,
3015 const VkRect2D* pDiscardRectangles)
3016 {
3017 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3018 struct radv_cmd_state *state = &cmd_buffer->state;
3019 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3020
3021 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3022 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3023
3024 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3025 pDiscardRectangles, discardRectangleCount);
3026
3027 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3028 }
3029
3030 void radv_CmdExecuteCommands(
3031 VkCommandBuffer commandBuffer,
3032 uint32_t commandBufferCount,
3033 const VkCommandBuffer* pCmdBuffers)
3034 {
3035 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3036
3037 assert(commandBufferCount > 0);
3038
3039 /* Emit pending flushes on primary prior to executing secondary */
3040 si_emit_cache_flush(primary);
3041
3042 for (uint32_t i = 0; i < commandBufferCount; i++) {
3043 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3044
3045 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3046 secondary->scratch_size_needed);
3047 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3048 secondary->compute_scratch_size_needed);
3049
3050 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3051 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3052 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3053 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3054 if (secondary->tess_rings_needed)
3055 primary->tess_rings_needed = true;
3056 if (secondary->sample_positions_needed)
3057 primary->sample_positions_needed = true;
3058
3059 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3060
3061
3062 /* When the secondary command buffer is compute only we don't
3063 * need to re-emit the current graphics pipeline.
3064 */
3065 if (secondary->state.emitted_pipeline) {
3066 primary->state.emitted_pipeline =
3067 secondary->state.emitted_pipeline;
3068 }
3069
3070 /* When the secondary command buffer is graphics only we don't
3071 * need to re-emit the current compute pipeline.
3072 */
3073 if (secondary->state.emitted_compute_pipeline) {
3074 primary->state.emitted_compute_pipeline =
3075 secondary->state.emitted_compute_pipeline;
3076 }
3077
3078 /* Only re-emit the draw packets when needed. */
3079 if (secondary->state.last_primitive_reset_en != -1) {
3080 primary->state.last_primitive_reset_en =
3081 secondary->state.last_primitive_reset_en;
3082 }
3083
3084 if (secondary->state.last_primitive_reset_index) {
3085 primary->state.last_primitive_reset_index =
3086 secondary->state.last_primitive_reset_index;
3087 }
3088
3089 if (secondary->state.last_ia_multi_vgt_param) {
3090 primary->state.last_ia_multi_vgt_param =
3091 secondary->state.last_ia_multi_vgt_param;
3092 }
3093
3094 primary->state.last_first_instance = secondary->state.last_first_instance;
3095 primary->state.last_num_instances = secondary->state.last_num_instances;
3096 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3097
3098 if (secondary->state.last_index_type != -1) {
3099 primary->state.last_index_type =
3100 secondary->state.last_index_type;
3101 }
3102 }
3103
3104 /* After executing commands from secondary buffers we have to dirty
3105 * some states.
3106 */
3107 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3108 RADV_CMD_DIRTY_INDEX_BUFFER |
3109 RADV_CMD_DIRTY_DYNAMIC_ALL;
3110 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3111 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3112 }
3113
3114 VkResult radv_CreateCommandPool(
3115 VkDevice _device,
3116 const VkCommandPoolCreateInfo* pCreateInfo,
3117 const VkAllocationCallbacks* pAllocator,
3118 VkCommandPool* pCmdPool)
3119 {
3120 RADV_FROM_HANDLE(radv_device, device, _device);
3121 struct radv_cmd_pool *pool;
3122
3123 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3124 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3125 if (pool == NULL)
3126 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3127
3128 if (pAllocator)
3129 pool->alloc = *pAllocator;
3130 else
3131 pool->alloc = device->alloc;
3132
3133 list_inithead(&pool->cmd_buffers);
3134 list_inithead(&pool->free_cmd_buffers);
3135
3136 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3137
3138 *pCmdPool = radv_cmd_pool_to_handle(pool);
3139
3140 return VK_SUCCESS;
3141
3142 }
3143
3144 void radv_DestroyCommandPool(
3145 VkDevice _device,
3146 VkCommandPool commandPool,
3147 const VkAllocationCallbacks* pAllocator)
3148 {
3149 RADV_FROM_HANDLE(radv_device, device, _device);
3150 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3151
3152 if (!pool)
3153 return;
3154
3155 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3156 &pool->cmd_buffers, pool_link) {
3157 radv_cmd_buffer_destroy(cmd_buffer);
3158 }
3159
3160 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3161 &pool->free_cmd_buffers, pool_link) {
3162 radv_cmd_buffer_destroy(cmd_buffer);
3163 }
3164
3165 vk_free2(&device->alloc, pAllocator, pool);
3166 }
3167
3168 VkResult radv_ResetCommandPool(
3169 VkDevice device,
3170 VkCommandPool commandPool,
3171 VkCommandPoolResetFlags flags)
3172 {
3173 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3174 VkResult result;
3175
3176 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3177 &pool->cmd_buffers, pool_link) {
3178 result = radv_reset_cmd_buffer(cmd_buffer);
3179 if (result != VK_SUCCESS)
3180 return result;
3181 }
3182
3183 return VK_SUCCESS;
3184 }
3185
3186 void radv_TrimCommandPool(
3187 VkDevice device,
3188 VkCommandPool commandPool,
3189 VkCommandPoolTrimFlagsKHR flags)
3190 {
3191 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3192
3193 if (!pool)
3194 return;
3195
3196 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3197 &pool->free_cmd_buffers, pool_link) {
3198 radv_cmd_buffer_destroy(cmd_buffer);
3199 }
3200 }
3201
3202 void radv_CmdBeginRenderPass(
3203 VkCommandBuffer commandBuffer,
3204 const VkRenderPassBeginInfo* pRenderPassBegin,
3205 VkSubpassContents contents)
3206 {
3207 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3208 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3209 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3210
3211 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3212 cmd_buffer->cs, 2048);
3213 MAYBE_UNUSED VkResult result;
3214
3215 cmd_buffer->state.framebuffer = framebuffer;
3216 cmd_buffer->state.pass = pass;
3217 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3218
3219 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3220 if (result != VK_SUCCESS)
3221 return;
3222
3223 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3224 assert(cmd_buffer->cs->cdw <= cdw_max);
3225
3226 radv_cmd_buffer_clear_subpass(cmd_buffer);
3227 }
3228
3229 void radv_CmdBeginRenderPass2KHR(
3230 VkCommandBuffer commandBuffer,
3231 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3232 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3233 {
3234 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3235 pSubpassBeginInfo->contents);
3236 }
3237
3238 void radv_CmdNextSubpass(
3239 VkCommandBuffer commandBuffer,
3240 VkSubpassContents contents)
3241 {
3242 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3243
3244 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3245
3246 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3247 2048);
3248
3249 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3250 radv_cmd_buffer_clear_subpass(cmd_buffer);
3251 }
3252
3253 void radv_CmdNextSubpass2KHR(
3254 VkCommandBuffer commandBuffer,
3255 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3256 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3257 {
3258 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3259 }
3260
3261 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3262 {
3263 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3264 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3265 if (!radv_get_shader(pipeline, stage))
3266 continue;
3267
3268 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3269 if (loc->sgpr_idx == -1)
3270 continue;
3271 uint32_t base_reg = pipeline->user_data_0[stage];
3272 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3273
3274 }
3275 if (pipeline->gs_copy_shader) {
3276 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3277 if (loc->sgpr_idx != -1) {
3278 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3279 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3280 }
3281 }
3282 }
3283
3284 static void
3285 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3286 uint32_t vertex_count,
3287 bool use_opaque)
3288 {
3289 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3290 radeon_emit(cmd_buffer->cs, vertex_count);
3291 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3292 S_0287F0_USE_OPAQUE(use_opaque));
3293 }
3294
3295 static void
3296 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3297 uint64_t index_va,
3298 uint32_t index_count)
3299 {
3300 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3301 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3302 radeon_emit(cmd_buffer->cs, index_va);
3303 radeon_emit(cmd_buffer->cs, index_va >> 32);
3304 radeon_emit(cmd_buffer->cs, index_count);
3305 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3306 }
3307
3308 static void
3309 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3310 bool indexed,
3311 uint32_t draw_count,
3312 uint64_t count_va,
3313 uint32_t stride)
3314 {
3315 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3316 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3317 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3318 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3319 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3320 bool predicating = cmd_buffer->state.predicating;
3321 assert(base_reg);
3322
3323 /* just reset draw state for vertex data */
3324 cmd_buffer->state.last_first_instance = -1;
3325 cmd_buffer->state.last_num_instances = -1;
3326 cmd_buffer->state.last_vertex_offset = -1;
3327
3328 if (draw_count == 1 && !count_va && !draw_id_enable) {
3329 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3330 PKT3_DRAW_INDIRECT, 3, predicating));
3331 radeon_emit(cs, 0);
3332 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3333 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3334 radeon_emit(cs, di_src_sel);
3335 } else {
3336 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3337 PKT3_DRAW_INDIRECT_MULTI,
3338 8, predicating));
3339 radeon_emit(cs, 0);
3340 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3341 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3342 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3343 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3344 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3345 radeon_emit(cs, draw_count); /* count */
3346 radeon_emit(cs, count_va); /* count_addr */
3347 radeon_emit(cs, count_va >> 32);
3348 radeon_emit(cs, stride); /* stride */
3349 radeon_emit(cs, di_src_sel);
3350 }
3351 }
3352
3353 struct radv_draw_info {
3354 /**
3355 * Number of vertices.
3356 */
3357 uint32_t count;
3358
3359 /**
3360 * Index of the first vertex.
3361 */
3362 int32_t vertex_offset;
3363
3364 /**
3365 * First instance id.
3366 */
3367 uint32_t first_instance;
3368
3369 /**
3370 * Number of instances.
3371 */
3372 uint32_t instance_count;
3373
3374 /**
3375 * First index (indexed draws only).
3376 */
3377 uint32_t first_index;
3378
3379 /**
3380 * Whether it's an indexed draw.
3381 */
3382 bool indexed;
3383
3384 /**
3385 * Indirect draw parameters resource.
3386 */
3387 struct radv_buffer *indirect;
3388 uint64_t indirect_offset;
3389 uint32_t stride;
3390
3391 /**
3392 * Draw count parameters resource.
3393 */
3394 struct radv_buffer *count_buffer;
3395 uint64_t count_buffer_offset;
3396
3397 /**
3398 * Stream output parameters resource.
3399 */
3400 struct radv_buffer *strmout_buffer;
3401 uint64_t strmout_buffer_offset;
3402 };
3403
3404 static void
3405 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3406 const struct radv_draw_info *info)
3407 {
3408 struct radv_cmd_state *state = &cmd_buffer->state;
3409 struct radeon_winsys *ws = cmd_buffer->device->ws;
3410 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3411
3412 if (info->strmout_buffer) {
3413 uint64_t va = radv_buffer_get_va(info->strmout_buffer->bo);
3414
3415 va += info->strmout_buffer->offset +
3416 info->strmout_buffer_offset;
3417
3418 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
3419 info->stride);
3420
3421 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3422 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3423 COPY_DATA_DST_SEL(COPY_DATA_REG) |
3424 COPY_DATA_WR_CONFIRM);
3425 radeon_emit(cs, va);
3426 radeon_emit(cs, va >> 32);
3427 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
3428 radeon_emit(cs, 0); /* unused */
3429
3430 radv_cs_add_buffer(ws, cs, info->strmout_buffer->bo);
3431 }
3432
3433 if (info->indirect) {
3434 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3435 uint64_t count_va = 0;
3436
3437 va += info->indirect->offset + info->indirect_offset;
3438
3439 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3440
3441 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3442 radeon_emit(cs, 1);
3443 radeon_emit(cs, va);
3444 radeon_emit(cs, va >> 32);
3445
3446 if (info->count_buffer) {
3447 count_va = radv_buffer_get_va(info->count_buffer->bo);
3448 count_va += info->count_buffer->offset +
3449 info->count_buffer_offset;
3450
3451 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3452 }
3453
3454 if (!state->subpass->view_mask) {
3455 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3456 info->indexed,
3457 info->count,
3458 count_va,
3459 info->stride);
3460 } else {
3461 unsigned i;
3462 for_each_bit(i, state->subpass->view_mask) {
3463 radv_emit_view_index(cmd_buffer, i);
3464
3465 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3466 info->indexed,
3467 info->count,
3468 count_va,
3469 info->stride);
3470 }
3471 }
3472 } else {
3473 assert(state->pipeline->graphics.vtx_base_sgpr);
3474
3475 if (info->vertex_offset != state->last_vertex_offset ||
3476 info->first_instance != state->last_first_instance) {
3477 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3478 state->pipeline->graphics.vtx_emit_num);
3479
3480 radeon_emit(cs, info->vertex_offset);
3481 radeon_emit(cs, info->first_instance);
3482 if (state->pipeline->graphics.vtx_emit_num == 3)
3483 radeon_emit(cs, 0);
3484 state->last_first_instance = info->first_instance;
3485 state->last_vertex_offset = info->vertex_offset;
3486 }
3487
3488 if (state->last_num_instances != info->instance_count) {
3489 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3490 radeon_emit(cs, info->instance_count);
3491 state->last_num_instances = info->instance_count;
3492 }
3493
3494 if (info->indexed) {
3495 int index_size = state->index_type ? 4 : 2;
3496 uint64_t index_va;
3497
3498 index_va = state->index_va;
3499 index_va += info->first_index * index_size;
3500
3501 if (!state->subpass->view_mask) {
3502 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3503 index_va,
3504 info->count);
3505 } else {
3506 unsigned i;
3507 for_each_bit(i, state->subpass->view_mask) {
3508 radv_emit_view_index(cmd_buffer, i);
3509
3510 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3511 index_va,
3512 info->count);
3513 }
3514 }
3515 } else {
3516 if (!state->subpass->view_mask) {
3517 radv_cs_emit_draw_packet(cmd_buffer,
3518 info->count,
3519 !!info->strmout_buffer);
3520 } else {
3521 unsigned i;
3522 for_each_bit(i, state->subpass->view_mask) {
3523 radv_emit_view_index(cmd_buffer, i);
3524
3525 radv_cs_emit_draw_packet(cmd_buffer,
3526 info->count,
3527 !!info->strmout_buffer);
3528 }
3529 }
3530 }
3531 }
3532 }
3533
3534 /*
3535 * Vega and raven have a bug which triggers if there are multiple context
3536 * register contexts active at the same time with different scissor values.
3537 *
3538 * There are two possible workarounds:
3539 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3540 * there is only ever 1 active set of scissor values at the same time.
3541 *
3542 * 2) Whenever the hardware switches contexts we have to set the scissor
3543 * registers again even if it is a noop. That way the new context gets
3544 * the correct scissor values.
3545 *
3546 * This implements option 2. radv_need_late_scissor_emission needs to
3547 * return true on affected HW if radv_emit_all_graphics_states sets
3548 * any context registers.
3549 */
3550 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3551 bool indexed_draw)
3552 {
3553 struct radv_cmd_state *state = &cmd_buffer->state;
3554
3555 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3556 return false;
3557
3558 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3559
3560 /* Index, vertex and streamout buffers don't change context regs, and
3561 * pipeline is handled later.
3562 */
3563 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3564 RADV_CMD_DIRTY_VERTEX_BUFFER |
3565 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3566 RADV_CMD_DIRTY_PIPELINE);
3567
3568 /* Assume all state changes except these two can imply context rolls. */
3569 if (cmd_buffer->state.dirty & used_states)
3570 return true;
3571
3572 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3573 return true;
3574
3575 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3576 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3577 return true;
3578
3579 return false;
3580 }
3581
3582 static void
3583 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3584 const struct radv_draw_info *info)
3585 {
3586 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3587
3588 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3589 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3590 radv_emit_rbplus_state(cmd_buffer);
3591
3592 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3593 radv_emit_graphics_pipeline(cmd_buffer);
3594
3595 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3596 radv_emit_framebuffer_state(cmd_buffer);
3597
3598 if (info->indexed) {
3599 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3600 radv_emit_index_buffer(cmd_buffer);
3601 } else {
3602 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3603 * so the state must be re-emitted before the next indexed
3604 * draw.
3605 */
3606 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3607 cmd_buffer->state.last_index_type = -1;
3608 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3609 }
3610 }
3611
3612 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3613
3614 radv_emit_draw_registers(cmd_buffer, info->indexed,
3615 info->instance_count > 1, info->indirect,
3616 info->indirect ? 0 : info->count);
3617
3618 if (late_scissor_emission)
3619 radv_emit_scissor(cmd_buffer);
3620 }
3621
3622 static void
3623 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3624 const struct radv_draw_info *info)
3625 {
3626 struct radeon_info *rad_info =
3627 &cmd_buffer->device->physical_device->rad_info;
3628 bool has_prefetch =
3629 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3630 bool pipeline_is_dirty =
3631 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3632 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3633
3634 MAYBE_UNUSED unsigned cdw_max =
3635 radeon_check_space(cmd_buffer->device->ws,
3636 cmd_buffer->cs, 4096);
3637
3638 /* Use optimal packet order based on whether we need to sync the
3639 * pipeline.
3640 */
3641 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3642 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3643 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3644 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3645 /* If we have to wait for idle, set all states first, so that
3646 * all SET packets are processed in parallel with previous draw
3647 * calls. Then upload descriptors, set shader pointers, and
3648 * draw, and prefetch at the end. This ensures that the time
3649 * the CUs are idle is very short. (there are only SET_SH
3650 * packets between the wait and the draw)
3651 */
3652 radv_emit_all_graphics_states(cmd_buffer, info);
3653 si_emit_cache_flush(cmd_buffer);
3654 /* <-- CUs are idle here --> */
3655
3656 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3657
3658 radv_emit_draw_packets(cmd_buffer, info);
3659 /* <-- CUs are busy here --> */
3660
3661 /* Start prefetches after the draw has been started. Both will
3662 * run in parallel, but starting the draw first is more
3663 * important.
3664 */
3665 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3666 radv_emit_prefetch_L2(cmd_buffer,
3667 cmd_buffer->state.pipeline, false);
3668 }
3669 } else {
3670 /* If we don't wait for idle, start prefetches first, then set
3671 * states, and draw at the end.
3672 */
3673 si_emit_cache_flush(cmd_buffer);
3674
3675 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3676 /* Only prefetch the vertex shader and VBO descriptors
3677 * in order to start the draw as soon as possible.
3678 */
3679 radv_emit_prefetch_L2(cmd_buffer,
3680 cmd_buffer->state.pipeline, true);
3681 }
3682
3683 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3684
3685 radv_emit_all_graphics_states(cmd_buffer, info);
3686 radv_emit_draw_packets(cmd_buffer, info);
3687
3688 /* Prefetch the remaining shaders after the draw has been
3689 * started.
3690 */
3691 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3692 radv_emit_prefetch_L2(cmd_buffer,
3693 cmd_buffer->state.pipeline, false);
3694 }
3695 }
3696
3697 /* Workaround for a VGT hang when streamout is enabled.
3698 * It must be done after drawing.
3699 */
3700 if (cmd_buffer->state.streamout.streamout_enabled &&
3701 (rad_info->family == CHIP_HAWAII ||
3702 rad_info->family == CHIP_TONGA ||
3703 rad_info->family == CHIP_FIJI)) {
3704 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3705 }
3706
3707 assert(cmd_buffer->cs->cdw <= cdw_max);
3708 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3709 }
3710
3711 void radv_CmdDraw(
3712 VkCommandBuffer commandBuffer,
3713 uint32_t vertexCount,
3714 uint32_t instanceCount,
3715 uint32_t firstVertex,
3716 uint32_t firstInstance)
3717 {
3718 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3719 struct radv_draw_info info = {};
3720
3721 info.count = vertexCount;
3722 info.instance_count = instanceCount;
3723 info.first_instance = firstInstance;
3724 info.vertex_offset = firstVertex;
3725
3726 radv_draw(cmd_buffer, &info);
3727 }
3728
3729 void radv_CmdDrawIndexed(
3730 VkCommandBuffer commandBuffer,
3731 uint32_t indexCount,
3732 uint32_t instanceCount,
3733 uint32_t firstIndex,
3734 int32_t vertexOffset,
3735 uint32_t firstInstance)
3736 {
3737 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3738 struct radv_draw_info info = {};
3739
3740 info.indexed = true;
3741 info.count = indexCount;
3742 info.instance_count = instanceCount;
3743 info.first_index = firstIndex;
3744 info.vertex_offset = vertexOffset;
3745 info.first_instance = firstInstance;
3746
3747 radv_draw(cmd_buffer, &info);
3748 }
3749
3750 void radv_CmdDrawIndirect(
3751 VkCommandBuffer commandBuffer,
3752 VkBuffer _buffer,
3753 VkDeviceSize offset,
3754 uint32_t drawCount,
3755 uint32_t stride)
3756 {
3757 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3758 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3759 struct radv_draw_info info = {};
3760
3761 info.count = drawCount;
3762 info.indirect = buffer;
3763 info.indirect_offset = offset;
3764 info.stride = stride;
3765
3766 radv_draw(cmd_buffer, &info);
3767 }
3768
3769 void radv_CmdDrawIndexedIndirect(
3770 VkCommandBuffer commandBuffer,
3771 VkBuffer _buffer,
3772 VkDeviceSize offset,
3773 uint32_t drawCount,
3774 uint32_t stride)
3775 {
3776 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3777 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3778 struct radv_draw_info info = {};
3779
3780 info.indexed = true;
3781 info.count = drawCount;
3782 info.indirect = buffer;
3783 info.indirect_offset = offset;
3784 info.stride = stride;
3785
3786 radv_draw(cmd_buffer, &info);
3787 }
3788
3789 void radv_CmdDrawIndirectCountAMD(
3790 VkCommandBuffer commandBuffer,
3791 VkBuffer _buffer,
3792 VkDeviceSize offset,
3793 VkBuffer _countBuffer,
3794 VkDeviceSize countBufferOffset,
3795 uint32_t maxDrawCount,
3796 uint32_t stride)
3797 {
3798 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3799 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3800 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3801 struct radv_draw_info info = {};
3802
3803 info.count = maxDrawCount;
3804 info.indirect = buffer;
3805 info.indirect_offset = offset;
3806 info.count_buffer = count_buffer;
3807 info.count_buffer_offset = countBufferOffset;
3808 info.stride = stride;
3809
3810 radv_draw(cmd_buffer, &info);
3811 }
3812
3813 void radv_CmdDrawIndexedIndirectCountAMD(
3814 VkCommandBuffer commandBuffer,
3815 VkBuffer _buffer,
3816 VkDeviceSize offset,
3817 VkBuffer _countBuffer,
3818 VkDeviceSize countBufferOffset,
3819 uint32_t maxDrawCount,
3820 uint32_t stride)
3821 {
3822 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3823 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3824 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3825 struct radv_draw_info info = {};
3826
3827 info.indexed = true;
3828 info.count = maxDrawCount;
3829 info.indirect = buffer;
3830 info.indirect_offset = offset;
3831 info.count_buffer = count_buffer;
3832 info.count_buffer_offset = countBufferOffset;
3833 info.stride = stride;
3834
3835 radv_draw(cmd_buffer, &info);
3836 }
3837
3838 void radv_CmdDrawIndirectCountKHR(
3839 VkCommandBuffer commandBuffer,
3840 VkBuffer _buffer,
3841 VkDeviceSize offset,
3842 VkBuffer _countBuffer,
3843 VkDeviceSize countBufferOffset,
3844 uint32_t maxDrawCount,
3845 uint32_t stride)
3846 {
3847 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3848 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3849 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3850 struct radv_draw_info info = {};
3851
3852 info.count = maxDrawCount;
3853 info.indirect = buffer;
3854 info.indirect_offset = offset;
3855 info.count_buffer = count_buffer;
3856 info.count_buffer_offset = countBufferOffset;
3857 info.stride = stride;
3858
3859 radv_draw(cmd_buffer, &info);
3860 }
3861
3862 void radv_CmdDrawIndexedIndirectCountKHR(
3863 VkCommandBuffer commandBuffer,
3864 VkBuffer _buffer,
3865 VkDeviceSize offset,
3866 VkBuffer _countBuffer,
3867 VkDeviceSize countBufferOffset,
3868 uint32_t maxDrawCount,
3869 uint32_t stride)
3870 {
3871 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3872 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3873 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3874 struct radv_draw_info info = {};
3875
3876 info.indexed = true;
3877 info.count = maxDrawCount;
3878 info.indirect = buffer;
3879 info.indirect_offset = offset;
3880 info.count_buffer = count_buffer;
3881 info.count_buffer_offset = countBufferOffset;
3882 info.stride = stride;
3883
3884 radv_draw(cmd_buffer, &info);
3885 }
3886
3887 struct radv_dispatch_info {
3888 /**
3889 * Determine the layout of the grid (in block units) to be used.
3890 */
3891 uint32_t blocks[3];
3892
3893 /**
3894 * A starting offset for the grid. If unaligned is set, the offset
3895 * must still be aligned.
3896 */
3897 uint32_t offsets[3];
3898 /**
3899 * Whether it's an unaligned compute dispatch.
3900 */
3901 bool unaligned;
3902
3903 /**
3904 * Indirect compute parameters resource.
3905 */
3906 struct radv_buffer *indirect;
3907 uint64_t indirect_offset;
3908 };
3909
3910 static void
3911 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3912 const struct radv_dispatch_info *info)
3913 {
3914 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3915 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3916 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3917 struct radeon_winsys *ws = cmd_buffer->device->ws;
3918 bool predicating = cmd_buffer->state.predicating;
3919 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3920 struct radv_userdata_info *loc;
3921
3922 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3923 AC_UD_CS_GRID_SIZE);
3924
3925 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3926
3927 if (info->indirect) {
3928 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3929
3930 va += info->indirect->offset + info->indirect_offset;
3931
3932 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3933
3934 if (loc->sgpr_idx != -1) {
3935 for (unsigned i = 0; i < 3; ++i) {
3936 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3937 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3938 COPY_DATA_DST_SEL(COPY_DATA_REG));
3939 radeon_emit(cs, (va + 4 * i));
3940 radeon_emit(cs, (va + 4 * i) >> 32);
3941 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3942 + loc->sgpr_idx * 4) >> 2) + i);
3943 radeon_emit(cs, 0);
3944 }
3945 }
3946
3947 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3948 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
3949 PKT3_SHADER_TYPE_S(1));
3950 radeon_emit(cs, va);
3951 radeon_emit(cs, va >> 32);
3952 radeon_emit(cs, dispatch_initiator);
3953 } else {
3954 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3955 PKT3_SHADER_TYPE_S(1));
3956 radeon_emit(cs, 1);
3957 radeon_emit(cs, va);
3958 radeon_emit(cs, va >> 32);
3959
3960 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
3961 PKT3_SHADER_TYPE_S(1));
3962 radeon_emit(cs, 0);
3963 radeon_emit(cs, dispatch_initiator);
3964 }
3965 } else {
3966 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3967 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3968
3969 if (info->unaligned) {
3970 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3971 unsigned remainder[3];
3972
3973 /* If aligned, these should be an entire block size,
3974 * not 0.
3975 */
3976 remainder[0] = blocks[0] + cs_block_size[0] -
3977 align_u32_npot(blocks[0], cs_block_size[0]);
3978 remainder[1] = blocks[1] + cs_block_size[1] -
3979 align_u32_npot(blocks[1], cs_block_size[1]);
3980 remainder[2] = blocks[2] + cs_block_size[2] -
3981 align_u32_npot(blocks[2], cs_block_size[2]);
3982
3983 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3984 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3985 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3986
3987 for(unsigned i = 0; i < 3; ++i) {
3988 assert(offsets[i] % cs_block_size[i] == 0);
3989 offsets[i] /= cs_block_size[i];
3990 }
3991
3992 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3993 radeon_emit(cs,
3994 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3995 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3996 radeon_emit(cs,
3997 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3998 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3999 radeon_emit(cs,
4000 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4001 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4002
4003 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4004 }
4005
4006 if (loc->sgpr_idx != -1) {
4007 assert(!loc->indirect);
4008 assert(loc->num_sgprs == 3);
4009
4010 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4011 loc->sgpr_idx * 4, 3);
4012 radeon_emit(cs, blocks[0]);
4013 radeon_emit(cs, blocks[1]);
4014 radeon_emit(cs, blocks[2]);
4015 }
4016
4017 if (offsets[0] || offsets[1] || offsets[2]) {
4018 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4019 radeon_emit(cs, offsets[0]);
4020 radeon_emit(cs, offsets[1]);
4021 radeon_emit(cs, offsets[2]);
4022
4023 /* The blocks in the packet are not counts but end values. */
4024 for (unsigned i = 0; i < 3; ++i)
4025 blocks[i] += offsets[i];
4026 } else {
4027 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4028 }
4029
4030 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4031 PKT3_SHADER_TYPE_S(1));
4032 radeon_emit(cs, blocks[0]);
4033 radeon_emit(cs, blocks[1]);
4034 radeon_emit(cs, blocks[2]);
4035 radeon_emit(cs, dispatch_initiator);
4036 }
4037
4038 assert(cmd_buffer->cs->cdw <= cdw_max);
4039 }
4040
4041 static void
4042 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4043 {
4044 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4045 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4046 }
4047
4048 static void
4049 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4050 const struct radv_dispatch_info *info)
4051 {
4052 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4053 bool has_prefetch =
4054 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4055 bool pipeline_is_dirty = pipeline &&
4056 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4057
4058 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4059 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4060 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4061 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4062 /* If we have to wait for idle, set all states first, so that
4063 * all SET packets are processed in parallel with previous draw
4064 * calls. Then upload descriptors, set shader pointers, and
4065 * dispatch, and prefetch at the end. This ensures that the
4066 * time the CUs are idle is very short. (there are only SET_SH
4067 * packets between the wait and the draw)
4068 */
4069 radv_emit_compute_pipeline(cmd_buffer);
4070 si_emit_cache_flush(cmd_buffer);
4071 /* <-- CUs are idle here --> */
4072
4073 radv_upload_compute_shader_descriptors(cmd_buffer);
4074
4075 radv_emit_dispatch_packets(cmd_buffer, info);
4076 /* <-- CUs are busy here --> */
4077
4078 /* Start prefetches after the dispatch has been started. Both
4079 * will run in parallel, but starting the dispatch first is
4080 * more important.
4081 */
4082 if (has_prefetch && pipeline_is_dirty) {
4083 radv_emit_shader_prefetch(cmd_buffer,
4084 pipeline->shaders[MESA_SHADER_COMPUTE]);
4085 }
4086 } else {
4087 /* If we don't wait for idle, start prefetches first, then set
4088 * states, and dispatch at the end.
4089 */
4090 si_emit_cache_flush(cmd_buffer);
4091
4092 if (has_prefetch && pipeline_is_dirty) {
4093 radv_emit_shader_prefetch(cmd_buffer,
4094 pipeline->shaders[MESA_SHADER_COMPUTE]);
4095 }
4096
4097 radv_upload_compute_shader_descriptors(cmd_buffer);
4098
4099 radv_emit_compute_pipeline(cmd_buffer);
4100 radv_emit_dispatch_packets(cmd_buffer, info);
4101 }
4102
4103 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4104 }
4105
4106 void radv_CmdDispatchBase(
4107 VkCommandBuffer commandBuffer,
4108 uint32_t base_x,
4109 uint32_t base_y,
4110 uint32_t base_z,
4111 uint32_t x,
4112 uint32_t y,
4113 uint32_t z)
4114 {
4115 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4116 struct radv_dispatch_info info = {};
4117
4118 info.blocks[0] = x;
4119 info.blocks[1] = y;
4120 info.blocks[2] = z;
4121
4122 info.offsets[0] = base_x;
4123 info.offsets[1] = base_y;
4124 info.offsets[2] = base_z;
4125 radv_dispatch(cmd_buffer, &info);
4126 }
4127
4128 void radv_CmdDispatch(
4129 VkCommandBuffer commandBuffer,
4130 uint32_t x,
4131 uint32_t y,
4132 uint32_t z)
4133 {
4134 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4135 }
4136
4137 void radv_CmdDispatchIndirect(
4138 VkCommandBuffer commandBuffer,
4139 VkBuffer _buffer,
4140 VkDeviceSize offset)
4141 {
4142 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4143 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4144 struct radv_dispatch_info info = {};
4145
4146 info.indirect = buffer;
4147 info.indirect_offset = offset;
4148
4149 radv_dispatch(cmd_buffer, &info);
4150 }
4151
4152 void radv_unaligned_dispatch(
4153 struct radv_cmd_buffer *cmd_buffer,
4154 uint32_t x,
4155 uint32_t y,
4156 uint32_t z)
4157 {
4158 struct radv_dispatch_info info = {};
4159
4160 info.blocks[0] = x;
4161 info.blocks[1] = y;
4162 info.blocks[2] = z;
4163 info.unaligned = 1;
4164
4165 radv_dispatch(cmd_buffer, &info);
4166 }
4167
4168 void radv_CmdEndRenderPass(
4169 VkCommandBuffer commandBuffer)
4170 {
4171 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4172
4173 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4174
4175 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4176
4177 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4178 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4179 radv_handle_subpass_image_transition(cmd_buffer,
4180 (struct radv_subpass_attachment){i, layout});
4181 }
4182
4183 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4184
4185 cmd_buffer->state.pass = NULL;
4186 cmd_buffer->state.subpass = NULL;
4187 cmd_buffer->state.attachments = NULL;
4188 cmd_buffer->state.framebuffer = NULL;
4189 }
4190
4191 void radv_CmdEndRenderPass2KHR(
4192 VkCommandBuffer commandBuffer,
4193 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4194 {
4195 radv_CmdEndRenderPass(commandBuffer);
4196 }
4197
4198 /*
4199 * For HTILE we have the following interesting clear words:
4200 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4201 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4202 * 0xfffffff0: Clear depth to 1.0
4203 * 0x00000000: Clear depth to 0.0
4204 */
4205 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4206 struct radv_image *image,
4207 const VkImageSubresourceRange *range,
4208 uint32_t clear_word)
4209 {
4210 assert(range->baseMipLevel == 0);
4211 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4212 unsigned layer_count = radv_get_layerCount(image, range);
4213 uint64_t size = image->surface.htile_slice_size * layer_count;
4214 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4215 uint64_t offset = image->offset + image->htile_offset +
4216 image->surface.htile_slice_size * range->baseArrayLayer;
4217 struct radv_cmd_state *state = &cmd_buffer->state;
4218 VkClearDepthStencilValue value = {};
4219
4220 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4221 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4222
4223 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4224 size, clear_word);
4225
4226 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4227
4228 if (vk_format_is_stencil(image->vk_format))
4229 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4230
4231 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4232 }
4233
4234 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4235 struct radv_image *image,
4236 VkImageLayout src_layout,
4237 VkImageLayout dst_layout,
4238 unsigned src_queue_mask,
4239 unsigned dst_queue_mask,
4240 const VkImageSubresourceRange *range)
4241 {
4242 if (!radv_image_has_htile(image))
4243 return;
4244
4245 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4246 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4247 /* TODO: merge with the clear if applicable */
4248 radv_initialize_htile(cmd_buffer, image, range, 0);
4249 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4250 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4251 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4252 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4253 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4254 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4255 VkImageSubresourceRange local_range = *range;
4256 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4257 local_range.baseMipLevel = 0;
4258 local_range.levelCount = 1;
4259
4260 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4261 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4262
4263 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4264
4265 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4266 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4267 }
4268 }
4269
4270 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4271 struct radv_image *image, uint32_t value)
4272 {
4273 struct radv_cmd_state *state = &cmd_buffer->state;
4274
4275 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4276 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4277
4278 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4279
4280 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4281 }
4282
4283 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4284 struct radv_image *image, uint32_t value)
4285 {
4286 struct radv_cmd_state *state = &cmd_buffer->state;
4287
4288 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4289 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4290
4291 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4292
4293 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4294 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4295 }
4296
4297 /**
4298 * Initialize DCC/FMASK/CMASK metadata for a color image.
4299 */
4300 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4301 struct radv_image *image,
4302 VkImageLayout src_layout,
4303 VkImageLayout dst_layout,
4304 unsigned src_queue_mask,
4305 unsigned dst_queue_mask)
4306 {
4307 if (radv_image_has_cmask(image)) {
4308 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4309
4310 /* TODO: clarify this. */
4311 if (radv_image_has_fmask(image)) {
4312 value = 0xccccccccu;
4313 }
4314
4315 radv_initialise_cmask(cmd_buffer, image, value);
4316 }
4317
4318 if (radv_image_has_dcc(image)) {
4319 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4320 bool need_decompress_pass = false;
4321
4322 if (radv_layout_dcc_compressed(image, dst_layout,
4323 dst_queue_mask)) {
4324 value = 0x20202020u;
4325 need_decompress_pass = true;
4326 }
4327
4328 radv_initialize_dcc(cmd_buffer, image, value);
4329
4330 radv_update_fce_metadata(cmd_buffer, image,
4331 need_decompress_pass);
4332 }
4333
4334 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4335 uint32_t color_values[2] = {};
4336 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4337 }
4338 }
4339
4340 /**
4341 * Handle color image transitions for DCC/FMASK/CMASK.
4342 */
4343 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4344 struct radv_image *image,
4345 VkImageLayout src_layout,
4346 VkImageLayout dst_layout,
4347 unsigned src_queue_mask,
4348 unsigned dst_queue_mask,
4349 const VkImageSubresourceRange *range)
4350 {
4351 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4352 radv_init_color_image_metadata(cmd_buffer, image,
4353 src_layout, dst_layout,
4354 src_queue_mask, dst_queue_mask);
4355 return;
4356 }
4357
4358 if (radv_image_has_dcc(image)) {
4359 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4360 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4361 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4362 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4363 radv_decompress_dcc(cmd_buffer, image, range);
4364 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4365 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4366 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4367 }
4368 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4369 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4370 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4371 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4372 }
4373 }
4374 }
4375
4376 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4377 struct radv_image *image,
4378 VkImageLayout src_layout,
4379 VkImageLayout dst_layout,
4380 uint32_t src_family,
4381 uint32_t dst_family,
4382 const VkImageSubresourceRange *range)
4383 {
4384 if (image->exclusive && src_family != dst_family) {
4385 /* This is an acquire or a release operation and there will be
4386 * a corresponding release/acquire. Do the transition in the
4387 * most flexible queue. */
4388
4389 assert(src_family == cmd_buffer->queue_family_index ||
4390 dst_family == cmd_buffer->queue_family_index);
4391
4392 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4393 return;
4394
4395 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4396 (src_family == RADV_QUEUE_GENERAL ||
4397 dst_family == RADV_QUEUE_GENERAL))
4398 return;
4399 }
4400
4401 unsigned src_queue_mask =
4402 radv_image_queue_family_mask(image, src_family,
4403 cmd_buffer->queue_family_index);
4404 unsigned dst_queue_mask =
4405 radv_image_queue_family_mask(image, dst_family,
4406 cmd_buffer->queue_family_index);
4407
4408 if (vk_format_is_depth(image->vk_format)) {
4409 radv_handle_depth_image_transition(cmd_buffer, image,
4410 src_layout, dst_layout,
4411 src_queue_mask, dst_queue_mask,
4412 range);
4413 } else {
4414 radv_handle_color_image_transition(cmd_buffer, image,
4415 src_layout, dst_layout,
4416 src_queue_mask, dst_queue_mask,
4417 range);
4418 }
4419 }
4420
4421 struct radv_barrier_info {
4422 uint32_t eventCount;
4423 const VkEvent *pEvents;
4424 VkPipelineStageFlags srcStageMask;
4425 };
4426
4427 static void
4428 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4429 uint32_t memoryBarrierCount,
4430 const VkMemoryBarrier *pMemoryBarriers,
4431 uint32_t bufferMemoryBarrierCount,
4432 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4433 uint32_t imageMemoryBarrierCount,
4434 const VkImageMemoryBarrier *pImageMemoryBarriers,
4435 const struct radv_barrier_info *info)
4436 {
4437 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4438 enum radv_cmd_flush_bits src_flush_bits = 0;
4439 enum radv_cmd_flush_bits dst_flush_bits = 0;
4440
4441 for (unsigned i = 0; i < info->eventCount; ++i) {
4442 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4443 uint64_t va = radv_buffer_get_va(event->bo);
4444
4445 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4446
4447 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4448
4449 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4450 assert(cmd_buffer->cs->cdw <= cdw_max);
4451 }
4452
4453 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4454 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4455 NULL);
4456 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4457 NULL);
4458 }
4459
4460 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4461 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4462 NULL);
4463 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4464 NULL);
4465 }
4466
4467 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4468 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4469
4470 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4471 image);
4472 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4473 image);
4474 }
4475
4476 radv_stage_flush(cmd_buffer, info->srcStageMask);
4477 cmd_buffer->state.flush_bits |= src_flush_bits;
4478
4479 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4480 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4481 radv_handle_image_transition(cmd_buffer, image,
4482 pImageMemoryBarriers[i].oldLayout,
4483 pImageMemoryBarriers[i].newLayout,
4484 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4485 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4486 &pImageMemoryBarriers[i].subresourceRange);
4487 }
4488
4489 /* Make sure CP DMA is idle because the driver might have performed a
4490 * DMA operation for copying or filling buffers/images.
4491 */
4492 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4493 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4494 si_cp_dma_wait_for_idle(cmd_buffer);
4495
4496 cmd_buffer->state.flush_bits |= dst_flush_bits;
4497 }
4498
4499 void radv_CmdPipelineBarrier(
4500 VkCommandBuffer commandBuffer,
4501 VkPipelineStageFlags srcStageMask,
4502 VkPipelineStageFlags destStageMask,
4503 VkBool32 byRegion,
4504 uint32_t memoryBarrierCount,
4505 const VkMemoryBarrier* pMemoryBarriers,
4506 uint32_t bufferMemoryBarrierCount,
4507 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4508 uint32_t imageMemoryBarrierCount,
4509 const VkImageMemoryBarrier* pImageMemoryBarriers)
4510 {
4511 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4512 struct radv_barrier_info info;
4513
4514 info.eventCount = 0;
4515 info.pEvents = NULL;
4516 info.srcStageMask = srcStageMask;
4517
4518 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4519 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4520 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4521 }
4522
4523
4524 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4525 struct radv_event *event,
4526 VkPipelineStageFlags stageMask,
4527 unsigned value)
4528 {
4529 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4530 uint64_t va = radv_buffer_get_va(event->bo);
4531
4532 si_emit_cache_flush(cmd_buffer);
4533
4534 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4535
4536 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4537
4538 /* Flags that only require a top-of-pipe event. */
4539 VkPipelineStageFlags top_of_pipe_flags =
4540 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4541
4542 /* Flags that only require a post-index-fetch event. */
4543 VkPipelineStageFlags post_index_fetch_flags =
4544 top_of_pipe_flags |
4545 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4546 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4547
4548 /* Make sure CP DMA is idle because the driver might have performed a
4549 * DMA operation for copying or filling buffers/images.
4550 */
4551 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4552 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4553 si_cp_dma_wait_for_idle(cmd_buffer);
4554
4555 /* TODO: Emit EOS events for syncing PS/CS stages. */
4556
4557 if (!(stageMask & ~top_of_pipe_flags)) {
4558 /* Just need to sync the PFP engine. */
4559 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4560 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4561 S_370_WR_CONFIRM(1) |
4562 S_370_ENGINE_SEL(V_370_PFP));
4563 radeon_emit(cs, va);
4564 radeon_emit(cs, va >> 32);
4565 radeon_emit(cs, value);
4566 } else if (!(stageMask & ~post_index_fetch_flags)) {
4567 /* Sync ME because PFP reads index and indirect buffers. */
4568 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4569 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4570 S_370_WR_CONFIRM(1) |
4571 S_370_ENGINE_SEL(V_370_ME));
4572 radeon_emit(cs, va);
4573 radeon_emit(cs, va >> 32);
4574 radeon_emit(cs, value);
4575 } else {
4576 /* Otherwise, sync all prior GPU work using an EOP event. */
4577 si_cs_emit_write_event_eop(cs,
4578 cmd_buffer->device->physical_device->rad_info.chip_class,
4579 radv_cmd_buffer_uses_mec(cmd_buffer),
4580 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4581 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4582 cmd_buffer->gfx9_eop_bug_va);
4583 }
4584
4585 assert(cmd_buffer->cs->cdw <= cdw_max);
4586 }
4587
4588 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4589 VkEvent _event,
4590 VkPipelineStageFlags stageMask)
4591 {
4592 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4593 RADV_FROM_HANDLE(radv_event, event, _event);
4594
4595 write_event(cmd_buffer, event, stageMask, 1);
4596 }
4597
4598 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4599 VkEvent _event,
4600 VkPipelineStageFlags stageMask)
4601 {
4602 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4603 RADV_FROM_HANDLE(radv_event, event, _event);
4604
4605 write_event(cmd_buffer, event, stageMask, 0);
4606 }
4607
4608 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4609 uint32_t eventCount,
4610 const VkEvent* pEvents,
4611 VkPipelineStageFlags srcStageMask,
4612 VkPipelineStageFlags dstStageMask,
4613 uint32_t memoryBarrierCount,
4614 const VkMemoryBarrier* pMemoryBarriers,
4615 uint32_t bufferMemoryBarrierCount,
4616 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4617 uint32_t imageMemoryBarrierCount,
4618 const VkImageMemoryBarrier* pImageMemoryBarriers)
4619 {
4620 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4621 struct radv_barrier_info info;
4622
4623 info.eventCount = eventCount;
4624 info.pEvents = pEvents;
4625 info.srcStageMask = 0;
4626
4627 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4628 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4629 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4630 }
4631
4632
4633 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4634 uint32_t deviceMask)
4635 {
4636 /* No-op */
4637 }
4638
4639 /* VK_EXT_conditional_rendering */
4640 void radv_CmdBeginConditionalRenderingEXT(
4641 VkCommandBuffer commandBuffer,
4642 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4643 {
4644 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4645 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4646 bool draw_visible = true;
4647 uint64_t va;
4648
4649 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4650
4651 /* By default, if the 32-bit value at offset in buffer memory is zero,
4652 * then the rendering commands are discarded, otherwise they are
4653 * executed as normal. If the inverted flag is set, all commands are
4654 * discarded if the value is non zero.
4655 */
4656 if (pConditionalRenderingBegin->flags &
4657 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4658 draw_visible = false;
4659 }
4660
4661 /* Enable predication for this command buffer. */
4662 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4663 cmd_buffer->state.predicating = true;
4664
4665 /* Store conditional rendering user info. */
4666 cmd_buffer->state.predication_type = draw_visible;
4667 cmd_buffer->state.predication_va = va;
4668 }
4669
4670 void radv_CmdEndConditionalRenderingEXT(
4671 VkCommandBuffer commandBuffer)
4672 {
4673 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4674
4675 /* Disable predication for this command buffer. */
4676 si_emit_set_predication_state(cmd_buffer, false, 0);
4677 cmd_buffer->state.predicating = false;
4678
4679 /* Reset conditional rendering user info. */
4680 cmd_buffer->state.predication_type = -1;
4681 cmd_buffer->state.predication_va = 0;
4682 }
4683
4684 /* VK_EXT_transform_feedback */
4685 void radv_CmdBindTransformFeedbackBuffersEXT(
4686 VkCommandBuffer commandBuffer,
4687 uint32_t firstBinding,
4688 uint32_t bindingCount,
4689 const VkBuffer* pBuffers,
4690 const VkDeviceSize* pOffsets,
4691 const VkDeviceSize* pSizes)
4692 {
4693 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4694 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4695 uint8_t enabled_mask = 0;
4696
4697 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4698 for (uint32_t i = 0; i < bindingCount; i++) {
4699 uint32_t idx = firstBinding + i;
4700
4701 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4702 sb[idx].offset = pOffsets[i];
4703 sb[idx].size = pSizes[i];
4704
4705 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4706 sb[idx].buffer->bo);
4707
4708 enabled_mask |= 1 << idx;
4709 }
4710
4711 cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4712
4713 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4714 }
4715
4716 static void
4717 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4718 {
4719 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4720 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4721
4722 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
4723 radeon_emit(cs,
4724 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
4725 S_028B94_RAST_STREAM(0) |
4726 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
4727 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
4728 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
4729 radeon_emit(cs, so->hw_enabled_mask &
4730 so->enabled_stream_buffers_mask);
4731 }
4732
4733 static void
4734 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
4735 {
4736 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4737 bool old_streamout_enabled = so->streamout_enabled;
4738 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
4739
4740 so->streamout_enabled = enable;
4741
4742 so->hw_enabled_mask = so->enabled_mask |
4743 (so->enabled_mask << 4) |
4744 (so->enabled_mask << 8) |
4745 (so->enabled_mask << 12);
4746
4747 if ((old_streamout_enabled != so->streamout_enabled) ||
4748 (old_hw_enabled_mask != so->hw_enabled_mask))
4749 radv_emit_streamout_enable(cmd_buffer);
4750 }
4751
4752 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
4753 {
4754 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4755 unsigned reg_strmout_cntl;
4756
4757 /* The register is at different places on different ASICs. */
4758 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
4759 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
4760 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
4761 } else {
4762 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
4763 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
4764 }
4765
4766 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4767 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
4768
4769 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
4770 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
4771 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
4772 radeon_emit(cs, 0);
4773 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4774 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4775 radeon_emit(cs, 4); /* poll interval */
4776 }
4777
4778 void radv_CmdBeginTransformFeedbackEXT(
4779 VkCommandBuffer commandBuffer,
4780 uint32_t firstCounterBuffer,
4781 uint32_t counterBufferCount,
4782 const VkBuffer* pCounterBuffers,
4783 const VkDeviceSize* pCounterBufferOffsets)
4784 {
4785 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4786 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4787 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4788 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4789 uint32_t i;
4790
4791 radv_flush_vgt_streamout(cmd_buffer);
4792
4793 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4794 for_each_bit(i, so->enabled_mask) {
4795 int32_t counter_buffer_idx = i - firstCounterBuffer;
4796 if (counter_buffer_idx >= 0 && counter_buffer_idx > counterBufferCount)
4797 counter_buffer_idx = -1;
4798
4799 /* SI binds streamout buffers as shader resources.
4800 * VGT only counts primitives and tells the shader through
4801 * SGPRs what to do.
4802 */
4803 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
4804 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
4805 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
4806
4807 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
4808 /* The array of counter buffers is optional. */
4809 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
4810 uint64_t va = radv_buffer_get_va(buffer->bo);
4811
4812 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
4813
4814 /* Append */
4815 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4816 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4817 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4818 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
4819 radeon_emit(cs, 0); /* unused */
4820 radeon_emit(cs, 0); /* unused */
4821 radeon_emit(cs, va); /* src address lo */
4822 radeon_emit(cs, va >> 32); /* src address hi */
4823
4824 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4825 } else {
4826 /* Start from the beginning. */
4827 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4828 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4829 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4830 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
4831 radeon_emit(cs, 0); /* unused */
4832 radeon_emit(cs, 0); /* unused */
4833 radeon_emit(cs, 0); /* unused */
4834 radeon_emit(cs, 0); /* unused */
4835 }
4836 }
4837
4838 radv_set_streamout_enable(cmd_buffer, true);
4839 }
4840
4841 void radv_CmdEndTransformFeedbackEXT(
4842 VkCommandBuffer commandBuffer,
4843 uint32_t firstCounterBuffer,
4844 uint32_t counterBufferCount,
4845 const VkBuffer* pCounterBuffers,
4846 const VkDeviceSize* pCounterBufferOffsets)
4847 {
4848 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4849 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4850 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4851 uint32_t i;
4852
4853 radv_flush_vgt_streamout(cmd_buffer);
4854
4855 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4856 for_each_bit(i, so->enabled_mask) {
4857 int32_t counter_buffer_idx = i - firstCounterBuffer;
4858 if (counter_buffer_idx >= 0 && counter_buffer_idx > counterBufferCount)
4859 counter_buffer_idx = -1;
4860
4861 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
4862 /* The array of counters buffer is optional. */
4863 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
4864 uint64_t va = radv_buffer_get_va(buffer->bo);
4865
4866 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
4867
4868 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4869 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4870 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4871 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
4872 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
4873 radeon_emit(cs, va); /* dst address lo */
4874 radeon_emit(cs, va >> 32); /* dst address hi */
4875 radeon_emit(cs, 0); /* unused */
4876 radeon_emit(cs, 0); /* unused */
4877
4878 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4879 }
4880
4881 /* Deactivate transform feedback by zeroing the buffer size.
4882 * The counters (primitives generated, primitives emitted) may
4883 * be enabled even if there is not buffer bound. This ensures
4884 * that the primitives-emitted query won't increment.
4885 */
4886 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
4887 }
4888
4889 radv_set_streamout_enable(cmd_buffer, false);
4890 }
4891
4892 void radv_CmdDrawIndirectByteCountEXT(
4893 VkCommandBuffer commandBuffer,
4894 uint32_t instanceCount,
4895 uint32_t firstInstance,
4896 VkBuffer _counterBuffer,
4897 VkDeviceSize counterBufferOffset,
4898 uint32_t counterOffset,
4899 uint32_t vertexStride)
4900 {
4901 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4902 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
4903 struct radv_draw_info info = {};
4904
4905 info.instance_count = instanceCount;
4906 info.first_instance = firstInstance;
4907 info.strmout_buffer = counterBuffer;
4908 info.strmout_buffer_offset = counterBufferOffset;
4909 info.stride = vertexStride;
4910
4911 radv_draw(cmd_buffer, &info);
4912 }