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radv: fix flushing indirect descriptors
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safely call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
314 cmd_buffer->descriptors[i].dirty = 0;
315 cmd_buffer->descriptors[i].valid = 0;
316 cmd_buffer->descriptors[i].push_dirty = false;
317 }
318
319 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
320 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
321 unsigned eop_bug_offset;
322 void *fence_ptr;
323
324 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
325 &cmd_buffer->gfx9_fence_offset,
326 &fence_ptr);
327 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
328
329 /* Allocate a buffer for the EOP bug on GFX9. */
330 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
331 &eop_bug_offset, &fence_ptr);
332 cmd_buffer->gfx9_eop_bug_va =
333 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
334 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
335 }
336
337 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
338
339 return cmd_buffer->record_result;
340 }
341
342 static bool
343 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
344 uint64_t min_needed)
345 {
346 uint64_t new_size;
347 struct radeon_winsys_bo *bo;
348 struct radv_cmd_buffer_upload *upload;
349 struct radv_device *device = cmd_buffer->device;
350
351 new_size = MAX2(min_needed, 16 * 1024);
352 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
353
354 bo = device->ws->buffer_create(device->ws,
355 new_size, 4096,
356 RADEON_DOMAIN_GTT,
357 RADEON_FLAG_CPU_ACCESS|
358 RADEON_FLAG_NO_INTERPROCESS_SHARING |
359 RADEON_FLAG_32BIT);
360
361 if (!bo) {
362 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
363 return false;
364 }
365
366 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
367 if (cmd_buffer->upload.upload_bo) {
368 upload = malloc(sizeof(*upload));
369
370 if (!upload) {
371 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
372 device->ws->buffer_destroy(bo);
373 return false;
374 }
375
376 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
377 list_add(&upload->list, &cmd_buffer->upload.list);
378 }
379
380 cmd_buffer->upload.upload_bo = bo;
381 cmd_buffer->upload.size = new_size;
382 cmd_buffer->upload.offset = 0;
383 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
384
385 if (!cmd_buffer->upload.map) {
386 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
387 return false;
388 }
389
390 return true;
391 }
392
393 bool
394 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
395 unsigned size,
396 unsigned alignment,
397 unsigned *out_offset,
398 void **ptr)
399 {
400 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
401 if (offset + size > cmd_buffer->upload.size) {
402 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
403 return false;
404 offset = 0;
405 }
406
407 *out_offset = offset;
408 *ptr = cmd_buffer->upload.map + offset;
409
410 cmd_buffer->upload.offset = offset + size;
411 return true;
412 }
413
414 bool
415 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
416 unsigned size, unsigned alignment,
417 const void *data, unsigned *out_offset)
418 {
419 uint8_t *ptr;
420
421 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
422 out_offset, (void **)&ptr))
423 return false;
424
425 if (ptr)
426 memcpy(ptr, data, size);
427
428 return true;
429 }
430
431 static void
432 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
433 unsigned count, const uint32_t *data)
434 {
435 struct radeon_cmdbuf *cs = cmd_buffer->cs;
436
437 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
438
439 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
440 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
441 S_370_WR_CONFIRM(1) |
442 S_370_ENGINE_SEL(V_370_ME));
443 radeon_emit(cs, va);
444 radeon_emit(cs, va >> 32);
445 radeon_emit_array(cs, data, count);
446 }
447
448 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
449 {
450 struct radv_device *device = cmd_buffer->device;
451 struct radeon_cmdbuf *cs = cmd_buffer->cs;
452 uint64_t va;
453
454 va = radv_buffer_get_va(device->trace_bo);
455 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
456 va += 4;
457
458 ++cmd_buffer->state.trace_id;
459 radv_emit_write_data_packet(cmd_buffer, va, 1,
460 &cmd_buffer->state.trace_id);
461
462 radeon_check_space(cmd_buffer->device->ws, cs, 2);
463
464 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
465 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
466 }
467
468 static void
469 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
470 enum radv_cmd_flush_bits flags)
471 {
472 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
473 uint32_t *ptr = NULL;
474 uint64_t va = 0;
475
476 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
477 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
478
479 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
480 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
481 cmd_buffer->gfx9_fence_offset;
482 ptr = &cmd_buffer->gfx9_fence_idx;
483 }
484
485 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
486
487 /* Force wait for graphics or compute engines to be idle. */
488 si_cs_emit_cache_flush(cmd_buffer->cs,
489 cmd_buffer->device->physical_device->rad_info.chip_class,
490 ptr, va,
491 radv_cmd_buffer_uses_mec(cmd_buffer),
492 flags, cmd_buffer->gfx9_eop_bug_va);
493 }
494
495 if (unlikely(cmd_buffer->device->trace_bo))
496 radv_cmd_buffer_trace_emit(cmd_buffer);
497 }
498
499 static void
500 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
501 struct radv_pipeline *pipeline, enum ring_type ring)
502 {
503 struct radv_device *device = cmd_buffer->device;
504 uint32_t data[2];
505 uint64_t va;
506
507 va = radv_buffer_get_va(device->trace_bo);
508
509 switch (ring) {
510 case RING_GFX:
511 va += 8;
512 break;
513 case RING_COMPUTE:
514 va += 16;
515 break;
516 default:
517 assert(!"invalid ring type");
518 }
519
520 data[0] = (uintptr_t)pipeline;
521 data[1] = (uintptr_t)pipeline >> 32;
522
523 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
524 }
525
526 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
527 VkPipelineBindPoint bind_point,
528 struct radv_descriptor_set *set,
529 unsigned idx)
530 {
531 struct radv_descriptor_state *descriptors_state =
532 radv_get_descriptors_state(cmd_buffer, bind_point);
533
534 descriptors_state->sets[idx] = set;
535
536 descriptors_state->valid |= (1u << idx); /* active descriptors */
537 descriptors_state->dirty |= (1u << idx);
538 }
539
540 static void
541 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
542 VkPipelineBindPoint bind_point)
543 {
544 struct radv_descriptor_state *descriptors_state =
545 radv_get_descriptors_state(cmd_buffer, bind_point);
546 struct radv_device *device = cmd_buffer->device;
547 uint32_t data[MAX_SETS * 2] = {};
548 uint64_t va;
549 unsigned i;
550 va = radv_buffer_get_va(device->trace_bo) + 24;
551
552 for_each_bit(i, descriptors_state->valid) {
553 struct radv_descriptor_set *set = descriptors_state->sets[i];
554 data[i * 2] = (uintptr_t)set;
555 data[i * 2 + 1] = (uintptr_t)set >> 32;
556 }
557
558 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
559 }
560
561 struct radv_userdata_info *
562 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
563 gl_shader_stage stage,
564 int idx)
565 {
566 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
567 return &shader->info.user_sgprs_locs.shader_data[idx];
568 }
569
570 static void
571 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
572 struct radv_pipeline *pipeline,
573 gl_shader_stage stage,
574 int idx, uint64_t va)
575 {
576 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
577 uint32_t base_reg = pipeline->user_data_0[stage];
578 if (loc->sgpr_idx == -1)
579 return;
580
581 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
582 assert(!loc->indirect);
583
584 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
585 base_reg + loc->sgpr_idx * 4, va, false);
586 }
587
588 static void
589 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
590 struct radv_pipeline *pipeline,
591 struct radv_descriptor_state *descriptors_state,
592 gl_shader_stage stage)
593 {
594 struct radv_device *device = cmd_buffer->device;
595 struct radeon_cmdbuf *cs = cmd_buffer->cs;
596 uint32_t sh_base = pipeline->user_data_0[stage];
597 struct radv_userdata_locations *locs =
598 &pipeline->shaders[stage]->info.user_sgprs_locs;
599 unsigned mask = locs->descriptor_sets_enabled;
600
601 mask &= descriptors_state->dirty & descriptors_state->valid;
602
603 while (mask) {
604 int start, count;
605
606 u_bit_scan_consecutive_range(&mask, &start, &count);
607
608 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
609 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
610
611 radv_emit_shader_pointer_head(cs, sh_offset, count,
612 HAVE_32BIT_POINTERS);
613 for (int i = 0; i < count; i++) {
614 struct radv_descriptor_set *set =
615 descriptors_state->sets[start + i];
616
617 radv_emit_shader_pointer_body(device, cs, set->va,
618 HAVE_32BIT_POINTERS);
619 }
620 }
621 }
622
623 static void
624 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
625 struct radv_pipeline *pipeline)
626 {
627 int num_samples = pipeline->graphics.ms.num_samples;
628 struct radv_multisample_state *ms = &pipeline->graphics.ms;
629 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
630
631 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
632 cmd_buffer->sample_positions_needed = true;
633
634 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
635 return;
636
637 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
638 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
639 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
640
641 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
642
643 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
644
645 /* GFX9: Flush DFSM when the AA mode changes. */
646 if (cmd_buffer->device->dfsm_allowed) {
647 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
648 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
649 }
650 }
651
652 static void
653 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
654 struct radv_shader_variant *shader)
655 {
656 uint64_t va;
657
658 if (!shader)
659 return;
660
661 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
662
663 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
664 }
665
666 static void
667 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
668 struct radv_pipeline *pipeline,
669 bool vertex_stage_only)
670 {
671 struct radv_cmd_state *state = &cmd_buffer->state;
672 uint32_t mask = state->prefetch_L2_mask;
673
674 if (vertex_stage_only) {
675 /* Fast prefetch path for starting draws as soon as possible.
676 */
677 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
678 RADV_PREFETCH_VBO_DESCRIPTORS);
679 }
680
681 if (mask & RADV_PREFETCH_VS)
682 radv_emit_shader_prefetch(cmd_buffer,
683 pipeline->shaders[MESA_SHADER_VERTEX]);
684
685 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
686 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
687
688 if (mask & RADV_PREFETCH_TCS)
689 radv_emit_shader_prefetch(cmd_buffer,
690 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
691
692 if (mask & RADV_PREFETCH_TES)
693 radv_emit_shader_prefetch(cmd_buffer,
694 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
695
696 if (mask & RADV_PREFETCH_GS) {
697 radv_emit_shader_prefetch(cmd_buffer,
698 pipeline->shaders[MESA_SHADER_GEOMETRY]);
699 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
700 }
701
702 if (mask & RADV_PREFETCH_PS)
703 radv_emit_shader_prefetch(cmd_buffer,
704 pipeline->shaders[MESA_SHADER_FRAGMENT]);
705
706 state->prefetch_L2_mask &= ~mask;
707 }
708
709 static void
710 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
711 {
712 if (!cmd_buffer->device->physical_device->rbplus_allowed)
713 return;
714
715 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
716 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
717 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
718
719 unsigned sx_ps_downconvert = 0;
720 unsigned sx_blend_opt_epsilon = 0;
721 unsigned sx_blend_opt_control = 0;
722
723 for (unsigned i = 0; i < subpass->color_count; ++i) {
724 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
725 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
726 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
727 continue;
728 }
729
730 int idx = subpass->color_attachments[i].attachment;
731 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
732
733 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
734 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
735 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
736 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
737
738 bool has_alpha, has_rgb;
739
740 /* Set if RGB and A are present. */
741 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
742
743 if (format == V_028C70_COLOR_8 ||
744 format == V_028C70_COLOR_16 ||
745 format == V_028C70_COLOR_32)
746 has_rgb = !has_alpha;
747 else
748 has_rgb = true;
749
750 /* Check the colormask and export format. */
751 if (!(colormask & 0x7))
752 has_rgb = false;
753 if (!(colormask & 0x8))
754 has_alpha = false;
755
756 if (spi_format == V_028714_SPI_SHADER_ZERO) {
757 has_rgb = false;
758 has_alpha = false;
759 }
760
761 /* Disable value checking for disabled channels. */
762 if (!has_rgb)
763 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
764 if (!has_alpha)
765 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
766
767 /* Enable down-conversion for 32bpp and smaller formats. */
768 switch (format) {
769 case V_028C70_COLOR_8:
770 case V_028C70_COLOR_8_8:
771 case V_028C70_COLOR_8_8_8_8:
772 /* For 1 and 2-channel formats, use the superset thereof. */
773 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
774 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
775 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
776 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
777 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
778 }
779 break;
780
781 case V_028C70_COLOR_5_6_5:
782 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
783 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
784 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
785 }
786 break;
787
788 case V_028C70_COLOR_1_5_5_5:
789 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
790 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
791 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
792 }
793 break;
794
795 case V_028C70_COLOR_4_4_4_4:
796 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
797 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
798 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
799 }
800 break;
801
802 case V_028C70_COLOR_32:
803 if (swap == V_028C70_SWAP_STD &&
804 spi_format == V_028714_SPI_SHADER_32_R)
805 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
806 else if (swap == V_028C70_SWAP_ALT_REV &&
807 spi_format == V_028714_SPI_SHADER_32_AR)
808 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
809 break;
810
811 case V_028C70_COLOR_16:
812 case V_028C70_COLOR_16_16:
813 /* For 1-channel formats, use the superset thereof. */
814 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
815 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
816 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
817 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
818 if (swap == V_028C70_SWAP_STD ||
819 swap == V_028C70_SWAP_STD_REV)
820 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
821 else
822 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
823 }
824 break;
825
826 case V_028C70_COLOR_10_11_11:
827 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
828 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
829 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
830 }
831 break;
832
833 case V_028C70_COLOR_2_10_10_10:
834 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
835 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
836 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
837 }
838 break;
839 }
840 }
841
842 for (unsigned i = subpass->color_count; i < 8; ++i) {
843 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
844 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
845 }
846 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
847 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
848 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
849 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
850 }
851
852 static void
853 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
854 {
855 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
856
857 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
858 return;
859
860 radv_update_multisample_state(cmd_buffer, pipeline);
861
862 cmd_buffer->scratch_size_needed =
863 MAX2(cmd_buffer->scratch_size_needed,
864 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
865
866 if (!cmd_buffer->state.emitted_pipeline ||
867 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
868 pipeline->graphics.can_use_guardband)
869 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
870
871 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
872
873 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
874 if (!pipeline->shaders[i])
875 continue;
876
877 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
878 pipeline->shaders[i]->bo);
879 }
880
881 if (radv_pipeline_has_gs(pipeline))
882 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
883 pipeline->gs_copy_shader->bo);
884
885 if (unlikely(cmd_buffer->device->trace_bo))
886 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
887
888 cmd_buffer->state.emitted_pipeline = pipeline;
889
890 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
891 }
892
893 static void
894 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
895 {
896 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
897 cmd_buffer->state.dynamic.viewport.viewports);
898 }
899
900 static void
901 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
902 {
903 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
904
905 si_write_scissors(cmd_buffer->cs, 0, count,
906 cmd_buffer->state.dynamic.scissor.scissors,
907 cmd_buffer->state.dynamic.viewport.viewports,
908 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
909 }
910
911 static void
912 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
913 {
914 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
915 return;
916
917 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
918 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
919 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
920 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
921 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
922 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
923 S_028214_BR_Y(rect.offset.y + rect.extent.height));
924 }
925 }
926
927 static void
928 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
929 {
930 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
931
932 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
933 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
934 }
935
936 static void
937 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
938 {
939 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
940
941 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
942 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
943 }
944
945 static void
946 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
947 {
948 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
949
950 radeon_set_context_reg_seq(cmd_buffer->cs,
951 R_028430_DB_STENCILREFMASK, 2);
952 radeon_emit(cmd_buffer->cs,
953 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
954 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
955 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
956 S_028430_STENCILOPVAL(1));
957 radeon_emit(cmd_buffer->cs,
958 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
959 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
960 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
961 S_028434_STENCILOPVAL_BF(1));
962 }
963
964 static void
965 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
966 {
967 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
968
969 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
970 fui(d->depth_bounds.min));
971 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
972 fui(d->depth_bounds.max));
973 }
974
975 static void
976 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
977 {
978 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
979 unsigned slope = fui(d->depth_bias.slope * 16.0f);
980 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
981
982
983 radeon_set_context_reg_seq(cmd_buffer->cs,
984 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
985 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
986 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
987 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
988 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
989 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
990 }
991
992 static void
993 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
994 int index,
995 struct radv_attachment_info *att,
996 struct radv_image *image,
997 VkImageLayout layout)
998 {
999 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1000 struct radv_color_buffer_info *cb = &att->cb;
1001 uint32_t cb_color_info = cb->cb_color_info;
1002
1003 if (!radv_layout_dcc_compressed(image, layout,
1004 radv_image_queue_family_mask(image,
1005 cmd_buffer->queue_family_index,
1006 cmd_buffer->queue_family_index))) {
1007 cb_color_info &= C_028C70_DCC_ENABLE;
1008 }
1009
1010 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1011 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1012 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1013 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1014 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1015 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1016 radeon_emit(cmd_buffer->cs, cb_color_info);
1017 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1018 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1019 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1020 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1021 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1022 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1023
1024 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1025 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1026 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1027
1028 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1029 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1030 } else {
1031 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1032 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1033 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1034 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1035 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1036 radeon_emit(cmd_buffer->cs, cb_color_info);
1037 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1038 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1039 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1040 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1041 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1042 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1043
1044 if (is_vi) { /* DCC BASE */
1045 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1046 }
1047 }
1048 }
1049
1050 static void
1051 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1052 struct radv_ds_buffer_info *ds,
1053 struct radv_image *image, VkImageLayout layout,
1054 bool requires_cond_write)
1055 {
1056 uint32_t db_z_info = ds->db_z_info;
1057 uint32_t db_z_info_reg;
1058
1059 if (!radv_image_is_tc_compat_htile(image))
1060 return;
1061
1062 if (!radv_layout_has_htile(image, layout,
1063 radv_image_queue_family_mask(image,
1064 cmd_buffer->queue_family_index,
1065 cmd_buffer->queue_family_index))) {
1066 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1067 }
1068
1069 db_z_info &= C_028040_ZRANGE_PRECISION;
1070
1071 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1072 db_z_info_reg = R_028038_DB_Z_INFO;
1073 } else {
1074 db_z_info_reg = R_028040_DB_Z_INFO;
1075 }
1076
1077 /* When we don't know the last fast clear value we need to emit a
1078 * conditional packet, otherwise we can update DB_Z_INFO directly.
1079 */
1080 if (requires_cond_write) {
1081 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1082
1083 const uint32_t write_space = 0 << 8; /* register */
1084 const uint32_t poll_space = 1 << 4; /* memory */
1085 const uint32_t function = 3 << 0; /* equal to the reference */
1086 const uint32_t options = write_space | poll_space | function;
1087 radeon_emit(cmd_buffer->cs, options);
1088
1089 /* poll address - location of the depth clear value */
1090 uint64_t va = radv_buffer_get_va(image->bo);
1091 va += image->offset + image->clear_value_offset;
1092
1093 /* In presence of stencil format, we have to adjust the base
1094 * address because the first value is the stencil clear value.
1095 */
1096 if (vk_format_is_stencil(image->vk_format))
1097 va += 4;
1098
1099 radeon_emit(cmd_buffer->cs, va);
1100 radeon_emit(cmd_buffer->cs, va >> 32);
1101
1102 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1103 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1104 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1105 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1106 radeon_emit(cmd_buffer->cs, db_z_info);
1107 } else {
1108 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1109 }
1110 }
1111
1112 static void
1113 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1114 struct radv_ds_buffer_info *ds,
1115 struct radv_image *image,
1116 VkImageLayout layout)
1117 {
1118 uint32_t db_z_info = ds->db_z_info;
1119 uint32_t db_stencil_info = ds->db_stencil_info;
1120
1121 if (!radv_layout_has_htile(image, layout,
1122 radv_image_queue_family_mask(image,
1123 cmd_buffer->queue_family_index,
1124 cmd_buffer->queue_family_index))) {
1125 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1126 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1127 }
1128
1129 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1130 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1131
1132
1133 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1134 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1135 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1136 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1137 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1138
1139 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1140 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1141 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1142 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1143 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1144 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1145 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1146 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1147 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1148 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1149 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1150
1151 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1152 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1153 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1154 } else {
1155 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1156
1157 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1158 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1159 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1160 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1161 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1162 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1163 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1164 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1165 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1166 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1167
1168 }
1169
1170 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1171 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1172
1173 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1174 ds->pa_su_poly_offset_db_fmt_cntl);
1175 }
1176
1177 /**
1178 * Update the fast clear depth/stencil values if the image is bound as a
1179 * depth/stencil buffer.
1180 */
1181 static void
1182 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1183 struct radv_image *image,
1184 VkClearDepthStencilValue ds_clear_value,
1185 VkImageAspectFlags aspects)
1186 {
1187 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1188 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1189 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1190 struct radv_attachment_info *att;
1191 uint32_t att_idx;
1192
1193 if (!framebuffer || !subpass)
1194 return;
1195
1196 att_idx = subpass->depth_stencil_attachment.attachment;
1197 if (att_idx == VK_ATTACHMENT_UNUSED)
1198 return;
1199
1200 att = &framebuffer->attachments[att_idx];
1201 if (att->attachment->image != image)
1202 return;
1203
1204 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1205 radeon_emit(cs, ds_clear_value.stencil);
1206 radeon_emit(cs, fui(ds_clear_value.depth));
1207
1208 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1209 * only needed when clearing Z to 0.0.
1210 */
1211 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1212 ds_clear_value.depth == 0.0) {
1213 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1214
1215 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1216 layout, false);
1217 }
1218 }
1219
1220 /**
1221 * Set the clear depth/stencil values to the image's metadata.
1222 */
1223 static void
1224 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1225 struct radv_image *image,
1226 VkClearDepthStencilValue ds_clear_value,
1227 VkImageAspectFlags aspects)
1228 {
1229 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1230 uint64_t va = radv_buffer_get_va(image->bo);
1231 unsigned reg_offset = 0, reg_count = 0;
1232
1233 va += image->offset + image->clear_value_offset;
1234
1235 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1236 ++reg_count;
1237 } else {
1238 ++reg_offset;
1239 va += 4;
1240 }
1241 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1242 ++reg_count;
1243
1244 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1245 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1246 S_370_WR_CONFIRM(1) |
1247 S_370_ENGINE_SEL(V_370_PFP));
1248 radeon_emit(cs, va);
1249 radeon_emit(cs, va >> 32);
1250 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1251 radeon_emit(cs, ds_clear_value.stencil);
1252 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1253 radeon_emit(cs, fui(ds_clear_value.depth));
1254 }
1255
1256 /**
1257 * Update the clear depth/stencil values for this image.
1258 */
1259 void
1260 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1261 struct radv_image *image,
1262 VkClearDepthStencilValue ds_clear_value,
1263 VkImageAspectFlags aspects)
1264 {
1265 assert(radv_image_has_htile(image));
1266
1267 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1268
1269 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1270 aspects);
1271 }
1272
1273 /**
1274 * Load the clear depth/stencil values from the image's metadata.
1275 */
1276 static void
1277 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1278 struct radv_image *image)
1279 {
1280 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1281 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1282 uint64_t va = radv_buffer_get_va(image->bo);
1283 unsigned reg_offset = 0, reg_count = 0;
1284
1285 va += image->offset + image->clear_value_offset;
1286
1287 if (!radv_image_has_htile(image))
1288 return;
1289
1290 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1291 ++reg_count;
1292 } else {
1293 ++reg_offset;
1294 va += 4;
1295 }
1296 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1297 ++reg_count;
1298
1299 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1300 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1301 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1302 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1303 radeon_emit(cs, va);
1304 radeon_emit(cs, va >> 32);
1305 radeon_emit(cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1306 radeon_emit(cs, 0);
1307
1308 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1309 radeon_emit(cs, 0);
1310 }
1311
1312 /*
1313 * With DCC some colors don't require CMASK elimination before being
1314 * used as a texture. This sets a predicate value to determine if the
1315 * cmask eliminate is required.
1316 */
1317 void
1318 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1319 struct radv_image *image,
1320 bool value)
1321 {
1322 uint64_t pred_val = value;
1323 uint64_t va = radv_buffer_get_va(image->bo);
1324 va += image->offset + image->dcc_pred_offset;
1325
1326 assert(radv_image_has_dcc(image));
1327
1328 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1329 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1330 S_370_WR_CONFIRM(1) |
1331 S_370_ENGINE_SEL(V_370_PFP));
1332 radeon_emit(cmd_buffer->cs, va);
1333 radeon_emit(cmd_buffer->cs, va >> 32);
1334 radeon_emit(cmd_buffer->cs, pred_val);
1335 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1336 }
1337
1338 /**
1339 * Update the fast clear color values if the image is bound as a color buffer.
1340 */
1341 static void
1342 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1343 struct radv_image *image,
1344 int cb_idx,
1345 uint32_t color_values[2])
1346 {
1347 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1348 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1349 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1350 struct radv_attachment_info *att;
1351 uint32_t att_idx;
1352
1353 if (!framebuffer || !subpass)
1354 return;
1355
1356 att_idx = subpass->color_attachments[cb_idx].attachment;
1357 if (att_idx == VK_ATTACHMENT_UNUSED)
1358 return;
1359
1360 att = &framebuffer->attachments[att_idx];
1361 if (att->attachment->image != image)
1362 return;
1363
1364 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1365 radeon_emit(cs, color_values[0]);
1366 radeon_emit(cs, color_values[1]);
1367 }
1368
1369 /**
1370 * Set the clear color values to the image's metadata.
1371 */
1372 static void
1373 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1374 struct radv_image *image,
1375 uint32_t color_values[2])
1376 {
1377 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1378 uint64_t va = radv_buffer_get_va(image->bo);
1379
1380 va += image->offset + image->clear_value_offset;
1381
1382 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1383
1384 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1385 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1386 S_370_WR_CONFIRM(1) |
1387 S_370_ENGINE_SEL(V_370_PFP));
1388 radeon_emit(cs, va);
1389 radeon_emit(cs, va >> 32);
1390 radeon_emit(cs, color_values[0]);
1391 radeon_emit(cs, color_values[1]);
1392 }
1393
1394 /**
1395 * Update the clear color values for this image.
1396 */
1397 void
1398 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1399 struct radv_image *image,
1400 int cb_idx,
1401 uint32_t color_values[2])
1402 {
1403 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1404
1405 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1406
1407 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1408 color_values);
1409 }
1410
1411 /**
1412 * Load the clear color values from the image's metadata.
1413 */
1414 static void
1415 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1416 struct radv_image *image,
1417 int cb_idx)
1418 {
1419 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1420 uint64_t va = radv_buffer_get_va(image->bo);
1421
1422 va += image->offset + image->clear_value_offset;
1423
1424 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1425 return;
1426
1427 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1428
1429 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1430 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1431 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1432 COPY_DATA_COUNT_SEL);
1433 radeon_emit(cs, va);
1434 radeon_emit(cs, va >> 32);
1435 radeon_emit(cs, reg >> 2);
1436 radeon_emit(cs, 0);
1437
1438 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1439 radeon_emit(cs, 0);
1440 }
1441
1442 static void
1443 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1444 {
1445 int i;
1446 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1447 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1448
1449 /* this may happen for inherited secondary recording */
1450 if (!framebuffer)
1451 return;
1452
1453 for (i = 0; i < 8; ++i) {
1454 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1455 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1456 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1457 continue;
1458 }
1459
1460 int idx = subpass->color_attachments[i].attachment;
1461 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1462 struct radv_image *image = att->attachment->image;
1463 VkImageLayout layout = subpass->color_attachments[i].layout;
1464
1465 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1466
1467 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1468 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1469
1470 radv_load_color_clear_metadata(cmd_buffer, image, i);
1471 }
1472
1473 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1474 int idx = subpass->depth_stencil_attachment.attachment;
1475 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1476 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1477 struct radv_image *image = att->attachment->image;
1478 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1479 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1480 cmd_buffer->queue_family_index,
1481 cmd_buffer->queue_family_index);
1482 /* We currently don't support writing decompressed HTILE */
1483 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1484 radv_layout_is_htile_compressed(image, layout, queue_mask));
1485
1486 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1487
1488 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1489 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1490 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1491 }
1492 radv_load_ds_clear_metadata(cmd_buffer, image);
1493 } else {
1494 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1495 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1496 else
1497 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1498
1499 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1500 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1501 }
1502 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1503 S_028208_BR_X(framebuffer->width) |
1504 S_028208_BR_Y(framebuffer->height));
1505
1506 if (cmd_buffer->device->dfsm_allowed) {
1507 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1508 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1509 }
1510
1511 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1512 }
1513
1514 static void
1515 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1516 {
1517 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1518 struct radv_cmd_state *state = &cmd_buffer->state;
1519
1520 if (state->index_type != state->last_index_type) {
1521 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1522 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1523 2, state->index_type);
1524 } else {
1525 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1526 radeon_emit(cs, state->index_type);
1527 }
1528
1529 state->last_index_type = state->index_type;
1530 }
1531
1532 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1533 radeon_emit(cs, state->index_va);
1534 radeon_emit(cs, state->index_va >> 32);
1535
1536 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1537 radeon_emit(cs, state->max_index_count);
1538
1539 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1540 }
1541
1542 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1543 {
1544 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1545 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1546 uint32_t pa_sc_mode_cntl_1 =
1547 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1548 uint32_t db_count_control;
1549
1550 if(!cmd_buffer->state.active_occlusion_queries) {
1551 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1552 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1553 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1554 has_perfect_queries) {
1555 /* Re-enable out-of-order rasterization if the
1556 * bound pipeline supports it and if it's has
1557 * been disabled before starting any perfect
1558 * occlusion queries.
1559 */
1560 radeon_set_context_reg(cmd_buffer->cs,
1561 R_028A4C_PA_SC_MODE_CNTL_1,
1562 pa_sc_mode_cntl_1);
1563 }
1564 }
1565 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1566 } else {
1567 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1568 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1569
1570 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1571 db_count_control =
1572 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1573 S_028004_SAMPLE_RATE(sample_rate) |
1574 S_028004_ZPASS_ENABLE(1) |
1575 S_028004_SLICE_EVEN_ENABLE(1) |
1576 S_028004_SLICE_ODD_ENABLE(1);
1577
1578 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1579 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1580 has_perfect_queries) {
1581 /* If the bound pipeline has enabled
1582 * out-of-order rasterization, we should
1583 * disable it before starting any perfect
1584 * occlusion queries.
1585 */
1586 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1587
1588 radeon_set_context_reg(cmd_buffer->cs,
1589 R_028A4C_PA_SC_MODE_CNTL_1,
1590 pa_sc_mode_cntl_1);
1591 }
1592 } else {
1593 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1594 S_028004_SAMPLE_RATE(sample_rate);
1595 }
1596 }
1597
1598 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1599 }
1600
1601 static void
1602 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1603 {
1604 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1605
1606 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1607 radv_emit_viewport(cmd_buffer);
1608
1609 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1610 !cmd_buffer->device->physical_device->has_scissor_bug)
1611 radv_emit_scissor(cmd_buffer);
1612
1613 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1614 radv_emit_line_width(cmd_buffer);
1615
1616 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1617 radv_emit_blend_constants(cmd_buffer);
1618
1619 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1620 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1621 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1622 radv_emit_stencil(cmd_buffer);
1623
1624 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1625 radv_emit_depth_bounds(cmd_buffer);
1626
1627 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1628 radv_emit_depth_bias(cmd_buffer);
1629
1630 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1631 radv_emit_discard_rectangle(cmd_buffer);
1632
1633 cmd_buffer->state.dirty &= ~states;
1634 }
1635
1636 static void
1637 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1638 VkPipelineBindPoint bind_point)
1639 {
1640 struct radv_descriptor_state *descriptors_state =
1641 radv_get_descriptors_state(cmd_buffer, bind_point);
1642 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1643 unsigned bo_offset;
1644
1645 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1646 set->mapped_ptr,
1647 &bo_offset))
1648 return;
1649
1650 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1651 set->va += bo_offset;
1652 }
1653
1654 static void
1655 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1656 VkPipelineBindPoint bind_point)
1657 {
1658 struct radv_descriptor_state *descriptors_state =
1659 radv_get_descriptors_state(cmd_buffer, bind_point);
1660 uint8_t ptr_size = HAVE_32BIT_POINTERS ? 1 : 2;
1661 uint32_t size = MAX_SETS * 4 * ptr_size;
1662 uint32_t offset;
1663 void *ptr;
1664
1665 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1666 256, &offset, &ptr))
1667 return;
1668
1669 for (unsigned i = 0; i < MAX_SETS; i++) {
1670 uint32_t *uptr = ((uint32_t *)ptr) + i * ptr_size;
1671 uint64_t set_va = 0;
1672 struct radv_descriptor_set *set = descriptors_state->sets[i];
1673 if (descriptors_state->valid & (1u << i))
1674 set_va = set->va;
1675 uptr[0] = set_va & 0xffffffff;
1676 if (ptr_size == 2)
1677 uptr[1] = set_va >> 32;
1678 }
1679
1680 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1681 va += offset;
1682
1683 if (cmd_buffer->state.pipeline) {
1684 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1685 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1686 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1687
1688 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1689 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1690 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1691
1692 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1693 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1694 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1695
1696 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1697 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1698 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1699
1700 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1701 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1702 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1703 }
1704
1705 if (cmd_buffer->state.compute_pipeline)
1706 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1707 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1708 }
1709
1710 static void
1711 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1712 VkShaderStageFlags stages)
1713 {
1714 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1715 VK_PIPELINE_BIND_POINT_COMPUTE :
1716 VK_PIPELINE_BIND_POINT_GRAPHICS;
1717 struct radv_descriptor_state *descriptors_state =
1718 radv_get_descriptors_state(cmd_buffer, bind_point);
1719 struct radv_cmd_state *state = &cmd_buffer->state;
1720 bool flush_indirect_descriptors;
1721
1722 if (!descriptors_state->dirty)
1723 return;
1724
1725 if (descriptors_state->push_dirty)
1726 radv_flush_push_descriptors(cmd_buffer, bind_point);
1727
1728 flush_indirect_descriptors =
1729 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1730 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1731 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1732 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1733
1734 if (flush_indirect_descriptors)
1735 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1736
1737 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1738 cmd_buffer->cs,
1739 MAX_SETS * MESA_SHADER_STAGES * 4);
1740
1741 if (cmd_buffer->state.pipeline) {
1742 radv_foreach_stage(stage, stages) {
1743 if (!cmd_buffer->state.pipeline->shaders[stage])
1744 continue;
1745
1746 radv_emit_descriptor_pointers(cmd_buffer,
1747 cmd_buffer->state.pipeline,
1748 descriptors_state, stage);
1749 }
1750 }
1751
1752 if (cmd_buffer->state.compute_pipeline &&
1753 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1754 radv_emit_descriptor_pointers(cmd_buffer,
1755 cmd_buffer->state.compute_pipeline,
1756 descriptors_state,
1757 MESA_SHADER_COMPUTE);
1758 }
1759
1760 descriptors_state->dirty = 0;
1761 descriptors_state->push_dirty = false;
1762
1763 assert(cmd_buffer->cs->cdw <= cdw_max);
1764
1765 if (unlikely(cmd_buffer->device->trace_bo))
1766 radv_save_descriptors(cmd_buffer, bind_point);
1767 }
1768
1769 static void
1770 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1771 VkShaderStageFlags stages)
1772 {
1773 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1774 ? cmd_buffer->state.compute_pipeline
1775 : cmd_buffer->state.pipeline;
1776 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1777 VK_PIPELINE_BIND_POINT_COMPUTE :
1778 VK_PIPELINE_BIND_POINT_GRAPHICS;
1779 struct radv_descriptor_state *descriptors_state =
1780 radv_get_descriptors_state(cmd_buffer, bind_point);
1781 struct radv_pipeline_layout *layout = pipeline->layout;
1782 struct radv_shader_variant *shader, *prev_shader;
1783 unsigned offset;
1784 void *ptr;
1785 uint64_t va;
1786
1787 stages &= cmd_buffer->push_constant_stages;
1788 if (!stages ||
1789 (!layout->push_constant_size && !layout->dynamic_offset_count))
1790 return;
1791
1792 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1793 16 * layout->dynamic_offset_count,
1794 256, &offset, &ptr))
1795 return;
1796
1797 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1798 memcpy((char*)ptr + layout->push_constant_size,
1799 descriptors_state->dynamic_buffers,
1800 16 * layout->dynamic_offset_count);
1801
1802 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1803 va += offset;
1804
1805 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1806 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1807
1808 prev_shader = NULL;
1809 radv_foreach_stage(stage, stages) {
1810 shader = radv_get_shader(pipeline, stage);
1811
1812 /* Avoid redundantly emitting the address for merged stages. */
1813 if (shader && shader != prev_shader) {
1814 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1815 AC_UD_PUSH_CONSTANTS, va);
1816
1817 prev_shader = shader;
1818 }
1819 }
1820
1821 cmd_buffer->push_constant_stages &= ~stages;
1822 assert(cmd_buffer->cs->cdw <= cdw_max);
1823 }
1824
1825 static void
1826 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1827 bool pipeline_is_dirty)
1828 {
1829 if ((pipeline_is_dirty ||
1830 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1831 cmd_buffer->state.pipeline->vertex_elements.count &&
1832 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1833 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1834 unsigned vb_offset;
1835 void *vb_ptr;
1836 uint32_t i = 0;
1837 uint32_t count = velems->count;
1838 uint64_t va;
1839
1840 /* allocate some descriptor state for vertex buffers */
1841 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1842 &vb_offset, &vb_ptr))
1843 return;
1844
1845 for (i = 0; i < count; i++) {
1846 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1847 uint32_t offset;
1848 int vb = velems->binding[i];
1849 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1850 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1851
1852 va = radv_buffer_get_va(buffer->bo);
1853
1854 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1855 va += offset + buffer->offset;
1856 desc[0] = va;
1857 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1858 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1859 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1860 else
1861 desc[2] = buffer->size - offset;
1862 desc[3] = velems->rsrc_word3[i];
1863 }
1864
1865 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1866 va += vb_offset;
1867
1868 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1869 AC_UD_VS_VERTEX_BUFFERS, va);
1870
1871 cmd_buffer->state.vb_va = va;
1872 cmd_buffer->state.vb_size = count * 16;
1873 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1874 }
1875 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1876 }
1877
1878 static void
1879 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1880 {
1881 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1882 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1883 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1884 }
1885
1886 static void
1887 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1888 bool instanced_draw, bool indirect_draw,
1889 uint32_t draw_vertex_count)
1890 {
1891 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1892 struct radv_cmd_state *state = &cmd_buffer->state;
1893 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1894 uint32_t ia_multi_vgt_param;
1895 int32_t primitive_reset_en;
1896
1897 /* Draw state. */
1898 ia_multi_vgt_param =
1899 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1900 indirect_draw, draw_vertex_count);
1901
1902 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1903 if (info->chip_class >= GFX9) {
1904 radeon_set_uconfig_reg_idx(cs,
1905 R_030960_IA_MULTI_VGT_PARAM,
1906 4, ia_multi_vgt_param);
1907 } else if (info->chip_class >= CIK) {
1908 radeon_set_context_reg_idx(cs,
1909 R_028AA8_IA_MULTI_VGT_PARAM,
1910 1, ia_multi_vgt_param);
1911 } else {
1912 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1913 ia_multi_vgt_param);
1914 }
1915 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1916 }
1917
1918 /* Primitive restart. */
1919 primitive_reset_en =
1920 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1921
1922 if (primitive_reset_en != state->last_primitive_reset_en) {
1923 state->last_primitive_reset_en = primitive_reset_en;
1924 if (info->chip_class >= GFX9) {
1925 radeon_set_uconfig_reg(cs,
1926 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1927 primitive_reset_en);
1928 } else {
1929 radeon_set_context_reg(cs,
1930 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1931 primitive_reset_en);
1932 }
1933 }
1934
1935 if (primitive_reset_en) {
1936 uint32_t primitive_reset_index =
1937 state->index_type ? 0xffffffffu : 0xffffu;
1938
1939 if (primitive_reset_index != state->last_primitive_reset_index) {
1940 radeon_set_context_reg(cs,
1941 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1942 primitive_reset_index);
1943 state->last_primitive_reset_index = primitive_reset_index;
1944 }
1945 }
1946 }
1947
1948 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1949 VkPipelineStageFlags src_stage_mask)
1950 {
1951 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1952 VK_PIPELINE_STAGE_TRANSFER_BIT |
1953 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1954 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1955 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1956 }
1957
1958 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1959 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1960 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1961 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1962 VK_PIPELINE_STAGE_TRANSFER_BIT |
1963 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1964 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1965 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1966 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1967 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1968 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1969 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
1970 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1971 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1972 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT)) {
1973 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1974 }
1975 }
1976
1977 static enum radv_cmd_flush_bits
1978 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1979 VkAccessFlags src_flags,
1980 struct radv_image *image)
1981 {
1982 bool flush_CB_meta = true, flush_DB_meta = true;
1983 enum radv_cmd_flush_bits flush_bits = 0;
1984 uint32_t b;
1985
1986 if (image) {
1987 if (!radv_image_has_CB_metadata(image))
1988 flush_CB_meta = false;
1989 if (!radv_image_has_htile(image))
1990 flush_DB_meta = false;
1991 }
1992
1993 for_each_bit(b, src_flags) {
1994 switch ((VkAccessFlagBits)(1 << b)) {
1995 case VK_ACCESS_SHADER_WRITE_BIT:
1996 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1997 break;
1998 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1999 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2000 if (flush_CB_meta)
2001 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2002 break;
2003 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2004 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2005 if (flush_DB_meta)
2006 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2007 break;
2008 case VK_ACCESS_TRANSFER_WRITE_BIT:
2009 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2010 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2011 RADV_CMD_FLAG_INV_GLOBAL_L2;
2012
2013 if (flush_CB_meta)
2014 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2015 if (flush_DB_meta)
2016 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2017 break;
2018 default:
2019 break;
2020 }
2021 }
2022 return flush_bits;
2023 }
2024
2025 static enum radv_cmd_flush_bits
2026 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2027 VkAccessFlags dst_flags,
2028 struct radv_image *image)
2029 {
2030 bool flush_CB_meta = true, flush_DB_meta = true;
2031 enum radv_cmd_flush_bits flush_bits = 0;
2032 bool flush_CB = true, flush_DB = true;
2033 bool image_is_coherent = false;
2034 uint32_t b;
2035
2036 if (image) {
2037 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2038 flush_CB = false;
2039 flush_DB = false;
2040 }
2041
2042 if (!radv_image_has_CB_metadata(image))
2043 flush_CB_meta = false;
2044 if (!radv_image_has_htile(image))
2045 flush_DB_meta = false;
2046
2047 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2048 if (image->info.samples == 1 &&
2049 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2050 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2051 !vk_format_is_stencil(image->vk_format)) {
2052 /* Single-sample color and single-sample depth
2053 * (not stencil) are coherent with shaders on
2054 * GFX9.
2055 */
2056 image_is_coherent = true;
2057 }
2058 }
2059 }
2060
2061 for_each_bit(b, dst_flags) {
2062 switch ((VkAccessFlagBits)(1 << b)) {
2063 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2064 case VK_ACCESS_INDEX_READ_BIT:
2065 break;
2066 case VK_ACCESS_UNIFORM_READ_BIT:
2067 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2068 break;
2069 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2070 case VK_ACCESS_TRANSFER_READ_BIT:
2071 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2072 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2073 RADV_CMD_FLAG_INV_GLOBAL_L2;
2074 break;
2075 case VK_ACCESS_SHADER_READ_BIT:
2076 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2077
2078 if (!image_is_coherent)
2079 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2080 break;
2081 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2082 if (flush_CB)
2083 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2084 if (flush_CB_meta)
2085 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2086 break;
2087 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2088 if (flush_DB)
2089 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2090 if (flush_DB_meta)
2091 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2092 break;
2093 default:
2094 break;
2095 }
2096 }
2097 return flush_bits;
2098 }
2099
2100 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2101 const struct radv_subpass_barrier *barrier)
2102 {
2103 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2104 NULL);
2105 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2106 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2107 NULL);
2108 }
2109
2110 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2111 struct radv_subpass_attachment att)
2112 {
2113 unsigned idx = att.attachment;
2114 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2115 VkImageSubresourceRange range;
2116 range.aspectMask = 0;
2117 range.baseMipLevel = view->base_mip;
2118 range.levelCount = 1;
2119 range.baseArrayLayer = view->base_layer;
2120 range.layerCount = cmd_buffer->state.framebuffer->layers;
2121
2122 radv_handle_image_transition(cmd_buffer,
2123 view->image,
2124 cmd_buffer->state.attachments[idx].current_layout,
2125 att.layout, 0, 0, &range,
2126 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2127
2128 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2129
2130
2131 }
2132
2133 void
2134 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2135 const struct radv_subpass *subpass, bool transitions)
2136 {
2137 if (transitions) {
2138 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2139
2140 for (unsigned i = 0; i < subpass->color_count; ++i) {
2141 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2142 radv_handle_subpass_image_transition(cmd_buffer,
2143 subpass->color_attachments[i]);
2144 }
2145
2146 for (unsigned i = 0; i < subpass->input_count; ++i) {
2147 radv_handle_subpass_image_transition(cmd_buffer,
2148 subpass->input_attachments[i]);
2149 }
2150
2151 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2152 radv_handle_subpass_image_transition(cmd_buffer,
2153 subpass->depth_stencil_attachment);
2154 }
2155 }
2156
2157 cmd_buffer->state.subpass = subpass;
2158
2159 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2160 }
2161
2162 static VkResult
2163 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2164 struct radv_render_pass *pass,
2165 const VkRenderPassBeginInfo *info)
2166 {
2167 struct radv_cmd_state *state = &cmd_buffer->state;
2168
2169 if (pass->attachment_count == 0) {
2170 state->attachments = NULL;
2171 return VK_SUCCESS;
2172 }
2173
2174 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2175 pass->attachment_count *
2176 sizeof(state->attachments[0]),
2177 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2178 if (state->attachments == NULL) {
2179 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2180 return cmd_buffer->record_result;
2181 }
2182
2183 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2184 struct radv_render_pass_attachment *att = &pass->attachments[i];
2185 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2186 VkImageAspectFlags clear_aspects = 0;
2187
2188 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2189 /* color attachment */
2190 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2191 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2192 }
2193 } else {
2194 /* depthstencil attachment */
2195 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2196 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2197 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2198 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2199 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2200 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2201 }
2202 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2203 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2204 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2205 }
2206 }
2207
2208 state->attachments[i].pending_clear_aspects = clear_aspects;
2209 state->attachments[i].cleared_views = 0;
2210 if (clear_aspects && info) {
2211 assert(info->clearValueCount > i);
2212 state->attachments[i].clear_value = info->pClearValues[i];
2213 }
2214
2215 state->attachments[i].current_layout = att->initial_layout;
2216 }
2217
2218 return VK_SUCCESS;
2219 }
2220
2221 VkResult radv_AllocateCommandBuffers(
2222 VkDevice _device,
2223 const VkCommandBufferAllocateInfo *pAllocateInfo,
2224 VkCommandBuffer *pCommandBuffers)
2225 {
2226 RADV_FROM_HANDLE(radv_device, device, _device);
2227 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2228
2229 VkResult result = VK_SUCCESS;
2230 uint32_t i;
2231
2232 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2233
2234 if (!list_empty(&pool->free_cmd_buffers)) {
2235 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2236
2237 list_del(&cmd_buffer->pool_link);
2238 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2239
2240 result = radv_reset_cmd_buffer(cmd_buffer);
2241 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2242 cmd_buffer->level = pAllocateInfo->level;
2243
2244 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2245 } else {
2246 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2247 &pCommandBuffers[i]);
2248 }
2249 if (result != VK_SUCCESS)
2250 break;
2251 }
2252
2253 if (result != VK_SUCCESS) {
2254 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2255 i, pCommandBuffers);
2256
2257 /* From the Vulkan 1.0.66 spec:
2258 *
2259 * "vkAllocateCommandBuffers can be used to create multiple
2260 * command buffers. If the creation of any of those command
2261 * buffers fails, the implementation must destroy all
2262 * successfully created command buffer objects from this
2263 * command, set all entries of the pCommandBuffers array to
2264 * NULL and return the error."
2265 */
2266 memset(pCommandBuffers, 0,
2267 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2268 }
2269
2270 return result;
2271 }
2272
2273 void radv_FreeCommandBuffers(
2274 VkDevice device,
2275 VkCommandPool commandPool,
2276 uint32_t commandBufferCount,
2277 const VkCommandBuffer *pCommandBuffers)
2278 {
2279 for (uint32_t i = 0; i < commandBufferCount; i++) {
2280 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2281
2282 if (cmd_buffer) {
2283 if (cmd_buffer->pool) {
2284 list_del(&cmd_buffer->pool_link);
2285 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2286 } else
2287 radv_cmd_buffer_destroy(cmd_buffer);
2288
2289 }
2290 }
2291 }
2292
2293 VkResult radv_ResetCommandBuffer(
2294 VkCommandBuffer commandBuffer,
2295 VkCommandBufferResetFlags flags)
2296 {
2297 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2298 return radv_reset_cmd_buffer(cmd_buffer);
2299 }
2300
2301 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2302 {
2303 struct radv_device *device = cmd_buffer->device;
2304 if (device->gfx_init) {
2305 uint64_t va = radv_buffer_get_va(device->gfx_init);
2306 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init);
2307 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2308 radeon_emit(cmd_buffer->cs, va);
2309 radeon_emit(cmd_buffer->cs, va >> 32);
2310 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2311 } else
2312 si_init_config(cmd_buffer);
2313 }
2314
2315 VkResult radv_BeginCommandBuffer(
2316 VkCommandBuffer commandBuffer,
2317 const VkCommandBufferBeginInfo *pBeginInfo)
2318 {
2319 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2320 VkResult result = VK_SUCCESS;
2321
2322 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2323 /* If the command buffer has already been resetted with
2324 * vkResetCommandBuffer, no need to do it again.
2325 */
2326 result = radv_reset_cmd_buffer(cmd_buffer);
2327 if (result != VK_SUCCESS)
2328 return result;
2329 }
2330
2331 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2332 cmd_buffer->state.last_primitive_reset_en = -1;
2333 cmd_buffer->state.last_index_type = -1;
2334 cmd_buffer->state.last_num_instances = -1;
2335 cmd_buffer->state.last_vertex_offset = -1;
2336 cmd_buffer->state.last_first_instance = -1;
2337 cmd_buffer->state.predication_type = -1;
2338 cmd_buffer->usage_flags = pBeginInfo->flags;
2339
2340 /* setup initial configuration into command buffer */
2341 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2342 switch (cmd_buffer->queue_family_index) {
2343 case RADV_QUEUE_GENERAL:
2344 emit_gfx_buffer_state(cmd_buffer);
2345 break;
2346 case RADV_QUEUE_COMPUTE:
2347 si_init_compute(cmd_buffer);
2348 break;
2349 case RADV_QUEUE_TRANSFER:
2350 default:
2351 break;
2352 }
2353 }
2354
2355 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2356 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2357 assert(pBeginInfo->pInheritanceInfo);
2358 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2359 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2360
2361 struct radv_subpass *subpass =
2362 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2363
2364 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2365 if (result != VK_SUCCESS)
2366 return result;
2367
2368 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2369 }
2370
2371 if (unlikely(cmd_buffer->device->trace_bo)) {
2372 struct radv_device *device = cmd_buffer->device;
2373
2374 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2375 device->trace_bo);
2376
2377 radv_cmd_buffer_trace_emit(cmd_buffer);
2378 }
2379
2380 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2381
2382 return result;
2383 }
2384
2385 void radv_CmdBindVertexBuffers(
2386 VkCommandBuffer commandBuffer,
2387 uint32_t firstBinding,
2388 uint32_t bindingCount,
2389 const VkBuffer* pBuffers,
2390 const VkDeviceSize* pOffsets)
2391 {
2392 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2393 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2394 bool changed = false;
2395
2396 /* We have to defer setting up vertex buffer since we need the buffer
2397 * stride from the pipeline. */
2398
2399 assert(firstBinding + bindingCount <= MAX_VBS);
2400 for (uint32_t i = 0; i < bindingCount; i++) {
2401 uint32_t idx = firstBinding + i;
2402
2403 if (!changed &&
2404 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2405 vb[idx].offset != pOffsets[i])) {
2406 changed = true;
2407 }
2408
2409 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2410 vb[idx].offset = pOffsets[i];
2411
2412 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2413 vb[idx].buffer->bo);
2414 }
2415
2416 if (!changed) {
2417 /* No state changes. */
2418 return;
2419 }
2420
2421 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2422 }
2423
2424 void radv_CmdBindIndexBuffer(
2425 VkCommandBuffer commandBuffer,
2426 VkBuffer buffer,
2427 VkDeviceSize offset,
2428 VkIndexType indexType)
2429 {
2430 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2431 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2432
2433 if (cmd_buffer->state.index_buffer == index_buffer &&
2434 cmd_buffer->state.index_offset == offset &&
2435 cmd_buffer->state.index_type == indexType) {
2436 /* No state changes. */
2437 return;
2438 }
2439
2440 cmd_buffer->state.index_buffer = index_buffer;
2441 cmd_buffer->state.index_offset = offset;
2442 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2443 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2444 cmd_buffer->state.index_va += index_buffer->offset + offset;
2445
2446 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2447 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2448 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2449 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2450 }
2451
2452
2453 static void
2454 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2455 VkPipelineBindPoint bind_point,
2456 struct radv_descriptor_set *set, unsigned idx)
2457 {
2458 struct radeon_winsys *ws = cmd_buffer->device->ws;
2459
2460 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2461
2462 assert(set);
2463 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2464
2465 if (!cmd_buffer->device->use_global_bo_list) {
2466 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2467 if (set->descriptors[j])
2468 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2469 }
2470
2471 if(set->bo)
2472 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2473 }
2474
2475 void radv_CmdBindDescriptorSets(
2476 VkCommandBuffer commandBuffer,
2477 VkPipelineBindPoint pipelineBindPoint,
2478 VkPipelineLayout _layout,
2479 uint32_t firstSet,
2480 uint32_t descriptorSetCount,
2481 const VkDescriptorSet* pDescriptorSets,
2482 uint32_t dynamicOffsetCount,
2483 const uint32_t* pDynamicOffsets)
2484 {
2485 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2486 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2487 unsigned dyn_idx = 0;
2488
2489 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2490 struct radv_descriptor_state *descriptors_state =
2491 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2492
2493 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2494 unsigned idx = i + firstSet;
2495 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2496 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2497
2498 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2499 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2500 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2501 assert(dyn_idx < dynamicOffsetCount);
2502
2503 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2504 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2505 dst[0] = va;
2506 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2507 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2508 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2509 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2510 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2511 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2512 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2513 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2514 cmd_buffer->push_constant_stages |=
2515 set->layout->dynamic_shader_stages;
2516 }
2517 }
2518 }
2519
2520 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2521 struct radv_descriptor_set *set,
2522 struct radv_descriptor_set_layout *layout,
2523 VkPipelineBindPoint bind_point)
2524 {
2525 struct radv_descriptor_state *descriptors_state =
2526 radv_get_descriptors_state(cmd_buffer, bind_point);
2527 set->size = layout->size;
2528 set->layout = layout;
2529
2530 if (descriptors_state->push_set.capacity < set->size) {
2531 size_t new_size = MAX2(set->size, 1024);
2532 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2533 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2534
2535 free(set->mapped_ptr);
2536 set->mapped_ptr = malloc(new_size);
2537
2538 if (!set->mapped_ptr) {
2539 descriptors_state->push_set.capacity = 0;
2540 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2541 return false;
2542 }
2543
2544 descriptors_state->push_set.capacity = new_size;
2545 }
2546
2547 return true;
2548 }
2549
2550 void radv_meta_push_descriptor_set(
2551 struct radv_cmd_buffer* cmd_buffer,
2552 VkPipelineBindPoint pipelineBindPoint,
2553 VkPipelineLayout _layout,
2554 uint32_t set,
2555 uint32_t descriptorWriteCount,
2556 const VkWriteDescriptorSet* pDescriptorWrites)
2557 {
2558 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2559 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2560 unsigned bo_offset;
2561
2562 assert(set == 0);
2563 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2564
2565 push_set->size = layout->set[set].layout->size;
2566 push_set->layout = layout->set[set].layout;
2567
2568 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2569 &bo_offset,
2570 (void**) &push_set->mapped_ptr))
2571 return;
2572
2573 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2574 push_set->va += bo_offset;
2575
2576 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2577 radv_descriptor_set_to_handle(push_set),
2578 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2579
2580 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2581 }
2582
2583 void radv_CmdPushDescriptorSetKHR(
2584 VkCommandBuffer commandBuffer,
2585 VkPipelineBindPoint pipelineBindPoint,
2586 VkPipelineLayout _layout,
2587 uint32_t set,
2588 uint32_t descriptorWriteCount,
2589 const VkWriteDescriptorSet* pDescriptorWrites)
2590 {
2591 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2592 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2593 struct radv_descriptor_state *descriptors_state =
2594 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2595 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2596
2597 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2598
2599 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2600 layout->set[set].layout,
2601 pipelineBindPoint))
2602 return;
2603
2604 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2605 radv_descriptor_set_to_handle(push_set),
2606 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2607
2608 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2609 descriptors_state->push_dirty = true;
2610 }
2611
2612 void radv_CmdPushDescriptorSetWithTemplateKHR(
2613 VkCommandBuffer commandBuffer,
2614 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2615 VkPipelineLayout _layout,
2616 uint32_t set,
2617 const void* pData)
2618 {
2619 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2620 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2621 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2622 struct radv_descriptor_state *descriptors_state =
2623 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2624 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2625
2626 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2627
2628 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2629 layout->set[set].layout,
2630 templ->bind_point))
2631 return;
2632
2633 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2634 descriptorUpdateTemplate, pData);
2635
2636 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2637 descriptors_state->push_dirty = true;
2638 }
2639
2640 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2641 VkPipelineLayout layout,
2642 VkShaderStageFlags stageFlags,
2643 uint32_t offset,
2644 uint32_t size,
2645 const void* pValues)
2646 {
2647 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2648 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2649 cmd_buffer->push_constant_stages |= stageFlags;
2650 }
2651
2652 VkResult radv_EndCommandBuffer(
2653 VkCommandBuffer commandBuffer)
2654 {
2655 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2656
2657 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2658 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2659 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2660 si_emit_cache_flush(cmd_buffer);
2661 }
2662
2663 /* Make sure CP DMA is idle at the end of IBs because the kernel
2664 * doesn't wait for it.
2665 */
2666 si_cp_dma_wait_for_idle(cmd_buffer);
2667
2668 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2669
2670 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2671 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2672
2673 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2674
2675 return cmd_buffer->record_result;
2676 }
2677
2678 static void
2679 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2680 {
2681 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2682
2683 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2684 return;
2685
2686 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2687
2688 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2689 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2690
2691 cmd_buffer->compute_scratch_size_needed =
2692 MAX2(cmd_buffer->compute_scratch_size_needed,
2693 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2694
2695 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2696 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2697
2698 if (unlikely(cmd_buffer->device->trace_bo))
2699 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2700 }
2701
2702 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2703 VkPipelineBindPoint bind_point)
2704 {
2705 struct radv_descriptor_state *descriptors_state =
2706 radv_get_descriptors_state(cmd_buffer, bind_point);
2707
2708 descriptors_state->dirty |= descriptors_state->valid;
2709 }
2710
2711 void radv_CmdBindPipeline(
2712 VkCommandBuffer commandBuffer,
2713 VkPipelineBindPoint pipelineBindPoint,
2714 VkPipeline _pipeline)
2715 {
2716 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2717 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2718
2719 switch (pipelineBindPoint) {
2720 case VK_PIPELINE_BIND_POINT_COMPUTE:
2721 if (cmd_buffer->state.compute_pipeline == pipeline)
2722 return;
2723 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2724
2725 cmd_buffer->state.compute_pipeline = pipeline;
2726 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2727 break;
2728 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2729 if (cmd_buffer->state.pipeline == pipeline)
2730 return;
2731 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2732
2733 cmd_buffer->state.pipeline = pipeline;
2734 if (!pipeline)
2735 break;
2736
2737 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2738 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2739
2740 /* the new vertex shader might not have the same user regs */
2741 cmd_buffer->state.last_first_instance = -1;
2742 cmd_buffer->state.last_vertex_offset = -1;
2743
2744 /* Prefetch all pipeline shaders at first draw time. */
2745 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2746
2747 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2748
2749 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2750 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2751 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2752 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2753
2754 if (radv_pipeline_has_tess(pipeline))
2755 cmd_buffer->tess_rings_needed = true;
2756 break;
2757 default:
2758 assert(!"invalid bind point");
2759 break;
2760 }
2761 }
2762
2763 void radv_CmdSetViewport(
2764 VkCommandBuffer commandBuffer,
2765 uint32_t firstViewport,
2766 uint32_t viewportCount,
2767 const VkViewport* pViewports)
2768 {
2769 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2770 struct radv_cmd_state *state = &cmd_buffer->state;
2771 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2772
2773 assert(firstViewport < MAX_VIEWPORTS);
2774 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2775
2776 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2777 viewportCount * sizeof(*pViewports));
2778
2779 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2780 }
2781
2782 void radv_CmdSetScissor(
2783 VkCommandBuffer commandBuffer,
2784 uint32_t firstScissor,
2785 uint32_t scissorCount,
2786 const VkRect2D* pScissors)
2787 {
2788 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2789 struct radv_cmd_state *state = &cmd_buffer->state;
2790 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2791
2792 assert(firstScissor < MAX_SCISSORS);
2793 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2794
2795 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2796 scissorCount * sizeof(*pScissors));
2797
2798 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2799 }
2800
2801 void radv_CmdSetLineWidth(
2802 VkCommandBuffer commandBuffer,
2803 float lineWidth)
2804 {
2805 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2806 cmd_buffer->state.dynamic.line_width = lineWidth;
2807 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2808 }
2809
2810 void radv_CmdSetDepthBias(
2811 VkCommandBuffer commandBuffer,
2812 float depthBiasConstantFactor,
2813 float depthBiasClamp,
2814 float depthBiasSlopeFactor)
2815 {
2816 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2817
2818 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2819 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2820 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2821
2822 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2823 }
2824
2825 void radv_CmdSetBlendConstants(
2826 VkCommandBuffer commandBuffer,
2827 const float blendConstants[4])
2828 {
2829 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2830
2831 memcpy(cmd_buffer->state.dynamic.blend_constants,
2832 blendConstants, sizeof(float) * 4);
2833
2834 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2835 }
2836
2837 void radv_CmdSetDepthBounds(
2838 VkCommandBuffer commandBuffer,
2839 float minDepthBounds,
2840 float maxDepthBounds)
2841 {
2842 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2843
2844 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2845 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2846
2847 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2848 }
2849
2850 void radv_CmdSetStencilCompareMask(
2851 VkCommandBuffer commandBuffer,
2852 VkStencilFaceFlags faceMask,
2853 uint32_t compareMask)
2854 {
2855 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2856
2857 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2858 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2859 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2860 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2861
2862 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2863 }
2864
2865 void radv_CmdSetStencilWriteMask(
2866 VkCommandBuffer commandBuffer,
2867 VkStencilFaceFlags faceMask,
2868 uint32_t writeMask)
2869 {
2870 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2871
2872 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2873 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2874 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2875 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2876
2877 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2878 }
2879
2880 void radv_CmdSetStencilReference(
2881 VkCommandBuffer commandBuffer,
2882 VkStencilFaceFlags faceMask,
2883 uint32_t reference)
2884 {
2885 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2886
2887 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2888 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2889 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2890 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2891
2892 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2893 }
2894
2895 void radv_CmdSetDiscardRectangleEXT(
2896 VkCommandBuffer commandBuffer,
2897 uint32_t firstDiscardRectangle,
2898 uint32_t discardRectangleCount,
2899 const VkRect2D* pDiscardRectangles)
2900 {
2901 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2902 struct radv_cmd_state *state = &cmd_buffer->state;
2903 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2904
2905 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2906 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2907
2908 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2909 pDiscardRectangles, discardRectangleCount);
2910
2911 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2912 }
2913
2914 void radv_CmdExecuteCommands(
2915 VkCommandBuffer commandBuffer,
2916 uint32_t commandBufferCount,
2917 const VkCommandBuffer* pCmdBuffers)
2918 {
2919 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2920
2921 assert(commandBufferCount > 0);
2922
2923 /* Emit pending flushes on primary prior to executing secondary */
2924 si_emit_cache_flush(primary);
2925
2926 for (uint32_t i = 0; i < commandBufferCount; i++) {
2927 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2928
2929 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2930 secondary->scratch_size_needed);
2931 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2932 secondary->compute_scratch_size_needed);
2933
2934 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2935 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2936 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2937 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2938 if (secondary->tess_rings_needed)
2939 primary->tess_rings_needed = true;
2940 if (secondary->sample_positions_needed)
2941 primary->sample_positions_needed = true;
2942
2943 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2944
2945
2946 /* When the secondary command buffer is compute only we don't
2947 * need to re-emit the current graphics pipeline.
2948 */
2949 if (secondary->state.emitted_pipeline) {
2950 primary->state.emitted_pipeline =
2951 secondary->state.emitted_pipeline;
2952 }
2953
2954 /* When the secondary command buffer is graphics only we don't
2955 * need to re-emit the current compute pipeline.
2956 */
2957 if (secondary->state.emitted_compute_pipeline) {
2958 primary->state.emitted_compute_pipeline =
2959 secondary->state.emitted_compute_pipeline;
2960 }
2961
2962 /* Only re-emit the draw packets when needed. */
2963 if (secondary->state.last_primitive_reset_en != -1) {
2964 primary->state.last_primitive_reset_en =
2965 secondary->state.last_primitive_reset_en;
2966 }
2967
2968 if (secondary->state.last_primitive_reset_index) {
2969 primary->state.last_primitive_reset_index =
2970 secondary->state.last_primitive_reset_index;
2971 }
2972
2973 if (secondary->state.last_ia_multi_vgt_param) {
2974 primary->state.last_ia_multi_vgt_param =
2975 secondary->state.last_ia_multi_vgt_param;
2976 }
2977
2978 primary->state.last_first_instance = secondary->state.last_first_instance;
2979 primary->state.last_num_instances = secondary->state.last_num_instances;
2980 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2981
2982 if (secondary->state.last_index_type != -1) {
2983 primary->state.last_index_type =
2984 secondary->state.last_index_type;
2985 }
2986 }
2987
2988 /* After executing commands from secondary buffers we have to dirty
2989 * some states.
2990 */
2991 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2992 RADV_CMD_DIRTY_INDEX_BUFFER |
2993 RADV_CMD_DIRTY_DYNAMIC_ALL;
2994 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2995 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2996 }
2997
2998 VkResult radv_CreateCommandPool(
2999 VkDevice _device,
3000 const VkCommandPoolCreateInfo* pCreateInfo,
3001 const VkAllocationCallbacks* pAllocator,
3002 VkCommandPool* pCmdPool)
3003 {
3004 RADV_FROM_HANDLE(radv_device, device, _device);
3005 struct radv_cmd_pool *pool;
3006
3007 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3008 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3009 if (pool == NULL)
3010 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3011
3012 if (pAllocator)
3013 pool->alloc = *pAllocator;
3014 else
3015 pool->alloc = device->alloc;
3016
3017 list_inithead(&pool->cmd_buffers);
3018 list_inithead(&pool->free_cmd_buffers);
3019
3020 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3021
3022 *pCmdPool = radv_cmd_pool_to_handle(pool);
3023
3024 return VK_SUCCESS;
3025
3026 }
3027
3028 void radv_DestroyCommandPool(
3029 VkDevice _device,
3030 VkCommandPool commandPool,
3031 const VkAllocationCallbacks* pAllocator)
3032 {
3033 RADV_FROM_HANDLE(radv_device, device, _device);
3034 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3035
3036 if (!pool)
3037 return;
3038
3039 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3040 &pool->cmd_buffers, pool_link) {
3041 radv_cmd_buffer_destroy(cmd_buffer);
3042 }
3043
3044 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3045 &pool->free_cmd_buffers, pool_link) {
3046 radv_cmd_buffer_destroy(cmd_buffer);
3047 }
3048
3049 vk_free2(&device->alloc, pAllocator, pool);
3050 }
3051
3052 VkResult radv_ResetCommandPool(
3053 VkDevice device,
3054 VkCommandPool commandPool,
3055 VkCommandPoolResetFlags flags)
3056 {
3057 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3058 VkResult result;
3059
3060 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3061 &pool->cmd_buffers, pool_link) {
3062 result = radv_reset_cmd_buffer(cmd_buffer);
3063 if (result != VK_SUCCESS)
3064 return result;
3065 }
3066
3067 return VK_SUCCESS;
3068 }
3069
3070 void radv_TrimCommandPool(
3071 VkDevice device,
3072 VkCommandPool commandPool,
3073 VkCommandPoolTrimFlagsKHR flags)
3074 {
3075 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3076
3077 if (!pool)
3078 return;
3079
3080 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3081 &pool->free_cmd_buffers, pool_link) {
3082 radv_cmd_buffer_destroy(cmd_buffer);
3083 }
3084 }
3085
3086 void radv_CmdBeginRenderPass(
3087 VkCommandBuffer commandBuffer,
3088 const VkRenderPassBeginInfo* pRenderPassBegin,
3089 VkSubpassContents contents)
3090 {
3091 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3092 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3093 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3094
3095 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3096 cmd_buffer->cs, 2048);
3097 MAYBE_UNUSED VkResult result;
3098
3099 cmd_buffer->state.framebuffer = framebuffer;
3100 cmd_buffer->state.pass = pass;
3101 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3102
3103 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3104 if (result != VK_SUCCESS)
3105 return;
3106
3107 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3108 assert(cmd_buffer->cs->cdw <= cdw_max);
3109
3110 radv_cmd_buffer_clear_subpass(cmd_buffer);
3111 }
3112
3113 void radv_CmdBeginRenderPass2KHR(
3114 VkCommandBuffer commandBuffer,
3115 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3116 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3117 {
3118 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3119 pSubpassBeginInfo->contents);
3120 }
3121
3122 void radv_CmdNextSubpass(
3123 VkCommandBuffer commandBuffer,
3124 VkSubpassContents contents)
3125 {
3126 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3127
3128 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3129
3130 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3131 2048);
3132
3133 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3134 radv_cmd_buffer_clear_subpass(cmd_buffer);
3135 }
3136
3137 void radv_CmdNextSubpass2KHR(
3138 VkCommandBuffer commandBuffer,
3139 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3140 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3141 {
3142 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3143 }
3144
3145 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3146 {
3147 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3148 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3149 if (!radv_get_shader(pipeline, stage))
3150 continue;
3151
3152 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3153 if (loc->sgpr_idx == -1)
3154 continue;
3155 uint32_t base_reg = pipeline->user_data_0[stage];
3156 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3157
3158 }
3159 if (pipeline->gs_copy_shader) {
3160 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3161 if (loc->sgpr_idx != -1) {
3162 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3163 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3164 }
3165 }
3166 }
3167
3168 static void
3169 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3170 uint32_t vertex_count)
3171 {
3172 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3173 radeon_emit(cmd_buffer->cs, vertex_count);
3174 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3175 S_0287F0_USE_OPAQUE(0));
3176 }
3177
3178 static void
3179 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3180 uint64_t index_va,
3181 uint32_t index_count)
3182 {
3183 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3184 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3185 radeon_emit(cmd_buffer->cs, index_va);
3186 radeon_emit(cmd_buffer->cs, index_va >> 32);
3187 radeon_emit(cmd_buffer->cs, index_count);
3188 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3189 }
3190
3191 static void
3192 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3193 bool indexed,
3194 uint32_t draw_count,
3195 uint64_t count_va,
3196 uint32_t stride)
3197 {
3198 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3199 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3200 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3201 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3202 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3203 bool predicating = cmd_buffer->state.predicating;
3204 assert(base_reg);
3205
3206 /* just reset draw state for vertex data */
3207 cmd_buffer->state.last_first_instance = -1;
3208 cmd_buffer->state.last_num_instances = -1;
3209 cmd_buffer->state.last_vertex_offset = -1;
3210
3211 if (draw_count == 1 && !count_va && !draw_id_enable) {
3212 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3213 PKT3_DRAW_INDIRECT, 3, predicating));
3214 radeon_emit(cs, 0);
3215 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3216 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3217 radeon_emit(cs, di_src_sel);
3218 } else {
3219 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3220 PKT3_DRAW_INDIRECT_MULTI,
3221 8, predicating));
3222 radeon_emit(cs, 0);
3223 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3224 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3225 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3226 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3227 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3228 radeon_emit(cs, draw_count); /* count */
3229 radeon_emit(cs, count_va); /* count_addr */
3230 radeon_emit(cs, count_va >> 32);
3231 radeon_emit(cs, stride); /* stride */
3232 radeon_emit(cs, di_src_sel);
3233 }
3234 }
3235
3236 struct radv_draw_info {
3237 /**
3238 * Number of vertices.
3239 */
3240 uint32_t count;
3241
3242 /**
3243 * Index of the first vertex.
3244 */
3245 int32_t vertex_offset;
3246
3247 /**
3248 * First instance id.
3249 */
3250 uint32_t first_instance;
3251
3252 /**
3253 * Number of instances.
3254 */
3255 uint32_t instance_count;
3256
3257 /**
3258 * First index (indexed draws only).
3259 */
3260 uint32_t first_index;
3261
3262 /**
3263 * Whether it's an indexed draw.
3264 */
3265 bool indexed;
3266
3267 /**
3268 * Indirect draw parameters resource.
3269 */
3270 struct radv_buffer *indirect;
3271 uint64_t indirect_offset;
3272 uint32_t stride;
3273
3274 /**
3275 * Draw count parameters resource.
3276 */
3277 struct radv_buffer *count_buffer;
3278 uint64_t count_buffer_offset;
3279 };
3280
3281 static void
3282 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3283 const struct radv_draw_info *info)
3284 {
3285 struct radv_cmd_state *state = &cmd_buffer->state;
3286 struct radeon_winsys *ws = cmd_buffer->device->ws;
3287 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3288
3289 if (info->indirect) {
3290 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3291 uint64_t count_va = 0;
3292
3293 va += info->indirect->offset + info->indirect_offset;
3294
3295 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3296
3297 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3298 radeon_emit(cs, 1);
3299 radeon_emit(cs, va);
3300 radeon_emit(cs, va >> 32);
3301
3302 if (info->count_buffer) {
3303 count_va = radv_buffer_get_va(info->count_buffer->bo);
3304 count_va += info->count_buffer->offset +
3305 info->count_buffer_offset;
3306
3307 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3308 }
3309
3310 if (!state->subpass->view_mask) {
3311 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3312 info->indexed,
3313 info->count,
3314 count_va,
3315 info->stride);
3316 } else {
3317 unsigned i;
3318 for_each_bit(i, state->subpass->view_mask) {
3319 radv_emit_view_index(cmd_buffer, i);
3320
3321 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3322 info->indexed,
3323 info->count,
3324 count_va,
3325 info->stride);
3326 }
3327 }
3328 } else {
3329 assert(state->pipeline->graphics.vtx_base_sgpr);
3330
3331 if (info->vertex_offset != state->last_vertex_offset ||
3332 info->first_instance != state->last_first_instance) {
3333 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3334 state->pipeline->graphics.vtx_emit_num);
3335
3336 radeon_emit(cs, info->vertex_offset);
3337 radeon_emit(cs, info->first_instance);
3338 if (state->pipeline->graphics.vtx_emit_num == 3)
3339 radeon_emit(cs, 0);
3340 state->last_first_instance = info->first_instance;
3341 state->last_vertex_offset = info->vertex_offset;
3342 }
3343
3344 if (state->last_num_instances != info->instance_count) {
3345 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3346 radeon_emit(cs, info->instance_count);
3347 state->last_num_instances = info->instance_count;
3348 }
3349
3350 if (info->indexed) {
3351 int index_size = state->index_type ? 4 : 2;
3352 uint64_t index_va;
3353
3354 index_va = state->index_va;
3355 index_va += info->first_index * index_size;
3356
3357 if (!state->subpass->view_mask) {
3358 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3359 index_va,
3360 info->count);
3361 } else {
3362 unsigned i;
3363 for_each_bit(i, state->subpass->view_mask) {
3364 radv_emit_view_index(cmd_buffer, i);
3365
3366 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3367 index_va,
3368 info->count);
3369 }
3370 }
3371 } else {
3372 if (!state->subpass->view_mask) {
3373 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3374 } else {
3375 unsigned i;
3376 for_each_bit(i, state->subpass->view_mask) {
3377 radv_emit_view_index(cmd_buffer, i);
3378
3379 radv_cs_emit_draw_packet(cmd_buffer,
3380 info->count);
3381 }
3382 }
3383 }
3384 }
3385 }
3386
3387 /*
3388 * Vega and raven have a bug which triggers if there are multiple context
3389 * register contexts active at the same time with different scissor values.
3390 *
3391 * There are two possible workarounds:
3392 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3393 * there is only ever 1 active set of scissor values at the same time.
3394 *
3395 * 2) Whenever the hardware switches contexts we have to set the scissor
3396 * registers again even if it is a noop. That way the new context gets
3397 * the correct scissor values.
3398 *
3399 * This implements option 2. radv_need_late_scissor_emission needs to
3400 * return true on affected HW if radv_emit_all_graphics_states sets
3401 * any context registers.
3402 */
3403 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3404 bool indexed_draw)
3405 {
3406 struct radv_cmd_state *state = &cmd_buffer->state;
3407
3408 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3409 return false;
3410
3411 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3412
3413 /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3414 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_VERTEX_BUFFER | RADV_CMD_DIRTY_PIPELINE);
3415
3416 /* Assume all state changes except these two can imply context rolls. */
3417 if (cmd_buffer->state.dirty & used_states)
3418 return true;
3419
3420 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3421 return true;
3422
3423 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3424 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3425 return true;
3426
3427 return false;
3428 }
3429
3430 static void
3431 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3432 const struct radv_draw_info *info)
3433 {
3434 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3435
3436 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3437 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3438 radv_emit_rbplus_state(cmd_buffer);
3439
3440 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3441 radv_emit_graphics_pipeline(cmd_buffer);
3442
3443 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3444 radv_emit_framebuffer_state(cmd_buffer);
3445
3446 if (info->indexed) {
3447 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3448 radv_emit_index_buffer(cmd_buffer);
3449 } else {
3450 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3451 * so the state must be re-emitted before the next indexed
3452 * draw.
3453 */
3454 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3455 cmd_buffer->state.last_index_type = -1;
3456 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3457 }
3458 }
3459
3460 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3461
3462 radv_emit_draw_registers(cmd_buffer, info->indexed,
3463 info->instance_count > 1, info->indirect,
3464 info->indirect ? 0 : info->count);
3465
3466 if (late_scissor_emission)
3467 radv_emit_scissor(cmd_buffer);
3468 }
3469
3470 static void
3471 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3472 const struct radv_draw_info *info)
3473 {
3474 bool has_prefetch =
3475 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3476 bool pipeline_is_dirty =
3477 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3478 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3479
3480 MAYBE_UNUSED unsigned cdw_max =
3481 radeon_check_space(cmd_buffer->device->ws,
3482 cmd_buffer->cs, 4096);
3483
3484 /* Use optimal packet order based on whether we need to sync the
3485 * pipeline.
3486 */
3487 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3488 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3489 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3490 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3491 /* If we have to wait for idle, set all states first, so that
3492 * all SET packets are processed in parallel with previous draw
3493 * calls. Then upload descriptors, set shader pointers, and
3494 * draw, and prefetch at the end. This ensures that the time
3495 * the CUs are idle is very short. (there are only SET_SH
3496 * packets between the wait and the draw)
3497 */
3498 radv_emit_all_graphics_states(cmd_buffer, info);
3499 si_emit_cache_flush(cmd_buffer);
3500 /* <-- CUs are idle here --> */
3501
3502 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3503
3504 radv_emit_draw_packets(cmd_buffer, info);
3505 /* <-- CUs are busy here --> */
3506
3507 /* Start prefetches after the draw has been started. Both will
3508 * run in parallel, but starting the draw first is more
3509 * important.
3510 */
3511 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3512 radv_emit_prefetch_L2(cmd_buffer,
3513 cmd_buffer->state.pipeline, false);
3514 }
3515 } else {
3516 /* If we don't wait for idle, start prefetches first, then set
3517 * states, and draw at the end.
3518 */
3519 si_emit_cache_flush(cmd_buffer);
3520
3521 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3522 /* Only prefetch the vertex shader and VBO descriptors
3523 * in order to start the draw as soon as possible.
3524 */
3525 radv_emit_prefetch_L2(cmd_buffer,
3526 cmd_buffer->state.pipeline, true);
3527 }
3528
3529 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3530
3531 radv_emit_all_graphics_states(cmd_buffer, info);
3532 radv_emit_draw_packets(cmd_buffer, info);
3533
3534 /* Prefetch the remaining shaders after the draw has been
3535 * started.
3536 */
3537 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3538 radv_emit_prefetch_L2(cmd_buffer,
3539 cmd_buffer->state.pipeline, false);
3540 }
3541 }
3542
3543 assert(cmd_buffer->cs->cdw <= cdw_max);
3544 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3545 }
3546
3547 void radv_CmdDraw(
3548 VkCommandBuffer commandBuffer,
3549 uint32_t vertexCount,
3550 uint32_t instanceCount,
3551 uint32_t firstVertex,
3552 uint32_t firstInstance)
3553 {
3554 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3555 struct radv_draw_info info = {};
3556
3557 info.count = vertexCount;
3558 info.instance_count = instanceCount;
3559 info.first_instance = firstInstance;
3560 info.vertex_offset = firstVertex;
3561
3562 radv_draw(cmd_buffer, &info);
3563 }
3564
3565 void radv_CmdDrawIndexed(
3566 VkCommandBuffer commandBuffer,
3567 uint32_t indexCount,
3568 uint32_t instanceCount,
3569 uint32_t firstIndex,
3570 int32_t vertexOffset,
3571 uint32_t firstInstance)
3572 {
3573 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3574 struct radv_draw_info info = {};
3575
3576 info.indexed = true;
3577 info.count = indexCount;
3578 info.instance_count = instanceCount;
3579 info.first_index = firstIndex;
3580 info.vertex_offset = vertexOffset;
3581 info.first_instance = firstInstance;
3582
3583 radv_draw(cmd_buffer, &info);
3584 }
3585
3586 void radv_CmdDrawIndirect(
3587 VkCommandBuffer commandBuffer,
3588 VkBuffer _buffer,
3589 VkDeviceSize offset,
3590 uint32_t drawCount,
3591 uint32_t stride)
3592 {
3593 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3594 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3595 struct radv_draw_info info = {};
3596
3597 info.count = drawCount;
3598 info.indirect = buffer;
3599 info.indirect_offset = offset;
3600 info.stride = stride;
3601
3602 radv_draw(cmd_buffer, &info);
3603 }
3604
3605 void radv_CmdDrawIndexedIndirect(
3606 VkCommandBuffer commandBuffer,
3607 VkBuffer _buffer,
3608 VkDeviceSize offset,
3609 uint32_t drawCount,
3610 uint32_t stride)
3611 {
3612 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3613 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3614 struct radv_draw_info info = {};
3615
3616 info.indexed = true;
3617 info.count = drawCount;
3618 info.indirect = buffer;
3619 info.indirect_offset = offset;
3620 info.stride = stride;
3621
3622 radv_draw(cmd_buffer, &info);
3623 }
3624
3625 void radv_CmdDrawIndirectCountAMD(
3626 VkCommandBuffer commandBuffer,
3627 VkBuffer _buffer,
3628 VkDeviceSize offset,
3629 VkBuffer _countBuffer,
3630 VkDeviceSize countBufferOffset,
3631 uint32_t maxDrawCount,
3632 uint32_t stride)
3633 {
3634 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3635 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3636 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3637 struct radv_draw_info info = {};
3638
3639 info.count = maxDrawCount;
3640 info.indirect = buffer;
3641 info.indirect_offset = offset;
3642 info.count_buffer = count_buffer;
3643 info.count_buffer_offset = countBufferOffset;
3644 info.stride = stride;
3645
3646 radv_draw(cmd_buffer, &info);
3647 }
3648
3649 void radv_CmdDrawIndexedIndirectCountAMD(
3650 VkCommandBuffer commandBuffer,
3651 VkBuffer _buffer,
3652 VkDeviceSize offset,
3653 VkBuffer _countBuffer,
3654 VkDeviceSize countBufferOffset,
3655 uint32_t maxDrawCount,
3656 uint32_t stride)
3657 {
3658 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3659 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3660 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3661 struct radv_draw_info info = {};
3662
3663 info.indexed = true;
3664 info.count = maxDrawCount;
3665 info.indirect = buffer;
3666 info.indirect_offset = offset;
3667 info.count_buffer = count_buffer;
3668 info.count_buffer_offset = countBufferOffset;
3669 info.stride = stride;
3670
3671 radv_draw(cmd_buffer, &info);
3672 }
3673
3674 void radv_CmdDrawIndirectCountKHR(
3675 VkCommandBuffer commandBuffer,
3676 VkBuffer _buffer,
3677 VkDeviceSize offset,
3678 VkBuffer _countBuffer,
3679 VkDeviceSize countBufferOffset,
3680 uint32_t maxDrawCount,
3681 uint32_t stride)
3682 {
3683 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3684 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3685 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3686 struct radv_draw_info info = {};
3687
3688 info.count = maxDrawCount;
3689 info.indirect = buffer;
3690 info.indirect_offset = offset;
3691 info.count_buffer = count_buffer;
3692 info.count_buffer_offset = countBufferOffset;
3693 info.stride = stride;
3694
3695 radv_draw(cmd_buffer, &info);
3696 }
3697
3698 void radv_CmdDrawIndexedIndirectCountKHR(
3699 VkCommandBuffer commandBuffer,
3700 VkBuffer _buffer,
3701 VkDeviceSize offset,
3702 VkBuffer _countBuffer,
3703 VkDeviceSize countBufferOffset,
3704 uint32_t maxDrawCount,
3705 uint32_t stride)
3706 {
3707 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3708 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3709 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3710 struct radv_draw_info info = {};
3711
3712 info.indexed = true;
3713 info.count = maxDrawCount;
3714 info.indirect = buffer;
3715 info.indirect_offset = offset;
3716 info.count_buffer = count_buffer;
3717 info.count_buffer_offset = countBufferOffset;
3718 info.stride = stride;
3719
3720 radv_draw(cmd_buffer, &info);
3721 }
3722
3723 struct radv_dispatch_info {
3724 /**
3725 * Determine the layout of the grid (in block units) to be used.
3726 */
3727 uint32_t blocks[3];
3728
3729 /**
3730 * A starting offset for the grid. If unaligned is set, the offset
3731 * must still be aligned.
3732 */
3733 uint32_t offsets[3];
3734 /**
3735 * Whether it's an unaligned compute dispatch.
3736 */
3737 bool unaligned;
3738
3739 /**
3740 * Indirect compute parameters resource.
3741 */
3742 struct radv_buffer *indirect;
3743 uint64_t indirect_offset;
3744 };
3745
3746 static void
3747 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3748 const struct radv_dispatch_info *info)
3749 {
3750 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3751 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3752 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3753 struct radeon_winsys *ws = cmd_buffer->device->ws;
3754 bool predicating = cmd_buffer->state.predicating;
3755 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3756 struct radv_userdata_info *loc;
3757
3758 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3759 AC_UD_CS_GRID_SIZE);
3760
3761 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3762
3763 if (info->indirect) {
3764 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3765
3766 va += info->indirect->offset + info->indirect_offset;
3767
3768 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3769
3770 if (loc->sgpr_idx != -1) {
3771 for (unsigned i = 0; i < 3; ++i) {
3772 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3773 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3774 COPY_DATA_DST_SEL(COPY_DATA_REG));
3775 radeon_emit(cs, (va + 4 * i));
3776 radeon_emit(cs, (va + 4 * i) >> 32);
3777 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3778 + loc->sgpr_idx * 4) >> 2) + i);
3779 radeon_emit(cs, 0);
3780 }
3781 }
3782
3783 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3784 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
3785 PKT3_SHADER_TYPE_S(1));
3786 radeon_emit(cs, va);
3787 radeon_emit(cs, va >> 32);
3788 radeon_emit(cs, dispatch_initiator);
3789 } else {
3790 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3791 PKT3_SHADER_TYPE_S(1));
3792 radeon_emit(cs, 1);
3793 radeon_emit(cs, va);
3794 radeon_emit(cs, va >> 32);
3795
3796 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
3797 PKT3_SHADER_TYPE_S(1));
3798 radeon_emit(cs, 0);
3799 radeon_emit(cs, dispatch_initiator);
3800 }
3801 } else {
3802 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3803 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3804
3805 if (info->unaligned) {
3806 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3807 unsigned remainder[3];
3808
3809 /* If aligned, these should be an entire block size,
3810 * not 0.
3811 */
3812 remainder[0] = blocks[0] + cs_block_size[0] -
3813 align_u32_npot(blocks[0], cs_block_size[0]);
3814 remainder[1] = blocks[1] + cs_block_size[1] -
3815 align_u32_npot(blocks[1], cs_block_size[1]);
3816 remainder[2] = blocks[2] + cs_block_size[2] -
3817 align_u32_npot(blocks[2], cs_block_size[2]);
3818
3819 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3820 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3821 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3822
3823 for(unsigned i = 0; i < 3; ++i) {
3824 assert(offsets[i] % cs_block_size[i] == 0);
3825 offsets[i] /= cs_block_size[i];
3826 }
3827
3828 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3829 radeon_emit(cs,
3830 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3831 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3832 radeon_emit(cs,
3833 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3834 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3835 radeon_emit(cs,
3836 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3837 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3838
3839 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3840 }
3841
3842 if (loc->sgpr_idx != -1) {
3843 assert(!loc->indirect);
3844 assert(loc->num_sgprs == 3);
3845
3846 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3847 loc->sgpr_idx * 4, 3);
3848 radeon_emit(cs, blocks[0]);
3849 radeon_emit(cs, blocks[1]);
3850 radeon_emit(cs, blocks[2]);
3851 }
3852
3853 if (offsets[0] || offsets[1] || offsets[2]) {
3854 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3855 radeon_emit(cs, offsets[0]);
3856 radeon_emit(cs, offsets[1]);
3857 radeon_emit(cs, offsets[2]);
3858
3859 /* The blocks in the packet are not counts but end values. */
3860 for (unsigned i = 0; i < 3; ++i)
3861 blocks[i] += offsets[i];
3862 } else {
3863 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3864 }
3865
3866 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
3867 PKT3_SHADER_TYPE_S(1));
3868 radeon_emit(cs, blocks[0]);
3869 radeon_emit(cs, blocks[1]);
3870 radeon_emit(cs, blocks[2]);
3871 radeon_emit(cs, dispatch_initiator);
3872 }
3873
3874 assert(cmd_buffer->cs->cdw <= cdw_max);
3875 }
3876
3877 static void
3878 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3879 {
3880 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3881 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3882 }
3883
3884 static void
3885 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3886 const struct radv_dispatch_info *info)
3887 {
3888 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3889 bool has_prefetch =
3890 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3891 bool pipeline_is_dirty = pipeline &&
3892 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3893
3894 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3895 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3896 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3897 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3898 /* If we have to wait for idle, set all states first, so that
3899 * all SET packets are processed in parallel with previous draw
3900 * calls. Then upload descriptors, set shader pointers, and
3901 * dispatch, and prefetch at the end. This ensures that the
3902 * time the CUs are idle is very short. (there are only SET_SH
3903 * packets between the wait and the draw)
3904 */
3905 radv_emit_compute_pipeline(cmd_buffer);
3906 si_emit_cache_flush(cmd_buffer);
3907 /* <-- CUs are idle here --> */
3908
3909 radv_upload_compute_shader_descriptors(cmd_buffer);
3910
3911 radv_emit_dispatch_packets(cmd_buffer, info);
3912 /* <-- CUs are busy here --> */
3913
3914 /* Start prefetches after the dispatch has been started. Both
3915 * will run in parallel, but starting the dispatch first is
3916 * more important.
3917 */
3918 if (has_prefetch && pipeline_is_dirty) {
3919 radv_emit_shader_prefetch(cmd_buffer,
3920 pipeline->shaders[MESA_SHADER_COMPUTE]);
3921 }
3922 } else {
3923 /* If we don't wait for idle, start prefetches first, then set
3924 * states, and dispatch at the end.
3925 */
3926 si_emit_cache_flush(cmd_buffer);
3927
3928 if (has_prefetch && pipeline_is_dirty) {
3929 radv_emit_shader_prefetch(cmd_buffer,
3930 pipeline->shaders[MESA_SHADER_COMPUTE]);
3931 }
3932
3933 radv_upload_compute_shader_descriptors(cmd_buffer);
3934
3935 radv_emit_compute_pipeline(cmd_buffer);
3936 radv_emit_dispatch_packets(cmd_buffer, info);
3937 }
3938
3939 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3940 }
3941
3942 void radv_CmdDispatchBase(
3943 VkCommandBuffer commandBuffer,
3944 uint32_t base_x,
3945 uint32_t base_y,
3946 uint32_t base_z,
3947 uint32_t x,
3948 uint32_t y,
3949 uint32_t z)
3950 {
3951 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3952 struct radv_dispatch_info info = {};
3953
3954 info.blocks[0] = x;
3955 info.blocks[1] = y;
3956 info.blocks[2] = z;
3957
3958 info.offsets[0] = base_x;
3959 info.offsets[1] = base_y;
3960 info.offsets[2] = base_z;
3961 radv_dispatch(cmd_buffer, &info);
3962 }
3963
3964 void radv_CmdDispatch(
3965 VkCommandBuffer commandBuffer,
3966 uint32_t x,
3967 uint32_t y,
3968 uint32_t z)
3969 {
3970 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3971 }
3972
3973 void radv_CmdDispatchIndirect(
3974 VkCommandBuffer commandBuffer,
3975 VkBuffer _buffer,
3976 VkDeviceSize offset)
3977 {
3978 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3979 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3980 struct radv_dispatch_info info = {};
3981
3982 info.indirect = buffer;
3983 info.indirect_offset = offset;
3984
3985 radv_dispatch(cmd_buffer, &info);
3986 }
3987
3988 void radv_unaligned_dispatch(
3989 struct radv_cmd_buffer *cmd_buffer,
3990 uint32_t x,
3991 uint32_t y,
3992 uint32_t z)
3993 {
3994 struct radv_dispatch_info info = {};
3995
3996 info.blocks[0] = x;
3997 info.blocks[1] = y;
3998 info.blocks[2] = z;
3999 info.unaligned = 1;
4000
4001 radv_dispatch(cmd_buffer, &info);
4002 }
4003
4004 void radv_CmdEndRenderPass(
4005 VkCommandBuffer commandBuffer)
4006 {
4007 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4008
4009 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4010
4011 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4012
4013 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4014 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4015 radv_handle_subpass_image_transition(cmd_buffer,
4016 (struct radv_subpass_attachment){i, layout});
4017 }
4018
4019 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4020
4021 cmd_buffer->state.pass = NULL;
4022 cmd_buffer->state.subpass = NULL;
4023 cmd_buffer->state.attachments = NULL;
4024 cmd_buffer->state.framebuffer = NULL;
4025 }
4026
4027 void radv_CmdEndRenderPass2KHR(
4028 VkCommandBuffer commandBuffer,
4029 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4030 {
4031 radv_CmdEndRenderPass(commandBuffer);
4032 }
4033
4034 /*
4035 * For HTILE we have the following interesting clear words:
4036 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4037 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4038 * 0xfffffff0: Clear depth to 1.0
4039 * 0x00000000: Clear depth to 0.0
4040 */
4041 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4042 struct radv_image *image,
4043 const VkImageSubresourceRange *range,
4044 uint32_t clear_word)
4045 {
4046 assert(range->baseMipLevel == 0);
4047 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4048 unsigned layer_count = radv_get_layerCount(image, range);
4049 uint64_t size = image->surface.htile_slice_size * layer_count;
4050 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4051 uint64_t offset = image->offset + image->htile_offset +
4052 image->surface.htile_slice_size * range->baseArrayLayer;
4053 struct radv_cmd_state *state = &cmd_buffer->state;
4054 VkClearDepthStencilValue value = {};
4055
4056 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4057 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4058
4059 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4060 size, clear_word);
4061
4062 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4063
4064 if (vk_format_is_stencil(image->vk_format))
4065 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4066
4067 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4068 }
4069
4070 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4071 struct radv_image *image,
4072 VkImageLayout src_layout,
4073 VkImageLayout dst_layout,
4074 unsigned src_queue_mask,
4075 unsigned dst_queue_mask,
4076 const VkImageSubresourceRange *range,
4077 VkImageAspectFlags pending_clears)
4078 {
4079 if (!radv_image_has_htile(image))
4080 return;
4081
4082 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4083 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4084 /* TODO: merge with the clear if applicable */
4085 radv_initialize_htile(cmd_buffer, image, range, 0);
4086 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4087 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4088 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4089 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4090 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4091 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4092 VkImageSubresourceRange local_range = *range;
4093 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4094 local_range.baseMipLevel = 0;
4095 local_range.levelCount = 1;
4096
4097 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4098 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4099
4100 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4101
4102 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4103 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4104 }
4105 }
4106
4107 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4108 struct radv_image *image, uint32_t value)
4109 {
4110 struct radv_cmd_state *state = &cmd_buffer->state;
4111
4112 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4113 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4114
4115 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4116
4117 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4118 }
4119
4120 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4121 struct radv_image *image, uint32_t value)
4122 {
4123 struct radv_cmd_state *state = &cmd_buffer->state;
4124
4125 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4126 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4127
4128 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4129
4130 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4131 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4132 }
4133
4134 /**
4135 * Initialize DCC/FMASK/CMASK metadata for a color image.
4136 */
4137 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4138 struct radv_image *image,
4139 VkImageLayout src_layout,
4140 VkImageLayout dst_layout,
4141 unsigned src_queue_mask,
4142 unsigned dst_queue_mask)
4143 {
4144 if (radv_image_has_cmask(image)) {
4145 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4146
4147 /* TODO: clarify this. */
4148 if (radv_image_has_fmask(image)) {
4149 value = 0xccccccccu;
4150 }
4151
4152 radv_initialise_cmask(cmd_buffer, image, value);
4153 }
4154
4155 if (radv_image_has_dcc(image)) {
4156 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4157 bool need_decompress_pass = false;
4158
4159 if (radv_layout_dcc_compressed(image, dst_layout,
4160 dst_queue_mask)) {
4161 value = 0x20202020u;
4162 need_decompress_pass = true;
4163 }
4164
4165 radv_initialize_dcc(cmd_buffer, image, value);
4166
4167 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image,
4168 need_decompress_pass);
4169 }
4170
4171 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4172 uint32_t color_values[2] = {};
4173 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4174 }
4175 }
4176
4177 /**
4178 * Handle color image transitions for DCC/FMASK/CMASK.
4179 */
4180 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4181 struct radv_image *image,
4182 VkImageLayout src_layout,
4183 VkImageLayout dst_layout,
4184 unsigned src_queue_mask,
4185 unsigned dst_queue_mask,
4186 const VkImageSubresourceRange *range)
4187 {
4188 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4189 radv_init_color_image_metadata(cmd_buffer, image,
4190 src_layout, dst_layout,
4191 src_queue_mask, dst_queue_mask);
4192 return;
4193 }
4194
4195 if (radv_image_has_dcc(image)) {
4196 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4197 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4198 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4199 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4200 radv_decompress_dcc(cmd_buffer, image, range);
4201 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4202 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4203 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4204 }
4205 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4206 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4207 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4208 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4209 }
4210 }
4211 }
4212
4213 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4214 struct radv_image *image,
4215 VkImageLayout src_layout,
4216 VkImageLayout dst_layout,
4217 uint32_t src_family,
4218 uint32_t dst_family,
4219 const VkImageSubresourceRange *range,
4220 VkImageAspectFlags pending_clears)
4221 {
4222 if (image->exclusive && src_family != dst_family) {
4223 /* This is an acquire or a release operation and there will be
4224 * a corresponding release/acquire. Do the transition in the
4225 * most flexible queue. */
4226
4227 assert(src_family == cmd_buffer->queue_family_index ||
4228 dst_family == cmd_buffer->queue_family_index);
4229
4230 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4231 return;
4232
4233 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4234 (src_family == RADV_QUEUE_GENERAL ||
4235 dst_family == RADV_QUEUE_GENERAL))
4236 return;
4237 }
4238
4239 unsigned src_queue_mask =
4240 radv_image_queue_family_mask(image, src_family,
4241 cmd_buffer->queue_family_index);
4242 unsigned dst_queue_mask =
4243 radv_image_queue_family_mask(image, dst_family,
4244 cmd_buffer->queue_family_index);
4245
4246 if (vk_format_is_depth(image->vk_format)) {
4247 radv_handle_depth_image_transition(cmd_buffer, image,
4248 src_layout, dst_layout,
4249 src_queue_mask, dst_queue_mask,
4250 range, pending_clears);
4251 } else {
4252 radv_handle_color_image_transition(cmd_buffer, image,
4253 src_layout, dst_layout,
4254 src_queue_mask, dst_queue_mask,
4255 range);
4256 }
4257 }
4258
4259 struct radv_barrier_info {
4260 uint32_t eventCount;
4261 const VkEvent *pEvents;
4262 VkPipelineStageFlags srcStageMask;
4263 };
4264
4265 static void
4266 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4267 uint32_t memoryBarrierCount,
4268 const VkMemoryBarrier *pMemoryBarriers,
4269 uint32_t bufferMemoryBarrierCount,
4270 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4271 uint32_t imageMemoryBarrierCount,
4272 const VkImageMemoryBarrier *pImageMemoryBarriers,
4273 const struct radv_barrier_info *info)
4274 {
4275 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4276 enum radv_cmd_flush_bits src_flush_bits = 0;
4277 enum radv_cmd_flush_bits dst_flush_bits = 0;
4278
4279 for (unsigned i = 0; i < info->eventCount; ++i) {
4280 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4281 uint64_t va = radv_buffer_get_va(event->bo);
4282
4283 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4284
4285 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4286
4287 si_emit_wait_fence(cs, va, 1, 0xffffffff);
4288 assert(cmd_buffer->cs->cdw <= cdw_max);
4289 }
4290
4291 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4292 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4293 NULL);
4294 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4295 NULL);
4296 }
4297
4298 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4299 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4300 NULL);
4301 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4302 NULL);
4303 }
4304
4305 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4306 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4307
4308 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4309 image);
4310 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4311 image);
4312 }
4313
4314 radv_stage_flush(cmd_buffer, info->srcStageMask);
4315 cmd_buffer->state.flush_bits |= src_flush_bits;
4316
4317 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4318 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4319 radv_handle_image_transition(cmd_buffer, image,
4320 pImageMemoryBarriers[i].oldLayout,
4321 pImageMemoryBarriers[i].newLayout,
4322 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4323 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4324 &pImageMemoryBarriers[i].subresourceRange,
4325 0);
4326 }
4327
4328 /* Make sure CP DMA is idle because the driver might have performed a
4329 * DMA operation for copying or filling buffers/images.
4330 */
4331 si_cp_dma_wait_for_idle(cmd_buffer);
4332
4333 cmd_buffer->state.flush_bits |= dst_flush_bits;
4334 }
4335
4336 void radv_CmdPipelineBarrier(
4337 VkCommandBuffer commandBuffer,
4338 VkPipelineStageFlags srcStageMask,
4339 VkPipelineStageFlags destStageMask,
4340 VkBool32 byRegion,
4341 uint32_t memoryBarrierCount,
4342 const VkMemoryBarrier* pMemoryBarriers,
4343 uint32_t bufferMemoryBarrierCount,
4344 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4345 uint32_t imageMemoryBarrierCount,
4346 const VkImageMemoryBarrier* pImageMemoryBarriers)
4347 {
4348 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4349 struct radv_barrier_info info;
4350
4351 info.eventCount = 0;
4352 info.pEvents = NULL;
4353 info.srcStageMask = srcStageMask;
4354
4355 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4356 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4357 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4358 }
4359
4360
4361 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4362 struct radv_event *event,
4363 VkPipelineStageFlags stageMask,
4364 unsigned value)
4365 {
4366 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4367 uint64_t va = radv_buffer_get_va(event->bo);
4368
4369 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4370
4371 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4372
4373 /* Flags that only require a top-of-pipe event. */
4374 VkPipelineStageFlags top_of_pipe_flags =
4375 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4376
4377 /* Flags that only require a post-index-fetch event. */
4378 VkPipelineStageFlags post_index_fetch_flags =
4379 top_of_pipe_flags |
4380 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4381 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4382
4383 /* Make sure CP DMA is idle because the driver might have performed a
4384 * DMA operation for copying or filling buffers/images.
4385 */
4386 si_cp_dma_wait_for_idle(cmd_buffer);
4387
4388 /* TODO: Emit EOS events for syncing PS/CS stages. */
4389
4390 if (!(stageMask & ~top_of_pipe_flags)) {
4391 /* Just need to sync the PFP engine. */
4392 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4393 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4394 S_370_WR_CONFIRM(1) |
4395 S_370_ENGINE_SEL(V_370_PFP));
4396 radeon_emit(cs, va);
4397 radeon_emit(cs, va >> 32);
4398 radeon_emit(cs, value);
4399 } else if (!(stageMask & ~post_index_fetch_flags)) {
4400 /* Sync ME because PFP reads index and indirect buffers. */
4401 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4402 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4403 S_370_WR_CONFIRM(1) |
4404 S_370_ENGINE_SEL(V_370_ME));
4405 radeon_emit(cs, va);
4406 radeon_emit(cs, va >> 32);
4407 radeon_emit(cs, value);
4408 } else {
4409 /* Otherwise, sync all prior GPU work using an EOP event. */
4410 si_cs_emit_write_event_eop(cs,
4411 cmd_buffer->device->physical_device->rad_info.chip_class,
4412 radv_cmd_buffer_uses_mec(cmd_buffer),
4413 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4414 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4415 cmd_buffer->gfx9_eop_bug_va);
4416 }
4417
4418 assert(cmd_buffer->cs->cdw <= cdw_max);
4419 }
4420
4421 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4422 VkEvent _event,
4423 VkPipelineStageFlags stageMask)
4424 {
4425 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4426 RADV_FROM_HANDLE(radv_event, event, _event);
4427
4428 write_event(cmd_buffer, event, stageMask, 1);
4429 }
4430
4431 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4432 VkEvent _event,
4433 VkPipelineStageFlags stageMask)
4434 {
4435 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4436 RADV_FROM_HANDLE(radv_event, event, _event);
4437
4438 write_event(cmd_buffer, event, stageMask, 0);
4439 }
4440
4441 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4442 uint32_t eventCount,
4443 const VkEvent* pEvents,
4444 VkPipelineStageFlags srcStageMask,
4445 VkPipelineStageFlags dstStageMask,
4446 uint32_t memoryBarrierCount,
4447 const VkMemoryBarrier* pMemoryBarriers,
4448 uint32_t bufferMemoryBarrierCount,
4449 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4450 uint32_t imageMemoryBarrierCount,
4451 const VkImageMemoryBarrier* pImageMemoryBarriers)
4452 {
4453 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4454 struct radv_barrier_info info;
4455
4456 info.eventCount = eventCount;
4457 info.pEvents = pEvents;
4458 info.srcStageMask = 0;
4459
4460 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4461 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4462 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4463 }
4464
4465
4466 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4467 uint32_t deviceMask)
4468 {
4469 /* No-op */
4470 }
4471
4472 /* VK_EXT_conditional_rendering */
4473 void radv_CmdBeginConditionalRenderingEXT(
4474 VkCommandBuffer commandBuffer,
4475 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4476 {
4477 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4478 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4479 bool draw_visible = true;
4480 uint64_t va;
4481
4482 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4483
4484 /* By default, if the 32-bit value at offset in buffer memory is zero,
4485 * then the rendering commands are discarded, otherwise they are
4486 * executed as normal. If the inverted flag is set, all commands are
4487 * discarded if the value is non zero.
4488 */
4489 if (pConditionalRenderingBegin->flags &
4490 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4491 draw_visible = false;
4492 }
4493
4494 /* Enable predication for this command buffer. */
4495 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4496 cmd_buffer->state.predicating = true;
4497
4498 /* Store conditional rendering user info. */
4499 cmd_buffer->state.predication_type = draw_visible;
4500 cmd_buffer->state.predication_va = va;
4501 }
4502
4503 void radv_CmdEndConditionalRenderingEXT(
4504 VkCommandBuffer commandBuffer)
4505 {
4506 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4507
4508 /* Disable predication for this command buffer. */
4509 si_emit_set_predication_state(cmd_buffer, false, 0);
4510 cmd_buffer->state.predicating = false;
4511
4512 /* Reset conditional rendering user info. */
4513 cmd_buffer->state.predication_type = -1;
4514 cmd_buffer->state.predication_va = 0;
4515 }