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radv: limit the scissor bug workaround to Vega 10 and Raven
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
96 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
97 src->viewport.count * sizeof(VkViewport))) {
98 typed_memcpy(dest->viewport.viewports,
99 src->viewport.viewports,
100 src->viewport.count);
101 dest_mask |= 1 << VK_DYNAMIC_STATE_VIEWPORT;
102 }
103 }
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
106 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
107 src->scissor.count * sizeof(VkRect2D))) {
108 typed_memcpy(dest->scissor.scissors,
109 src->scissor.scissors, src->scissor.count);
110 dest_mask |= 1 << VK_DYNAMIC_STATE_SCISSOR;
111 }
112 }
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
115 if (dest->line_width != src->line_width) {
116 dest->line_width = src->line_width;
117 dest_mask |= 1 << VK_DYNAMIC_STATE_LINE_WIDTH;
118 }
119 }
120
121 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
122 if (memcmp(&dest->depth_bias, &src->depth_bias,
123 sizeof(src->depth_bias))) {
124 dest->depth_bias = src->depth_bias;
125 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS;
126 }
127 }
128
129 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
130 if (memcmp(&dest->blend_constants, &src->blend_constants,
131 sizeof(src->blend_constants))) {
132 typed_memcpy(dest->blend_constants,
133 src->blend_constants, 4);
134 dest_mask |= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS;
135 }
136 }
137
138 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
139 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
140 sizeof(src->depth_bounds))) {
141 dest->depth_bounds = src->depth_bounds;
142 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS;
143 }
144 }
145
146 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
147 if (memcmp(&dest->stencil_compare_mask,
148 &src->stencil_compare_mask,
149 sizeof(src->stencil_compare_mask))) {
150 dest->stencil_compare_mask = src->stencil_compare_mask;
151 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK;
152 }
153 }
154
155 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
156 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
157 sizeof(src->stencil_write_mask))) {
158 dest->stencil_write_mask = src->stencil_write_mask;
159 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK;
160 }
161 }
162
163 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
164 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
165 sizeof(src->stencil_reference))) {
166 dest->stencil_reference = src->stencil_reference;
167 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE;
168 }
169 }
170
171 cmd_buffer->state.dirty |= dest_mask;
172 }
173
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
175 {
176 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
177 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
178 }
179
180 enum ring_type radv_queue_family_to_ring(int f) {
181 switch (f) {
182 case RADV_QUEUE_GENERAL:
183 return RING_GFX;
184 case RADV_QUEUE_COMPUTE:
185 return RING_COMPUTE;
186 case RADV_QUEUE_TRANSFER:
187 return RING_DMA;
188 default:
189 unreachable("Unknown queue family");
190 }
191 }
192
193 static VkResult radv_create_cmd_buffer(
194 struct radv_device * device,
195 struct radv_cmd_pool * pool,
196 VkCommandBufferLevel level,
197 VkCommandBuffer* pCommandBuffer)
198 {
199 struct radv_cmd_buffer *cmd_buffer;
200 unsigned ring;
201 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
203 if (cmd_buffer == NULL)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
205
206 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
207 cmd_buffer->device = device;
208 cmd_buffer->pool = pool;
209 cmd_buffer->level = level;
210
211 if (pool) {
212 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
213 cmd_buffer->queue_family_index = pool->queue_family_index;
214
215 } else {
216 /* Init the pool_link so we can safefly call list_del when we destroy
217 * the command buffer
218 */
219 list_inithead(&cmd_buffer->pool_link);
220 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
221 }
222
223 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
224
225 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
226 if (!cmd_buffer->cs) {
227 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
228 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
229 }
230
231 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
232
233 list_inithead(&cmd_buffer->upload.list);
234
235 return VK_SUCCESS;
236 }
237
238 static void
239 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
240 {
241 list_del(&cmd_buffer->pool_link);
242
243 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
244 &cmd_buffer->upload.list, list) {
245 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
246 list_del(&up->list);
247 free(up);
248 }
249
250 if (cmd_buffer->upload.upload_bo)
251 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
252 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
253 free(cmd_buffer->push_descriptors.set.mapped_ptr);
254 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
255 }
256
257 static VkResult
258 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
259 {
260
261 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
262
263 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
264 &cmd_buffer->upload.list, list) {
265 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
266 list_del(&up->list);
267 free(up);
268 }
269
270 cmd_buffer->push_constant_stages = 0;
271 cmd_buffer->scratch_size_needed = 0;
272 cmd_buffer->compute_scratch_size_needed = 0;
273 cmd_buffer->esgs_ring_size_needed = 0;
274 cmd_buffer->gsvs_ring_size_needed = 0;
275 cmd_buffer->tess_rings_needed = false;
276 cmd_buffer->sample_positions_needed = false;
277
278 if (cmd_buffer->upload.upload_bo)
279 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
280 cmd_buffer->upload.upload_bo, 8);
281 cmd_buffer->upload.offset = 0;
282
283 cmd_buffer->record_result = VK_SUCCESS;
284
285 cmd_buffer->ring_offsets_idx = -1;
286
287 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
288 void *fence_ptr;
289 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
290 &cmd_buffer->gfx9_fence_offset,
291 &fence_ptr);
292 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
293 }
294
295 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
296
297 return cmd_buffer->record_result;
298 }
299
300 static bool
301 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
302 uint64_t min_needed)
303 {
304 uint64_t new_size;
305 struct radeon_winsys_bo *bo;
306 struct radv_cmd_buffer_upload *upload;
307 struct radv_device *device = cmd_buffer->device;
308
309 new_size = MAX2(min_needed, 16 * 1024);
310 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
311
312 bo = device->ws->buffer_create(device->ws,
313 new_size, 4096,
314 RADEON_DOMAIN_GTT,
315 RADEON_FLAG_CPU_ACCESS|
316 RADEON_FLAG_NO_INTERPROCESS_SHARING);
317
318 if (!bo) {
319 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
320 return false;
321 }
322
323 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
324 if (cmd_buffer->upload.upload_bo) {
325 upload = malloc(sizeof(*upload));
326
327 if (!upload) {
328 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
329 device->ws->buffer_destroy(bo);
330 return false;
331 }
332
333 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
334 list_add(&upload->list, &cmd_buffer->upload.list);
335 }
336
337 cmd_buffer->upload.upload_bo = bo;
338 cmd_buffer->upload.size = new_size;
339 cmd_buffer->upload.offset = 0;
340 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
341
342 if (!cmd_buffer->upload.map) {
343 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
344 return false;
345 }
346
347 return true;
348 }
349
350 bool
351 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
352 unsigned size,
353 unsigned alignment,
354 unsigned *out_offset,
355 void **ptr)
356 {
357 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
358 if (offset + size > cmd_buffer->upload.size) {
359 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
360 return false;
361 offset = 0;
362 }
363
364 *out_offset = offset;
365 *ptr = cmd_buffer->upload.map + offset;
366
367 cmd_buffer->upload.offset = offset + size;
368 return true;
369 }
370
371 bool
372 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
373 unsigned size, unsigned alignment,
374 const void *data, unsigned *out_offset)
375 {
376 uint8_t *ptr;
377
378 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
379 out_offset, (void **)&ptr))
380 return false;
381
382 if (ptr)
383 memcpy(ptr, data, size);
384
385 return true;
386 }
387
388 static void
389 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
390 unsigned count, const uint32_t *data)
391 {
392 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
393 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
394 S_370_WR_CONFIRM(1) |
395 S_370_ENGINE_SEL(V_370_ME));
396 radeon_emit(cs, va);
397 radeon_emit(cs, va >> 32);
398 radeon_emit_array(cs, data, count);
399 }
400
401 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
402 {
403 struct radv_device *device = cmd_buffer->device;
404 struct radeon_winsys_cs *cs = cmd_buffer->cs;
405 uint64_t va;
406
407 va = radv_buffer_get_va(device->trace_bo);
408 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
409 va += 4;
410
411 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
412
413 ++cmd_buffer->state.trace_id;
414 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
415 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
416 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
417 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
418 }
419
420 static void
421 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
422 {
423 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
424 enum radv_cmd_flush_bits flags;
425
426 /* Force wait for graphics/compute engines to be idle. */
427 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
428 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
429
430 si_cs_emit_cache_flush(cmd_buffer->cs, false,
431 cmd_buffer->device->physical_device->rad_info.chip_class,
432 NULL, 0,
433 radv_cmd_buffer_uses_mec(cmd_buffer),
434 flags);
435 }
436
437 if (unlikely(cmd_buffer->device->trace_bo))
438 radv_cmd_buffer_trace_emit(cmd_buffer);
439 }
440
441 static void
442 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
443 struct radv_pipeline *pipeline, enum ring_type ring)
444 {
445 struct radv_device *device = cmd_buffer->device;
446 struct radeon_winsys_cs *cs = cmd_buffer->cs;
447 uint32_t data[2];
448 uint64_t va;
449
450 va = radv_buffer_get_va(device->trace_bo);
451
452 switch (ring) {
453 case RING_GFX:
454 va += 8;
455 break;
456 case RING_COMPUTE:
457 va += 16;
458 break;
459 default:
460 assert(!"invalid ring type");
461 }
462
463 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
464 cmd_buffer->cs, 6);
465
466 data[0] = (uintptr_t)pipeline;
467 data[1] = (uintptr_t)pipeline >> 32;
468
469 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
470 radv_emit_write_data_packet(cs, va, 2, data);
471 }
472
473 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
474 struct radv_descriptor_set *set,
475 unsigned idx)
476 {
477 cmd_buffer->descriptors[idx] = set;
478 if (set)
479 cmd_buffer->state.valid_descriptors |= (1u << idx);
480 else
481 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
482 cmd_buffer->state.descriptors_dirty |= (1u << idx);
483
484 }
485
486 static void
487 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
488 {
489 struct radv_device *device = cmd_buffer->device;
490 struct radeon_winsys_cs *cs = cmd_buffer->cs;
491 uint32_t data[MAX_SETS * 2] = {};
492 uint64_t va;
493 unsigned i;
494 va = radv_buffer_get_va(device->trace_bo) + 24;
495
496 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
497 cmd_buffer->cs, 4 + MAX_SETS * 2);
498
499 for_each_bit(i, cmd_buffer->state.valid_descriptors) {
500 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
501 data[i * 2] = (uintptr_t)set;
502 data[i * 2 + 1] = (uintptr_t)set >> 32;
503 }
504
505 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
506 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
507 }
508
509 static void
510 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
511 struct radv_pipeline *pipeline)
512 {
513 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
514 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
515 8);
516 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
517 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
518
519 if (cmd_buffer->device->physical_device->has_rbplus) {
520
521 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
522 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
523
524 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
525 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
526 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
527 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
528 }
529 }
530
531 static void
532 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
533 struct radv_pipeline *pipeline)
534 {
535 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
536 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
537 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
538
539 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
540 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
541 }
542
543 struct ac_userdata_info *
544 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
545 gl_shader_stage stage,
546 int idx)
547 {
548 if (stage == MESA_SHADER_VERTEX) {
549 if (pipeline->shaders[MESA_SHADER_VERTEX])
550 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
551 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
552 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
553 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
554 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
555 } else if (stage == MESA_SHADER_TESS_EVAL) {
556 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
557 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
558 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
559 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
560 }
561 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
562 }
563
564 static void
565 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
566 struct radv_pipeline *pipeline,
567 gl_shader_stage stage,
568 int idx, uint64_t va)
569 {
570 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
571 uint32_t base_reg = pipeline->user_data_0[stage];
572 if (loc->sgpr_idx == -1)
573 return;
574 assert(loc->num_sgprs == 2);
575 assert(!loc->indirect);
576 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
577 radeon_emit(cmd_buffer->cs, va);
578 radeon_emit(cmd_buffer->cs, va >> 32);
579 }
580
581 static void
582 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
583 struct radv_pipeline *pipeline)
584 {
585 int num_samples = pipeline->graphics.ms.num_samples;
586 struct radv_multisample_state *ms = &pipeline->graphics.ms;
587 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
588
589 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
590 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
591 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
592
593 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
594 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
595
596 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples &&
597 old_pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions == pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
598 return;
599
600 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
601 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
602 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
603
604 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
605
606 /* GFX9: Flush DFSM when the AA mode changes. */
607 if (cmd_buffer->device->dfsm_allowed) {
608 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
609 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
610 }
611 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
612 uint32_t offset;
613 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
614 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
615 if (loc->sgpr_idx == -1)
616 return;
617 assert(loc->num_sgprs == 1);
618 assert(!loc->indirect);
619 switch (num_samples) {
620 default:
621 offset = 0;
622 break;
623 case 2:
624 offset = 1;
625 break;
626 case 4:
627 offset = 3;
628 break;
629 case 8:
630 offset = 7;
631 break;
632 case 16:
633 offset = 15;
634 break;
635 }
636
637 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
638 cmd_buffer->sample_positions_needed = true;
639 }
640 }
641
642 static void
643 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
644 struct radv_pipeline *pipeline)
645 {
646 struct radv_raster_state *raster = &pipeline->graphics.raster;
647
648 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
649 raster->pa_cl_clip_cntl);
650 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
651 raster->spi_interp_control);
652 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
653 raster->pa_su_vtx_cntl);
654 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
655 raster->pa_su_sc_mode_cntl);
656 }
657
658 static inline void
659 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
660 unsigned size)
661 {
662 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
663 si_cp_dma_prefetch(cmd_buffer, va, size);
664 }
665
666 static void
667 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
668 {
669 if (cmd_buffer->state.vb_prefetch_dirty) {
670 radv_emit_prefetch_TC_L2_async(cmd_buffer,
671 cmd_buffer->state.vb_va,
672 cmd_buffer->state.vb_size);
673 cmd_buffer->state.vb_prefetch_dirty = false;
674 }
675 }
676
677 static void
678 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
679 struct radv_shader_variant *shader)
680 {
681 struct radeon_winsys *ws = cmd_buffer->device->ws;
682 struct radeon_winsys_cs *cs = cmd_buffer->cs;
683 uint64_t va;
684
685 if (!shader)
686 return;
687
688 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
689
690 radv_cs_add_buffer(ws, cs, shader->bo, 8);
691 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
692 }
693
694 static void
695 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
696 struct radv_pipeline *pipeline)
697 {
698 radv_emit_shader_prefetch(cmd_buffer,
699 pipeline->shaders[MESA_SHADER_VERTEX]);
700 radv_emit_VBO_descriptors_prefetch(cmd_buffer);
701 radv_emit_shader_prefetch(cmd_buffer,
702 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
703 radv_emit_shader_prefetch(cmd_buffer,
704 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
705 radv_emit_shader_prefetch(cmd_buffer,
706 pipeline->shaders[MESA_SHADER_GEOMETRY]);
707 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
708 radv_emit_shader_prefetch(cmd_buffer,
709 pipeline->shaders[MESA_SHADER_FRAGMENT]);
710 }
711
712 static void
713 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
714 struct radv_pipeline *pipeline,
715 struct radv_shader_variant *shader)
716 {
717 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
718
719 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
720 pipeline->graphics.vs.spi_vs_out_config);
721
722 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
723 pipeline->graphics.vs.spi_shader_pos_format);
724
725 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
726 radeon_emit(cmd_buffer->cs, va >> 8);
727 radeon_emit(cmd_buffer->cs, va >> 40);
728 radeon_emit(cmd_buffer->cs, shader->rsrc1);
729 radeon_emit(cmd_buffer->cs, shader->rsrc2);
730
731 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
732 S_028818_VTX_W0_FMT(1) |
733 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
734 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
735 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
736
737
738 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
739 pipeline->graphics.vs.pa_cl_vs_out_cntl);
740
741 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
742 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
743 pipeline->graphics.vs.vgt_reuse_off);
744 }
745
746 static void
747 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
748 struct radv_pipeline *pipeline,
749 struct radv_shader_variant *shader)
750 {
751 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
752
753 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
754 radeon_emit(cmd_buffer->cs, va >> 8);
755 radeon_emit(cmd_buffer->cs, va >> 40);
756 radeon_emit(cmd_buffer->cs, shader->rsrc1);
757 radeon_emit(cmd_buffer->cs, shader->rsrc2);
758 }
759
760 static void
761 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
762 struct radv_shader_variant *shader)
763 {
764 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
765 uint32_t rsrc2 = shader->rsrc2;
766
767 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
768 radeon_emit(cmd_buffer->cs, va >> 8);
769 radeon_emit(cmd_buffer->cs, va >> 40);
770
771 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
772 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
773 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
774 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
775
776 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
777 radeon_emit(cmd_buffer->cs, shader->rsrc1);
778 radeon_emit(cmd_buffer->cs, rsrc2);
779 }
780
781 static void
782 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
783 struct radv_shader_variant *shader)
784 {
785 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
786
787 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
788 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
789 radeon_emit(cmd_buffer->cs, va >> 8);
790 radeon_emit(cmd_buffer->cs, va >> 40);
791
792 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
793 radeon_emit(cmd_buffer->cs, shader->rsrc1);
794 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
795 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
796 } else {
797 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
798 radeon_emit(cmd_buffer->cs, va >> 8);
799 radeon_emit(cmd_buffer->cs, va >> 40);
800 radeon_emit(cmd_buffer->cs, shader->rsrc1);
801 radeon_emit(cmd_buffer->cs, shader->rsrc2);
802 }
803 }
804
805 static void
806 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
807 struct radv_pipeline *pipeline)
808 {
809 struct radv_shader_variant *vs;
810
811 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
812
813 /* Skip shaders merged into HS/GS */
814 vs = pipeline->shaders[MESA_SHADER_VERTEX];
815 if (!vs)
816 return;
817
818 if (vs->info.vs.as_ls)
819 radv_emit_hw_ls(cmd_buffer, vs);
820 else if (vs->info.vs.as_es)
821 radv_emit_hw_es(cmd_buffer, pipeline, vs);
822 else
823 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
824 }
825
826
827 static void
828 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
829 struct radv_pipeline *pipeline)
830 {
831 if (!radv_pipeline_has_tess(pipeline))
832 return;
833
834 struct radv_shader_variant *tes, *tcs;
835
836 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
837 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
838
839 if (tes) {
840 if (tes->info.tes.as_es)
841 radv_emit_hw_es(cmd_buffer, pipeline, tes);
842 else
843 radv_emit_hw_vs(cmd_buffer, pipeline, tes);
844 }
845
846 radv_emit_hw_hs(cmd_buffer, tcs);
847
848 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
849 pipeline->graphics.tess.tf_param);
850
851 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
852 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
853 pipeline->graphics.tess.ls_hs_config);
854 else
855 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
856 pipeline->graphics.tess.ls_hs_config);
857
858 struct ac_userdata_info *loc;
859
860 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
861 if (loc->sgpr_idx != -1) {
862 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
863 assert(loc->num_sgprs == 4);
864 assert(!loc->indirect);
865 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
866 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
867 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
868 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
869 pipeline->graphics.tess.num_tcs_input_cp << 26);
870 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
871 }
872
873 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
874 if (loc->sgpr_idx != -1) {
875 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
876 assert(loc->num_sgprs == 1);
877 assert(!loc->indirect);
878
879 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
880 pipeline->graphics.tess.offchip_layout);
881 }
882
883 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
884 if (loc->sgpr_idx != -1) {
885 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
886 assert(loc->num_sgprs == 1);
887 assert(!loc->indirect);
888
889 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
890 pipeline->graphics.tess.tcs_in_layout);
891 }
892 }
893
894 static void
895 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
896 struct radv_pipeline *pipeline)
897 {
898 struct radv_shader_variant *gs;
899 uint64_t va;
900
901 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
902
903 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
904 if (!gs)
905 return;
906
907 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
908
909 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
910 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
911 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
912 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
913
914 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
915
916 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
917
918 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
919 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
920 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
921 radeon_emit(cmd_buffer->cs, 0);
922 radeon_emit(cmd_buffer->cs, 0);
923 radeon_emit(cmd_buffer->cs, 0);
924
925 uint32_t gs_num_invocations = gs->info.gs.invocations;
926 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
927 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
928 S_028B90_ENABLE(gs_num_invocations > 0));
929
930 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
931 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
932
933 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
934
935 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
936 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
937 radeon_emit(cmd_buffer->cs, va >> 8);
938 radeon_emit(cmd_buffer->cs, va >> 40);
939
940 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
941 radeon_emit(cmd_buffer->cs, gs->rsrc1);
942 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
943 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
944
945 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
946 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
947 } else {
948 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
949 radeon_emit(cmd_buffer->cs, va >> 8);
950 radeon_emit(cmd_buffer->cs, va >> 40);
951 radeon_emit(cmd_buffer->cs, gs->rsrc1);
952 radeon_emit(cmd_buffer->cs, gs->rsrc2);
953 }
954
955 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
956
957 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
958 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
959 if (loc->sgpr_idx != -1) {
960 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
961 uint32_t num_entries = 64;
962 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
963
964 if (is_vi)
965 num_entries *= stride;
966
967 stride = S_008F04_STRIDE(stride);
968 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
969 radeon_emit(cmd_buffer->cs, stride);
970 radeon_emit(cmd_buffer->cs, num_entries);
971 }
972 }
973
974 static void
975 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
976 struct radv_pipeline *pipeline)
977 {
978 struct radv_shader_variant *ps;
979 uint64_t va;
980 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
981 struct radv_blend_state *blend = &pipeline->graphics.blend;
982 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
983
984 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
985 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
986
987 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
988 radeon_emit(cmd_buffer->cs, va >> 8);
989 radeon_emit(cmd_buffer->cs, va >> 40);
990 radeon_emit(cmd_buffer->cs, ps->rsrc1);
991 radeon_emit(cmd_buffer->cs, ps->rsrc2);
992
993 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
994 pipeline->graphics.db_shader_control);
995
996 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
997 ps->config.spi_ps_input_ena);
998
999 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
1000 ps->config.spi_ps_input_addr);
1001
1002 if (ps->info.info.ps.force_persample)
1003 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1004
1005 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
1006 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
1007
1008 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1009
1010 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
1011 pipeline->graphics.shader_z_format);
1012
1013 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1014
1015 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1016 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1017
1018 if (cmd_buffer->device->dfsm_allowed) {
1019 /* optimise this? */
1020 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1021 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1022 }
1023
1024 if (pipeline->graphics.ps_input_cntl_num) {
1025 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1026 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1027 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1028 }
1029 }
1030 }
1031
1032 static void
1033 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1034 struct radv_pipeline *pipeline)
1035 {
1036 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1037
1038 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1039 return;
1040
1041 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1042 pipeline->graphics.vtx_reuse_depth);
1043 }
1044
1045 static void
1046 radv_emit_binning_state(struct radv_cmd_buffer *cmd_buffer,
1047 struct radv_pipeline *pipeline)
1048 {
1049 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1050
1051 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9)
1052 return;
1053
1054 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
1055 pipeline->graphics.bin.pa_sc_binner_cntl_0);
1056 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
1057 pipeline->graphics.bin.db_dfsm_control);
1058 }
1059
1060 static void
1061 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1062 {
1063 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1064
1065 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1066 return;
1067
1068 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1069 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1070 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1071 radv_update_multisample_state(cmd_buffer, pipeline);
1072 radv_emit_vertex_shader(cmd_buffer, pipeline);
1073 radv_emit_tess_shaders(cmd_buffer, pipeline);
1074 radv_emit_geometry_shader(cmd_buffer, pipeline);
1075 radv_emit_fragment_shader(cmd_buffer, pipeline);
1076 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1077 radv_emit_binning_state(cmd_buffer, pipeline);
1078
1079 cmd_buffer->scratch_size_needed =
1080 MAX2(cmd_buffer->scratch_size_needed,
1081 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1082
1083 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1084 S_0286E8_WAVES(pipeline->max_waves) |
1085 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1086
1087 if (!cmd_buffer->state.emitted_pipeline ||
1088 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1089 pipeline->graphics.can_use_guardband)
1090 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1091
1092 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1093
1094 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1095 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1096 } else {
1097 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1098 }
1099 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1100
1101 if (unlikely(cmd_buffer->device->trace_bo))
1102 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1103
1104 cmd_buffer->state.emitted_pipeline = pipeline;
1105
1106 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1107 }
1108
1109 static void
1110 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1111 {
1112 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1113 cmd_buffer->state.dynamic.viewport.viewports);
1114 }
1115
1116 static void
1117 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1118 {
1119 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1120
1121 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
1122 * scissor registers are changed. There is also a more efficient but
1123 * more involved alternative workaround.
1124 */
1125 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA10 ||
1126 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN) {
1127 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1128 si_emit_cache_flush(cmd_buffer);
1129 }
1130 si_write_scissors(cmd_buffer->cs, 0, count,
1131 cmd_buffer->state.dynamic.scissor.scissors,
1132 cmd_buffer->state.dynamic.viewport.viewports,
1133 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1134 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1135 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1136 }
1137
1138 static void
1139 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1140 {
1141 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1142
1143 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1144 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1145 }
1146
1147 static void
1148 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1149 {
1150 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1151
1152 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1153 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1154 }
1155
1156 static void
1157 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1158 {
1159 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1160
1161 radeon_set_context_reg_seq(cmd_buffer->cs,
1162 R_028430_DB_STENCILREFMASK, 2);
1163 radeon_emit(cmd_buffer->cs,
1164 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1165 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1166 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1167 S_028430_STENCILOPVAL(1));
1168 radeon_emit(cmd_buffer->cs,
1169 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1170 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1171 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1172 S_028434_STENCILOPVAL_BF(1));
1173 }
1174
1175 static void
1176 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1177 {
1178 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1179
1180 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1181 fui(d->depth_bounds.min));
1182 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1183 fui(d->depth_bounds.max));
1184 }
1185
1186 static void
1187 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1188 {
1189 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1190 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1191 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1192 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1193
1194 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1195 radeon_set_context_reg_seq(cmd_buffer->cs,
1196 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1197 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1198 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1199 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1200 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1201 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1202 }
1203 }
1204
1205 static void
1206 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1207 int index,
1208 struct radv_attachment_info *att,
1209 struct radv_image *image,
1210 VkImageLayout layout)
1211 {
1212 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1213 struct radv_color_buffer_info *cb = &att->cb;
1214 uint32_t cb_color_info = cb->cb_color_info;
1215
1216 if (!radv_layout_dcc_compressed(image, layout,
1217 radv_image_queue_family_mask(image,
1218 cmd_buffer->queue_family_index,
1219 cmd_buffer->queue_family_index))) {
1220 cb_color_info &= C_028C70_DCC_ENABLE;
1221 }
1222
1223 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1224 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1225 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1226 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1227 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1228 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1229 radeon_emit(cmd_buffer->cs, cb_color_info);
1230 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1231 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1232 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1233 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1234 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1235 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1236
1237 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1238 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1239 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1240
1241 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1242 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1243 } else {
1244 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1245 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1246 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1247 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1248 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1249 radeon_emit(cmd_buffer->cs, cb_color_info);
1250 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1251 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1252 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1253 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1254 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1255 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1256
1257 if (is_vi) { /* DCC BASE */
1258 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1259 }
1260 }
1261 }
1262
1263 static void
1264 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1265 struct radv_ds_buffer_info *ds,
1266 struct radv_image *image,
1267 VkImageLayout layout)
1268 {
1269 uint32_t db_z_info = ds->db_z_info;
1270 uint32_t db_stencil_info = ds->db_stencil_info;
1271
1272 if (!radv_layout_has_htile(image, layout,
1273 radv_image_queue_family_mask(image,
1274 cmd_buffer->queue_family_index,
1275 cmd_buffer->queue_family_index))) {
1276 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1277 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1278 }
1279
1280 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1281 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1282
1283
1284 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1285 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1286 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1287 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1288 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1289
1290 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1291 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1292 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1293 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1294 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1295 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1296 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1297 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1298 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1299 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1300 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1301
1302 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1303 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1304 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1305 } else {
1306 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1307
1308 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1309 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1310 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1311 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1312 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1313 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1314 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1315 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1316 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1317 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1318
1319 }
1320
1321 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1322 ds->pa_su_poly_offset_db_fmt_cntl);
1323 }
1324
1325 void
1326 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1327 struct radv_image *image,
1328 VkClearDepthStencilValue ds_clear_value,
1329 VkImageAspectFlags aspects)
1330 {
1331 uint64_t va = radv_buffer_get_va(image->bo);
1332 va += image->offset + image->clear_value_offset;
1333 unsigned reg_offset = 0, reg_count = 0;
1334
1335 assert(image->surface.htile_size);
1336
1337 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1338 ++reg_count;
1339 } else {
1340 ++reg_offset;
1341 va += 4;
1342 }
1343 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1344 ++reg_count;
1345
1346 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1347 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1348 S_370_WR_CONFIRM(1) |
1349 S_370_ENGINE_SEL(V_370_PFP));
1350 radeon_emit(cmd_buffer->cs, va);
1351 radeon_emit(cmd_buffer->cs, va >> 32);
1352 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1353 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1354 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1355 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1356
1357 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1358 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1359 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1360 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1361 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1362 }
1363
1364 static void
1365 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1366 struct radv_image *image)
1367 {
1368 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1369 uint64_t va = radv_buffer_get_va(image->bo);
1370 va += image->offset + image->clear_value_offset;
1371 unsigned reg_offset = 0, reg_count = 0;
1372
1373 if (!image->surface.htile_size)
1374 return;
1375
1376 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1377 ++reg_count;
1378 } else {
1379 ++reg_offset;
1380 va += 4;
1381 }
1382 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1383 ++reg_count;
1384
1385 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1386 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1387 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1388 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1389 radeon_emit(cmd_buffer->cs, va);
1390 radeon_emit(cmd_buffer->cs, va >> 32);
1391 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1392 radeon_emit(cmd_buffer->cs, 0);
1393
1394 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1395 radeon_emit(cmd_buffer->cs, 0);
1396 }
1397
1398 /*
1399 *with DCC some colors don't require CMASK elimiation before being
1400 * used as a texture. This sets a predicate value to determine if the
1401 * cmask eliminate is required.
1402 */
1403 void
1404 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1405 struct radv_image *image,
1406 bool value)
1407 {
1408 uint64_t pred_val = value;
1409 uint64_t va = radv_buffer_get_va(image->bo);
1410 va += image->offset + image->dcc_pred_offset;
1411
1412 assert(image->surface.dcc_size);
1413
1414 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1415 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1416 S_370_WR_CONFIRM(1) |
1417 S_370_ENGINE_SEL(V_370_PFP));
1418 radeon_emit(cmd_buffer->cs, va);
1419 radeon_emit(cmd_buffer->cs, va >> 32);
1420 radeon_emit(cmd_buffer->cs, pred_val);
1421 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1422 }
1423
1424 void
1425 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1426 struct radv_image *image,
1427 int idx,
1428 uint32_t color_values[2])
1429 {
1430 uint64_t va = radv_buffer_get_va(image->bo);
1431 va += image->offset + image->clear_value_offset;
1432
1433 assert(image->cmask.size || image->surface.dcc_size);
1434
1435 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1436 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1437 S_370_WR_CONFIRM(1) |
1438 S_370_ENGINE_SEL(V_370_PFP));
1439 radeon_emit(cmd_buffer->cs, va);
1440 radeon_emit(cmd_buffer->cs, va >> 32);
1441 radeon_emit(cmd_buffer->cs, color_values[0]);
1442 radeon_emit(cmd_buffer->cs, color_values[1]);
1443
1444 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1445 radeon_emit(cmd_buffer->cs, color_values[0]);
1446 radeon_emit(cmd_buffer->cs, color_values[1]);
1447 }
1448
1449 static void
1450 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1451 struct radv_image *image,
1452 int idx)
1453 {
1454 uint64_t va = radv_buffer_get_va(image->bo);
1455 va += image->offset + image->clear_value_offset;
1456
1457 if (!image->cmask.size && !image->surface.dcc_size)
1458 return;
1459
1460 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1461
1462 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1463 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1464 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1465 COPY_DATA_COUNT_SEL);
1466 radeon_emit(cmd_buffer->cs, va);
1467 radeon_emit(cmd_buffer->cs, va >> 32);
1468 radeon_emit(cmd_buffer->cs, reg >> 2);
1469 radeon_emit(cmd_buffer->cs, 0);
1470
1471 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1472 radeon_emit(cmd_buffer->cs, 0);
1473 }
1474
1475 static void
1476 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1477 {
1478 int i;
1479 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1480 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1481
1482 /* this may happen for inherited secondary recording */
1483 if (!framebuffer)
1484 return;
1485
1486 for (i = 0; i < 8; ++i) {
1487 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1488 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1489 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1490 continue;
1491 }
1492
1493 int idx = subpass->color_attachments[i].attachment;
1494 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1495 struct radv_image *image = att->attachment->image;
1496 VkImageLayout layout = subpass->color_attachments[i].layout;
1497
1498 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1499
1500 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1501 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1502
1503 radv_load_color_clear_regs(cmd_buffer, image, i);
1504 }
1505
1506 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1507 int idx = subpass->depth_stencil_attachment.attachment;
1508 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1509 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1510 struct radv_image *image = att->attachment->image;
1511 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1512 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1513 cmd_buffer->queue_family_index,
1514 cmd_buffer->queue_family_index);
1515 /* We currently don't support writing decompressed HTILE */
1516 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1517 radv_layout_is_htile_compressed(image, layout, queue_mask));
1518
1519 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1520
1521 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1522 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1523 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1524 }
1525 radv_load_depth_clear_regs(cmd_buffer, image);
1526 } else {
1527 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1528 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1529 else
1530 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1531
1532 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1533 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1534 }
1535 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1536 S_028208_BR_X(framebuffer->width) |
1537 S_028208_BR_Y(framebuffer->height));
1538
1539 if (cmd_buffer->device->dfsm_allowed) {
1540 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1541 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1542 }
1543
1544 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1545 }
1546
1547 static void
1548 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1549 {
1550 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1551 struct radv_cmd_state *state = &cmd_buffer->state;
1552
1553 if (state->index_type != state->last_index_type) {
1554 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1555 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1556 2, state->index_type);
1557 } else {
1558 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1559 radeon_emit(cs, state->index_type);
1560 }
1561
1562 state->last_index_type = state->index_type;
1563 }
1564
1565 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1566 radeon_emit(cs, state->index_va);
1567 radeon_emit(cs, state->index_va >> 32);
1568
1569 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1570 radeon_emit(cs, state->max_index_count);
1571
1572 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1573 }
1574
1575 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1576 {
1577 uint32_t db_count_control;
1578
1579 if(!cmd_buffer->state.active_occlusion_queries) {
1580 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1581 db_count_control = 0;
1582 } else {
1583 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1584 }
1585 } else {
1586 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1587 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1588 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1589 S_028004_ZPASS_ENABLE(1) |
1590 S_028004_SLICE_EVEN_ENABLE(1) |
1591 S_028004_SLICE_ODD_ENABLE(1);
1592 } else {
1593 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1594 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1595 }
1596 }
1597
1598 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1599 }
1600
1601 static void
1602 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1603 {
1604 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1605 return;
1606
1607 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1608 radv_emit_viewport(cmd_buffer);
1609
1610 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1611 radv_emit_scissor(cmd_buffer);
1612
1613 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1614 radv_emit_line_width(cmd_buffer);
1615
1616 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1617 radv_emit_blend_constants(cmd_buffer);
1618
1619 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1620 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1621 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1622 radv_emit_stencil(cmd_buffer);
1623
1624 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1625 radv_emit_depth_bounds(cmd_buffer);
1626
1627 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1628 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1629 radv_emit_depth_biais(cmd_buffer);
1630
1631 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1632 }
1633
1634 static void
1635 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1636 struct radv_pipeline *pipeline,
1637 int idx,
1638 uint64_t va,
1639 gl_shader_stage stage)
1640 {
1641 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1642 uint32_t base_reg = pipeline->user_data_0[stage];
1643
1644 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1645 return;
1646
1647 assert(!desc_set_loc->indirect);
1648 assert(desc_set_loc->num_sgprs == 2);
1649 radeon_set_sh_reg_seq(cmd_buffer->cs,
1650 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1651 radeon_emit(cmd_buffer->cs, va);
1652 radeon_emit(cmd_buffer->cs, va >> 32);
1653 }
1654
1655 static void
1656 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1657 VkShaderStageFlags stages,
1658 struct radv_descriptor_set *set,
1659 unsigned idx)
1660 {
1661 if (cmd_buffer->state.pipeline) {
1662 radv_foreach_stage(stage, stages) {
1663 if (cmd_buffer->state.pipeline->shaders[stage])
1664 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1665 idx, set->va,
1666 stage);
1667 }
1668 }
1669
1670 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1671 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1672 idx, set->va,
1673 MESA_SHADER_COMPUTE);
1674 }
1675
1676 static void
1677 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1678 {
1679 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1680 unsigned bo_offset;
1681
1682 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1683 set->mapped_ptr,
1684 &bo_offset))
1685 return;
1686
1687 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1688 set->va += bo_offset;
1689 }
1690
1691 static void
1692 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1693 {
1694 uint32_t size = MAX_SETS * 2 * 4;
1695 uint32_t offset;
1696 void *ptr;
1697
1698 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1699 256, &offset, &ptr))
1700 return;
1701
1702 for (unsigned i = 0; i < MAX_SETS; i++) {
1703 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1704 uint64_t set_va = 0;
1705 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1706 if (cmd_buffer->state.valid_descriptors & (1u << i))
1707 set_va = set->va;
1708 uptr[0] = set_va & 0xffffffff;
1709 uptr[1] = set_va >> 32;
1710 }
1711
1712 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1713 va += offset;
1714
1715 if (cmd_buffer->state.pipeline) {
1716 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1717 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1718 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1719
1720 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1721 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1722 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1723
1724 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1725 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1726 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1727
1728 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1729 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1730 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1731
1732 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1733 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1734 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1735 }
1736
1737 if (cmd_buffer->state.compute_pipeline)
1738 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1739 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1740 }
1741
1742 static void
1743 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1744 VkShaderStageFlags stages)
1745 {
1746 unsigned i;
1747
1748 if (!cmd_buffer->state.descriptors_dirty)
1749 return;
1750
1751 if (cmd_buffer->state.push_descriptors_dirty)
1752 radv_flush_push_descriptors(cmd_buffer);
1753
1754 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1755 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1756 radv_flush_indirect_descriptor_sets(cmd_buffer);
1757 }
1758
1759 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1760 cmd_buffer->cs,
1761 MAX_SETS * MESA_SHADER_STAGES * 4);
1762
1763 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1764 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1765 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1766 continue;
1767
1768 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1769 }
1770 cmd_buffer->state.descriptors_dirty = 0;
1771 cmd_buffer->state.push_descriptors_dirty = false;
1772
1773 if (unlikely(cmd_buffer->device->trace_bo))
1774 radv_save_descriptors(cmd_buffer);
1775
1776 assert(cmd_buffer->cs->cdw <= cdw_max);
1777 }
1778
1779 static void
1780 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1781 struct radv_pipeline *pipeline,
1782 VkShaderStageFlags stages)
1783 {
1784 struct radv_pipeline_layout *layout = pipeline->layout;
1785 unsigned offset;
1786 void *ptr;
1787 uint64_t va;
1788
1789 stages &= cmd_buffer->push_constant_stages;
1790 if (!stages ||
1791 (!layout->push_constant_size && !layout->dynamic_offset_count))
1792 return;
1793
1794 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1795 16 * layout->dynamic_offset_count,
1796 256, &offset, &ptr))
1797 return;
1798
1799 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1800 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1801 16 * layout->dynamic_offset_count);
1802
1803 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1804 va += offset;
1805
1806 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1807 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1808
1809 radv_foreach_stage(stage, stages) {
1810 if (pipeline->shaders[stage]) {
1811 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1812 AC_UD_PUSH_CONSTANTS, va);
1813 }
1814 }
1815
1816 cmd_buffer->push_constant_stages &= ~stages;
1817 assert(cmd_buffer->cs->cdw <= cdw_max);
1818 }
1819
1820 static bool
1821 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1822 {
1823 if ((pipeline_is_dirty ||
1824 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1825 cmd_buffer->state.pipeline->vertex_elements.count &&
1826 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1827 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1828 unsigned vb_offset;
1829 void *vb_ptr;
1830 uint32_t i = 0;
1831 uint32_t count = velems->count;
1832 uint64_t va;
1833
1834 /* allocate some descriptor state for vertex buffers */
1835 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1836 &vb_offset, &vb_ptr))
1837 return false;
1838
1839 for (i = 0; i < count; i++) {
1840 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1841 uint32_t offset;
1842 int vb = velems->binding[i];
1843 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1844 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1845
1846 va = radv_buffer_get_va(buffer->bo);
1847
1848 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1849 va += offset + buffer->offset;
1850 desc[0] = va;
1851 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1852 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1853 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1854 else
1855 desc[2] = buffer->size - offset;
1856 desc[3] = velems->rsrc_word3[i];
1857 }
1858
1859 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1860 va += vb_offset;
1861
1862 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1863 AC_UD_VS_VERTEX_BUFFERS, va);
1864
1865 cmd_buffer->state.vb_va = va;
1866 cmd_buffer->state.vb_size = count * 16;
1867 cmd_buffer->state.vb_prefetch_dirty = true;
1868 }
1869 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1870
1871 return true;
1872 }
1873
1874 static bool
1875 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1876 {
1877 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1878 return false;
1879
1880 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1881 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1882 VK_SHADER_STAGE_ALL_GRAPHICS);
1883
1884 return true;
1885 }
1886
1887 static void
1888 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1889 bool instanced_draw, bool indirect_draw,
1890 uint32_t draw_vertex_count)
1891 {
1892 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1893 struct radv_cmd_state *state = &cmd_buffer->state;
1894 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1895 uint32_t ia_multi_vgt_param;
1896 int32_t primitive_reset_en;
1897
1898 /* Draw state. */
1899 ia_multi_vgt_param =
1900 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1901 indirect_draw, draw_vertex_count);
1902
1903 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1904 if (info->chip_class >= GFX9) {
1905 radeon_set_uconfig_reg_idx(cs,
1906 R_030960_IA_MULTI_VGT_PARAM,
1907 4, ia_multi_vgt_param);
1908 } else if (info->chip_class >= CIK) {
1909 radeon_set_context_reg_idx(cs,
1910 R_028AA8_IA_MULTI_VGT_PARAM,
1911 1, ia_multi_vgt_param);
1912 } else {
1913 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1914 ia_multi_vgt_param);
1915 }
1916 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1917 }
1918
1919 /* Primitive restart. */
1920 primitive_reset_en =
1921 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1922
1923 if (primitive_reset_en != state->last_primitive_reset_en) {
1924 state->last_primitive_reset_en = primitive_reset_en;
1925 if (info->chip_class >= GFX9) {
1926 radeon_set_uconfig_reg(cs,
1927 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1928 primitive_reset_en);
1929 } else {
1930 radeon_set_context_reg(cs,
1931 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1932 primitive_reset_en);
1933 }
1934 }
1935
1936 if (primitive_reset_en) {
1937 uint32_t primitive_reset_index =
1938 state->index_type ? 0xffffffffu : 0xffffu;
1939
1940 if (primitive_reset_index != state->last_primitive_reset_index) {
1941 radeon_set_context_reg(cs,
1942 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1943 primitive_reset_index);
1944 state->last_primitive_reset_index = primitive_reset_index;
1945 }
1946 }
1947 }
1948
1949 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1950 VkPipelineStageFlags src_stage_mask)
1951 {
1952 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1953 VK_PIPELINE_STAGE_TRANSFER_BIT |
1954 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1955 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1956 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1957 }
1958
1959 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1960 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1961 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1962 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1963 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1964 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1965 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1966 VK_PIPELINE_STAGE_TRANSFER_BIT |
1967 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1968 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1969 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1970 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1971 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1972 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1973 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1974 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1975 }
1976 }
1977
1978 static enum radv_cmd_flush_bits
1979 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1980 VkAccessFlags src_flags)
1981 {
1982 enum radv_cmd_flush_bits flush_bits = 0;
1983 uint32_t b;
1984 for_each_bit(b, src_flags) {
1985 switch ((VkAccessFlagBits)(1 << b)) {
1986 case VK_ACCESS_SHADER_WRITE_BIT:
1987 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1988 break;
1989 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1990 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1991 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1992 break;
1993 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1994 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1995 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1996 break;
1997 case VK_ACCESS_TRANSFER_WRITE_BIT:
1998 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1999 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2000 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2001 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2002 RADV_CMD_FLAG_INV_GLOBAL_L2;
2003 break;
2004 default:
2005 break;
2006 }
2007 }
2008 return flush_bits;
2009 }
2010
2011 static enum radv_cmd_flush_bits
2012 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2013 VkAccessFlags dst_flags,
2014 struct radv_image *image)
2015 {
2016 enum radv_cmd_flush_bits flush_bits = 0;
2017 uint32_t b;
2018 for_each_bit(b, dst_flags) {
2019 switch ((VkAccessFlagBits)(1 << b)) {
2020 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2021 case VK_ACCESS_INDEX_READ_BIT:
2022 break;
2023 case VK_ACCESS_UNIFORM_READ_BIT:
2024 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2025 break;
2026 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2027 case VK_ACCESS_SHADER_READ_BIT:
2028 case VK_ACCESS_TRANSFER_READ_BIT:
2029 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2030 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2031 RADV_CMD_FLAG_INV_GLOBAL_L2;
2032 break;
2033 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2034 /* TODO: change to image && when the image gets passed
2035 * through from the subpass. */
2036 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2037 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2038 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2039 break;
2040 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2041 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2042 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2043 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2044 break;
2045 default:
2046 break;
2047 }
2048 }
2049 return flush_bits;
2050 }
2051
2052 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2053 {
2054 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2055 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2056 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2057 NULL);
2058 }
2059
2060 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2061 VkAttachmentReference att)
2062 {
2063 unsigned idx = att.attachment;
2064 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2065 VkImageSubresourceRange range;
2066 range.aspectMask = 0;
2067 range.baseMipLevel = view->base_mip;
2068 range.levelCount = 1;
2069 range.baseArrayLayer = view->base_layer;
2070 range.layerCount = cmd_buffer->state.framebuffer->layers;
2071
2072 radv_handle_image_transition(cmd_buffer,
2073 view->image,
2074 cmd_buffer->state.attachments[idx].current_layout,
2075 att.layout, 0, 0, &range,
2076 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2077
2078 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2079
2080
2081 }
2082
2083 void
2084 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2085 const struct radv_subpass *subpass, bool transitions)
2086 {
2087 if (transitions) {
2088 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2089
2090 for (unsigned i = 0; i < subpass->color_count; ++i) {
2091 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2092 radv_handle_subpass_image_transition(cmd_buffer,
2093 subpass->color_attachments[i]);
2094 }
2095
2096 for (unsigned i = 0; i < subpass->input_count; ++i) {
2097 radv_handle_subpass_image_transition(cmd_buffer,
2098 subpass->input_attachments[i]);
2099 }
2100
2101 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2102 radv_handle_subpass_image_transition(cmd_buffer,
2103 subpass->depth_stencil_attachment);
2104 }
2105 }
2106
2107 cmd_buffer->state.subpass = subpass;
2108
2109 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2110 }
2111
2112 static VkResult
2113 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2114 struct radv_render_pass *pass,
2115 const VkRenderPassBeginInfo *info)
2116 {
2117 struct radv_cmd_state *state = &cmd_buffer->state;
2118
2119 if (pass->attachment_count == 0) {
2120 state->attachments = NULL;
2121 return VK_SUCCESS;
2122 }
2123
2124 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2125 pass->attachment_count *
2126 sizeof(state->attachments[0]),
2127 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2128 if (state->attachments == NULL) {
2129 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2130 return cmd_buffer->record_result;
2131 }
2132
2133 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2134 struct radv_render_pass_attachment *att = &pass->attachments[i];
2135 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2136 VkImageAspectFlags clear_aspects = 0;
2137
2138 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2139 /* color attachment */
2140 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2141 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2142 }
2143 } else {
2144 /* depthstencil attachment */
2145 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2146 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2147 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2148 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2149 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2150 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2151 }
2152 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2153 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2154 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2155 }
2156 }
2157
2158 state->attachments[i].pending_clear_aspects = clear_aspects;
2159 state->attachments[i].cleared_views = 0;
2160 if (clear_aspects && info) {
2161 assert(info->clearValueCount > i);
2162 state->attachments[i].clear_value = info->pClearValues[i];
2163 }
2164
2165 state->attachments[i].current_layout = att->initial_layout;
2166 }
2167
2168 return VK_SUCCESS;
2169 }
2170
2171 VkResult radv_AllocateCommandBuffers(
2172 VkDevice _device,
2173 const VkCommandBufferAllocateInfo *pAllocateInfo,
2174 VkCommandBuffer *pCommandBuffers)
2175 {
2176 RADV_FROM_HANDLE(radv_device, device, _device);
2177 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2178
2179 VkResult result = VK_SUCCESS;
2180 uint32_t i;
2181
2182 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2183
2184 if (!list_empty(&pool->free_cmd_buffers)) {
2185 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2186
2187 list_del(&cmd_buffer->pool_link);
2188 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2189
2190 result = radv_reset_cmd_buffer(cmd_buffer);
2191 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2192 cmd_buffer->level = pAllocateInfo->level;
2193
2194 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2195 } else {
2196 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2197 &pCommandBuffers[i]);
2198 }
2199 if (result != VK_SUCCESS)
2200 break;
2201 }
2202
2203 if (result != VK_SUCCESS) {
2204 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2205 i, pCommandBuffers);
2206
2207 /* From the Vulkan 1.0.66 spec:
2208 *
2209 * "vkAllocateCommandBuffers can be used to create multiple
2210 * command buffers. If the creation of any of those command
2211 * buffers fails, the implementation must destroy all
2212 * successfully created command buffer objects from this
2213 * command, set all entries of the pCommandBuffers array to
2214 * NULL and return the error."
2215 */
2216 memset(pCommandBuffers, 0,
2217 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2218 }
2219
2220 return result;
2221 }
2222
2223 void radv_FreeCommandBuffers(
2224 VkDevice device,
2225 VkCommandPool commandPool,
2226 uint32_t commandBufferCount,
2227 const VkCommandBuffer *pCommandBuffers)
2228 {
2229 for (uint32_t i = 0; i < commandBufferCount; i++) {
2230 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2231
2232 if (cmd_buffer) {
2233 if (cmd_buffer->pool) {
2234 list_del(&cmd_buffer->pool_link);
2235 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2236 } else
2237 radv_cmd_buffer_destroy(cmd_buffer);
2238
2239 }
2240 }
2241 }
2242
2243 VkResult radv_ResetCommandBuffer(
2244 VkCommandBuffer commandBuffer,
2245 VkCommandBufferResetFlags flags)
2246 {
2247 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2248 return radv_reset_cmd_buffer(cmd_buffer);
2249 }
2250
2251 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2252 {
2253 struct radv_device *device = cmd_buffer->device;
2254 if (device->gfx_init) {
2255 uint64_t va = radv_buffer_get_va(device->gfx_init);
2256 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2257 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2258 radeon_emit(cmd_buffer->cs, va);
2259 radeon_emit(cmd_buffer->cs, va >> 32);
2260 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2261 } else
2262 si_init_config(cmd_buffer);
2263 }
2264
2265 VkResult radv_BeginCommandBuffer(
2266 VkCommandBuffer commandBuffer,
2267 const VkCommandBufferBeginInfo *pBeginInfo)
2268 {
2269 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2270 VkResult result = VK_SUCCESS;
2271
2272 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2273 /* If the command buffer has already been resetted with
2274 * vkResetCommandBuffer, no need to do it again.
2275 */
2276 result = radv_reset_cmd_buffer(cmd_buffer);
2277 if (result != VK_SUCCESS)
2278 return result;
2279 }
2280
2281 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2282 cmd_buffer->state.last_primitive_reset_en = -1;
2283 cmd_buffer->state.last_index_type = -1;
2284 cmd_buffer->usage_flags = pBeginInfo->flags;
2285
2286 /* setup initial configuration into command buffer */
2287 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2288 switch (cmd_buffer->queue_family_index) {
2289 case RADV_QUEUE_GENERAL:
2290 emit_gfx_buffer_state(cmd_buffer);
2291 break;
2292 case RADV_QUEUE_COMPUTE:
2293 si_init_compute(cmd_buffer);
2294 break;
2295 case RADV_QUEUE_TRANSFER:
2296 default:
2297 break;
2298 }
2299 }
2300
2301 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2302 assert(pBeginInfo->pInheritanceInfo);
2303 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2304 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2305
2306 struct radv_subpass *subpass =
2307 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2308
2309 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2310 if (result != VK_SUCCESS)
2311 return result;
2312
2313 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2314 }
2315
2316 if (unlikely(cmd_buffer->device->trace_bo))
2317 radv_cmd_buffer_trace_emit(cmd_buffer);
2318
2319 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2320
2321 return result;
2322 }
2323
2324 void radv_CmdBindVertexBuffers(
2325 VkCommandBuffer commandBuffer,
2326 uint32_t firstBinding,
2327 uint32_t bindingCount,
2328 const VkBuffer* pBuffers,
2329 const VkDeviceSize* pOffsets)
2330 {
2331 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2332 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2333 bool changed = false;
2334
2335 /* We have to defer setting up vertex buffer since we need the buffer
2336 * stride from the pipeline. */
2337
2338 assert(firstBinding + bindingCount <= MAX_VBS);
2339 for (uint32_t i = 0; i < bindingCount; i++) {
2340 uint32_t idx = firstBinding + i;
2341
2342 if (!changed &&
2343 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2344 vb[idx].offset != pOffsets[i])) {
2345 changed = true;
2346 }
2347
2348 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2349 vb[idx].offset = pOffsets[i];
2350
2351 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2352 vb[idx].buffer->bo, 8);
2353 }
2354
2355 if (!changed) {
2356 /* No state changes. */
2357 return;
2358 }
2359
2360 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2361 }
2362
2363 void radv_CmdBindIndexBuffer(
2364 VkCommandBuffer commandBuffer,
2365 VkBuffer buffer,
2366 VkDeviceSize offset,
2367 VkIndexType indexType)
2368 {
2369 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2370 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2371
2372 if (cmd_buffer->state.index_buffer == index_buffer &&
2373 cmd_buffer->state.index_offset == offset &&
2374 cmd_buffer->state.index_type == indexType) {
2375 /* No state changes. */
2376 return;
2377 }
2378
2379 cmd_buffer->state.index_buffer = index_buffer;
2380 cmd_buffer->state.index_offset = offset;
2381 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2382 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2383 cmd_buffer->state.index_va += index_buffer->offset + offset;
2384
2385 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2386 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2387 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2388 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2389 }
2390
2391
2392 static void
2393 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2394 struct radv_descriptor_set *set, unsigned idx)
2395 {
2396 struct radeon_winsys *ws = cmd_buffer->device->ws;
2397
2398 radv_set_descriptor_set(cmd_buffer, set, idx);
2399 if (!set)
2400 return;
2401
2402 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2403
2404 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2405 if (set->descriptors[j])
2406 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2407
2408 if(set->bo)
2409 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2410 }
2411
2412 void radv_CmdBindDescriptorSets(
2413 VkCommandBuffer commandBuffer,
2414 VkPipelineBindPoint pipelineBindPoint,
2415 VkPipelineLayout _layout,
2416 uint32_t firstSet,
2417 uint32_t descriptorSetCount,
2418 const VkDescriptorSet* pDescriptorSets,
2419 uint32_t dynamicOffsetCount,
2420 const uint32_t* pDynamicOffsets)
2421 {
2422 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2423 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2424 unsigned dyn_idx = 0;
2425
2426 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2427 unsigned idx = i + firstSet;
2428 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2429 radv_bind_descriptor_set(cmd_buffer, set, idx);
2430
2431 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2432 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2433 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2434 assert(dyn_idx < dynamicOffsetCount);
2435
2436 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2437 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2438 dst[0] = va;
2439 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2440 dst[2] = range->size;
2441 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2442 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2443 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2444 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2445 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2446 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2447 cmd_buffer->push_constant_stages |=
2448 set->layout->dynamic_shader_stages;
2449 }
2450 }
2451 }
2452
2453 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2454 struct radv_descriptor_set *set,
2455 struct radv_descriptor_set_layout *layout)
2456 {
2457 set->size = layout->size;
2458 set->layout = layout;
2459
2460 if (cmd_buffer->push_descriptors.capacity < set->size) {
2461 size_t new_size = MAX2(set->size, 1024);
2462 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2463 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2464
2465 free(set->mapped_ptr);
2466 set->mapped_ptr = malloc(new_size);
2467
2468 if (!set->mapped_ptr) {
2469 cmd_buffer->push_descriptors.capacity = 0;
2470 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2471 return false;
2472 }
2473
2474 cmd_buffer->push_descriptors.capacity = new_size;
2475 }
2476
2477 return true;
2478 }
2479
2480 void radv_meta_push_descriptor_set(
2481 struct radv_cmd_buffer* cmd_buffer,
2482 VkPipelineBindPoint pipelineBindPoint,
2483 VkPipelineLayout _layout,
2484 uint32_t set,
2485 uint32_t descriptorWriteCount,
2486 const VkWriteDescriptorSet* pDescriptorWrites)
2487 {
2488 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2489 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2490 unsigned bo_offset;
2491
2492 assert(set == 0);
2493 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2494
2495 push_set->size = layout->set[set].layout->size;
2496 push_set->layout = layout->set[set].layout;
2497
2498 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2499 &bo_offset,
2500 (void**) &push_set->mapped_ptr))
2501 return;
2502
2503 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2504 push_set->va += bo_offset;
2505
2506 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2507 radv_descriptor_set_to_handle(push_set),
2508 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2509
2510 radv_set_descriptor_set(cmd_buffer, push_set, set);
2511 }
2512
2513 void radv_CmdPushDescriptorSetKHR(
2514 VkCommandBuffer commandBuffer,
2515 VkPipelineBindPoint pipelineBindPoint,
2516 VkPipelineLayout _layout,
2517 uint32_t set,
2518 uint32_t descriptorWriteCount,
2519 const VkWriteDescriptorSet* pDescriptorWrites)
2520 {
2521 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2522 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2523 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2524
2525 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2526
2527 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2528 return;
2529
2530 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2531 radv_descriptor_set_to_handle(push_set),
2532 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2533
2534 radv_set_descriptor_set(cmd_buffer, push_set, set);
2535 cmd_buffer->state.push_descriptors_dirty = true;
2536 }
2537
2538 void radv_CmdPushDescriptorSetWithTemplateKHR(
2539 VkCommandBuffer commandBuffer,
2540 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2541 VkPipelineLayout _layout,
2542 uint32_t set,
2543 const void* pData)
2544 {
2545 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2546 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2547 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2548
2549 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2550
2551 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2552 return;
2553
2554 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2555 descriptorUpdateTemplate, pData);
2556
2557 radv_set_descriptor_set(cmd_buffer, push_set, set);
2558 cmd_buffer->state.push_descriptors_dirty = true;
2559 }
2560
2561 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2562 VkPipelineLayout layout,
2563 VkShaderStageFlags stageFlags,
2564 uint32_t offset,
2565 uint32_t size,
2566 const void* pValues)
2567 {
2568 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2569 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2570 cmd_buffer->push_constant_stages |= stageFlags;
2571 }
2572
2573 VkResult radv_EndCommandBuffer(
2574 VkCommandBuffer commandBuffer)
2575 {
2576 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2577
2578 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2579 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2580 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2581 si_emit_cache_flush(cmd_buffer);
2582 }
2583
2584 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2585
2586 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2587 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2588
2589 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2590
2591 return cmd_buffer->record_result;
2592 }
2593
2594 static void
2595 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2596 {
2597 struct radv_shader_variant *compute_shader;
2598 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2599 struct radv_device *device = cmd_buffer->device;
2600 unsigned compute_resource_limits;
2601 unsigned waves_per_threadgroup;
2602 uint64_t va;
2603
2604 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2605 return;
2606
2607 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2608
2609 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2610 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2611
2612 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2613 cmd_buffer->cs, 19);
2614
2615 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2616 radeon_emit(cmd_buffer->cs, va >> 8);
2617 radeon_emit(cmd_buffer->cs, va >> 40);
2618
2619 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2620 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2621 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2622
2623
2624 cmd_buffer->compute_scratch_size_needed =
2625 MAX2(cmd_buffer->compute_scratch_size_needed,
2626 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2627
2628 /* change these once we have scratch support */
2629 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2630 S_00B860_WAVES(pipeline->max_waves) |
2631 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2632
2633 /* Calculate best compute resource limits. */
2634 waves_per_threadgroup =
2635 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
2636 compute_shader->info.cs.block_size[1] *
2637 compute_shader->info.cs.block_size[2], 64);
2638 compute_resource_limits =
2639 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
2640
2641 if (device->physical_device->rad_info.chip_class >= CIK) {
2642 unsigned num_cu_per_se =
2643 device->physical_device->rad_info.num_good_compute_units /
2644 device->physical_device->rad_info.max_se;
2645
2646 /* Force even distribution on all SIMDs in CU if the workgroup
2647 * size is 64. This has shown some good improvements if # of
2648 * CUs per SE is not a multiple of 4.
2649 */
2650 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
2651 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
2652 }
2653
2654 radeon_set_sh_reg(cmd_buffer->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
2655 compute_resource_limits);
2656
2657 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2658 radeon_emit(cmd_buffer->cs,
2659 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2660 radeon_emit(cmd_buffer->cs,
2661 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2662 radeon_emit(cmd_buffer->cs,
2663 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2664
2665 assert(cmd_buffer->cs->cdw <= cdw_max);
2666
2667 if (unlikely(cmd_buffer->device->trace_bo))
2668 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2669 }
2670
2671 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2672 {
2673 cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2674 }
2675
2676 void radv_CmdBindPipeline(
2677 VkCommandBuffer commandBuffer,
2678 VkPipelineBindPoint pipelineBindPoint,
2679 VkPipeline _pipeline)
2680 {
2681 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2682 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2683
2684 switch (pipelineBindPoint) {
2685 case VK_PIPELINE_BIND_POINT_COMPUTE:
2686 if (cmd_buffer->state.compute_pipeline == pipeline)
2687 return;
2688 radv_mark_descriptor_sets_dirty(cmd_buffer);
2689
2690 cmd_buffer->state.compute_pipeline = pipeline;
2691 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2692 break;
2693 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2694 if (cmd_buffer->state.pipeline == pipeline)
2695 return;
2696 radv_mark_descriptor_sets_dirty(cmd_buffer);
2697
2698 cmd_buffer->state.pipeline = pipeline;
2699 if (!pipeline)
2700 break;
2701
2702 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2703 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2704
2705 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2706
2707 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2708 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2709 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2710 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2711
2712 if (radv_pipeline_has_tess(pipeline))
2713 cmd_buffer->tess_rings_needed = true;
2714
2715 if (radv_pipeline_has_gs(pipeline)) {
2716 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2717 AC_UD_SCRATCH_RING_OFFSETS);
2718 if (cmd_buffer->ring_offsets_idx == -1)
2719 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2720 else if (loc->sgpr_idx != -1)
2721 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2722 }
2723 break;
2724 default:
2725 assert(!"invalid bind point");
2726 break;
2727 }
2728 }
2729
2730 void radv_CmdSetViewport(
2731 VkCommandBuffer commandBuffer,
2732 uint32_t firstViewport,
2733 uint32_t viewportCount,
2734 const VkViewport* pViewports)
2735 {
2736 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2737 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2738
2739 assert(firstViewport < MAX_VIEWPORTS);
2740 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2741
2742 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2743 pViewports, viewportCount * sizeof(*pViewports));
2744
2745 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2746 }
2747
2748 void radv_CmdSetScissor(
2749 VkCommandBuffer commandBuffer,
2750 uint32_t firstScissor,
2751 uint32_t scissorCount,
2752 const VkRect2D* pScissors)
2753 {
2754 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2755 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2756
2757 assert(firstScissor < MAX_SCISSORS);
2758 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2759
2760 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2761 pScissors, scissorCount * sizeof(*pScissors));
2762 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2763 }
2764
2765 void radv_CmdSetLineWidth(
2766 VkCommandBuffer commandBuffer,
2767 float lineWidth)
2768 {
2769 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2770 cmd_buffer->state.dynamic.line_width = lineWidth;
2771 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2772 }
2773
2774 void radv_CmdSetDepthBias(
2775 VkCommandBuffer commandBuffer,
2776 float depthBiasConstantFactor,
2777 float depthBiasClamp,
2778 float depthBiasSlopeFactor)
2779 {
2780 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2781
2782 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2783 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2784 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2785
2786 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2787 }
2788
2789 void radv_CmdSetBlendConstants(
2790 VkCommandBuffer commandBuffer,
2791 const float blendConstants[4])
2792 {
2793 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2794
2795 memcpy(cmd_buffer->state.dynamic.blend_constants,
2796 blendConstants, sizeof(float) * 4);
2797
2798 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2799 }
2800
2801 void radv_CmdSetDepthBounds(
2802 VkCommandBuffer commandBuffer,
2803 float minDepthBounds,
2804 float maxDepthBounds)
2805 {
2806 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2807
2808 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2809 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2810
2811 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2812 }
2813
2814 void radv_CmdSetStencilCompareMask(
2815 VkCommandBuffer commandBuffer,
2816 VkStencilFaceFlags faceMask,
2817 uint32_t compareMask)
2818 {
2819 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2820
2821 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2822 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2823 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2824 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2825
2826 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2827 }
2828
2829 void radv_CmdSetStencilWriteMask(
2830 VkCommandBuffer commandBuffer,
2831 VkStencilFaceFlags faceMask,
2832 uint32_t writeMask)
2833 {
2834 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2835
2836 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2837 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2838 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2839 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2840
2841 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2842 }
2843
2844 void radv_CmdSetStencilReference(
2845 VkCommandBuffer commandBuffer,
2846 VkStencilFaceFlags faceMask,
2847 uint32_t reference)
2848 {
2849 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2850
2851 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2852 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2853 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2854 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2855
2856 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2857 }
2858
2859 void radv_CmdExecuteCommands(
2860 VkCommandBuffer commandBuffer,
2861 uint32_t commandBufferCount,
2862 const VkCommandBuffer* pCmdBuffers)
2863 {
2864 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2865
2866 assert(commandBufferCount > 0);
2867
2868 /* Emit pending flushes on primary prior to executing secondary */
2869 si_emit_cache_flush(primary);
2870
2871 for (uint32_t i = 0; i < commandBufferCount; i++) {
2872 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2873
2874 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2875 secondary->scratch_size_needed);
2876 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2877 secondary->compute_scratch_size_needed);
2878
2879 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2880 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2881 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2882 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2883 if (secondary->tess_rings_needed)
2884 primary->tess_rings_needed = true;
2885 if (secondary->sample_positions_needed)
2886 primary->sample_positions_needed = true;
2887
2888 if (secondary->ring_offsets_idx != -1) {
2889 if (primary->ring_offsets_idx == -1)
2890 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2891 else
2892 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2893 }
2894 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2895
2896
2897 /* When the secondary command buffer is compute only we don't
2898 * need to re-emit the current graphics pipeline.
2899 */
2900 if (secondary->state.emitted_pipeline) {
2901 primary->state.emitted_pipeline =
2902 secondary->state.emitted_pipeline;
2903 }
2904
2905 /* When the secondary command buffer is graphics only we don't
2906 * need to re-emit the current compute pipeline.
2907 */
2908 if (secondary->state.emitted_compute_pipeline) {
2909 primary->state.emitted_compute_pipeline =
2910 secondary->state.emitted_compute_pipeline;
2911 }
2912
2913 /* Only re-emit the draw packets when needed. */
2914 if (secondary->state.last_primitive_reset_en != -1) {
2915 primary->state.last_primitive_reset_en =
2916 secondary->state.last_primitive_reset_en;
2917 }
2918
2919 if (secondary->state.last_primitive_reset_index) {
2920 primary->state.last_primitive_reset_index =
2921 secondary->state.last_primitive_reset_index;
2922 }
2923
2924 if (secondary->state.last_ia_multi_vgt_param) {
2925 primary->state.last_ia_multi_vgt_param =
2926 secondary->state.last_ia_multi_vgt_param;
2927 }
2928
2929 if (secondary->state.last_index_type != -1) {
2930 primary->state.last_index_type =
2931 secondary->state.last_index_type;
2932 }
2933 }
2934
2935 /* After executing commands from secondary buffers we have to dirty
2936 * some states.
2937 */
2938 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2939 RADV_CMD_DIRTY_INDEX_BUFFER |
2940 RADV_CMD_DIRTY_DYNAMIC_ALL;
2941 radv_mark_descriptor_sets_dirty(primary);
2942 }
2943
2944 VkResult radv_CreateCommandPool(
2945 VkDevice _device,
2946 const VkCommandPoolCreateInfo* pCreateInfo,
2947 const VkAllocationCallbacks* pAllocator,
2948 VkCommandPool* pCmdPool)
2949 {
2950 RADV_FROM_HANDLE(radv_device, device, _device);
2951 struct radv_cmd_pool *pool;
2952
2953 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2954 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2955 if (pool == NULL)
2956 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2957
2958 if (pAllocator)
2959 pool->alloc = *pAllocator;
2960 else
2961 pool->alloc = device->alloc;
2962
2963 list_inithead(&pool->cmd_buffers);
2964 list_inithead(&pool->free_cmd_buffers);
2965
2966 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2967
2968 *pCmdPool = radv_cmd_pool_to_handle(pool);
2969
2970 return VK_SUCCESS;
2971
2972 }
2973
2974 void radv_DestroyCommandPool(
2975 VkDevice _device,
2976 VkCommandPool commandPool,
2977 const VkAllocationCallbacks* pAllocator)
2978 {
2979 RADV_FROM_HANDLE(radv_device, device, _device);
2980 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2981
2982 if (!pool)
2983 return;
2984
2985 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2986 &pool->cmd_buffers, pool_link) {
2987 radv_cmd_buffer_destroy(cmd_buffer);
2988 }
2989
2990 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2991 &pool->free_cmd_buffers, pool_link) {
2992 radv_cmd_buffer_destroy(cmd_buffer);
2993 }
2994
2995 vk_free2(&device->alloc, pAllocator, pool);
2996 }
2997
2998 VkResult radv_ResetCommandPool(
2999 VkDevice device,
3000 VkCommandPool commandPool,
3001 VkCommandPoolResetFlags flags)
3002 {
3003 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3004 VkResult result;
3005
3006 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3007 &pool->cmd_buffers, pool_link) {
3008 result = radv_reset_cmd_buffer(cmd_buffer);
3009 if (result != VK_SUCCESS)
3010 return result;
3011 }
3012
3013 return VK_SUCCESS;
3014 }
3015
3016 void radv_TrimCommandPoolKHR(
3017 VkDevice device,
3018 VkCommandPool commandPool,
3019 VkCommandPoolTrimFlagsKHR flags)
3020 {
3021 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3022
3023 if (!pool)
3024 return;
3025
3026 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3027 &pool->free_cmd_buffers, pool_link) {
3028 radv_cmd_buffer_destroy(cmd_buffer);
3029 }
3030 }
3031
3032 void radv_CmdBeginRenderPass(
3033 VkCommandBuffer commandBuffer,
3034 const VkRenderPassBeginInfo* pRenderPassBegin,
3035 VkSubpassContents contents)
3036 {
3037 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3038 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3039 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3040
3041 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3042 cmd_buffer->cs, 2048);
3043 MAYBE_UNUSED VkResult result;
3044
3045 cmd_buffer->state.framebuffer = framebuffer;
3046 cmd_buffer->state.pass = pass;
3047 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3048
3049 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3050 if (result != VK_SUCCESS)
3051 return;
3052
3053 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3054 assert(cmd_buffer->cs->cdw <= cdw_max);
3055
3056 radv_cmd_buffer_clear_subpass(cmd_buffer);
3057 }
3058
3059 void radv_CmdNextSubpass(
3060 VkCommandBuffer commandBuffer,
3061 VkSubpassContents contents)
3062 {
3063 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3064
3065 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3066
3067 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3068 2048);
3069
3070 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3071 radv_cmd_buffer_clear_subpass(cmd_buffer);
3072 }
3073
3074 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3075 {
3076 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3077 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3078 if (!pipeline->shaders[stage])
3079 continue;
3080 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3081 if (loc->sgpr_idx == -1)
3082 continue;
3083 uint32_t base_reg = pipeline->user_data_0[stage];
3084 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3085
3086 }
3087 if (pipeline->gs_copy_shader) {
3088 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3089 if (loc->sgpr_idx != -1) {
3090 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3091 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3092 }
3093 }
3094 }
3095
3096 static void
3097 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3098 uint32_t vertex_count)
3099 {
3100 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3101 radeon_emit(cmd_buffer->cs, vertex_count);
3102 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3103 S_0287F0_USE_OPAQUE(0));
3104 }
3105
3106 static void
3107 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3108 uint64_t index_va,
3109 uint32_t index_count)
3110 {
3111 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3112 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3113 radeon_emit(cmd_buffer->cs, index_va);
3114 radeon_emit(cmd_buffer->cs, index_va >> 32);
3115 radeon_emit(cmd_buffer->cs, index_count);
3116 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3117 }
3118
3119 static void
3120 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3121 bool indexed,
3122 uint32_t draw_count,
3123 uint64_t count_va,
3124 uint32_t stride)
3125 {
3126 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3127 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3128 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3129 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3130 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3131 assert(base_reg);
3132
3133 if (draw_count == 1 && !count_va && !draw_id_enable) {
3134 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3135 PKT3_DRAW_INDIRECT, 3, false));
3136 radeon_emit(cs, 0);
3137 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3138 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3139 radeon_emit(cs, di_src_sel);
3140 } else {
3141 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3142 PKT3_DRAW_INDIRECT_MULTI,
3143 8, false));
3144 radeon_emit(cs, 0);
3145 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3146 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3147 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3148 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3149 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3150 radeon_emit(cs, draw_count); /* count */
3151 radeon_emit(cs, count_va); /* count_addr */
3152 radeon_emit(cs, count_va >> 32);
3153 radeon_emit(cs, stride); /* stride */
3154 radeon_emit(cs, di_src_sel);
3155 }
3156 }
3157
3158 struct radv_draw_info {
3159 /**
3160 * Number of vertices.
3161 */
3162 uint32_t count;
3163
3164 /**
3165 * Index of the first vertex.
3166 */
3167 int32_t vertex_offset;
3168
3169 /**
3170 * First instance id.
3171 */
3172 uint32_t first_instance;
3173
3174 /**
3175 * Number of instances.
3176 */
3177 uint32_t instance_count;
3178
3179 /**
3180 * First index (indexed draws only).
3181 */
3182 uint32_t first_index;
3183
3184 /**
3185 * Whether it's an indexed draw.
3186 */
3187 bool indexed;
3188
3189 /**
3190 * Indirect draw parameters resource.
3191 */
3192 struct radv_buffer *indirect;
3193 uint64_t indirect_offset;
3194 uint32_t stride;
3195
3196 /**
3197 * Draw count parameters resource.
3198 */
3199 struct radv_buffer *count_buffer;
3200 uint64_t count_buffer_offset;
3201 };
3202
3203 static void
3204 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3205 const struct radv_draw_info *info)
3206 {
3207 struct radv_cmd_state *state = &cmd_buffer->state;
3208 struct radeon_winsys *ws = cmd_buffer->device->ws;
3209 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3210
3211 if (info->indirect) {
3212 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3213 uint64_t count_va = 0;
3214
3215 va += info->indirect->offset + info->indirect_offset;
3216
3217 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3218
3219 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3220 radeon_emit(cs, 1);
3221 radeon_emit(cs, va);
3222 radeon_emit(cs, va >> 32);
3223
3224 if (info->count_buffer) {
3225 count_va = radv_buffer_get_va(info->count_buffer->bo);
3226 count_va += info->count_buffer->offset +
3227 info->count_buffer_offset;
3228
3229 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3230 }
3231
3232 if (!state->subpass->view_mask) {
3233 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3234 info->indexed,
3235 info->count,
3236 count_va,
3237 info->stride);
3238 } else {
3239 unsigned i;
3240 for_each_bit(i, state->subpass->view_mask) {
3241 radv_emit_view_index(cmd_buffer, i);
3242
3243 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3244 info->indexed,
3245 info->count,
3246 count_va,
3247 info->stride);
3248 }
3249 }
3250 } else {
3251 assert(state->pipeline->graphics.vtx_base_sgpr);
3252 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3253 state->pipeline->graphics.vtx_emit_num);
3254 radeon_emit(cs, info->vertex_offset);
3255 radeon_emit(cs, info->first_instance);
3256 if (state->pipeline->graphics.vtx_emit_num == 3)
3257 radeon_emit(cs, 0);
3258
3259 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3260 radeon_emit(cs, info->instance_count);
3261
3262 if (info->indexed) {
3263 int index_size = state->index_type ? 4 : 2;
3264 uint64_t index_va;
3265
3266 index_va = state->index_va;
3267 index_va += info->first_index * index_size;
3268
3269 if (!state->subpass->view_mask) {
3270 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3271 index_va,
3272 info->count);
3273 } else {
3274 unsigned i;
3275 for_each_bit(i, state->subpass->view_mask) {
3276 radv_emit_view_index(cmd_buffer, i);
3277
3278 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3279 index_va,
3280 info->count);
3281 }
3282 }
3283 } else {
3284 if (!state->subpass->view_mask) {
3285 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3286 } else {
3287 unsigned i;
3288 for_each_bit(i, state->subpass->view_mask) {
3289 radv_emit_view_index(cmd_buffer, i);
3290
3291 radv_cs_emit_draw_packet(cmd_buffer,
3292 info->count);
3293 }
3294 }
3295 }
3296 }
3297 }
3298
3299 static void
3300 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3301 const struct radv_draw_info *info)
3302 {
3303 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3304 radv_emit_graphics_pipeline(cmd_buffer);
3305
3306 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3307 radv_emit_framebuffer_state(cmd_buffer);
3308
3309 if (info->indexed) {
3310 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3311 radv_emit_index_buffer(cmd_buffer);
3312 } else {
3313 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3314 * so the state must be re-emitted before the next indexed
3315 * draw.
3316 */
3317 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3318 cmd_buffer->state.last_index_type = -1;
3319 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3320 }
3321 }
3322
3323 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3324
3325 radv_emit_draw_registers(cmd_buffer, info->indexed,
3326 info->instance_count > 1, info->indirect,
3327 info->indirect ? 0 : info->count);
3328 }
3329
3330 static void
3331 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3332 const struct radv_draw_info *info)
3333 {
3334 bool pipeline_is_dirty =
3335 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3336 cmd_buffer->state.pipeline &&
3337 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3338
3339 MAYBE_UNUSED unsigned cdw_max =
3340 radeon_check_space(cmd_buffer->device->ws,
3341 cmd_buffer->cs, 4096);
3342
3343 /* Use optimal packet order based on whether we need to sync the
3344 * pipeline.
3345 */
3346 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3347 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3348 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3349 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3350 /* If we have to wait for idle, set all states first, so that
3351 * all SET packets are processed in parallel with previous draw
3352 * calls. Then upload descriptors, set shader pointers, and
3353 * draw, and prefetch at the end. This ensures that the time
3354 * the CUs are idle is very short. (there are only SET_SH
3355 * packets between the wait and the draw)
3356 */
3357 radv_emit_all_graphics_states(cmd_buffer, info);
3358 si_emit_cache_flush(cmd_buffer);
3359 /* <-- CUs are idle here --> */
3360
3361 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3362 return;
3363
3364 radv_emit_draw_packets(cmd_buffer, info);
3365 /* <-- CUs are busy here --> */
3366
3367 /* Start prefetches after the draw has been started. Both will
3368 * run in parallel, but starting the draw first is more
3369 * important.
3370 */
3371 if (pipeline_is_dirty) {
3372 radv_emit_prefetch(cmd_buffer,
3373 cmd_buffer->state.pipeline);
3374 }
3375 } else {
3376 /* If we don't wait for idle, start prefetches first, then set
3377 * states, and draw at the end.
3378 */
3379 si_emit_cache_flush(cmd_buffer);
3380
3381 if (pipeline_is_dirty) {
3382 radv_emit_prefetch(cmd_buffer,
3383 cmd_buffer->state.pipeline);
3384 }
3385
3386 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3387 return;
3388
3389 radv_emit_all_graphics_states(cmd_buffer, info);
3390 radv_emit_draw_packets(cmd_buffer, info);
3391 }
3392
3393 assert(cmd_buffer->cs->cdw <= cdw_max);
3394 radv_cmd_buffer_after_draw(cmd_buffer);
3395 }
3396
3397 void radv_CmdDraw(
3398 VkCommandBuffer commandBuffer,
3399 uint32_t vertexCount,
3400 uint32_t instanceCount,
3401 uint32_t firstVertex,
3402 uint32_t firstInstance)
3403 {
3404 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3405 struct radv_draw_info info = {};
3406
3407 info.count = vertexCount;
3408 info.instance_count = instanceCount;
3409 info.first_instance = firstInstance;
3410 info.vertex_offset = firstVertex;
3411
3412 radv_draw(cmd_buffer, &info);
3413 }
3414
3415 void radv_CmdDrawIndexed(
3416 VkCommandBuffer commandBuffer,
3417 uint32_t indexCount,
3418 uint32_t instanceCount,
3419 uint32_t firstIndex,
3420 int32_t vertexOffset,
3421 uint32_t firstInstance)
3422 {
3423 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3424 struct radv_draw_info info = {};
3425
3426 info.indexed = true;
3427 info.count = indexCount;
3428 info.instance_count = instanceCount;
3429 info.first_index = firstIndex;
3430 info.vertex_offset = vertexOffset;
3431 info.first_instance = firstInstance;
3432
3433 radv_draw(cmd_buffer, &info);
3434 }
3435
3436 void radv_CmdDrawIndirect(
3437 VkCommandBuffer commandBuffer,
3438 VkBuffer _buffer,
3439 VkDeviceSize offset,
3440 uint32_t drawCount,
3441 uint32_t stride)
3442 {
3443 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3444 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3445 struct radv_draw_info info = {};
3446
3447 info.count = drawCount;
3448 info.indirect = buffer;
3449 info.indirect_offset = offset;
3450 info.stride = stride;
3451
3452 radv_draw(cmd_buffer, &info);
3453 }
3454
3455 void radv_CmdDrawIndexedIndirect(
3456 VkCommandBuffer commandBuffer,
3457 VkBuffer _buffer,
3458 VkDeviceSize offset,
3459 uint32_t drawCount,
3460 uint32_t stride)
3461 {
3462 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3463 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3464 struct radv_draw_info info = {};
3465
3466 info.indexed = true;
3467 info.count = drawCount;
3468 info.indirect = buffer;
3469 info.indirect_offset = offset;
3470 info.stride = stride;
3471
3472 radv_draw(cmd_buffer, &info);
3473 }
3474
3475 void radv_CmdDrawIndirectCountAMD(
3476 VkCommandBuffer commandBuffer,
3477 VkBuffer _buffer,
3478 VkDeviceSize offset,
3479 VkBuffer _countBuffer,
3480 VkDeviceSize countBufferOffset,
3481 uint32_t maxDrawCount,
3482 uint32_t stride)
3483 {
3484 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3485 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3486 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3487 struct radv_draw_info info = {};
3488
3489 info.count = maxDrawCount;
3490 info.indirect = buffer;
3491 info.indirect_offset = offset;
3492 info.count_buffer = count_buffer;
3493 info.count_buffer_offset = countBufferOffset;
3494 info.stride = stride;
3495
3496 radv_draw(cmd_buffer, &info);
3497 }
3498
3499 void radv_CmdDrawIndexedIndirectCountAMD(
3500 VkCommandBuffer commandBuffer,
3501 VkBuffer _buffer,
3502 VkDeviceSize offset,
3503 VkBuffer _countBuffer,
3504 VkDeviceSize countBufferOffset,
3505 uint32_t maxDrawCount,
3506 uint32_t stride)
3507 {
3508 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3509 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3510 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3511 struct radv_draw_info info = {};
3512
3513 info.indexed = true;
3514 info.count = maxDrawCount;
3515 info.indirect = buffer;
3516 info.indirect_offset = offset;
3517 info.count_buffer = count_buffer;
3518 info.count_buffer_offset = countBufferOffset;
3519 info.stride = stride;
3520
3521 radv_draw(cmd_buffer, &info);
3522 }
3523
3524 struct radv_dispatch_info {
3525 /**
3526 * Determine the layout of the grid (in block units) to be used.
3527 */
3528 uint32_t blocks[3];
3529
3530 /**
3531 * Whether it's an unaligned compute dispatch.
3532 */
3533 bool unaligned;
3534
3535 /**
3536 * Indirect compute parameters resource.
3537 */
3538 struct radv_buffer *indirect;
3539 uint64_t indirect_offset;
3540 };
3541
3542 static void
3543 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3544 const struct radv_dispatch_info *info)
3545 {
3546 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3547 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3548 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3549 struct radeon_winsys *ws = cmd_buffer->device->ws;
3550 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3551 struct ac_userdata_info *loc;
3552
3553 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3554 AC_UD_CS_GRID_SIZE);
3555
3556 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3557
3558 if (info->indirect) {
3559 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3560
3561 va += info->indirect->offset + info->indirect_offset;
3562
3563 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3564
3565 if (loc->sgpr_idx != -1) {
3566 for (unsigned i = 0; i < 3; ++i) {
3567 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3568 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3569 COPY_DATA_DST_SEL(COPY_DATA_REG));
3570 radeon_emit(cs, (va + 4 * i));
3571 radeon_emit(cs, (va + 4 * i) >> 32);
3572 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3573 + loc->sgpr_idx * 4) >> 2) + i);
3574 radeon_emit(cs, 0);
3575 }
3576 }
3577
3578 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3579 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3580 PKT3_SHADER_TYPE_S(1));
3581 radeon_emit(cs, va);
3582 radeon_emit(cs, va >> 32);
3583 radeon_emit(cs, dispatch_initiator);
3584 } else {
3585 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3586 PKT3_SHADER_TYPE_S(1));
3587 radeon_emit(cs, 1);
3588 radeon_emit(cs, va);
3589 radeon_emit(cs, va >> 32);
3590
3591 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3592 PKT3_SHADER_TYPE_S(1));
3593 radeon_emit(cs, 0);
3594 radeon_emit(cs, dispatch_initiator);
3595 }
3596 } else {
3597 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3598
3599 if (info->unaligned) {
3600 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3601 unsigned remainder[3];
3602
3603 /* If aligned, these should be an entire block size,
3604 * not 0.
3605 */
3606 remainder[0] = blocks[0] + cs_block_size[0] -
3607 align_u32_npot(blocks[0], cs_block_size[0]);
3608 remainder[1] = blocks[1] + cs_block_size[1] -
3609 align_u32_npot(blocks[1], cs_block_size[1]);
3610 remainder[2] = blocks[2] + cs_block_size[2] -
3611 align_u32_npot(blocks[2], cs_block_size[2]);
3612
3613 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3614 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3615 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3616
3617 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3618 radeon_emit(cs,
3619 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3620 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3621 radeon_emit(cs,
3622 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3623 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3624 radeon_emit(cs,
3625 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3626 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3627
3628 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3629 }
3630
3631 if (loc->sgpr_idx != -1) {
3632 assert(!loc->indirect);
3633 assert(loc->num_sgprs == 3);
3634
3635 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3636 loc->sgpr_idx * 4, 3);
3637 radeon_emit(cs, blocks[0]);
3638 radeon_emit(cs, blocks[1]);
3639 radeon_emit(cs, blocks[2]);
3640 }
3641
3642 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3643 PKT3_SHADER_TYPE_S(1));
3644 radeon_emit(cs, blocks[0]);
3645 radeon_emit(cs, blocks[1]);
3646 radeon_emit(cs, blocks[2]);
3647 radeon_emit(cs, dispatch_initiator);
3648 }
3649
3650 assert(cmd_buffer->cs->cdw <= cdw_max);
3651 }
3652
3653 static void
3654 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3655 {
3656 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3657 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3658 VK_SHADER_STAGE_COMPUTE_BIT);
3659 }
3660
3661 static void
3662 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3663 const struct radv_dispatch_info *info)
3664 {
3665 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3666 bool pipeline_is_dirty = pipeline &&
3667 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3668
3669 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3670 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3671 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3672 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3673 /* If we have to wait for idle, set all states first, so that
3674 * all SET packets are processed in parallel with previous draw
3675 * calls. Then upload descriptors, set shader pointers, and
3676 * dispatch, and prefetch at the end. This ensures that the
3677 * time the CUs are idle is very short. (there are only SET_SH
3678 * packets between the wait and the draw)
3679 */
3680 radv_emit_compute_pipeline(cmd_buffer);
3681 si_emit_cache_flush(cmd_buffer);
3682 /* <-- CUs are idle here --> */
3683
3684 radv_upload_compute_shader_descriptors(cmd_buffer);
3685
3686 radv_emit_dispatch_packets(cmd_buffer, info);
3687 /* <-- CUs are busy here --> */
3688
3689 /* Start prefetches after the dispatch has been started. Both
3690 * will run in parallel, but starting the dispatch first is
3691 * more important.
3692 */
3693 if (pipeline_is_dirty) {
3694 radv_emit_shader_prefetch(cmd_buffer,
3695 pipeline->shaders[MESA_SHADER_COMPUTE]);
3696 }
3697 } else {
3698 /* If we don't wait for idle, start prefetches first, then set
3699 * states, and dispatch at the end.
3700 */
3701 si_emit_cache_flush(cmd_buffer);
3702
3703 if (pipeline_is_dirty) {
3704 radv_emit_shader_prefetch(cmd_buffer,
3705 pipeline->shaders[MESA_SHADER_COMPUTE]);
3706 }
3707
3708 radv_upload_compute_shader_descriptors(cmd_buffer);
3709
3710 radv_emit_compute_pipeline(cmd_buffer);
3711 radv_emit_dispatch_packets(cmd_buffer, info);
3712 }
3713
3714 radv_cmd_buffer_after_draw(cmd_buffer);
3715 }
3716
3717 void radv_CmdDispatch(
3718 VkCommandBuffer commandBuffer,
3719 uint32_t x,
3720 uint32_t y,
3721 uint32_t z)
3722 {
3723 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3724 struct radv_dispatch_info info = {};
3725
3726 info.blocks[0] = x;
3727 info.blocks[1] = y;
3728 info.blocks[2] = z;
3729
3730 radv_dispatch(cmd_buffer, &info);
3731 }
3732
3733 void radv_CmdDispatchIndirect(
3734 VkCommandBuffer commandBuffer,
3735 VkBuffer _buffer,
3736 VkDeviceSize offset)
3737 {
3738 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3739 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3740 struct radv_dispatch_info info = {};
3741
3742 info.indirect = buffer;
3743 info.indirect_offset = offset;
3744
3745 radv_dispatch(cmd_buffer, &info);
3746 }
3747
3748 void radv_unaligned_dispatch(
3749 struct radv_cmd_buffer *cmd_buffer,
3750 uint32_t x,
3751 uint32_t y,
3752 uint32_t z)
3753 {
3754 struct radv_dispatch_info info = {};
3755
3756 info.blocks[0] = x;
3757 info.blocks[1] = y;
3758 info.blocks[2] = z;
3759 info.unaligned = 1;
3760
3761 radv_dispatch(cmd_buffer, &info);
3762 }
3763
3764 void radv_CmdEndRenderPass(
3765 VkCommandBuffer commandBuffer)
3766 {
3767 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3768
3769 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3770
3771 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3772
3773 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3774 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3775 radv_handle_subpass_image_transition(cmd_buffer,
3776 (VkAttachmentReference){i, layout});
3777 }
3778
3779 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3780
3781 cmd_buffer->state.pass = NULL;
3782 cmd_buffer->state.subpass = NULL;
3783 cmd_buffer->state.attachments = NULL;
3784 cmd_buffer->state.framebuffer = NULL;
3785 }
3786
3787 /*
3788 * For HTILE we have the following interesting clear words:
3789 * 0x0000030f: Uncompressed for depth+stencil HTILE.
3790 * 0x0000000f: Uncompressed for depth only HTILE.
3791 * 0xfffffff0: Clear depth to 1.0
3792 * 0x00000000: Clear depth to 0.0
3793 */
3794 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3795 struct radv_image *image,
3796 const VkImageSubresourceRange *range,
3797 uint32_t clear_word)
3798 {
3799 assert(range->baseMipLevel == 0);
3800 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3801 unsigned layer_count = radv_get_layerCount(image, range);
3802 uint64_t size = image->surface.htile_slice_size * layer_count;
3803 uint64_t offset = image->offset + image->htile_offset +
3804 image->surface.htile_slice_size * range->baseArrayLayer;
3805 struct radv_cmd_state *state = &cmd_buffer->state;
3806
3807 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3808 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3809
3810 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3811 size, clear_word);
3812
3813 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3814 }
3815
3816 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3817 struct radv_image *image,
3818 VkImageLayout src_layout,
3819 VkImageLayout dst_layout,
3820 unsigned src_queue_mask,
3821 unsigned dst_queue_mask,
3822 const VkImageSubresourceRange *range,
3823 VkImageAspectFlags pending_clears)
3824 {
3825 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3826 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3827 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3828 cmd_buffer->state.render_area.extent.width == image->info.width &&
3829 cmd_buffer->state.render_area.extent.height == image->info.height) {
3830 /* The clear will initialize htile. */
3831 return;
3832 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3833 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3834 /* TODO: merge with the clear if applicable */
3835 radv_initialize_htile(cmd_buffer, image, range, 0);
3836 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3837 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3838 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0x30f : 0xf;
3839 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3840 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3841 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3842 VkImageSubresourceRange local_range = *range;
3843 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3844 local_range.baseMipLevel = 0;
3845 local_range.levelCount = 1;
3846
3847 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3848 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3849
3850 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3851
3852 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3853 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3854 }
3855 }
3856
3857 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3858 struct radv_image *image, uint32_t value)
3859 {
3860 struct radv_cmd_state *state = &cmd_buffer->state;
3861
3862 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3863 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3864
3865 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3866 image->offset + image->cmask.offset,
3867 image->cmask.size, value);
3868
3869 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3870 }
3871
3872 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3873 struct radv_image *image,
3874 VkImageLayout src_layout,
3875 VkImageLayout dst_layout,
3876 unsigned src_queue_mask,
3877 unsigned dst_queue_mask,
3878 const VkImageSubresourceRange *range)
3879 {
3880 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3881 if (image->fmask.size)
3882 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3883 else
3884 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3885 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3886 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3887 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3888 }
3889 }
3890
3891 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3892 struct radv_image *image, uint32_t value)
3893 {
3894 struct radv_cmd_state *state = &cmd_buffer->state;
3895
3896 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3897 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3898
3899 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3900 image->offset + image->dcc_offset,
3901 image->surface.dcc_size, value);
3902
3903 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3904 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3905 }
3906
3907 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3908 struct radv_image *image,
3909 VkImageLayout src_layout,
3910 VkImageLayout dst_layout,
3911 unsigned src_queue_mask,
3912 unsigned dst_queue_mask,
3913 const VkImageSubresourceRange *range)
3914 {
3915 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3916 radv_initialize_dcc(cmd_buffer, image,
3917 radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ?
3918 0x20202020u : 0xffffffffu);
3919 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3920 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3921 radv_decompress_dcc(cmd_buffer, image, range);
3922 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3923 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3924 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3925 }
3926 }
3927
3928 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3929 struct radv_image *image,
3930 VkImageLayout src_layout,
3931 VkImageLayout dst_layout,
3932 uint32_t src_family,
3933 uint32_t dst_family,
3934 const VkImageSubresourceRange *range,
3935 VkImageAspectFlags pending_clears)
3936 {
3937 if (image->exclusive && src_family != dst_family) {
3938 /* This is an acquire or a release operation and there will be
3939 * a corresponding release/acquire. Do the transition in the
3940 * most flexible queue. */
3941
3942 assert(src_family == cmd_buffer->queue_family_index ||
3943 dst_family == cmd_buffer->queue_family_index);
3944
3945 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3946 return;
3947
3948 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3949 (src_family == RADV_QUEUE_GENERAL ||
3950 dst_family == RADV_QUEUE_GENERAL))
3951 return;
3952 }
3953
3954 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3955 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3956
3957 if (image->surface.htile_size)
3958 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3959 dst_layout, src_queue_mask,
3960 dst_queue_mask, range,
3961 pending_clears);
3962
3963 if (image->cmask.size || image->fmask.size)
3964 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3965 dst_layout, src_queue_mask,
3966 dst_queue_mask, range);
3967
3968 if (image->surface.dcc_size)
3969 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3970 dst_layout, src_queue_mask,
3971 dst_queue_mask, range);
3972 }
3973
3974 void radv_CmdPipelineBarrier(
3975 VkCommandBuffer commandBuffer,
3976 VkPipelineStageFlags srcStageMask,
3977 VkPipelineStageFlags destStageMask,
3978 VkBool32 byRegion,
3979 uint32_t memoryBarrierCount,
3980 const VkMemoryBarrier* pMemoryBarriers,
3981 uint32_t bufferMemoryBarrierCount,
3982 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3983 uint32_t imageMemoryBarrierCount,
3984 const VkImageMemoryBarrier* pImageMemoryBarriers)
3985 {
3986 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3987 enum radv_cmd_flush_bits src_flush_bits = 0;
3988 enum radv_cmd_flush_bits dst_flush_bits = 0;
3989
3990 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3991 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3992 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3993 NULL);
3994 }
3995
3996 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3997 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3998 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3999 NULL);
4000 }
4001
4002 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4003 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4004 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
4005 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4006 image);
4007 }
4008
4009 radv_stage_flush(cmd_buffer, srcStageMask);
4010 cmd_buffer->state.flush_bits |= src_flush_bits;
4011
4012 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4013 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4014 radv_handle_image_transition(cmd_buffer, image,
4015 pImageMemoryBarriers[i].oldLayout,
4016 pImageMemoryBarriers[i].newLayout,
4017 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4018 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4019 &pImageMemoryBarriers[i].subresourceRange,
4020 0);
4021 }
4022
4023 cmd_buffer->state.flush_bits |= dst_flush_bits;
4024 }
4025
4026
4027 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4028 struct radv_event *event,
4029 VkPipelineStageFlags stageMask,
4030 unsigned value)
4031 {
4032 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4033 uint64_t va = radv_buffer_get_va(event->bo);
4034
4035 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4036
4037 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4038
4039 /* TODO: this is overkill. Probably should figure something out from
4040 * the stage mask. */
4041
4042 si_cs_emit_write_event_eop(cs,
4043 cmd_buffer->state.predicating,
4044 cmd_buffer->device->physical_device->rad_info.chip_class,
4045 radv_cmd_buffer_uses_mec(cmd_buffer),
4046 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4047 1, va, 2, value);
4048
4049 assert(cmd_buffer->cs->cdw <= cdw_max);
4050 }
4051
4052 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4053 VkEvent _event,
4054 VkPipelineStageFlags stageMask)
4055 {
4056 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4057 RADV_FROM_HANDLE(radv_event, event, _event);
4058
4059 write_event(cmd_buffer, event, stageMask, 1);
4060 }
4061
4062 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4063 VkEvent _event,
4064 VkPipelineStageFlags stageMask)
4065 {
4066 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4067 RADV_FROM_HANDLE(radv_event, event, _event);
4068
4069 write_event(cmd_buffer, event, stageMask, 0);
4070 }
4071
4072 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4073 uint32_t eventCount,
4074 const VkEvent* pEvents,
4075 VkPipelineStageFlags srcStageMask,
4076 VkPipelineStageFlags dstStageMask,
4077 uint32_t memoryBarrierCount,
4078 const VkMemoryBarrier* pMemoryBarriers,
4079 uint32_t bufferMemoryBarrierCount,
4080 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4081 uint32_t imageMemoryBarrierCount,
4082 const VkImageMemoryBarrier* pImageMemoryBarriers)
4083 {
4084 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4085 struct radeon_winsys_cs *cs = cmd_buffer->cs;
4086
4087 for (unsigned i = 0; i < eventCount; ++i) {
4088 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4089 uint64_t va = radv_buffer_get_va(event->bo);
4090
4091 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4092
4093 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4094
4095 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4096 assert(cmd_buffer->cs->cdw <= cdw_max);
4097 }
4098
4099
4100 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4101 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4102
4103 radv_handle_image_transition(cmd_buffer, image,
4104 pImageMemoryBarriers[i].oldLayout,
4105 pImageMemoryBarriers[i].newLayout,
4106 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4107 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4108 &pImageMemoryBarriers[i].subresourceRange,
4109 0);
4110 }
4111
4112 /* TODO: figure out how to do memory barriers without waiting */
4113 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4114 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4115 RADV_CMD_FLAG_INV_VMEM_L1 |
4116 RADV_CMD_FLAG_INV_SMEM_L1;
4117 }