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radv/gfx10: do not allocate space for the ZPASS_DONE bug
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 struct radv_sample_locations_state *sample_locs);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109 dest->sample_location.count = src->sample_location.count;
110
111 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
112 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
113 src->viewport.count * sizeof(VkViewport))) {
114 typed_memcpy(dest->viewport.viewports,
115 src->viewport.viewports,
116 src->viewport.count);
117 dest_mask |= RADV_DYNAMIC_VIEWPORT;
118 }
119 }
120
121 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
122 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
123 src->scissor.count * sizeof(VkRect2D))) {
124 typed_memcpy(dest->scissor.scissors,
125 src->scissor.scissors, src->scissor.count);
126 dest_mask |= RADV_DYNAMIC_SCISSOR;
127 }
128 }
129
130 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
131 if (dest->line_width != src->line_width) {
132 dest->line_width = src->line_width;
133 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
134 }
135 }
136
137 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
138 if (memcmp(&dest->depth_bias, &src->depth_bias,
139 sizeof(src->depth_bias))) {
140 dest->depth_bias = src->depth_bias;
141 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
142 }
143 }
144
145 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
146 if (memcmp(&dest->blend_constants, &src->blend_constants,
147 sizeof(src->blend_constants))) {
148 typed_memcpy(dest->blend_constants,
149 src->blend_constants, 4);
150 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
151 }
152 }
153
154 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
155 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
156 sizeof(src->depth_bounds))) {
157 dest->depth_bounds = src->depth_bounds;
158 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
159 }
160 }
161
162 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
163 if (memcmp(&dest->stencil_compare_mask,
164 &src->stencil_compare_mask,
165 sizeof(src->stencil_compare_mask))) {
166 dest->stencil_compare_mask = src->stencil_compare_mask;
167 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
168 }
169 }
170
171 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
172 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
173 sizeof(src->stencil_write_mask))) {
174 dest->stencil_write_mask = src->stencil_write_mask;
175 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
176 }
177 }
178
179 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
180 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
181 sizeof(src->stencil_reference))) {
182 dest->stencil_reference = src->stencil_reference;
183 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
184 }
185 }
186
187 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
188 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
189 src->discard_rectangle.count * sizeof(VkRect2D))) {
190 typed_memcpy(dest->discard_rectangle.rectangles,
191 src->discard_rectangle.rectangles,
192 src->discard_rectangle.count);
193 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
194 }
195 }
196
197 if (copy_mask & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
198 if (dest->sample_location.per_pixel != src->sample_location.per_pixel ||
199 dest->sample_location.grid_size.width != src->sample_location.grid_size.width ||
200 dest->sample_location.grid_size.height != src->sample_location.grid_size.height ||
201 memcmp(&dest->sample_location.locations,
202 &src->sample_location.locations,
203 src->sample_location.count * sizeof(VkSampleLocationEXT))) {
204 dest->sample_location.per_pixel = src->sample_location.per_pixel;
205 dest->sample_location.grid_size = src->sample_location.grid_size;
206 typed_memcpy(dest->sample_location.locations,
207 src->sample_location.locations,
208 src->sample_location.count);
209 dest_mask |= RADV_DYNAMIC_SAMPLE_LOCATIONS;
210 }
211 }
212
213 cmd_buffer->state.dirty |= dest_mask;
214 }
215
216 static void
217 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
218 struct radv_pipeline *pipeline)
219 {
220 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
221 struct radv_shader_info *info;
222
223 if (!pipeline->streamout_shader)
224 return;
225
226 info = &pipeline->streamout_shader->info.info;
227 for (int i = 0; i < MAX_SO_BUFFERS; i++)
228 so->stride_in_dw[i] = info->so.strides[i];
229
230 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
231 }
232
233 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
234 {
235 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
236 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
237 }
238
239 enum ring_type radv_queue_family_to_ring(int f) {
240 switch (f) {
241 case RADV_QUEUE_GENERAL:
242 return RING_GFX;
243 case RADV_QUEUE_COMPUTE:
244 return RING_COMPUTE;
245 case RADV_QUEUE_TRANSFER:
246 return RING_DMA;
247 default:
248 unreachable("Unknown queue family");
249 }
250 }
251
252 static VkResult radv_create_cmd_buffer(
253 struct radv_device * device,
254 struct radv_cmd_pool * pool,
255 VkCommandBufferLevel level,
256 VkCommandBuffer* pCommandBuffer)
257 {
258 struct radv_cmd_buffer *cmd_buffer;
259 unsigned ring;
260 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
262 if (cmd_buffer == NULL)
263 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
264
265 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 cmd_buffer->device = device;
267 cmd_buffer->pool = pool;
268 cmd_buffer->level = level;
269
270 if (pool) {
271 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
272 cmd_buffer->queue_family_index = pool->queue_family_index;
273
274 } else {
275 /* Init the pool_link so we can safely call list_del when we destroy
276 * the command buffer
277 */
278 list_inithead(&cmd_buffer->pool_link);
279 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
280 }
281
282 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
283
284 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
285 if (!cmd_buffer->cs) {
286 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
287 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
288 }
289
290 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
291
292 list_inithead(&cmd_buffer->upload.list);
293
294 return VK_SUCCESS;
295 }
296
297 static void
298 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
299 {
300 list_del(&cmd_buffer->pool_link);
301
302 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
303 &cmd_buffer->upload.list, list) {
304 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
305 list_del(&up->list);
306 free(up);
307 }
308
309 if (cmd_buffer->upload.upload_bo)
310 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
311 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
312
313 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
314 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
315
316 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
317 }
318
319 static VkResult
320 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
321 {
322 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
323
324 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
325 &cmd_buffer->upload.list, list) {
326 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
327 list_del(&up->list);
328 free(up);
329 }
330
331 cmd_buffer->push_constant_stages = 0;
332 cmd_buffer->scratch_size_needed = 0;
333 cmd_buffer->compute_scratch_size_needed = 0;
334 cmd_buffer->esgs_ring_size_needed = 0;
335 cmd_buffer->gsvs_ring_size_needed = 0;
336 cmd_buffer->tess_rings_needed = false;
337 cmd_buffer->sample_positions_needed = false;
338
339 if (cmd_buffer->upload.upload_bo)
340 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
341 cmd_buffer->upload.upload_bo);
342 cmd_buffer->upload.offset = 0;
343
344 cmd_buffer->record_result = VK_SUCCESS;
345
346 memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
347
348 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
349 cmd_buffer->descriptors[i].dirty = 0;
350 cmd_buffer->descriptors[i].valid = 0;
351 cmd_buffer->descriptors[i].push_dirty = false;
352 }
353
354 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
355 cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
356 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
357 unsigned fence_offset, eop_bug_offset;
358 void *fence_ptr;
359
360 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
361 &fence_ptr);
362
363 cmd_buffer->gfx9_fence_va =
364 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
365 cmd_buffer->gfx9_fence_va += fence_offset;
366
367 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
368 /* Allocate a buffer for the EOP bug on GFX9. */
369 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
370 &eop_bug_offset, &fence_ptr);
371 cmd_buffer->gfx9_eop_bug_va =
372 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
373 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
374 }
375 }
376
377 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
378
379 return cmd_buffer->record_result;
380 }
381
382 static bool
383 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
384 uint64_t min_needed)
385 {
386 uint64_t new_size;
387 struct radeon_winsys_bo *bo;
388 struct radv_cmd_buffer_upload *upload;
389 struct radv_device *device = cmd_buffer->device;
390
391 new_size = MAX2(min_needed, 16 * 1024);
392 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
393
394 bo = device->ws->buffer_create(device->ws,
395 new_size, 4096,
396 RADEON_DOMAIN_GTT,
397 RADEON_FLAG_CPU_ACCESS|
398 RADEON_FLAG_NO_INTERPROCESS_SHARING |
399 RADEON_FLAG_32BIT,
400 RADV_BO_PRIORITY_UPLOAD_BUFFER);
401
402 if (!bo) {
403 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
404 return false;
405 }
406
407 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
408 if (cmd_buffer->upload.upload_bo) {
409 upload = malloc(sizeof(*upload));
410
411 if (!upload) {
412 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
413 device->ws->buffer_destroy(bo);
414 return false;
415 }
416
417 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
418 list_add(&upload->list, &cmd_buffer->upload.list);
419 }
420
421 cmd_buffer->upload.upload_bo = bo;
422 cmd_buffer->upload.size = new_size;
423 cmd_buffer->upload.offset = 0;
424 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
425
426 if (!cmd_buffer->upload.map) {
427 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
428 return false;
429 }
430
431 return true;
432 }
433
434 bool
435 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
436 unsigned size,
437 unsigned alignment,
438 unsigned *out_offset,
439 void **ptr)
440 {
441 assert(util_is_power_of_two_nonzero(alignment));
442
443 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
444 if (offset + size > cmd_buffer->upload.size) {
445 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
446 return false;
447 offset = 0;
448 }
449
450 *out_offset = offset;
451 *ptr = cmd_buffer->upload.map + offset;
452
453 cmd_buffer->upload.offset = offset + size;
454 return true;
455 }
456
457 bool
458 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
459 unsigned size, unsigned alignment,
460 const void *data, unsigned *out_offset)
461 {
462 uint8_t *ptr;
463
464 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
465 out_offset, (void **)&ptr))
466 return false;
467
468 if (ptr)
469 memcpy(ptr, data, size);
470
471 return true;
472 }
473
474 static void
475 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
476 unsigned count, const uint32_t *data)
477 {
478 struct radeon_cmdbuf *cs = cmd_buffer->cs;
479
480 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
481
482 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
483 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
484 S_370_WR_CONFIRM(1) |
485 S_370_ENGINE_SEL(V_370_ME));
486 radeon_emit(cs, va);
487 radeon_emit(cs, va >> 32);
488 radeon_emit_array(cs, data, count);
489 }
490
491 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
492 {
493 struct radv_device *device = cmd_buffer->device;
494 struct radeon_cmdbuf *cs = cmd_buffer->cs;
495 uint64_t va;
496
497 va = radv_buffer_get_va(device->trace_bo);
498 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
499 va += 4;
500
501 ++cmd_buffer->state.trace_id;
502 radv_emit_write_data_packet(cmd_buffer, va, 1,
503 &cmd_buffer->state.trace_id);
504
505 radeon_check_space(cmd_buffer->device->ws, cs, 2);
506
507 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
508 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
509 }
510
511 static void
512 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
513 enum radv_cmd_flush_bits flags)
514 {
515 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
516 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
517 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
518
519 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
520
521 /* Force wait for graphics or compute engines to be idle. */
522 si_cs_emit_cache_flush(cmd_buffer->cs,
523 cmd_buffer->device->physical_device->rad_info.chip_class,
524 &cmd_buffer->gfx9_fence_idx,
525 cmd_buffer->gfx9_fence_va,
526 radv_cmd_buffer_uses_mec(cmd_buffer),
527 flags, cmd_buffer->gfx9_eop_bug_va);
528 }
529
530 if (unlikely(cmd_buffer->device->trace_bo))
531 radv_cmd_buffer_trace_emit(cmd_buffer);
532 }
533
534 static void
535 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
536 struct radv_pipeline *pipeline, enum ring_type ring)
537 {
538 struct radv_device *device = cmd_buffer->device;
539 uint32_t data[2];
540 uint64_t va;
541
542 va = radv_buffer_get_va(device->trace_bo);
543
544 switch (ring) {
545 case RING_GFX:
546 va += 8;
547 break;
548 case RING_COMPUTE:
549 va += 16;
550 break;
551 default:
552 assert(!"invalid ring type");
553 }
554
555 data[0] = (uintptr_t)pipeline;
556 data[1] = (uintptr_t)pipeline >> 32;
557
558 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
559 }
560
561 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
562 VkPipelineBindPoint bind_point,
563 struct radv_descriptor_set *set,
564 unsigned idx)
565 {
566 struct radv_descriptor_state *descriptors_state =
567 radv_get_descriptors_state(cmd_buffer, bind_point);
568
569 descriptors_state->sets[idx] = set;
570
571 descriptors_state->valid |= (1u << idx); /* active descriptors */
572 descriptors_state->dirty |= (1u << idx);
573 }
574
575 static void
576 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
577 VkPipelineBindPoint bind_point)
578 {
579 struct radv_descriptor_state *descriptors_state =
580 radv_get_descriptors_state(cmd_buffer, bind_point);
581 struct radv_device *device = cmd_buffer->device;
582 uint32_t data[MAX_SETS * 2] = {};
583 uint64_t va;
584 unsigned i;
585 va = radv_buffer_get_va(device->trace_bo) + 24;
586
587 for_each_bit(i, descriptors_state->valid) {
588 struct radv_descriptor_set *set = descriptors_state->sets[i];
589 data[i * 2] = (uint64_t)(uintptr_t)set;
590 data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
591 }
592
593 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
594 }
595
596 struct radv_userdata_info *
597 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
598 gl_shader_stage stage,
599 int idx)
600 {
601 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
602 return &shader->info.user_sgprs_locs.shader_data[idx];
603 }
604
605 static void
606 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
607 struct radv_pipeline *pipeline,
608 gl_shader_stage stage,
609 int idx, uint64_t va)
610 {
611 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
612 uint32_t base_reg = pipeline->user_data_0[stage];
613 if (loc->sgpr_idx == -1)
614 return;
615
616 assert(loc->num_sgprs == 1);
617
618 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
619 base_reg + loc->sgpr_idx * 4, va, false);
620 }
621
622 static void
623 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
624 struct radv_pipeline *pipeline,
625 struct radv_descriptor_state *descriptors_state,
626 gl_shader_stage stage)
627 {
628 struct radv_device *device = cmd_buffer->device;
629 struct radeon_cmdbuf *cs = cmd_buffer->cs;
630 uint32_t sh_base = pipeline->user_data_0[stage];
631 struct radv_userdata_locations *locs =
632 &pipeline->shaders[stage]->info.user_sgprs_locs;
633 unsigned mask = locs->descriptor_sets_enabled;
634
635 mask &= descriptors_state->dirty & descriptors_state->valid;
636
637 while (mask) {
638 int start, count;
639
640 u_bit_scan_consecutive_range(&mask, &start, &count);
641
642 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
643 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
644
645 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
646 for (int i = 0; i < count; i++) {
647 struct radv_descriptor_set *set =
648 descriptors_state->sets[start + i];
649
650 radv_emit_shader_pointer_body(device, cs, set->va, true);
651 }
652 }
653 }
654
655 /**
656 * Convert the user sample locations to hardware sample locations (the values
657 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
658 */
659 static void
660 radv_convert_user_sample_locs(struct radv_sample_locations_state *state,
661 uint32_t x, uint32_t y, VkOffset2D *sample_locs)
662 {
663 uint32_t x_offset = x % state->grid_size.width;
664 uint32_t y_offset = y % state->grid_size.height;
665 uint32_t num_samples = (uint32_t)state->per_pixel;
666 VkSampleLocationEXT *user_locs;
667 uint32_t pixel_offset;
668
669 pixel_offset = (x_offset + y_offset * state->grid_size.width) * num_samples;
670
671 assert(pixel_offset <= MAX_SAMPLE_LOCATIONS);
672 user_locs = &state->locations[pixel_offset];
673
674 for (uint32_t i = 0; i < num_samples; i++) {
675 float shifted_pos_x = user_locs[i].x - 0.5;
676 float shifted_pos_y = user_locs[i].y - 0.5;
677
678 int32_t scaled_pos_x = floor(shifted_pos_x * 16);
679 int32_t scaled_pos_y = floor(shifted_pos_y * 16);
680
681 sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7);
682 sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7);
683 }
684 }
685
686 /**
687 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
688 * locations.
689 */
690 static void
691 radv_compute_sample_locs_pixel(uint32_t num_samples, VkOffset2D *sample_locs,
692 uint32_t *sample_locs_pixel)
693 {
694 for (uint32_t i = 0; i < num_samples; i++) {
695 uint32_t sample_reg_idx = i / 4;
696 uint32_t sample_loc_idx = i % 4;
697 int32_t pos_x = sample_locs[i].x;
698 int32_t pos_y = sample_locs[i].y;
699
700 uint32_t shift_x = 8 * sample_loc_idx;
701 uint32_t shift_y = shift_x + 4;
702
703 sample_locs_pixel[sample_reg_idx] |= (pos_x & 0xf) << shift_x;
704 sample_locs_pixel[sample_reg_idx] |= (pos_y & 0xf) << shift_y;
705 }
706 }
707
708 /**
709 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
710 * sample locations.
711 */
712 static uint64_t
713 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer,
714 VkOffset2D *sample_locs,
715 uint32_t num_samples)
716 {
717 uint32_t centroid_priorities[num_samples];
718 uint32_t sample_mask = num_samples - 1;
719 uint32_t distances[num_samples];
720 uint64_t centroid_priority = 0;
721
722 /* Compute the distances from center for each sample. */
723 for (int i = 0; i < num_samples; i++) {
724 distances[i] = (sample_locs[i].x * sample_locs[i].x) +
725 (sample_locs[i].y * sample_locs[i].y);
726 }
727
728 /* Compute the centroid priorities by looking at the distances array. */
729 for (int i = 0; i < num_samples; i++) {
730 uint32_t min_idx = 0;
731
732 for (int j = 1; j < num_samples; j++) {
733 if (distances[j] < distances[min_idx])
734 min_idx = j;
735 }
736
737 centroid_priorities[i] = min_idx;
738 distances[min_idx] = 0xffffffff;
739 }
740
741 /* Compute the final centroid priority. */
742 for (int i = 0; i < 8; i++) {
743 centroid_priority |=
744 centroid_priorities[i & sample_mask] << (i * 4);
745 }
746
747 return centroid_priority << 32 | centroid_priority;
748 }
749
750 /**
751 * Emit the sample locations that are specified with VK_EXT_sample_locations.
752 */
753 static void
754 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
755 {
756 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
757 struct radv_multisample_state *ms = &pipeline->graphics.ms;
758 struct radv_sample_locations_state *sample_location =
759 &cmd_buffer->state.dynamic.sample_location;
760 uint32_t num_samples = (uint32_t)sample_location->per_pixel;
761 struct radeon_cmdbuf *cs = cmd_buffer->cs;
762 uint32_t sample_locs_pixel[4][2] = {};
763 VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
764 uint32_t max_sample_dist = 0;
765 uint64_t centroid_priority;
766
767 if (!cmd_buffer->state.dynamic.sample_location.count)
768 return;
769
770 /* Convert the user sample locations to hardware sample locations. */
771 radv_convert_user_sample_locs(sample_location, 0, 0, sample_locs[0]);
772 radv_convert_user_sample_locs(sample_location, 1, 0, sample_locs[1]);
773 radv_convert_user_sample_locs(sample_location, 0, 1, sample_locs[2]);
774 radv_convert_user_sample_locs(sample_location, 1, 1, sample_locs[3]);
775
776 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
777 for (uint32_t i = 0; i < 4; i++) {
778 radv_compute_sample_locs_pixel(num_samples, sample_locs[i],
779 sample_locs_pixel[i]);
780 }
781
782 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
783 centroid_priority =
784 radv_compute_centroid_priority(cmd_buffer, sample_locs[0],
785 num_samples);
786
787 /* Compute the maximum sample distance from the specified locations. */
788 for (uint32_t i = 0; i < num_samples; i++) {
789 VkOffset2D offset = sample_locs[0][i];
790 max_sample_dist = MAX2(max_sample_dist,
791 MAX2(abs(offset.x), abs(offset.y)));
792 }
793
794 /* Emit the specified user sample locations. */
795 switch (num_samples) {
796 case 2:
797 case 4:
798 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
799 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
800 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
801 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
802 break;
803 case 8:
804 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_pixel[0][0]);
805 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_pixel[1][0]);
806 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_pixel[2][0]);
807 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_pixel[3][0]);
808 radeon_set_context_reg(cs, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs_pixel[0][1]);
809 radeon_set_context_reg(cs, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs_pixel[1][1]);
810 radeon_set_context_reg(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs_pixel[2][1]);
811 radeon_set_context_reg(cs, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs_pixel[3][1]);
812 break;
813 default:
814 unreachable("invalid number of samples");
815 }
816
817 /* Emit the maximum sample distance and the centroid priority. */
818 uint32_t pa_sc_aa_config = ms->pa_sc_aa_config;
819
820 pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
821 pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
822
823 radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1);
824 radeon_emit(cs, pa_sc_aa_config);
825
826 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
827 radeon_emit(cs, centroid_priority);
828 radeon_emit(cs, centroid_priority >> 32);
829
830 /* GFX9: Flush DFSM when the AA mode changes. */
831 if (cmd_buffer->device->dfsm_allowed) {
832 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
833 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
834 }
835
836 cmd_buffer->state.context_roll_without_scissor_emitted = true;
837 }
838
839 static void
840 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
841 struct radv_pipeline *pipeline,
842 gl_shader_stage stage,
843 int idx, int count, uint32_t *values)
844 {
845 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
846 uint32_t base_reg = pipeline->user_data_0[stage];
847 if (loc->sgpr_idx == -1)
848 return;
849
850 assert(loc->num_sgprs == count);
851
852 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
853 radeon_emit_array(cmd_buffer->cs, values, count);
854 }
855
856 static void
857 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
858 struct radv_pipeline *pipeline)
859 {
860 int num_samples = pipeline->graphics.ms.num_samples;
861 struct radv_multisample_state *ms = &pipeline->graphics.ms;
862 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
863
864 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
865 cmd_buffer->sample_positions_needed = true;
866
867 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
868 return;
869
870 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
871 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
872 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
873
874 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
875
876 radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
877
878 /* GFX9: Flush DFSM when the AA mode changes. */
879 if (cmd_buffer->device->dfsm_allowed) {
880 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
881 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
882 }
883
884 cmd_buffer->state.context_roll_without_scissor_emitted = true;
885 }
886
887 static void
888 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
889 struct radv_shader_variant *shader)
890 {
891 uint64_t va;
892
893 if (!shader)
894 return;
895
896 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
897
898 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
899 }
900
901 static void
902 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
903 struct radv_pipeline *pipeline,
904 bool vertex_stage_only)
905 {
906 struct radv_cmd_state *state = &cmd_buffer->state;
907 uint32_t mask = state->prefetch_L2_mask;
908
909 if (vertex_stage_only) {
910 /* Fast prefetch path for starting draws as soon as possible.
911 */
912 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
913 RADV_PREFETCH_VBO_DESCRIPTORS);
914 }
915
916 if (mask & RADV_PREFETCH_VS)
917 radv_emit_shader_prefetch(cmd_buffer,
918 pipeline->shaders[MESA_SHADER_VERTEX]);
919
920 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
921 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
922
923 if (mask & RADV_PREFETCH_TCS)
924 radv_emit_shader_prefetch(cmd_buffer,
925 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
926
927 if (mask & RADV_PREFETCH_TES)
928 radv_emit_shader_prefetch(cmd_buffer,
929 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
930
931 if (mask & RADV_PREFETCH_GS) {
932 radv_emit_shader_prefetch(cmd_buffer,
933 pipeline->shaders[MESA_SHADER_GEOMETRY]);
934 if (radv_pipeline_has_gs_copy_shader(pipeline))
935 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
936 }
937
938 if (mask & RADV_PREFETCH_PS)
939 radv_emit_shader_prefetch(cmd_buffer,
940 pipeline->shaders[MESA_SHADER_FRAGMENT]);
941
942 state->prefetch_L2_mask &= ~mask;
943 }
944
945 static void
946 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
947 {
948 if (!cmd_buffer->device->physical_device->rbplus_allowed)
949 return;
950
951 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
952 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
953 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
954
955 unsigned sx_ps_downconvert = 0;
956 unsigned sx_blend_opt_epsilon = 0;
957 unsigned sx_blend_opt_control = 0;
958
959 for (unsigned i = 0; i < subpass->color_count; ++i) {
960 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
961 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
962 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
963 continue;
964 }
965
966 int idx = subpass->color_attachments[i].attachment;
967 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
968
969 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
970 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
971 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
972 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
973
974 bool has_alpha, has_rgb;
975
976 /* Set if RGB and A are present. */
977 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
978
979 if (format == V_028C70_COLOR_8 ||
980 format == V_028C70_COLOR_16 ||
981 format == V_028C70_COLOR_32)
982 has_rgb = !has_alpha;
983 else
984 has_rgb = true;
985
986 /* Check the colormask and export format. */
987 if (!(colormask & 0x7))
988 has_rgb = false;
989 if (!(colormask & 0x8))
990 has_alpha = false;
991
992 if (spi_format == V_028714_SPI_SHADER_ZERO) {
993 has_rgb = false;
994 has_alpha = false;
995 }
996
997 /* Disable value checking for disabled channels. */
998 if (!has_rgb)
999 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1000 if (!has_alpha)
1001 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1002
1003 /* Enable down-conversion for 32bpp and smaller formats. */
1004 switch (format) {
1005 case V_028C70_COLOR_8:
1006 case V_028C70_COLOR_8_8:
1007 case V_028C70_COLOR_8_8_8_8:
1008 /* For 1 and 2-channel formats, use the superset thereof. */
1009 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
1010 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1011 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1012 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
1013 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
1014 }
1015 break;
1016
1017 case V_028C70_COLOR_5_6_5:
1018 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1019 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
1020 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
1021 }
1022 break;
1023
1024 case V_028C70_COLOR_1_5_5_5:
1025 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1026 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
1027 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
1028 }
1029 break;
1030
1031 case V_028C70_COLOR_4_4_4_4:
1032 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1033 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
1034 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
1035 }
1036 break;
1037
1038 case V_028C70_COLOR_32:
1039 if (swap == V_028C70_SWAP_STD &&
1040 spi_format == V_028714_SPI_SHADER_32_R)
1041 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
1042 else if (swap == V_028C70_SWAP_ALT_REV &&
1043 spi_format == V_028714_SPI_SHADER_32_AR)
1044 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
1045 break;
1046
1047 case V_028C70_COLOR_16:
1048 case V_028C70_COLOR_16_16:
1049 /* For 1-channel formats, use the superset thereof. */
1050 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
1051 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
1052 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
1053 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
1054 if (swap == V_028C70_SWAP_STD ||
1055 swap == V_028C70_SWAP_STD_REV)
1056 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
1057 else
1058 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
1059 }
1060 break;
1061
1062 case V_028C70_COLOR_10_11_11:
1063 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1064 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
1065 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
1066 }
1067 break;
1068
1069 case V_028C70_COLOR_2_10_10_10:
1070 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
1071 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
1072 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
1073 }
1074 break;
1075 }
1076 }
1077
1078 for (unsigned i = subpass->color_count; i < 8; ++i) {
1079 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
1080 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
1081 }
1082 /* TODO: avoid redundantly setting context registers */
1083 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
1084 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
1085 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
1086 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
1087
1088 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1089 }
1090
1091 static void
1092 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1093 {
1094 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1095
1096 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1097 return;
1098
1099 radv_update_multisample_state(cmd_buffer, pipeline);
1100
1101 cmd_buffer->scratch_size_needed =
1102 MAX2(cmd_buffer->scratch_size_needed,
1103 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1104
1105 if (!cmd_buffer->state.emitted_pipeline ||
1106 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1107 pipeline->graphics.can_use_guardband)
1108 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1109
1110 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
1111
1112 if (!cmd_buffer->state.emitted_pipeline ||
1113 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
1114 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
1115 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
1116 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
1117 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
1118 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1119 }
1120
1121 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
1122 if (!pipeline->shaders[i])
1123 continue;
1124
1125 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1126 pipeline->shaders[i]->bo);
1127 }
1128
1129 if (radv_pipeline_has_gs_copy_shader(pipeline))
1130 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1131 pipeline->gs_copy_shader->bo);
1132
1133 if (unlikely(cmd_buffer->device->trace_bo))
1134 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1135
1136 cmd_buffer->state.emitted_pipeline = pipeline;
1137
1138 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1139 }
1140
1141 static void
1142 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1143 {
1144 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1145 cmd_buffer->state.dynamic.viewport.viewports);
1146 }
1147
1148 static void
1149 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1150 {
1151 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1152
1153 si_write_scissors(cmd_buffer->cs, 0, count,
1154 cmd_buffer->state.dynamic.scissor.scissors,
1155 cmd_buffer->state.dynamic.viewport.viewports,
1156 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1157
1158 cmd_buffer->state.context_roll_without_scissor_emitted = false;
1159 }
1160
1161 static void
1162 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1163 {
1164 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1165 return;
1166
1167 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1168 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1169 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1170 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1171 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1172 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1173 S_028214_BR_Y(rect.offset.y + rect.extent.height));
1174 }
1175 }
1176
1177 static void
1178 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1179 {
1180 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1181
1182 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1183 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1184 }
1185
1186 static void
1187 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1188 {
1189 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1190
1191 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1192 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1193 }
1194
1195 static void
1196 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1197 {
1198 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1199
1200 radeon_set_context_reg_seq(cmd_buffer->cs,
1201 R_028430_DB_STENCILREFMASK, 2);
1202 radeon_emit(cmd_buffer->cs,
1203 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1204 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1205 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1206 S_028430_STENCILOPVAL(1));
1207 radeon_emit(cmd_buffer->cs,
1208 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1209 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1210 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1211 S_028434_STENCILOPVAL_BF(1));
1212 }
1213
1214 static void
1215 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1216 {
1217 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1218
1219 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1220 fui(d->depth_bounds.min));
1221 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1222 fui(d->depth_bounds.max));
1223 }
1224
1225 static void
1226 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1227 {
1228 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1229 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1230 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1231
1232
1233 radeon_set_context_reg_seq(cmd_buffer->cs,
1234 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1235 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1236 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1237 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1238 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1239 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1240 }
1241
1242 static void
1243 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1244 int index,
1245 struct radv_attachment_info *att,
1246 struct radv_image_view *iview,
1247 VkImageLayout layout)
1248 {
1249 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
1250 struct radv_color_buffer_info *cb = &att->cb;
1251 uint32_t cb_color_info = cb->cb_color_info;
1252 struct radv_image *image = iview->image;
1253
1254 if (!radv_layout_dcc_compressed(image, layout,
1255 radv_image_queue_family_mask(image,
1256 cmd_buffer->queue_family_index,
1257 cmd_buffer->queue_family_index))) {
1258 cb_color_info &= C_028C70_DCC_ENABLE;
1259 }
1260
1261 if (radv_image_is_tc_compat_cmask(image) &&
1262 (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
1263 radv_is_dcc_decompress_pipeline(cmd_buffer))) {
1264 /* If this bit is set, the FMASK decompression operation
1265 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1266 */
1267 cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
1268 }
1269
1270 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1271 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1272 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1273 radeon_emit(cmd_buffer->cs, 0);
1274 radeon_emit(cmd_buffer->cs, 0);
1275 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1276 radeon_emit(cmd_buffer->cs, cb_color_info);
1277 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1278 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1279 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1280 radeon_emit(cmd_buffer->cs, 0);
1281 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1282 radeon_emit(cmd_buffer->cs, 0);
1283
1284 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
1285 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1286
1287 radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
1288 cb->cb_color_base >> 32);
1289 radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
1290 cb->cb_color_cmask >> 32);
1291 radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
1292 cb->cb_color_fmask >> 32);
1293 radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
1294 cb->cb_dcc_base >> 32);
1295 radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
1296 cb->cb_color_attrib2);
1297 radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
1298 cb->cb_color_attrib3);
1299 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1300 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1301 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1302 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1303 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1304 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1305 radeon_emit(cmd_buffer->cs, cb_color_info);
1306 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1307 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1308 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1309 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1310 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1311 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1312
1313 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1314 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1315 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1316
1317 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1318 cb->cb_mrt_epitch);
1319 } else {
1320 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1321 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1322 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1323 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1324 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1325 radeon_emit(cmd_buffer->cs, cb_color_info);
1326 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1327 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1328 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1329 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1330 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1331 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1332
1333 if (is_vi) { /* DCC BASE */
1334 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1335 }
1336 }
1337
1338 if (radv_dcc_enabled(image, iview->base_mip)) {
1339 /* Drawing with DCC enabled also compresses colorbuffers. */
1340 VkImageSubresourceRange range = {
1341 .aspectMask = iview->aspect_mask,
1342 .baseMipLevel = iview->base_mip,
1343 .levelCount = iview->level_count,
1344 .baseArrayLayer = iview->base_layer,
1345 .layerCount = iview->layer_count,
1346 };
1347
1348 radv_update_dcc_metadata(cmd_buffer, image, &range, true);
1349 }
1350 }
1351
1352 static void
1353 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1354 struct radv_ds_buffer_info *ds,
1355 struct radv_image *image, VkImageLayout layout,
1356 bool requires_cond_exec)
1357 {
1358 uint32_t db_z_info = ds->db_z_info;
1359 uint32_t db_z_info_reg;
1360
1361 if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug ||
1362 !radv_image_is_tc_compat_htile(image))
1363 return;
1364
1365 if (!radv_layout_has_htile(image, layout,
1366 radv_image_queue_family_mask(image,
1367 cmd_buffer->queue_family_index,
1368 cmd_buffer->queue_family_index))) {
1369 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1370 }
1371
1372 db_z_info &= C_028040_ZRANGE_PRECISION;
1373
1374 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1375 db_z_info_reg = R_028038_DB_Z_INFO;
1376 } else {
1377 db_z_info_reg = R_028040_DB_Z_INFO;
1378 }
1379
1380 /* When we don't know the last fast clear value we need to emit a
1381 * conditional packet that will eventually skip the following
1382 * SET_CONTEXT_REG packet.
1383 */
1384 if (requires_cond_exec) {
1385 uint64_t va = radv_buffer_get_va(image->bo);
1386 va += image->offset + image->tc_compat_zrange_offset;
1387
1388 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1389 radeon_emit(cmd_buffer->cs, va);
1390 radeon_emit(cmd_buffer->cs, va >> 32);
1391 radeon_emit(cmd_buffer->cs, 0);
1392 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1393 }
1394
1395 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1396 }
1397
1398 static void
1399 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1400 struct radv_ds_buffer_info *ds,
1401 struct radv_image *image,
1402 VkImageLayout layout)
1403 {
1404 uint32_t db_z_info = ds->db_z_info;
1405 uint32_t db_stencil_info = ds->db_stencil_info;
1406
1407 if (!radv_layout_has_htile(image, layout,
1408 radv_image_queue_family_mask(image,
1409 cmd_buffer->queue_family_index,
1410 cmd_buffer->queue_family_index))) {
1411 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1412 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1413 }
1414
1415 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1416 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1417
1418 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1419 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1420 radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
1421
1422 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
1423 radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
1424 radeon_emit(cmd_buffer->cs, db_z_info);
1425 radeon_emit(cmd_buffer->cs, db_stencil_info);
1426 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1427 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1428 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
1429 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
1430
1431 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
1432 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1433 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1434 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
1435 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
1436 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1437 } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
1438 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1439 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1440 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1441 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1442
1443 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1444 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1445 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1446 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1447 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1448 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1449 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1450 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1451 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1452 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1453 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1454
1455 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1456 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1457 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1458 } else {
1459 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1460
1461 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1462 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1463 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1464 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1465 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1466 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1467 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1468 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1469 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1470 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1471
1472 }
1473
1474 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1475 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1476
1477 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1478 ds->pa_su_poly_offset_db_fmt_cntl);
1479 }
1480
1481 /**
1482 * Update the fast clear depth/stencil values if the image is bound as a
1483 * depth/stencil buffer.
1484 */
1485 static void
1486 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1487 struct radv_image *image,
1488 VkClearDepthStencilValue ds_clear_value,
1489 VkImageAspectFlags aspects)
1490 {
1491 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1492 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1493 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1494 struct radv_attachment_info *att;
1495 uint32_t att_idx;
1496
1497 if (!framebuffer || !subpass)
1498 return;
1499
1500 if (!subpass->depth_stencil_attachment)
1501 return;
1502
1503 att_idx = subpass->depth_stencil_attachment->attachment;
1504 att = &framebuffer->attachments[att_idx];
1505 if (att->attachment->image != image)
1506 return;
1507
1508 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1509 radeon_emit(cs, ds_clear_value.stencil);
1510 radeon_emit(cs, fui(ds_clear_value.depth));
1511
1512 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1513 * only needed when clearing Z to 0.0.
1514 */
1515 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1516 ds_clear_value.depth == 0.0) {
1517 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1518
1519 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1520 layout, false);
1521 }
1522
1523 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1524 }
1525
1526 /**
1527 * Set the clear depth/stencil values to the image's metadata.
1528 */
1529 static void
1530 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1531 struct radv_image *image,
1532 VkClearDepthStencilValue ds_clear_value,
1533 VkImageAspectFlags aspects)
1534 {
1535 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1536 uint64_t va = radv_buffer_get_va(image->bo);
1537 unsigned reg_offset = 0, reg_count = 0;
1538
1539 va += image->offset + image->clear_value_offset;
1540
1541 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1542 ++reg_count;
1543 } else {
1544 ++reg_offset;
1545 va += 4;
1546 }
1547 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1548 ++reg_count;
1549
1550 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
1551 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1552 S_370_WR_CONFIRM(1) |
1553 S_370_ENGINE_SEL(V_370_PFP));
1554 radeon_emit(cs, va);
1555 radeon_emit(cs, va >> 32);
1556 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1557 radeon_emit(cs, ds_clear_value.stencil);
1558 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1559 radeon_emit(cs, fui(ds_clear_value.depth));
1560 }
1561
1562 /**
1563 * Update the TC-compat metadata value for this image.
1564 */
1565 static void
1566 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1567 struct radv_image *image,
1568 uint32_t value)
1569 {
1570 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1571 uint64_t va = radv_buffer_get_va(image->bo);
1572
1573 if (!cmd_buffer->device->physical_device->has_tc_compat_zrange_bug)
1574 return;
1575
1576 va += image->offset + image->tc_compat_zrange_offset;
1577
1578 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
1579 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1580 S_370_WR_CONFIRM(1) |
1581 S_370_ENGINE_SEL(V_370_PFP));
1582 radeon_emit(cs, va);
1583 radeon_emit(cs, va >> 32);
1584 radeon_emit(cs, value);
1585 }
1586
1587 static void
1588 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1589 struct radv_image *image,
1590 VkClearDepthStencilValue ds_clear_value)
1591 {
1592 uint32_t cond_val;
1593
1594 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1595 * depth clear value is 0.0f.
1596 */
1597 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1598
1599 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1600 }
1601
1602 /**
1603 * Update the clear depth/stencil values for this image.
1604 */
1605 void
1606 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1607 struct radv_image *image,
1608 VkClearDepthStencilValue ds_clear_value,
1609 VkImageAspectFlags aspects)
1610 {
1611 assert(radv_image_has_htile(image));
1612
1613 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1614
1615 if (radv_image_is_tc_compat_htile(image) &&
1616 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1617 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1618 ds_clear_value);
1619 }
1620
1621 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1622 aspects);
1623 }
1624
1625 /**
1626 * Load the clear depth/stencil values from the image's metadata.
1627 */
1628 static void
1629 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1630 struct radv_image *image)
1631 {
1632 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1633 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1634 uint64_t va = radv_buffer_get_va(image->bo);
1635 unsigned reg_offset = 0, reg_count = 0;
1636
1637 va += image->offset + image->clear_value_offset;
1638
1639 if (!radv_image_has_htile(image))
1640 return;
1641
1642 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1643 ++reg_count;
1644 } else {
1645 ++reg_offset;
1646 va += 4;
1647 }
1648 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1649 ++reg_count;
1650
1651 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1652
1653 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1654 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1655 radeon_emit(cs, va);
1656 radeon_emit(cs, va >> 32);
1657 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1658 radeon_emit(cs, reg_count);
1659 } else {
1660 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1661 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1662 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1663 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1664 radeon_emit(cs, va);
1665 radeon_emit(cs, va >> 32);
1666 radeon_emit(cs, reg >> 2);
1667 radeon_emit(cs, 0);
1668
1669 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1670 radeon_emit(cs, 0);
1671 }
1672 }
1673
1674 /*
1675 * With DCC some colors don't require CMASK elimination before being
1676 * used as a texture. This sets a predicate value to determine if the
1677 * cmask eliminate is required.
1678 */
1679 void
1680 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1681 struct radv_image *image,
1682 const VkImageSubresourceRange *range, bool value)
1683 {
1684 uint64_t pred_val = value;
1685 uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
1686 uint32_t level_count = radv_get_levelCount(image, range);
1687 uint32_t count = 2 * level_count;
1688
1689 assert(radv_dcc_enabled(image, range->baseMipLevel));
1690
1691 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1692 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1693 S_370_WR_CONFIRM(1) |
1694 S_370_ENGINE_SEL(V_370_PFP));
1695 radeon_emit(cmd_buffer->cs, va);
1696 radeon_emit(cmd_buffer->cs, va >> 32);
1697
1698 for (uint32_t l = 0; l < level_count; l++) {
1699 radeon_emit(cmd_buffer->cs, pred_val);
1700 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1701 }
1702 }
1703
1704 /**
1705 * Update the DCC predicate to reflect the compression state.
1706 */
1707 void
1708 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1709 struct radv_image *image,
1710 const VkImageSubresourceRange *range, bool value)
1711 {
1712 uint64_t pred_val = value;
1713 uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
1714 uint32_t level_count = radv_get_levelCount(image, range);
1715 uint32_t count = 2 * level_count;
1716
1717 assert(radv_dcc_enabled(image, range->baseMipLevel));
1718
1719 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
1720 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1721 S_370_WR_CONFIRM(1) |
1722 S_370_ENGINE_SEL(V_370_PFP));
1723 radeon_emit(cmd_buffer->cs, va);
1724 radeon_emit(cmd_buffer->cs, va >> 32);
1725
1726 for (uint32_t l = 0; l < level_count; l++) {
1727 radeon_emit(cmd_buffer->cs, pred_val);
1728 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1729 }
1730 }
1731
1732 /**
1733 * Update the fast clear color values if the image is bound as a color buffer.
1734 */
1735 static void
1736 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1737 struct radv_image *image,
1738 int cb_idx,
1739 uint32_t color_values[2])
1740 {
1741 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1742 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1743 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1744 struct radv_attachment_info *att;
1745 uint32_t att_idx;
1746
1747 if (!framebuffer || !subpass)
1748 return;
1749
1750 att_idx = subpass->color_attachments[cb_idx].attachment;
1751 if (att_idx == VK_ATTACHMENT_UNUSED)
1752 return;
1753
1754 att = &framebuffer->attachments[att_idx];
1755 if (att->attachment->image != image)
1756 return;
1757
1758 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1759 radeon_emit(cs, color_values[0]);
1760 radeon_emit(cs, color_values[1]);
1761
1762 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1763 }
1764
1765 /**
1766 * Set the clear color values to the image's metadata.
1767 */
1768 static void
1769 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1770 struct radv_image *image,
1771 const VkImageSubresourceRange *range,
1772 uint32_t color_values[2])
1773 {
1774 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1775 uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
1776 uint32_t level_count = radv_get_levelCount(image, range);
1777 uint32_t count = 2 * level_count;
1778
1779 assert(radv_image_has_cmask(image) ||
1780 radv_dcc_enabled(image, range->baseMipLevel));
1781
1782 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
1783 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1784 S_370_WR_CONFIRM(1) |
1785 S_370_ENGINE_SEL(V_370_PFP));
1786 radeon_emit(cs, va);
1787 radeon_emit(cs, va >> 32);
1788
1789 for (uint32_t l = 0; l < level_count; l++) {
1790 radeon_emit(cs, color_values[0]);
1791 radeon_emit(cs, color_values[1]);
1792 }
1793 }
1794
1795 /**
1796 * Update the clear color values for this image.
1797 */
1798 void
1799 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1800 const struct radv_image_view *iview,
1801 int cb_idx,
1802 uint32_t color_values[2])
1803 {
1804 struct radv_image *image = iview->image;
1805 VkImageSubresourceRange range = {
1806 .aspectMask = iview->aspect_mask,
1807 .baseMipLevel = iview->base_mip,
1808 .levelCount = iview->level_count,
1809 .baseArrayLayer = iview->base_layer,
1810 .layerCount = iview->layer_count,
1811 };
1812
1813 assert(radv_image_has_cmask(image) ||
1814 radv_dcc_enabled(image, iview->base_mip));
1815
1816 radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
1817
1818 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1819 color_values);
1820 }
1821
1822 /**
1823 * Load the clear color values from the image's metadata.
1824 */
1825 static void
1826 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1827 struct radv_image_view *iview,
1828 int cb_idx)
1829 {
1830 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1831 struct radv_image *image = iview->image;
1832 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
1833
1834 if (!radv_image_has_cmask(image) &&
1835 !radv_dcc_enabled(image, iview->base_mip))
1836 return;
1837
1838 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1839
1840 if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1841 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1842 radeon_emit(cs, va);
1843 radeon_emit(cs, va >> 32);
1844 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1845 radeon_emit(cs, 2);
1846 } else {
1847 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1848 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1849 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1850 COPY_DATA_COUNT_SEL);
1851 radeon_emit(cs, va);
1852 radeon_emit(cs, va >> 32);
1853 radeon_emit(cs, reg >> 2);
1854 radeon_emit(cs, 0);
1855
1856 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1857 radeon_emit(cs, 0);
1858 }
1859 }
1860
1861 static void
1862 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1863 {
1864 int i;
1865 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1866 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1867
1868 /* this may happen for inherited secondary recording */
1869 if (!framebuffer)
1870 return;
1871
1872 for (i = 0; i < 8; ++i) {
1873 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1874 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1875 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1876 continue;
1877 }
1878
1879 int idx = subpass->color_attachments[i].attachment;
1880 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1881 struct radv_image_view *iview = att->attachment;
1882 VkImageLayout layout = subpass->color_attachments[i].layout;
1883
1884 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1885
1886 assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
1887 VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
1888 radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
1889
1890 radv_load_color_clear_metadata(cmd_buffer, iview, i);
1891 }
1892
1893 if (subpass->depth_stencil_attachment) {
1894 int idx = subpass->depth_stencil_attachment->attachment;
1895 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1896 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1897 struct radv_image *image = att->attachment->image;
1898 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1899 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1900 cmd_buffer->queue_family_index,
1901 cmd_buffer->queue_family_index);
1902 /* We currently don't support writing decompressed HTILE */
1903 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1904 radv_layout_is_htile_compressed(image, layout, queue_mask));
1905
1906 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1907
1908 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1909 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1910 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1911 }
1912 radv_load_ds_clear_metadata(cmd_buffer, image);
1913 } else {
1914 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
1915 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1916 else
1917 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1918
1919 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1920 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1921 }
1922 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1923 S_028208_BR_X(framebuffer->width) |
1924 S_028208_BR_Y(framebuffer->height));
1925
1926 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
1927 bool disable_constant_encode =
1928 cmd_buffer->device->physical_device->has_dcc_constant_encode;
1929 enum chip_class chip_class =
1930 cmd_buffer->device->physical_device->rad_info.chip_class;
1931 uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
1932
1933 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1934 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
1935 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
1936 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
1937 }
1938
1939 if (cmd_buffer->device->dfsm_allowed) {
1940 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1941 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1942 }
1943
1944 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1945 }
1946
1947 static void
1948 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1949 {
1950 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1951 struct radv_cmd_state *state = &cmd_buffer->state;
1952
1953 if (state->index_type != state->last_index_type) {
1954 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1955 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
1956 cs, R_03090C_VGT_INDEX_TYPE,
1957 2, state->index_type);
1958 } else {
1959 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1960 radeon_emit(cs, state->index_type);
1961 }
1962
1963 state->last_index_type = state->index_type;
1964 }
1965
1966 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1967 radeon_emit(cs, state->index_va);
1968 radeon_emit(cs, state->index_va >> 32);
1969
1970 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1971 radeon_emit(cs, state->max_index_count);
1972
1973 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1974 }
1975
1976 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1977 {
1978 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1979 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1980 uint32_t pa_sc_mode_cntl_1 =
1981 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1982 uint32_t db_count_control;
1983
1984 if(!cmd_buffer->state.active_occlusion_queries) {
1985 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1986 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1987 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1988 has_perfect_queries) {
1989 /* Re-enable out-of-order rasterization if the
1990 * bound pipeline supports it and if it's has
1991 * been disabled before starting any perfect
1992 * occlusion queries.
1993 */
1994 radeon_set_context_reg(cmd_buffer->cs,
1995 R_028A4C_PA_SC_MODE_CNTL_1,
1996 pa_sc_mode_cntl_1);
1997 }
1998 }
1999 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
2000 } else {
2001 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
2002 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
2003 bool gfx10_perfect = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;
2004
2005 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
2006 db_count_control =
2007 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
2008 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
2009 S_028004_SAMPLE_RATE(sample_rate) |
2010 S_028004_ZPASS_ENABLE(1) |
2011 S_028004_SLICE_EVEN_ENABLE(1) |
2012 S_028004_SLICE_ODD_ENABLE(1);
2013
2014 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
2015 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
2016 has_perfect_queries) {
2017 /* If the bound pipeline has enabled
2018 * out-of-order rasterization, we should
2019 * disable it before starting any perfect
2020 * occlusion queries.
2021 */
2022 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
2023
2024 radeon_set_context_reg(cmd_buffer->cs,
2025 R_028A4C_PA_SC_MODE_CNTL_1,
2026 pa_sc_mode_cntl_1);
2027 }
2028 } else {
2029 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
2030 S_028004_SAMPLE_RATE(sample_rate);
2031 }
2032 }
2033
2034 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
2035
2036 cmd_buffer->state.context_roll_without_scissor_emitted = true;
2037 }
2038
2039 static void
2040 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
2041 {
2042 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
2043
2044 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
2045 radv_emit_viewport(cmd_buffer);
2046
2047 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2048 !cmd_buffer->device->physical_device->has_scissor_bug)
2049 radv_emit_scissor(cmd_buffer);
2050
2051 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
2052 radv_emit_line_width(cmd_buffer);
2053
2054 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
2055 radv_emit_blend_constants(cmd_buffer);
2056
2057 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
2058 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
2059 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
2060 radv_emit_stencil(cmd_buffer);
2061
2062 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
2063 radv_emit_depth_bounds(cmd_buffer);
2064
2065 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
2066 radv_emit_depth_bias(cmd_buffer);
2067
2068 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
2069 radv_emit_discard_rectangle(cmd_buffer);
2070
2071 if (states & RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS)
2072 radv_emit_sample_locations(cmd_buffer);
2073
2074 cmd_buffer->state.dirty &= ~states;
2075 }
2076
2077 static void
2078 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
2079 VkPipelineBindPoint bind_point)
2080 {
2081 struct radv_descriptor_state *descriptors_state =
2082 radv_get_descriptors_state(cmd_buffer, bind_point);
2083 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
2084 unsigned bo_offset;
2085
2086 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
2087 set->mapped_ptr,
2088 &bo_offset))
2089 return;
2090
2091 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2092 set->va += bo_offset;
2093 }
2094
2095 static void
2096 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
2097 VkPipelineBindPoint bind_point)
2098 {
2099 struct radv_descriptor_state *descriptors_state =
2100 radv_get_descriptors_state(cmd_buffer, bind_point);
2101 uint32_t size = MAX_SETS * 4;
2102 uint32_t offset;
2103 void *ptr;
2104
2105 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
2106 256, &offset, &ptr))
2107 return;
2108
2109 for (unsigned i = 0; i < MAX_SETS; i++) {
2110 uint32_t *uptr = ((uint32_t *)ptr) + i;
2111 uint64_t set_va = 0;
2112 struct radv_descriptor_set *set = descriptors_state->sets[i];
2113 if (descriptors_state->valid & (1u << i))
2114 set_va = set->va;
2115 uptr[0] = set_va & 0xffffffff;
2116 }
2117
2118 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2119 va += offset;
2120
2121 if (cmd_buffer->state.pipeline) {
2122 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
2123 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2124 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2125
2126 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
2127 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
2128 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2129
2130 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
2131 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2132 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2133
2134 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2135 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
2136 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2137
2138 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
2139 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
2140 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2141 }
2142
2143 if (cmd_buffer->state.compute_pipeline)
2144 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
2145 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
2146 }
2147
2148 static void
2149 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
2150 VkShaderStageFlags stages)
2151 {
2152 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2153 VK_PIPELINE_BIND_POINT_COMPUTE :
2154 VK_PIPELINE_BIND_POINT_GRAPHICS;
2155 struct radv_descriptor_state *descriptors_state =
2156 radv_get_descriptors_state(cmd_buffer, bind_point);
2157 struct radv_cmd_state *state = &cmd_buffer->state;
2158 bool flush_indirect_descriptors;
2159
2160 if (!descriptors_state->dirty)
2161 return;
2162
2163 if (descriptors_state->push_dirty)
2164 radv_flush_push_descriptors(cmd_buffer, bind_point);
2165
2166 flush_indirect_descriptors =
2167 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
2168 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
2169 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
2170 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
2171
2172 if (flush_indirect_descriptors)
2173 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
2174
2175 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2176 cmd_buffer->cs,
2177 MAX_SETS * MESA_SHADER_STAGES * 4);
2178
2179 if (cmd_buffer->state.pipeline) {
2180 radv_foreach_stage(stage, stages) {
2181 if (!cmd_buffer->state.pipeline->shaders[stage])
2182 continue;
2183
2184 radv_emit_descriptor_pointers(cmd_buffer,
2185 cmd_buffer->state.pipeline,
2186 descriptors_state, stage);
2187 }
2188 }
2189
2190 if (cmd_buffer->state.compute_pipeline &&
2191 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
2192 radv_emit_descriptor_pointers(cmd_buffer,
2193 cmd_buffer->state.compute_pipeline,
2194 descriptors_state,
2195 MESA_SHADER_COMPUTE);
2196 }
2197
2198 descriptors_state->dirty = 0;
2199 descriptors_state->push_dirty = false;
2200
2201 assert(cmd_buffer->cs->cdw <= cdw_max);
2202
2203 if (unlikely(cmd_buffer->device->trace_bo))
2204 radv_save_descriptors(cmd_buffer, bind_point);
2205 }
2206
2207 static void
2208 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
2209 VkShaderStageFlags stages)
2210 {
2211 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
2212 ? cmd_buffer->state.compute_pipeline
2213 : cmd_buffer->state.pipeline;
2214 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
2215 VK_PIPELINE_BIND_POINT_COMPUTE :
2216 VK_PIPELINE_BIND_POINT_GRAPHICS;
2217 struct radv_descriptor_state *descriptors_state =
2218 radv_get_descriptors_state(cmd_buffer, bind_point);
2219 struct radv_pipeline_layout *layout = pipeline->layout;
2220 struct radv_shader_variant *shader, *prev_shader;
2221 bool need_push_constants = false;
2222 unsigned offset;
2223 void *ptr;
2224 uint64_t va;
2225
2226 stages &= cmd_buffer->push_constant_stages;
2227 if (!stages ||
2228 (!layout->push_constant_size && !layout->dynamic_offset_count))
2229 return;
2230
2231 radv_foreach_stage(stage, stages) {
2232 if (!pipeline->shaders[stage])
2233 continue;
2234
2235 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
2236 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
2237
2238 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
2239 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
2240
2241 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
2242 AC_UD_INLINE_PUSH_CONSTANTS,
2243 count,
2244 (uint32_t *)&cmd_buffer->push_constants[base * 4]);
2245 }
2246
2247 if (need_push_constants) {
2248 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
2249 16 * layout->dynamic_offset_count,
2250 256, &offset, &ptr))
2251 return;
2252
2253 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
2254 memcpy((char*)ptr + layout->push_constant_size,
2255 descriptors_state->dynamic_buffers,
2256 16 * layout->dynamic_offset_count);
2257
2258 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2259 va += offset;
2260
2261 MAYBE_UNUSED unsigned cdw_max =
2262 radeon_check_space(cmd_buffer->device->ws,
2263 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
2264
2265 prev_shader = NULL;
2266 radv_foreach_stage(stage, stages) {
2267 shader = radv_get_shader(pipeline, stage);
2268
2269 /* Avoid redundantly emitting the address for merged stages. */
2270 if (shader && shader != prev_shader) {
2271 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
2272 AC_UD_PUSH_CONSTANTS, va);
2273
2274 prev_shader = shader;
2275 }
2276 }
2277 assert(cmd_buffer->cs->cdw <= cdw_max);
2278 }
2279
2280 cmd_buffer->push_constant_stages &= ~stages;
2281 }
2282
2283 static void
2284 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
2285 bool pipeline_is_dirty)
2286 {
2287 if ((pipeline_is_dirty ||
2288 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
2289 cmd_buffer->state.pipeline->num_vertex_bindings &&
2290 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
2291 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
2292 unsigned vb_offset;
2293 void *vb_ptr;
2294 uint32_t i = 0;
2295 uint32_t count = cmd_buffer->state.pipeline->num_vertex_bindings;
2296 uint64_t va;
2297
2298 /* allocate some descriptor state for vertex buffers */
2299 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
2300 &vb_offset, &vb_ptr))
2301 return;
2302
2303 for (i = 0; i < count; i++) {
2304 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2305 uint32_t offset;
2306 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[i].buffer;
2307 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[i];
2308
2309 if (!buffer)
2310 continue;
2311
2312 va = radv_buffer_get_va(buffer->bo);
2313
2314 offset = cmd_buffer->vertex_bindings[i].offset;
2315 va += offset + buffer->offset;
2316 desc[0] = va;
2317 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2318 if (cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
2319 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2320 else
2321 desc[2] = buffer->size - offset;
2322 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2323 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2324 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2325 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2326
2327 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
2328 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
2329 S_008F0C_OOB_SELECT(1) |
2330 S_008F0C_RESOURCE_LEVEL(1);
2331 } else {
2332 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
2333 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2334 }
2335 }
2336
2337 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2338 va += vb_offset;
2339
2340 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2341 AC_UD_VS_VERTEX_BUFFERS, va);
2342
2343 cmd_buffer->state.vb_va = va;
2344 cmd_buffer->state.vb_size = count * 16;
2345 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2346 }
2347 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2348 }
2349
2350 static void
2351 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2352 {
2353 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2354 struct radv_userdata_info *loc;
2355 uint32_t base_reg;
2356
2357 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2358 if (!radv_get_shader(pipeline, stage))
2359 continue;
2360
2361 loc = radv_lookup_user_sgpr(pipeline, stage,
2362 AC_UD_STREAMOUT_BUFFERS);
2363 if (loc->sgpr_idx == -1)
2364 continue;
2365
2366 base_reg = pipeline->user_data_0[stage];
2367
2368 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2369 base_reg + loc->sgpr_idx * 4, va, false);
2370 }
2371
2372 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
2373 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2374 if (loc->sgpr_idx != -1) {
2375 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2376
2377 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2378 base_reg + loc->sgpr_idx * 4, va, false);
2379 }
2380 }
2381 }
2382
2383 static void
2384 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2385 {
2386 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2387 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2388 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2389 unsigned so_offset;
2390 void *so_ptr;
2391 uint64_t va;
2392
2393 /* Allocate some descriptor state for streamout buffers. */
2394 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2395 MAX_SO_BUFFERS * 16, 256,
2396 &so_offset, &so_ptr))
2397 return;
2398
2399 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2400 struct radv_buffer *buffer = sb[i].buffer;
2401 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2402
2403 if (!(so->enabled_mask & (1 << i)))
2404 continue;
2405
2406 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2407
2408 va += sb[i].offset;
2409
2410 /* Set the descriptor.
2411 *
2412 * On GFX8, the format must be non-INVALID, otherwise
2413 * the buffer will be considered not bound and store
2414 * instructions will be no-ops.
2415 */
2416 desc[0] = va;
2417 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2418 desc[2] = 0xffffffff;
2419 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2420 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2421 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2422 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2423 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2424 }
2425
2426 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2427 va += so_offset;
2428
2429 radv_emit_streamout_buffers(cmd_buffer, va);
2430 }
2431
2432 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2433 }
2434
2435 static void
2436 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2437 {
2438 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2439 radv_flush_streamout_descriptors(cmd_buffer);
2440 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2441 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2442 }
2443
2444 struct radv_draw_info {
2445 /**
2446 * Number of vertices.
2447 */
2448 uint32_t count;
2449
2450 /**
2451 * Index of the first vertex.
2452 */
2453 int32_t vertex_offset;
2454
2455 /**
2456 * First instance id.
2457 */
2458 uint32_t first_instance;
2459
2460 /**
2461 * Number of instances.
2462 */
2463 uint32_t instance_count;
2464
2465 /**
2466 * First index (indexed draws only).
2467 */
2468 uint32_t first_index;
2469
2470 /**
2471 * Whether it's an indexed draw.
2472 */
2473 bool indexed;
2474
2475 /**
2476 * Indirect draw parameters resource.
2477 */
2478 struct radv_buffer *indirect;
2479 uint64_t indirect_offset;
2480 uint32_t stride;
2481
2482 /**
2483 * Draw count parameters resource.
2484 */
2485 struct radv_buffer *count_buffer;
2486 uint64_t count_buffer_offset;
2487
2488 /**
2489 * Stream output parameters resource.
2490 */
2491 struct radv_buffer *strmout_buffer;
2492 uint64_t strmout_buffer_offset;
2493 };
2494
2495 static void
2496 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
2497 bool instanced_draw, bool indirect_draw,
2498 bool count_from_stream_output,
2499 uint32_t draw_vertex_count)
2500 {
2501 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2502 struct radv_cmd_state *state = &cmd_buffer->state;
2503 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2504 unsigned ia_multi_vgt_param;
2505
2506 ia_multi_vgt_param =
2507 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2508 indirect_draw,
2509 count_from_stream_output,
2510 draw_vertex_count);
2511
2512 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2513 if (info->chip_class == GFX9) {
2514 radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
2515 cs,
2516 R_030960_IA_MULTI_VGT_PARAM,
2517 4, ia_multi_vgt_param);
2518 } else if (info->chip_class >= GFX7) {
2519 radeon_set_context_reg_idx(cs,
2520 R_028AA8_IA_MULTI_VGT_PARAM,
2521 1, ia_multi_vgt_param);
2522 } else {
2523 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2524 ia_multi_vgt_param);
2525 }
2526 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2527 }
2528 }
2529
2530 static void
2531 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2532 const struct radv_draw_info *draw_info)
2533 {
2534 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2535 struct radv_cmd_state *state = &cmd_buffer->state;
2536 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2537 int32_t primitive_reset_en;
2538
2539 /* Draw state. */
2540 if (info->chip_class < GFX10) {
2541 si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2542 draw_info->indirect,
2543 !!draw_info->strmout_buffer,
2544 draw_info->indirect ? 0 : draw_info->count);
2545 }
2546
2547 /* Primitive restart. */
2548 primitive_reset_en =
2549 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2550
2551 if (primitive_reset_en != state->last_primitive_reset_en) {
2552 state->last_primitive_reset_en = primitive_reset_en;
2553 if (info->chip_class >= GFX9) {
2554 radeon_set_uconfig_reg(cs,
2555 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2556 primitive_reset_en);
2557 } else {
2558 radeon_set_context_reg(cs,
2559 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2560 primitive_reset_en);
2561 }
2562 }
2563
2564 if (primitive_reset_en) {
2565 uint32_t primitive_reset_index =
2566 state->index_type ? 0xffffffffu : 0xffffu;
2567
2568 if (primitive_reset_index != state->last_primitive_reset_index) {
2569 radeon_set_context_reg(cs,
2570 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2571 primitive_reset_index);
2572 state->last_primitive_reset_index = primitive_reset_index;
2573 }
2574 }
2575
2576 if (draw_info->strmout_buffer) {
2577 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2578
2579 va += draw_info->strmout_buffer->offset +
2580 draw_info->strmout_buffer_offset;
2581
2582 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2583 draw_info->stride);
2584
2585 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2586 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2587 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2588 COPY_DATA_WR_CONFIRM);
2589 radeon_emit(cs, va);
2590 radeon_emit(cs, va >> 32);
2591 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2592 radeon_emit(cs, 0); /* unused */
2593
2594 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2595 }
2596 }
2597
2598 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2599 VkPipelineStageFlags src_stage_mask)
2600 {
2601 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2602 VK_PIPELINE_STAGE_TRANSFER_BIT |
2603 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2604 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2605 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2606 }
2607
2608 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2609 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2610 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2611 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2612 VK_PIPELINE_STAGE_TRANSFER_BIT |
2613 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2614 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2615 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2616 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2617 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2618 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2619 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2620 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2621 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2622 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2623 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2624 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2625 }
2626 }
2627
2628 static enum radv_cmd_flush_bits
2629 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2630 VkAccessFlags src_flags,
2631 struct radv_image *image)
2632 {
2633 bool flush_CB_meta = true, flush_DB_meta = true;
2634 enum radv_cmd_flush_bits flush_bits = 0;
2635 uint32_t b;
2636
2637 if (image) {
2638 if (!radv_image_has_CB_metadata(image))
2639 flush_CB_meta = false;
2640 if (!radv_image_has_htile(image))
2641 flush_DB_meta = false;
2642 }
2643
2644 for_each_bit(b, src_flags) {
2645 switch ((VkAccessFlagBits)(1 << b)) {
2646 case VK_ACCESS_SHADER_WRITE_BIT:
2647 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2648 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2649 flush_bits |= RADV_CMD_FLAG_WB_L2;
2650 break;
2651 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2652 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2653 if (flush_CB_meta)
2654 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2655 break;
2656 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2657 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2658 if (flush_DB_meta)
2659 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2660 break;
2661 case VK_ACCESS_TRANSFER_WRITE_BIT:
2662 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2663 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2664 RADV_CMD_FLAG_INV_L2;
2665
2666 if (flush_CB_meta)
2667 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2668 if (flush_DB_meta)
2669 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2670 break;
2671 default:
2672 break;
2673 }
2674 }
2675 return flush_bits;
2676 }
2677
2678 static enum radv_cmd_flush_bits
2679 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2680 VkAccessFlags dst_flags,
2681 struct radv_image *image)
2682 {
2683 bool flush_CB_meta = true, flush_DB_meta = true;
2684 enum radv_cmd_flush_bits flush_bits = 0;
2685 bool flush_CB = true, flush_DB = true;
2686 bool image_is_coherent = false;
2687 uint32_t b;
2688
2689 if (image) {
2690 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2691 flush_CB = false;
2692 flush_DB = false;
2693 }
2694
2695 if (!radv_image_has_CB_metadata(image))
2696 flush_CB_meta = false;
2697 if (!radv_image_has_htile(image))
2698 flush_DB_meta = false;
2699
2700 /* TODO: implement shader coherent for GFX10 */
2701
2702 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
2703 if (image->info.samples == 1 &&
2704 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2705 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2706 !vk_format_is_stencil(image->vk_format)) {
2707 /* Single-sample color and single-sample depth
2708 * (not stencil) are coherent with shaders on
2709 * GFX9.
2710 */
2711 image_is_coherent = true;
2712 }
2713 }
2714 }
2715
2716 for_each_bit(b, dst_flags) {
2717 switch ((VkAccessFlagBits)(1 << b)) {
2718 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2719 case VK_ACCESS_INDEX_READ_BIT:
2720 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2721 break;
2722 case VK_ACCESS_UNIFORM_READ_BIT:
2723 flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
2724 break;
2725 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2726 case VK_ACCESS_TRANSFER_READ_BIT:
2727 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2728 flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
2729 RADV_CMD_FLAG_INV_L2;
2730 break;
2731 case VK_ACCESS_SHADER_READ_BIT:
2732 flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
2733
2734 if (!image_is_coherent)
2735 flush_bits |= RADV_CMD_FLAG_INV_L2;
2736 break;
2737 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2738 if (flush_CB)
2739 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2740 if (flush_CB_meta)
2741 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2742 break;
2743 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2744 if (flush_DB)
2745 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2746 if (flush_DB_meta)
2747 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2748 break;
2749 default:
2750 break;
2751 }
2752 }
2753 return flush_bits;
2754 }
2755
2756 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2757 const struct radv_subpass_barrier *barrier)
2758 {
2759 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2760 NULL);
2761 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2762 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2763 NULL);
2764 }
2765
2766 uint32_t
2767 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
2768 {
2769 struct radv_cmd_state *state = &cmd_buffer->state;
2770 uint32_t subpass_id = state->subpass - state->pass->subpasses;
2771
2772 /* The id of this subpass shouldn't exceed the number of subpasses in
2773 * this render pass minus 1.
2774 */
2775 assert(subpass_id < state->pass->subpass_count);
2776 return subpass_id;
2777 }
2778
2779 static struct radv_sample_locations_state *
2780 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2781 uint32_t att_idx,
2782 bool begin_subpass)
2783 {
2784 struct radv_cmd_state *state = &cmd_buffer->state;
2785 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
2786 struct radv_image_view *view = state->framebuffer->attachments[att_idx].attachment;
2787
2788 if (view->image->info.samples == 1)
2789 return NULL;
2790
2791 if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
2792 /* Return the initial sample locations if this is the initial
2793 * layout transition of the given subpass attachemnt.
2794 */
2795 if (state->attachments[att_idx].sample_location.count > 0)
2796 return &state->attachments[att_idx].sample_location;
2797 } else {
2798 /* Otherwise return the subpass sample locations if defined. */
2799 if (state->subpass_sample_locs) {
2800 /* Because the driver sets the current subpass before
2801 * initial layout transitions, we should use the sample
2802 * locations from the previous subpass to avoid an
2803 * off-by-one problem. Otherwise, use the sample
2804 * locations for the current subpass for final layout
2805 * transitions.
2806 */
2807 if (begin_subpass)
2808 subpass_id--;
2809
2810 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
2811 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
2812 return &state->subpass_sample_locs[i].sample_location;
2813 }
2814 }
2815 }
2816
2817 return NULL;
2818 }
2819
2820 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2821 struct radv_subpass_attachment att,
2822 bool begin_subpass)
2823 {
2824 unsigned idx = att.attachment;
2825 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2826 struct radv_sample_locations_state *sample_locs;
2827 VkImageSubresourceRange range;
2828 range.aspectMask = 0;
2829 range.baseMipLevel = view->base_mip;
2830 range.levelCount = 1;
2831 range.baseArrayLayer = view->base_layer;
2832 range.layerCount = cmd_buffer->state.framebuffer->layers;
2833
2834 if (cmd_buffer->state.subpass->view_mask) {
2835 /* If the current subpass uses multiview, the driver might have
2836 * performed a fast color/depth clear to the whole image
2837 * (including all layers). To make sure the driver will
2838 * decompress the image correctly (if needed), we have to
2839 * account for the "real" number of layers. If the view mask is
2840 * sparse, this will decompress more layers than needed.
2841 */
2842 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2843 }
2844
2845 /* Get the subpass sample locations for the given attachment, if NULL
2846 * is returned the driver will use the default HW locations.
2847 */
2848 sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx,
2849 begin_subpass);
2850
2851 radv_handle_image_transition(cmd_buffer,
2852 view->image,
2853 cmd_buffer->state.attachments[idx].current_layout,
2854 att.layout, 0, 0, &range, sample_locs);
2855
2856 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2857
2858
2859 }
2860
2861 void
2862 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2863 const struct radv_subpass *subpass)
2864 {
2865 cmd_buffer->state.subpass = subpass;
2866
2867 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2868 }
2869
2870 static VkResult
2871 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
2872 struct radv_render_pass *pass,
2873 const VkRenderPassBeginInfo *info)
2874 {
2875 const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
2876 vk_find_struct_const(info->pNext,
2877 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
2878 struct radv_cmd_state *state = &cmd_buffer->state;
2879 struct radv_framebuffer *framebuffer = state->framebuffer;
2880
2881 if (!sample_locs) {
2882 state->subpass_sample_locs = NULL;
2883 return VK_SUCCESS;
2884 }
2885
2886 for (uint32_t i = 0; i < sample_locs->attachmentInitialSampleLocationsCount; i++) {
2887 const VkAttachmentSampleLocationsEXT *att_sample_locs =
2888 &sample_locs->pAttachmentInitialSampleLocations[i];
2889 uint32_t att_idx = att_sample_locs->attachmentIndex;
2890 struct radv_attachment_info *att = &framebuffer->attachments[att_idx];
2891 struct radv_image *image = att->attachment->image;
2892
2893 assert(vk_format_is_depth_or_stencil(image->vk_format));
2894
2895 /* From the Vulkan spec 1.1.108:
2896 *
2897 * "If the image referenced by the framebuffer attachment at
2898 * index attachmentIndex was not created with
2899 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
2900 * then the values specified in sampleLocationsInfo are
2901 * ignored."
2902 */
2903 if (!(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT))
2904 continue;
2905
2906 const VkSampleLocationsInfoEXT *sample_locs_info =
2907 &att_sample_locs->sampleLocationsInfo;
2908
2909 state->attachments[att_idx].sample_location.per_pixel =
2910 sample_locs_info->sampleLocationsPerPixel;
2911 state->attachments[att_idx].sample_location.grid_size =
2912 sample_locs_info->sampleLocationGridSize;
2913 state->attachments[att_idx].sample_location.count =
2914 sample_locs_info->sampleLocationsCount;
2915 typed_memcpy(&state->attachments[att_idx].sample_location.locations[0],
2916 sample_locs_info->pSampleLocations,
2917 sample_locs_info->sampleLocationsCount);
2918 }
2919
2920 state->subpass_sample_locs = vk_alloc(&cmd_buffer->pool->alloc,
2921 sample_locs->postSubpassSampleLocationsCount *
2922 sizeof(state->subpass_sample_locs[0]),
2923 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2924 if (state->subpass_sample_locs == NULL) {
2925 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2926 return cmd_buffer->record_result;
2927 }
2928
2929 state->num_subpass_sample_locs = sample_locs->postSubpassSampleLocationsCount;
2930
2931 for (uint32_t i = 0; i < sample_locs->postSubpassSampleLocationsCount; i++) {
2932 const VkSubpassSampleLocationsEXT *subpass_sample_locs_info =
2933 &sample_locs->pPostSubpassSampleLocations[i];
2934 const VkSampleLocationsInfoEXT *sample_locs_info =
2935 &subpass_sample_locs_info->sampleLocationsInfo;
2936
2937 state->subpass_sample_locs[i].subpass_idx =
2938 subpass_sample_locs_info->subpassIndex;
2939 state->subpass_sample_locs[i].sample_location.per_pixel =
2940 sample_locs_info->sampleLocationsPerPixel;
2941 state->subpass_sample_locs[i].sample_location.grid_size =
2942 sample_locs_info->sampleLocationGridSize;
2943 state->subpass_sample_locs[i].sample_location.count =
2944 sample_locs_info->sampleLocationsCount;
2945 typed_memcpy(&state->subpass_sample_locs[i].sample_location.locations[0],
2946 sample_locs_info->pSampleLocations,
2947 sample_locs_info->sampleLocationsCount);
2948 }
2949
2950 return VK_SUCCESS;
2951 }
2952
2953 static VkResult
2954 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2955 struct radv_render_pass *pass,
2956 const VkRenderPassBeginInfo *info)
2957 {
2958 struct radv_cmd_state *state = &cmd_buffer->state;
2959
2960 if (pass->attachment_count == 0) {
2961 state->attachments = NULL;
2962 return VK_SUCCESS;
2963 }
2964
2965 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2966 pass->attachment_count *
2967 sizeof(state->attachments[0]),
2968 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2969 if (state->attachments == NULL) {
2970 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2971 return cmd_buffer->record_result;
2972 }
2973
2974 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2975 struct radv_render_pass_attachment *att = &pass->attachments[i];
2976 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2977 VkImageAspectFlags clear_aspects = 0;
2978
2979 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2980 /* color attachment */
2981 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2982 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2983 }
2984 } else {
2985 /* depthstencil attachment */
2986 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2987 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2988 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2989 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2990 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2991 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2992 }
2993 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2994 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2995 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2996 }
2997 }
2998
2999 state->attachments[i].pending_clear_aspects = clear_aspects;
3000 state->attachments[i].cleared_views = 0;
3001 if (clear_aspects && info) {
3002 assert(info->clearValueCount > i);
3003 state->attachments[i].clear_value = info->pClearValues[i];
3004 }
3005
3006 state->attachments[i].current_layout = att->initial_layout;
3007 state->attachments[i].sample_location.count = 0;
3008 }
3009
3010 return VK_SUCCESS;
3011 }
3012
3013 VkResult radv_AllocateCommandBuffers(
3014 VkDevice _device,
3015 const VkCommandBufferAllocateInfo *pAllocateInfo,
3016 VkCommandBuffer *pCommandBuffers)
3017 {
3018 RADV_FROM_HANDLE(radv_device, device, _device);
3019 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
3020
3021 VkResult result = VK_SUCCESS;
3022 uint32_t i;
3023
3024 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
3025
3026 if (!list_empty(&pool->free_cmd_buffers)) {
3027 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
3028
3029 list_del(&cmd_buffer->pool_link);
3030 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
3031
3032 result = radv_reset_cmd_buffer(cmd_buffer);
3033 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
3034 cmd_buffer->level = pAllocateInfo->level;
3035
3036 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
3037 } else {
3038 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
3039 &pCommandBuffers[i]);
3040 }
3041 if (result != VK_SUCCESS)
3042 break;
3043 }
3044
3045 if (result != VK_SUCCESS) {
3046 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
3047 i, pCommandBuffers);
3048
3049 /* From the Vulkan 1.0.66 spec:
3050 *
3051 * "vkAllocateCommandBuffers can be used to create multiple
3052 * command buffers. If the creation of any of those command
3053 * buffers fails, the implementation must destroy all
3054 * successfully created command buffer objects from this
3055 * command, set all entries of the pCommandBuffers array to
3056 * NULL and return the error."
3057 */
3058 memset(pCommandBuffers, 0,
3059 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
3060 }
3061
3062 return result;
3063 }
3064
3065 void radv_FreeCommandBuffers(
3066 VkDevice device,
3067 VkCommandPool commandPool,
3068 uint32_t commandBufferCount,
3069 const VkCommandBuffer *pCommandBuffers)
3070 {
3071 for (uint32_t i = 0; i < commandBufferCount; i++) {
3072 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
3073
3074 if (cmd_buffer) {
3075 if (cmd_buffer->pool) {
3076 list_del(&cmd_buffer->pool_link);
3077 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
3078 } else
3079 radv_cmd_buffer_destroy(cmd_buffer);
3080
3081 }
3082 }
3083 }
3084
3085 VkResult radv_ResetCommandBuffer(
3086 VkCommandBuffer commandBuffer,
3087 VkCommandBufferResetFlags flags)
3088 {
3089 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3090 return radv_reset_cmd_buffer(cmd_buffer);
3091 }
3092
3093 VkResult radv_BeginCommandBuffer(
3094 VkCommandBuffer commandBuffer,
3095 const VkCommandBufferBeginInfo *pBeginInfo)
3096 {
3097 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3098 VkResult result = VK_SUCCESS;
3099
3100 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
3101 /* If the command buffer has already been resetted with
3102 * vkResetCommandBuffer, no need to do it again.
3103 */
3104 result = radv_reset_cmd_buffer(cmd_buffer);
3105 if (result != VK_SUCCESS)
3106 return result;
3107 }
3108
3109 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
3110 cmd_buffer->state.last_primitive_reset_en = -1;
3111 cmd_buffer->state.last_index_type = -1;
3112 cmd_buffer->state.last_num_instances = -1;
3113 cmd_buffer->state.last_vertex_offset = -1;
3114 cmd_buffer->state.last_first_instance = -1;
3115 cmd_buffer->state.predication_type = -1;
3116 cmd_buffer->usage_flags = pBeginInfo->flags;
3117
3118 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
3119 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
3120 assert(pBeginInfo->pInheritanceInfo);
3121 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
3122 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
3123
3124 struct radv_subpass *subpass =
3125 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
3126
3127 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
3128 if (result != VK_SUCCESS)
3129 return result;
3130
3131 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3132 }
3133
3134 if (unlikely(cmd_buffer->device->trace_bo)) {
3135 struct radv_device *device = cmd_buffer->device;
3136
3137 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
3138 device->trace_bo);
3139
3140 radv_cmd_buffer_trace_emit(cmd_buffer);
3141 }
3142
3143 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
3144
3145 return result;
3146 }
3147
3148 void radv_CmdBindVertexBuffers(
3149 VkCommandBuffer commandBuffer,
3150 uint32_t firstBinding,
3151 uint32_t bindingCount,
3152 const VkBuffer* pBuffers,
3153 const VkDeviceSize* pOffsets)
3154 {
3155 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3156 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
3157 bool changed = false;
3158
3159 /* We have to defer setting up vertex buffer since we need the buffer
3160 * stride from the pipeline. */
3161
3162 assert(firstBinding + bindingCount <= MAX_VBS);
3163 for (uint32_t i = 0; i < bindingCount; i++) {
3164 uint32_t idx = firstBinding + i;
3165
3166 if (!changed &&
3167 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
3168 vb[idx].offset != pOffsets[i])) {
3169 changed = true;
3170 }
3171
3172 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
3173 vb[idx].offset = pOffsets[i];
3174
3175 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3176 vb[idx].buffer->bo);
3177 }
3178
3179 if (!changed) {
3180 /* No state changes. */
3181 return;
3182 }
3183
3184 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
3185 }
3186
3187 void radv_CmdBindIndexBuffer(
3188 VkCommandBuffer commandBuffer,
3189 VkBuffer buffer,
3190 VkDeviceSize offset,
3191 VkIndexType indexType)
3192 {
3193 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3194 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
3195
3196 if (cmd_buffer->state.index_buffer == index_buffer &&
3197 cmd_buffer->state.index_offset == offset &&
3198 cmd_buffer->state.index_type == indexType) {
3199 /* No state changes. */
3200 return;
3201 }
3202
3203 cmd_buffer->state.index_buffer = index_buffer;
3204 cmd_buffer->state.index_offset = offset;
3205 cmd_buffer->state.index_type = indexType; /* vk matches hw */
3206 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
3207 cmd_buffer->state.index_va += index_buffer->offset + offset;
3208
3209 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
3210 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
3211 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3212 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
3213 }
3214
3215
3216 static void
3217 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3218 VkPipelineBindPoint bind_point,
3219 struct radv_descriptor_set *set, unsigned idx)
3220 {
3221 struct radeon_winsys *ws = cmd_buffer->device->ws;
3222
3223 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
3224
3225 assert(set);
3226 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
3227
3228 if (!cmd_buffer->device->use_global_bo_list) {
3229 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3230 if (set->descriptors[j])
3231 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
3232 }
3233
3234 if(set->bo)
3235 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
3236 }
3237
3238 void radv_CmdBindDescriptorSets(
3239 VkCommandBuffer commandBuffer,
3240 VkPipelineBindPoint pipelineBindPoint,
3241 VkPipelineLayout _layout,
3242 uint32_t firstSet,
3243 uint32_t descriptorSetCount,
3244 const VkDescriptorSet* pDescriptorSets,
3245 uint32_t dynamicOffsetCount,
3246 const uint32_t* pDynamicOffsets)
3247 {
3248 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3249 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3250 unsigned dyn_idx = 0;
3251
3252 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
3253 struct radv_descriptor_state *descriptors_state =
3254 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3255
3256 for (unsigned i = 0; i < descriptorSetCount; ++i) {
3257 unsigned idx = i + firstSet;
3258 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
3259 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
3260
3261 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
3262 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
3263 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
3264 assert(dyn_idx < dynamicOffsetCount);
3265
3266 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
3267 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
3268 dst[0] = va;
3269 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
3270 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
3271 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3272 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3273 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3274 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3275
3276 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
3277 dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3278 S_008F0C_OOB_SELECT(3) |
3279 S_008F0C_RESOURCE_LEVEL(1);
3280 } else {
3281 dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3282 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3283 }
3284
3285 cmd_buffer->push_constant_stages |=
3286 set->layout->dynamic_shader_stages;
3287 }
3288 }
3289 }
3290
3291 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
3292 struct radv_descriptor_set *set,
3293 struct radv_descriptor_set_layout *layout,
3294 VkPipelineBindPoint bind_point)
3295 {
3296 struct radv_descriptor_state *descriptors_state =
3297 radv_get_descriptors_state(cmd_buffer, bind_point);
3298 set->size = layout->size;
3299 set->layout = layout;
3300
3301 if (descriptors_state->push_set.capacity < set->size) {
3302 size_t new_size = MAX2(set->size, 1024);
3303 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
3304 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
3305
3306 free(set->mapped_ptr);
3307 set->mapped_ptr = malloc(new_size);
3308
3309 if (!set->mapped_ptr) {
3310 descriptors_state->push_set.capacity = 0;
3311 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3312 return false;
3313 }
3314
3315 descriptors_state->push_set.capacity = new_size;
3316 }
3317
3318 return true;
3319 }
3320
3321 void radv_meta_push_descriptor_set(
3322 struct radv_cmd_buffer* cmd_buffer,
3323 VkPipelineBindPoint pipelineBindPoint,
3324 VkPipelineLayout _layout,
3325 uint32_t set,
3326 uint32_t descriptorWriteCount,
3327 const VkWriteDescriptorSet* pDescriptorWrites)
3328 {
3329 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3330 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
3331 unsigned bo_offset;
3332
3333 assert(set == 0);
3334 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3335
3336 push_set->size = layout->set[set].layout->size;
3337 push_set->layout = layout->set[set].layout;
3338
3339 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
3340 &bo_offset,
3341 (void**) &push_set->mapped_ptr))
3342 return;
3343
3344 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
3345 push_set->va += bo_offset;
3346
3347 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3348 radv_descriptor_set_to_handle(push_set),
3349 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3350
3351 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3352 }
3353
3354 void radv_CmdPushDescriptorSetKHR(
3355 VkCommandBuffer commandBuffer,
3356 VkPipelineBindPoint pipelineBindPoint,
3357 VkPipelineLayout _layout,
3358 uint32_t set,
3359 uint32_t descriptorWriteCount,
3360 const VkWriteDescriptorSet* pDescriptorWrites)
3361 {
3362 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3363 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3364 struct radv_descriptor_state *descriptors_state =
3365 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
3366 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3367
3368 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3369
3370 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3371 layout->set[set].layout,
3372 pipelineBindPoint))
3373 return;
3374
3375 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3376 * because it is invalid, according to Vulkan spec.
3377 */
3378 for (int i = 0; i < descriptorWriteCount; i++) {
3379 MAYBE_UNUSED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
3380 assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
3381 }
3382
3383 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
3384 radv_descriptor_set_to_handle(push_set),
3385 descriptorWriteCount, pDescriptorWrites, 0, NULL);
3386
3387 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
3388 descriptors_state->push_dirty = true;
3389 }
3390
3391 void radv_CmdPushDescriptorSetWithTemplateKHR(
3392 VkCommandBuffer commandBuffer,
3393 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
3394 VkPipelineLayout _layout,
3395 uint32_t set,
3396 const void* pData)
3397 {
3398 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3399 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
3400 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
3401 struct radv_descriptor_state *descriptors_state =
3402 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
3403 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
3404
3405 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
3406
3407 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
3408 layout->set[set].layout,
3409 templ->bind_point))
3410 return;
3411
3412 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
3413 descriptorUpdateTemplate, pData);
3414
3415 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
3416 descriptors_state->push_dirty = true;
3417 }
3418
3419 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
3420 VkPipelineLayout layout,
3421 VkShaderStageFlags stageFlags,
3422 uint32_t offset,
3423 uint32_t size,
3424 const void* pValues)
3425 {
3426 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3427 memcpy(cmd_buffer->push_constants + offset, pValues, size);
3428 cmd_buffer->push_constant_stages |= stageFlags;
3429 }
3430
3431 VkResult radv_EndCommandBuffer(
3432 VkCommandBuffer commandBuffer)
3433 {
3434 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3435
3436 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
3437 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
3438 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
3439
3440 /* Make sure to sync all pending active queries at the end of
3441 * command buffer.
3442 */
3443 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
3444
3445 si_emit_cache_flush(cmd_buffer);
3446 }
3447
3448 /* Make sure CP DMA is idle at the end of IBs because the kernel
3449 * doesn't wait for it.
3450 */
3451 si_cp_dma_wait_for_idle(cmd_buffer);
3452
3453 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3454 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
3455
3456 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
3457 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3458
3459 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
3460
3461 return cmd_buffer->record_result;
3462 }
3463
3464 static void
3465 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
3466 {
3467 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3468
3469 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
3470 return;
3471
3472 assert(!pipeline->ctx_cs.cdw);
3473
3474 cmd_buffer->state.emitted_compute_pipeline = pipeline;
3475
3476 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
3477 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
3478
3479 cmd_buffer->compute_scratch_size_needed =
3480 MAX2(cmd_buffer->compute_scratch_size_needed,
3481 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
3482
3483 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
3484 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
3485
3486 if (unlikely(cmd_buffer->device->trace_bo))
3487 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
3488 }
3489
3490 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
3491 VkPipelineBindPoint bind_point)
3492 {
3493 struct radv_descriptor_state *descriptors_state =
3494 radv_get_descriptors_state(cmd_buffer, bind_point);
3495
3496 descriptors_state->dirty |= descriptors_state->valid;
3497 }
3498
3499 void radv_CmdBindPipeline(
3500 VkCommandBuffer commandBuffer,
3501 VkPipelineBindPoint pipelineBindPoint,
3502 VkPipeline _pipeline)
3503 {
3504 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3505 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3506
3507 switch (pipelineBindPoint) {
3508 case VK_PIPELINE_BIND_POINT_COMPUTE:
3509 if (cmd_buffer->state.compute_pipeline == pipeline)
3510 return;
3511 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3512
3513 cmd_buffer->state.compute_pipeline = pipeline;
3514 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3515 break;
3516 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3517 if (cmd_buffer->state.pipeline == pipeline)
3518 return;
3519 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3520
3521 cmd_buffer->state.pipeline = pipeline;
3522 if (!pipeline)
3523 break;
3524
3525 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3526 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3527
3528 /* the new vertex shader might not have the same user regs */
3529 cmd_buffer->state.last_first_instance = -1;
3530 cmd_buffer->state.last_vertex_offset = -1;
3531
3532 /* Prefetch all pipeline shaders at first draw time. */
3533 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3534
3535 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3536 radv_bind_streamout_state(cmd_buffer, pipeline);
3537
3538 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3539 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3540 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3541 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3542
3543 if (radv_pipeline_has_tess(pipeline))
3544 cmd_buffer->tess_rings_needed = true;
3545 break;
3546 default:
3547 assert(!"invalid bind point");
3548 break;
3549 }
3550 }
3551
3552 void radv_CmdSetViewport(
3553 VkCommandBuffer commandBuffer,
3554 uint32_t firstViewport,
3555 uint32_t viewportCount,
3556 const VkViewport* pViewports)
3557 {
3558 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3559 struct radv_cmd_state *state = &cmd_buffer->state;
3560 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3561
3562 assert(firstViewport < MAX_VIEWPORTS);
3563 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3564
3565 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3566 pViewports, viewportCount * sizeof(*pViewports))) {
3567 return;
3568 }
3569
3570 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3571 viewportCount * sizeof(*pViewports));
3572
3573 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3574 }
3575
3576 void radv_CmdSetScissor(
3577 VkCommandBuffer commandBuffer,
3578 uint32_t firstScissor,
3579 uint32_t scissorCount,
3580 const VkRect2D* pScissors)
3581 {
3582 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3583 struct radv_cmd_state *state = &cmd_buffer->state;
3584 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3585
3586 assert(firstScissor < MAX_SCISSORS);
3587 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3588
3589 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3590 scissorCount * sizeof(*pScissors))) {
3591 return;
3592 }
3593
3594 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3595 scissorCount * sizeof(*pScissors));
3596
3597 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3598 }
3599
3600 void radv_CmdSetLineWidth(
3601 VkCommandBuffer commandBuffer,
3602 float lineWidth)
3603 {
3604 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3605
3606 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3607 return;
3608
3609 cmd_buffer->state.dynamic.line_width = lineWidth;
3610 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3611 }
3612
3613 void radv_CmdSetDepthBias(
3614 VkCommandBuffer commandBuffer,
3615 float depthBiasConstantFactor,
3616 float depthBiasClamp,
3617 float depthBiasSlopeFactor)
3618 {
3619 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3620 struct radv_cmd_state *state = &cmd_buffer->state;
3621
3622 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3623 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3624 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3625 return;
3626 }
3627
3628 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3629 state->dynamic.depth_bias.clamp = depthBiasClamp;
3630 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3631
3632 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3633 }
3634
3635 void radv_CmdSetBlendConstants(
3636 VkCommandBuffer commandBuffer,
3637 const float blendConstants[4])
3638 {
3639 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3640 struct radv_cmd_state *state = &cmd_buffer->state;
3641
3642 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3643 return;
3644
3645 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3646
3647 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3648 }
3649
3650 void radv_CmdSetDepthBounds(
3651 VkCommandBuffer commandBuffer,
3652 float minDepthBounds,
3653 float maxDepthBounds)
3654 {
3655 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3656 struct radv_cmd_state *state = &cmd_buffer->state;
3657
3658 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3659 state->dynamic.depth_bounds.max == maxDepthBounds) {
3660 return;
3661 }
3662
3663 state->dynamic.depth_bounds.min = minDepthBounds;
3664 state->dynamic.depth_bounds.max = maxDepthBounds;
3665
3666 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3667 }
3668
3669 void radv_CmdSetStencilCompareMask(
3670 VkCommandBuffer commandBuffer,
3671 VkStencilFaceFlags faceMask,
3672 uint32_t compareMask)
3673 {
3674 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3675 struct radv_cmd_state *state = &cmd_buffer->state;
3676 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3677 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3678
3679 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3680 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3681 return;
3682 }
3683
3684 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3685 state->dynamic.stencil_compare_mask.front = compareMask;
3686 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3687 state->dynamic.stencil_compare_mask.back = compareMask;
3688
3689 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3690 }
3691
3692 void radv_CmdSetStencilWriteMask(
3693 VkCommandBuffer commandBuffer,
3694 VkStencilFaceFlags faceMask,
3695 uint32_t writeMask)
3696 {
3697 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3698 struct radv_cmd_state *state = &cmd_buffer->state;
3699 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3700 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3701
3702 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3703 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3704 return;
3705 }
3706
3707 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3708 state->dynamic.stencil_write_mask.front = writeMask;
3709 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3710 state->dynamic.stencil_write_mask.back = writeMask;
3711
3712 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3713 }
3714
3715 void radv_CmdSetStencilReference(
3716 VkCommandBuffer commandBuffer,
3717 VkStencilFaceFlags faceMask,
3718 uint32_t reference)
3719 {
3720 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3721 struct radv_cmd_state *state = &cmd_buffer->state;
3722 bool front_same = state->dynamic.stencil_reference.front == reference;
3723 bool back_same = state->dynamic.stencil_reference.back == reference;
3724
3725 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3726 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3727 return;
3728 }
3729
3730 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3731 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3732 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3733 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3734
3735 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3736 }
3737
3738 void radv_CmdSetDiscardRectangleEXT(
3739 VkCommandBuffer commandBuffer,
3740 uint32_t firstDiscardRectangle,
3741 uint32_t discardRectangleCount,
3742 const VkRect2D* pDiscardRectangles)
3743 {
3744 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3745 struct radv_cmd_state *state = &cmd_buffer->state;
3746 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3747
3748 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3749 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3750
3751 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3752 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3753 return;
3754 }
3755
3756 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3757 pDiscardRectangles, discardRectangleCount);
3758
3759 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3760 }
3761
3762 void radv_CmdSetSampleLocationsEXT(
3763 VkCommandBuffer commandBuffer,
3764 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
3765 {
3766 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3767 struct radv_cmd_state *state = &cmd_buffer->state;
3768
3769 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
3770
3771 state->dynamic.sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
3772 state->dynamic.sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
3773 state->dynamic.sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
3774 typed_memcpy(&state->dynamic.sample_location.locations[0],
3775 pSampleLocationsInfo->pSampleLocations,
3776 pSampleLocationsInfo->sampleLocationsCount);
3777
3778 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
3779 }
3780
3781 void radv_CmdExecuteCommands(
3782 VkCommandBuffer commandBuffer,
3783 uint32_t commandBufferCount,
3784 const VkCommandBuffer* pCmdBuffers)
3785 {
3786 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3787
3788 assert(commandBufferCount > 0);
3789
3790 /* Emit pending flushes on primary prior to executing secondary */
3791 si_emit_cache_flush(primary);
3792
3793 for (uint32_t i = 0; i < commandBufferCount; i++) {
3794 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3795
3796 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3797 secondary->scratch_size_needed);
3798 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3799 secondary->compute_scratch_size_needed);
3800
3801 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3802 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3803 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3804 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3805 if (secondary->tess_rings_needed)
3806 primary->tess_rings_needed = true;
3807 if (secondary->sample_positions_needed)
3808 primary->sample_positions_needed = true;
3809
3810 if (!secondary->state.framebuffer &&
3811 (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
3812 /* Emit the framebuffer state from primary if secondary
3813 * has been recorded without a framebuffer, otherwise
3814 * fast color/depth clears can't work.
3815 */
3816 radv_emit_framebuffer_state(primary);
3817 }
3818
3819 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3820
3821
3822 /* When the secondary command buffer is compute only we don't
3823 * need to re-emit the current graphics pipeline.
3824 */
3825 if (secondary->state.emitted_pipeline) {
3826 primary->state.emitted_pipeline =
3827 secondary->state.emitted_pipeline;
3828 }
3829
3830 /* When the secondary command buffer is graphics only we don't
3831 * need to re-emit the current compute pipeline.
3832 */
3833 if (secondary->state.emitted_compute_pipeline) {
3834 primary->state.emitted_compute_pipeline =
3835 secondary->state.emitted_compute_pipeline;
3836 }
3837
3838 /* Only re-emit the draw packets when needed. */
3839 if (secondary->state.last_primitive_reset_en != -1) {
3840 primary->state.last_primitive_reset_en =
3841 secondary->state.last_primitive_reset_en;
3842 }
3843
3844 if (secondary->state.last_primitive_reset_index) {
3845 primary->state.last_primitive_reset_index =
3846 secondary->state.last_primitive_reset_index;
3847 }
3848
3849 if (secondary->state.last_ia_multi_vgt_param) {
3850 primary->state.last_ia_multi_vgt_param =
3851 secondary->state.last_ia_multi_vgt_param;
3852 }
3853
3854 primary->state.last_first_instance = secondary->state.last_first_instance;
3855 primary->state.last_num_instances = secondary->state.last_num_instances;
3856 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3857
3858 if (secondary->state.last_index_type != -1) {
3859 primary->state.last_index_type =
3860 secondary->state.last_index_type;
3861 }
3862 }
3863
3864 /* After executing commands from secondary buffers we have to dirty
3865 * some states.
3866 */
3867 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3868 RADV_CMD_DIRTY_INDEX_BUFFER |
3869 RADV_CMD_DIRTY_DYNAMIC_ALL;
3870 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3871 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3872 }
3873
3874 VkResult radv_CreateCommandPool(
3875 VkDevice _device,
3876 const VkCommandPoolCreateInfo* pCreateInfo,
3877 const VkAllocationCallbacks* pAllocator,
3878 VkCommandPool* pCmdPool)
3879 {
3880 RADV_FROM_HANDLE(radv_device, device, _device);
3881 struct radv_cmd_pool *pool;
3882
3883 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3884 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3885 if (pool == NULL)
3886 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3887
3888 if (pAllocator)
3889 pool->alloc = *pAllocator;
3890 else
3891 pool->alloc = device->alloc;
3892
3893 list_inithead(&pool->cmd_buffers);
3894 list_inithead(&pool->free_cmd_buffers);
3895
3896 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3897
3898 *pCmdPool = radv_cmd_pool_to_handle(pool);
3899
3900 return VK_SUCCESS;
3901
3902 }
3903
3904 void radv_DestroyCommandPool(
3905 VkDevice _device,
3906 VkCommandPool commandPool,
3907 const VkAllocationCallbacks* pAllocator)
3908 {
3909 RADV_FROM_HANDLE(radv_device, device, _device);
3910 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3911
3912 if (!pool)
3913 return;
3914
3915 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3916 &pool->cmd_buffers, pool_link) {
3917 radv_cmd_buffer_destroy(cmd_buffer);
3918 }
3919
3920 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3921 &pool->free_cmd_buffers, pool_link) {
3922 radv_cmd_buffer_destroy(cmd_buffer);
3923 }
3924
3925 vk_free2(&device->alloc, pAllocator, pool);
3926 }
3927
3928 VkResult radv_ResetCommandPool(
3929 VkDevice device,
3930 VkCommandPool commandPool,
3931 VkCommandPoolResetFlags flags)
3932 {
3933 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3934 VkResult result;
3935
3936 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3937 &pool->cmd_buffers, pool_link) {
3938 result = radv_reset_cmd_buffer(cmd_buffer);
3939 if (result != VK_SUCCESS)
3940 return result;
3941 }
3942
3943 return VK_SUCCESS;
3944 }
3945
3946 void radv_TrimCommandPool(
3947 VkDevice device,
3948 VkCommandPool commandPool,
3949 VkCommandPoolTrimFlags flags)
3950 {
3951 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3952
3953 if (!pool)
3954 return;
3955
3956 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3957 &pool->free_cmd_buffers, pool_link) {
3958 radv_cmd_buffer_destroy(cmd_buffer);
3959 }
3960 }
3961
3962 static void
3963 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3964 uint32_t subpass_id)
3965 {
3966 struct radv_cmd_state *state = &cmd_buffer->state;
3967 struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3968
3969 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3970 cmd_buffer->cs, 4096);
3971
3972 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3973
3974 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3975
3976 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3977 const uint32_t a = subpass->attachments[i].attachment;
3978 if (a == VK_ATTACHMENT_UNUSED)
3979 continue;
3980
3981 radv_handle_subpass_image_transition(cmd_buffer,
3982 subpass->attachments[i],
3983 true);
3984 }
3985
3986 radv_cmd_buffer_clear_subpass(cmd_buffer);
3987
3988 assert(cmd_buffer->cs->cdw <= cdw_max);
3989 }
3990
3991 static void
3992 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3993 {
3994 struct radv_cmd_state *state = &cmd_buffer->state;
3995 const struct radv_subpass *subpass = state->subpass;
3996 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3997
3998 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3999
4000 for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
4001 const uint32_t a = subpass->attachments[i].attachment;
4002 if (a == VK_ATTACHMENT_UNUSED)
4003 continue;
4004
4005 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
4006 continue;
4007
4008 VkImageLayout layout = state->pass->attachments[a].final_layout;
4009 struct radv_subpass_attachment att = { a, layout };
4010 radv_handle_subpass_image_transition(cmd_buffer, att, false);
4011 }
4012 }
4013
4014 void radv_CmdBeginRenderPass(
4015 VkCommandBuffer commandBuffer,
4016 const VkRenderPassBeginInfo* pRenderPassBegin,
4017 VkSubpassContents contents)
4018 {
4019 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4020 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
4021 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
4022 VkResult result;
4023
4024 cmd_buffer->state.framebuffer = framebuffer;
4025 cmd_buffer->state.pass = pass;
4026 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
4027
4028 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
4029 if (result != VK_SUCCESS)
4030 return;
4031
4032 result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);
4033 if (result != VK_SUCCESS)
4034 return;
4035
4036 radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
4037 }
4038
4039 void radv_CmdBeginRenderPass2KHR(
4040 VkCommandBuffer commandBuffer,
4041 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
4042 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
4043 {
4044 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
4045 pSubpassBeginInfo->contents);
4046 }
4047
4048 void radv_CmdNextSubpass(
4049 VkCommandBuffer commandBuffer,
4050 VkSubpassContents contents)
4051 {
4052 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4053
4054 uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
4055 radv_cmd_buffer_end_subpass(cmd_buffer);
4056 radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
4057 }
4058
4059 void radv_CmdNextSubpass2KHR(
4060 VkCommandBuffer commandBuffer,
4061 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
4062 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4063 {
4064 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
4065 }
4066
4067 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
4068 {
4069 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
4070 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
4071 if (!radv_get_shader(pipeline, stage))
4072 continue;
4073
4074 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
4075 if (loc->sgpr_idx == -1)
4076 continue;
4077 uint32_t base_reg = pipeline->user_data_0[stage];
4078 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4079
4080 }
4081 if (radv_pipeline_has_gs_copy_shader(pipeline)) {
4082 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
4083 if (loc->sgpr_idx != -1) {
4084 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
4085 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
4086 }
4087 }
4088 }
4089
4090 static void
4091 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4092 uint32_t vertex_count,
4093 bool use_opaque)
4094 {
4095 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
4096 radeon_emit(cmd_buffer->cs, vertex_count);
4097 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
4098 S_0287F0_USE_OPAQUE(use_opaque));
4099 }
4100
4101 static void
4102 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
4103 uint64_t index_va,
4104 uint32_t index_count)
4105 {
4106 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
4107 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
4108 radeon_emit(cmd_buffer->cs, index_va);
4109 radeon_emit(cmd_buffer->cs, index_va >> 32);
4110 radeon_emit(cmd_buffer->cs, index_count);
4111 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
4112 }
4113
4114 static void
4115 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
4116 bool indexed,
4117 uint32_t draw_count,
4118 uint64_t count_va,
4119 uint32_t stride)
4120 {
4121 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4122 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
4123 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
4124 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
4125 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
4126 bool predicating = cmd_buffer->state.predicating;
4127 assert(base_reg);
4128
4129 /* just reset draw state for vertex data */
4130 cmd_buffer->state.last_first_instance = -1;
4131 cmd_buffer->state.last_num_instances = -1;
4132 cmd_buffer->state.last_vertex_offset = -1;
4133
4134 if (draw_count == 1 && !count_va && !draw_id_enable) {
4135 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
4136 PKT3_DRAW_INDIRECT, 3, predicating));
4137 radeon_emit(cs, 0);
4138 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4139 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4140 radeon_emit(cs, di_src_sel);
4141 } else {
4142 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
4143 PKT3_DRAW_INDIRECT_MULTI,
4144 8, predicating));
4145 radeon_emit(cs, 0);
4146 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
4147 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
4148 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
4149 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
4150 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
4151 radeon_emit(cs, draw_count); /* count */
4152 radeon_emit(cs, count_va); /* count_addr */
4153 radeon_emit(cs, count_va >> 32);
4154 radeon_emit(cs, stride); /* stride */
4155 radeon_emit(cs, di_src_sel);
4156 }
4157 }
4158
4159 static void
4160 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
4161 const struct radv_draw_info *info)
4162 {
4163 struct radv_cmd_state *state = &cmd_buffer->state;
4164 struct radeon_winsys *ws = cmd_buffer->device->ws;
4165 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4166
4167 if (info->indirect) {
4168 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4169 uint64_t count_va = 0;
4170
4171 va += info->indirect->offset + info->indirect_offset;
4172
4173 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4174
4175 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
4176 radeon_emit(cs, 1);
4177 radeon_emit(cs, va);
4178 radeon_emit(cs, va >> 32);
4179
4180 if (info->count_buffer) {
4181 count_va = radv_buffer_get_va(info->count_buffer->bo);
4182 count_va += info->count_buffer->offset +
4183 info->count_buffer_offset;
4184
4185 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
4186 }
4187
4188 if (!state->subpass->view_mask) {
4189 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4190 info->indexed,
4191 info->count,
4192 count_va,
4193 info->stride);
4194 } else {
4195 unsigned i;
4196 for_each_bit(i, state->subpass->view_mask) {
4197 radv_emit_view_index(cmd_buffer, i);
4198
4199 radv_cs_emit_indirect_draw_packet(cmd_buffer,
4200 info->indexed,
4201 info->count,
4202 count_va,
4203 info->stride);
4204 }
4205 }
4206 } else {
4207 assert(state->pipeline->graphics.vtx_base_sgpr);
4208
4209 if (info->vertex_offset != state->last_vertex_offset ||
4210 info->first_instance != state->last_first_instance) {
4211 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4212 state->pipeline->graphics.vtx_emit_num);
4213
4214 radeon_emit(cs, info->vertex_offset);
4215 radeon_emit(cs, info->first_instance);
4216 if (state->pipeline->graphics.vtx_emit_num == 3)
4217 radeon_emit(cs, 0);
4218 state->last_first_instance = info->first_instance;
4219 state->last_vertex_offset = info->vertex_offset;
4220 }
4221
4222 if (state->last_num_instances != info->instance_count) {
4223 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
4224 radeon_emit(cs, info->instance_count);
4225 state->last_num_instances = info->instance_count;
4226 }
4227
4228 if (info->indexed) {
4229 int index_size = state->index_type ? 4 : 2;
4230 uint64_t index_va;
4231
4232 index_va = state->index_va;
4233 index_va += info->first_index * index_size;
4234
4235 if (!state->subpass->view_mask) {
4236 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4237 index_va,
4238 info->count);
4239 } else {
4240 unsigned i;
4241 for_each_bit(i, state->subpass->view_mask) {
4242 radv_emit_view_index(cmd_buffer, i);
4243
4244 radv_cs_emit_draw_indexed_packet(cmd_buffer,
4245 index_va,
4246 info->count);
4247 }
4248 }
4249 } else {
4250 if (!state->subpass->view_mask) {
4251 radv_cs_emit_draw_packet(cmd_buffer,
4252 info->count,
4253 !!info->strmout_buffer);
4254 } else {
4255 unsigned i;
4256 for_each_bit(i, state->subpass->view_mask) {
4257 radv_emit_view_index(cmd_buffer, i);
4258
4259 radv_cs_emit_draw_packet(cmd_buffer,
4260 info->count,
4261 !!info->strmout_buffer);
4262 }
4263 }
4264 }
4265 }
4266 }
4267
4268 /*
4269 * Vega and raven have a bug which triggers if there are multiple context
4270 * register contexts active at the same time with different scissor values.
4271 *
4272 * There are two possible workarounds:
4273 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
4274 * there is only ever 1 active set of scissor values at the same time.
4275 *
4276 * 2) Whenever the hardware switches contexts we have to set the scissor
4277 * registers again even if it is a noop. That way the new context gets
4278 * the correct scissor values.
4279 *
4280 * This implements option 2. radv_need_late_scissor_emission needs to
4281 * return true on affected HW if radv_emit_all_graphics_states sets
4282 * any context registers.
4283 */
4284 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
4285 const struct radv_draw_info *info)
4286 {
4287 struct radv_cmd_state *state = &cmd_buffer->state;
4288
4289 if (!cmd_buffer->device->physical_device->has_scissor_bug)
4290 return false;
4291
4292 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
4293 return true;
4294
4295 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
4296
4297 /* Index, vertex and streamout buffers don't change context regs, and
4298 * pipeline is already handled.
4299 */
4300 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
4301 RADV_CMD_DIRTY_VERTEX_BUFFER |
4302 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
4303 RADV_CMD_DIRTY_PIPELINE);
4304
4305 if (cmd_buffer->state.dirty & used_states)
4306 return true;
4307
4308 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
4309 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
4310 return true;
4311
4312 return false;
4313 }
4314
4315 static void
4316 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
4317 const struct radv_draw_info *info)
4318 {
4319 bool late_scissor_emission;
4320
4321 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
4322 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
4323 radv_emit_rbplus_state(cmd_buffer);
4324
4325 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
4326 radv_emit_graphics_pipeline(cmd_buffer);
4327
4328 /* This should be before the cmd_buffer->state.dirty is cleared
4329 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
4330 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
4331 late_scissor_emission =
4332 radv_need_late_scissor_emission(cmd_buffer, info);
4333
4334 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
4335 radv_emit_framebuffer_state(cmd_buffer);
4336
4337 if (info->indexed) {
4338 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
4339 radv_emit_index_buffer(cmd_buffer);
4340 } else {
4341 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
4342 * so the state must be re-emitted before the next indexed
4343 * draw.
4344 */
4345 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
4346 cmd_buffer->state.last_index_type = -1;
4347 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
4348 }
4349 }
4350
4351 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
4352
4353 radv_emit_draw_registers(cmd_buffer, info);
4354
4355 if (late_scissor_emission)
4356 radv_emit_scissor(cmd_buffer);
4357 }
4358
4359 static void
4360 radv_draw(struct radv_cmd_buffer *cmd_buffer,
4361 const struct radv_draw_info *info)
4362 {
4363 struct radeon_info *rad_info =
4364 &cmd_buffer->device->physical_device->rad_info;
4365 bool has_prefetch =
4366 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4367 bool pipeline_is_dirty =
4368 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
4369 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
4370
4371 MAYBE_UNUSED unsigned cdw_max =
4372 radeon_check_space(cmd_buffer->device->ws,
4373 cmd_buffer->cs, 4096);
4374
4375 if (likely(!info->indirect)) {
4376 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
4377 * no workaround for indirect draws, but we can at least skip
4378 * direct draws.
4379 */
4380 if (unlikely(!info->instance_count))
4381 return;
4382
4383 /* Handle count == 0. */
4384 if (unlikely(!info->count && !info->strmout_buffer))
4385 return;
4386 }
4387
4388 /* Use optimal packet order based on whether we need to sync the
4389 * pipeline.
4390 */
4391 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4392 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4393 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4394 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4395 /* If we have to wait for idle, set all states first, so that
4396 * all SET packets are processed in parallel with previous draw
4397 * calls. Then upload descriptors, set shader pointers, and
4398 * draw, and prefetch at the end. This ensures that the time
4399 * the CUs are idle is very short. (there are only SET_SH
4400 * packets between the wait and the draw)
4401 */
4402 radv_emit_all_graphics_states(cmd_buffer, info);
4403 si_emit_cache_flush(cmd_buffer);
4404 /* <-- CUs are idle here --> */
4405
4406 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4407
4408 radv_emit_draw_packets(cmd_buffer, info);
4409 /* <-- CUs are busy here --> */
4410
4411 /* Start prefetches after the draw has been started. Both will
4412 * run in parallel, but starting the draw first is more
4413 * important.
4414 */
4415 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4416 radv_emit_prefetch_L2(cmd_buffer,
4417 cmd_buffer->state.pipeline, false);
4418 }
4419 } else {
4420 /* If we don't wait for idle, start prefetches first, then set
4421 * states, and draw at the end.
4422 */
4423 si_emit_cache_flush(cmd_buffer);
4424
4425 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4426 /* Only prefetch the vertex shader and VBO descriptors
4427 * in order to start the draw as soon as possible.
4428 */
4429 radv_emit_prefetch_L2(cmd_buffer,
4430 cmd_buffer->state.pipeline, true);
4431 }
4432
4433 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
4434
4435 radv_emit_all_graphics_states(cmd_buffer, info);
4436 radv_emit_draw_packets(cmd_buffer, info);
4437
4438 /* Prefetch the remaining shaders after the draw has been
4439 * started.
4440 */
4441 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
4442 radv_emit_prefetch_L2(cmd_buffer,
4443 cmd_buffer->state.pipeline, false);
4444 }
4445 }
4446
4447 /* Workaround for a VGT hang when streamout is enabled.
4448 * It must be done after drawing.
4449 */
4450 if (cmd_buffer->state.streamout.streamout_enabled &&
4451 (rad_info->family == CHIP_HAWAII ||
4452 rad_info->family == CHIP_TONGA ||
4453 rad_info->family == CHIP_FIJI)) {
4454 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
4455 }
4456
4457 assert(cmd_buffer->cs->cdw <= cdw_max);
4458 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
4459 }
4460
4461 void radv_CmdDraw(
4462 VkCommandBuffer commandBuffer,
4463 uint32_t vertexCount,
4464 uint32_t instanceCount,
4465 uint32_t firstVertex,
4466 uint32_t firstInstance)
4467 {
4468 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4469 struct radv_draw_info info = {};
4470
4471 info.count = vertexCount;
4472 info.instance_count = instanceCount;
4473 info.first_instance = firstInstance;
4474 info.vertex_offset = firstVertex;
4475
4476 radv_draw(cmd_buffer, &info);
4477 }
4478
4479 void radv_CmdDrawIndexed(
4480 VkCommandBuffer commandBuffer,
4481 uint32_t indexCount,
4482 uint32_t instanceCount,
4483 uint32_t firstIndex,
4484 int32_t vertexOffset,
4485 uint32_t firstInstance)
4486 {
4487 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4488 struct radv_draw_info info = {};
4489
4490 info.indexed = true;
4491 info.count = indexCount;
4492 info.instance_count = instanceCount;
4493 info.first_index = firstIndex;
4494 info.vertex_offset = vertexOffset;
4495 info.first_instance = firstInstance;
4496
4497 radv_draw(cmd_buffer, &info);
4498 }
4499
4500 void radv_CmdDrawIndirect(
4501 VkCommandBuffer commandBuffer,
4502 VkBuffer _buffer,
4503 VkDeviceSize offset,
4504 uint32_t drawCount,
4505 uint32_t stride)
4506 {
4507 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4508 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4509 struct radv_draw_info info = {};
4510
4511 info.count = drawCount;
4512 info.indirect = buffer;
4513 info.indirect_offset = offset;
4514 info.stride = stride;
4515
4516 radv_draw(cmd_buffer, &info);
4517 }
4518
4519 void radv_CmdDrawIndexedIndirect(
4520 VkCommandBuffer commandBuffer,
4521 VkBuffer _buffer,
4522 VkDeviceSize offset,
4523 uint32_t drawCount,
4524 uint32_t stride)
4525 {
4526 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4527 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4528 struct radv_draw_info info = {};
4529
4530 info.indexed = true;
4531 info.count = drawCount;
4532 info.indirect = buffer;
4533 info.indirect_offset = offset;
4534 info.stride = stride;
4535
4536 radv_draw(cmd_buffer, &info);
4537 }
4538
4539 void radv_CmdDrawIndirectCountKHR(
4540 VkCommandBuffer commandBuffer,
4541 VkBuffer _buffer,
4542 VkDeviceSize offset,
4543 VkBuffer _countBuffer,
4544 VkDeviceSize countBufferOffset,
4545 uint32_t maxDrawCount,
4546 uint32_t stride)
4547 {
4548 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4549 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4550 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4551 struct radv_draw_info info = {};
4552
4553 info.count = maxDrawCount;
4554 info.indirect = buffer;
4555 info.indirect_offset = offset;
4556 info.count_buffer = count_buffer;
4557 info.count_buffer_offset = countBufferOffset;
4558 info.stride = stride;
4559
4560 radv_draw(cmd_buffer, &info);
4561 }
4562
4563 void radv_CmdDrawIndexedIndirectCountKHR(
4564 VkCommandBuffer commandBuffer,
4565 VkBuffer _buffer,
4566 VkDeviceSize offset,
4567 VkBuffer _countBuffer,
4568 VkDeviceSize countBufferOffset,
4569 uint32_t maxDrawCount,
4570 uint32_t stride)
4571 {
4572 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4573 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4574 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4575 struct radv_draw_info info = {};
4576
4577 info.indexed = true;
4578 info.count = maxDrawCount;
4579 info.indirect = buffer;
4580 info.indirect_offset = offset;
4581 info.count_buffer = count_buffer;
4582 info.count_buffer_offset = countBufferOffset;
4583 info.stride = stride;
4584
4585 radv_draw(cmd_buffer, &info);
4586 }
4587
4588 struct radv_dispatch_info {
4589 /**
4590 * Determine the layout of the grid (in block units) to be used.
4591 */
4592 uint32_t blocks[3];
4593
4594 /**
4595 * A starting offset for the grid. If unaligned is set, the offset
4596 * must still be aligned.
4597 */
4598 uint32_t offsets[3];
4599 /**
4600 * Whether it's an unaligned compute dispatch.
4601 */
4602 bool unaligned;
4603
4604 /**
4605 * Indirect compute parameters resource.
4606 */
4607 struct radv_buffer *indirect;
4608 uint64_t indirect_offset;
4609 };
4610
4611 static void
4612 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4613 const struct radv_dispatch_info *info)
4614 {
4615 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4616 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4617 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4618 struct radeon_winsys *ws = cmd_buffer->device->ws;
4619 bool predicating = cmd_buffer->state.predicating;
4620 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4621 struct radv_userdata_info *loc;
4622
4623 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4624 AC_UD_CS_GRID_SIZE);
4625
4626 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4627
4628 if (info->indirect) {
4629 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4630
4631 va += info->indirect->offset + info->indirect_offset;
4632
4633 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4634
4635 if (loc->sgpr_idx != -1) {
4636 for (unsigned i = 0; i < 3; ++i) {
4637 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4638 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4639 COPY_DATA_DST_SEL(COPY_DATA_REG));
4640 radeon_emit(cs, (va + 4 * i));
4641 radeon_emit(cs, (va + 4 * i) >> 32);
4642 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4643 + loc->sgpr_idx * 4) >> 2) + i);
4644 radeon_emit(cs, 0);
4645 }
4646 }
4647
4648 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4649 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4650 PKT3_SHADER_TYPE_S(1));
4651 radeon_emit(cs, va);
4652 radeon_emit(cs, va >> 32);
4653 radeon_emit(cs, dispatch_initiator);
4654 } else {
4655 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4656 PKT3_SHADER_TYPE_S(1));
4657 radeon_emit(cs, 1);
4658 radeon_emit(cs, va);
4659 radeon_emit(cs, va >> 32);
4660
4661 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4662 PKT3_SHADER_TYPE_S(1));
4663 radeon_emit(cs, 0);
4664 radeon_emit(cs, dispatch_initiator);
4665 }
4666 } else {
4667 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4668 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4669
4670 if (info->unaligned) {
4671 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4672 unsigned remainder[3];
4673
4674 /* If aligned, these should be an entire block size,
4675 * not 0.
4676 */
4677 remainder[0] = blocks[0] + cs_block_size[0] -
4678 align_u32_npot(blocks[0], cs_block_size[0]);
4679 remainder[1] = blocks[1] + cs_block_size[1] -
4680 align_u32_npot(blocks[1], cs_block_size[1]);
4681 remainder[2] = blocks[2] + cs_block_size[2] -
4682 align_u32_npot(blocks[2], cs_block_size[2]);
4683
4684 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4685 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4686 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4687
4688 for(unsigned i = 0; i < 3; ++i) {
4689 assert(offsets[i] % cs_block_size[i] == 0);
4690 offsets[i] /= cs_block_size[i];
4691 }
4692
4693 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4694 radeon_emit(cs,
4695 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4696 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4697 radeon_emit(cs,
4698 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4699 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4700 radeon_emit(cs,
4701 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4702 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4703
4704 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4705 }
4706
4707 if (loc->sgpr_idx != -1) {
4708 assert(loc->num_sgprs == 3);
4709
4710 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4711 loc->sgpr_idx * 4, 3);
4712 radeon_emit(cs, blocks[0]);
4713 radeon_emit(cs, blocks[1]);
4714 radeon_emit(cs, blocks[2]);
4715 }
4716
4717 if (offsets[0] || offsets[1] || offsets[2]) {
4718 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4719 radeon_emit(cs, offsets[0]);
4720 radeon_emit(cs, offsets[1]);
4721 radeon_emit(cs, offsets[2]);
4722
4723 /* The blocks in the packet are not counts but end values. */
4724 for (unsigned i = 0; i < 3; ++i)
4725 blocks[i] += offsets[i];
4726 } else {
4727 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4728 }
4729
4730 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4731 PKT3_SHADER_TYPE_S(1));
4732 radeon_emit(cs, blocks[0]);
4733 radeon_emit(cs, blocks[1]);
4734 radeon_emit(cs, blocks[2]);
4735 radeon_emit(cs, dispatch_initiator);
4736 }
4737
4738 assert(cmd_buffer->cs->cdw <= cdw_max);
4739 }
4740
4741 static void
4742 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4743 {
4744 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4745 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4746 }
4747
4748 static void
4749 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4750 const struct radv_dispatch_info *info)
4751 {
4752 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4753 bool has_prefetch =
4754 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
4755 bool pipeline_is_dirty = pipeline &&
4756 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4757
4758 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4759 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4760 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4761 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4762 /* If we have to wait for idle, set all states first, so that
4763 * all SET packets are processed in parallel with previous draw
4764 * calls. Then upload descriptors, set shader pointers, and
4765 * dispatch, and prefetch at the end. This ensures that the
4766 * time the CUs are idle is very short. (there are only SET_SH
4767 * packets between the wait and the draw)
4768 */
4769 radv_emit_compute_pipeline(cmd_buffer);
4770 si_emit_cache_flush(cmd_buffer);
4771 /* <-- CUs are idle here --> */
4772
4773 radv_upload_compute_shader_descriptors(cmd_buffer);
4774
4775 radv_emit_dispatch_packets(cmd_buffer, info);
4776 /* <-- CUs are busy here --> */
4777
4778 /* Start prefetches after the dispatch has been started. Both
4779 * will run in parallel, but starting the dispatch first is
4780 * more important.
4781 */
4782 if (has_prefetch && pipeline_is_dirty) {
4783 radv_emit_shader_prefetch(cmd_buffer,
4784 pipeline->shaders[MESA_SHADER_COMPUTE]);
4785 }
4786 } else {
4787 /* If we don't wait for idle, start prefetches first, then set
4788 * states, and dispatch at the end.
4789 */
4790 si_emit_cache_flush(cmd_buffer);
4791
4792 if (has_prefetch && pipeline_is_dirty) {
4793 radv_emit_shader_prefetch(cmd_buffer,
4794 pipeline->shaders[MESA_SHADER_COMPUTE]);
4795 }
4796
4797 radv_upload_compute_shader_descriptors(cmd_buffer);
4798
4799 radv_emit_compute_pipeline(cmd_buffer);
4800 radv_emit_dispatch_packets(cmd_buffer, info);
4801 }
4802
4803 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4804 }
4805
4806 void radv_CmdDispatchBase(
4807 VkCommandBuffer commandBuffer,
4808 uint32_t base_x,
4809 uint32_t base_y,
4810 uint32_t base_z,
4811 uint32_t x,
4812 uint32_t y,
4813 uint32_t z)
4814 {
4815 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4816 struct radv_dispatch_info info = {};
4817
4818 info.blocks[0] = x;
4819 info.blocks[1] = y;
4820 info.blocks[2] = z;
4821
4822 info.offsets[0] = base_x;
4823 info.offsets[1] = base_y;
4824 info.offsets[2] = base_z;
4825 radv_dispatch(cmd_buffer, &info);
4826 }
4827
4828 void radv_CmdDispatch(
4829 VkCommandBuffer commandBuffer,
4830 uint32_t x,
4831 uint32_t y,
4832 uint32_t z)
4833 {
4834 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4835 }
4836
4837 void radv_CmdDispatchIndirect(
4838 VkCommandBuffer commandBuffer,
4839 VkBuffer _buffer,
4840 VkDeviceSize offset)
4841 {
4842 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4843 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4844 struct radv_dispatch_info info = {};
4845
4846 info.indirect = buffer;
4847 info.indirect_offset = offset;
4848
4849 radv_dispatch(cmd_buffer, &info);
4850 }
4851
4852 void radv_unaligned_dispatch(
4853 struct radv_cmd_buffer *cmd_buffer,
4854 uint32_t x,
4855 uint32_t y,
4856 uint32_t z)
4857 {
4858 struct radv_dispatch_info info = {};
4859
4860 info.blocks[0] = x;
4861 info.blocks[1] = y;
4862 info.blocks[2] = z;
4863 info.unaligned = 1;
4864
4865 radv_dispatch(cmd_buffer, &info);
4866 }
4867
4868 void radv_CmdEndRenderPass(
4869 VkCommandBuffer commandBuffer)
4870 {
4871 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4872
4873 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4874
4875 radv_cmd_buffer_end_subpass(cmd_buffer);
4876
4877 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4878 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.subpass_sample_locs);
4879
4880 cmd_buffer->state.pass = NULL;
4881 cmd_buffer->state.subpass = NULL;
4882 cmd_buffer->state.attachments = NULL;
4883 cmd_buffer->state.framebuffer = NULL;
4884 cmd_buffer->state.subpass_sample_locs = NULL;
4885 }
4886
4887 void radv_CmdEndRenderPass2KHR(
4888 VkCommandBuffer commandBuffer,
4889 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4890 {
4891 radv_CmdEndRenderPass(commandBuffer);
4892 }
4893
4894 /*
4895 * For HTILE we have the following interesting clear words:
4896 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4897 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4898 * 0xfffffff0: Clear depth to 1.0
4899 * 0x00000000: Clear depth to 0.0
4900 */
4901 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4902 struct radv_image *image,
4903 const VkImageSubresourceRange *range,
4904 uint32_t clear_word)
4905 {
4906 assert(range->baseMipLevel == 0);
4907 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4908 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4909 struct radv_cmd_state *state = &cmd_buffer->state;
4910 VkClearDepthStencilValue value = {};
4911
4912 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4913 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4914
4915 state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, clear_word);
4916
4917 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4918
4919 if (vk_format_is_stencil(image->vk_format))
4920 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4921
4922 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4923
4924 if (radv_image_is_tc_compat_htile(image)) {
4925 /* Initialize the TC-compat metada value to 0 because by
4926 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4927 * need have to conditionally update its value when performing
4928 * a fast depth clear.
4929 */
4930 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4931 }
4932 }
4933
4934 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4935 struct radv_image *image,
4936 VkImageLayout src_layout,
4937 VkImageLayout dst_layout,
4938 unsigned src_queue_mask,
4939 unsigned dst_queue_mask,
4940 const VkImageSubresourceRange *range,
4941 struct radv_sample_locations_state *sample_locs)
4942 {
4943 if (!radv_image_has_htile(image))
4944 return;
4945
4946 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4947 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4948
4949 if (radv_layout_is_htile_compressed(image, dst_layout,
4950 dst_queue_mask)) {
4951 clear_value = 0;
4952 }
4953
4954 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4955 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4956 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4957 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4958 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4959 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4960 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4961 VkImageSubresourceRange local_range = *range;
4962 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4963 local_range.baseMipLevel = 0;
4964 local_range.levelCount = 1;
4965
4966 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4967 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4968
4969 radv_decompress_depth_image_inplace(cmd_buffer, image,
4970 &local_range, sample_locs);
4971
4972 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4973 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4974 }
4975 }
4976
4977 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4978 struct radv_image *image,
4979 const VkImageSubresourceRange *range,
4980 uint32_t value)
4981 {
4982 struct radv_cmd_state *state = &cmd_buffer->state;
4983
4984 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4985 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4986
4987 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
4988
4989 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4990 }
4991
4992 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4993 struct radv_image *image,
4994 const VkImageSubresourceRange *range)
4995 {
4996 struct radv_cmd_state *state = &cmd_buffer->state;
4997 static const uint32_t fmask_clear_values[4] = {
4998 0x00000000,
4999 0x02020202,
5000 0xE4E4E4E4,
5001 0x76543210
5002 };
5003 uint32_t log2_samples = util_logbase2(image->info.samples);
5004 uint32_t value = fmask_clear_values[log2_samples];
5005
5006 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5007 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5008
5009 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
5010
5011 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5012 }
5013
5014 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
5015 struct radv_image *image,
5016 const VkImageSubresourceRange *range, uint32_t value)
5017 {
5018 struct radv_cmd_state *state = &cmd_buffer->state;
5019 unsigned size = 0;
5020
5021 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5022 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5023
5024 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
5025
5026 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
5027 /* When DCC is enabled with mipmaps, some levels might not
5028 * support fast clears and we have to initialize them as "fully
5029 * expanded".
5030 */
5031 /* Compute the size of all fast clearable DCC levels. */
5032 for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
5033 struct legacy_surf_level *surf_level =
5034 &image->planes[0].surface.u.legacy.level[i];
5035 unsigned dcc_fast_clear_size =
5036 surf_level->dcc_slice_fast_clear_size * image->info.array_size;
5037
5038 if (!dcc_fast_clear_size)
5039 break;
5040
5041 size = surf_level->dcc_offset + dcc_fast_clear_size;
5042 }
5043
5044 /* Initialize the mipmap levels without DCC. */
5045 if (size != image->planes[0].surface.dcc_size) {
5046 state->flush_bits |=
5047 radv_fill_buffer(cmd_buffer, image->bo,
5048 image->offset + image->dcc_offset + size,
5049 image->planes[0].surface.dcc_size - size,
5050 0xffffffff);
5051 }
5052 }
5053
5054 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
5055 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
5056 }
5057
5058 /**
5059 * Initialize DCC/FMASK/CMASK metadata for a color image.
5060 */
5061 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
5062 struct radv_image *image,
5063 VkImageLayout src_layout,
5064 VkImageLayout dst_layout,
5065 unsigned src_queue_mask,
5066 unsigned dst_queue_mask,
5067 const VkImageSubresourceRange *range)
5068 {
5069 if (radv_image_has_cmask(image)) {
5070 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5071
5072 /* TODO: clarify this. */
5073 if (radv_image_has_fmask(image)) {
5074 value = 0xccccccccu;
5075 }
5076
5077 radv_initialise_cmask(cmd_buffer, image, range, value);
5078 }
5079
5080 if (radv_image_has_fmask(image)) {
5081 radv_initialize_fmask(cmd_buffer, image, range);
5082 }
5083
5084 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5085 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
5086 bool need_decompress_pass = false;
5087
5088 if (radv_layout_dcc_compressed(image, dst_layout,
5089 dst_queue_mask)) {
5090 value = 0x20202020u;
5091 need_decompress_pass = true;
5092 }
5093
5094 radv_initialize_dcc(cmd_buffer, image, range, value);
5095
5096 radv_update_fce_metadata(cmd_buffer, image, range,
5097 need_decompress_pass);
5098 }
5099
5100 if (radv_image_has_cmask(image) ||
5101 radv_dcc_enabled(image, range->baseMipLevel)) {
5102 uint32_t color_values[2] = {};
5103 radv_set_color_clear_metadata(cmd_buffer, image, range,
5104 color_values);
5105 }
5106 }
5107
5108 /**
5109 * Handle color image transitions for DCC/FMASK/CMASK.
5110 */
5111 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
5112 struct radv_image *image,
5113 VkImageLayout src_layout,
5114 VkImageLayout dst_layout,
5115 unsigned src_queue_mask,
5116 unsigned dst_queue_mask,
5117 const VkImageSubresourceRange *range)
5118 {
5119 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
5120 radv_init_color_image_metadata(cmd_buffer, image,
5121 src_layout, dst_layout,
5122 src_queue_mask, dst_queue_mask,
5123 range);
5124 return;
5125 }
5126
5127 if (radv_dcc_enabled(image, range->baseMipLevel)) {
5128 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
5129 radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
5130 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
5131 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
5132 radv_decompress_dcc(cmd_buffer, image, range);
5133 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5134 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5135 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5136 }
5137 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
5138 bool fce_eliminate = false, fmask_expand = false;
5139
5140 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
5141 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
5142 fce_eliminate = true;
5143 }
5144
5145 if (radv_image_has_fmask(image)) {
5146 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
5147 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
5148 /* A FMASK decompress is required before doing
5149 * a MSAA decompress using FMASK.
5150 */
5151 fmask_expand = true;
5152 }
5153 }
5154
5155 if (fce_eliminate || fmask_expand)
5156 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
5157
5158 if (fmask_expand)
5159 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
5160 }
5161 }
5162
5163 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
5164 struct radv_image *image,
5165 VkImageLayout src_layout,
5166 VkImageLayout dst_layout,
5167 uint32_t src_family,
5168 uint32_t dst_family,
5169 const VkImageSubresourceRange *range,
5170 struct radv_sample_locations_state *sample_locs)
5171 {
5172 if (image->exclusive && src_family != dst_family) {
5173 /* This is an acquire or a release operation and there will be
5174 * a corresponding release/acquire. Do the transition in the
5175 * most flexible queue. */
5176
5177 assert(src_family == cmd_buffer->queue_family_index ||
5178 dst_family == cmd_buffer->queue_family_index);
5179
5180 if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
5181 src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
5182 return;
5183
5184 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
5185 return;
5186
5187 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
5188 (src_family == RADV_QUEUE_GENERAL ||
5189 dst_family == RADV_QUEUE_GENERAL))
5190 return;
5191 }
5192
5193 if (src_layout == dst_layout)
5194 return;
5195
5196 unsigned src_queue_mask =
5197 radv_image_queue_family_mask(image, src_family,
5198 cmd_buffer->queue_family_index);
5199 unsigned dst_queue_mask =
5200 radv_image_queue_family_mask(image, dst_family,
5201 cmd_buffer->queue_family_index);
5202
5203 if (vk_format_is_depth(image->vk_format)) {
5204 radv_handle_depth_image_transition(cmd_buffer, image,
5205 src_layout, dst_layout,
5206 src_queue_mask, dst_queue_mask,
5207 range, sample_locs);
5208 } else {
5209 radv_handle_color_image_transition(cmd_buffer, image,
5210 src_layout, dst_layout,
5211 src_queue_mask, dst_queue_mask,
5212 range);
5213 }
5214 }
5215
5216 struct radv_barrier_info {
5217 uint32_t eventCount;
5218 const VkEvent *pEvents;
5219 VkPipelineStageFlags srcStageMask;
5220 VkPipelineStageFlags dstStageMask;
5221 };
5222
5223 static void
5224 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
5225 uint32_t memoryBarrierCount,
5226 const VkMemoryBarrier *pMemoryBarriers,
5227 uint32_t bufferMemoryBarrierCount,
5228 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
5229 uint32_t imageMemoryBarrierCount,
5230 const VkImageMemoryBarrier *pImageMemoryBarriers,
5231 const struct radv_barrier_info *info)
5232 {
5233 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5234 enum radv_cmd_flush_bits src_flush_bits = 0;
5235 enum radv_cmd_flush_bits dst_flush_bits = 0;
5236
5237 for (unsigned i = 0; i < info->eventCount; ++i) {
5238 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
5239 uint64_t va = radv_buffer_get_va(event->bo);
5240
5241 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5242
5243 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
5244
5245 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
5246 assert(cmd_buffer->cs->cdw <= cdw_max);
5247 }
5248
5249 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
5250 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
5251 NULL);
5252 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
5253 NULL);
5254 }
5255
5256 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
5257 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
5258 NULL);
5259 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
5260 NULL);
5261 }
5262
5263 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5264 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5265
5266 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
5267 image);
5268 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
5269 image);
5270 }
5271
5272 /* The Vulkan spec 1.1.98 says:
5273 *
5274 * "An execution dependency with only
5275 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
5276 * will only prevent that stage from executing in subsequently
5277 * submitted commands. As this stage does not perform any actual
5278 * execution, this is not observable - in effect, it does not delay
5279 * processing of subsequent commands. Similarly an execution dependency
5280 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
5281 * will effectively not wait for any prior commands to complete."
5282 */
5283 if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
5284 radv_stage_flush(cmd_buffer, info->srcStageMask);
5285 cmd_buffer->state.flush_bits |= src_flush_bits;
5286
5287 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
5288 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
5289
5290 const struct VkSampleLocationsInfoEXT *sample_locs_info =
5291 vk_find_struct_const(pImageMemoryBarriers[i].pNext,
5292 SAMPLE_LOCATIONS_INFO_EXT);
5293 struct radv_sample_locations_state sample_locations = {};
5294
5295 if (sample_locs_info) {
5296 assert(image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
5297 sample_locations.per_pixel = sample_locs_info->sampleLocationsPerPixel;
5298 sample_locations.grid_size = sample_locs_info->sampleLocationGridSize;
5299 sample_locations.count = sample_locs_info->sampleLocationsCount;
5300 typed_memcpy(&sample_locations.locations[0],
5301 sample_locs_info->pSampleLocations,
5302 sample_locs_info->sampleLocationsCount);
5303 }
5304
5305 radv_handle_image_transition(cmd_buffer, image,
5306 pImageMemoryBarriers[i].oldLayout,
5307 pImageMemoryBarriers[i].newLayout,
5308 pImageMemoryBarriers[i].srcQueueFamilyIndex,
5309 pImageMemoryBarriers[i].dstQueueFamilyIndex,
5310 &pImageMemoryBarriers[i].subresourceRange,
5311 sample_locs_info ? &sample_locations : NULL);
5312 }
5313
5314 /* Make sure CP DMA is idle because the driver might have performed a
5315 * DMA operation for copying or filling buffers/images.
5316 */
5317 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5318 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5319 si_cp_dma_wait_for_idle(cmd_buffer);
5320
5321 cmd_buffer->state.flush_bits |= dst_flush_bits;
5322 }
5323
5324 void radv_CmdPipelineBarrier(
5325 VkCommandBuffer commandBuffer,
5326 VkPipelineStageFlags srcStageMask,
5327 VkPipelineStageFlags destStageMask,
5328 VkBool32 byRegion,
5329 uint32_t memoryBarrierCount,
5330 const VkMemoryBarrier* pMemoryBarriers,
5331 uint32_t bufferMemoryBarrierCount,
5332 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5333 uint32_t imageMemoryBarrierCount,
5334 const VkImageMemoryBarrier* pImageMemoryBarriers)
5335 {
5336 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5337 struct radv_barrier_info info;
5338
5339 info.eventCount = 0;
5340 info.pEvents = NULL;
5341 info.srcStageMask = srcStageMask;
5342 info.dstStageMask = destStageMask;
5343
5344 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5345 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5346 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5347 }
5348
5349
5350 static void write_event(struct radv_cmd_buffer *cmd_buffer,
5351 struct radv_event *event,
5352 VkPipelineStageFlags stageMask,
5353 unsigned value)
5354 {
5355 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5356 uint64_t va = radv_buffer_get_va(event->bo);
5357
5358 si_emit_cache_flush(cmd_buffer);
5359
5360 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
5361
5362 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);
5363
5364 /* Flags that only require a top-of-pipe event. */
5365 VkPipelineStageFlags top_of_pipe_flags =
5366 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
5367
5368 /* Flags that only require a post-index-fetch event. */
5369 VkPipelineStageFlags post_index_fetch_flags =
5370 top_of_pipe_flags |
5371 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
5372 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
5373
5374 /* Make sure CP DMA is idle because the driver might have performed a
5375 * DMA operation for copying or filling buffers/images.
5376 */
5377 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
5378 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
5379 si_cp_dma_wait_for_idle(cmd_buffer);
5380
5381 /* TODO: Emit EOS events for syncing PS/CS stages. */
5382
5383 if (!(stageMask & ~top_of_pipe_flags)) {
5384 /* Just need to sync the PFP engine. */
5385 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5386 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5387 S_370_WR_CONFIRM(1) |
5388 S_370_ENGINE_SEL(V_370_PFP));
5389 radeon_emit(cs, va);
5390 radeon_emit(cs, va >> 32);
5391 radeon_emit(cs, value);
5392 } else if (!(stageMask & ~post_index_fetch_flags)) {
5393 /* Sync ME because PFP reads index and indirect buffers. */
5394 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
5395 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
5396 S_370_WR_CONFIRM(1) |
5397 S_370_ENGINE_SEL(V_370_ME));
5398 radeon_emit(cs, va);
5399 radeon_emit(cs, va >> 32);
5400 radeon_emit(cs, value);
5401 } else {
5402 /* Otherwise, sync all prior GPU work using an EOP event. */
5403 si_cs_emit_write_event_eop(cs,
5404 cmd_buffer->device->physical_device->rad_info.chip_class,
5405 radv_cmd_buffer_uses_mec(cmd_buffer),
5406 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5407 EOP_DST_SEL_MEM,
5408 EOP_DATA_SEL_VALUE_32BIT, va, value,
5409 cmd_buffer->gfx9_eop_bug_va);
5410 }
5411
5412 assert(cmd_buffer->cs->cdw <= cdw_max);
5413 }
5414
5415 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
5416 VkEvent _event,
5417 VkPipelineStageFlags stageMask)
5418 {
5419 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5420 RADV_FROM_HANDLE(radv_event, event, _event);
5421
5422 write_event(cmd_buffer, event, stageMask, 1);
5423 }
5424
5425 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
5426 VkEvent _event,
5427 VkPipelineStageFlags stageMask)
5428 {
5429 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5430 RADV_FROM_HANDLE(radv_event, event, _event);
5431
5432 write_event(cmd_buffer, event, stageMask, 0);
5433 }
5434
5435 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
5436 uint32_t eventCount,
5437 const VkEvent* pEvents,
5438 VkPipelineStageFlags srcStageMask,
5439 VkPipelineStageFlags dstStageMask,
5440 uint32_t memoryBarrierCount,
5441 const VkMemoryBarrier* pMemoryBarriers,
5442 uint32_t bufferMemoryBarrierCount,
5443 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
5444 uint32_t imageMemoryBarrierCount,
5445 const VkImageMemoryBarrier* pImageMemoryBarriers)
5446 {
5447 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5448 struct radv_barrier_info info;
5449
5450 info.eventCount = eventCount;
5451 info.pEvents = pEvents;
5452 info.srcStageMask = 0;
5453
5454 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
5455 bufferMemoryBarrierCount, pBufferMemoryBarriers,
5456 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
5457 }
5458
5459
5460 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
5461 uint32_t deviceMask)
5462 {
5463 /* No-op */
5464 }
5465
5466 /* VK_EXT_conditional_rendering */
5467 void radv_CmdBeginConditionalRenderingEXT(
5468 VkCommandBuffer commandBuffer,
5469 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
5470 {
5471 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5472 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
5473 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5474 bool draw_visible = true;
5475 uint64_t pred_value = 0;
5476 uint64_t va, new_va;
5477 unsigned pred_offset;
5478
5479 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
5480
5481 /* By default, if the 32-bit value at offset in buffer memory is zero,
5482 * then the rendering commands are discarded, otherwise they are
5483 * executed as normal. If the inverted flag is set, all commands are
5484 * discarded if the value is non zero.
5485 */
5486 if (pConditionalRenderingBegin->flags &
5487 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
5488 draw_visible = false;
5489 }
5490
5491 si_emit_cache_flush(cmd_buffer);
5492
5493 /* From the Vulkan spec 1.1.107:
5494 *
5495 * "If the 32-bit value at offset in buffer memory is zero, then the
5496 * rendering commands are discarded, otherwise they are executed as
5497 * normal. If the value of the predicate in buffer memory changes while
5498 * conditional rendering is active, the rendering commands may be
5499 * discarded in an implementation-dependent way. Some implementations
5500 * may latch the value of the predicate upon beginning conditional
5501 * rendering while others may read it before every rendering command."
5502 *
5503 * But, the AMD hardware treats the predicate as a 64-bit value which
5504 * means we need a workaround in the driver. Luckily, it's not required
5505 * to support if the value changes when predication is active.
5506 *
5507 * The workaround is as follows:
5508 * 1) allocate a 64-value in the upload BO and initialize it to 0
5509 * 2) copy the 32-bit predicate value to the upload BO
5510 * 3) use the new allocated VA address for predication
5511 *
5512 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
5513 * in ME (+ sync PFP) instead of PFP.
5514 */
5515 radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
5516
5517 new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
5518
5519 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5520 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
5521 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5522 COPY_DATA_WR_CONFIRM);
5523 radeon_emit(cs, va);
5524 radeon_emit(cs, va >> 32);
5525 radeon_emit(cs, new_va);
5526 radeon_emit(cs, new_va >> 32);
5527
5528 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
5529 radeon_emit(cs, 0);
5530
5531 /* Enable predication for this command buffer. */
5532 si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
5533 cmd_buffer->state.predicating = true;
5534
5535 /* Store conditional rendering user info. */
5536 cmd_buffer->state.predication_type = draw_visible;
5537 cmd_buffer->state.predication_va = new_va;
5538 }
5539
5540 void radv_CmdEndConditionalRenderingEXT(
5541 VkCommandBuffer commandBuffer)
5542 {
5543 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5544
5545 /* Disable predication for this command buffer. */
5546 si_emit_set_predication_state(cmd_buffer, false, 0);
5547 cmd_buffer->state.predicating = false;
5548
5549 /* Reset conditional rendering user info. */
5550 cmd_buffer->state.predication_type = -1;
5551 cmd_buffer->state.predication_va = 0;
5552 }
5553
5554 /* VK_EXT_transform_feedback */
5555 void radv_CmdBindTransformFeedbackBuffersEXT(
5556 VkCommandBuffer commandBuffer,
5557 uint32_t firstBinding,
5558 uint32_t bindingCount,
5559 const VkBuffer* pBuffers,
5560 const VkDeviceSize* pOffsets,
5561 const VkDeviceSize* pSizes)
5562 {
5563 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5564 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5565 uint8_t enabled_mask = 0;
5566
5567 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
5568 for (uint32_t i = 0; i < bindingCount; i++) {
5569 uint32_t idx = firstBinding + i;
5570
5571 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
5572 sb[idx].offset = pOffsets[i];
5573 sb[idx].size = pSizes[i];
5574
5575 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
5576 sb[idx].buffer->bo);
5577
5578 enabled_mask |= 1 << idx;
5579 }
5580
5581 cmd_buffer->state.streamout.enabled_mask |= enabled_mask;
5582
5583 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
5584 }
5585
5586 static void
5587 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
5588 {
5589 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5590 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5591
5592 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
5593 radeon_emit(cs,
5594 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5595 S_028B94_RAST_STREAM(0) |
5596 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5597 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5598 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5599 radeon_emit(cs, so->hw_enabled_mask &
5600 so->enabled_stream_buffers_mask);
5601
5602 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5603 }
5604
5605 static void
5606 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5607 {
5608 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5609 bool old_streamout_enabled = so->streamout_enabled;
5610 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5611
5612 so->streamout_enabled = enable;
5613
5614 so->hw_enabled_mask = so->enabled_mask |
5615 (so->enabled_mask << 4) |
5616 (so->enabled_mask << 8) |
5617 (so->enabled_mask << 12);
5618
5619 if ((old_streamout_enabled != so->streamout_enabled) ||
5620 (old_hw_enabled_mask != so->hw_enabled_mask))
5621 radv_emit_streamout_enable(cmd_buffer);
5622 }
5623
5624 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5625 {
5626 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5627 unsigned reg_strmout_cntl;
5628
5629 /* The register is at different places on different ASICs. */
5630 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
5631 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5632 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5633 } else {
5634 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5635 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5636 }
5637
5638 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5639 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5640
5641 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5642 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5643 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
5644 radeon_emit(cs, 0);
5645 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5646 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5647 radeon_emit(cs, 4); /* poll interval */
5648 }
5649
5650 static void
5651 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer,
5652 uint32_t firstCounterBuffer,
5653 uint32_t counterBufferCount,
5654 const VkBuffer *pCounterBuffers,
5655 const VkDeviceSize *pCounterBufferOffsets)
5656
5657 {
5658 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5659 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5660 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5661 uint32_t i;
5662
5663 radv_flush_vgt_streamout(cmd_buffer);
5664
5665 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5666 for_each_bit(i, so->enabled_mask) {
5667 int32_t counter_buffer_idx = i - firstCounterBuffer;
5668 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5669 counter_buffer_idx = -1;
5670
5671 /* AMD GCN binds streamout buffers as shader resources.
5672 * VGT only counts primitives and tells the shader through
5673 * SGPRs what to do.
5674 */
5675 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5676 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5677 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5678
5679 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5680
5681 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5682 /* The array of counter buffers is optional. */
5683 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5684 uint64_t va = radv_buffer_get_va(buffer->bo);
5685
5686 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5687
5688 /* Append */
5689 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5690 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5691 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5692 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5693 radeon_emit(cs, 0); /* unused */
5694 radeon_emit(cs, 0); /* unused */
5695 radeon_emit(cs, va); /* src address lo */
5696 radeon_emit(cs, va >> 32); /* src address hi */
5697
5698 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5699 } else {
5700 /* Start from the beginning. */
5701 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5702 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5703 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5704 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5705 radeon_emit(cs, 0); /* unused */
5706 radeon_emit(cs, 0); /* unused */
5707 radeon_emit(cs, 0); /* unused */
5708 radeon_emit(cs, 0); /* unused */
5709 }
5710 }
5711
5712 radv_set_streamout_enable(cmd_buffer, true);
5713 }
5714
5715 void radv_CmdBeginTransformFeedbackEXT(
5716 VkCommandBuffer commandBuffer,
5717 uint32_t firstCounterBuffer,
5718 uint32_t counterBufferCount,
5719 const VkBuffer* pCounterBuffers,
5720 const VkDeviceSize* pCounterBufferOffsets)
5721 {
5722 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5723
5724 radv_emit_streamout_begin(cmd_buffer,
5725 firstCounterBuffer, counterBufferCount,
5726 pCounterBuffers, pCounterBufferOffsets);
5727 }
5728
5729 static void
5730 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer,
5731 uint32_t firstCounterBuffer,
5732 uint32_t counterBufferCount,
5733 const VkBuffer *pCounterBuffers,
5734 const VkDeviceSize *pCounterBufferOffsets)
5735 {
5736 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5737 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5738 uint32_t i;
5739
5740 radv_flush_vgt_streamout(cmd_buffer);
5741
5742 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5743 for_each_bit(i, so->enabled_mask) {
5744 int32_t counter_buffer_idx = i - firstCounterBuffer;
5745 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5746 counter_buffer_idx = -1;
5747
5748 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5749 /* The array of counters buffer is optional. */
5750 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5751 uint64_t va = radv_buffer_get_va(buffer->bo);
5752
5753 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5754
5755 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5756 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5757 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5758 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5759 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5760 radeon_emit(cs, va); /* dst address lo */
5761 radeon_emit(cs, va >> 32); /* dst address hi */
5762 radeon_emit(cs, 0); /* unused */
5763 radeon_emit(cs, 0); /* unused */
5764
5765 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5766 }
5767
5768 /* Deactivate transform feedback by zeroing the buffer size.
5769 * The counters (primitives generated, primitives emitted) may
5770 * be enabled even if there is not buffer bound. This ensures
5771 * that the primitives-emitted query won't increment.
5772 */
5773 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5774
5775 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5776 }
5777
5778 radv_set_streamout_enable(cmd_buffer, false);
5779 }
5780
5781 void radv_CmdEndTransformFeedbackEXT(
5782 VkCommandBuffer commandBuffer,
5783 uint32_t firstCounterBuffer,
5784 uint32_t counterBufferCount,
5785 const VkBuffer* pCounterBuffers,
5786 const VkDeviceSize* pCounterBufferOffsets)
5787 {
5788 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5789
5790 radv_emit_streamout_end(cmd_buffer,
5791 firstCounterBuffer, counterBufferCount,
5792 pCounterBuffers, pCounterBufferOffsets);
5793 }
5794
5795 void radv_CmdDrawIndirectByteCountEXT(
5796 VkCommandBuffer commandBuffer,
5797 uint32_t instanceCount,
5798 uint32_t firstInstance,
5799 VkBuffer _counterBuffer,
5800 VkDeviceSize counterBufferOffset,
5801 uint32_t counterOffset,
5802 uint32_t vertexStride)
5803 {
5804 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5805 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5806 struct radv_draw_info info = {};
5807
5808 info.instance_count = instanceCount;
5809 info.first_instance = firstInstance;
5810 info.strmout_buffer = counterBuffer;
5811 info.strmout_buffer_offset = counterBufferOffset;
5812 info.stride = vertexStride;
5813
5814 radv_draw(cmd_buffer, &info);
5815 }
5816
5817 /* VK_AMD_buffer_marker */
5818 void radv_CmdWriteBufferMarkerAMD(
5819 VkCommandBuffer commandBuffer,
5820 VkPipelineStageFlagBits pipelineStage,
5821 VkBuffer dstBuffer,
5822 VkDeviceSize dstOffset,
5823 uint32_t marker)
5824 {
5825 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5826 RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
5827 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5828 uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
5829
5830 si_emit_cache_flush(cmd_buffer);
5831
5832 if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
5833 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
5834 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
5835 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
5836 COPY_DATA_WR_CONFIRM);
5837 radeon_emit(cs, marker);
5838 radeon_emit(cs, 0);
5839 radeon_emit(cs, va);
5840 radeon_emit(cs, va >> 32);
5841 } else {
5842 si_cs_emit_write_event_eop(cs,
5843 cmd_buffer->device->physical_device->rad_info.chip_class,
5844 radv_cmd_buffer_uses_mec(cmd_buffer),
5845 V_028A90_BOTTOM_OF_PIPE_TS, 0,
5846 EOP_DST_SEL_MEM,
5847 EOP_DATA_SEL_VALUE_32BIT,
5848 va, marker,
5849 cmd_buffer->gfx9_eop_bug_va);
5850 }
5851 }