2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
40 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
41 struct radv_image
*image
,
42 VkImageLayout src_layout
,
43 VkImageLayout dst_layout
,
46 const VkImageSubresourceRange
*range
,
47 VkImageAspectFlags pending_clears
);
49 const struct radv_dynamic_state default_dynamic_state
= {
62 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
67 .stencil_compare_mask
= {
71 .stencil_write_mask
= {
75 .stencil_reference
= {
82 radv_dynamic_state_copy(struct radv_dynamic_state
*dest
,
83 const struct radv_dynamic_state
*src
,
86 if (copy_mask
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
87 dest
->viewport
.count
= src
->viewport
.count
;
88 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
92 if (copy_mask
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
93 dest
->scissor
.count
= src
->scissor
.count
;
94 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
98 if (copy_mask
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
))
99 dest
->line_width
= src
->line_width
;
101 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
))
102 dest
->depth_bias
= src
->depth_bias
;
104 if (copy_mask
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
105 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
107 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
))
108 dest
->depth_bounds
= src
->depth_bounds
;
110 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
))
111 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
113 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
))
114 dest
->stencil_write_mask
= src
->stencil_write_mask
;
116 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
))
117 dest
->stencil_reference
= src
->stencil_reference
;
120 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
122 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
123 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
126 enum ring_type
radv_queue_family_to_ring(int f
) {
128 case RADV_QUEUE_GENERAL
:
130 case RADV_QUEUE_COMPUTE
:
132 case RADV_QUEUE_TRANSFER
:
135 unreachable("Unknown queue family");
139 static VkResult
radv_create_cmd_buffer(
140 struct radv_device
* device
,
141 struct radv_cmd_pool
* pool
,
142 VkCommandBufferLevel level
,
143 VkCommandBuffer
* pCommandBuffer
)
145 struct radv_cmd_buffer
*cmd_buffer
;
147 cmd_buffer
= vk_alloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
148 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
149 if (cmd_buffer
== NULL
)
150 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
152 memset(cmd_buffer
, 0, sizeof(*cmd_buffer
));
153 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
154 cmd_buffer
->device
= device
;
155 cmd_buffer
->pool
= pool
;
156 cmd_buffer
->level
= level
;
159 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
160 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
163 /* Init the pool_link so we can safefly call list_del when we destroy
166 list_inithead(&cmd_buffer
->pool_link
);
167 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
170 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
172 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
173 if (!cmd_buffer
->cs
) {
174 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
175 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
178 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
180 cmd_buffer
->upload
.offset
= 0;
181 cmd_buffer
->upload
.size
= 0;
182 list_inithead(&cmd_buffer
->upload
.list
);
188 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
190 list_del(&cmd_buffer
->pool_link
);
192 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
193 &cmd_buffer
->upload
.list
, list
) {
194 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
199 if (cmd_buffer
->upload
.upload_bo
)
200 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
201 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
202 free(cmd_buffer
->push_descriptors
.set
.mapped_ptr
);
203 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
207 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
210 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
212 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
213 &cmd_buffer
->upload
.list
, list
) {
214 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
219 cmd_buffer
->push_constant_stages
= 0;
220 cmd_buffer
->scratch_size_needed
= 0;
221 cmd_buffer
->compute_scratch_size_needed
= 0;
222 cmd_buffer
->esgs_ring_size_needed
= 0;
223 cmd_buffer
->gsvs_ring_size_needed
= 0;
224 cmd_buffer
->tess_rings_needed
= false;
225 cmd_buffer
->sample_positions_needed
= false;
227 if (cmd_buffer
->upload
.upload_bo
)
228 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
,
229 cmd_buffer
->upload
.upload_bo
, 8);
230 cmd_buffer
->upload
.offset
= 0;
232 cmd_buffer
->record_result
= VK_SUCCESS
;
234 cmd_buffer
->ring_offsets_idx
= -1;
236 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
238 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 0,
239 &cmd_buffer
->gfx9_fence_offset
,
241 cmd_buffer
->gfx9_fence_bo
= cmd_buffer
->upload
.upload_bo
;
244 return cmd_buffer
->record_result
;
248 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
252 struct radeon_winsys_bo
*bo
;
253 struct radv_cmd_buffer_upload
*upload
;
254 struct radv_device
*device
= cmd_buffer
->device
;
256 new_size
= MAX2(min_needed
, 16 * 1024);
257 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
259 bo
= device
->ws
->buffer_create(device
->ws
,
262 RADEON_FLAG_CPU_ACCESS
);
265 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
269 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, bo
, 8);
270 if (cmd_buffer
->upload
.upload_bo
) {
271 upload
= malloc(sizeof(*upload
));
274 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
275 device
->ws
->buffer_destroy(bo
);
279 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
280 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
283 cmd_buffer
->upload
.upload_bo
= bo
;
284 cmd_buffer
->upload
.size
= new_size
;
285 cmd_buffer
->upload
.offset
= 0;
286 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
288 if (!cmd_buffer
->upload
.map
) {
289 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
297 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
300 unsigned *out_offset
,
303 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
304 if (offset
+ size
> cmd_buffer
->upload
.size
) {
305 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
310 *out_offset
= offset
;
311 *ptr
= cmd_buffer
->upload
.map
+ offset
;
313 cmd_buffer
->upload
.offset
= offset
+ size
;
318 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
319 unsigned size
, unsigned alignment
,
320 const void *data
, unsigned *out_offset
)
324 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
325 out_offset
, (void **)&ptr
))
329 memcpy(ptr
, data
, size
);
335 radv_emit_write_data_packet(struct radeon_winsys_cs
*cs
, uint64_t va
,
336 unsigned count
, const uint32_t *data
)
338 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
339 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
340 S_370_WR_CONFIRM(1) |
341 S_370_ENGINE_SEL(V_370_ME
));
343 radeon_emit(cs
, va
>> 32);
344 radeon_emit_array(cs
, data
, count
);
347 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
349 struct radv_device
*device
= cmd_buffer
->device
;
350 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
353 if (!device
->trace_bo
)
356 va
= device
->ws
->buffer_get_va(device
->trace_bo
);
357 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
360 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 7);
362 ++cmd_buffer
->state
.trace_id
;
363 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
364 radv_emit_write_data_packet(cs
, va
, 1, &cmd_buffer
->state
.trace_id
);
365 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
366 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
370 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
)
372 if (cmd_buffer
->device
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
373 enum radv_cmd_flush_bits flags
;
375 /* Force wait for graphics/compute engines to be idle. */
376 flags
= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
377 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
379 si_cs_emit_cache_flush(cmd_buffer
->cs
, false,
380 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
382 radv_cmd_buffer_uses_mec(cmd_buffer
),
386 radv_cmd_buffer_trace_emit(cmd_buffer
);
390 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
391 struct radv_pipeline
*pipeline
, enum ring_type ring
)
393 struct radv_device
*device
= cmd_buffer
->device
;
394 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
398 if (!device
->trace_bo
)
401 va
= device
->ws
->buffer_get_va(device
->trace_bo
);
411 assert(!"invalid ring type");
414 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
417 data
[0] = (uintptr_t)pipeline
;
418 data
[1] = (uintptr_t)pipeline
>> 32;
420 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
421 radv_emit_write_data_packet(cs
, va
, 2, data
);
425 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
427 struct radv_device
*device
= cmd_buffer
->device
;
428 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
429 uint32_t data
[MAX_SETS
* 2] = {};
432 if (!device
->trace_bo
)
435 va
= device
->ws
->buffer_get_va(device
->trace_bo
) + 24;
437 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
438 cmd_buffer
->cs
, 4 + MAX_SETS
* 2);
440 for (int i
= 0; i
< MAX_SETS
; i
++) {
441 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
445 data
[i
* 2] = (uintptr_t)set
;
446 data
[i
* 2 + 1] = (uintptr_t)set
>> 32;
449 device
->ws
->cs_add_buffer(cs
, device
->trace_bo
, 8);
450 radv_emit_write_data_packet(cs
, va
, MAX_SETS
* 2, data
);
454 radv_emit_graphics_blend_state(struct radv_cmd_buffer
*cmd_buffer
,
455 struct radv_pipeline
*pipeline
)
457 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028780_CB_BLEND0_CONTROL
, 8);
458 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.cb_blend_control
,
460 radeon_set_context_reg(cmd_buffer
->cs
, R_028808_CB_COLOR_CONTROL
, pipeline
->graphics
.blend
.cb_color_control
);
461 radeon_set_context_reg(cmd_buffer
->cs
, R_028B70_DB_ALPHA_TO_MASK
, pipeline
->graphics
.blend
.db_alpha_to_mask
);
463 if (cmd_buffer
->device
->physical_device
->has_rbplus
) {
465 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
466 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.sx_mrt_blend_opt
, 8);
468 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
469 radeon_emit(cmd_buffer
->cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
470 radeon_emit(cmd_buffer
->cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
471 radeon_emit(cmd_buffer
->cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
476 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer
*cmd_buffer
,
477 struct radv_pipeline
*pipeline
)
479 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
480 radeon_set_context_reg(cmd_buffer
->cs
, R_028800_DB_DEPTH_CONTROL
, ds
->db_depth_control
);
481 radeon_set_context_reg(cmd_buffer
->cs
, R_02842C_DB_STENCIL_CONTROL
, ds
->db_stencil_control
);
483 radeon_set_context_reg(cmd_buffer
->cs
, R_028000_DB_RENDER_CONTROL
, ds
->db_render_control
);
484 radeon_set_context_reg(cmd_buffer
->cs
, R_028010_DB_RENDER_OVERRIDE2
, ds
->db_render_override2
);
487 /* 12.4 fixed-point */
488 static unsigned radv_pack_float_12p4(float x
)
491 x
>= 4096 ? 0xffff : x
* 16;
494 struct ac_userdata_info
*
495 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
496 gl_shader_stage stage
,
499 return &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.shader_data
[idx
];
503 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
504 struct radv_pipeline
*pipeline
,
505 gl_shader_stage stage
,
506 int idx
, uint64_t va
)
508 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
509 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
510 if (loc
->sgpr_idx
== -1)
512 assert(loc
->num_sgprs
== 2);
513 assert(!loc
->indirect
);
514 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 2);
515 radeon_emit(cmd_buffer
->cs
, va
);
516 radeon_emit(cmd_buffer
->cs
, va
>> 32);
520 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
521 struct radv_pipeline
*pipeline
)
523 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
524 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
525 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
527 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
528 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[0]);
529 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[1]);
531 radeon_set_context_reg(cmd_buffer
->cs
, CM_R_028804_DB_EQAA
, ms
->db_eqaa
);
532 radeon_set_context_reg(cmd_buffer
->cs
, EG_R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
534 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
537 radeon_set_context_reg_seq(cmd_buffer
->cs
, CM_R_028BDC_PA_SC_LINE_CNTL
, 2);
538 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
539 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
541 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
543 /* GFX9: Flush DFSM when the AA mode changes. */
544 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
545 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
546 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
548 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
) {
550 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_FRAGMENT
, AC_UD_PS_SAMPLE_POS_OFFSET
);
551 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
552 if (loc
->sgpr_idx
== -1)
554 assert(loc
->num_sgprs
== 1);
555 assert(!loc
->indirect
);
556 switch (num_samples
) {
574 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, offset
);
575 cmd_buffer
->sample_positions_needed
= true;
580 radv_emit_graphics_raster_state(struct radv_cmd_buffer
*cmd_buffer
,
581 struct radv_pipeline
*pipeline
)
583 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
585 radeon_set_context_reg(cmd_buffer
->cs
, R_028810_PA_CL_CLIP_CNTL
,
586 raster
->pa_cl_clip_cntl
);
588 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
589 raster
->spi_interp_control
);
591 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028A00_PA_SU_POINT_SIZE
, 2);
592 unsigned tmp
= (unsigned)(1.0 * 8.0);
593 radeon_emit(cmd_buffer
->cs
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
594 radeon_emit(cmd_buffer
->cs
, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
595 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
597 radeon_set_context_reg(cmd_buffer
->cs
, R_028BE4_PA_SU_VTX_CNTL
,
598 raster
->pa_su_vtx_cntl
);
600 radeon_set_context_reg(cmd_buffer
->cs
, R_028814_PA_SU_SC_MODE_CNTL
,
601 raster
->pa_su_sc_mode_cntl
);
605 radv_emit_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
608 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
609 si_cp_dma_prefetch(cmd_buffer
, va
, size
);
613 radv_emit_hw_vs(struct radv_cmd_buffer
*cmd_buffer
,
614 struct radv_pipeline
*pipeline
,
615 struct radv_shader_variant
*shader
,
616 struct ac_vs_output_info
*outinfo
)
618 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
619 uint64_t va
= ws
->buffer_get_va(shader
->bo
) + shader
->bo_offset
;
620 unsigned export_count
;
622 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
623 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
625 export_count
= MAX2(1, outinfo
->param_exports
);
626 radeon_set_context_reg(cmd_buffer
->cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
627 S_0286C4_VS_EXPORT_COUNT(export_count
- 1));
629 radeon_set_context_reg(cmd_buffer
->cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
630 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
631 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
632 V_02870C_SPI_SHADER_4COMP
:
633 V_02870C_SPI_SHADER_NONE
) |
634 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
635 V_02870C_SPI_SHADER_4COMP
:
636 V_02870C_SPI_SHADER_NONE
) |
637 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
638 V_02870C_SPI_SHADER_4COMP
:
639 V_02870C_SPI_SHADER_NONE
));
642 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
643 radeon_emit(cmd_buffer
->cs
, va
>> 8);
644 radeon_emit(cmd_buffer
->cs
, va
>> 40);
645 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
646 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
648 radeon_set_context_reg(cmd_buffer
->cs
, R_028818_PA_CL_VTE_CNTL
,
649 S_028818_VTX_W0_FMT(1) |
650 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
651 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
652 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
655 radeon_set_context_reg(cmd_buffer
->cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
656 pipeline
->graphics
.pa_cl_vs_out_cntl
);
658 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= VI
)
659 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB4_VGT_REUSE_OFF
,
660 S_028AB4_REUSE_OFF(outinfo
->writes_viewport_index
));
664 radv_emit_hw_es(struct radv_cmd_buffer
*cmd_buffer
,
665 struct radv_shader_variant
*shader
,
666 struct ac_es_output_info
*outinfo
)
668 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
669 uint64_t va
= ws
->buffer_get_va(shader
->bo
) + shader
->bo_offset
;
671 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
672 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
674 radeon_set_context_reg(cmd_buffer
->cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
675 outinfo
->esgs_itemsize
/ 4);
676 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
677 radeon_emit(cmd_buffer
->cs
, va
>> 8);
678 radeon_emit(cmd_buffer
->cs
, va
>> 40);
679 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
680 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
684 radv_emit_hw_ls(struct radv_cmd_buffer
*cmd_buffer
,
685 struct radv_shader_variant
*shader
)
687 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
688 uint64_t va
= ws
->buffer_get_va(shader
->bo
) + shader
->bo_offset
;
689 uint32_t rsrc2
= shader
->rsrc2
;
691 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
692 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
694 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
695 radeon_emit(cmd_buffer
->cs
, va
>> 8);
696 radeon_emit(cmd_buffer
->cs
, va
>> 40);
698 rsrc2
|= S_00B52C_LDS_SIZE(cmd_buffer
->state
.pipeline
->graphics
.tess
.lds_size
);
699 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== CIK
&&
700 cmd_buffer
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
701 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
703 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
704 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
705 radeon_emit(cmd_buffer
->cs
, rsrc2
);
709 radv_emit_hw_hs(struct radv_cmd_buffer
*cmd_buffer
,
710 struct radv_shader_variant
*shader
)
712 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
713 uint64_t va
= ws
->buffer_get_va(shader
->bo
) + shader
->bo_offset
;
715 ws
->cs_add_buffer(cmd_buffer
->cs
, shader
->bo
, 8);
716 radv_emit_prefetch(cmd_buffer
, va
, shader
->code_size
);
718 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
719 radeon_emit(cmd_buffer
->cs
, va
>> 8);
720 radeon_emit(cmd_buffer
->cs
, va
>> 40);
721 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
722 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
726 radv_emit_vertex_shader(struct radv_cmd_buffer
*cmd_buffer
,
727 struct radv_pipeline
*pipeline
)
729 struct radv_shader_variant
*vs
;
731 assert (pipeline
->shaders
[MESA_SHADER_VERTEX
]);
733 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
735 if (vs
->info
.vs
.as_ls
)
736 radv_emit_hw_ls(cmd_buffer
, vs
);
737 else if (vs
->info
.vs
.as_es
)
738 radv_emit_hw_es(cmd_buffer
, vs
, &vs
->info
.vs
.es_info
);
740 radv_emit_hw_vs(cmd_buffer
, pipeline
, vs
, &vs
->info
.vs
.outinfo
);
742 radeon_set_context_reg(cmd_buffer
->cs
, R_028A84_VGT_PRIMITIVEID_EN
, pipeline
->graphics
.vgt_primitiveid_en
);
747 radv_emit_tess_shaders(struct radv_cmd_buffer
*cmd_buffer
,
748 struct radv_pipeline
*pipeline
)
750 if (!radv_pipeline_has_tess(pipeline
))
753 struct radv_shader_variant
*tes
, *tcs
;
755 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
756 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
758 if (tes
->info
.tes
.as_es
)
759 radv_emit_hw_es(cmd_buffer
, tes
, &tes
->info
.tes
.es_info
);
761 radv_emit_hw_vs(cmd_buffer
, pipeline
, tes
, &tes
->info
.tes
.outinfo
);
763 radv_emit_hw_hs(cmd_buffer
, tcs
);
765 radeon_set_context_reg(cmd_buffer
->cs
, R_028B6C_VGT_TF_PARAM
,
766 pipeline
->graphics
.tess
.tf_param
);
768 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
769 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
770 pipeline
->graphics
.tess
.ls_hs_config
);
772 radeon_set_context_reg(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
,
773 pipeline
->graphics
.tess
.ls_hs_config
);
775 struct ac_userdata_info
*loc
;
777 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_CTRL
, AC_UD_TCS_OFFCHIP_LAYOUT
);
778 if (loc
->sgpr_idx
!= -1) {
779 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
780 assert(loc
->num_sgprs
== 4);
781 assert(!loc
->indirect
);
782 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 4);
783 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.offchip_layout
);
784 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_offsets
);
785 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_layout
|
786 pipeline
->graphics
.tess
.num_tcs_input_cp
<< 26);
787 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_in_layout
);
790 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_EVAL
, AC_UD_TES_OFFCHIP_LAYOUT
);
791 if (loc
->sgpr_idx
!= -1) {
792 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
793 assert(loc
->num_sgprs
== 1);
794 assert(!loc
->indirect
);
796 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
797 pipeline
->graphics
.tess
.offchip_layout
);
800 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
, AC_UD_VS_LS_TCS_IN_LAYOUT
);
801 if (loc
->sgpr_idx
!= -1) {
802 uint32_t base_reg
= radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
803 assert(loc
->num_sgprs
== 1);
804 assert(!loc
->indirect
);
806 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
807 pipeline
->graphics
.tess
.tcs_in_layout
);
812 radv_emit_geometry_shader(struct radv_cmd_buffer
*cmd_buffer
,
813 struct radv_pipeline
*pipeline
)
815 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
816 struct radv_shader_variant
*gs
;
819 radeon_set_context_reg(cmd_buffer
->cs
, R_028A40_VGT_GS_MODE
, pipeline
->graphics
.vgt_gs_mode
);
821 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
825 uint32_t gsvs_itemsize
= gs
->info
.gs
.max_gsvs_emit_size
>> 2;
827 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
828 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
829 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
830 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
832 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
);
834 radeon_set_context_reg(cmd_buffer
->cs
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs
->info
.gs
.vertices_out
);
836 uint32_t gs_vert_itemsize
= gs
->info
.gs
.gsvs_vertex_size
;
837 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
838 radeon_emit(cmd_buffer
->cs
, gs_vert_itemsize
>> 2);
839 radeon_emit(cmd_buffer
->cs
, 0);
840 radeon_emit(cmd_buffer
->cs
, 0);
841 radeon_emit(cmd_buffer
->cs
, 0);
843 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
844 radeon_set_context_reg(cmd_buffer
->cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
845 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
846 S_028B90_ENABLE(gs_num_invocations
> 0));
848 va
= ws
->buffer_get_va(gs
->bo
) + gs
->bo_offset
;
849 ws
->cs_add_buffer(cmd_buffer
->cs
, gs
->bo
, 8);
850 radv_emit_prefetch(cmd_buffer
, va
, gs
->code_size
);
852 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
853 radeon_emit(cmd_buffer
->cs
, va
>> 8);
854 radeon_emit(cmd_buffer
->cs
, va
>> 40);
855 radeon_emit(cmd_buffer
->cs
, gs
->rsrc1
);
856 radeon_emit(cmd_buffer
->cs
, gs
->rsrc2
);
858 radv_emit_hw_vs(cmd_buffer
, pipeline
, pipeline
->gs_copy_shader
, &pipeline
->gs_copy_shader
->info
.vs
.outinfo
);
860 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
861 AC_UD_GS_VS_RING_STRIDE_ENTRIES
);
862 if (loc
->sgpr_idx
!= -1) {
863 uint32_t stride
= gs
->info
.gs
.max_gsvs_emit_size
;
864 uint32_t num_entries
= 64;
865 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
868 num_entries
*= stride
;
870 stride
= S_008F04_STRIDE(stride
);
871 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
+ loc
->sgpr_idx
* 4, 2);
872 radeon_emit(cmd_buffer
->cs
, stride
);
873 radeon_emit(cmd_buffer
->cs
, num_entries
);
878 radv_emit_fragment_shader(struct radv_cmd_buffer
*cmd_buffer
,
879 struct radv_pipeline
*pipeline
)
881 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
882 struct radv_shader_variant
*ps
;
884 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
885 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
886 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
888 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
889 va
= ws
->buffer_get_va(ps
->bo
) + ps
->bo_offset
;
890 ws
->cs_add_buffer(cmd_buffer
->cs
, ps
->bo
, 8);
891 radv_emit_prefetch(cmd_buffer
, va
, ps
->code_size
);
893 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
894 radeon_emit(cmd_buffer
->cs
, va
>> 8);
895 radeon_emit(cmd_buffer
->cs
, va
>> 40);
896 radeon_emit(cmd_buffer
->cs
, ps
->rsrc1
);
897 radeon_emit(cmd_buffer
->cs
, ps
->rsrc2
);
899 radeon_set_context_reg(cmd_buffer
->cs
, R_02880C_DB_SHADER_CONTROL
,
900 pipeline
->graphics
.db_shader_control
);
902 radeon_set_context_reg(cmd_buffer
->cs
, R_0286CC_SPI_PS_INPUT_ENA
,
903 ps
->config
.spi_ps_input_ena
);
905 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
906 ps
->config
.spi_ps_input_addr
);
908 if (ps
->info
.info
.ps
.force_persample
)
909 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
911 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D8_SPI_PS_IN_CONTROL
,
912 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
914 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
916 radeon_set_context_reg(cmd_buffer
->cs
, R_028710_SPI_SHADER_Z_FORMAT
,
917 pipeline
->graphics
.shader_z_format
);
919 radeon_set_context_reg(cmd_buffer
->cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
921 radeon_set_context_reg(cmd_buffer
->cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
922 radeon_set_context_reg(cmd_buffer
->cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
924 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
926 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
927 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
930 if (pipeline
->graphics
.ps_input_cntl_num
) {
931 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028644_SPI_PS_INPUT_CNTL_0
, pipeline
->graphics
.ps_input_cntl_num
);
932 for (unsigned i
= 0; i
< pipeline
->graphics
.ps_input_cntl_num
; i
++) {
933 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.ps_input_cntl
[i
]);
938 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer
*cmd_buffer
,
939 struct radv_pipeline
*pipeline
)
941 uint32_t vtx_reuse_depth
= 30;
942 if (cmd_buffer
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
)
945 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
946 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
)
947 vtx_reuse_depth
= 14;
949 radeon_set_context_reg(cmd_buffer
->cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
954 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
956 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
958 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
961 radv_emit_graphics_depth_stencil_state(cmd_buffer
, pipeline
);
962 radv_emit_graphics_blend_state(cmd_buffer
, pipeline
);
963 radv_emit_graphics_raster_state(cmd_buffer
, pipeline
);
964 radv_update_multisample_state(cmd_buffer
, pipeline
);
965 radv_emit_vertex_shader(cmd_buffer
, pipeline
);
966 radv_emit_tess_shaders(cmd_buffer
, pipeline
);
967 radv_emit_geometry_shader(cmd_buffer
, pipeline
);
968 radv_emit_fragment_shader(cmd_buffer
, pipeline
);
969 polaris_set_vgt_vertex_reuse(cmd_buffer
, pipeline
);
971 cmd_buffer
->scratch_size_needed
=
972 MAX2(cmd_buffer
->scratch_size_needed
,
973 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
975 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E8_SPI_TMPRING_SIZE
,
976 S_0286E8_WAVES(pipeline
->max_waves
) |
977 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
979 if (!cmd_buffer
->state
.emitted_pipeline
||
980 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
981 pipeline
->graphics
.can_use_guardband
)
982 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
984 radeon_set_context_reg(cmd_buffer
->cs
, R_028B54_VGT_SHADER_STAGES_EN
, pipeline
->graphics
.vgt_shader_stages_en
);
986 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
987 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, pipeline
->graphics
.prim
);
989 radeon_set_config_reg(cmd_buffer
->cs
, R_008958_VGT_PRIMITIVE_TYPE
, pipeline
->graphics
.prim
);
991 radeon_set_context_reg(cmd_buffer
->cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, pipeline
->graphics
.gs_out
);
993 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
995 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
999 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1001 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1002 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1006 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1008 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1009 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1010 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1011 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1012 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1013 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
,
1014 cmd_buffer
->state
.pipeline
->graphics
.ms
.pa_sc_mode_cntl_0
| S_028A48_VPORT_SCISSOR_ENABLE(count
? 1 : 0));
1018 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1020 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1022 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1023 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1027 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1029 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1031 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1032 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1036 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1038 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1040 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1041 R_028430_DB_STENCILREFMASK
, 2);
1042 radeon_emit(cmd_buffer
->cs
,
1043 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1044 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1045 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1046 S_028430_STENCILOPVAL(1));
1047 radeon_emit(cmd_buffer
->cs
,
1048 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1049 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1050 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1051 S_028434_STENCILOPVAL_BF(1));
1055 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1057 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1059 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1060 fui(d
->depth_bounds
.min
));
1061 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1062 fui(d
->depth_bounds
.max
));
1066 radv_emit_depth_biais(struct radv_cmd_buffer
*cmd_buffer
)
1068 struct radv_raster_state
*raster
= &cmd_buffer
->state
.pipeline
->graphics
.raster
;
1069 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1070 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1071 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1073 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster
->pa_su_sc_mode_cntl
)) {
1074 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1075 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1076 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1077 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1078 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1079 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1080 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1085 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1087 struct radv_color_buffer_info
*cb
)
1089 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
1091 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1092 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1093 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1094 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
>> 32);
1095 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1096 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1097 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
1098 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1099 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1100 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1101 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
>> 32);
1102 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1103 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
>> 32);
1105 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1106 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1107 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
>> 32);
1109 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1112 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1113 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1114 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1115 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1116 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1117 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_info
);
1118 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1119 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1120 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1121 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1122 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1123 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1125 if (is_vi
) { /* DCC BASE */
1126 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1132 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1133 struct radv_ds_buffer_info
*ds
,
1134 struct radv_image
*image
,
1135 VkImageLayout layout
)
1137 uint32_t db_z_info
= ds
->db_z_info
;
1138 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1140 if (!radv_layout_has_htile(image
, layout
,
1141 radv_image_queue_family_mask(image
,
1142 cmd_buffer
->queue_family_index
,
1143 cmd_buffer
->queue_family_index
))) {
1144 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1145 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1148 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1149 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1152 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1153 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1154 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1155 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1156 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1158 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1159 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1160 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1161 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1162 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32); /* DB_Z_READ_BASE_HI */
1163 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1164 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
1165 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1166 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
>> 32); /* DB_Z_WRITE_BASE_HI */
1167 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1168 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
1170 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1171 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1172 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1174 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1176 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1177 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1178 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1179 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1180 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1181 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1182 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1183 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1184 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1185 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1189 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1190 ds
->pa_su_poly_offset_db_fmt_cntl
);
1194 radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1195 struct radv_image
*image
,
1196 VkClearDepthStencilValue ds_clear_value
,
1197 VkImageAspectFlags aspects
)
1199 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1200 va
+= image
->offset
+ image
->clear_value_offset
;
1201 unsigned reg_offset
= 0, reg_count
= 0;
1203 if (!image
->surface
.htile_size
|| !aspects
)
1206 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1212 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1215 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1217 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
1218 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1219 S_370_WR_CONFIRM(1) |
1220 S_370_ENGINE_SEL(V_370_PFP
));
1221 radeon_emit(cmd_buffer
->cs
, va
);
1222 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1223 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1224 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
);
1225 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1226 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
));
1228 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
, reg_count
);
1229 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1230 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
); /* R_028028_DB_STENCIL_CLEAR */
1231 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1232 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
)); /* R_02802C_DB_DEPTH_CLEAR */
1236 radv_load_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1237 struct radv_image
*image
)
1239 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1240 va
+= image
->offset
+ image
->clear_value_offset
;
1242 if (!image
->surface
.htile_size
)
1245 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1247 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1248 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1249 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1250 COPY_DATA_COUNT_SEL
);
1251 radeon_emit(cmd_buffer
->cs
, va
);
1252 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1253 radeon_emit(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
>> 2);
1254 radeon_emit(cmd_buffer
->cs
, 0);
1256 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1257 radeon_emit(cmd_buffer
->cs
, 0);
1261 *with DCC some colors don't require CMASK elimiation before being
1262 * used as a texture. This sets a predicate value to determine if the
1263 * cmask eliminate is required.
1266 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1267 struct radv_image
*image
,
1270 uint64_t pred_val
= value
;
1271 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1272 va
+= image
->offset
+ image
->dcc_pred_offset
;
1274 if (!image
->surface
.dcc_size
)
1277 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1279 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1280 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1281 S_370_WR_CONFIRM(1) |
1282 S_370_ENGINE_SEL(V_370_PFP
));
1283 radeon_emit(cmd_buffer
->cs
, va
);
1284 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1285 radeon_emit(cmd_buffer
->cs
, pred_val
);
1286 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1290 radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1291 struct radv_image
*image
,
1293 uint32_t color_values
[2])
1295 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1296 va
+= image
->offset
+ image
->clear_value_offset
;
1298 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1301 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1303 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1304 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1305 S_370_WR_CONFIRM(1) |
1306 S_370_ENGINE_SEL(V_370_PFP
));
1307 radeon_emit(cmd_buffer
->cs
, va
);
1308 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1309 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1310 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1312 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c, 2);
1313 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1314 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1318 radv_load_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1319 struct radv_image
*image
,
1322 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(image
->bo
);
1323 va
+= image
->offset
+ image
->clear_value_offset
;
1325 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1328 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c;
1329 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, image
->bo
, 8);
1331 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1332 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1333 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1334 COPY_DATA_COUNT_SEL
);
1335 radeon_emit(cmd_buffer
->cs
, va
);
1336 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1337 radeon_emit(cmd_buffer
->cs
, reg
>> 2);
1338 radeon_emit(cmd_buffer
->cs
, 0);
1340 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1341 radeon_emit(cmd_buffer
->cs
, 0);
1345 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1348 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1349 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1351 /* this may happen for inherited secondary recording */
1355 for (i
= 0; i
< 8; ++i
) {
1356 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1357 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1358 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1362 int idx
= subpass
->color_attachments
[i
].attachment
;
1363 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1365 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1367 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
1368 radv_emit_fb_color_state(cmd_buffer
, i
, &att
->cb
);
1370 radv_load_color_clear_regs(cmd_buffer
, att
->attachment
->image
, i
);
1373 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1374 int idx
= subpass
->depth_stencil_attachment
.attachment
;
1375 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1376 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1377 struct radv_image
*image
= att
->attachment
->image
;
1378 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1379 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1380 cmd_buffer
->queue_family_index
,
1381 cmd_buffer
->queue_family_index
);
1382 /* We currently don't support writing decompressed HTILE */
1383 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1384 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1386 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1388 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1389 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1390 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1392 radv_load_depth_clear_regs(cmd_buffer
, image
);
1394 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1395 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1397 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1399 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1400 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1402 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1403 S_028208_BR_X(framebuffer
->width
) |
1404 S_028208_BR_Y(framebuffer
->height
));
1406 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1407 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1408 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1412 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1414 uint32_t db_count_control
;
1416 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1417 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1418 db_count_control
= 0;
1420 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1423 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1424 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1425 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1426 S_028004_ZPASS_ENABLE(1) |
1427 S_028004_SLICE_EVEN_ENABLE(1) |
1428 S_028004_SLICE_ODD_ENABLE(1);
1430 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1431 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1435 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1439 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1441 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer
->state
.pipeline
->graphics
.raster
.pa_cl_clip_cntl
))
1444 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1445 radv_emit_viewport(cmd_buffer
);
1447 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1448 radv_emit_scissor(cmd_buffer
);
1450 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
1451 radv_emit_line_width(cmd_buffer
);
1453 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1454 radv_emit_blend_constants(cmd_buffer
);
1456 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1457 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1458 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
1459 radv_emit_stencil(cmd_buffer
);
1461 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
1462 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
))
1463 radv_emit_depth_bounds(cmd_buffer
);
1465 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
1466 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
))
1467 radv_emit_depth_biais(cmd_buffer
);
1469 cmd_buffer
->state
.dirty
= 0;
1473 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1474 struct radv_pipeline
*pipeline
,
1477 gl_shader_stage stage
)
1479 struct ac_userdata_info
*desc_set_loc
= &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.descriptor_sets
[idx
];
1480 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
1482 if (desc_set_loc
->sgpr_idx
== -1 || desc_set_loc
->indirect
)
1485 assert(!desc_set_loc
->indirect
);
1486 assert(desc_set_loc
->num_sgprs
== 2);
1487 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
1488 base_reg
+ desc_set_loc
->sgpr_idx
* 4, 2);
1489 radeon_emit(cmd_buffer
->cs
, va
);
1490 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1494 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1495 VkShaderStageFlags stages
,
1496 struct radv_descriptor_set
*set
,
1499 if (cmd_buffer
->state
.pipeline
) {
1500 radv_foreach_stage(stage
, stages
) {
1501 if (cmd_buffer
->state
.pipeline
->shaders
[stage
])
1502 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1508 if (cmd_buffer
->state
.compute_pipeline
&& (stages
& VK_SHADER_STAGE_COMPUTE_BIT
))
1509 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
1511 MESA_SHADER_COMPUTE
);
1515 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
1517 struct radv_descriptor_set
*set
= &cmd_buffer
->push_descriptors
.set
;
1520 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
1525 set
->va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1526 set
->va
+= bo_offset
;
1530 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
)
1532 uint32_t size
= MAX_SETS
* 2 * 4;
1536 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1537 256, &offset
, &ptr
))
1540 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1541 uint32_t *uptr
= ((uint32_t *)ptr
) + i
* 2;
1542 uint64_t set_va
= 0;
1543 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
1546 uptr
[0] = set_va
& 0xffffffff;
1547 uptr
[1] = set_va
>> 32;
1550 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1553 if (cmd_buffer
->state
.pipeline
) {
1554 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1555 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1556 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1558 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1559 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1560 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1562 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1563 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1564 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1566 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1567 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1568 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1570 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1571 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1572 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1575 if (cmd_buffer
->state
.compute_pipeline
)
1576 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1577 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1581 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1582 VkShaderStageFlags stages
)
1586 if (!cmd_buffer
->state
.descriptors_dirty
)
1589 if (cmd_buffer
->state
.push_descriptors_dirty
)
1590 radv_flush_push_descriptors(cmd_buffer
);
1592 if ((cmd_buffer
->state
.pipeline
&& cmd_buffer
->state
.pipeline
->need_indirect_descriptor_sets
) ||
1593 (cmd_buffer
->state
.compute_pipeline
&& cmd_buffer
->state
.compute_pipeline
->need_indirect_descriptor_sets
)) {
1594 radv_flush_indirect_descriptor_sets(cmd_buffer
);
1597 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1599 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1601 for (i
= 0; i
< MAX_SETS
; i
++) {
1602 if (!(cmd_buffer
->state
.descriptors_dirty
& (1u << i
)))
1604 struct radv_descriptor_set
*set
= cmd_buffer
->state
.descriptors
[i
];
1608 radv_emit_descriptor_set_userdata(cmd_buffer
, stages
, set
, i
);
1610 cmd_buffer
->state
.descriptors_dirty
= 0;
1611 cmd_buffer
->state
.push_descriptors_dirty
= false;
1613 radv_save_descriptors(cmd_buffer
);
1615 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1619 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1620 struct radv_pipeline
*pipeline
,
1621 VkShaderStageFlags stages
)
1623 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1628 stages
&= cmd_buffer
->push_constant_stages
;
1629 if (!stages
|| !layout
|| (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1632 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1633 16 * layout
->dynamic_offset_count
,
1634 256, &offset
, &ptr
))
1637 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1638 memcpy((char*)ptr
+ layout
->push_constant_size
, cmd_buffer
->dynamic_buffers
,
1639 16 * layout
->dynamic_offset_count
);
1641 va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1644 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1645 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1647 radv_foreach_stage(stage
, stages
) {
1648 if (pipeline
->shaders
[stage
]) {
1649 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1650 AC_UD_PUSH_CONSTANTS
, va
);
1654 cmd_buffer
->push_constant_stages
&= ~stages
;
1655 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1658 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer
*cmd_buffer
,
1661 int32_t primitive_reset_en
= indexed_draw
&& cmd_buffer
->state
.pipeline
->graphics
.prim_restart_enable
;
1663 if (primitive_reset_en
!= cmd_buffer
->state
.last_primitive_reset_en
) {
1664 cmd_buffer
->state
.last_primitive_reset_en
= primitive_reset_en
;
1665 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1666 radeon_set_uconfig_reg(cmd_buffer
->cs
, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
1667 primitive_reset_en
);
1669 radeon_set_context_reg(cmd_buffer
->cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
1670 primitive_reset_en
);
1674 if (primitive_reset_en
) {
1675 uint32_t primitive_reset_index
= cmd_buffer
->state
.index_type
? 0xffffffffu
: 0xffffu
;
1677 if (primitive_reset_index
!= cmd_buffer
->state
.last_primitive_reset_index
) {
1678 cmd_buffer
->state
.last_primitive_reset_index
= primitive_reset_index
;
1679 radeon_set_context_reg(cmd_buffer
->cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
1680 primitive_reset_index
);
1686 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
1688 struct radv_device
*device
= cmd_buffer
->device
;
1690 if ((cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
|| cmd_buffer
->state
.vb_dirty
) &&
1691 cmd_buffer
->state
.pipeline
->vertex_elements
.count
&&
1692 cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.has_vertex_buffers
) {
1693 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
1697 uint32_t count
= velems
->count
;
1700 /* allocate some descriptor state for vertex buffers */
1701 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
1702 &vb_offset
, &vb_ptr
))
1705 for (i
= 0; i
< count
; i
++) {
1706 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
1708 int vb
= velems
->binding
[i
];
1709 struct radv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1710 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
1712 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, buffer
->bo
, 8);
1713 va
= device
->ws
->buffer_get_va(buffer
->bo
);
1715 offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
+ velems
->offset
[i
];
1716 va
+= offset
+ buffer
->offset
;
1718 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
1719 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= CIK
&& stride
)
1720 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
1722 desc
[2] = buffer
->size
- offset
;
1723 desc
[3] = velems
->rsrc_word3
[i
];
1726 va
= device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1729 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1730 AC_UD_VS_VERTEX_BUFFERS
, va
);
1732 cmd_buffer
->state
.vb_dirty
= false;
1738 radv_cmd_buffer_flush_state(struct radv_cmd_buffer
*cmd_buffer
,
1739 bool indexed_draw
, bool instanced_draw
,
1741 uint32_t draw_vertex_count
)
1743 uint32_t ia_multi_vgt_param
;
1745 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1746 cmd_buffer
->cs
, 4096);
1748 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer
))
1751 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
1752 radv_emit_graphics_pipeline(cmd_buffer
);
1754 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_RENDER_TARGETS
)
1755 radv_emit_framebuffer_state(cmd_buffer
);
1757 ia_multi_vgt_param
= si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
, indirect_draw
, draw_vertex_count
);
1758 if (cmd_buffer
->state
.last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
1759 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1760 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_030960_IA_MULTI_VGT_PARAM
, 4, ia_multi_vgt_param
);
1761 else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
1762 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028AA8_IA_MULTI_VGT_PARAM
, 1, ia_multi_vgt_param
);
1764 radeon_set_context_reg(cmd_buffer
->cs
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
1765 cmd_buffer
->state
.last_ia_multi_vgt_param
= ia_multi_vgt_param
;
1768 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
1770 radv_emit_primitive_reset_state(cmd_buffer
, indexed_draw
);
1772 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
1773 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1774 VK_SHADER_STAGE_ALL_GRAPHICS
);
1776 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1778 si_emit_cache_flush(cmd_buffer
);
1781 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
1782 VkPipelineStageFlags src_stage_mask
)
1784 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
1785 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1786 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1787 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1788 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
1791 if (src_stage_mask
& (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
1792 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
1793 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
1794 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
1795 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
1796 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
1797 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
1798 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1799 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1800 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
1801 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1802 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1803 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
|
1804 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
1805 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
1806 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
)) {
1807 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
1811 static enum radv_cmd_flush_bits
1812 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1813 VkAccessFlags src_flags
)
1815 enum radv_cmd_flush_bits flush_bits
= 0;
1817 for_each_bit(b
, src_flags
) {
1818 switch ((VkAccessFlagBits
)(1 << b
)) {
1819 case VK_ACCESS_SHADER_WRITE_BIT
:
1820 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
1822 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1823 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1824 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1826 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1827 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1828 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1830 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1831 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1832 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1833 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1834 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
1835 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1844 static enum radv_cmd_flush_bits
1845 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1846 VkAccessFlags dst_flags
,
1847 struct radv_image
*image
)
1849 enum radv_cmd_flush_bits flush_bits
= 0;
1851 for_each_bit(b
, dst_flags
) {
1852 switch ((VkAccessFlagBits
)(1 << b
)) {
1853 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1854 case VK_ACCESS_INDEX_READ_BIT
:
1855 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1857 case VK_ACCESS_UNIFORM_READ_BIT
:
1858 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
1860 case VK_ACCESS_SHADER_READ_BIT
:
1861 case VK_ACCESS_TRANSFER_READ_BIT
:
1862 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1863 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
1864 RADV_CMD_FLAG_INV_GLOBAL_L2
;
1866 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
1867 /* TODO: change to image && when the image gets passed
1868 * through from the subpass. */
1869 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
1870 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1871 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1873 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
1874 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
1875 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1876 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1885 static void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
, const struct radv_subpass_barrier
*barrier
)
1887 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
);
1888 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
1889 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
1893 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
1894 VkAttachmentReference att
)
1896 unsigned idx
= att
.attachment
;
1897 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
1898 VkImageSubresourceRange range
;
1899 range
.aspectMask
= 0;
1900 range
.baseMipLevel
= view
->base_mip
;
1901 range
.levelCount
= 1;
1902 range
.baseArrayLayer
= view
->base_layer
;
1903 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
1905 radv_handle_image_transition(cmd_buffer
,
1907 cmd_buffer
->state
.attachments
[idx
].current_layout
,
1908 att
.layout
, 0, 0, &range
,
1909 cmd_buffer
->state
.attachments
[idx
].pending_clear_aspects
);
1911 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
1917 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1918 const struct radv_subpass
*subpass
, bool transitions
)
1921 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
1923 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1924 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1925 radv_handle_subpass_image_transition(cmd_buffer
,
1926 subpass
->color_attachments
[i
]);
1929 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
1930 radv_handle_subpass_image_transition(cmd_buffer
,
1931 subpass
->input_attachments
[i
]);
1934 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1935 radv_handle_subpass_image_transition(cmd_buffer
,
1936 subpass
->depth_stencil_attachment
);
1940 cmd_buffer
->state
.subpass
= subpass
;
1942 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_RENDER_TARGETS
;
1946 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
1947 struct radv_render_pass
*pass
,
1948 const VkRenderPassBeginInfo
*info
)
1950 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1952 if (pass
->attachment_count
== 0) {
1953 state
->attachments
= NULL
;
1957 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1958 pass
->attachment_count
*
1959 sizeof(state
->attachments
[0]),
1960 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1961 if (state
->attachments
== NULL
) {
1962 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1963 return cmd_buffer
->record_result
;
1966 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1967 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1968 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1969 VkImageAspectFlags clear_aspects
= 0;
1971 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
1972 /* color attachment */
1973 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1974 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1977 /* depthstencil attachment */
1978 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1979 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1980 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1981 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
1982 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
1983 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1985 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
1986 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1987 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1991 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1992 state
->attachments
[i
].cleared_views
= 0;
1993 if (clear_aspects
&& info
) {
1994 assert(info
->clearValueCount
> i
);
1995 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
1998 state
->attachments
[i
].current_layout
= att
->initial_layout
;
2004 VkResult
radv_AllocateCommandBuffers(
2006 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
2007 VkCommandBuffer
*pCommandBuffers
)
2009 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2010 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
2012 VkResult result
= VK_SUCCESS
;
2015 memset(pCommandBuffers
, 0,
2016 sizeof(*pCommandBuffers
)*pAllocateInfo
->commandBufferCount
);
2018 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
2020 if (!list_empty(&pool
->free_cmd_buffers
)) {
2021 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
2023 list_del(&cmd_buffer
->pool_link
);
2024 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
2026 result
= radv_reset_cmd_buffer(cmd_buffer
);
2027 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2028 cmd_buffer
->level
= pAllocateInfo
->level
;
2030 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
2032 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
2033 &pCommandBuffers
[i
]);
2035 if (result
!= VK_SUCCESS
)
2039 if (result
!= VK_SUCCESS
)
2040 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
2041 i
, pCommandBuffers
);
2046 void radv_FreeCommandBuffers(
2048 VkCommandPool commandPool
,
2049 uint32_t commandBufferCount
,
2050 const VkCommandBuffer
*pCommandBuffers
)
2052 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2053 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
2056 if (cmd_buffer
->pool
) {
2057 list_del(&cmd_buffer
->pool_link
);
2058 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
2060 radv_cmd_buffer_destroy(cmd_buffer
);
2066 VkResult
radv_ResetCommandBuffer(
2067 VkCommandBuffer commandBuffer
,
2068 VkCommandBufferResetFlags flags
)
2070 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2071 return radv_reset_cmd_buffer(cmd_buffer
);
2074 static void emit_gfx_buffer_state(struct radv_cmd_buffer
*cmd_buffer
)
2076 struct radv_device
*device
= cmd_buffer
->device
;
2077 if (device
->gfx_init
) {
2078 uint64_t va
= device
->ws
->buffer_get_va(device
->gfx_init
);
2079 device
->ws
->cs_add_buffer(cmd_buffer
->cs
, device
->gfx_init
, 8);
2080 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2081 radeon_emit(cmd_buffer
->cs
, va
);
2082 radeon_emit(cmd_buffer
->cs
, va
>> 32);
2083 radeon_emit(cmd_buffer
->cs
, device
->gfx_init_size_dw
& 0xffff);
2085 si_init_config(cmd_buffer
);
2088 VkResult
radv_BeginCommandBuffer(
2089 VkCommandBuffer commandBuffer
,
2090 const VkCommandBufferBeginInfo
*pBeginInfo
)
2092 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2095 result
= radv_reset_cmd_buffer(cmd_buffer
);
2096 if (result
!= VK_SUCCESS
)
2099 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
2100 cmd_buffer
->state
.last_primitive_reset_en
= -1;
2101 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
2103 /* setup initial configuration into command buffer */
2104 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
2105 switch (cmd_buffer
->queue_family_index
) {
2106 case RADV_QUEUE_GENERAL
:
2107 emit_gfx_buffer_state(cmd_buffer
);
2108 radv_set_db_count_control(cmd_buffer
);
2110 case RADV_QUEUE_COMPUTE
:
2111 si_init_compute(cmd_buffer
);
2113 case RADV_QUEUE_TRANSFER
:
2119 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2120 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
2121 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
2123 struct radv_subpass
*subpass
=
2124 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
2126 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
2127 if (result
!= VK_SUCCESS
)
2130 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
2133 radv_cmd_buffer_trace_emit(cmd_buffer
);
2137 void radv_CmdBindVertexBuffers(
2138 VkCommandBuffer commandBuffer
,
2139 uint32_t firstBinding
,
2140 uint32_t bindingCount
,
2141 const VkBuffer
* pBuffers
,
2142 const VkDeviceSize
* pOffsets
)
2144 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2145 struct radv_vertex_binding
*vb
= cmd_buffer
->state
.vertex_bindings
;
2147 /* We have to defer setting up vertex buffer since we need the buffer
2148 * stride from the pipeline. */
2150 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
2151 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2152 vb
[firstBinding
+ i
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2153 vb
[firstBinding
+ i
].offset
= pOffsets
[i
];
2156 cmd_buffer
->state
.vb_dirty
= true;
2159 void radv_CmdBindIndexBuffer(
2160 VkCommandBuffer commandBuffer
,
2162 VkDeviceSize offset
,
2163 VkIndexType indexType
)
2165 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2166 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2168 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2169 cmd_buffer
->state
.index_va
= cmd_buffer
->device
->ws
->buffer_get_va(index_buffer
->bo
);
2170 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2172 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2173 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2174 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2175 cmd_buffer
->device
->ws
->cs_add_buffer(cmd_buffer
->cs
, index_buffer
->bo
, 8);
2179 void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2180 struct radv_descriptor_set
*set
,
2183 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2185 cmd_buffer
->state
.descriptors
[idx
] = set
;
2186 cmd_buffer
->state
.descriptors_dirty
|= (1u << idx
);
2190 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2192 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2193 if (set
->descriptors
[j
])
2194 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->descriptors
[j
], 7);
2197 ws
->cs_add_buffer(cmd_buffer
->cs
, set
->bo
, 8);
2200 void radv_CmdBindDescriptorSets(
2201 VkCommandBuffer commandBuffer
,
2202 VkPipelineBindPoint pipelineBindPoint
,
2203 VkPipelineLayout _layout
,
2205 uint32_t descriptorSetCount
,
2206 const VkDescriptorSet
* pDescriptorSets
,
2207 uint32_t dynamicOffsetCount
,
2208 const uint32_t* pDynamicOffsets
)
2210 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2211 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2212 unsigned dyn_idx
= 0;
2214 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2215 unsigned idx
= i
+ firstSet
;
2216 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2217 radv_bind_descriptor_set(cmd_buffer
, set
, idx
);
2219 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2220 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2221 uint32_t *dst
= cmd_buffer
->dynamic_buffers
+ idx
* 4;
2222 assert(dyn_idx
< dynamicOffsetCount
);
2224 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2225 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2227 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2228 dst
[2] = range
->size
;
2229 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2230 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2231 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2232 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2233 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2234 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2235 cmd_buffer
->push_constant_stages
|=
2236 set
->layout
->dynamic_shader_stages
;
2241 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2242 struct radv_descriptor_set
*set
,
2243 struct radv_descriptor_set_layout
*layout
)
2245 set
->size
= layout
->size
;
2246 set
->layout
= layout
;
2248 if (cmd_buffer
->push_descriptors
.capacity
< set
->size
) {
2249 size_t new_size
= MAX2(set
->size
, 1024);
2250 new_size
= MAX2(new_size
, 2 * cmd_buffer
->push_descriptors
.capacity
);
2251 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2253 free(set
->mapped_ptr
);
2254 set
->mapped_ptr
= malloc(new_size
);
2256 if (!set
->mapped_ptr
) {
2257 cmd_buffer
->push_descriptors
.capacity
= 0;
2258 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2262 cmd_buffer
->push_descriptors
.capacity
= new_size
;
2268 void radv_meta_push_descriptor_set(
2269 struct radv_cmd_buffer
* cmd_buffer
,
2270 VkPipelineBindPoint pipelineBindPoint
,
2271 VkPipelineLayout _layout
,
2273 uint32_t descriptorWriteCount
,
2274 const VkWriteDescriptorSet
* pDescriptorWrites
)
2276 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2277 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2281 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2283 push_set
->size
= layout
->set
[set
].layout
->size
;
2284 push_set
->layout
= layout
->set
[set
].layout
;
2286 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2288 (void**) &push_set
->mapped_ptr
))
2291 push_set
->va
= cmd_buffer
->device
->ws
->buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2292 push_set
->va
+= bo_offset
;
2294 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2295 radv_descriptor_set_to_handle(push_set
),
2296 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2298 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2299 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2302 void radv_CmdPushDescriptorSetKHR(
2303 VkCommandBuffer commandBuffer
,
2304 VkPipelineBindPoint pipelineBindPoint
,
2305 VkPipelineLayout _layout
,
2307 uint32_t descriptorWriteCount
,
2308 const VkWriteDescriptorSet
* pDescriptorWrites
)
2310 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2311 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2312 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2314 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2316 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2319 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2320 radv_descriptor_set_to_handle(push_set
),
2321 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2323 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2324 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2325 cmd_buffer
->state
.push_descriptors_dirty
= true;
2328 void radv_CmdPushDescriptorSetWithTemplateKHR(
2329 VkCommandBuffer commandBuffer
,
2330 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
2331 VkPipelineLayout _layout
,
2335 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2336 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2337 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2339 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2341 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2344 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2345 descriptorUpdateTemplate
, pData
);
2347 cmd_buffer
->state
.descriptors
[set
] = push_set
;
2348 cmd_buffer
->state
.descriptors_dirty
|= (1u << set
);
2349 cmd_buffer
->state
.push_descriptors_dirty
= true;
2352 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2353 VkPipelineLayout layout
,
2354 VkShaderStageFlags stageFlags
,
2357 const void* pValues
)
2359 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2360 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2361 cmd_buffer
->push_constant_stages
|= stageFlags
;
2364 VkResult
radv_EndCommandBuffer(
2365 VkCommandBuffer commandBuffer
)
2367 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2369 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
2370 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== SI
)
2371 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2372 si_emit_cache_flush(cmd_buffer
);
2375 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
2376 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2378 return cmd_buffer
->record_result
;
2382 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2384 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2385 struct radv_shader_variant
*compute_shader
;
2386 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2389 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2392 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2394 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
2395 va
= ws
->buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
2397 ws
->cs_add_buffer(cmd_buffer
->cs
, compute_shader
->bo
, 8);
2398 radv_emit_prefetch(cmd_buffer
, va
, compute_shader
->code_size
);
2400 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2401 cmd_buffer
->cs
, 16);
2403 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
2404 radeon_emit(cmd_buffer
->cs
, va
>> 8);
2405 radeon_emit(cmd_buffer
->cs
, va
>> 40);
2407 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
2408 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc1
);
2409 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc2
);
2412 cmd_buffer
->compute_scratch_size_needed
=
2413 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2414 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2416 /* change these once we have scratch support */
2417 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
2418 S_00B860_WAVES(pipeline
->max_waves
) |
2419 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
2421 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
2422 radeon_emit(cmd_buffer
->cs
,
2423 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
2424 radeon_emit(cmd_buffer
->cs
,
2425 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
2426 radeon_emit(cmd_buffer
->cs
,
2427 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
2429 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2430 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
2433 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
)
2435 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2436 if (cmd_buffer
->state
.descriptors
[i
])
2437 cmd_buffer
->state
.descriptors_dirty
|= (1u << i
);
2441 void radv_CmdBindPipeline(
2442 VkCommandBuffer commandBuffer
,
2443 VkPipelineBindPoint pipelineBindPoint
,
2444 VkPipeline _pipeline
)
2446 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2447 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
2449 radv_mark_descriptor_sets_dirty(cmd_buffer
);
2451 switch (pipelineBindPoint
) {
2452 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2453 cmd_buffer
->state
.compute_pipeline
= pipeline
;
2454 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2456 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2457 cmd_buffer
->state
.pipeline
= pipeline
;
2461 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2462 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
2464 /* Apply the dynamic state from the pipeline */
2465 cmd_buffer
->state
.dirty
|= pipeline
->dynamic_state_mask
;
2466 radv_dynamic_state_copy(&cmd_buffer
->state
.dynamic
,
2467 &pipeline
->dynamic_state
,
2468 pipeline
->dynamic_state_mask
);
2470 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
2471 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
2472 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
2473 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
2475 if (radv_pipeline_has_tess(pipeline
))
2476 cmd_buffer
->tess_rings_needed
= true;
2478 if (radv_pipeline_has_gs(pipeline
)) {
2479 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2480 AC_UD_SCRATCH_RING_OFFSETS
);
2481 if (cmd_buffer
->ring_offsets_idx
== -1)
2482 cmd_buffer
->ring_offsets_idx
= loc
->sgpr_idx
;
2483 else if (loc
->sgpr_idx
!= -1)
2484 assert(loc
->sgpr_idx
== cmd_buffer
->ring_offsets_idx
);
2488 assert(!"invalid bind point");
2493 void radv_CmdSetViewport(
2494 VkCommandBuffer commandBuffer
,
2495 uint32_t firstViewport
,
2496 uint32_t viewportCount
,
2497 const VkViewport
* pViewports
)
2499 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2501 const uint32_t total_count
= firstViewport
+ viewportCount
;
2502 if (cmd_buffer
->state
.dynamic
.viewport
.count
< total_count
)
2503 cmd_buffer
->state
.dynamic
.viewport
.count
= total_count
;
2505 memcpy(cmd_buffer
->state
.dynamic
.viewport
.viewports
+ firstViewport
,
2506 pViewports
, viewportCount
* sizeof(*pViewports
));
2508 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2511 void radv_CmdSetScissor(
2512 VkCommandBuffer commandBuffer
,
2513 uint32_t firstScissor
,
2514 uint32_t scissorCount
,
2515 const VkRect2D
* pScissors
)
2517 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2519 const uint32_t total_count
= firstScissor
+ scissorCount
;
2520 if (cmd_buffer
->state
.dynamic
.scissor
.count
< total_count
)
2521 cmd_buffer
->state
.dynamic
.scissor
.count
= total_count
;
2523 memcpy(cmd_buffer
->state
.dynamic
.scissor
.scissors
+ firstScissor
,
2524 pScissors
, scissorCount
* sizeof(*pScissors
));
2525 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2528 void radv_CmdSetLineWidth(
2529 VkCommandBuffer commandBuffer
,
2532 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2533 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
2534 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2537 void radv_CmdSetDepthBias(
2538 VkCommandBuffer commandBuffer
,
2539 float depthBiasConstantFactor
,
2540 float depthBiasClamp
,
2541 float depthBiasSlopeFactor
)
2543 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2545 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
2546 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
2547 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
2549 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2552 void radv_CmdSetBlendConstants(
2553 VkCommandBuffer commandBuffer
,
2554 const float blendConstants
[4])
2556 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2558 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
2559 blendConstants
, sizeof(float) * 4);
2561 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2564 void radv_CmdSetDepthBounds(
2565 VkCommandBuffer commandBuffer
,
2566 float minDepthBounds
,
2567 float maxDepthBounds
)
2569 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2571 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
2572 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
2574 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2577 void radv_CmdSetStencilCompareMask(
2578 VkCommandBuffer commandBuffer
,
2579 VkStencilFaceFlags faceMask
,
2580 uint32_t compareMask
)
2582 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2584 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2585 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2586 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2587 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2589 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2592 void radv_CmdSetStencilWriteMask(
2593 VkCommandBuffer commandBuffer
,
2594 VkStencilFaceFlags faceMask
,
2597 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2599 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2600 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2601 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2602 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2604 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2607 void radv_CmdSetStencilReference(
2608 VkCommandBuffer commandBuffer
,
2609 VkStencilFaceFlags faceMask
,
2612 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2614 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2615 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
2616 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2617 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
2619 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2622 void radv_CmdExecuteCommands(
2623 VkCommandBuffer commandBuffer
,
2624 uint32_t commandBufferCount
,
2625 const VkCommandBuffer
* pCmdBuffers
)
2627 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
2629 /* Emit pending flushes on primary prior to executing secondary */
2630 si_emit_cache_flush(primary
);
2632 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2633 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2635 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
2636 secondary
->scratch_size_needed
);
2637 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
2638 secondary
->compute_scratch_size_needed
);
2640 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
2641 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
2642 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
2643 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
2644 if (secondary
->tess_rings_needed
)
2645 primary
->tess_rings_needed
= true;
2646 if (secondary
->sample_positions_needed
)
2647 primary
->sample_positions_needed
= true;
2649 if (secondary
->ring_offsets_idx
!= -1) {
2650 if (primary
->ring_offsets_idx
== -1)
2651 primary
->ring_offsets_idx
= secondary
->ring_offsets_idx
;
2653 assert(secondary
->ring_offsets_idx
== primary
->ring_offsets_idx
);
2655 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
2657 primary
->state
.emitted_pipeline
= secondary
->state
.emitted_pipeline
;
2658 primary
->state
.emitted_compute_pipeline
= secondary
->state
.emitted_compute_pipeline
;
2659 primary
->state
.last_primitive_reset_en
= secondary
->state
.last_primitive_reset_en
;
2660 primary
->state
.last_primitive_reset_index
= secondary
->state
.last_primitive_reset_index
;
2663 /* if we execute secondary we need to mark some stuff to reset dirty */
2664 if (commandBufferCount
) {
2665 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2666 primary
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_ALL
;
2667 radv_mark_descriptor_sets_dirty(primary
);
2671 VkResult
radv_CreateCommandPool(
2673 const VkCommandPoolCreateInfo
* pCreateInfo
,
2674 const VkAllocationCallbacks
* pAllocator
,
2675 VkCommandPool
* pCmdPool
)
2677 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2678 struct radv_cmd_pool
*pool
;
2680 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2681 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2683 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2686 pool
->alloc
= *pAllocator
;
2688 pool
->alloc
= device
->alloc
;
2690 list_inithead(&pool
->cmd_buffers
);
2691 list_inithead(&pool
->free_cmd_buffers
);
2693 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2695 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
2701 void radv_DestroyCommandPool(
2703 VkCommandPool commandPool
,
2704 const VkAllocationCallbacks
* pAllocator
)
2706 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2707 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2712 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2713 &pool
->cmd_buffers
, pool_link
) {
2714 radv_cmd_buffer_destroy(cmd_buffer
);
2717 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2718 &pool
->free_cmd_buffers
, pool_link
) {
2719 radv_cmd_buffer_destroy(cmd_buffer
);
2722 vk_free2(&device
->alloc
, pAllocator
, pool
);
2725 VkResult
radv_ResetCommandPool(
2727 VkCommandPool commandPool
,
2728 VkCommandPoolResetFlags flags
)
2730 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2733 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
2734 &pool
->cmd_buffers
, pool_link
) {
2735 result
= radv_reset_cmd_buffer(cmd_buffer
);
2736 if (result
!= VK_SUCCESS
)
2743 void radv_TrimCommandPoolKHR(
2745 VkCommandPool commandPool
,
2746 VkCommandPoolTrimFlagsKHR flags
)
2748 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2753 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2754 &pool
->free_cmd_buffers
, pool_link
) {
2755 radv_cmd_buffer_destroy(cmd_buffer
);
2759 void radv_CmdBeginRenderPass(
2760 VkCommandBuffer commandBuffer
,
2761 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2762 VkSubpassContents contents
)
2764 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2765 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2766 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2768 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2769 cmd_buffer
->cs
, 2048);
2770 MAYBE_UNUSED VkResult result
;
2772 cmd_buffer
->state
.framebuffer
= framebuffer
;
2773 cmd_buffer
->state
.pass
= pass
;
2774 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2776 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
2777 if (result
!= VK_SUCCESS
)
2780 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
2781 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2783 radv_cmd_buffer_clear_subpass(cmd_buffer
);
2786 void radv_CmdNextSubpass(
2787 VkCommandBuffer commandBuffer
,
2788 VkSubpassContents contents
)
2790 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2792 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
2794 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2797 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
2798 radv_cmd_buffer_clear_subpass(cmd_buffer
);
2801 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
2803 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2804 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2805 if (!pipeline
->shaders
[stage
])
2807 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
2808 if (loc
->sgpr_idx
== -1)
2810 uint32_t base_reg
= radv_shader_stage_to_user_data_0(stage
, radv_pipeline_has_gs(pipeline
), radv_pipeline_has_tess(pipeline
));
2811 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
2814 if (pipeline
->gs_copy_shader
) {
2815 struct ac_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
2816 if (loc
->sgpr_idx
!= -1) {
2817 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2818 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
2824 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
2825 uint32_t vertex_count
)
2827 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
2828 radeon_emit(cmd_buffer
->cs
, vertex_count
);
2829 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
2830 S_0287F0_USE_OPAQUE(0));
2834 VkCommandBuffer commandBuffer
,
2835 uint32_t vertexCount
,
2836 uint32_t instanceCount
,
2837 uint32_t firstVertex
,
2838 uint32_t firstInstance
)
2840 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2842 radv_cmd_buffer_flush_state(cmd_buffer
, false, (instanceCount
> 1), false, vertexCount
);
2844 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 20 * MAX_VIEWS
);
2846 assert(cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
);
2847 radeon_set_sh_reg_seq(cmd_buffer
->cs
, cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
,
2848 cmd_buffer
->state
.pipeline
->graphics
.vtx_emit_num
);
2849 radeon_emit(cmd_buffer
->cs
, firstVertex
);
2850 radeon_emit(cmd_buffer
->cs
, firstInstance
);
2851 if (cmd_buffer
->state
.pipeline
->graphics
.vtx_emit_num
== 3)
2852 radeon_emit(cmd_buffer
->cs
, 0);
2854 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_NUM_INSTANCES
, 0, cmd_buffer
->state
.predicating
));
2855 radeon_emit(cmd_buffer
->cs
, instanceCount
);
2857 if (!cmd_buffer
->state
.subpass
->view_mask
) {
2858 radv_cs_emit_draw_packet(cmd_buffer
, vertexCount
);
2861 for_each_bit(i
, cmd_buffer
->state
.subpass
->view_mask
) {
2862 radv_emit_view_index(cmd_buffer
, i
);
2864 radv_cs_emit_draw_packet(cmd_buffer
, vertexCount
);
2868 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2870 radv_cmd_buffer_after_draw(cmd_buffer
);
2875 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
2877 uint32_t index_count
)
2879 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, false));
2880 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
2881 radeon_emit(cmd_buffer
->cs
, index_va
);
2882 radeon_emit(cmd_buffer
->cs
, (index_va
>> 32UL) & 0xFF);
2883 radeon_emit(cmd_buffer
->cs
, index_count
);
2884 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
2887 void radv_CmdDrawIndexed(
2888 VkCommandBuffer commandBuffer
,
2889 uint32_t indexCount
,
2890 uint32_t instanceCount
,
2891 uint32_t firstIndex
,
2892 int32_t vertexOffset
,
2893 uint32_t firstInstance
)
2895 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2896 int index_size
= cmd_buffer
->state
.index_type
? 4 : 2;
2899 radv_cmd_buffer_flush_state(cmd_buffer
, true, (instanceCount
> 1), false, indexCount
);
2901 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 26 * MAX_VIEWS
);
2903 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2904 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_03090C_VGT_INDEX_TYPE
,
2905 2, cmd_buffer
->state
.index_type
);
2907 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2908 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.index_type
);
2911 assert(cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
);
2912 radeon_set_sh_reg_seq(cmd_buffer
->cs
, cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
,
2913 cmd_buffer
->state
.pipeline
->graphics
.vtx_emit_num
);
2914 radeon_emit(cmd_buffer
->cs
, vertexOffset
);
2915 radeon_emit(cmd_buffer
->cs
, firstInstance
);
2916 if (cmd_buffer
->state
.pipeline
->graphics
.vtx_emit_num
== 3)
2917 radeon_emit(cmd_buffer
->cs
, 0);
2919 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
2920 radeon_emit(cmd_buffer
->cs
, instanceCount
);
2922 index_va
= cmd_buffer
->state
.index_va
;
2923 index_va
+= firstIndex
* index_size
;
2924 if (!cmd_buffer
->state
.subpass
->view_mask
) {
2925 radv_cs_emit_draw_indexed_packet(cmd_buffer
, index_va
, indexCount
);
2928 for_each_bit(i
, cmd_buffer
->state
.subpass
->view_mask
) {
2929 radv_emit_view_index(cmd_buffer
, i
);
2931 radv_cs_emit_draw_indexed_packet(cmd_buffer
, index_va
, indexCount
);
2935 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2936 radv_cmd_buffer_after_draw(cmd_buffer
);
2940 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
2942 uint32_t draw_count
,
2946 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
2947 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
2948 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
2949 bool draw_id_enable
= cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.needs_draw_id
;
2950 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
2953 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
2954 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
2955 PKT3_DRAW_INDIRECT
, 3, false));
2957 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
2958 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
2959 radeon_emit(cs
, di_src_sel
);
2961 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
2962 PKT3_DRAW_INDIRECT_MULTI
,
2965 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
2966 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
2967 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
2968 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
2969 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
2970 radeon_emit(cs
, draw_count
); /* count */
2971 radeon_emit(cs
, count_va
); /* count_addr */
2972 radeon_emit(cs
, count_va
>> 32);
2973 radeon_emit(cs
, stride
); /* stride */
2974 radeon_emit(cs
, di_src_sel
);
2979 radv_emit_indirect_draw(struct radv_cmd_buffer
*cmd_buffer
,
2981 VkDeviceSize offset
,
2982 VkBuffer _count_buffer
,
2983 VkDeviceSize count_offset
,
2984 uint32_t draw_count
,
2988 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2989 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _count_buffer
);
2990 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
2992 uint64_t indirect_va
= cmd_buffer
->device
->ws
->buffer_get_va(buffer
->bo
);
2993 indirect_va
+= offset
+ buffer
->offset
;
2994 uint64_t count_va
= 0;
2997 count_va
= cmd_buffer
->device
->ws
->buffer_get_va(count_buffer
->bo
);
2998 count_va
+= count_offset
+ count_buffer
->offset
;
3004 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, buffer
->bo
, 8);
3006 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
3008 radeon_emit(cs
, indirect_va
);
3009 radeon_emit(cs
, indirect_va
>> 32);
3011 if (!cmd_buffer
->state
.subpass
->view_mask
) {
3012 radv_cs_emit_indirect_draw_packet(cmd_buffer
, indexed
, draw_count
, count_va
, stride
);
3015 for_each_bit(i
, cmd_buffer
->state
.subpass
->view_mask
) {
3016 radv_emit_view_index(cmd_buffer
, i
);
3018 radv_cs_emit_indirect_draw_packet(cmd_buffer
, indexed
, draw_count
, count_va
, stride
);
3021 radv_cmd_buffer_after_draw(cmd_buffer
);
3025 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer
,
3027 VkDeviceSize offset
,
3028 VkBuffer countBuffer
,
3029 VkDeviceSize countBufferOffset
,
3030 uint32_t maxDrawCount
,
3033 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3034 radv_cmd_buffer_flush_state(cmd_buffer
, false, false, true, 0);
3036 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
3037 cmd_buffer
->cs
, 24 * MAX_VIEWS
);
3039 radv_emit_indirect_draw(cmd_buffer
, buffer
, offset
,
3040 countBuffer
, countBufferOffset
, maxDrawCount
, stride
, false);
3042 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3046 radv_cmd_draw_indexed_indirect_count(
3047 VkCommandBuffer commandBuffer
,
3049 VkDeviceSize offset
,
3050 VkBuffer countBuffer
,
3051 VkDeviceSize countBufferOffset
,
3052 uint32_t maxDrawCount
,
3055 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3057 radv_cmd_buffer_flush_state(cmd_buffer
, true, false, true, 0);
3059 index_va
= cmd_buffer
->state
.index_va
;
3061 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 31 * MAX_VIEWS
);
3063 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
3064 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.index_type
);
3066 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
3067 radeon_emit(cmd_buffer
->cs
, index_va
);
3068 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
3070 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
3071 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
3073 radv_emit_indirect_draw(cmd_buffer
, buffer
, offset
,
3074 countBuffer
, countBufferOffset
, maxDrawCount
, stride
, true);
3076 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3079 void radv_CmdDrawIndirect(
3080 VkCommandBuffer commandBuffer
,
3082 VkDeviceSize offset
,
3086 radv_cmd_draw_indirect_count(commandBuffer
, buffer
, offset
,
3087 VK_NULL_HANDLE
, 0, drawCount
, stride
);
3090 void radv_CmdDrawIndexedIndirect(
3091 VkCommandBuffer commandBuffer
,
3093 VkDeviceSize offset
,
3097 radv_cmd_draw_indexed_indirect_count(commandBuffer
, buffer
, offset
,
3098 VK_NULL_HANDLE
, 0, drawCount
, stride
);
3101 void radv_CmdDrawIndirectCountAMD(
3102 VkCommandBuffer commandBuffer
,
3104 VkDeviceSize offset
,
3105 VkBuffer countBuffer
,
3106 VkDeviceSize countBufferOffset
,
3107 uint32_t maxDrawCount
,
3110 radv_cmd_draw_indirect_count(commandBuffer
, buffer
, offset
,
3111 countBuffer
, countBufferOffset
,
3112 maxDrawCount
, stride
);
3115 void radv_CmdDrawIndexedIndirectCountAMD(
3116 VkCommandBuffer commandBuffer
,
3118 VkDeviceSize offset
,
3119 VkBuffer countBuffer
,
3120 VkDeviceSize countBufferOffset
,
3121 uint32_t maxDrawCount
,
3124 radv_cmd_draw_indexed_indirect_count(commandBuffer
, buffer
, offset
,
3125 countBuffer
, countBufferOffset
,
3126 maxDrawCount
, stride
);
3130 radv_flush_compute_state(struct radv_cmd_buffer
*cmd_buffer
)
3132 radv_emit_compute_pipeline(cmd_buffer
);
3133 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
3134 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
3135 VK_SHADER_STAGE_COMPUTE_BIT
);
3136 si_emit_cache_flush(cmd_buffer
);
3139 struct radv_dispatch_info
{
3141 * Determine the layout of the grid (in block units) to be used.
3146 * Whether it's an unaligned compute dispatch.
3151 * Indirect compute parameters resource.
3153 struct radv_buffer
*indirect
;
3154 uint64_t indirect_offset
;
3158 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
3159 const struct radv_dispatch_info
*info
)
3161 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3162 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3163 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3164 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3165 struct ac_userdata_info
*loc
;
3168 grid_used
= compute_shader
->info
.info
.cs
.grid_components_used
;
3170 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
3171 AC_UD_CS_GRID_SIZE
);
3173 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
3175 if (info
->indirect
) {
3176 uint64_t va
= ws
->buffer_get_va(info
->indirect
->bo
);
3178 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3180 ws
->cs_add_buffer(cs
, info
->indirect
->bo
, 8);
3182 if (loc
->sgpr_idx
!= -1) {
3183 for (unsigned i
= 0; i
< grid_used
; ++i
) {
3184 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3185 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
3186 COPY_DATA_DST_SEL(COPY_DATA_REG
));
3187 radeon_emit(cs
, (va
+ 4 * i
));
3188 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
3189 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
3190 + loc
->sgpr_idx
* 4) >> 2) + i
);
3195 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
3196 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, 0) |
3197 PKT3_SHADER_TYPE_S(1));
3198 radeon_emit(cs
, va
);
3199 radeon_emit(cs
, va
>> 32);
3202 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
3203 PKT3_SHADER_TYPE_S(1));
3205 radeon_emit(cs
, va
);
3206 radeon_emit(cs
, va
>> 32);
3208 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, 0) |
3209 PKT3_SHADER_TYPE_S(1));
3214 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
3215 unsigned dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
3217 if (info
->unaligned
) {
3218 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
3219 unsigned remainder
[3];
3221 /* If aligned, these should be an entire block size,
3224 remainder
[0] = blocks
[0] + cs_block_size
[0] -
3225 align_u32_npot(blocks
[0], cs_block_size
[0]);
3226 remainder
[1] = blocks
[1] + cs_block_size
[1] -
3227 align_u32_npot(blocks
[1], cs_block_size
[1]);
3228 remainder
[2] = blocks
[2] + cs_block_size
[2] -
3229 align_u32_npot(blocks
[2], cs_block_size
[2]);
3231 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
3232 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
3233 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
3235 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3237 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
3238 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
3240 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
3241 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
3243 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
3244 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
3246 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
3249 if (loc
->sgpr_idx
!= -1) {
3250 assert(!loc
->indirect
);
3251 assert(loc
->num_sgprs
== grid_used
);
3253 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
3254 loc
->sgpr_idx
* 4, grid_used
);
3255 radeon_emit(cs
, blocks
[0]);
3257 radeon_emit(cs
, blocks
[1]);
3259 radeon_emit(cs
, blocks
[2]);
3262 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
3263 PKT3_SHADER_TYPE_S(1));
3264 radeon_emit(cs
, blocks
[0]);
3265 radeon_emit(cs
, blocks
[1]);
3266 radeon_emit(cs
, blocks
[2]);
3267 radeon_emit(cs
, dispatch_initiator
);
3270 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3273 void radv_CmdDispatch(
3274 VkCommandBuffer commandBuffer
,
3279 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3280 struct radv_dispatch_info info
= {};
3282 radv_flush_compute_state(cmd_buffer
);
3288 radv_emit_dispatch_packets(cmd_buffer
, &info
);
3290 radv_cmd_buffer_after_draw(cmd_buffer
);
3293 void radv_CmdDispatchIndirect(
3294 VkCommandBuffer commandBuffer
,
3296 VkDeviceSize offset
)
3298 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3299 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3300 struct radv_dispatch_info info
= {};
3302 radv_flush_compute_state(cmd_buffer
);
3304 info
.indirect
= buffer
;
3305 info
.indirect_offset
= offset
;
3307 radv_emit_dispatch_packets(cmd_buffer
, &info
);
3309 radv_cmd_buffer_after_draw(cmd_buffer
);
3312 void radv_unaligned_dispatch(
3313 struct radv_cmd_buffer
*cmd_buffer
,
3318 struct radv_dispatch_info info
= {};
3325 radv_flush_compute_state(cmd_buffer
);
3327 radv_emit_dispatch_packets(cmd_buffer
, &info
);
3329 radv_cmd_buffer_after_draw(cmd_buffer
);
3332 void radv_CmdEndRenderPass(
3333 VkCommandBuffer commandBuffer
)
3335 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3337 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
3339 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3341 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
3342 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
3343 radv_handle_subpass_image_transition(cmd_buffer
,
3344 (VkAttachmentReference
){i
, layout
});
3347 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3349 cmd_buffer
->state
.pass
= NULL
;
3350 cmd_buffer
->state
.subpass
= NULL
;
3351 cmd_buffer
->state
.attachments
= NULL
;
3352 cmd_buffer
->state
.framebuffer
= NULL
;
3356 * For HTILE we have the following interesting clear words:
3357 * 0x0000030f: Uncompressed.
3358 * 0xfffffff0: Clear depth to 1.0
3359 * 0x00000000: Clear depth to 0.0
3361 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
3362 struct radv_image
*image
,
3363 const VkImageSubresourceRange
*range
,
3364 uint32_t clear_word
)
3366 assert(range
->baseMipLevel
== 0);
3367 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
3368 unsigned layer_count
= radv_get_layerCount(image
, range
);
3369 uint64_t size
= image
->surface
.htile_slice_size
* layer_count
;
3370 uint64_t offset
= image
->offset
+ image
->htile_offset
+
3371 image
->surface
.htile_slice_size
* range
->baseArrayLayer
;
3373 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3374 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3376 radv_fill_buffer(cmd_buffer
, image
->bo
, offset
, size
, clear_word
);
3378 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
3379 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3380 RADV_CMD_FLAG_INV_VMEM_L1
|
3381 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3384 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3385 struct radv_image
*image
,
3386 VkImageLayout src_layout
,
3387 VkImageLayout dst_layout
,
3388 unsigned src_queue_mask
,
3389 unsigned dst_queue_mask
,
3390 const VkImageSubresourceRange
*range
,
3391 VkImageAspectFlags pending_clears
)
3393 if (dst_layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
&&
3394 (pending_clears
& vk_format_aspects(image
->vk_format
)) == vk_format_aspects(image
->vk_format
) &&
3395 cmd_buffer
->state
.render_area
.offset
.x
== 0 && cmd_buffer
->state
.render_area
.offset
.y
== 0 &&
3396 cmd_buffer
->state
.render_area
.extent
.width
== image
->info
.width
&&
3397 cmd_buffer
->state
.render_area
.extent
.height
== image
->info
.height
) {
3398 /* The clear will initialize htile. */
3400 } else if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
3401 radv_layout_has_htile(image
, dst_layout
, dst_queue_mask
)) {
3402 /* TODO: merge with the clear if applicable */
3403 radv_initialize_htile(cmd_buffer
, image
, range
, 0);
3404 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3405 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3406 radv_initialize_htile(cmd_buffer
, image
, range
, 0xffffffff);
3407 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3408 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3409 VkImageSubresourceRange local_range
= *range
;
3410 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
3411 local_range
.baseMipLevel
= 0;
3412 local_range
.levelCount
= 1;
3414 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3415 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3417 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
3419 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3420 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3424 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
3425 struct radv_image
*image
, uint32_t value
)
3427 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3428 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3430 radv_fill_buffer(cmd_buffer
, image
->bo
, image
->offset
+ image
->cmask
.offset
,
3431 image
->cmask
.size
, value
);
3433 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
3434 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3435 RADV_CMD_FLAG_INV_VMEM_L1
|
3436 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3439 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3440 struct radv_image
*image
,
3441 VkImageLayout src_layout
,
3442 VkImageLayout dst_layout
,
3443 unsigned src_queue_mask
,
3444 unsigned dst_queue_mask
,
3445 const VkImageSubresourceRange
*range
,
3446 VkImageAspectFlags pending_clears
)
3448 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3449 if (image
->fmask
.size
)
3450 radv_initialise_cmask(cmd_buffer
, image
, 0xccccccccu
);
3452 radv_initialise_cmask(cmd_buffer
, image
, 0xffffffffu
);
3453 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3454 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3455 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3459 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
3460 struct radv_image
*image
, uint32_t value
)
3463 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3464 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3466 radv_fill_buffer(cmd_buffer
, image
->bo
, image
->offset
+ image
->dcc_offset
,
3467 image
->surface
.dcc_size
, value
);
3469 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3470 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
3471 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
3472 RADV_CMD_FLAG_INV_VMEM_L1
|
3473 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
3476 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3477 struct radv_image
*image
,
3478 VkImageLayout src_layout
,
3479 VkImageLayout dst_layout
,
3480 unsigned src_queue_mask
,
3481 unsigned dst_queue_mask
,
3482 const VkImageSubresourceRange
*range
,
3483 VkImageAspectFlags pending_clears
)
3485 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3486 radv_initialize_dcc(cmd_buffer
, image
, 0x20202020u
);
3487 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3488 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3489 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3493 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3494 struct radv_image
*image
,
3495 VkImageLayout src_layout
,
3496 VkImageLayout dst_layout
,
3497 uint32_t src_family
,
3498 uint32_t dst_family
,
3499 const VkImageSubresourceRange
*range
,
3500 VkImageAspectFlags pending_clears
)
3502 if (image
->exclusive
&& src_family
!= dst_family
) {
3503 /* This is an acquire or a release operation and there will be
3504 * a corresponding release/acquire. Do the transition in the
3505 * most flexible queue. */
3507 assert(src_family
== cmd_buffer
->queue_family_index
||
3508 dst_family
== cmd_buffer
->queue_family_index
);
3510 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
3513 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
3514 (src_family
== RADV_QUEUE_GENERAL
||
3515 dst_family
== RADV_QUEUE_GENERAL
))
3519 unsigned src_queue_mask
= radv_image_queue_family_mask(image
, src_family
, cmd_buffer
->queue_family_index
);
3520 unsigned dst_queue_mask
= radv_image_queue_family_mask(image
, dst_family
, cmd_buffer
->queue_family_index
);
3522 if (image
->surface
.htile_size
)
3523 radv_handle_depth_image_transition(cmd_buffer
, image
, src_layout
,
3524 dst_layout
, src_queue_mask
,
3525 dst_queue_mask
, range
,
3528 if (image
->cmask
.size
)
3529 radv_handle_cmask_image_transition(cmd_buffer
, image
, src_layout
,
3530 dst_layout
, src_queue_mask
,
3531 dst_queue_mask
, range
,
3534 if (image
->surface
.dcc_size
)
3535 radv_handle_dcc_image_transition(cmd_buffer
, image
, src_layout
,
3536 dst_layout
, src_queue_mask
,
3537 dst_queue_mask
, range
,
3541 void radv_CmdPipelineBarrier(
3542 VkCommandBuffer commandBuffer
,
3543 VkPipelineStageFlags srcStageMask
,
3544 VkPipelineStageFlags destStageMask
,
3546 uint32_t memoryBarrierCount
,
3547 const VkMemoryBarrier
* pMemoryBarriers
,
3548 uint32_t bufferMemoryBarrierCount
,
3549 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3550 uint32_t imageMemoryBarrierCount
,
3551 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3553 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3554 enum radv_cmd_flush_bits src_flush_bits
= 0;
3555 enum radv_cmd_flush_bits dst_flush_bits
= 0;
3557 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3558 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
);
3559 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
3563 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3564 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
);
3565 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
3569 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3570 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3571 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
);
3572 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
3576 radv_stage_flush(cmd_buffer
, srcStageMask
);
3577 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
3579 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3580 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3581 radv_handle_image_transition(cmd_buffer
, image
,
3582 pImageMemoryBarriers
[i
].oldLayout
,
3583 pImageMemoryBarriers
[i
].newLayout
,
3584 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
3585 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
3586 &pImageMemoryBarriers
[i
].subresourceRange
,
3590 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
3594 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
3595 struct radv_event
*event
,
3596 VkPipelineStageFlags stageMask
,
3599 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3600 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(event
->bo
);
3602 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
3604 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 18);
3606 /* TODO: this is overkill. Probably should figure something out from
3607 * the stage mask. */
3609 si_cs_emit_write_event_eop(cs
,
3610 cmd_buffer
->state
.predicating
,
3611 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
3613 EVENT_TYPE_BOTTOM_OF_PIPE_TS
, 0,
3616 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3619 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
3621 VkPipelineStageFlags stageMask
)
3623 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3624 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3626 write_event(cmd_buffer
, event
, stageMask
, 1);
3629 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
3631 VkPipelineStageFlags stageMask
)
3633 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3634 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3636 write_event(cmd_buffer
, event
, stageMask
, 0);
3639 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3640 uint32_t eventCount
,
3641 const VkEvent
* pEvents
,
3642 VkPipelineStageFlags srcStageMask
,
3643 VkPipelineStageFlags dstStageMask
,
3644 uint32_t memoryBarrierCount
,
3645 const VkMemoryBarrier
* pMemoryBarriers
,
3646 uint32_t bufferMemoryBarrierCount
,
3647 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3648 uint32_t imageMemoryBarrierCount
,
3649 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3651 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3652 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3654 for (unsigned i
= 0; i
< eventCount
; ++i
) {
3655 RADV_FROM_HANDLE(radv_event
, event
, pEvents
[i
]);
3656 uint64_t va
= cmd_buffer
->device
->ws
->buffer_get_va(event
->bo
);
3658 cmd_buffer
->device
->ws
->cs_add_buffer(cs
, event
->bo
, 8);
3660 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
3662 si_emit_wait_fence(cs
, false, va
, 1, 0xffffffff);
3663 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3667 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3668 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
3670 radv_handle_image_transition(cmd_buffer
, image
,
3671 pImageMemoryBarriers
[i
].oldLayout
,
3672 pImageMemoryBarriers
[i
].newLayout
,
3673 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
3674 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
3675 &pImageMemoryBarriers
[i
].subresourceRange
,
3679 /* TODO: figure out how to do memory barriers without waiting */
3680 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
|
3681 RADV_CMD_FLAG_INV_GLOBAL_L2
|
3682 RADV_CMD_FLAG_INV_VMEM_L1
|
3683 RADV_CMD_FLAG_INV_SMEM_L1
;