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radv: Implement indirect dispatch for the MEC.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
36 struct radv_image *image,
37 VkImageLayout src_layout,
38 VkImageLayout dst_layout,
39 VkImageSubresourceRange range,
40 VkImageAspectFlags pending_clears);
41
42 const struct radv_dynamic_state default_dynamic_state = {
43 .viewport = {
44 .count = 0,
45 },
46 .scissor = {
47 .count = 0,
48 },
49 .line_width = 1.0f,
50 .depth_bias = {
51 .bias = 0.0f,
52 .clamp = 0.0f,
53 .slope = 0.0f,
54 },
55 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
56 .depth_bounds = {
57 .min = 0.0f,
58 .max = 1.0f,
59 },
60 .stencil_compare_mask = {
61 .front = ~0u,
62 .back = ~0u,
63 },
64 .stencil_write_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_reference = {
69 .front = 0u,
70 .back = 0u,
71 },
72 };
73
74 void
75 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
76 const struct radv_dynamic_state *src,
77 uint32_t copy_mask)
78 {
79 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
80 dest->viewport.count = src->viewport.count;
81 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
82 src->viewport.count);
83 }
84
85 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
86 dest->scissor.count = src->scissor.count;
87 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
88 src->scissor.count);
89 }
90
91 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
92 dest->line_width = src->line_width;
93
94 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
95 dest->depth_bias = src->depth_bias;
96
97 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
98 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
99
100 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
101 dest->depth_bounds = src->depth_bounds;
102
103 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
104 dest->stencil_compare_mask = src->stencil_compare_mask;
105
106 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
107 dest->stencil_write_mask = src->stencil_write_mask;
108
109 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
110 dest->stencil_reference = src->stencil_reference;
111 }
112
113 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
114 {
115 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
116 cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= CIK;
117 }
118
119 enum ring_type radv_queue_family_to_ring(int f) {
120 switch (f) {
121 case RADV_QUEUE_GENERAL:
122 return RING_GFX;
123 case RADV_QUEUE_COMPUTE:
124 return RING_COMPUTE;
125 case RADV_QUEUE_TRANSFER:
126 return RING_DMA;
127 default:
128 unreachable("Unknown queue family");
129 }
130 }
131
132 static VkResult radv_create_cmd_buffer(
133 struct radv_device * device,
134 struct radv_cmd_pool * pool,
135 VkCommandBufferLevel level,
136 VkCommandBuffer* pCommandBuffer)
137 {
138 struct radv_cmd_buffer *cmd_buffer;
139 VkResult result;
140 unsigned ring;
141 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
142 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
143 if (cmd_buffer == NULL)
144 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
145
146 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
147 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
148 cmd_buffer->device = device;
149 cmd_buffer->pool = pool;
150 cmd_buffer->level = level;
151
152 if (pool) {
153 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
154 cmd_buffer->queue_family_index = pool->queue_family_index;
155
156 } else {
157 /* Init the pool_link so we can safefly call list_del when we destroy
158 * the command buffer
159 */
160 list_inithead(&cmd_buffer->pool_link);
161 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
162 }
163
164 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
165
166 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
167 if (!cmd_buffer->cs) {
168 result = VK_ERROR_OUT_OF_HOST_MEMORY;
169 goto fail;
170 }
171
172 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
173
174 cmd_buffer->upload.offset = 0;
175 cmd_buffer->upload.size = 0;
176 list_inithead(&cmd_buffer->upload.list);
177
178 return VK_SUCCESS;
179
180 fail:
181 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
182
183 return result;
184 }
185
186 static bool
187 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
188 uint64_t min_needed)
189 {
190 uint64_t new_size;
191 struct radeon_winsys_bo *bo;
192 struct radv_cmd_buffer_upload *upload;
193 struct radv_device *device = cmd_buffer->device;
194
195 new_size = MAX2(min_needed, 16 * 1024);
196 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
197
198 bo = device->ws->buffer_create(device->ws,
199 new_size, 4096,
200 RADEON_DOMAIN_GTT,
201 RADEON_FLAG_CPU_ACCESS);
202
203 if (!bo) {
204 cmd_buffer->record_fail = true;
205 return false;
206 }
207
208 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
209 if (cmd_buffer->upload.upload_bo) {
210 upload = malloc(sizeof(*upload));
211
212 if (!upload) {
213 cmd_buffer->record_fail = true;
214 device->ws->buffer_destroy(bo);
215 return false;
216 }
217
218 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
219 list_add(&upload->list, &cmd_buffer->upload.list);
220 }
221
222 cmd_buffer->upload.upload_bo = bo;
223 cmd_buffer->upload.size = new_size;
224 cmd_buffer->upload.offset = 0;
225 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
226
227 if (!cmd_buffer->upload.map) {
228 cmd_buffer->record_fail = true;
229 return false;
230 }
231
232 return true;
233 }
234
235 bool
236 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
237 unsigned size,
238 unsigned alignment,
239 unsigned *out_offset,
240 void **ptr)
241 {
242 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
243 if (offset + size > cmd_buffer->upload.size) {
244 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
245 return false;
246 offset = 0;
247 }
248
249 *out_offset = offset;
250 *ptr = cmd_buffer->upload.map + offset;
251
252 cmd_buffer->upload.offset = offset + size;
253 return true;
254 }
255
256 bool
257 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
258 unsigned size, unsigned alignment,
259 const void *data, unsigned *out_offset)
260 {
261 uint8_t *ptr;
262
263 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
264 out_offset, (void **)&ptr))
265 return false;
266
267 if (ptr)
268 memcpy(ptr, data, size);
269
270 return true;
271 }
272
273 static void
274 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
275 struct radv_pipeline *pipeline)
276 {
277 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
278 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
279 8);
280 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
281 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
282 }
283
284 static void
285 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
286 struct radv_pipeline *pipeline)
287 {
288 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
289 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
290 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
291
292 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
293 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
294 }
295
296 /* 12.4 fixed-point */
297 static unsigned radv_pack_float_12p4(float x)
298 {
299 return x <= 0 ? 0 :
300 x >= 4096 ? 0xffff : x * 16;
301 }
302
303 static uint32_t
304 shader_stage_to_user_data_0(gl_shader_stage stage)
305 {
306 switch (stage) {
307 case MESA_SHADER_FRAGMENT:
308 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
309 case MESA_SHADER_VERTEX:
310 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
311 case MESA_SHADER_COMPUTE:
312 return R_00B900_COMPUTE_USER_DATA_0;
313 default:
314 unreachable("unknown shader");
315 }
316 }
317
318 static struct ac_userdata_info *
319 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
320 gl_shader_stage stage,
321 int idx)
322 {
323 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
324 }
325
326 static void
327 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
328 struct radv_pipeline *pipeline,
329 gl_shader_stage stage,
330 int idx, uint64_t va)
331 {
332 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
333 uint32_t base_reg = shader_stage_to_user_data_0(stage);
334 if (loc->sgpr_idx == -1)
335 return;
336 assert(loc->num_sgprs == 2);
337 assert(!loc->indirect);
338 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
339 radeon_emit(cmd_buffer->cs, va);
340 radeon_emit(cmd_buffer->cs, va >> 32);
341 }
342
343 static void
344 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
345 struct radv_pipeline *pipeline)
346 {
347 int num_samples = pipeline->graphics.ms.num_samples;
348 struct radv_multisample_state *ms = &pipeline->graphics.ms;
349 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
350
351 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
352 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
353 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
354
355 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
356 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
357
358 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
359 return;
360
361 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
362 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
363 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
364
365 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
366
367 uint32_t samples_offset;
368 void *samples_ptr;
369 void *src;
370 radv_cmd_buffer_upload_alloc(cmd_buffer, num_samples * 4 * 2, 256, &samples_offset,
371 &samples_ptr);
372 switch (num_samples) {
373 case 1:
374 src = cmd_buffer->device->sample_locations_1x;
375 break;
376 case 2:
377 src = cmd_buffer->device->sample_locations_2x;
378 break;
379 case 4:
380 src = cmd_buffer->device->sample_locations_4x;
381 break;
382 case 8:
383 src = cmd_buffer->device->sample_locations_8x;
384 break;
385 case 16:
386 src = cmd_buffer->device->sample_locations_16x;
387 break;
388 }
389 memcpy(samples_ptr, src, num_samples * 4 * 2);
390
391 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
392 va += samples_offset;
393
394 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
395 AC_UD_PS_SAMPLE_POS, va);
396 }
397
398 static void
399 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
400 struct radv_pipeline *pipeline)
401 {
402 struct radv_raster_state *raster = &pipeline->graphics.raster;
403
404 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
405 raster->pa_cl_clip_cntl);
406
407 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
408 raster->spi_interp_control);
409
410 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
411 radeon_emit(cmd_buffer->cs, 0);
412 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
413 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
414
415 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
416 raster->pa_su_vtx_cntl);
417
418 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
419 raster->pa_su_sc_mode_cntl);
420 }
421
422 static void
423 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
424 struct radv_pipeline *pipeline)
425 {
426 struct radeon_winsys *ws = cmd_buffer->device->ws;
427 struct radv_shader_variant *vs;
428 uint64_t va;
429 unsigned export_count;
430 unsigned clip_dist_mask, cull_dist_mask, total_mask;
431
432 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
433
434 vs = pipeline->shaders[MESA_SHADER_VERTEX];
435 va = ws->buffer_get_va(vs->bo);
436 ws->cs_add_buffer(cmd_buffer->cs, vs->bo, 8);
437
438 clip_dist_mask = vs->info.vs.clip_dist_mask;
439 cull_dist_mask = vs->info.vs.cull_dist_mask;
440 total_mask = clip_dist_mask | cull_dist_mask;
441 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, 0);
442 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
443
444 export_count = MAX2(1, vs->info.vs.param_exports);
445 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
446 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
447 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
448 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
449 S_02870C_POS1_EXPORT_FORMAT(vs->info.vs.pos_exports > 1 ?
450 V_02870C_SPI_SHADER_4COMP :
451 V_02870C_SPI_SHADER_NONE) |
452 S_02870C_POS2_EXPORT_FORMAT(vs->info.vs.pos_exports > 2 ?
453 V_02870C_SPI_SHADER_4COMP :
454 V_02870C_SPI_SHADER_NONE) |
455 S_02870C_POS3_EXPORT_FORMAT(vs->info.vs.pos_exports > 3 ?
456 V_02870C_SPI_SHADER_4COMP :
457 V_02870C_SPI_SHADER_NONE));
458
459 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
460 radeon_emit(cmd_buffer->cs, va >> 8);
461 radeon_emit(cmd_buffer->cs, va >> 40);
462 radeon_emit(cmd_buffer->cs, vs->rsrc1);
463 radeon_emit(cmd_buffer->cs, vs->rsrc2);
464
465 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
466 S_028818_VTX_W0_FMT(1) |
467 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
468 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
469 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
470
471 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
472 S_02881C_USE_VTX_POINT_SIZE(vs->info.vs.writes_pointsize) |
473 S_02881C_VS_OUT_MISC_VEC_ENA(vs->info.vs.writes_pointsize) |
474 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
475 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
476 pipeline->graphics.raster.pa_cl_vs_out_cntl |
477 cull_dist_mask << 8 |
478 clip_dist_mask);
479
480 }
481
482
483
484 static void
485 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
486 struct radv_pipeline *pipeline)
487 {
488 struct radeon_winsys *ws = cmd_buffer->device->ws;
489 struct radv_shader_variant *ps, *vs;
490 uint64_t va;
491 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
492 struct radv_blend_state *blend = &pipeline->graphics.blend;
493 unsigned ps_offset = 0;
494 unsigned z_order;
495 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
496
497 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
498 vs = pipeline->shaders[MESA_SHADER_VERTEX];
499 va = ws->buffer_get_va(ps->bo);
500 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
501
502 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
503 radeon_emit(cmd_buffer->cs, va >> 8);
504 radeon_emit(cmd_buffer->cs, va >> 40);
505 radeon_emit(cmd_buffer->cs, ps->rsrc1);
506 radeon_emit(cmd_buffer->cs, ps->rsrc2);
507
508 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
509 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
510 else
511 z_order = V_02880C_LATE_Z;
512
513
514 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
515 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
516 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
517 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
518 S_02880C_Z_ORDER(z_order) |
519 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
520 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
521 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory));
522
523 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
524 ps->config.spi_ps_input_ena);
525
526 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
527 ps->config.spi_ps_input_addr);
528
529 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(0);
530 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
531 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
532
533 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
534
535 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
536 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
537 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
538 V_028710_SPI_SHADER_ZERO);
539
540 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
541
542 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
543 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
544
545 if (ps->info.fs.has_pcoord) {
546 unsigned val;
547 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
548 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
549 ps_offset = 1;
550 }
551
552 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
553 unsigned vs_offset, flat_shade;
554 unsigned val;
555
556 if (!(ps->info.fs.input_mask & (1u << i)))
557 continue;
558
559
560 if (!(vs->info.vs.export_mask & (1u << i))) {
561 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset,
562 S_028644_OFFSET(0x20));
563 ++ps_offset;
564 continue;
565 }
566
567 vs_offset = util_bitcount(vs->info.vs.export_mask & ((1u << i) - 1));
568 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
569
570 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
571 radeon_set_context_reg(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0 + 4 * ps_offset, val);
572 ++ps_offset;
573 }
574 }
575
576 static void
577 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
578 struct radv_pipeline *pipeline)
579 {
580 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
581 return;
582
583 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
584 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
585 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
586 radv_update_multisample_state(cmd_buffer, pipeline);
587 radv_emit_vertex_shader(cmd_buffer, pipeline);
588 radv_emit_fragment_shader(cmd_buffer, pipeline);
589
590 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
591 pipeline->graphics.prim_restart_enable);
592
593 cmd_buffer->state.emitted_pipeline = pipeline;
594 }
595
596 static void
597 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
598 {
599 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
600 cmd_buffer->state.dynamic.viewport.viewports);
601 }
602
603 static void
604 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
605 {
606 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
607 si_write_scissors(cmd_buffer->cs, 0, count,
608 cmd_buffer->state.dynamic.scissor.scissors);
609 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
610 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
611 }
612
613 static void
614 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
615 int index,
616 struct radv_color_buffer_info *cb)
617 {
618 bool is_vi = cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= VI;
619 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
620 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
621 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
622 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
623 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
624 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
625 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
626 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
627 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
628 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
629 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
630 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
631
632 if (is_vi) { /* DCC BASE */
633 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
634 }
635 }
636
637 static void
638 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
639 struct radv_ds_buffer_info *ds,
640 struct radv_image *image,
641 VkImageLayout layout)
642 {
643 uint32_t db_z_info = ds->db_z_info;
644
645 if (!radv_layout_has_htile(image, layout))
646 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
647
648 if (!radv_layout_can_expclear(image, layout))
649 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
650
651 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
652 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
653
654 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
655 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
656 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
657 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
658 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
659 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
660 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
661 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
662 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
663 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
664
665 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
666 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
667 ds->pa_su_poly_offset_db_fmt_cntl);
668 }
669
670 /*
671 * To hw resolve multisample images both src and dst need to have the same
672 * micro tiling mode. However we don't always know in advance when creating
673 * the images. This function gets called if we have a resolve attachment,
674 * and tests if the attachment image has the same tiling mode, then it
675 * checks if the generated framebuffer data has the same tiling mode, and
676 * updates it if not.
677 */
678 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
679 struct radv_attachment_info *att,
680 uint32_t micro_tile_mode)
681 {
682 struct radv_image *image = att->attachment->image;
683 uint32_t tile_mode_index;
684 if (image->surface.nsamples <= 1)
685 return;
686
687 if (image->surface.micro_tile_mode != micro_tile_mode) {
688 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
689 }
690
691 if (att->cb.micro_tile_mode != micro_tile_mode) {
692 tile_mode_index = image->surface.tiling_index[0];
693
694 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
695 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
696 att->cb.micro_tile_mode = micro_tile_mode;
697 }
698 }
699
700 void
701 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
702 struct radv_image *image,
703 VkClearDepthStencilValue ds_clear_value,
704 VkImageAspectFlags aspects)
705 {
706 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
707 va += image->offset + image->clear_value_offset;
708 unsigned reg_offset = 0, reg_count = 0;
709
710 if (!image->htile.size || !aspects)
711 return;
712
713 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
714 ++reg_count;
715 } else {
716 ++reg_offset;
717 va += 4;
718 }
719 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
720 ++reg_count;
721
722 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
723
724 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
725 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
726 S_370_WR_CONFIRM(1) |
727 S_370_ENGINE_SEL(V_370_PFP));
728 radeon_emit(cmd_buffer->cs, va);
729 radeon_emit(cmd_buffer->cs, va >> 32);
730 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
731 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
732 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
733 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
734
735 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
736 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
737 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
738 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
739 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
740 }
741
742 static void
743 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
744 struct radv_image *image)
745 {
746 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
747 va += image->offset + image->clear_value_offset;
748
749 if (!image->htile.size)
750 return;
751
752 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
753
754 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
755 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
756 COPY_DATA_DST_SEL(COPY_DATA_REG) |
757 COPY_DATA_COUNT_SEL);
758 radeon_emit(cmd_buffer->cs, va);
759 radeon_emit(cmd_buffer->cs, va >> 32);
760 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
761 radeon_emit(cmd_buffer->cs, 0);
762
763 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
764 radeon_emit(cmd_buffer->cs, 0);
765 }
766
767 void
768 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
769 struct radv_image *image,
770 int idx,
771 uint32_t color_values[2])
772 {
773 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
774 va += image->offset + image->clear_value_offset;
775
776 if (!image->cmask.size && !image->surface.dcc_size)
777 return;
778
779 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
780
781 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
782 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
783 S_370_WR_CONFIRM(1) |
784 S_370_ENGINE_SEL(V_370_PFP));
785 radeon_emit(cmd_buffer->cs, va);
786 radeon_emit(cmd_buffer->cs, va >> 32);
787 radeon_emit(cmd_buffer->cs, color_values[0]);
788 radeon_emit(cmd_buffer->cs, color_values[1]);
789
790 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
791 radeon_emit(cmd_buffer->cs, color_values[0]);
792 radeon_emit(cmd_buffer->cs, color_values[1]);
793 }
794
795 static void
796 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
797 struct radv_image *image,
798 int idx)
799 {
800 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
801 va += image->offset + image->clear_value_offset;
802
803 if (!image->cmask.size && !image->surface.dcc_size)
804 return;
805
806 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
807 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
808
809 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
810 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
811 COPY_DATA_DST_SEL(COPY_DATA_REG) |
812 COPY_DATA_COUNT_SEL);
813 radeon_emit(cmd_buffer->cs, va);
814 radeon_emit(cmd_buffer->cs, va >> 32);
815 radeon_emit(cmd_buffer->cs, reg >> 2);
816 radeon_emit(cmd_buffer->cs, 0);
817
818 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
819 radeon_emit(cmd_buffer->cs, 0);
820 }
821
822 void
823 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
824 {
825 int i;
826 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
827 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
828 int dst_resolve_micro_tile_mode = -1;
829
830 if (subpass->has_resolve) {
831 uint32_t a = subpass->resolve_attachments[0].attachment;
832 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
833 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
834 }
835 for (i = 0; i < subpass->color_count; ++i) {
836 int idx = subpass->color_attachments[i].attachment;
837 struct radv_attachment_info *att = &framebuffer->attachments[idx];
838
839 if (dst_resolve_micro_tile_mode != -1) {
840 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
841 att, dst_resolve_micro_tile_mode);
842 }
843 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
844
845 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
846 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
847
848 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
849 }
850
851 for (i = subpass->color_count; i < 8; i++)
852 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
853 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
854
855 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
856 int idx = subpass->depth_stencil_attachment.attachment;
857 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
858 struct radv_attachment_info *att = &framebuffer->attachments[idx];
859 struct radv_image *image = att->attachment->image;
860 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
861
862 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
863
864 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
865 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
866 cmd_buffer->state.offset_scale = att->ds.offset_scale;
867 }
868 radv_load_depth_clear_regs(cmd_buffer, image);
869 } else {
870 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
871 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
872 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
873 }
874 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
875 S_028208_BR_X(framebuffer->width) |
876 S_028208_BR_Y(framebuffer->height));
877 }
878
879 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
880 {
881 uint32_t db_count_control;
882
883 if(!cmd_buffer->state.active_occlusion_queries) {
884 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= CIK) {
885 db_count_control = 0;
886 } else {
887 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
888 }
889 } else {
890 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= CIK) {
891 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
892 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
893 S_028004_ZPASS_ENABLE(1) |
894 S_028004_SLICE_EVEN_ENABLE(1) |
895 S_028004_SLICE_ODD_ENABLE(1);
896 } else {
897 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
898 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
899 }
900 }
901
902 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
903 }
904
905 static void
906 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
907 {
908 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
909
910 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
911 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
912 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
913 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
914 }
915
916 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
917 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
918 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
919 }
920
921 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
922 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
923 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
924 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
925 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
926 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
927 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
928 S_028430_STENCILOPVAL(1));
929 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
930 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
931 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
932 S_028434_STENCILOPVAL_BF(1));
933 }
934
935 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
936 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
937 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
938 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
939 }
940
941 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
942 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
943 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
944 unsigned slope = fui(d->depth_bias.slope * 16.0f);
945 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
946
947 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
948 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
949 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
950 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
951 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
952 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
953 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
954 }
955 }
956
957 cmd_buffer->state.dirty = 0;
958 }
959
960 static void
961 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
962 struct radv_pipeline *pipeline,
963 int idx,
964 uint64_t va,
965 gl_shader_stage stage)
966 {
967 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
968 uint32_t base_reg = shader_stage_to_user_data_0(stage);
969
970 if (desc_set_loc->sgpr_idx == -1)
971 return;
972
973 assert(!desc_set_loc->indirect);
974 assert(desc_set_loc->num_sgprs == 2);
975 radeon_set_sh_reg_seq(cmd_buffer->cs,
976 base_reg + desc_set_loc->sgpr_idx * 4, 2);
977 radeon_emit(cmd_buffer->cs, va);
978 radeon_emit(cmd_buffer->cs, va >> 32);
979 }
980
981 static void
982 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
983 struct radv_pipeline *pipeline,
984 VkShaderStageFlags stages,
985 struct radv_descriptor_set *set,
986 unsigned idx)
987 {
988 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
989 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
990 idx, set->va,
991 MESA_SHADER_FRAGMENT);
992
993 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
994 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
995 idx, set->va,
996 MESA_SHADER_VERTEX);
997
998 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
999 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1000 idx, set->va,
1001 MESA_SHADER_COMPUTE);
1002 }
1003
1004 static void
1005 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1006 struct radv_pipeline *pipeline,
1007 VkShaderStageFlags stages)
1008 {
1009 unsigned i;
1010 if (!cmd_buffer->state.descriptors_dirty)
1011 return;
1012
1013 for (i = 0; i < MAX_SETS; i++) {
1014 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1015 continue;
1016 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1017 if (!set)
1018 continue;
1019
1020 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1021 }
1022 cmd_buffer->state.descriptors_dirty = 0;
1023 }
1024
1025 static void
1026 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1027 struct radv_pipeline *pipeline,
1028 VkShaderStageFlags stages)
1029 {
1030 struct radv_pipeline_layout *layout = pipeline->layout;
1031 unsigned offset;
1032 void *ptr;
1033 uint64_t va;
1034
1035 stages &= cmd_buffer->push_constant_stages;
1036 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1037 return;
1038
1039 radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1040 16 * layout->dynamic_offset_count,
1041 256, &offset, &ptr);
1042
1043 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1044 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1045 16 * layout->dynamic_offset_count);
1046
1047 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1048 va += offset;
1049
1050 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1051 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1052 AC_UD_PUSH_CONSTANTS, va);
1053
1054 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1055 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1056 AC_UD_PUSH_CONSTANTS, va);
1057
1058 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1059 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1060 AC_UD_PUSH_CONSTANTS, va);
1061
1062 cmd_buffer->push_constant_stages &= ~stages;
1063 }
1064
1065 static void
1066 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer)
1067 {
1068 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1069 struct radv_device *device = cmd_buffer->device;
1070 uint32_t ia_multi_vgt_param;
1071 uint32_t ls_hs_config = 0;
1072
1073 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1074 cmd_buffer->cs, 4096);
1075
1076 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1077 cmd_buffer->state.pipeline->num_vertex_attribs) {
1078 unsigned vb_offset;
1079 void *vb_ptr;
1080 uint32_t i = 0;
1081 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1082 uint64_t va;
1083
1084 /* allocate some descriptor state for vertex buffers */
1085 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1086 &vb_offset, &vb_ptr);
1087
1088 for (i = 0; i < num_attribs; i++) {
1089 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1090 uint32_t offset;
1091 int vb = cmd_buffer->state.pipeline->va_binding[i];
1092 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1093 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1094
1095 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1096 va = device->ws->buffer_get_va(buffer->bo);
1097
1098 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1099 va += offset + buffer->offset;
1100 desc[0] = va;
1101 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1102 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class <= CIK && stride)
1103 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1104 else
1105 desc[2] = buffer->size - offset;
1106 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1107 }
1108
1109 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1110 va += vb_offset;
1111
1112 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1113 AC_UD_VS_VERTEX_BUFFERS, va);
1114 }
1115
1116 cmd_buffer->state.vertex_descriptors_dirty = false;
1117 cmd_buffer->state.vb_dirty = 0;
1118 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1119 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1120
1121 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1122 radv_emit_framebuffer_state(cmd_buffer);
1123
1124 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1125 radv_emit_viewport(cmd_buffer);
1126
1127 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR))
1128 radv_emit_scissor(cmd_buffer);
1129
1130 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1131 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, 0);
1132 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer);
1133
1134 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1135 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1136 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
1137 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1138 } else {
1139 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1140 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1141 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
1142 }
1143 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1144 }
1145
1146 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1147
1148 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1149 VK_SHADER_STAGE_ALL_GRAPHICS);
1150 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1151 VK_SHADER_STAGE_ALL_GRAPHICS);
1152
1153 assert(cmd_buffer->cs->cdw <= cdw_max);
1154
1155 si_emit_cache_flush(cmd_buffer);
1156 }
1157
1158 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1159 VkPipelineStageFlags src_stage_mask)
1160 {
1161 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1162 VK_PIPELINE_STAGE_TRANSFER_BIT |
1163 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1164 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1165 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1166 }
1167
1168 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1169 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1170 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1171 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1172 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1173 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1174 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1175 VK_PIPELINE_STAGE_TRANSFER_BIT |
1176 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1177 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1178 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1179 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1180 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1181 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1182 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1183 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1184 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1185 }
1186 }
1187
1188 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1189 {
1190 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1191
1192 /* TODO: actual cache flushes */
1193 }
1194
1195 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1196 VkAttachmentReference att)
1197 {
1198 unsigned idx = att.attachment;
1199 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1200 VkImageSubresourceRange range;
1201 range.aspectMask = 0;
1202 range.baseMipLevel = view->base_mip;
1203 range.levelCount = 1;
1204 range.baseArrayLayer = view->base_layer;
1205 range.layerCount = cmd_buffer->state.framebuffer->layers;
1206
1207 radv_handle_image_transition(cmd_buffer,
1208 view->image,
1209 cmd_buffer->state.attachments[idx].current_layout,
1210 att.layout, range,
1211 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1212
1213 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1214
1215
1216 }
1217
1218 void
1219 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1220 const struct radv_subpass *subpass, bool transitions)
1221 {
1222 if (transitions) {
1223 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1224
1225 for (unsigned i = 0; i < subpass->color_count; ++i) {
1226 radv_handle_subpass_image_transition(cmd_buffer,
1227 subpass->color_attachments[i]);
1228 }
1229
1230 for (unsigned i = 0; i < subpass->input_count; ++i) {
1231 radv_handle_subpass_image_transition(cmd_buffer,
1232 subpass->input_attachments[i]);
1233 }
1234
1235 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1236 radv_handle_subpass_image_transition(cmd_buffer,
1237 subpass->depth_stencil_attachment);
1238 }
1239 }
1240
1241 cmd_buffer->state.subpass = subpass;
1242
1243 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1244 }
1245
1246 static void
1247 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1248 struct radv_render_pass *pass,
1249 const VkRenderPassBeginInfo *info)
1250 {
1251 struct radv_cmd_state *state = &cmd_buffer->state;
1252
1253 if (pass->attachment_count == 0) {
1254 state->attachments = NULL;
1255 return;
1256 }
1257
1258 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1259 pass->attachment_count *
1260 sizeof(state->attachments[0]),
1261 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1262 if (state->attachments == NULL) {
1263 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1264 abort();
1265 }
1266
1267 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1268 struct radv_render_pass_attachment *att = &pass->attachments[i];
1269 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1270 VkImageAspectFlags clear_aspects = 0;
1271
1272 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1273 /* color attachment */
1274 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1275 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1276 }
1277 } else {
1278 /* depthstencil attachment */
1279 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1280 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1281 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1282 }
1283 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1284 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1285 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1286 }
1287 }
1288
1289 state->attachments[i].pending_clear_aspects = clear_aspects;
1290 if (clear_aspects && info) {
1291 assert(info->clearValueCount > i);
1292 state->attachments[i].clear_value = info->pClearValues[i];
1293 }
1294
1295 state->attachments[i].current_layout = att->initial_layout;
1296 }
1297 }
1298
1299 VkResult radv_AllocateCommandBuffers(
1300 VkDevice _device,
1301 const VkCommandBufferAllocateInfo *pAllocateInfo,
1302 VkCommandBuffer *pCommandBuffers)
1303 {
1304 RADV_FROM_HANDLE(radv_device, device, _device);
1305 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1306
1307 VkResult result = VK_SUCCESS;
1308 uint32_t i;
1309
1310 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1311 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1312 &pCommandBuffers[i]);
1313 if (result != VK_SUCCESS)
1314 break;
1315 }
1316
1317 if (result != VK_SUCCESS)
1318 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1319 i, pCommandBuffers);
1320
1321 return result;
1322 }
1323
1324 static void
1325 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
1326 {
1327 list_del(&cmd_buffer->pool_link);
1328
1329 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1330 &cmd_buffer->upload.list, list) {
1331 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1332 list_del(&up->list);
1333 free(up);
1334 }
1335
1336 if (cmd_buffer->upload.upload_bo)
1337 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
1338 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
1339 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1340 }
1341
1342 void radv_FreeCommandBuffers(
1343 VkDevice device,
1344 VkCommandPool commandPool,
1345 uint32_t commandBufferCount,
1346 const VkCommandBuffer *pCommandBuffers)
1347 {
1348 for (uint32_t i = 0; i < commandBufferCount; i++) {
1349 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1350
1351 if (cmd_buffer)
1352 radv_cmd_buffer_destroy(cmd_buffer);
1353 }
1354 }
1355
1356 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
1357 {
1358
1359 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
1360
1361 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
1362 &cmd_buffer->upload.list, list) {
1363 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
1364 list_del(&up->list);
1365 free(up);
1366 }
1367
1368 if (cmd_buffer->upload.upload_bo)
1369 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
1370 cmd_buffer->upload.upload_bo, 8);
1371 cmd_buffer->upload.offset = 0;
1372
1373 cmd_buffer->record_fail = false;
1374 }
1375
1376 VkResult radv_ResetCommandBuffer(
1377 VkCommandBuffer commandBuffer,
1378 VkCommandBufferResetFlags flags)
1379 {
1380 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1381 radv_reset_cmd_buffer(cmd_buffer);
1382 return VK_SUCCESS;
1383 }
1384
1385 VkResult radv_BeginCommandBuffer(
1386 VkCommandBuffer commandBuffer,
1387 const VkCommandBufferBeginInfo *pBeginInfo)
1388 {
1389 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1390 radv_reset_cmd_buffer(cmd_buffer);
1391
1392 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1393
1394 /* setup initial configuration into command buffer */
1395 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1396 switch (cmd_buffer->queue_family_index) {
1397 case RADV_QUEUE_GENERAL:
1398 /* Flush read caches at the beginning of CS not flushed by the kernel. */
1399 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_ICACHE |
1400 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1401 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1402 RADV_CMD_FLAG_INV_VMEM_L1 |
1403 RADV_CMD_FLAG_INV_SMEM_L1 |
1404 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
1405 RADV_CMD_FLAG_INV_GLOBAL_L2;
1406 si_init_config(&cmd_buffer->device->instance->physicalDevice, cmd_buffer);
1407 radv_set_db_count_control(cmd_buffer);
1408 si_emit_cache_flush(cmd_buffer);
1409 break;
1410 case RADV_QUEUE_COMPUTE:
1411 cmd_buffer->state.flush_bits = RADV_CMD_FLAG_INV_ICACHE |
1412 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1413 RADV_CMD_FLAG_INV_VMEM_L1 |
1414 RADV_CMD_FLAG_INV_SMEM_L1 |
1415 RADV_CMD_FLAG_INV_GLOBAL_L2;
1416 si_init_compute(&cmd_buffer->device->instance->physicalDevice, cmd_buffer);
1417 si_emit_cache_flush(cmd_buffer);
1418 break;
1419 case RADV_QUEUE_TRANSFER:
1420 default:
1421 break;
1422 }
1423 }
1424
1425 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1426 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1427 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1428
1429 struct radv_subpass *subpass =
1430 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1431
1432 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1433 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1434 }
1435
1436 return VK_SUCCESS;
1437 }
1438
1439 void radv_CmdBindVertexBuffers(
1440 VkCommandBuffer commandBuffer,
1441 uint32_t firstBinding,
1442 uint32_t bindingCount,
1443 const VkBuffer* pBuffers,
1444 const VkDeviceSize* pOffsets)
1445 {
1446 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1447 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1448
1449 /* We have to defer setting up vertex buffer since we need the buffer
1450 * stride from the pipeline. */
1451
1452 assert(firstBinding + bindingCount < MAX_VBS);
1453 for (uint32_t i = 0; i < bindingCount; i++) {
1454 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1455 vb[firstBinding + i].offset = pOffsets[i];
1456 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1457 }
1458 }
1459
1460 void radv_CmdBindIndexBuffer(
1461 VkCommandBuffer commandBuffer,
1462 VkBuffer buffer,
1463 VkDeviceSize offset,
1464 VkIndexType indexType)
1465 {
1466 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1467
1468 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1469 cmd_buffer->state.index_offset = offset;
1470 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1471 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1472 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1473 }
1474
1475
1476 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1477 struct radv_descriptor_set *set,
1478 unsigned idx)
1479 {
1480 struct radeon_winsys *ws = cmd_buffer->device->ws;
1481
1482 cmd_buffer->state.descriptors[idx] = set;
1483 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1484 if (!set)
1485 return;
1486
1487 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1488 if (set->descriptors[j])
1489 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1490
1491 if(set->bo)
1492 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1493 }
1494
1495 void radv_CmdBindDescriptorSets(
1496 VkCommandBuffer commandBuffer,
1497 VkPipelineBindPoint pipelineBindPoint,
1498 VkPipelineLayout _layout,
1499 uint32_t firstSet,
1500 uint32_t descriptorSetCount,
1501 const VkDescriptorSet* pDescriptorSets,
1502 uint32_t dynamicOffsetCount,
1503 const uint32_t* pDynamicOffsets)
1504 {
1505 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1506 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1507 unsigned dyn_idx = 0;
1508
1509 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1510 cmd_buffer->cs, MAX_SETS * 4 * 6);
1511
1512 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1513 unsigned idx = i + firstSet;
1514 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1515 radv_bind_descriptor_set(cmd_buffer, set, idx);
1516
1517 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1518 unsigned idx = j + layout->set[i].dynamic_offset_start;
1519 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1520 assert(dyn_idx < dynamicOffsetCount);
1521
1522 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1523 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1524 dst[0] = va;
1525 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1526 dst[2] = range->size;
1527 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1528 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1529 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1530 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1531 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1532 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1533 cmd_buffer->push_constant_stages |=
1534 set->layout->dynamic_shader_stages;
1535 }
1536 }
1537
1538 assert(cmd_buffer->cs->cdw <= cdw_max);
1539 }
1540
1541 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1542 VkPipelineLayout layout,
1543 VkShaderStageFlags stageFlags,
1544 uint32_t offset,
1545 uint32_t size,
1546 const void* pValues)
1547 {
1548 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1549 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1550 cmd_buffer->push_constant_stages |= stageFlags;
1551 }
1552
1553 VkResult radv_EndCommandBuffer(
1554 VkCommandBuffer commandBuffer)
1555 {
1556 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1557
1558 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
1559 si_emit_cache_flush(cmd_buffer);
1560 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1561 cmd_buffer->record_fail)
1562 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1563 return VK_SUCCESS;
1564 }
1565
1566 static void
1567 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1568 {
1569 struct radeon_winsys *ws = cmd_buffer->device->ws;
1570 struct radv_shader_variant *compute_shader;
1571 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1572 uint64_t va;
1573
1574 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1575 return;
1576
1577 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1578
1579 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1580 va = ws->buffer_get_va(compute_shader->bo);
1581
1582 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1583
1584 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1585 cmd_buffer->cs, 16);
1586
1587 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1588 radeon_emit(cmd_buffer->cs, va >> 8);
1589 radeon_emit(cmd_buffer->cs, va >> 40);
1590
1591 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1592 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1593 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1594
1595 /* change these once we have scratch support */
1596 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1597 S_00B860_WAVES(32) | S_00B860_WAVESIZE(0));
1598
1599 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1600 radeon_emit(cmd_buffer->cs,
1601 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1602 radeon_emit(cmd_buffer->cs,
1603 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1604 radeon_emit(cmd_buffer->cs,
1605 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1606
1607 assert(cmd_buffer->cs->cdw <= cdw_max);
1608 }
1609
1610
1611 void radv_CmdBindPipeline(
1612 VkCommandBuffer commandBuffer,
1613 VkPipelineBindPoint pipelineBindPoint,
1614 VkPipeline _pipeline)
1615 {
1616 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1617 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1618
1619 for (unsigned i = 0; i < MAX_SETS; i++) {
1620 if (cmd_buffer->state.descriptors[i])
1621 cmd_buffer->state.descriptors_dirty |= (1 << i);
1622 }
1623
1624 switch (pipelineBindPoint) {
1625 case VK_PIPELINE_BIND_POINT_COMPUTE:
1626 cmd_buffer->state.compute_pipeline = pipeline;
1627 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
1628 break;
1629 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1630 cmd_buffer->state.pipeline = pipeline;
1631 cmd_buffer->state.vertex_descriptors_dirty = true;
1632 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1633 cmd_buffer->push_constant_stages |= pipeline->active_stages;
1634
1635 /* Apply the dynamic state from the pipeline */
1636 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
1637 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
1638 &pipeline->dynamic_state,
1639 pipeline->dynamic_state_mask);
1640 break;
1641 default:
1642 assert(!"invalid bind point");
1643 break;
1644 }
1645 }
1646
1647 void radv_CmdSetViewport(
1648 VkCommandBuffer commandBuffer,
1649 uint32_t firstViewport,
1650 uint32_t viewportCount,
1651 const VkViewport* pViewports)
1652 {
1653 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1654
1655 const uint32_t total_count = firstViewport + viewportCount;
1656 if (cmd_buffer->state.dynamic.viewport.count < total_count)
1657 cmd_buffer->state.dynamic.viewport.count = total_count;
1658
1659 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
1660 pViewports, viewportCount * sizeof(*pViewports));
1661
1662 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
1663 }
1664
1665 void radv_CmdSetScissor(
1666 VkCommandBuffer commandBuffer,
1667 uint32_t firstScissor,
1668 uint32_t scissorCount,
1669 const VkRect2D* pScissors)
1670 {
1671 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1672
1673 const uint32_t total_count = firstScissor + scissorCount;
1674 if (cmd_buffer->state.dynamic.scissor.count < total_count)
1675 cmd_buffer->state.dynamic.scissor.count = total_count;
1676
1677 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
1678 pScissors, scissorCount * sizeof(*pScissors));
1679 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1680 }
1681
1682 void radv_CmdSetLineWidth(
1683 VkCommandBuffer commandBuffer,
1684 float lineWidth)
1685 {
1686 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1687 cmd_buffer->state.dynamic.line_width = lineWidth;
1688 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1689 }
1690
1691 void radv_CmdSetDepthBias(
1692 VkCommandBuffer commandBuffer,
1693 float depthBiasConstantFactor,
1694 float depthBiasClamp,
1695 float depthBiasSlopeFactor)
1696 {
1697 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1698
1699 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
1700 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
1701 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
1702
1703 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1704 }
1705
1706 void radv_CmdSetBlendConstants(
1707 VkCommandBuffer commandBuffer,
1708 const float blendConstants[4])
1709 {
1710 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1711
1712 memcpy(cmd_buffer->state.dynamic.blend_constants,
1713 blendConstants, sizeof(float) * 4);
1714
1715 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
1716 }
1717
1718 void radv_CmdSetDepthBounds(
1719 VkCommandBuffer commandBuffer,
1720 float minDepthBounds,
1721 float maxDepthBounds)
1722 {
1723 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1724
1725 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
1726 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
1727
1728 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
1729 }
1730
1731 void radv_CmdSetStencilCompareMask(
1732 VkCommandBuffer commandBuffer,
1733 VkStencilFaceFlags faceMask,
1734 uint32_t compareMask)
1735 {
1736 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1737
1738 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1739 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
1740 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1741 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
1742
1743 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1744 }
1745
1746 void radv_CmdSetStencilWriteMask(
1747 VkCommandBuffer commandBuffer,
1748 VkStencilFaceFlags faceMask,
1749 uint32_t writeMask)
1750 {
1751 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1752
1753 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1754 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
1755 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1756 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
1757
1758 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1759 }
1760
1761 void radv_CmdSetStencilReference(
1762 VkCommandBuffer commandBuffer,
1763 VkStencilFaceFlags faceMask,
1764 uint32_t reference)
1765 {
1766 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1767
1768 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1769 cmd_buffer->state.dynamic.stencil_reference.front = reference;
1770 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1771 cmd_buffer->state.dynamic.stencil_reference.back = reference;
1772
1773 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1774 }
1775
1776
1777 void radv_CmdExecuteCommands(
1778 VkCommandBuffer commandBuffer,
1779 uint32_t commandBufferCount,
1780 const VkCommandBuffer* pCmdBuffers)
1781 {
1782 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
1783
1784 for (uint32_t i = 0; i < commandBufferCount; i++) {
1785 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
1786
1787 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
1788 }
1789
1790 /* if we execute secondary we need to re-emit out pipelines */
1791 if (commandBufferCount) {
1792 primary->state.emitted_pipeline = NULL;
1793 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1794 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
1795 }
1796 }
1797
1798 VkResult radv_CreateCommandPool(
1799 VkDevice _device,
1800 const VkCommandPoolCreateInfo* pCreateInfo,
1801 const VkAllocationCallbacks* pAllocator,
1802 VkCommandPool* pCmdPool)
1803 {
1804 RADV_FROM_HANDLE(radv_device, device, _device);
1805 struct radv_cmd_pool *pool;
1806
1807 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
1808 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1809 if (pool == NULL)
1810 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1811
1812 if (pAllocator)
1813 pool->alloc = *pAllocator;
1814 else
1815 pool->alloc = device->alloc;
1816
1817 list_inithead(&pool->cmd_buffers);
1818
1819 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
1820
1821 *pCmdPool = radv_cmd_pool_to_handle(pool);
1822
1823 return VK_SUCCESS;
1824
1825 }
1826
1827 void radv_DestroyCommandPool(
1828 VkDevice _device,
1829 VkCommandPool commandPool,
1830 const VkAllocationCallbacks* pAllocator)
1831 {
1832 RADV_FROM_HANDLE(radv_device, device, _device);
1833 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
1834
1835 if (!pool)
1836 return;
1837
1838 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
1839 &pool->cmd_buffers, pool_link) {
1840 radv_cmd_buffer_destroy(cmd_buffer);
1841 }
1842
1843 vk_free2(&device->alloc, pAllocator, pool);
1844 }
1845
1846 VkResult radv_ResetCommandPool(
1847 VkDevice device,
1848 VkCommandPool commandPool,
1849 VkCommandPoolResetFlags flags)
1850 {
1851 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
1852
1853 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
1854 &pool->cmd_buffers, pool_link) {
1855 radv_reset_cmd_buffer(cmd_buffer);
1856 }
1857
1858 return VK_SUCCESS;
1859 }
1860
1861 void radv_CmdBeginRenderPass(
1862 VkCommandBuffer commandBuffer,
1863 const VkRenderPassBeginInfo* pRenderPassBegin,
1864 VkSubpassContents contents)
1865 {
1866 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1867 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
1868 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
1869
1870 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1871 cmd_buffer->cs, 2048);
1872
1873 cmd_buffer->state.framebuffer = framebuffer;
1874 cmd_buffer->state.pass = pass;
1875 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
1876 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
1877
1878 si_emit_cache_flush(cmd_buffer);
1879
1880 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
1881 assert(cmd_buffer->cs->cdw <= cdw_max);
1882
1883 radv_cmd_buffer_clear_subpass(cmd_buffer);
1884 }
1885
1886 void radv_CmdNextSubpass(
1887 VkCommandBuffer commandBuffer,
1888 VkSubpassContents contents)
1889 {
1890 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1891
1892 si_emit_cache_flush(cmd_buffer);
1893 radv_cmd_buffer_resolve_subpass(cmd_buffer);
1894
1895 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
1896 2048);
1897
1898 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
1899 radv_cmd_buffer_clear_subpass(cmd_buffer);
1900 }
1901
1902 void radv_CmdDraw(
1903 VkCommandBuffer commandBuffer,
1904 uint32_t vertexCount,
1905 uint32_t instanceCount,
1906 uint32_t firstVertex,
1907 uint32_t firstInstance)
1908 {
1909 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1910 radv_cmd_buffer_flush_state(cmd_buffer);
1911
1912 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1913
1914 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1915 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
1916 if (loc->sgpr_idx != -1) {
1917 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4, 2);
1918 radeon_emit(cmd_buffer->cs, firstVertex);
1919 radeon_emit(cmd_buffer->cs, firstInstance);
1920 }
1921 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
1922 radeon_emit(cmd_buffer->cs, instanceCount);
1923
1924 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
1925 radeon_emit(cmd_buffer->cs, vertexCount);
1926 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1927 S_0287F0_USE_OPAQUE(0));
1928
1929 assert(cmd_buffer->cs->cdw <= cdw_max);
1930 }
1931
1932 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
1933 {
1934 uint32_t primitive_reset_index = cmd_buffer->state.last_primitive_reset_index ? 0xffffffffu : 0xffffu;
1935
1936 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
1937 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1938 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1939 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1940 primitive_reset_index);
1941 }
1942 }
1943
1944 void radv_CmdDrawIndexed(
1945 VkCommandBuffer commandBuffer,
1946 uint32_t indexCount,
1947 uint32_t instanceCount,
1948 uint32_t firstIndex,
1949 int32_t vertexOffset,
1950 uint32_t firstInstance)
1951 {
1952 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1953 int index_size = cmd_buffer->state.index_type ? 4 : 2;
1954 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
1955 uint64_t index_va;
1956
1957 radv_cmd_buffer_flush_state(cmd_buffer);
1958 radv_emit_primitive_reset_index(cmd_buffer);
1959
1960 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 14);
1961
1962 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1963 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
1964
1965 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1966 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
1967 if (loc->sgpr_idx != -1) {
1968 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4, 2);
1969 radeon_emit(cmd_buffer->cs, vertexOffset);
1970 radeon_emit(cmd_buffer->cs, firstInstance);
1971 }
1972 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
1973 radeon_emit(cmd_buffer->cs, instanceCount);
1974
1975 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
1976 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
1977 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
1978 radeon_emit(cmd_buffer->cs, index_max_size);
1979 radeon_emit(cmd_buffer->cs, index_va);
1980 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
1981 radeon_emit(cmd_buffer->cs, indexCount);
1982 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
1983
1984 assert(cmd_buffer->cs->cdw <= cdw_max);
1985 }
1986
1987 static void
1988 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
1989 VkBuffer _buffer,
1990 VkDeviceSize offset,
1991 VkBuffer _count_buffer,
1992 VkDeviceSize count_offset,
1993 uint32_t draw_count,
1994 uint32_t stride,
1995 bool indexed)
1996 {
1997 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1998 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
1999 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2000 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2001 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2002 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2003 indirect_va += offset + buffer->offset;
2004 uint64_t count_va = 0;
2005
2006 if (count_buffer) {
2007 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2008 count_va += count_offset + count_buffer->offset;
2009 }
2010
2011 if (!draw_count)
2012 return;
2013
2014 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2015
2016 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2017 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2018 assert(loc->sgpr_idx != -1);
2019 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2020 radeon_emit(cs, 1);
2021 radeon_emit(cs, indirect_va);
2022 radeon_emit(cs, indirect_va >> 32);
2023
2024 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2025 PKT3_DRAW_INDIRECT_MULTI,
2026 8, false));
2027 radeon_emit(cs, 0);
2028 radeon_emit(cs, ((R_00B130_SPI_SHADER_USER_DATA_VS_0 + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2029 radeon_emit(cs, ((R_00B130_SPI_SHADER_USER_DATA_VS_0 + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2030 radeon_emit(cs, S_2C3_COUNT_INDIRECT_ENABLE(!!count_va)); /* draw_index and count_indirect enable */
2031 radeon_emit(cs, draw_count); /* count */
2032 radeon_emit(cs, count_va); /* count_addr */
2033 radeon_emit(cs, count_va >> 32);
2034 radeon_emit(cs, stride); /* stride */
2035 radeon_emit(cs, di_src_sel);
2036 }
2037
2038 static void
2039 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2040 VkBuffer buffer,
2041 VkDeviceSize offset,
2042 VkBuffer countBuffer,
2043 VkDeviceSize countBufferOffset,
2044 uint32_t maxDrawCount,
2045 uint32_t stride)
2046 {
2047 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2048 radv_cmd_buffer_flush_state(cmd_buffer);
2049
2050 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2051 cmd_buffer->cs, 14);
2052
2053 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2054 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2055
2056 assert(cmd_buffer->cs->cdw <= cdw_max);
2057 }
2058
2059 static void
2060 radv_cmd_draw_indexed_indirect_count(
2061 VkCommandBuffer commandBuffer,
2062 VkBuffer buffer,
2063 VkDeviceSize offset,
2064 VkBuffer countBuffer,
2065 VkDeviceSize countBufferOffset,
2066 uint32_t maxDrawCount,
2067 uint32_t stride)
2068 {
2069 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2070 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2071 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2072 uint64_t index_va;
2073 radv_cmd_buffer_flush_state(cmd_buffer);
2074 radv_emit_primitive_reset_index(cmd_buffer);
2075
2076 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2077 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2078
2079 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2080
2081 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2082 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2083
2084 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2085 radeon_emit(cmd_buffer->cs, index_va);
2086 radeon_emit(cmd_buffer->cs, index_va >> 32);
2087
2088 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2089 radeon_emit(cmd_buffer->cs, index_max_size);
2090
2091 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2092 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2093
2094 assert(cmd_buffer->cs->cdw <= cdw_max);
2095 }
2096
2097 void radv_CmdDrawIndirect(
2098 VkCommandBuffer commandBuffer,
2099 VkBuffer buffer,
2100 VkDeviceSize offset,
2101 uint32_t drawCount,
2102 uint32_t stride)
2103 {
2104 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2105 VK_NULL_HANDLE, 0, drawCount, stride);
2106 }
2107
2108 void radv_CmdDrawIndexedIndirect(
2109 VkCommandBuffer commandBuffer,
2110 VkBuffer buffer,
2111 VkDeviceSize offset,
2112 uint32_t drawCount,
2113 uint32_t stride)
2114 {
2115 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2116 VK_NULL_HANDLE, 0, drawCount, stride);
2117 }
2118
2119 void radv_CmdDrawIndirectCountAMD(
2120 VkCommandBuffer commandBuffer,
2121 VkBuffer buffer,
2122 VkDeviceSize offset,
2123 VkBuffer countBuffer,
2124 VkDeviceSize countBufferOffset,
2125 uint32_t maxDrawCount,
2126 uint32_t stride)
2127 {
2128 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2129 countBuffer, countBufferOffset,
2130 maxDrawCount, stride);
2131 }
2132
2133 void radv_CmdDrawIndexedIndirectCountAMD(
2134 VkCommandBuffer commandBuffer,
2135 VkBuffer buffer,
2136 VkDeviceSize offset,
2137 VkBuffer countBuffer,
2138 VkDeviceSize countBufferOffset,
2139 uint32_t maxDrawCount,
2140 uint32_t stride)
2141 {
2142 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2143 countBuffer, countBufferOffset,
2144 maxDrawCount, stride);
2145 }
2146
2147 static void
2148 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2149 {
2150 radv_emit_compute_pipeline(cmd_buffer);
2151 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2152 VK_SHADER_STAGE_COMPUTE_BIT);
2153 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2154 VK_SHADER_STAGE_COMPUTE_BIT);
2155 si_emit_cache_flush(cmd_buffer);
2156 }
2157
2158 void radv_CmdDispatch(
2159 VkCommandBuffer commandBuffer,
2160 uint32_t x,
2161 uint32_t y,
2162 uint32_t z)
2163 {
2164 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2165
2166 radv_flush_compute_state(cmd_buffer);
2167
2168 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2169
2170 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2171 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2172 if (loc->sgpr_idx != -1) {
2173 assert(!loc->indirect);
2174 assert(loc->num_sgprs == 3);
2175 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2176 radeon_emit(cmd_buffer->cs, x);
2177 radeon_emit(cmd_buffer->cs, y);
2178 radeon_emit(cmd_buffer->cs, z);
2179 }
2180
2181 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2182 PKT3_SHADER_TYPE_S(1));
2183 radeon_emit(cmd_buffer->cs, x);
2184 radeon_emit(cmd_buffer->cs, y);
2185 radeon_emit(cmd_buffer->cs, z);
2186 radeon_emit(cmd_buffer->cs, 1);
2187
2188 assert(cmd_buffer->cs->cdw <= cdw_max);
2189 }
2190
2191 void radv_CmdDispatchIndirect(
2192 VkCommandBuffer commandBuffer,
2193 VkBuffer _buffer,
2194 VkDeviceSize offset)
2195 {
2196 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2197 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2198 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2199 va += buffer->offset + offset;
2200
2201 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2202
2203 radv_flush_compute_state(cmd_buffer);
2204
2205 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2206 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2207 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2208 if (loc->sgpr_idx != -1) {
2209 for (unsigned i = 0; i < 3; ++i) {
2210 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2211 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2212 COPY_DATA_DST_SEL(COPY_DATA_REG));
2213 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2214 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2215 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2216 radeon_emit(cmd_buffer->cs, 0);
2217 }
2218 }
2219
2220 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2221 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2222 PKT3_SHADER_TYPE_S(1));
2223 radeon_emit(cmd_buffer->cs, va);
2224 radeon_emit(cmd_buffer->cs, va >> 32);
2225 radeon_emit(cmd_buffer->cs, 1);
2226 } else {
2227 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2228 PKT3_SHADER_TYPE_S(1));
2229 radeon_emit(cmd_buffer->cs, 1);
2230 radeon_emit(cmd_buffer->cs, va);
2231 radeon_emit(cmd_buffer->cs, va >> 32);
2232
2233 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2234 PKT3_SHADER_TYPE_S(1));
2235 radeon_emit(cmd_buffer->cs, 0);
2236 radeon_emit(cmd_buffer->cs, 1);
2237 }
2238
2239 assert(cmd_buffer->cs->cdw <= cdw_max);
2240 }
2241
2242 void radv_unaligned_dispatch(
2243 struct radv_cmd_buffer *cmd_buffer,
2244 uint32_t x,
2245 uint32_t y,
2246 uint32_t z)
2247 {
2248 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2249 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2250 uint32_t blocks[3], remainder[3];
2251
2252 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2253 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2254 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2255
2256 /* If aligned, these should be an entire block size, not 0 */
2257 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2258 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2259 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2260
2261 radv_flush_compute_state(cmd_buffer);
2262
2263 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2264
2265 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2266 radeon_emit(cmd_buffer->cs,
2267 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2268 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2269 radeon_emit(cmd_buffer->cs,
2270 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2271 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2272 radeon_emit(cmd_buffer->cs,
2273 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2274 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2275
2276 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2277 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2278 if (loc->sgpr_idx != -1) {
2279 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2280 radeon_emit(cmd_buffer->cs, blocks[0]);
2281 radeon_emit(cmd_buffer->cs, blocks[1]);
2282 radeon_emit(cmd_buffer->cs, blocks[2]);
2283 }
2284 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2285 PKT3_SHADER_TYPE_S(1));
2286 radeon_emit(cmd_buffer->cs, blocks[0]);
2287 radeon_emit(cmd_buffer->cs, blocks[1]);
2288 radeon_emit(cmd_buffer->cs, blocks[2]);
2289 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2290 S_00B800_PARTIAL_TG_EN(1));
2291
2292 assert(cmd_buffer->cs->cdw <= cdw_max);
2293 }
2294
2295 void radv_CmdEndRenderPass(
2296 VkCommandBuffer commandBuffer)
2297 {
2298 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2299
2300 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2301
2302 si_emit_cache_flush(cmd_buffer);
2303 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2304
2305 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2306 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2307 radv_handle_subpass_image_transition(cmd_buffer,
2308 (VkAttachmentReference){i, layout});
2309 }
2310
2311 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2312
2313 cmd_buffer->state.pass = NULL;
2314 cmd_buffer->state.subpass = NULL;
2315 cmd_buffer->state.attachments = NULL;
2316 cmd_buffer->state.framebuffer = NULL;
2317 }
2318
2319
2320 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2321 struct radv_image *image)
2322 {
2323
2324 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2325 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2326
2327 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->htile.offset,
2328 image->htile.size, 0xffffffff);
2329
2330 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2331 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2332 RADV_CMD_FLAG_INV_VMEM_L1 |
2333 RADV_CMD_FLAG_INV_GLOBAL_L2;
2334 }
2335
2336 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2337 struct radv_image *image,
2338 VkImageLayout src_layout,
2339 VkImageLayout dst_layout,
2340 VkImageSubresourceRange range,
2341 VkImageAspectFlags pending_clears)
2342 {
2343 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2344 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2345 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2346 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2347 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2348 /* The clear will initialize htile. */
2349 return;
2350 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2351 radv_layout_has_htile(image, dst_layout)) {
2352 /* TODO: merge with the clear if applicable */
2353 radv_initialize_htile(cmd_buffer, image);
2354 } else if (!radv_layout_has_htile(image, src_layout) &&
2355 radv_layout_has_htile(image, dst_layout)) {
2356 radv_initialize_htile(cmd_buffer, image);
2357 } else if ((radv_layout_has_htile(image, src_layout) &&
2358 !radv_layout_has_htile(image, dst_layout)) ||
2359 (radv_layout_is_htile_compressed(image, src_layout) &&
2360 !radv_layout_is_htile_compressed(image, dst_layout))) {
2361
2362 range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2363 range.baseMipLevel = 0;
2364 range.levelCount = 1;
2365
2366 radv_decompress_depth_image_inplace(cmd_buffer, image, &range);
2367 }
2368 }
2369
2370 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2371 struct radv_image *image, uint32_t value)
2372 {
2373 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2374 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2375
2376 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2377 image->cmask.size, value);
2378
2379 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2380 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2381 RADV_CMD_FLAG_INV_VMEM_L1 |
2382 RADV_CMD_FLAG_INV_GLOBAL_L2;
2383 }
2384
2385 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2386 struct radv_image *image,
2387 VkImageLayout src_layout,
2388 VkImageLayout dst_layout,
2389 VkImageSubresourceRange range,
2390 VkImageAspectFlags pending_clears)
2391 {
2392 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2393 if (image->fmask.size)
2394 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2395 else
2396 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2397 } else if (radv_layout_has_cmask(image, src_layout) &&
2398 !radv_layout_has_cmask(image, dst_layout)) {
2399 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2400 }
2401 }
2402
2403 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2404 struct radv_image *image, uint32_t value)
2405 {
2406
2407 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2408 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2409
2410 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2411 image->surface.dcc_size, value);
2412
2413 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2414 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2415 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2416 RADV_CMD_FLAG_INV_VMEM_L1 |
2417 RADV_CMD_FLAG_INV_GLOBAL_L2;
2418 }
2419
2420 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2421 struct radv_image *image,
2422 VkImageLayout src_layout,
2423 VkImageLayout dst_layout,
2424 VkImageSubresourceRange range,
2425 VkImageAspectFlags pending_clears)
2426 {
2427 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2428 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2429 } else if(src_layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
2430 dst_layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL) {
2431 radv_fast_clear_flush_image_inplace(cmd_buffer, image);
2432 }
2433 }
2434
2435 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2436 struct radv_image *image,
2437 VkImageLayout src_layout,
2438 VkImageLayout dst_layout,
2439 VkImageSubresourceRange range,
2440 VkImageAspectFlags pending_clears)
2441 {
2442 if (image->htile.size)
2443 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2444 dst_layout, range, pending_clears);
2445
2446 if (image->cmask.size)
2447 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2448 dst_layout, range, pending_clears);
2449
2450 if (image->surface.dcc_size)
2451 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2452 dst_layout, range, pending_clears);
2453 }
2454
2455 void radv_CmdPipelineBarrier(
2456 VkCommandBuffer commandBuffer,
2457 VkPipelineStageFlags srcStageMask,
2458 VkPipelineStageFlags destStageMask,
2459 VkBool32 byRegion,
2460 uint32_t memoryBarrierCount,
2461 const VkMemoryBarrier* pMemoryBarriers,
2462 uint32_t bufferMemoryBarrierCount,
2463 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2464 uint32_t imageMemoryBarrierCount,
2465 const VkImageMemoryBarrier* pImageMemoryBarriers)
2466 {
2467 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2468 VkAccessFlags src_flags = 0;
2469 VkAccessFlags dst_flags = 0;
2470 uint32_t b;
2471 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2472 src_flags |= pMemoryBarriers[i].srcAccessMask;
2473 dst_flags |= pMemoryBarriers[i].dstAccessMask;
2474 }
2475
2476 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2477 src_flags |= pBufferMemoryBarriers[i].srcAccessMask;
2478 dst_flags |= pBufferMemoryBarriers[i].dstAccessMask;
2479 }
2480
2481 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2482 src_flags |= pImageMemoryBarriers[i].srcAccessMask;
2483 dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
2484 }
2485
2486 enum radv_cmd_flush_bits flush_bits = 0;
2487 for_each_bit(b, src_flags) {
2488 switch ((VkAccessFlagBits)(1 << b)) {
2489 case VK_ACCESS_SHADER_WRITE_BIT:
2490 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2491 break;
2492 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2493 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2494 break;
2495 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2496 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2497 break;
2498 case VK_ACCESS_TRANSFER_WRITE_BIT:
2499 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2500 break;
2501 default:
2502 break;
2503 }
2504 }
2505 cmd_buffer->state.flush_bits |= flush_bits;
2506
2507 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2508 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2509 radv_handle_image_transition(cmd_buffer, image,
2510 pImageMemoryBarriers[i].oldLayout,
2511 pImageMemoryBarriers[i].newLayout,
2512 pImageMemoryBarriers[i].subresourceRange,
2513 0);
2514 }
2515
2516 flush_bits = 0;
2517
2518 for_each_bit(b, dst_flags) {
2519 switch ((VkAccessFlagBits)(1 << b)) {
2520 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2521 case VK_ACCESS_INDEX_READ_BIT:
2522 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2523 case VK_ACCESS_UNIFORM_READ_BIT:
2524 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2525 break;
2526 case VK_ACCESS_SHADER_READ_BIT:
2527 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2528 break;
2529 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2530 case VK_ACCESS_TRANSFER_READ_BIT:
2531 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2532 flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER | RADV_CMD_FLAG_INV_GLOBAL_L2;
2533 default:
2534 break;
2535 }
2536 }
2537
2538 flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2539 RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2540
2541 cmd_buffer->state.flush_bits |= flush_bits;
2542 }
2543
2544
2545 static void write_event(struct radv_cmd_buffer *cmd_buffer,
2546 struct radv_event *event,
2547 VkPipelineStageFlags stageMask,
2548 unsigned value)
2549 {
2550 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2551 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2552
2553 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2554
2555 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
2556
2557 /* TODO: this is overkill. Probably should figure something out from
2558 * the stage mask. */
2559
2560 if (cmd_buffer->device->instance->physicalDevice.rad_info.chip_class == CIK) {
2561 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2562 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2563 EVENT_INDEX(5));
2564 radeon_emit(cs, va);
2565 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2566 radeon_emit(cs, 2);
2567 radeon_emit(cs, 0);
2568 }
2569
2570 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2571 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2572 EVENT_INDEX(5));
2573 radeon_emit(cs, va);
2574 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2575 radeon_emit(cs, value);
2576 radeon_emit(cs, 0);
2577
2578 assert(cmd_buffer->cs->cdw <= cdw_max);
2579 }
2580
2581 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
2582 VkEvent _event,
2583 VkPipelineStageFlags stageMask)
2584 {
2585 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2586 RADV_FROM_HANDLE(radv_event, event, _event);
2587
2588 write_event(cmd_buffer, event, stageMask, 1);
2589 }
2590
2591 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
2592 VkEvent _event,
2593 VkPipelineStageFlags stageMask)
2594 {
2595 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2596 RADV_FROM_HANDLE(radv_event, event, _event);
2597
2598 write_event(cmd_buffer, event, stageMask, 0);
2599 }
2600
2601 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
2602 uint32_t eventCount,
2603 const VkEvent* pEvents,
2604 VkPipelineStageFlags srcStageMask,
2605 VkPipelineStageFlags dstStageMask,
2606 uint32_t memoryBarrierCount,
2607 const VkMemoryBarrier* pMemoryBarriers,
2608 uint32_t bufferMemoryBarrierCount,
2609 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2610 uint32_t imageMemoryBarrierCount,
2611 const VkImageMemoryBarrier* pImageMemoryBarriers)
2612 {
2613 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2614 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2615
2616 for (unsigned i = 0; i < eventCount; ++i) {
2617 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
2618 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2619
2620 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2621
2622 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
2623
2624 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
2625 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
2626 radeon_emit(cs, va);
2627 radeon_emit(cs, va >> 32);
2628 radeon_emit(cs, 1); /* reference value */
2629 radeon_emit(cs, 0xffffffff); /* mask */
2630 radeon_emit(cs, 4); /* poll interval */
2631
2632 assert(cmd_buffer->cs->cdw <= cdw_max);
2633 }
2634
2635
2636 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2637 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2638
2639 radv_handle_image_transition(cmd_buffer, image,
2640 pImageMemoryBarriers[i].oldLayout,
2641 pImageMemoryBarriers[i].newLayout,
2642 pImageMemoryBarriers[i].subresourceRange,
2643 0);
2644 }
2645
2646 /* TODO: figure out how to do memory barriers without waiting */
2647 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
2648 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2649 RADV_CMD_FLAG_INV_VMEM_L1 |
2650 RADV_CMD_FLAG_INV_SMEM_L1;
2651 }