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radv: remove unused 'predicated' parameter from some functions
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safely call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo, 8);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 cmd_buffer->ring_offsets_idx = -1;
314
315 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
316 cmd_buffer->descriptors[i].dirty = 0;
317 cmd_buffer->descriptors[i].valid = 0;
318 cmd_buffer->descriptors[i].push_dirty = false;
319 }
320
321 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
322 void *fence_ptr;
323 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
324 &cmd_buffer->gfx9_fence_offset,
325 &fence_ptr);
326 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
327 }
328
329 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
330
331 return cmd_buffer->record_result;
332 }
333
334 static bool
335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
336 uint64_t min_needed)
337 {
338 uint64_t new_size;
339 struct radeon_winsys_bo *bo;
340 struct radv_cmd_buffer_upload *upload;
341 struct radv_device *device = cmd_buffer->device;
342
343 new_size = MAX2(min_needed, 16 * 1024);
344 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
345
346 bo = device->ws->buffer_create(device->ws,
347 new_size, 4096,
348 RADEON_DOMAIN_GTT,
349 RADEON_FLAG_CPU_ACCESS|
350 RADEON_FLAG_NO_INTERPROCESS_SHARING |
351 RADEON_FLAG_32BIT);
352
353 if (!bo) {
354 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
355 return false;
356 }
357
358 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
359 if (cmd_buffer->upload.upload_bo) {
360 upload = malloc(sizeof(*upload));
361
362 if (!upload) {
363 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
364 device->ws->buffer_destroy(bo);
365 return false;
366 }
367
368 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
369 list_add(&upload->list, &cmd_buffer->upload.list);
370 }
371
372 cmd_buffer->upload.upload_bo = bo;
373 cmd_buffer->upload.size = new_size;
374 cmd_buffer->upload.offset = 0;
375 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
376
377 if (!cmd_buffer->upload.map) {
378 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
379 return false;
380 }
381
382 return true;
383 }
384
385 bool
386 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
387 unsigned size,
388 unsigned alignment,
389 unsigned *out_offset,
390 void **ptr)
391 {
392 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
393 if (offset + size > cmd_buffer->upload.size) {
394 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
395 return false;
396 offset = 0;
397 }
398
399 *out_offset = offset;
400 *ptr = cmd_buffer->upload.map + offset;
401
402 cmd_buffer->upload.offset = offset + size;
403 return true;
404 }
405
406 bool
407 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
408 unsigned size, unsigned alignment,
409 const void *data, unsigned *out_offset)
410 {
411 uint8_t *ptr;
412
413 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
414 out_offset, (void **)&ptr))
415 return false;
416
417 if (ptr)
418 memcpy(ptr, data, size);
419
420 return true;
421 }
422
423 static void
424 radv_emit_write_data_packet(struct radeon_cmdbuf *cs, uint64_t va,
425 unsigned count, const uint32_t *data)
426 {
427 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
428 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
429 S_370_WR_CONFIRM(1) |
430 S_370_ENGINE_SEL(V_370_ME));
431 radeon_emit(cs, va);
432 radeon_emit(cs, va >> 32);
433 radeon_emit_array(cs, data, count);
434 }
435
436 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
437 {
438 struct radv_device *device = cmd_buffer->device;
439 struct radeon_cmdbuf *cs = cmd_buffer->cs;
440 uint64_t va;
441
442 va = radv_buffer_get_va(device->trace_bo);
443 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
444 va += 4;
445
446 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
447
448 ++cmd_buffer->state.trace_id;
449 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
450 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
451 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
452 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
453 }
454
455 static void
456 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
457 enum radv_cmd_flush_bits flags)
458 {
459 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
460 uint32_t *ptr = NULL;
461 uint64_t va = 0;
462
463 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
464 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
465
466 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
467 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
468 cmd_buffer->gfx9_fence_offset;
469 ptr = &cmd_buffer->gfx9_fence_idx;
470 }
471
472 /* Force wait for graphics or compute engines to be idle. */
473 si_cs_emit_cache_flush(cmd_buffer->cs,
474 cmd_buffer->device->physical_device->rad_info.chip_class,
475 ptr, va,
476 radv_cmd_buffer_uses_mec(cmd_buffer),
477 flags);
478 }
479
480 if (unlikely(cmd_buffer->device->trace_bo))
481 radv_cmd_buffer_trace_emit(cmd_buffer);
482 }
483
484 static void
485 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
486 struct radv_pipeline *pipeline, enum ring_type ring)
487 {
488 struct radv_device *device = cmd_buffer->device;
489 struct radeon_cmdbuf *cs = cmd_buffer->cs;
490 uint32_t data[2];
491 uint64_t va;
492
493 va = radv_buffer_get_va(device->trace_bo);
494
495 switch (ring) {
496 case RING_GFX:
497 va += 8;
498 break;
499 case RING_COMPUTE:
500 va += 16;
501 break;
502 default:
503 assert(!"invalid ring type");
504 }
505
506 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
507 cmd_buffer->cs, 6);
508
509 data[0] = (uintptr_t)pipeline;
510 data[1] = (uintptr_t)pipeline >> 32;
511
512 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
513 radv_emit_write_data_packet(cs, va, 2, data);
514 }
515
516 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
517 VkPipelineBindPoint bind_point,
518 struct radv_descriptor_set *set,
519 unsigned idx)
520 {
521 struct radv_descriptor_state *descriptors_state =
522 radv_get_descriptors_state(cmd_buffer, bind_point);
523
524 descriptors_state->sets[idx] = set;
525 if (set)
526 descriptors_state->valid |= (1u << idx);
527 else
528 descriptors_state->valid &= ~(1u << idx);
529 descriptors_state->dirty |= (1u << idx);
530 }
531
532 static void
533 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
534 VkPipelineBindPoint bind_point)
535 {
536 struct radv_descriptor_state *descriptors_state =
537 radv_get_descriptors_state(cmd_buffer, bind_point);
538 struct radv_device *device = cmd_buffer->device;
539 struct radeon_cmdbuf *cs = cmd_buffer->cs;
540 uint32_t data[MAX_SETS * 2] = {};
541 uint64_t va;
542 unsigned i;
543 va = radv_buffer_get_va(device->trace_bo) + 24;
544
545 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
546 cmd_buffer->cs, 4 + MAX_SETS * 2);
547
548 for_each_bit(i, descriptors_state->valid) {
549 struct radv_descriptor_set *set = descriptors_state->sets[i];
550 data[i * 2] = (uintptr_t)set;
551 data[i * 2 + 1] = (uintptr_t)set >> 32;
552 }
553
554 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
555 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
556 }
557
558 struct radv_userdata_info *
559 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
560 gl_shader_stage stage,
561 int idx)
562 {
563 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
564 return &shader->info.user_sgprs_locs.shader_data[idx];
565 }
566
567 static void
568 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
569 struct radv_pipeline *pipeline,
570 gl_shader_stage stage,
571 int idx, uint64_t va)
572 {
573 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
574 uint32_t base_reg = pipeline->user_data_0[stage];
575 if (loc->sgpr_idx == -1)
576 return;
577
578 assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
579 assert(!loc->indirect);
580
581 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
582 base_reg + loc->sgpr_idx * 4, va, false);
583 }
584
585 static void
586 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
587 struct radv_pipeline *pipeline,
588 struct radv_descriptor_state *descriptors_state,
589 gl_shader_stage stage)
590 {
591 struct radv_device *device = cmd_buffer->device;
592 struct radeon_cmdbuf *cs = cmd_buffer->cs;
593 uint32_t sh_base = pipeline->user_data_0[stage];
594 struct radv_userdata_locations *locs =
595 &pipeline->shaders[stage]->info.user_sgprs_locs;
596 unsigned mask;
597
598 mask = descriptors_state->dirty & descriptors_state->valid;
599
600 for (int i = 0; i < MAX_SETS; i++) {
601 struct radv_userdata_info *loc = &locs->descriptor_sets[i];
602 if (loc->sgpr_idx != -1 && !loc->indirect)
603 continue;
604 mask &= ~(1 << i);
605 }
606
607 while (mask) {
608 int start, count;
609
610 u_bit_scan_consecutive_range(&mask, &start, &count);
611
612 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
613 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
614
615 radv_emit_shader_pointer_head(cs, sh_offset, count,
616 HAVE_32BIT_POINTERS);
617 for (int i = 0; i < count; i++) {
618 struct radv_descriptor_set *set =
619 descriptors_state->sets[start + i];
620
621 radv_emit_shader_pointer_body(device, cs, set->va,
622 HAVE_32BIT_POINTERS);
623 }
624 }
625 }
626
627 static void
628 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
629 struct radv_pipeline *pipeline)
630 {
631 int num_samples = pipeline->graphics.ms.num_samples;
632 struct radv_multisample_state *ms = &pipeline->graphics.ms;
633 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
634
635 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
636 cmd_buffer->sample_positions_needed = true;
637
638 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
639 return;
640
641 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
642 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
643 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
644
645 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
646
647 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
648
649 /* GFX9: Flush DFSM when the AA mode changes. */
650 if (cmd_buffer->device->dfsm_allowed) {
651 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
652 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
653 }
654 }
655
656 static void
657 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
658 struct radv_shader_variant *shader)
659 {
660 uint64_t va;
661
662 if (!shader)
663 return;
664
665 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
666
667 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
668 }
669
670 static void
671 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
672 struct radv_pipeline *pipeline,
673 bool vertex_stage_only)
674 {
675 struct radv_cmd_state *state = &cmd_buffer->state;
676 uint32_t mask = state->prefetch_L2_mask;
677
678 if (vertex_stage_only) {
679 /* Fast prefetch path for starting draws as soon as possible.
680 */
681 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
682 RADV_PREFETCH_VBO_DESCRIPTORS);
683 }
684
685 if (mask & RADV_PREFETCH_VS)
686 radv_emit_shader_prefetch(cmd_buffer,
687 pipeline->shaders[MESA_SHADER_VERTEX]);
688
689 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
690 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
691
692 if (mask & RADV_PREFETCH_TCS)
693 radv_emit_shader_prefetch(cmd_buffer,
694 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
695
696 if (mask & RADV_PREFETCH_TES)
697 radv_emit_shader_prefetch(cmd_buffer,
698 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
699
700 if (mask & RADV_PREFETCH_GS) {
701 radv_emit_shader_prefetch(cmd_buffer,
702 pipeline->shaders[MESA_SHADER_GEOMETRY]);
703 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
704 }
705
706 if (mask & RADV_PREFETCH_PS)
707 radv_emit_shader_prefetch(cmd_buffer,
708 pipeline->shaders[MESA_SHADER_FRAGMENT]);
709
710 state->prefetch_L2_mask &= ~mask;
711 }
712
713 static void
714 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
715 {
716 if (!cmd_buffer->device->physical_device->rbplus_allowed)
717 return;
718
719 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
720 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
721 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
722
723 unsigned sx_ps_downconvert = 0;
724 unsigned sx_blend_opt_epsilon = 0;
725 unsigned sx_blend_opt_control = 0;
726
727 for (unsigned i = 0; i < subpass->color_count; ++i) {
728 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
729 continue;
730
731 int idx = subpass->color_attachments[i].attachment;
732 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
733
734 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
735 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
736 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
737 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
738
739 bool has_alpha, has_rgb;
740
741 /* Set if RGB and A are present. */
742 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
743
744 if (format == V_028C70_COLOR_8 ||
745 format == V_028C70_COLOR_16 ||
746 format == V_028C70_COLOR_32)
747 has_rgb = !has_alpha;
748 else
749 has_rgb = true;
750
751 /* Check the colormask and export format. */
752 if (!(colormask & 0x7))
753 has_rgb = false;
754 if (!(colormask & 0x8))
755 has_alpha = false;
756
757 if (spi_format == V_028714_SPI_SHADER_ZERO) {
758 has_rgb = false;
759 has_alpha = false;
760 }
761
762 /* Disable value checking for disabled channels. */
763 if (!has_rgb)
764 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
765 if (!has_alpha)
766 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
767
768 /* Enable down-conversion for 32bpp and smaller formats. */
769 switch (format) {
770 case V_028C70_COLOR_8:
771 case V_028C70_COLOR_8_8:
772 case V_028C70_COLOR_8_8_8_8:
773 /* For 1 and 2-channel formats, use the superset thereof. */
774 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
775 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
776 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
777 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
778 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
779 }
780 break;
781
782 case V_028C70_COLOR_5_6_5:
783 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
784 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
785 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
786 }
787 break;
788
789 case V_028C70_COLOR_1_5_5_5:
790 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
791 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
792 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
793 }
794 break;
795
796 case V_028C70_COLOR_4_4_4_4:
797 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
798 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
799 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
800 }
801 break;
802
803 case V_028C70_COLOR_32:
804 if (swap == V_028C70_SWAP_STD &&
805 spi_format == V_028714_SPI_SHADER_32_R)
806 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
807 else if (swap == V_028C70_SWAP_ALT_REV &&
808 spi_format == V_028714_SPI_SHADER_32_AR)
809 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
810 break;
811
812 case V_028C70_COLOR_16:
813 case V_028C70_COLOR_16_16:
814 /* For 1-channel formats, use the superset thereof. */
815 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
816 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
817 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
818 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
819 if (swap == V_028C70_SWAP_STD ||
820 swap == V_028C70_SWAP_STD_REV)
821 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
822 else
823 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
824 }
825 break;
826
827 case V_028C70_COLOR_10_11_11:
828 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
829 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
830 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
831 }
832 break;
833
834 case V_028C70_COLOR_2_10_10_10:
835 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
836 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
837 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
838 }
839 break;
840 }
841 }
842
843 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
844 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
845 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
846 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
847 }
848
849 static void
850 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
851 {
852 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
853
854 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
855 return;
856
857 radv_update_multisample_state(cmd_buffer, pipeline);
858
859 cmd_buffer->scratch_size_needed =
860 MAX2(cmd_buffer->scratch_size_needed,
861 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
862
863 if (!cmd_buffer->state.emitted_pipeline ||
864 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
865 pipeline->graphics.can_use_guardband)
866 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
867
868 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
869
870 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
871 if (!pipeline->shaders[i])
872 continue;
873
874 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
875 pipeline->shaders[i]->bo, 8);
876 }
877
878 if (radv_pipeline_has_gs(pipeline))
879 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
880 pipeline->gs_copy_shader->bo, 8);
881
882 if (unlikely(cmd_buffer->device->trace_bo))
883 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
884
885 cmd_buffer->state.emitted_pipeline = pipeline;
886
887 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
888 }
889
890 static void
891 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
892 {
893 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
894 cmd_buffer->state.dynamic.viewport.viewports);
895 }
896
897 static void
898 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
899 {
900 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
901
902 si_write_scissors(cmd_buffer->cs, 0, count,
903 cmd_buffer->state.dynamic.scissor.scissors,
904 cmd_buffer->state.dynamic.viewport.viewports,
905 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
906 }
907
908 static void
909 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
910 {
911 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
912 return;
913
914 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
915 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
916 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
917 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
918 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
919 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
920 S_028214_BR_Y(rect.offset.y + rect.extent.height));
921 }
922 }
923
924 static void
925 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
926 {
927 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
928
929 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
930 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
931 }
932
933 static void
934 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
935 {
936 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
937
938 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
939 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
940 }
941
942 static void
943 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
944 {
945 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
946
947 radeon_set_context_reg_seq(cmd_buffer->cs,
948 R_028430_DB_STENCILREFMASK, 2);
949 radeon_emit(cmd_buffer->cs,
950 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
951 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
952 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
953 S_028430_STENCILOPVAL(1));
954 radeon_emit(cmd_buffer->cs,
955 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
956 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
957 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
958 S_028434_STENCILOPVAL_BF(1));
959 }
960
961 static void
962 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
963 {
964 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
965
966 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
967 fui(d->depth_bounds.min));
968 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
969 fui(d->depth_bounds.max));
970 }
971
972 static void
973 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
974 {
975 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
976 unsigned slope = fui(d->depth_bias.slope * 16.0f);
977 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
978
979
980 radeon_set_context_reg_seq(cmd_buffer->cs,
981 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
982 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
983 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
984 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
985 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
986 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
987 }
988
989 static void
990 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
991 int index,
992 struct radv_attachment_info *att,
993 struct radv_image *image,
994 VkImageLayout layout)
995 {
996 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
997 struct radv_color_buffer_info *cb = &att->cb;
998 uint32_t cb_color_info = cb->cb_color_info;
999
1000 if (!radv_layout_dcc_compressed(image, layout,
1001 radv_image_queue_family_mask(image,
1002 cmd_buffer->queue_family_index,
1003 cmd_buffer->queue_family_index))) {
1004 cb_color_info &= C_028C70_DCC_ENABLE;
1005 }
1006
1007 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1008 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1009 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1010 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1011 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1012 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1013 radeon_emit(cmd_buffer->cs, cb_color_info);
1014 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1015 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1016 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1017 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1018 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1019 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1020
1021 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1022 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1023 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1024
1025 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1026 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1027 } else {
1028 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1029 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1030 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1031 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1032 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1033 radeon_emit(cmd_buffer->cs, cb_color_info);
1034 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1035 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1036 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1037 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1038 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1039 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1040
1041 if (is_vi) { /* DCC BASE */
1042 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1043 }
1044 }
1045 }
1046
1047 static void
1048 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1049 struct radv_ds_buffer_info *ds,
1050 struct radv_image *image, VkImageLayout layout,
1051 bool requires_cond_write)
1052 {
1053 uint32_t db_z_info = ds->db_z_info;
1054 uint32_t db_z_info_reg;
1055
1056 if (!radv_image_is_tc_compat_htile(image))
1057 return;
1058
1059 if (!radv_layout_has_htile(image, layout,
1060 radv_image_queue_family_mask(image,
1061 cmd_buffer->queue_family_index,
1062 cmd_buffer->queue_family_index))) {
1063 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1064 }
1065
1066 db_z_info &= C_028040_ZRANGE_PRECISION;
1067
1068 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1069 db_z_info_reg = R_028038_DB_Z_INFO;
1070 } else {
1071 db_z_info_reg = R_028040_DB_Z_INFO;
1072 }
1073
1074 /* When we don't know the last fast clear value we need to emit a
1075 * conditional packet, otherwise we can update DB_Z_INFO directly.
1076 */
1077 if (requires_cond_write) {
1078 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1079
1080 const uint32_t write_space = 0 << 8; /* register */
1081 const uint32_t poll_space = 1 << 4; /* memory */
1082 const uint32_t function = 3 << 0; /* equal to the reference */
1083 const uint32_t options = write_space | poll_space | function;
1084 radeon_emit(cmd_buffer->cs, options);
1085
1086 /* poll address - location of the depth clear value */
1087 uint64_t va = radv_buffer_get_va(image->bo);
1088 va += image->offset + image->clear_value_offset;
1089
1090 /* In presence of stencil format, we have to adjust the base
1091 * address because the first value is the stencil clear value.
1092 */
1093 if (vk_format_is_stencil(image->vk_format))
1094 va += 4;
1095
1096 radeon_emit(cmd_buffer->cs, va);
1097 radeon_emit(cmd_buffer->cs, va >> 32);
1098
1099 radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
1100 radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
1101 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1102 radeon_emit(cmd_buffer->cs, 0u); /* write address high */
1103 radeon_emit(cmd_buffer->cs, db_z_info);
1104 } else {
1105 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1106 }
1107 }
1108
1109 static void
1110 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1111 struct radv_ds_buffer_info *ds,
1112 struct radv_image *image,
1113 VkImageLayout layout)
1114 {
1115 uint32_t db_z_info = ds->db_z_info;
1116 uint32_t db_stencil_info = ds->db_stencil_info;
1117
1118 if (!radv_layout_has_htile(image, layout,
1119 radv_image_queue_family_mask(image,
1120 cmd_buffer->queue_family_index,
1121 cmd_buffer->queue_family_index))) {
1122 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1123 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1124 }
1125
1126 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1127 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1128
1129
1130 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1131 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1132 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1133 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1134 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1135
1136 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1137 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1138 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1139 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1140 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1141 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1142 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1143 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1144 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1145 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1146 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1147
1148 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1149 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1150 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1151 } else {
1152 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1153
1154 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1155 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1156 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1157 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1158 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1159 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1160 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1161 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1162 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1163 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1164
1165 }
1166
1167 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1168 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1169
1170 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1171 ds->pa_su_poly_offset_db_fmt_cntl);
1172 }
1173
1174 /**
1175 * Update the fast clear depth/stencil values if the image is bound as a
1176 * depth/stencil buffer.
1177 */
1178 static void
1179 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1180 struct radv_image *image,
1181 VkClearDepthStencilValue ds_clear_value,
1182 VkImageAspectFlags aspects)
1183 {
1184 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1185 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1186 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1187 struct radv_attachment_info *att;
1188 uint32_t att_idx;
1189
1190 if (!framebuffer || !subpass)
1191 return;
1192
1193 att_idx = subpass->depth_stencil_attachment.attachment;
1194 if (att_idx == VK_ATTACHMENT_UNUSED)
1195 return;
1196
1197 att = &framebuffer->attachments[att_idx];
1198 if (att->attachment->image != image)
1199 return;
1200
1201 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1202 radeon_emit(cs, ds_clear_value.stencil);
1203 radeon_emit(cs, fui(ds_clear_value.depth));
1204
1205 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1206 * only needed when clearing Z to 0.0.
1207 */
1208 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1209 ds_clear_value.depth == 0.0) {
1210 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1211
1212 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1213 layout, false);
1214 }
1215 }
1216
1217 /**
1218 * Set the clear depth/stencil values to the image's metadata.
1219 */
1220 static void
1221 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1222 struct radv_image *image,
1223 VkClearDepthStencilValue ds_clear_value,
1224 VkImageAspectFlags aspects)
1225 {
1226 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1227 uint64_t va = radv_buffer_get_va(image->bo);
1228 unsigned reg_offset = 0, reg_count = 0;
1229
1230 va += image->offset + image->clear_value_offset;
1231
1232 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1233 ++reg_count;
1234 } else {
1235 ++reg_offset;
1236 va += 4;
1237 }
1238 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1239 ++reg_count;
1240
1241 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1242 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1243 S_370_WR_CONFIRM(1) |
1244 S_370_ENGINE_SEL(V_370_PFP));
1245 radeon_emit(cs, va);
1246 radeon_emit(cs, va >> 32);
1247 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1248 radeon_emit(cs, ds_clear_value.stencil);
1249 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1250 radeon_emit(cs, fui(ds_clear_value.depth));
1251 }
1252
1253 /**
1254 * Update the clear depth/stencil values for this image.
1255 */
1256 void
1257 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1258 struct radv_image *image,
1259 VkClearDepthStencilValue ds_clear_value,
1260 VkImageAspectFlags aspects)
1261 {
1262 assert(radv_image_has_htile(image));
1263
1264 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1265
1266 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1267 aspects);
1268 }
1269
1270 /**
1271 * Load the clear depth/stencil values from the image's metadata.
1272 */
1273 static void
1274 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1275 struct radv_image *image)
1276 {
1277 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1278 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1279 uint64_t va = radv_buffer_get_va(image->bo);
1280 unsigned reg_offset = 0, reg_count = 0;
1281
1282 va += image->offset + image->clear_value_offset;
1283
1284 if (!radv_image_has_htile(image))
1285 return;
1286
1287 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1288 ++reg_count;
1289 } else {
1290 ++reg_offset;
1291 va += 4;
1292 }
1293 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1294 ++reg_count;
1295
1296 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1297 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1298 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1299 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1300 radeon_emit(cs, va);
1301 radeon_emit(cs, va >> 32);
1302 radeon_emit(cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1303 radeon_emit(cs, 0);
1304
1305 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1306 radeon_emit(cs, 0);
1307 }
1308
1309 /*
1310 * With DCC some colors don't require CMASK elimination before being
1311 * used as a texture. This sets a predicate value to determine if the
1312 * cmask eliminate is required.
1313 */
1314 void
1315 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1316 struct radv_image *image,
1317 bool value)
1318 {
1319 uint64_t pred_val = value;
1320 uint64_t va = radv_buffer_get_va(image->bo);
1321 va += image->offset + image->dcc_pred_offset;
1322
1323 assert(radv_image_has_dcc(image));
1324
1325 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1326 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1327 S_370_WR_CONFIRM(1) |
1328 S_370_ENGINE_SEL(V_370_PFP));
1329 radeon_emit(cmd_buffer->cs, va);
1330 radeon_emit(cmd_buffer->cs, va >> 32);
1331 radeon_emit(cmd_buffer->cs, pred_val);
1332 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1333 }
1334
1335 /**
1336 * Update the fast clear color values if the image is bound as a color buffer.
1337 */
1338 static void
1339 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1340 struct radv_image *image,
1341 int cb_idx,
1342 uint32_t color_values[2])
1343 {
1344 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1345 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1346 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1347 struct radv_attachment_info *att;
1348 uint32_t att_idx;
1349
1350 if (!framebuffer || !subpass)
1351 return;
1352
1353 att_idx = subpass->color_attachments[cb_idx].attachment;
1354 if (att_idx == VK_ATTACHMENT_UNUSED)
1355 return;
1356
1357 att = &framebuffer->attachments[att_idx];
1358 if (att->attachment->image != image)
1359 return;
1360
1361 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1362 radeon_emit(cs, color_values[0]);
1363 radeon_emit(cs, color_values[1]);
1364 }
1365
1366 /**
1367 * Set the clear color values to the image's metadata.
1368 */
1369 static void
1370 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1371 struct radv_image *image,
1372 uint32_t color_values[2])
1373 {
1374 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1375 uint64_t va = radv_buffer_get_va(image->bo);
1376
1377 va += image->offset + image->clear_value_offset;
1378
1379 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1380
1381 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1382 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1383 S_370_WR_CONFIRM(1) |
1384 S_370_ENGINE_SEL(V_370_PFP));
1385 radeon_emit(cs, va);
1386 radeon_emit(cs, va >> 32);
1387 radeon_emit(cs, color_values[0]);
1388 radeon_emit(cs, color_values[1]);
1389 }
1390
1391 /**
1392 * Update the clear color values for this image.
1393 */
1394 void
1395 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1396 struct radv_image *image,
1397 int cb_idx,
1398 uint32_t color_values[2])
1399 {
1400 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1401
1402 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1403
1404 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1405 color_values);
1406 }
1407
1408 /**
1409 * Load the clear color values from the image's metadata.
1410 */
1411 static void
1412 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1413 struct radv_image *image,
1414 int cb_idx)
1415 {
1416 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1417 uint64_t va = radv_buffer_get_va(image->bo);
1418
1419 va += image->offset + image->clear_value_offset;
1420
1421 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1422 return;
1423
1424 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1425
1426 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1427 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1428 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1429 COPY_DATA_COUNT_SEL);
1430 radeon_emit(cs, va);
1431 radeon_emit(cs, va >> 32);
1432 radeon_emit(cs, reg >> 2);
1433 radeon_emit(cs, 0);
1434
1435 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1436 radeon_emit(cs, 0);
1437 }
1438
1439 static void
1440 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1441 {
1442 int i;
1443 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1444 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1445
1446 /* this may happen for inherited secondary recording */
1447 if (!framebuffer)
1448 return;
1449
1450 for (i = 0; i < 8; ++i) {
1451 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1452 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1453 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1454 continue;
1455 }
1456
1457 int idx = subpass->color_attachments[i].attachment;
1458 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1459 struct radv_image *image = att->attachment->image;
1460 VkImageLayout layout = subpass->color_attachments[i].layout;
1461
1462 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1463
1464 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1465 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1466
1467 radv_load_color_clear_metadata(cmd_buffer, image, i);
1468 }
1469
1470 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1471 int idx = subpass->depth_stencil_attachment.attachment;
1472 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1473 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1474 struct radv_image *image = att->attachment->image;
1475 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1476 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1477 cmd_buffer->queue_family_index,
1478 cmd_buffer->queue_family_index);
1479 /* We currently don't support writing decompressed HTILE */
1480 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1481 radv_layout_is_htile_compressed(image, layout, queue_mask));
1482
1483 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1484
1485 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1486 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1487 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1488 }
1489 radv_load_ds_clear_metadata(cmd_buffer, image);
1490 } else {
1491 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1492 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1493 else
1494 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1495
1496 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1497 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1498 }
1499 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1500 S_028208_BR_X(framebuffer->width) |
1501 S_028208_BR_Y(framebuffer->height));
1502
1503 if (cmd_buffer->device->dfsm_allowed) {
1504 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1505 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1506 }
1507
1508 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1509 }
1510
1511 static void
1512 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1513 {
1514 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1515 struct radv_cmd_state *state = &cmd_buffer->state;
1516
1517 if (state->index_type != state->last_index_type) {
1518 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1519 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1520 2, state->index_type);
1521 } else {
1522 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1523 radeon_emit(cs, state->index_type);
1524 }
1525
1526 state->last_index_type = state->index_type;
1527 }
1528
1529 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1530 radeon_emit(cs, state->index_va);
1531 radeon_emit(cs, state->index_va >> 32);
1532
1533 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1534 radeon_emit(cs, state->max_index_count);
1535
1536 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1537 }
1538
1539 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1540 {
1541 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1542 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1543 uint32_t pa_sc_mode_cntl_1 =
1544 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1545 uint32_t db_count_control;
1546
1547 if(!cmd_buffer->state.active_occlusion_queries) {
1548 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1549 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1550 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1551 has_perfect_queries) {
1552 /* Re-enable out-of-order rasterization if the
1553 * bound pipeline supports it and if it's has
1554 * been disabled before starting any perfect
1555 * occlusion queries.
1556 */
1557 radeon_set_context_reg(cmd_buffer->cs,
1558 R_028A4C_PA_SC_MODE_CNTL_1,
1559 pa_sc_mode_cntl_1);
1560 }
1561 db_count_control = 0;
1562 } else {
1563 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1564 }
1565 } else {
1566 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1567 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1568
1569 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1570 db_count_control =
1571 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1572 S_028004_SAMPLE_RATE(sample_rate) |
1573 S_028004_ZPASS_ENABLE(1) |
1574 S_028004_SLICE_EVEN_ENABLE(1) |
1575 S_028004_SLICE_ODD_ENABLE(1);
1576
1577 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1578 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1579 has_perfect_queries) {
1580 /* If the bound pipeline has enabled
1581 * out-of-order rasterization, we should
1582 * disable it before starting any perfect
1583 * occlusion queries.
1584 */
1585 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1586
1587 radeon_set_context_reg(cmd_buffer->cs,
1588 R_028A4C_PA_SC_MODE_CNTL_1,
1589 pa_sc_mode_cntl_1);
1590 }
1591 } else {
1592 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1593 S_028004_SAMPLE_RATE(sample_rate);
1594 }
1595 }
1596
1597 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1598 }
1599
1600 static void
1601 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1602 {
1603 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1604
1605 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1606 radv_emit_viewport(cmd_buffer);
1607
1608 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1609 !cmd_buffer->device->physical_device->has_scissor_bug)
1610 radv_emit_scissor(cmd_buffer);
1611
1612 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1613 radv_emit_line_width(cmd_buffer);
1614
1615 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1616 radv_emit_blend_constants(cmd_buffer);
1617
1618 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1619 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1620 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1621 radv_emit_stencil(cmd_buffer);
1622
1623 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1624 radv_emit_depth_bounds(cmd_buffer);
1625
1626 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1627 radv_emit_depth_bias(cmd_buffer);
1628
1629 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1630 radv_emit_discard_rectangle(cmd_buffer);
1631
1632 cmd_buffer->state.dirty &= ~states;
1633 }
1634
1635 static void
1636 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1637 VkPipelineBindPoint bind_point)
1638 {
1639 struct radv_descriptor_state *descriptors_state =
1640 radv_get_descriptors_state(cmd_buffer, bind_point);
1641 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1642 unsigned bo_offset;
1643
1644 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1645 set->mapped_ptr,
1646 &bo_offset))
1647 return;
1648
1649 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1650 set->va += bo_offset;
1651 }
1652
1653 static void
1654 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1655 VkPipelineBindPoint bind_point)
1656 {
1657 struct radv_descriptor_state *descriptors_state =
1658 radv_get_descriptors_state(cmd_buffer, bind_point);
1659 uint32_t size = MAX_SETS * 2 * 4;
1660 uint32_t offset;
1661 void *ptr;
1662
1663 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1664 256, &offset, &ptr))
1665 return;
1666
1667 for (unsigned i = 0; i < MAX_SETS; i++) {
1668 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1669 uint64_t set_va = 0;
1670 struct radv_descriptor_set *set = descriptors_state->sets[i];
1671 if (descriptors_state->valid & (1u << i))
1672 set_va = set->va;
1673 uptr[0] = set_va & 0xffffffff;
1674 uptr[1] = set_va >> 32;
1675 }
1676
1677 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1678 va += offset;
1679
1680 if (cmd_buffer->state.pipeline) {
1681 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1682 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1683 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1684
1685 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1686 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1687 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1688
1689 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1690 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1691 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1692
1693 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1694 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1695 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1696
1697 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1698 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1699 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1700 }
1701
1702 if (cmd_buffer->state.compute_pipeline)
1703 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1704 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1705 }
1706
1707 static void
1708 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1709 VkShaderStageFlags stages)
1710 {
1711 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1712 VK_PIPELINE_BIND_POINT_COMPUTE :
1713 VK_PIPELINE_BIND_POINT_GRAPHICS;
1714 struct radv_descriptor_state *descriptors_state =
1715 radv_get_descriptors_state(cmd_buffer, bind_point);
1716
1717 if (!descriptors_state->dirty)
1718 return;
1719
1720 if (descriptors_state->push_dirty)
1721 radv_flush_push_descriptors(cmd_buffer, bind_point);
1722
1723 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1724 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1725 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1726 }
1727
1728 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1729 cmd_buffer->cs,
1730 MAX_SETS * MESA_SHADER_STAGES * 4);
1731
1732 if (cmd_buffer->state.pipeline) {
1733 radv_foreach_stage(stage, stages) {
1734 if (!cmd_buffer->state.pipeline->shaders[stage])
1735 continue;
1736
1737 radv_emit_descriptor_pointers(cmd_buffer,
1738 cmd_buffer->state.pipeline,
1739 descriptors_state, stage);
1740 }
1741 }
1742
1743 if (cmd_buffer->state.compute_pipeline &&
1744 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1745 radv_emit_descriptor_pointers(cmd_buffer,
1746 cmd_buffer->state.compute_pipeline,
1747 descriptors_state,
1748 MESA_SHADER_COMPUTE);
1749 }
1750
1751 descriptors_state->dirty = 0;
1752 descriptors_state->push_dirty = false;
1753
1754 if (unlikely(cmd_buffer->device->trace_bo))
1755 radv_save_descriptors(cmd_buffer, bind_point);
1756
1757 assert(cmd_buffer->cs->cdw <= cdw_max);
1758 }
1759
1760 static void
1761 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1762 VkShaderStageFlags stages)
1763 {
1764 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1765 ? cmd_buffer->state.compute_pipeline
1766 : cmd_buffer->state.pipeline;
1767 struct radv_pipeline_layout *layout = pipeline->layout;
1768 struct radv_shader_variant *shader, *prev_shader;
1769 unsigned offset;
1770 void *ptr;
1771 uint64_t va;
1772
1773 stages &= cmd_buffer->push_constant_stages;
1774 if (!stages ||
1775 (!layout->push_constant_size && !layout->dynamic_offset_count))
1776 return;
1777
1778 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1779 16 * layout->dynamic_offset_count,
1780 256, &offset, &ptr))
1781 return;
1782
1783 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1784 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1785 16 * layout->dynamic_offset_count);
1786
1787 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1788 va += offset;
1789
1790 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1791 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1792
1793 prev_shader = NULL;
1794 radv_foreach_stage(stage, stages) {
1795 shader = radv_get_shader(pipeline, stage);
1796
1797 /* Avoid redundantly emitting the address for merged stages. */
1798 if (shader && shader != prev_shader) {
1799 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1800 AC_UD_PUSH_CONSTANTS, va);
1801
1802 prev_shader = shader;
1803 }
1804 }
1805
1806 cmd_buffer->push_constant_stages &= ~stages;
1807 assert(cmd_buffer->cs->cdw <= cdw_max);
1808 }
1809
1810 static void
1811 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1812 bool pipeline_is_dirty)
1813 {
1814 if ((pipeline_is_dirty ||
1815 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1816 cmd_buffer->state.pipeline->vertex_elements.count &&
1817 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1818 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1819 unsigned vb_offset;
1820 void *vb_ptr;
1821 uint32_t i = 0;
1822 uint32_t count = velems->count;
1823 uint64_t va;
1824
1825 /* allocate some descriptor state for vertex buffers */
1826 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1827 &vb_offset, &vb_ptr))
1828 return;
1829
1830 for (i = 0; i < count; i++) {
1831 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1832 uint32_t offset;
1833 int vb = velems->binding[i];
1834 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1835 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1836
1837 va = radv_buffer_get_va(buffer->bo);
1838
1839 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1840 va += offset + buffer->offset;
1841 desc[0] = va;
1842 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1843 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1844 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1845 else
1846 desc[2] = buffer->size - offset;
1847 desc[3] = velems->rsrc_word3[i];
1848 }
1849
1850 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1851 va += vb_offset;
1852
1853 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1854 AC_UD_VS_VERTEX_BUFFERS, va);
1855
1856 cmd_buffer->state.vb_va = va;
1857 cmd_buffer->state.vb_size = count * 16;
1858 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1859 }
1860 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1861 }
1862
1863 static void
1864 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1865 {
1866 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1867 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1868 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1869 }
1870
1871 static void
1872 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1873 bool instanced_draw, bool indirect_draw,
1874 uint32_t draw_vertex_count)
1875 {
1876 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1877 struct radv_cmd_state *state = &cmd_buffer->state;
1878 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1879 uint32_t ia_multi_vgt_param;
1880 int32_t primitive_reset_en;
1881
1882 /* Draw state. */
1883 ia_multi_vgt_param =
1884 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1885 indirect_draw, draw_vertex_count);
1886
1887 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1888 if (info->chip_class >= GFX9) {
1889 radeon_set_uconfig_reg_idx(cs,
1890 R_030960_IA_MULTI_VGT_PARAM,
1891 4, ia_multi_vgt_param);
1892 } else if (info->chip_class >= CIK) {
1893 radeon_set_context_reg_idx(cs,
1894 R_028AA8_IA_MULTI_VGT_PARAM,
1895 1, ia_multi_vgt_param);
1896 } else {
1897 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1898 ia_multi_vgt_param);
1899 }
1900 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1901 }
1902
1903 /* Primitive restart. */
1904 primitive_reset_en =
1905 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1906
1907 if (primitive_reset_en != state->last_primitive_reset_en) {
1908 state->last_primitive_reset_en = primitive_reset_en;
1909 if (info->chip_class >= GFX9) {
1910 radeon_set_uconfig_reg(cs,
1911 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1912 primitive_reset_en);
1913 } else {
1914 radeon_set_context_reg(cs,
1915 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1916 primitive_reset_en);
1917 }
1918 }
1919
1920 if (primitive_reset_en) {
1921 uint32_t primitive_reset_index =
1922 state->index_type ? 0xffffffffu : 0xffffu;
1923
1924 if (primitive_reset_index != state->last_primitive_reset_index) {
1925 radeon_set_context_reg(cs,
1926 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1927 primitive_reset_index);
1928 state->last_primitive_reset_index = primitive_reset_index;
1929 }
1930 }
1931 }
1932
1933 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1934 VkPipelineStageFlags src_stage_mask)
1935 {
1936 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1937 VK_PIPELINE_STAGE_TRANSFER_BIT |
1938 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1939 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1940 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1941 }
1942
1943 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1944 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1945 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1946 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1947 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1948 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1949 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1950 VK_PIPELINE_STAGE_TRANSFER_BIT |
1951 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1952 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1953 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1954 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1955 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1956 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1957 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1958 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1959 }
1960 }
1961
1962 static enum radv_cmd_flush_bits
1963 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1964 VkAccessFlags src_flags)
1965 {
1966 enum radv_cmd_flush_bits flush_bits = 0;
1967 uint32_t b;
1968 for_each_bit(b, src_flags) {
1969 switch ((VkAccessFlagBits)(1 << b)) {
1970 case VK_ACCESS_SHADER_WRITE_BIT:
1971 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1972 break;
1973 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1974 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1975 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1976 break;
1977 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1978 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1979 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1980 break;
1981 case VK_ACCESS_TRANSFER_WRITE_BIT:
1982 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1983 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1984 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1985 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1986 RADV_CMD_FLAG_INV_GLOBAL_L2;
1987 break;
1988 default:
1989 break;
1990 }
1991 }
1992 return flush_bits;
1993 }
1994
1995 static enum radv_cmd_flush_bits
1996 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1997 VkAccessFlags dst_flags,
1998 struct radv_image *image)
1999 {
2000 enum radv_cmd_flush_bits flush_bits = 0;
2001 uint32_t b;
2002 for_each_bit(b, dst_flags) {
2003 switch ((VkAccessFlagBits)(1 << b)) {
2004 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2005 case VK_ACCESS_INDEX_READ_BIT:
2006 break;
2007 case VK_ACCESS_UNIFORM_READ_BIT:
2008 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2009 break;
2010 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2011 case VK_ACCESS_SHADER_READ_BIT:
2012 case VK_ACCESS_TRANSFER_READ_BIT:
2013 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2014 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2015 RADV_CMD_FLAG_INV_GLOBAL_L2;
2016 break;
2017 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2018 /* TODO: change to image && when the image gets passed
2019 * through from the subpass. */
2020 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2021 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2022 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2023 break;
2024 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2025 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2026 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2027 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2028 break;
2029 default:
2030 break;
2031 }
2032 }
2033 return flush_bits;
2034 }
2035
2036 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2037 {
2038 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2039 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2040 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2041 NULL);
2042 }
2043
2044 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2045 VkAttachmentReference att)
2046 {
2047 unsigned idx = att.attachment;
2048 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2049 VkImageSubresourceRange range;
2050 range.aspectMask = 0;
2051 range.baseMipLevel = view->base_mip;
2052 range.levelCount = 1;
2053 range.baseArrayLayer = view->base_layer;
2054 range.layerCount = cmd_buffer->state.framebuffer->layers;
2055
2056 radv_handle_image_transition(cmd_buffer,
2057 view->image,
2058 cmd_buffer->state.attachments[idx].current_layout,
2059 att.layout, 0, 0, &range,
2060 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2061
2062 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2063
2064
2065 }
2066
2067 void
2068 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2069 const struct radv_subpass *subpass, bool transitions)
2070 {
2071 if (transitions) {
2072 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2073
2074 for (unsigned i = 0; i < subpass->color_count; ++i) {
2075 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2076 radv_handle_subpass_image_transition(cmd_buffer,
2077 subpass->color_attachments[i]);
2078 }
2079
2080 for (unsigned i = 0; i < subpass->input_count; ++i) {
2081 radv_handle_subpass_image_transition(cmd_buffer,
2082 subpass->input_attachments[i]);
2083 }
2084
2085 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2086 radv_handle_subpass_image_transition(cmd_buffer,
2087 subpass->depth_stencil_attachment);
2088 }
2089 }
2090
2091 cmd_buffer->state.subpass = subpass;
2092
2093 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2094 }
2095
2096 static VkResult
2097 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2098 struct radv_render_pass *pass,
2099 const VkRenderPassBeginInfo *info)
2100 {
2101 struct radv_cmd_state *state = &cmd_buffer->state;
2102
2103 if (pass->attachment_count == 0) {
2104 state->attachments = NULL;
2105 return VK_SUCCESS;
2106 }
2107
2108 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2109 pass->attachment_count *
2110 sizeof(state->attachments[0]),
2111 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2112 if (state->attachments == NULL) {
2113 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2114 return cmd_buffer->record_result;
2115 }
2116
2117 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2118 struct radv_render_pass_attachment *att = &pass->attachments[i];
2119 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2120 VkImageAspectFlags clear_aspects = 0;
2121
2122 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2123 /* color attachment */
2124 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2125 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2126 }
2127 } else {
2128 /* depthstencil attachment */
2129 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2130 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2131 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2132 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2133 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2134 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2135 }
2136 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2137 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2138 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2139 }
2140 }
2141
2142 state->attachments[i].pending_clear_aspects = clear_aspects;
2143 state->attachments[i].cleared_views = 0;
2144 if (clear_aspects && info) {
2145 assert(info->clearValueCount > i);
2146 state->attachments[i].clear_value = info->pClearValues[i];
2147 }
2148
2149 state->attachments[i].current_layout = att->initial_layout;
2150 }
2151
2152 return VK_SUCCESS;
2153 }
2154
2155 VkResult radv_AllocateCommandBuffers(
2156 VkDevice _device,
2157 const VkCommandBufferAllocateInfo *pAllocateInfo,
2158 VkCommandBuffer *pCommandBuffers)
2159 {
2160 RADV_FROM_HANDLE(radv_device, device, _device);
2161 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2162
2163 VkResult result = VK_SUCCESS;
2164 uint32_t i;
2165
2166 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2167
2168 if (!list_empty(&pool->free_cmd_buffers)) {
2169 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2170
2171 list_del(&cmd_buffer->pool_link);
2172 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2173
2174 result = radv_reset_cmd_buffer(cmd_buffer);
2175 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2176 cmd_buffer->level = pAllocateInfo->level;
2177
2178 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2179 } else {
2180 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2181 &pCommandBuffers[i]);
2182 }
2183 if (result != VK_SUCCESS)
2184 break;
2185 }
2186
2187 if (result != VK_SUCCESS) {
2188 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2189 i, pCommandBuffers);
2190
2191 /* From the Vulkan 1.0.66 spec:
2192 *
2193 * "vkAllocateCommandBuffers can be used to create multiple
2194 * command buffers. If the creation of any of those command
2195 * buffers fails, the implementation must destroy all
2196 * successfully created command buffer objects from this
2197 * command, set all entries of the pCommandBuffers array to
2198 * NULL and return the error."
2199 */
2200 memset(pCommandBuffers, 0,
2201 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2202 }
2203
2204 return result;
2205 }
2206
2207 void radv_FreeCommandBuffers(
2208 VkDevice device,
2209 VkCommandPool commandPool,
2210 uint32_t commandBufferCount,
2211 const VkCommandBuffer *pCommandBuffers)
2212 {
2213 for (uint32_t i = 0; i < commandBufferCount; i++) {
2214 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2215
2216 if (cmd_buffer) {
2217 if (cmd_buffer->pool) {
2218 list_del(&cmd_buffer->pool_link);
2219 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2220 } else
2221 radv_cmd_buffer_destroy(cmd_buffer);
2222
2223 }
2224 }
2225 }
2226
2227 VkResult radv_ResetCommandBuffer(
2228 VkCommandBuffer commandBuffer,
2229 VkCommandBufferResetFlags flags)
2230 {
2231 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2232 return radv_reset_cmd_buffer(cmd_buffer);
2233 }
2234
2235 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2236 {
2237 struct radv_device *device = cmd_buffer->device;
2238 if (device->gfx_init) {
2239 uint64_t va = radv_buffer_get_va(device->gfx_init);
2240 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2241 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2242 radeon_emit(cmd_buffer->cs, va);
2243 radeon_emit(cmd_buffer->cs, va >> 32);
2244 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2245 } else
2246 si_init_config(cmd_buffer);
2247 }
2248
2249 VkResult radv_BeginCommandBuffer(
2250 VkCommandBuffer commandBuffer,
2251 const VkCommandBufferBeginInfo *pBeginInfo)
2252 {
2253 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2254 VkResult result = VK_SUCCESS;
2255
2256 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2257 /* If the command buffer has already been resetted with
2258 * vkResetCommandBuffer, no need to do it again.
2259 */
2260 result = radv_reset_cmd_buffer(cmd_buffer);
2261 if (result != VK_SUCCESS)
2262 return result;
2263 }
2264
2265 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2266 cmd_buffer->state.last_primitive_reset_en = -1;
2267 cmd_buffer->state.last_index_type = -1;
2268 cmd_buffer->state.last_num_instances = -1;
2269 cmd_buffer->state.last_vertex_offset = -1;
2270 cmd_buffer->state.last_first_instance = -1;
2271 cmd_buffer->usage_flags = pBeginInfo->flags;
2272
2273 /* setup initial configuration into command buffer */
2274 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2275 switch (cmd_buffer->queue_family_index) {
2276 case RADV_QUEUE_GENERAL:
2277 emit_gfx_buffer_state(cmd_buffer);
2278 break;
2279 case RADV_QUEUE_COMPUTE:
2280 si_init_compute(cmd_buffer);
2281 break;
2282 case RADV_QUEUE_TRANSFER:
2283 default:
2284 break;
2285 }
2286 }
2287
2288 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2289 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2290 assert(pBeginInfo->pInheritanceInfo);
2291 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2292 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2293
2294 struct radv_subpass *subpass =
2295 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2296
2297 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2298 if (result != VK_SUCCESS)
2299 return result;
2300
2301 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2302 }
2303
2304 if (unlikely(cmd_buffer->device->trace_bo))
2305 radv_cmd_buffer_trace_emit(cmd_buffer);
2306
2307 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2308
2309 return result;
2310 }
2311
2312 void radv_CmdBindVertexBuffers(
2313 VkCommandBuffer commandBuffer,
2314 uint32_t firstBinding,
2315 uint32_t bindingCount,
2316 const VkBuffer* pBuffers,
2317 const VkDeviceSize* pOffsets)
2318 {
2319 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2320 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2321 bool changed = false;
2322
2323 /* We have to defer setting up vertex buffer since we need the buffer
2324 * stride from the pipeline. */
2325
2326 assert(firstBinding + bindingCount <= MAX_VBS);
2327 for (uint32_t i = 0; i < bindingCount; i++) {
2328 uint32_t idx = firstBinding + i;
2329
2330 if (!changed &&
2331 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2332 vb[idx].offset != pOffsets[i])) {
2333 changed = true;
2334 }
2335
2336 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2337 vb[idx].offset = pOffsets[i];
2338
2339 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2340 vb[idx].buffer->bo, 8);
2341 }
2342
2343 if (!changed) {
2344 /* No state changes. */
2345 return;
2346 }
2347
2348 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2349 }
2350
2351 void radv_CmdBindIndexBuffer(
2352 VkCommandBuffer commandBuffer,
2353 VkBuffer buffer,
2354 VkDeviceSize offset,
2355 VkIndexType indexType)
2356 {
2357 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2358 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2359
2360 if (cmd_buffer->state.index_buffer == index_buffer &&
2361 cmd_buffer->state.index_offset == offset &&
2362 cmd_buffer->state.index_type == indexType) {
2363 /* No state changes. */
2364 return;
2365 }
2366
2367 cmd_buffer->state.index_buffer = index_buffer;
2368 cmd_buffer->state.index_offset = offset;
2369 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2370 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2371 cmd_buffer->state.index_va += index_buffer->offset + offset;
2372
2373 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2374 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2375 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2376 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2377 }
2378
2379
2380 static void
2381 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2382 VkPipelineBindPoint bind_point,
2383 struct radv_descriptor_set *set, unsigned idx)
2384 {
2385 struct radeon_winsys *ws = cmd_buffer->device->ws;
2386
2387 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2388 if (!set)
2389 return;
2390
2391 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2392
2393 if (!cmd_buffer->device->use_global_bo_list) {
2394 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2395 if (set->descriptors[j])
2396 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2397 }
2398
2399 if(set->bo)
2400 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2401 }
2402
2403 void radv_CmdBindDescriptorSets(
2404 VkCommandBuffer commandBuffer,
2405 VkPipelineBindPoint pipelineBindPoint,
2406 VkPipelineLayout _layout,
2407 uint32_t firstSet,
2408 uint32_t descriptorSetCount,
2409 const VkDescriptorSet* pDescriptorSets,
2410 uint32_t dynamicOffsetCount,
2411 const uint32_t* pDynamicOffsets)
2412 {
2413 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2414 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2415 unsigned dyn_idx = 0;
2416
2417 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2418
2419 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2420 unsigned idx = i + firstSet;
2421 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2422 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2423
2424 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2425 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2426 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2427 assert(dyn_idx < dynamicOffsetCount);
2428
2429 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2430 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2431 dst[0] = va;
2432 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2433 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2434 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2435 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2436 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2437 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2438 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2439 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2440 cmd_buffer->push_constant_stages |=
2441 set->layout->dynamic_shader_stages;
2442 }
2443 }
2444 }
2445
2446 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2447 struct radv_descriptor_set *set,
2448 struct radv_descriptor_set_layout *layout,
2449 VkPipelineBindPoint bind_point)
2450 {
2451 struct radv_descriptor_state *descriptors_state =
2452 radv_get_descriptors_state(cmd_buffer, bind_point);
2453 set->size = layout->size;
2454 set->layout = layout;
2455
2456 if (descriptors_state->push_set.capacity < set->size) {
2457 size_t new_size = MAX2(set->size, 1024);
2458 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2459 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2460
2461 free(set->mapped_ptr);
2462 set->mapped_ptr = malloc(new_size);
2463
2464 if (!set->mapped_ptr) {
2465 descriptors_state->push_set.capacity = 0;
2466 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2467 return false;
2468 }
2469
2470 descriptors_state->push_set.capacity = new_size;
2471 }
2472
2473 return true;
2474 }
2475
2476 void radv_meta_push_descriptor_set(
2477 struct radv_cmd_buffer* cmd_buffer,
2478 VkPipelineBindPoint pipelineBindPoint,
2479 VkPipelineLayout _layout,
2480 uint32_t set,
2481 uint32_t descriptorWriteCount,
2482 const VkWriteDescriptorSet* pDescriptorWrites)
2483 {
2484 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2485 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2486 unsigned bo_offset;
2487
2488 assert(set == 0);
2489 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2490
2491 push_set->size = layout->set[set].layout->size;
2492 push_set->layout = layout->set[set].layout;
2493
2494 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2495 &bo_offset,
2496 (void**) &push_set->mapped_ptr))
2497 return;
2498
2499 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2500 push_set->va += bo_offset;
2501
2502 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2503 radv_descriptor_set_to_handle(push_set),
2504 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2505
2506 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2507 }
2508
2509 void radv_CmdPushDescriptorSetKHR(
2510 VkCommandBuffer commandBuffer,
2511 VkPipelineBindPoint pipelineBindPoint,
2512 VkPipelineLayout _layout,
2513 uint32_t set,
2514 uint32_t descriptorWriteCount,
2515 const VkWriteDescriptorSet* pDescriptorWrites)
2516 {
2517 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2518 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2519 struct radv_descriptor_state *descriptors_state =
2520 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2521 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2522
2523 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2524
2525 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2526 layout->set[set].layout,
2527 pipelineBindPoint))
2528 return;
2529
2530 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2531 radv_descriptor_set_to_handle(push_set),
2532 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2533
2534 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2535 descriptors_state->push_dirty = true;
2536 }
2537
2538 void radv_CmdPushDescriptorSetWithTemplateKHR(
2539 VkCommandBuffer commandBuffer,
2540 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2541 VkPipelineLayout _layout,
2542 uint32_t set,
2543 const void* pData)
2544 {
2545 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2546 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2547 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2548 struct radv_descriptor_state *descriptors_state =
2549 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2550 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2551
2552 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2553
2554 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2555 layout->set[set].layout,
2556 templ->bind_point))
2557 return;
2558
2559 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2560 descriptorUpdateTemplate, pData);
2561
2562 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2563 descriptors_state->push_dirty = true;
2564 }
2565
2566 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2567 VkPipelineLayout layout,
2568 VkShaderStageFlags stageFlags,
2569 uint32_t offset,
2570 uint32_t size,
2571 const void* pValues)
2572 {
2573 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2574 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2575 cmd_buffer->push_constant_stages |= stageFlags;
2576 }
2577
2578 VkResult radv_EndCommandBuffer(
2579 VkCommandBuffer commandBuffer)
2580 {
2581 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2582
2583 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2584 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2585 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2586 si_emit_cache_flush(cmd_buffer);
2587 }
2588
2589 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2590
2591 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2592 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2593
2594 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2595
2596 return cmd_buffer->record_result;
2597 }
2598
2599 static void
2600 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2601 {
2602 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2603
2604 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2605 return;
2606
2607 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2608
2609 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2610 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2611
2612 cmd_buffer->compute_scratch_size_needed =
2613 MAX2(cmd_buffer->compute_scratch_size_needed,
2614 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2615
2616 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2617 pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
2618
2619 if (unlikely(cmd_buffer->device->trace_bo))
2620 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2621 }
2622
2623 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2624 VkPipelineBindPoint bind_point)
2625 {
2626 struct radv_descriptor_state *descriptors_state =
2627 radv_get_descriptors_state(cmd_buffer, bind_point);
2628
2629 descriptors_state->dirty |= descriptors_state->valid;
2630 }
2631
2632 void radv_CmdBindPipeline(
2633 VkCommandBuffer commandBuffer,
2634 VkPipelineBindPoint pipelineBindPoint,
2635 VkPipeline _pipeline)
2636 {
2637 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2638 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2639
2640 switch (pipelineBindPoint) {
2641 case VK_PIPELINE_BIND_POINT_COMPUTE:
2642 if (cmd_buffer->state.compute_pipeline == pipeline)
2643 return;
2644 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2645
2646 cmd_buffer->state.compute_pipeline = pipeline;
2647 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2648 break;
2649 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2650 if (cmd_buffer->state.pipeline == pipeline)
2651 return;
2652 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2653
2654 cmd_buffer->state.pipeline = pipeline;
2655 if (!pipeline)
2656 break;
2657
2658 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2659 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2660
2661 /* the new vertex shader might not have the same user regs */
2662 cmd_buffer->state.last_first_instance = -1;
2663 cmd_buffer->state.last_vertex_offset = -1;
2664
2665 /* Prefetch all pipeline shaders at first draw time. */
2666 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2667
2668 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2669
2670 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2671 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2672 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2673 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2674
2675 if (radv_pipeline_has_tess(pipeline))
2676 cmd_buffer->tess_rings_needed = true;
2677
2678 if (radv_pipeline_has_gs(pipeline)) {
2679 struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2680 AC_UD_SCRATCH_RING_OFFSETS);
2681 if (cmd_buffer->ring_offsets_idx == -1)
2682 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2683 else if (loc->sgpr_idx != -1)
2684 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2685 }
2686 break;
2687 default:
2688 assert(!"invalid bind point");
2689 break;
2690 }
2691 }
2692
2693 void radv_CmdSetViewport(
2694 VkCommandBuffer commandBuffer,
2695 uint32_t firstViewport,
2696 uint32_t viewportCount,
2697 const VkViewport* pViewports)
2698 {
2699 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2700 struct radv_cmd_state *state = &cmd_buffer->state;
2701 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2702
2703 assert(firstViewport < MAX_VIEWPORTS);
2704 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2705
2706 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2707 viewportCount * sizeof(*pViewports));
2708
2709 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2710 }
2711
2712 void radv_CmdSetScissor(
2713 VkCommandBuffer commandBuffer,
2714 uint32_t firstScissor,
2715 uint32_t scissorCount,
2716 const VkRect2D* pScissors)
2717 {
2718 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2719 struct radv_cmd_state *state = &cmd_buffer->state;
2720 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2721
2722 assert(firstScissor < MAX_SCISSORS);
2723 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2724
2725 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2726 scissorCount * sizeof(*pScissors));
2727
2728 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2729 }
2730
2731 void radv_CmdSetLineWidth(
2732 VkCommandBuffer commandBuffer,
2733 float lineWidth)
2734 {
2735 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2736 cmd_buffer->state.dynamic.line_width = lineWidth;
2737 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2738 }
2739
2740 void radv_CmdSetDepthBias(
2741 VkCommandBuffer commandBuffer,
2742 float depthBiasConstantFactor,
2743 float depthBiasClamp,
2744 float depthBiasSlopeFactor)
2745 {
2746 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2747
2748 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2749 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2750 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2751
2752 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2753 }
2754
2755 void radv_CmdSetBlendConstants(
2756 VkCommandBuffer commandBuffer,
2757 const float blendConstants[4])
2758 {
2759 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2760
2761 memcpy(cmd_buffer->state.dynamic.blend_constants,
2762 blendConstants, sizeof(float) * 4);
2763
2764 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2765 }
2766
2767 void radv_CmdSetDepthBounds(
2768 VkCommandBuffer commandBuffer,
2769 float minDepthBounds,
2770 float maxDepthBounds)
2771 {
2772 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2773
2774 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2775 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2776
2777 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2778 }
2779
2780 void radv_CmdSetStencilCompareMask(
2781 VkCommandBuffer commandBuffer,
2782 VkStencilFaceFlags faceMask,
2783 uint32_t compareMask)
2784 {
2785 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2786
2787 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2788 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2789 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2790 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2791
2792 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2793 }
2794
2795 void radv_CmdSetStencilWriteMask(
2796 VkCommandBuffer commandBuffer,
2797 VkStencilFaceFlags faceMask,
2798 uint32_t writeMask)
2799 {
2800 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2801
2802 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2803 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2804 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2805 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2806
2807 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2808 }
2809
2810 void radv_CmdSetStencilReference(
2811 VkCommandBuffer commandBuffer,
2812 VkStencilFaceFlags faceMask,
2813 uint32_t reference)
2814 {
2815 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2816
2817 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2818 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2819 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2820 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2821
2822 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2823 }
2824
2825 void radv_CmdSetDiscardRectangleEXT(
2826 VkCommandBuffer commandBuffer,
2827 uint32_t firstDiscardRectangle,
2828 uint32_t discardRectangleCount,
2829 const VkRect2D* pDiscardRectangles)
2830 {
2831 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2832 struct radv_cmd_state *state = &cmd_buffer->state;
2833 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2834
2835 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2836 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2837
2838 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2839 pDiscardRectangles, discardRectangleCount);
2840
2841 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2842 }
2843
2844 void radv_CmdExecuteCommands(
2845 VkCommandBuffer commandBuffer,
2846 uint32_t commandBufferCount,
2847 const VkCommandBuffer* pCmdBuffers)
2848 {
2849 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2850
2851 assert(commandBufferCount > 0);
2852
2853 /* Emit pending flushes on primary prior to executing secondary */
2854 si_emit_cache_flush(primary);
2855
2856 for (uint32_t i = 0; i < commandBufferCount; i++) {
2857 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2858
2859 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2860 secondary->scratch_size_needed);
2861 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2862 secondary->compute_scratch_size_needed);
2863
2864 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2865 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2866 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2867 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2868 if (secondary->tess_rings_needed)
2869 primary->tess_rings_needed = true;
2870 if (secondary->sample_positions_needed)
2871 primary->sample_positions_needed = true;
2872
2873 if (secondary->ring_offsets_idx != -1) {
2874 if (primary->ring_offsets_idx == -1)
2875 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2876 else
2877 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2878 }
2879 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2880
2881
2882 /* When the secondary command buffer is compute only we don't
2883 * need to re-emit the current graphics pipeline.
2884 */
2885 if (secondary->state.emitted_pipeline) {
2886 primary->state.emitted_pipeline =
2887 secondary->state.emitted_pipeline;
2888 }
2889
2890 /* When the secondary command buffer is graphics only we don't
2891 * need to re-emit the current compute pipeline.
2892 */
2893 if (secondary->state.emitted_compute_pipeline) {
2894 primary->state.emitted_compute_pipeline =
2895 secondary->state.emitted_compute_pipeline;
2896 }
2897
2898 /* Only re-emit the draw packets when needed. */
2899 if (secondary->state.last_primitive_reset_en != -1) {
2900 primary->state.last_primitive_reset_en =
2901 secondary->state.last_primitive_reset_en;
2902 }
2903
2904 if (secondary->state.last_primitive_reset_index) {
2905 primary->state.last_primitive_reset_index =
2906 secondary->state.last_primitive_reset_index;
2907 }
2908
2909 if (secondary->state.last_ia_multi_vgt_param) {
2910 primary->state.last_ia_multi_vgt_param =
2911 secondary->state.last_ia_multi_vgt_param;
2912 }
2913
2914 primary->state.last_first_instance = secondary->state.last_first_instance;
2915 primary->state.last_num_instances = secondary->state.last_num_instances;
2916 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2917
2918 if (secondary->state.last_index_type != -1) {
2919 primary->state.last_index_type =
2920 secondary->state.last_index_type;
2921 }
2922 }
2923
2924 /* After executing commands from secondary buffers we have to dirty
2925 * some states.
2926 */
2927 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2928 RADV_CMD_DIRTY_INDEX_BUFFER |
2929 RADV_CMD_DIRTY_DYNAMIC_ALL;
2930 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2931 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2932 }
2933
2934 VkResult radv_CreateCommandPool(
2935 VkDevice _device,
2936 const VkCommandPoolCreateInfo* pCreateInfo,
2937 const VkAllocationCallbacks* pAllocator,
2938 VkCommandPool* pCmdPool)
2939 {
2940 RADV_FROM_HANDLE(radv_device, device, _device);
2941 struct radv_cmd_pool *pool;
2942
2943 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2944 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2945 if (pool == NULL)
2946 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2947
2948 if (pAllocator)
2949 pool->alloc = *pAllocator;
2950 else
2951 pool->alloc = device->alloc;
2952
2953 list_inithead(&pool->cmd_buffers);
2954 list_inithead(&pool->free_cmd_buffers);
2955
2956 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2957
2958 *pCmdPool = radv_cmd_pool_to_handle(pool);
2959
2960 return VK_SUCCESS;
2961
2962 }
2963
2964 void radv_DestroyCommandPool(
2965 VkDevice _device,
2966 VkCommandPool commandPool,
2967 const VkAllocationCallbacks* pAllocator)
2968 {
2969 RADV_FROM_HANDLE(radv_device, device, _device);
2970 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2971
2972 if (!pool)
2973 return;
2974
2975 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2976 &pool->cmd_buffers, pool_link) {
2977 radv_cmd_buffer_destroy(cmd_buffer);
2978 }
2979
2980 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2981 &pool->free_cmd_buffers, pool_link) {
2982 radv_cmd_buffer_destroy(cmd_buffer);
2983 }
2984
2985 vk_free2(&device->alloc, pAllocator, pool);
2986 }
2987
2988 VkResult radv_ResetCommandPool(
2989 VkDevice device,
2990 VkCommandPool commandPool,
2991 VkCommandPoolResetFlags flags)
2992 {
2993 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2994 VkResult result;
2995
2996 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2997 &pool->cmd_buffers, pool_link) {
2998 result = radv_reset_cmd_buffer(cmd_buffer);
2999 if (result != VK_SUCCESS)
3000 return result;
3001 }
3002
3003 return VK_SUCCESS;
3004 }
3005
3006 void radv_TrimCommandPool(
3007 VkDevice device,
3008 VkCommandPool commandPool,
3009 VkCommandPoolTrimFlagsKHR flags)
3010 {
3011 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3012
3013 if (!pool)
3014 return;
3015
3016 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3017 &pool->free_cmd_buffers, pool_link) {
3018 radv_cmd_buffer_destroy(cmd_buffer);
3019 }
3020 }
3021
3022 void radv_CmdBeginRenderPass(
3023 VkCommandBuffer commandBuffer,
3024 const VkRenderPassBeginInfo* pRenderPassBegin,
3025 VkSubpassContents contents)
3026 {
3027 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3028 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3029 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3030
3031 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3032 cmd_buffer->cs, 2048);
3033 MAYBE_UNUSED VkResult result;
3034
3035 cmd_buffer->state.framebuffer = framebuffer;
3036 cmd_buffer->state.pass = pass;
3037 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3038
3039 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3040 if (result != VK_SUCCESS)
3041 return;
3042
3043 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3044 assert(cmd_buffer->cs->cdw <= cdw_max);
3045
3046 radv_cmd_buffer_clear_subpass(cmd_buffer);
3047 }
3048
3049 void radv_CmdNextSubpass(
3050 VkCommandBuffer commandBuffer,
3051 VkSubpassContents contents)
3052 {
3053 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3054
3055 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3056
3057 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3058 2048);
3059
3060 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3061 radv_cmd_buffer_clear_subpass(cmd_buffer);
3062 }
3063
3064 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3065 {
3066 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3067 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3068 if (!pipeline->shaders[stage])
3069 continue;
3070 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3071 if (loc->sgpr_idx == -1)
3072 continue;
3073 uint32_t base_reg = pipeline->user_data_0[stage];
3074 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3075
3076 }
3077 if (pipeline->gs_copy_shader) {
3078 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3079 if (loc->sgpr_idx != -1) {
3080 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3081 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3082 }
3083 }
3084 }
3085
3086 static void
3087 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3088 uint32_t vertex_count)
3089 {
3090 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3091 radeon_emit(cmd_buffer->cs, vertex_count);
3092 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3093 S_0287F0_USE_OPAQUE(0));
3094 }
3095
3096 static void
3097 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3098 uint64_t index_va,
3099 uint32_t index_count)
3100 {
3101 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3102 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3103 radeon_emit(cmd_buffer->cs, index_va);
3104 radeon_emit(cmd_buffer->cs, index_va >> 32);
3105 radeon_emit(cmd_buffer->cs, index_count);
3106 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3107 }
3108
3109 static void
3110 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3111 bool indexed,
3112 uint32_t draw_count,
3113 uint64_t count_va,
3114 uint32_t stride)
3115 {
3116 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3117 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3118 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3119 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3120 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3121 assert(base_reg);
3122
3123 /* just reset draw state for vertex data */
3124 cmd_buffer->state.last_first_instance = -1;
3125 cmd_buffer->state.last_num_instances = -1;
3126 cmd_buffer->state.last_vertex_offset = -1;
3127
3128 if (draw_count == 1 && !count_va && !draw_id_enable) {
3129 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3130 PKT3_DRAW_INDIRECT, 3, false));
3131 radeon_emit(cs, 0);
3132 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3133 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3134 radeon_emit(cs, di_src_sel);
3135 } else {
3136 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3137 PKT3_DRAW_INDIRECT_MULTI,
3138 8, false));
3139 radeon_emit(cs, 0);
3140 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3141 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3142 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3143 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3144 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3145 radeon_emit(cs, draw_count); /* count */
3146 radeon_emit(cs, count_va); /* count_addr */
3147 radeon_emit(cs, count_va >> 32);
3148 radeon_emit(cs, stride); /* stride */
3149 radeon_emit(cs, di_src_sel);
3150 }
3151 }
3152
3153 struct radv_draw_info {
3154 /**
3155 * Number of vertices.
3156 */
3157 uint32_t count;
3158
3159 /**
3160 * Index of the first vertex.
3161 */
3162 int32_t vertex_offset;
3163
3164 /**
3165 * First instance id.
3166 */
3167 uint32_t first_instance;
3168
3169 /**
3170 * Number of instances.
3171 */
3172 uint32_t instance_count;
3173
3174 /**
3175 * First index (indexed draws only).
3176 */
3177 uint32_t first_index;
3178
3179 /**
3180 * Whether it's an indexed draw.
3181 */
3182 bool indexed;
3183
3184 /**
3185 * Indirect draw parameters resource.
3186 */
3187 struct radv_buffer *indirect;
3188 uint64_t indirect_offset;
3189 uint32_t stride;
3190
3191 /**
3192 * Draw count parameters resource.
3193 */
3194 struct radv_buffer *count_buffer;
3195 uint64_t count_buffer_offset;
3196 };
3197
3198 static void
3199 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3200 const struct radv_draw_info *info)
3201 {
3202 struct radv_cmd_state *state = &cmd_buffer->state;
3203 struct radeon_winsys *ws = cmd_buffer->device->ws;
3204 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3205
3206 if (info->indirect) {
3207 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3208 uint64_t count_va = 0;
3209
3210 va += info->indirect->offset + info->indirect_offset;
3211
3212 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3213
3214 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3215 radeon_emit(cs, 1);
3216 radeon_emit(cs, va);
3217 radeon_emit(cs, va >> 32);
3218
3219 if (info->count_buffer) {
3220 count_va = radv_buffer_get_va(info->count_buffer->bo);
3221 count_va += info->count_buffer->offset +
3222 info->count_buffer_offset;
3223
3224 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3225 }
3226
3227 if (!state->subpass->view_mask) {
3228 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3229 info->indexed,
3230 info->count,
3231 count_va,
3232 info->stride);
3233 } else {
3234 unsigned i;
3235 for_each_bit(i, state->subpass->view_mask) {
3236 radv_emit_view_index(cmd_buffer, i);
3237
3238 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3239 info->indexed,
3240 info->count,
3241 count_va,
3242 info->stride);
3243 }
3244 }
3245 } else {
3246 assert(state->pipeline->graphics.vtx_base_sgpr);
3247
3248 if (info->vertex_offset != state->last_vertex_offset ||
3249 info->first_instance != state->last_first_instance) {
3250 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3251 state->pipeline->graphics.vtx_emit_num);
3252
3253 radeon_emit(cs, info->vertex_offset);
3254 radeon_emit(cs, info->first_instance);
3255 if (state->pipeline->graphics.vtx_emit_num == 3)
3256 radeon_emit(cs, 0);
3257 state->last_first_instance = info->first_instance;
3258 state->last_vertex_offset = info->vertex_offset;
3259 }
3260
3261 if (state->last_num_instances != info->instance_count) {
3262 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3263 radeon_emit(cs, info->instance_count);
3264 state->last_num_instances = info->instance_count;
3265 }
3266
3267 if (info->indexed) {
3268 int index_size = state->index_type ? 4 : 2;
3269 uint64_t index_va;
3270
3271 index_va = state->index_va;
3272 index_va += info->first_index * index_size;
3273
3274 if (!state->subpass->view_mask) {
3275 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3276 index_va,
3277 info->count);
3278 } else {
3279 unsigned i;
3280 for_each_bit(i, state->subpass->view_mask) {
3281 radv_emit_view_index(cmd_buffer, i);
3282
3283 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3284 index_va,
3285 info->count);
3286 }
3287 }
3288 } else {
3289 if (!state->subpass->view_mask) {
3290 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3291 } else {
3292 unsigned i;
3293 for_each_bit(i, state->subpass->view_mask) {
3294 radv_emit_view_index(cmd_buffer, i);
3295
3296 radv_cs_emit_draw_packet(cmd_buffer,
3297 info->count);
3298 }
3299 }
3300 }
3301 }
3302 }
3303
3304 /*
3305 * Vega and raven have a bug which triggers if there are multiple context
3306 * register contexts active at the same time with different scissor values.
3307 *
3308 * There are two possible workarounds:
3309 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3310 * there is only ever 1 active set of scissor values at the same time.
3311 *
3312 * 2) Whenever the hardware switches contexts we have to set the scissor
3313 * registers again even if it is a noop. That way the new context gets
3314 * the correct scissor values.
3315 *
3316 * This implements option 2. radv_need_late_scissor_emission needs to
3317 * return true on affected HW if radv_emit_all_graphics_states sets
3318 * any context registers.
3319 */
3320 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3321 bool indexed_draw)
3322 {
3323 struct radv_cmd_state *state = &cmd_buffer->state;
3324
3325 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3326 return false;
3327
3328 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3329
3330 /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3331 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_VERTEX_BUFFER | RADV_CMD_DIRTY_PIPELINE);
3332
3333 /* Assume all state changes except these two can imply context rolls. */
3334 if (cmd_buffer->state.dirty & used_states)
3335 return true;
3336
3337 if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3338 return true;
3339
3340 if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3341 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3342 return true;
3343
3344 return false;
3345 }
3346
3347 static void
3348 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3349 const struct radv_draw_info *info)
3350 {
3351 bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3352
3353 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3354 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3355 radv_emit_rbplus_state(cmd_buffer);
3356
3357 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3358 radv_emit_graphics_pipeline(cmd_buffer);
3359
3360 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3361 radv_emit_framebuffer_state(cmd_buffer);
3362
3363 if (info->indexed) {
3364 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3365 radv_emit_index_buffer(cmd_buffer);
3366 } else {
3367 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3368 * so the state must be re-emitted before the next indexed
3369 * draw.
3370 */
3371 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3372 cmd_buffer->state.last_index_type = -1;
3373 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3374 }
3375 }
3376
3377 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3378
3379 radv_emit_draw_registers(cmd_buffer, info->indexed,
3380 info->instance_count > 1, info->indirect,
3381 info->indirect ? 0 : info->count);
3382
3383 if (late_scissor_emission)
3384 radv_emit_scissor(cmd_buffer);
3385 }
3386
3387 static void
3388 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3389 const struct radv_draw_info *info)
3390 {
3391 bool has_prefetch =
3392 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3393 bool pipeline_is_dirty =
3394 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3395 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3396
3397 MAYBE_UNUSED unsigned cdw_max =
3398 radeon_check_space(cmd_buffer->device->ws,
3399 cmd_buffer->cs, 4096);
3400
3401 /* Use optimal packet order based on whether we need to sync the
3402 * pipeline.
3403 */
3404 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3405 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3406 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3407 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3408 /* If we have to wait for idle, set all states first, so that
3409 * all SET packets are processed in parallel with previous draw
3410 * calls. Then upload descriptors, set shader pointers, and
3411 * draw, and prefetch at the end. This ensures that the time
3412 * the CUs are idle is very short. (there are only SET_SH
3413 * packets between the wait and the draw)
3414 */
3415 radv_emit_all_graphics_states(cmd_buffer, info);
3416 si_emit_cache_flush(cmd_buffer);
3417 /* <-- CUs are idle here --> */
3418
3419 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3420
3421 radv_emit_draw_packets(cmd_buffer, info);
3422 /* <-- CUs are busy here --> */
3423
3424 /* Start prefetches after the draw has been started. Both will
3425 * run in parallel, but starting the draw first is more
3426 * important.
3427 */
3428 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3429 radv_emit_prefetch_L2(cmd_buffer,
3430 cmd_buffer->state.pipeline, false);
3431 }
3432 } else {
3433 /* If we don't wait for idle, start prefetches first, then set
3434 * states, and draw at the end.
3435 */
3436 si_emit_cache_flush(cmd_buffer);
3437
3438 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3439 /* Only prefetch the vertex shader and VBO descriptors
3440 * in order to start the draw as soon as possible.
3441 */
3442 radv_emit_prefetch_L2(cmd_buffer,
3443 cmd_buffer->state.pipeline, true);
3444 }
3445
3446 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3447
3448 radv_emit_all_graphics_states(cmd_buffer, info);
3449 radv_emit_draw_packets(cmd_buffer, info);
3450
3451 /* Prefetch the remaining shaders after the draw has been
3452 * started.
3453 */
3454 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3455 radv_emit_prefetch_L2(cmd_buffer,
3456 cmd_buffer->state.pipeline, false);
3457 }
3458 }
3459
3460 assert(cmd_buffer->cs->cdw <= cdw_max);
3461 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3462 }
3463
3464 void radv_CmdDraw(
3465 VkCommandBuffer commandBuffer,
3466 uint32_t vertexCount,
3467 uint32_t instanceCount,
3468 uint32_t firstVertex,
3469 uint32_t firstInstance)
3470 {
3471 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3472 struct radv_draw_info info = {};
3473
3474 info.count = vertexCount;
3475 info.instance_count = instanceCount;
3476 info.first_instance = firstInstance;
3477 info.vertex_offset = firstVertex;
3478
3479 radv_draw(cmd_buffer, &info);
3480 }
3481
3482 void radv_CmdDrawIndexed(
3483 VkCommandBuffer commandBuffer,
3484 uint32_t indexCount,
3485 uint32_t instanceCount,
3486 uint32_t firstIndex,
3487 int32_t vertexOffset,
3488 uint32_t firstInstance)
3489 {
3490 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3491 struct radv_draw_info info = {};
3492
3493 info.indexed = true;
3494 info.count = indexCount;
3495 info.instance_count = instanceCount;
3496 info.first_index = firstIndex;
3497 info.vertex_offset = vertexOffset;
3498 info.first_instance = firstInstance;
3499
3500 radv_draw(cmd_buffer, &info);
3501 }
3502
3503 void radv_CmdDrawIndirect(
3504 VkCommandBuffer commandBuffer,
3505 VkBuffer _buffer,
3506 VkDeviceSize offset,
3507 uint32_t drawCount,
3508 uint32_t stride)
3509 {
3510 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3511 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3512 struct radv_draw_info info = {};
3513
3514 info.count = drawCount;
3515 info.indirect = buffer;
3516 info.indirect_offset = offset;
3517 info.stride = stride;
3518
3519 radv_draw(cmd_buffer, &info);
3520 }
3521
3522 void radv_CmdDrawIndexedIndirect(
3523 VkCommandBuffer commandBuffer,
3524 VkBuffer _buffer,
3525 VkDeviceSize offset,
3526 uint32_t drawCount,
3527 uint32_t stride)
3528 {
3529 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3530 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3531 struct radv_draw_info info = {};
3532
3533 info.indexed = true;
3534 info.count = drawCount;
3535 info.indirect = buffer;
3536 info.indirect_offset = offset;
3537 info.stride = stride;
3538
3539 radv_draw(cmd_buffer, &info);
3540 }
3541
3542 void radv_CmdDrawIndirectCountAMD(
3543 VkCommandBuffer commandBuffer,
3544 VkBuffer _buffer,
3545 VkDeviceSize offset,
3546 VkBuffer _countBuffer,
3547 VkDeviceSize countBufferOffset,
3548 uint32_t maxDrawCount,
3549 uint32_t stride)
3550 {
3551 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3552 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3553 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3554 struct radv_draw_info info = {};
3555
3556 info.count = maxDrawCount;
3557 info.indirect = buffer;
3558 info.indirect_offset = offset;
3559 info.count_buffer = count_buffer;
3560 info.count_buffer_offset = countBufferOffset;
3561 info.stride = stride;
3562
3563 radv_draw(cmd_buffer, &info);
3564 }
3565
3566 void radv_CmdDrawIndexedIndirectCountAMD(
3567 VkCommandBuffer commandBuffer,
3568 VkBuffer _buffer,
3569 VkDeviceSize offset,
3570 VkBuffer _countBuffer,
3571 VkDeviceSize countBufferOffset,
3572 uint32_t maxDrawCount,
3573 uint32_t stride)
3574 {
3575 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3576 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3577 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3578 struct radv_draw_info info = {};
3579
3580 info.indexed = true;
3581 info.count = maxDrawCount;
3582 info.indirect = buffer;
3583 info.indirect_offset = offset;
3584 info.count_buffer = count_buffer;
3585 info.count_buffer_offset = countBufferOffset;
3586 info.stride = stride;
3587
3588 radv_draw(cmd_buffer, &info);
3589 }
3590
3591 void radv_CmdDrawIndirectCountKHR(
3592 VkCommandBuffer commandBuffer,
3593 VkBuffer _buffer,
3594 VkDeviceSize offset,
3595 VkBuffer _countBuffer,
3596 VkDeviceSize countBufferOffset,
3597 uint32_t maxDrawCount,
3598 uint32_t stride)
3599 {
3600 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3601 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3602 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3603 struct radv_draw_info info = {};
3604
3605 info.count = maxDrawCount;
3606 info.indirect = buffer;
3607 info.indirect_offset = offset;
3608 info.count_buffer = count_buffer;
3609 info.count_buffer_offset = countBufferOffset;
3610 info.stride = stride;
3611
3612 radv_draw(cmd_buffer, &info);
3613 }
3614
3615 void radv_CmdDrawIndexedIndirectCountKHR(
3616 VkCommandBuffer commandBuffer,
3617 VkBuffer _buffer,
3618 VkDeviceSize offset,
3619 VkBuffer _countBuffer,
3620 VkDeviceSize countBufferOffset,
3621 uint32_t maxDrawCount,
3622 uint32_t stride)
3623 {
3624 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3625 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3626 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3627 struct radv_draw_info info = {};
3628
3629 info.indexed = true;
3630 info.count = maxDrawCount;
3631 info.indirect = buffer;
3632 info.indirect_offset = offset;
3633 info.count_buffer = count_buffer;
3634 info.count_buffer_offset = countBufferOffset;
3635 info.stride = stride;
3636
3637 radv_draw(cmd_buffer, &info);
3638 }
3639
3640 struct radv_dispatch_info {
3641 /**
3642 * Determine the layout of the grid (in block units) to be used.
3643 */
3644 uint32_t blocks[3];
3645
3646 /**
3647 * A starting offset for the grid. If unaligned is set, the offset
3648 * must still be aligned.
3649 */
3650 uint32_t offsets[3];
3651 /**
3652 * Whether it's an unaligned compute dispatch.
3653 */
3654 bool unaligned;
3655
3656 /**
3657 * Indirect compute parameters resource.
3658 */
3659 struct radv_buffer *indirect;
3660 uint64_t indirect_offset;
3661 };
3662
3663 static void
3664 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3665 const struct radv_dispatch_info *info)
3666 {
3667 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3668 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3669 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3670 struct radeon_winsys *ws = cmd_buffer->device->ws;
3671 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3672 struct radv_userdata_info *loc;
3673
3674 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3675 AC_UD_CS_GRID_SIZE);
3676
3677 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3678
3679 if (info->indirect) {
3680 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3681
3682 va += info->indirect->offset + info->indirect_offset;
3683
3684 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3685
3686 if (loc->sgpr_idx != -1) {
3687 for (unsigned i = 0; i < 3; ++i) {
3688 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3689 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3690 COPY_DATA_DST_SEL(COPY_DATA_REG));
3691 radeon_emit(cs, (va + 4 * i));
3692 radeon_emit(cs, (va + 4 * i) >> 32);
3693 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3694 + loc->sgpr_idx * 4) >> 2) + i);
3695 radeon_emit(cs, 0);
3696 }
3697 }
3698
3699 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3700 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3701 PKT3_SHADER_TYPE_S(1));
3702 radeon_emit(cs, va);
3703 radeon_emit(cs, va >> 32);
3704 radeon_emit(cs, dispatch_initiator);
3705 } else {
3706 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3707 PKT3_SHADER_TYPE_S(1));
3708 radeon_emit(cs, 1);
3709 radeon_emit(cs, va);
3710 radeon_emit(cs, va >> 32);
3711
3712 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3713 PKT3_SHADER_TYPE_S(1));
3714 radeon_emit(cs, 0);
3715 radeon_emit(cs, dispatch_initiator);
3716 }
3717 } else {
3718 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3719 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3720
3721 if (info->unaligned) {
3722 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3723 unsigned remainder[3];
3724
3725 /* If aligned, these should be an entire block size,
3726 * not 0.
3727 */
3728 remainder[0] = blocks[0] + cs_block_size[0] -
3729 align_u32_npot(blocks[0], cs_block_size[0]);
3730 remainder[1] = blocks[1] + cs_block_size[1] -
3731 align_u32_npot(blocks[1], cs_block_size[1]);
3732 remainder[2] = blocks[2] + cs_block_size[2] -
3733 align_u32_npot(blocks[2], cs_block_size[2]);
3734
3735 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3736 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3737 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3738
3739 for(unsigned i = 0; i < 3; ++i) {
3740 assert(offsets[i] % cs_block_size[i] == 0);
3741 offsets[i] /= cs_block_size[i];
3742 }
3743
3744 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3745 radeon_emit(cs,
3746 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3747 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3748 radeon_emit(cs,
3749 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3750 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3751 radeon_emit(cs,
3752 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3753 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3754
3755 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3756 }
3757
3758 if (loc->sgpr_idx != -1) {
3759 assert(!loc->indirect);
3760 assert(loc->num_sgprs == 3);
3761
3762 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3763 loc->sgpr_idx * 4, 3);
3764 radeon_emit(cs, blocks[0]);
3765 radeon_emit(cs, blocks[1]);
3766 radeon_emit(cs, blocks[2]);
3767 }
3768
3769 if (offsets[0] || offsets[1] || offsets[2]) {
3770 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3771 radeon_emit(cs, offsets[0]);
3772 radeon_emit(cs, offsets[1]);
3773 radeon_emit(cs, offsets[2]);
3774
3775 /* The blocks in the packet are not counts but end values. */
3776 for (unsigned i = 0; i < 3; ++i)
3777 blocks[i] += offsets[i];
3778 } else {
3779 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3780 }
3781
3782 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3783 PKT3_SHADER_TYPE_S(1));
3784 radeon_emit(cs, blocks[0]);
3785 radeon_emit(cs, blocks[1]);
3786 radeon_emit(cs, blocks[2]);
3787 radeon_emit(cs, dispatch_initiator);
3788 }
3789
3790 assert(cmd_buffer->cs->cdw <= cdw_max);
3791 }
3792
3793 static void
3794 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3795 {
3796 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3797 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3798 }
3799
3800 static void
3801 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3802 const struct radv_dispatch_info *info)
3803 {
3804 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3805 bool has_prefetch =
3806 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3807 bool pipeline_is_dirty = pipeline &&
3808 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3809
3810 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3811 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3812 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3813 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3814 /* If we have to wait for idle, set all states first, so that
3815 * all SET packets are processed in parallel with previous draw
3816 * calls. Then upload descriptors, set shader pointers, and
3817 * dispatch, and prefetch at the end. This ensures that the
3818 * time the CUs are idle is very short. (there are only SET_SH
3819 * packets between the wait and the draw)
3820 */
3821 radv_emit_compute_pipeline(cmd_buffer);
3822 si_emit_cache_flush(cmd_buffer);
3823 /* <-- CUs are idle here --> */
3824
3825 radv_upload_compute_shader_descriptors(cmd_buffer);
3826
3827 radv_emit_dispatch_packets(cmd_buffer, info);
3828 /* <-- CUs are busy here --> */
3829
3830 /* Start prefetches after the dispatch has been started. Both
3831 * will run in parallel, but starting the dispatch first is
3832 * more important.
3833 */
3834 if (has_prefetch && pipeline_is_dirty) {
3835 radv_emit_shader_prefetch(cmd_buffer,
3836 pipeline->shaders[MESA_SHADER_COMPUTE]);
3837 }
3838 } else {
3839 /* If we don't wait for idle, start prefetches first, then set
3840 * states, and dispatch at the end.
3841 */
3842 si_emit_cache_flush(cmd_buffer);
3843
3844 if (has_prefetch && pipeline_is_dirty) {
3845 radv_emit_shader_prefetch(cmd_buffer,
3846 pipeline->shaders[MESA_SHADER_COMPUTE]);
3847 }
3848
3849 radv_upload_compute_shader_descriptors(cmd_buffer);
3850
3851 radv_emit_compute_pipeline(cmd_buffer);
3852 radv_emit_dispatch_packets(cmd_buffer, info);
3853 }
3854
3855 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3856 }
3857
3858 void radv_CmdDispatchBase(
3859 VkCommandBuffer commandBuffer,
3860 uint32_t base_x,
3861 uint32_t base_y,
3862 uint32_t base_z,
3863 uint32_t x,
3864 uint32_t y,
3865 uint32_t z)
3866 {
3867 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3868 struct radv_dispatch_info info = {};
3869
3870 info.blocks[0] = x;
3871 info.blocks[1] = y;
3872 info.blocks[2] = z;
3873
3874 info.offsets[0] = base_x;
3875 info.offsets[1] = base_y;
3876 info.offsets[2] = base_z;
3877 radv_dispatch(cmd_buffer, &info);
3878 }
3879
3880 void radv_CmdDispatch(
3881 VkCommandBuffer commandBuffer,
3882 uint32_t x,
3883 uint32_t y,
3884 uint32_t z)
3885 {
3886 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3887 }
3888
3889 void radv_CmdDispatchIndirect(
3890 VkCommandBuffer commandBuffer,
3891 VkBuffer _buffer,
3892 VkDeviceSize offset)
3893 {
3894 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3895 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3896 struct radv_dispatch_info info = {};
3897
3898 info.indirect = buffer;
3899 info.indirect_offset = offset;
3900
3901 radv_dispatch(cmd_buffer, &info);
3902 }
3903
3904 void radv_unaligned_dispatch(
3905 struct radv_cmd_buffer *cmd_buffer,
3906 uint32_t x,
3907 uint32_t y,
3908 uint32_t z)
3909 {
3910 struct radv_dispatch_info info = {};
3911
3912 info.blocks[0] = x;
3913 info.blocks[1] = y;
3914 info.blocks[2] = z;
3915 info.unaligned = 1;
3916
3917 radv_dispatch(cmd_buffer, &info);
3918 }
3919
3920 void radv_CmdEndRenderPass(
3921 VkCommandBuffer commandBuffer)
3922 {
3923 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3924
3925 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3926
3927 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3928
3929 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3930 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3931 radv_handle_subpass_image_transition(cmd_buffer,
3932 (VkAttachmentReference){i, layout});
3933 }
3934
3935 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3936
3937 cmd_buffer->state.pass = NULL;
3938 cmd_buffer->state.subpass = NULL;
3939 cmd_buffer->state.attachments = NULL;
3940 cmd_buffer->state.framebuffer = NULL;
3941 }
3942
3943 /*
3944 * For HTILE we have the following interesting clear words:
3945 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3946 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3947 * 0xfffffff0: Clear depth to 1.0
3948 * 0x00000000: Clear depth to 0.0
3949 */
3950 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3951 struct radv_image *image,
3952 const VkImageSubresourceRange *range,
3953 uint32_t clear_word)
3954 {
3955 assert(range->baseMipLevel == 0);
3956 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3957 unsigned layer_count = radv_get_layerCount(image, range);
3958 uint64_t size = image->surface.htile_slice_size * layer_count;
3959 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
3960 uint64_t offset = image->offset + image->htile_offset +
3961 image->surface.htile_slice_size * range->baseArrayLayer;
3962 struct radv_cmd_state *state = &cmd_buffer->state;
3963 VkClearDepthStencilValue value = {};
3964
3965 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3966 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3967
3968 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3969 size, clear_word);
3970
3971 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3972
3973 if (vk_format_is_stencil(image->vk_format))
3974 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3975
3976 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
3977 }
3978
3979 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3980 struct radv_image *image,
3981 VkImageLayout src_layout,
3982 VkImageLayout dst_layout,
3983 unsigned src_queue_mask,
3984 unsigned dst_queue_mask,
3985 const VkImageSubresourceRange *range,
3986 VkImageAspectFlags pending_clears)
3987 {
3988 if (!radv_image_has_htile(image))
3989 return;
3990
3991 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3992 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3993 /* TODO: merge with the clear if applicable */
3994 radv_initialize_htile(cmd_buffer, image, range, 0);
3995 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3996 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3997 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3998 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3999 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4000 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4001 VkImageSubresourceRange local_range = *range;
4002 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4003 local_range.baseMipLevel = 0;
4004 local_range.levelCount = 1;
4005
4006 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4007 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4008
4009 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4010
4011 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4012 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4013 }
4014 }
4015
4016 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4017 struct radv_image *image, uint32_t value)
4018 {
4019 struct radv_cmd_state *state = &cmd_buffer->state;
4020
4021 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4022 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4023
4024 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4025
4026 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4027 }
4028
4029 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4030 struct radv_image *image, uint32_t value)
4031 {
4032 struct radv_cmd_state *state = &cmd_buffer->state;
4033
4034 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4035 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4036
4037 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4038
4039 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4040 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4041 }
4042
4043 /**
4044 * Initialize DCC/FMASK/CMASK metadata for a color image.
4045 */
4046 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4047 struct radv_image *image,
4048 VkImageLayout src_layout,
4049 VkImageLayout dst_layout,
4050 unsigned src_queue_mask,
4051 unsigned dst_queue_mask)
4052 {
4053 if (radv_image_has_cmask(image)) {
4054 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4055
4056 /* TODO: clarify this. */
4057 if (radv_image_has_fmask(image)) {
4058 value = 0xccccccccu;
4059 }
4060
4061 radv_initialise_cmask(cmd_buffer, image, value);
4062 }
4063
4064 if (radv_image_has_dcc(image)) {
4065 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4066
4067 if (radv_layout_dcc_compressed(image, dst_layout,
4068 dst_queue_mask)) {
4069 value = 0x20202020u;
4070 }
4071
4072 radv_initialize_dcc(cmd_buffer, image, value);
4073
4074 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image, false);
4075 }
4076
4077 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4078 uint32_t color_values[2] = {};
4079 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4080 }
4081 }
4082
4083 /**
4084 * Handle color image transitions for DCC/FMASK/CMASK.
4085 */
4086 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4087 struct radv_image *image,
4088 VkImageLayout src_layout,
4089 VkImageLayout dst_layout,
4090 unsigned src_queue_mask,
4091 unsigned dst_queue_mask,
4092 const VkImageSubresourceRange *range)
4093 {
4094 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4095 radv_init_color_image_metadata(cmd_buffer, image,
4096 src_layout, dst_layout,
4097 src_queue_mask, dst_queue_mask);
4098 return;
4099 }
4100
4101 if (radv_image_has_dcc(image)) {
4102 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4103 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4104 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4105 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4106 radv_decompress_dcc(cmd_buffer, image, range);
4107 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4108 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4109 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4110 }
4111 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4112 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4113 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4114 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4115 }
4116 }
4117 }
4118
4119 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4120 struct radv_image *image,
4121 VkImageLayout src_layout,
4122 VkImageLayout dst_layout,
4123 uint32_t src_family,
4124 uint32_t dst_family,
4125 const VkImageSubresourceRange *range,
4126 VkImageAspectFlags pending_clears)
4127 {
4128 if (image->exclusive && src_family != dst_family) {
4129 /* This is an acquire or a release operation and there will be
4130 * a corresponding release/acquire. Do the transition in the
4131 * most flexible queue. */
4132
4133 assert(src_family == cmd_buffer->queue_family_index ||
4134 dst_family == cmd_buffer->queue_family_index);
4135
4136 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4137 return;
4138
4139 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4140 (src_family == RADV_QUEUE_GENERAL ||
4141 dst_family == RADV_QUEUE_GENERAL))
4142 return;
4143 }
4144
4145 unsigned src_queue_mask =
4146 radv_image_queue_family_mask(image, src_family,
4147 cmd_buffer->queue_family_index);
4148 unsigned dst_queue_mask =
4149 radv_image_queue_family_mask(image, dst_family,
4150 cmd_buffer->queue_family_index);
4151
4152 if (vk_format_is_depth(image->vk_format)) {
4153 radv_handle_depth_image_transition(cmd_buffer, image,
4154 src_layout, dst_layout,
4155 src_queue_mask, dst_queue_mask,
4156 range, pending_clears);
4157 } else {
4158 radv_handle_color_image_transition(cmd_buffer, image,
4159 src_layout, dst_layout,
4160 src_queue_mask, dst_queue_mask,
4161 range);
4162 }
4163 }
4164
4165 void radv_CmdPipelineBarrier(
4166 VkCommandBuffer commandBuffer,
4167 VkPipelineStageFlags srcStageMask,
4168 VkPipelineStageFlags destStageMask,
4169 VkBool32 byRegion,
4170 uint32_t memoryBarrierCount,
4171 const VkMemoryBarrier* pMemoryBarriers,
4172 uint32_t bufferMemoryBarrierCount,
4173 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4174 uint32_t imageMemoryBarrierCount,
4175 const VkImageMemoryBarrier* pImageMemoryBarriers)
4176 {
4177 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4178 enum radv_cmd_flush_bits src_flush_bits = 0;
4179 enum radv_cmd_flush_bits dst_flush_bits = 0;
4180
4181 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4182 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
4183 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4184 NULL);
4185 }
4186
4187 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4188 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
4189 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4190 NULL);
4191 }
4192
4193 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4194 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4195 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
4196 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4197 image);
4198 }
4199
4200 radv_stage_flush(cmd_buffer, srcStageMask);
4201 cmd_buffer->state.flush_bits |= src_flush_bits;
4202
4203 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4204 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4205 radv_handle_image_transition(cmd_buffer, image,
4206 pImageMemoryBarriers[i].oldLayout,
4207 pImageMemoryBarriers[i].newLayout,
4208 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4209 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4210 &pImageMemoryBarriers[i].subresourceRange,
4211 0);
4212 }
4213
4214 cmd_buffer->state.flush_bits |= dst_flush_bits;
4215 }
4216
4217
4218 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4219 struct radv_event *event,
4220 VkPipelineStageFlags stageMask,
4221 unsigned value)
4222 {
4223 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4224 uint64_t va = radv_buffer_get_va(event->bo);
4225
4226 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4227
4228 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4229
4230 /* TODO: this is overkill. Probably should figure something out from
4231 * the stage mask. */
4232
4233 si_cs_emit_write_event_eop(cs,
4234 cmd_buffer->device->physical_device->rad_info.chip_class,
4235 radv_cmd_buffer_uses_mec(cmd_buffer),
4236 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4237 EOP_DATA_SEL_VALUE_32BIT, va, 2, value);
4238
4239 assert(cmd_buffer->cs->cdw <= cdw_max);
4240 }
4241
4242 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4243 VkEvent _event,
4244 VkPipelineStageFlags stageMask)
4245 {
4246 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4247 RADV_FROM_HANDLE(radv_event, event, _event);
4248
4249 write_event(cmd_buffer, event, stageMask, 1);
4250 }
4251
4252 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4253 VkEvent _event,
4254 VkPipelineStageFlags stageMask)
4255 {
4256 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4257 RADV_FROM_HANDLE(radv_event, event, _event);
4258
4259 write_event(cmd_buffer, event, stageMask, 0);
4260 }
4261
4262 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4263 uint32_t eventCount,
4264 const VkEvent* pEvents,
4265 VkPipelineStageFlags srcStageMask,
4266 VkPipelineStageFlags dstStageMask,
4267 uint32_t memoryBarrierCount,
4268 const VkMemoryBarrier* pMemoryBarriers,
4269 uint32_t bufferMemoryBarrierCount,
4270 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4271 uint32_t imageMemoryBarrierCount,
4272 const VkImageMemoryBarrier* pImageMemoryBarriers)
4273 {
4274 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4275 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4276
4277 for (unsigned i = 0; i < eventCount; ++i) {
4278 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4279 uint64_t va = radv_buffer_get_va(event->bo);
4280
4281 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4282
4283 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4284
4285 si_emit_wait_fence(cs, va, 1, 0xffffffff);
4286 assert(cmd_buffer->cs->cdw <= cdw_max);
4287 }
4288
4289
4290 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4291 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4292
4293 radv_handle_image_transition(cmd_buffer, image,
4294 pImageMemoryBarriers[i].oldLayout,
4295 pImageMemoryBarriers[i].newLayout,
4296 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4297 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4298 &pImageMemoryBarriers[i].subresourceRange,
4299 0);
4300 }
4301
4302 /* TODO: figure out how to do memory barriers without waiting */
4303 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4304 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4305 RADV_CMD_FLAG_INV_VMEM_L1 |
4306 RADV_CMD_FLAG_INV_SMEM_L1;
4307 }
4308
4309
4310 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4311 uint32_t deviceMask)
4312 {
4313 /* No-op */
4314 }