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radv: use a mask for VBOs and shaders prefetching
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range,
61 VkImageAspectFlags pending_clears);
62
63 const struct radv_dynamic_state default_dynamic_state = {
64 .viewport = {
65 .count = 0,
66 },
67 .scissor = {
68 .count = 0,
69 },
70 .line_width = 1.0f,
71 .depth_bias = {
72 .bias = 0.0f,
73 .clamp = 0.0f,
74 .slope = 0.0f,
75 },
76 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
77 .depth_bounds = {
78 .min = 0.0f,
79 .max = 1.0f,
80 },
81 .stencil_compare_mask = {
82 .front = ~0u,
83 .back = ~0u,
84 },
85 .stencil_write_mask = {
86 .front = ~0u,
87 .back = ~0u,
88 },
89 .stencil_reference = {
90 .front = 0u,
91 .back = 0u,
92 },
93 };
94
95 static void
96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
97 const struct radv_dynamic_state *src)
98 {
99 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
100 uint32_t copy_mask = src->mask;
101 uint32_t dest_mask = 0;
102
103 /* Make sure to copy the number of viewports/scissors because they can
104 * only be specified at pipeline creation time.
105 */
106 dest->viewport.count = src->viewport.count;
107 dest->scissor.count = src->scissor.count;
108 dest->discard_rectangle.count = src->discard_rectangle.count;
109
110 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
111 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
112 src->viewport.count * sizeof(VkViewport))) {
113 typed_memcpy(dest->viewport.viewports,
114 src->viewport.viewports,
115 src->viewport.count);
116 dest_mask |= RADV_DYNAMIC_VIEWPORT;
117 }
118 }
119
120 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
121 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
122 src->scissor.count * sizeof(VkRect2D))) {
123 typed_memcpy(dest->scissor.scissors,
124 src->scissor.scissors, src->scissor.count);
125 dest_mask |= RADV_DYNAMIC_SCISSOR;
126 }
127 }
128
129 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
130 if (dest->line_width != src->line_width) {
131 dest->line_width = src->line_width;
132 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
133 }
134 }
135
136 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
137 if (memcmp(&dest->depth_bias, &src->depth_bias,
138 sizeof(src->depth_bias))) {
139 dest->depth_bias = src->depth_bias;
140 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
141 }
142 }
143
144 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
145 if (memcmp(&dest->blend_constants, &src->blend_constants,
146 sizeof(src->blend_constants))) {
147 typed_memcpy(dest->blend_constants,
148 src->blend_constants, 4);
149 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
150 }
151 }
152
153 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
154 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
155 sizeof(src->depth_bounds))) {
156 dest->depth_bounds = src->depth_bounds;
157 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
158 }
159 }
160
161 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
162 if (memcmp(&dest->stencil_compare_mask,
163 &src->stencil_compare_mask,
164 sizeof(src->stencil_compare_mask))) {
165 dest->stencil_compare_mask = src->stencil_compare_mask;
166 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
167 }
168 }
169
170 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
171 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
172 sizeof(src->stencil_write_mask))) {
173 dest->stencil_write_mask = src->stencil_write_mask;
174 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
175 }
176 }
177
178 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
179 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
180 sizeof(src->stencil_reference))) {
181 dest->stencil_reference = src->stencil_reference;
182 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
183 }
184 }
185
186 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
187 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
188 src->discard_rectangle.count * sizeof(VkRect2D))) {
189 typed_memcpy(dest->discard_rectangle.rectangles,
190 src->discard_rectangle.rectangles,
191 src->discard_rectangle.count);
192 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
193 }
194 }
195
196 cmd_buffer->state.dirty |= dest_mask;
197 }
198
199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
200 {
201 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
202 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
203 }
204
205 enum ring_type radv_queue_family_to_ring(int f) {
206 switch (f) {
207 case RADV_QUEUE_GENERAL:
208 return RING_GFX;
209 case RADV_QUEUE_COMPUTE:
210 return RING_COMPUTE;
211 case RADV_QUEUE_TRANSFER:
212 return RING_DMA;
213 default:
214 unreachable("Unknown queue family");
215 }
216 }
217
218 static VkResult radv_create_cmd_buffer(
219 struct radv_device * device,
220 struct radv_cmd_pool * pool,
221 VkCommandBufferLevel level,
222 VkCommandBuffer* pCommandBuffer)
223 {
224 struct radv_cmd_buffer *cmd_buffer;
225 unsigned ring;
226 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
227 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
228 if (cmd_buffer == NULL)
229 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
230
231 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
232 cmd_buffer->device = device;
233 cmd_buffer->pool = pool;
234 cmd_buffer->level = level;
235
236 if (pool) {
237 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
238 cmd_buffer->queue_family_index = pool->queue_family_index;
239
240 } else {
241 /* Init the pool_link so we can safefly call list_del when we destroy
242 * the command buffer
243 */
244 list_inithead(&cmd_buffer->pool_link);
245 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
246 }
247
248 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
249
250 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
251 if (!cmd_buffer->cs) {
252 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
253 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
254 }
255
256 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
257
258 list_inithead(&cmd_buffer->upload.list);
259
260 return VK_SUCCESS;
261 }
262
263 static void
264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
265 {
266 list_del(&cmd_buffer->pool_link);
267
268 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
269 &cmd_buffer->upload.list, list) {
270 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
271 list_del(&up->list);
272 free(up);
273 }
274
275 if (cmd_buffer->upload.upload_bo)
276 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
277 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
278
279 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
280 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
281
282 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
283 }
284
285 static VkResult
286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
287 {
288
289 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
290
291 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
292 &cmd_buffer->upload.list, list) {
293 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
294 list_del(&up->list);
295 free(up);
296 }
297
298 cmd_buffer->push_constant_stages = 0;
299 cmd_buffer->scratch_size_needed = 0;
300 cmd_buffer->compute_scratch_size_needed = 0;
301 cmd_buffer->esgs_ring_size_needed = 0;
302 cmd_buffer->gsvs_ring_size_needed = 0;
303 cmd_buffer->tess_rings_needed = false;
304 cmd_buffer->sample_positions_needed = false;
305
306 if (cmd_buffer->upload.upload_bo)
307 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
308 cmd_buffer->upload.upload_bo, 8);
309 cmd_buffer->upload.offset = 0;
310
311 cmd_buffer->record_result = VK_SUCCESS;
312
313 cmd_buffer->ring_offsets_idx = -1;
314
315 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
316 cmd_buffer->descriptors[i].dirty = 0;
317 cmd_buffer->descriptors[i].valid = 0;
318 cmd_buffer->descriptors[i].push_dirty = false;
319 }
320
321 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
322 void *fence_ptr;
323 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
324 &cmd_buffer->gfx9_fence_offset,
325 &fence_ptr);
326 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
327 }
328
329 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
330
331 return cmd_buffer->record_result;
332 }
333
334 static bool
335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
336 uint64_t min_needed)
337 {
338 uint64_t new_size;
339 struct radeon_winsys_bo *bo;
340 struct radv_cmd_buffer_upload *upload;
341 struct radv_device *device = cmd_buffer->device;
342
343 new_size = MAX2(min_needed, 16 * 1024);
344 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
345
346 bo = device->ws->buffer_create(device->ws,
347 new_size, 4096,
348 RADEON_DOMAIN_GTT,
349 RADEON_FLAG_CPU_ACCESS|
350 RADEON_FLAG_NO_INTERPROCESS_SHARING);
351
352 if (!bo) {
353 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
354 return false;
355 }
356
357 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
358 if (cmd_buffer->upload.upload_bo) {
359 upload = malloc(sizeof(*upload));
360
361 if (!upload) {
362 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
363 device->ws->buffer_destroy(bo);
364 return false;
365 }
366
367 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
368 list_add(&upload->list, &cmd_buffer->upload.list);
369 }
370
371 cmd_buffer->upload.upload_bo = bo;
372 cmd_buffer->upload.size = new_size;
373 cmd_buffer->upload.offset = 0;
374 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
375
376 if (!cmd_buffer->upload.map) {
377 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
378 return false;
379 }
380
381 return true;
382 }
383
384 bool
385 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
386 unsigned size,
387 unsigned alignment,
388 unsigned *out_offset,
389 void **ptr)
390 {
391 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
392 if (offset + size > cmd_buffer->upload.size) {
393 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
394 return false;
395 offset = 0;
396 }
397
398 *out_offset = offset;
399 *ptr = cmd_buffer->upload.map + offset;
400
401 cmd_buffer->upload.offset = offset + size;
402 return true;
403 }
404
405 bool
406 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
407 unsigned size, unsigned alignment,
408 const void *data, unsigned *out_offset)
409 {
410 uint8_t *ptr;
411
412 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
413 out_offset, (void **)&ptr))
414 return false;
415
416 if (ptr)
417 memcpy(ptr, data, size);
418
419 return true;
420 }
421
422 static void
423 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
424 unsigned count, const uint32_t *data)
425 {
426 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
427 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
428 S_370_WR_CONFIRM(1) |
429 S_370_ENGINE_SEL(V_370_ME));
430 radeon_emit(cs, va);
431 radeon_emit(cs, va >> 32);
432 radeon_emit_array(cs, data, count);
433 }
434
435 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
436 {
437 struct radv_device *device = cmd_buffer->device;
438 struct radeon_winsys_cs *cs = cmd_buffer->cs;
439 uint64_t va;
440
441 va = radv_buffer_get_va(device->trace_bo);
442 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
443 va += 4;
444
445 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
446
447 ++cmd_buffer->state.trace_id;
448 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
449 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
450 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
451 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
452 }
453
454 static void
455 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
456 enum radv_cmd_flush_bits flags)
457 {
458 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
459 uint32_t *ptr = NULL;
460 uint64_t va = 0;
461
462 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
463 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
464
465 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
466 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
467 cmd_buffer->gfx9_fence_offset;
468 ptr = &cmd_buffer->gfx9_fence_idx;
469 }
470
471 /* Force wait for graphics or compute engines to be idle. */
472 si_cs_emit_cache_flush(cmd_buffer->cs,
473 cmd_buffer->device->physical_device->rad_info.chip_class,
474 ptr, va,
475 radv_cmd_buffer_uses_mec(cmd_buffer),
476 flags);
477 }
478
479 if (unlikely(cmd_buffer->device->trace_bo))
480 radv_cmd_buffer_trace_emit(cmd_buffer);
481 }
482
483 static void
484 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
485 struct radv_pipeline *pipeline, enum ring_type ring)
486 {
487 struct radv_device *device = cmd_buffer->device;
488 struct radeon_winsys_cs *cs = cmd_buffer->cs;
489 uint32_t data[2];
490 uint64_t va;
491
492 va = radv_buffer_get_va(device->trace_bo);
493
494 switch (ring) {
495 case RING_GFX:
496 va += 8;
497 break;
498 case RING_COMPUTE:
499 va += 16;
500 break;
501 default:
502 assert(!"invalid ring type");
503 }
504
505 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
506 cmd_buffer->cs, 6);
507
508 data[0] = (uintptr_t)pipeline;
509 data[1] = (uintptr_t)pipeline >> 32;
510
511 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
512 radv_emit_write_data_packet(cs, va, 2, data);
513 }
514
515 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
516 VkPipelineBindPoint bind_point,
517 struct radv_descriptor_set *set,
518 unsigned idx)
519 {
520 struct radv_descriptor_state *descriptors_state =
521 radv_get_descriptors_state(cmd_buffer, bind_point);
522
523 descriptors_state->sets[idx] = set;
524 if (set)
525 descriptors_state->valid |= (1u << idx);
526 else
527 descriptors_state->valid &= ~(1u << idx);
528 descriptors_state->dirty |= (1u << idx);
529 }
530
531 static void
532 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
533 VkPipelineBindPoint bind_point)
534 {
535 struct radv_descriptor_state *descriptors_state =
536 radv_get_descriptors_state(cmd_buffer, bind_point);
537 struct radv_device *device = cmd_buffer->device;
538 struct radeon_winsys_cs *cs = cmd_buffer->cs;
539 uint32_t data[MAX_SETS * 2] = {};
540 uint64_t va;
541 unsigned i;
542 va = radv_buffer_get_va(device->trace_bo) + 24;
543
544 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
545 cmd_buffer->cs, 4 + MAX_SETS * 2);
546
547 for_each_bit(i, descriptors_state->valid) {
548 struct radv_descriptor_set *set = descriptors_state->sets[i];
549 data[i * 2] = (uintptr_t)set;
550 data[i * 2 + 1] = (uintptr_t)set >> 32;
551 }
552
553 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
554 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
555 }
556
557 struct radv_userdata_info *
558 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
559 gl_shader_stage stage,
560 int idx)
561 {
562 if (stage == MESA_SHADER_VERTEX) {
563 if (pipeline->shaders[MESA_SHADER_VERTEX])
564 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
565 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
566 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
567 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
568 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
569 } else if (stage == MESA_SHADER_TESS_EVAL) {
570 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
571 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
572 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
573 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
574 }
575 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
576 }
577
578 static void
579 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
580 struct radv_pipeline *pipeline,
581 gl_shader_stage stage,
582 int idx, uint64_t va)
583 {
584 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
585 uint32_t base_reg = pipeline->user_data_0[stage];
586 if (loc->sgpr_idx == -1)
587 return;
588 assert(loc->num_sgprs == 2);
589 assert(!loc->indirect);
590 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
591 radeon_emit(cmd_buffer->cs, va);
592 radeon_emit(cmd_buffer->cs, va >> 32);
593 }
594
595 static void
596 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
597 struct radv_pipeline *pipeline)
598 {
599 int num_samples = pipeline->graphics.ms.num_samples;
600 struct radv_multisample_state *ms = &pipeline->graphics.ms;
601 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
602
603 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
604 cmd_buffer->sample_positions_needed = true;
605
606 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
607 return;
608
609 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
610 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
611 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
612
613 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
614
615 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
616
617 /* GFX9: Flush DFSM when the AA mode changes. */
618 if (cmd_buffer->device->dfsm_allowed) {
619 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
620 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
621 }
622 }
623
624
625
626 static inline void
627 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
628 unsigned size)
629 {
630 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
631 si_cp_dma_prefetch(cmd_buffer, va, size);
632 }
633
634 static void
635 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
636 struct radv_shader_variant *shader)
637 {
638 struct radeon_winsys *ws = cmd_buffer->device->ws;
639 struct radeon_winsys_cs *cs = cmd_buffer->cs;
640 uint64_t va;
641
642 if (!shader)
643 return;
644
645 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
646
647 radv_cs_add_buffer(ws, cs, shader->bo, 8);
648 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
649 }
650
651 static void
652 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
653 struct radv_pipeline *pipeline)
654 {
655 struct radv_cmd_state *state = &cmd_buffer->state;
656
657 if (state->prefetch_L2_mask & RADV_PREFETCH_VS)
658 radv_emit_shader_prefetch(cmd_buffer,
659 pipeline->shaders[MESA_SHADER_VERTEX]);
660
661 if (state->prefetch_L2_mask & RADV_PREFETCH_VBO_DESCRIPTORS)
662 radv_emit_prefetch_TC_L2_async(cmd_buffer, state->vb_va,
663 state->vb_size);
664
665 if (state->prefetch_L2_mask & RADV_PREFETCH_TCS)
666 radv_emit_shader_prefetch(cmd_buffer,
667 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
668
669 if (state->prefetch_L2_mask & RADV_PREFETCH_TES)
670 radv_emit_shader_prefetch(cmd_buffer,
671 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
672
673 if (state->prefetch_L2_mask & RADV_PREFETCH_GS) {
674 radv_emit_shader_prefetch(cmd_buffer,
675 pipeline->shaders[MESA_SHADER_GEOMETRY]);
676 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
677 }
678
679 if (state->prefetch_L2_mask & RADV_PREFETCH_PS)
680 radv_emit_shader_prefetch(cmd_buffer,
681 pipeline->shaders[MESA_SHADER_FRAGMENT]);
682
683 state->prefetch_L2_mask = 0;
684 }
685
686 static void
687 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
688 {
689 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
690
691 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
692 return;
693
694 radv_update_multisample_state(cmd_buffer, pipeline);
695
696 cmd_buffer->scratch_size_needed =
697 MAX2(cmd_buffer->scratch_size_needed,
698 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
699
700 if (!cmd_buffer->state.emitted_pipeline ||
701 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
702 pipeline->graphics.can_use_guardband)
703 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
704
705 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
706
707 if (unlikely(cmd_buffer->device->trace_bo))
708 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
709
710 cmd_buffer->state.emitted_pipeline = pipeline;
711
712 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
713 }
714
715 static void
716 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
717 {
718 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
719 cmd_buffer->state.dynamic.viewport.viewports);
720 }
721
722 static void
723 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
724 {
725 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
726
727 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
728 * scissor registers are changed. There is also a more efficient but
729 * more involved alternative workaround.
730 */
731 if (cmd_buffer->device->physical_device->has_scissor_bug) {
732 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
733 si_emit_cache_flush(cmd_buffer);
734 }
735 si_write_scissors(cmd_buffer->cs, 0, count,
736 cmd_buffer->state.dynamic.scissor.scissors,
737 cmd_buffer->state.dynamic.viewport.viewports,
738 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
739 }
740
741 static void
742 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
743 {
744 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
745 return;
746
747 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
748 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
749 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
750 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
751 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
752 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
753 S_028214_BR_Y(rect.offset.y + rect.extent.height));
754 }
755 }
756
757 static void
758 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
759 {
760 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
761
762 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
763 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
764 }
765
766 static void
767 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
768 {
769 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
770
771 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
772 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
773 }
774
775 static void
776 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
777 {
778 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
779
780 radeon_set_context_reg_seq(cmd_buffer->cs,
781 R_028430_DB_STENCILREFMASK, 2);
782 radeon_emit(cmd_buffer->cs,
783 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
784 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
785 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
786 S_028430_STENCILOPVAL(1));
787 radeon_emit(cmd_buffer->cs,
788 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
789 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
790 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
791 S_028434_STENCILOPVAL_BF(1));
792 }
793
794 static void
795 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
796 {
797 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
798
799 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
800 fui(d->depth_bounds.min));
801 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
802 fui(d->depth_bounds.max));
803 }
804
805 static void
806 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
807 {
808 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
809 unsigned slope = fui(d->depth_bias.slope * 16.0f);
810 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
811
812
813 radeon_set_context_reg_seq(cmd_buffer->cs,
814 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
815 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
816 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
817 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
818 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
819 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
820 }
821
822 static void
823 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
824 int index,
825 struct radv_attachment_info *att,
826 struct radv_image *image,
827 VkImageLayout layout)
828 {
829 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
830 struct radv_color_buffer_info *cb = &att->cb;
831 uint32_t cb_color_info = cb->cb_color_info;
832
833 if (!radv_layout_dcc_compressed(image, layout,
834 radv_image_queue_family_mask(image,
835 cmd_buffer->queue_family_index,
836 cmd_buffer->queue_family_index))) {
837 cb_color_info &= C_028C70_DCC_ENABLE;
838 }
839
840 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
841 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
842 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
843 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
844 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
845 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
846 radeon_emit(cmd_buffer->cs, cb_color_info);
847 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
848 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
849 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
850 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
851 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
852 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
853
854 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
855 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
856 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
857
858 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
859 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
860 } else {
861 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
862 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
863 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
864 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
865 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
866 radeon_emit(cmd_buffer->cs, cb_color_info);
867 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
868 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
869 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
870 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
871 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
872 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
873
874 if (is_vi) { /* DCC BASE */
875 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
876 }
877 }
878 }
879
880 static void
881 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
882 struct radv_ds_buffer_info *ds,
883 struct radv_image *image,
884 VkImageLayout layout)
885 {
886 uint32_t db_z_info = ds->db_z_info;
887 uint32_t db_stencil_info = ds->db_stencil_info;
888
889 if (!radv_layout_has_htile(image, layout,
890 radv_image_queue_family_mask(image,
891 cmd_buffer->queue_family_index,
892 cmd_buffer->queue_family_index))) {
893 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
894 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
895 }
896
897 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
898 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
899
900
901 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
902 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
903 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
904 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
905 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
906
907 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
908 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
909 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
910 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
911 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
912 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
913 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
914 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
915 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
916 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
917 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
918
919 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
920 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
921 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
922 } else {
923 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
924
925 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
926 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
927 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
928 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
929 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
930 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
931 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
932 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
933 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
934 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
935
936 }
937
938 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
939 ds->pa_su_poly_offset_db_fmt_cntl);
940 }
941
942 void
943 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
944 struct radv_image *image,
945 VkClearDepthStencilValue ds_clear_value,
946 VkImageAspectFlags aspects)
947 {
948 uint64_t va = radv_buffer_get_va(image->bo);
949 va += image->offset + image->clear_value_offset;
950 unsigned reg_offset = 0, reg_count = 0;
951
952 assert(image->surface.htile_size);
953
954 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
955 ++reg_count;
956 } else {
957 ++reg_offset;
958 va += 4;
959 }
960 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
961 ++reg_count;
962
963 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
964 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
965 S_370_WR_CONFIRM(1) |
966 S_370_ENGINE_SEL(V_370_PFP));
967 radeon_emit(cmd_buffer->cs, va);
968 radeon_emit(cmd_buffer->cs, va >> 32);
969 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
970 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
971 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
972 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
973
974 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
975 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
976 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
977 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
978 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
979 }
980
981 static void
982 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
983 struct radv_image *image)
984 {
985 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
986 uint64_t va = radv_buffer_get_va(image->bo);
987 va += image->offset + image->clear_value_offset;
988 unsigned reg_offset = 0, reg_count = 0;
989
990 if (!image->surface.htile_size)
991 return;
992
993 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
994 ++reg_count;
995 } else {
996 ++reg_offset;
997 va += 4;
998 }
999 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1000 ++reg_count;
1001
1002 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1003 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1004 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1005 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1006 radeon_emit(cmd_buffer->cs, va);
1007 radeon_emit(cmd_buffer->cs, va >> 32);
1008 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1009 radeon_emit(cmd_buffer->cs, 0);
1010
1011 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1012 radeon_emit(cmd_buffer->cs, 0);
1013 }
1014
1015 /*
1016 *with DCC some colors don't require CMASK elimiation before being
1017 * used as a texture. This sets a predicate value to determine if the
1018 * cmask eliminate is required.
1019 */
1020 void
1021 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1022 struct radv_image *image,
1023 bool value)
1024 {
1025 uint64_t pred_val = value;
1026 uint64_t va = radv_buffer_get_va(image->bo);
1027 va += image->offset + image->dcc_pred_offset;
1028
1029 assert(image->surface.dcc_size);
1030
1031 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1032 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1033 S_370_WR_CONFIRM(1) |
1034 S_370_ENGINE_SEL(V_370_PFP));
1035 radeon_emit(cmd_buffer->cs, va);
1036 radeon_emit(cmd_buffer->cs, va >> 32);
1037 radeon_emit(cmd_buffer->cs, pred_val);
1038 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1039 }
1040
1041 void
1042 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1043 struct radv_image *image,
1044 int idx,
1045 uint32_t color_values[2])
1046 {
1047 uint64_t va = radv_buffer_get_va(image->bo);
1048 va += image->offset + image->clear_value_offset;
1049
1050 assert(image->cmask.size || image->surface.dcc_size);
1051
1052 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1053 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1054 S_370_WR_CONFIRM(1) |
1055 S_370_ENGINE_SEL(V_370_PFP));
1056 radeon_emit(cmd_buffer->cs, va);
1057 radeon_emit(cmd_buffer->cs, va >> 32);
1058 radeon_emit(cmd_buffer->cs, color_values[0]);
1059 radeon_emit(cmd_buffer->cs, color_values[1]);
1060
1061 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1062 radeon_emit(cmd_buffer->cs, color_values[0]);
1063 radeon_emit(cmd_buffer->cs, color_values[1]);
1064 }
1065
1066 static void
1067 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1068 struct radv_image *image,
1069 int idx)
1070 {
1071 uint64_t va = radv_buffer_get_va(image->bo);
1072 va += image->offset + image->clear_value_offset;
1073
1074 if (!image->cmask.size && !image->surface.dcc_size)
1075 return;
1076
1077 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1078
1079 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1080 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1081 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1082 COPY_DATA_COUNT_SEL);
1083 radeon_emit(cmd_buffer->cs, va);
1084 radeon_emit(cmd_buffer->cs, va >> 32);
1085 radeon_emit(cmd_buffer->cs, reg >> 2);
1086 radeon_emit(cmd_buffer->cs, 0);
1087
1088 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1089 radeon_emit(cmd_buffer->cs, 0);
1090 }
1091
1092 static void
1093 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1094 {
1095 int i;
1096 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1097 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1098
1099 /* this may happen for inherited secondary recording */
1100 if (!framebuffer)
1101 return;
1102
1103 for (i = 0; i < 8; ++i) {
1104 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1105 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1106 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1107 continue;
1108 }
1109
1110 int idx = subpass->color_attachments[i].attachment;
1111 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1112 struct radv_image *image = att->attachment->image;
1113 VkImageLayout layout = subpass->color_attachments[i].layout;
1114
1115 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1116
1117 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1118 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1119
1120 radv_load_color_clear_regs(cmd_buffer, image, i);
1121 }
1122
1123 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1124 int idx = subpass->depth_stencil_attachment.attachment;
1125 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1126 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1127 struct radv_image *image = att->attachment->image;
1128 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1129 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1130 cmd_buffer->queue_family_index,
1131 cmd_buffer->queue_family_index);
1132 /* We currently don't support writing decompressed HTILE */
1133 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1134 radv_layout_is_htile_compressed(image, layout, queue_mask));
1135
1136 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1137
1138 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1139 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1140 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1141 }
1142 radv_load_depth_clear_regs(cmd_buffer, image);
1143 } else {
1144 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1145 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1146 else
1147 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1148
1149 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1150 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1151 }
1152 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1153 S_028208_BR_X(framebuffer->width) |
1154 S_028208_BR_Y(framebuffer->height));
1155
1156 if (cmd_buffer->device->dfsm_allowed) {
1157 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1158 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1159 }
1160
1161 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1162 }
1163
1164 static void
1165 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1166 {
1167 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1168 struct radv_cmd_state *state = &cmd_buffer->state;
1169
1170 if (state->index_type != state->last_index_type) {
1171 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1172 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1173 2, state->index_type);
1174 } else {
1175 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1176 radeon_emit(cs, state->index_type);
1177 }
1178
1179 state->last_index_type = state->index_type;
1180 }
1181
1182 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1183 radeon_emit(cs, state->index_va);
1184 radeon_emit(cs, state->index_va >> 32);
1185
1186 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1187 radeon_emit(cs, state->max_index_count);
1188
1189 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1190 }
1191
1192 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1193 {
1194 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1195 uint32_t pa_sc_mode_cntl_1 =
1196 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1197 uint32_t db_count_control;
1198
1199 if(!cmd_buffer->state.active_occlusion_queries) {
1200 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1201 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1202 pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
1203 /* Re-enable out-of-order rasterization if the
1204 * bound pipeline supports it and if it's has
1205 * been disabled before starting occlusion
1206 * queries.
1207 */
1208 radeon_set_context_reg(cmd_buffer->cs,
1209 R_028A4C_PA_SC_MODE_CNTL_1,
1210 pa_sc_mode_cntl_1);
1211 }
1212 db_count_control = 0;
1213 } else {
1214 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1215 }
1216 } else {
1217 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1218 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1219
1220 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1221 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1222 S_028004_SAMPLE_RATE(sample_rate) |
1223 S_028004_ZPASS_ENABLE(1) |
1224 S_028004_SLICE_EVEN_ENABLE(1) |
1225 S_028004_SLICE_ODD_ENABLE(1);
1226
1227 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1228 pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
1229 /* If the bound pipeline has enabled
1230 * out-of-order rasterization, we should
1231 * disable it before starting occlusion
1232 * queries.
1233 */
1234 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1235
1236 radeon_set_context_reg(cmd_buffer->cs,
1237 R_028A4C_PA_SC_MODE_CNTL_1,
1238 pa_sc_mode_cntl_1);
1239 }
1240 } else {
1241 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1242 S_028004_SAMPLE_RATE(sample_rate);
1243 }
1244 }
1245
1246 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1247 }
1248
1249 static void
1250 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1251 {
1252 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1253
1254 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1255 radv_emit_viewport(cmd_buffer);
1256
1257 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1258 radv_emit_scissor(cmd_buffer);
1259
1260 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1261 radv_emit_line_width(cmd_buffer);
1262
1263 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1264 radv_emit_blend_constants(cmd_buffer);
1265
1266 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1267 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1268 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1269 radv_emit_stencil(cmd_buffer);
1270
1271 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1272 radv_emit_depth_bounds(cmd_buffer);
1273
1274 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1275 radv_emit_depth_bias(cmd_buffer);
1276
1277 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1278 radv_emit_discard_rectangle(cmd_buffer);
1279
1280 cmd_buffer->state.dirty &= ~states;
1281 }
1282
1283 static void
1284 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1285 struct radv_pipeline *pipeline,
1286 int idx,
1287 uint64_t va,
1288 gl_shader_stage stage)
1289 {
1290 struct radv_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1291 uint32_t base_reg = pipeline->user_data_0[stage];
1292
1293 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1294 return;
1295
1296 assert(!desc_set_loc->indirect);
1297 assert(desc_set_loc->num_sgprs == 2);
1298 radeon_set_sh_reg_seq(cmd_buffer->cs,
1299 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1300 radeon_emit(cmd_buffer->cs, va);
1301 radeon_emit(cmd_buffer->cs, va >> 32);
1302 }
1303
1304 static void
1305 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1306 VkShaderStageFlags stages,
1307 struct radv_descriptor_set *set,
1308 unsigned idx)
1309 {
1310 if (cmd_buffer->state.pipeline) {
1311 radv_foreach_stage(stage, stages) {
1312 if (cmd_buffer->state.pipeline->shaders[stage])
1313 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1314 idx, set->va,
1315 stage);
1316 }
1317 }
1318
1319 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1320 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1321 idx, set->va,
1322 MESA_SHADER_COMPUTE);
1323 }
1324
1325 static void
1326 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1327 VkPipelineBindPoint bind_point)
1328 {
1329 struct radv_descriptor_state *descriptors_state =
1330 radv_get_descriptors_state(cmd_buffer, bind_point);
1331 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1332 unsigned bo_offset;
1333
1334 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1335 set->mapped_ptr,
1336 &bo_offset))
1337 return;
1338
1339 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1340 set->va += bo_offset;
1341 }
1342
1343 static void
1344 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1345 VkPipelineBindPoint bind_point)
1346 {
1347 struct radv_descriptor_state *descriptors_state =
1348 radv_get_descriptors_state(cmd_buffer, bind_point);
1349 uint32_t size = MAX_SETS * 2 * 4;
1350 uint32_t offset;
1351 void *ptr;
1352
1353 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1354 256, &offset, &ptr))
1355 return;
1356
1357 for (unsigned i = 0; i < MAX_SETS; i++) {
1358 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1359 uint64_t set_va = 0;
1360 struct radv_descriptor_set *set = descriptors_state->sets[i];
1361 if (descriptors_state->valid & (1u << i))
1362 set_va = set->va;
1363 uptr[0] = set_va & 0xffffffff;
1364 uptr[1] = set_va >> 32;
1365 }
1366
1367 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1368 va += offset;
1369
1370 if (cmd_buffer->state.pipeline) {
1371 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1372 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1373 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1374
1375 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1376 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1377 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1378
1379 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1380 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1381 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1382
1383 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1384 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1385 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1386
1387 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1388 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1389 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1390 }
1391
1392 if (cmd_buffer->state.compute_pipeline)
1393 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1394 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1395 }
1396
1397 static void
1398 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1399 VkShaderStageFlags stages)
1400 {
1401 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1402 VK_PIPELINE_BIND_POINT_COMPUTE :
1403 VK_PIPELINE_BIND_POINT_GRAPHICS;
1404 struct radv_descriptor_state *descriptors_state =
1405 radv_get_descriptors_state(cmd_buffer, bind_point);
1406 unsigned i;
1407
1408 if (!descriptors_state->dirty)
1409 return;
1410
1411 if (descriptors_state->push_dirty)
1412 radv_flush_push_descriptors(cmd_buffer, bind_point);
1413
1414 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1415 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1416 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1417 }
1418
1419 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1420 cmd_buffer->cs,
1421 MAX_SETS * MESA_SHADER_STAGES * 4);
1422
1423 for_each_bit(i, descriptors_state->dirty) {
1424 struct radv_descriptor_set *set = descriptors_state->sets[i];
1425 if (!(descriptors_state->valid & (1u << i)))
1426 continue;
1427
1428 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1429 }
1430 descriptors_state->dirty = 0;
1431 descriptors_state->push_dirty = false;
1432
1433 if (unlikely(cmd_buffer->device->trace_bo))
1434 radv_save_descriptors(cmd_buffer, bind_point);
1435
1436 assert(cmd_buffer->cs->cdw <= cdw_max);
1437 }
1438
1439 static void
1440 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1441 struct radv_pipeline *pipeline,
1442 VkShaderStageFlags stages)
1443 {
1444 struct radv_pipeline_layout *layout = pipeline->layout;
1445 unsigned offset;
1446 void *ptr;
1447 uint64_t va;
1448
1449 stages &= cmd_buffer->push_constant_stages;
1450 if (!stages ||
1451 (!layout->push_constant_size && !layout->dynamic_offset_count))
1452 return;
1453
1454 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1455 16 * layout->dynamic_offset_count,
1456 256, &offset, &ptr))
1457 return;
1458
1459 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1460 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1461 16 * layout->dynamic_offset_count);
1462
1463 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1464 va += offset;
1465
1466 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1467 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1468
1469 radv_foreach_stage(stage, stages) {
1470 if (pipeline->shaders[stage]) {
1471 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1472 AC_UD_PUSH_CONSTANTS, va);
1473 }
1474 }
1475
1476 cmd_buffer->push_constant_stages &= ~stages;
1477 assert(cmd_buffer->cs->cdw <= cdw_max);
1478 }
1479
1480 static bool
1481 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1482 {
1483 if ((pipeline_is_dirty ||
1484 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1485 cmd_buffer->state.pipeline->vertex_elements.count &&
1486 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1487 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1488 unsigned vb_offset;
1489 void *vb_ptr;
1490 uint32_t i = 0;
1491 uint32_t count = velems->count;
1492 uint64_t va;
1493
1494 /* allocate some descriptor state for vertex buffers */
1495 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1496 &vb_offset, &vb_ptr))
1497 return false;
1498
1499 for (i = 0; i < count; i++) {
1500 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1501 uint32_t offset;
1502 int vb = velems->binding[i];
1503 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1504 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1505
1506 va = radv_buffer_get_va(buffer->bo);
1507
1508 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1509 va += offset + buffer->offset;
1510 desc[0] = va;
1511 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1512 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1513 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1514 else
1515 desc[2] = buffer->size - offset;
1516 desc[3] = velems->rsrc_word3[i];
1517 }
1518
1519 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1520 va += vb_offset;
1521
1522 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1523 AC_UD_VS_VERTEX_BUFFERS, va);
1524
1525 cmd_buffer->state.vb_va = va;
1526 cmd_buffer->state.vb_size = count * 16;
1527 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1528 }
1529 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1530
1531 return true;
1532 }
1533
1534 static bool
1535 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1536 {
1537 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1538 return false;
1539
1540 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1541 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1542 VK_SHADER_STAGE_ALL_GRAPHICS);
1543
1544 return true;
1545 }
1546
1547 static void
1548 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1549 bool instanced_draw, bool indirect_draw,
1550 uint32_t draw_vertex_count)
1551 {
1552 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1553 struct radv_cmd_state *state = &cmd_buffer->state;
1554 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1555 uint32_t ia_multi_vgt_param;
1556 int32_t primitive_reset_en;
1557
1558 /* Draw state. */
1559 ia_multi_vgt_param =
1560 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1561 indirect_draw, draw_vertex_count);
1562
1563 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1564 if (info->chip_class >= GFX9) {
1565 radeon_set_uconfig_reg_idx(cs,
1566 R_030960_IA_MULTI_VGT_PARAM,
1567 4, ia_multi_vgt_param);
1568 } else if (info->chip_class >= CIK) {
1569 radeon_set_context_reg_idx(cs,
1570 R_028AA8_IA_MULTI_VGT_PARAM,
1571 1, ia_multi_vgt_param);
1572 } else {
1573 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1574 ia_multi_vgt_param);
1575 }
1576 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1577 }
1578
1579 /* Primitive restart. */
1580 primitive_reset_en =
1581 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1582
1583 if (primitive_reset_en != state->last_primitive_reset_en) {
1584 state->last_primitive_reset_en = primitive_reset_en;
1585 if (info->chip_class >= GFX9) {
1586 radeon_set_uconfig_reg(cs,
1587 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1588 primitive_reset_en);
1589 } else {
1590 radeon_set_context_reg(cs,
1591 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1592 primitive_reset_en);
1593 }
1594 }
1595
1596 if (primitive_reset_en) {
1597 uint32_t primitive_reset_index =
1598 state->index_type ? 0xffffffffu : 0xffffu;
1599
1600 if (primitive_reset_index != state->last_primitive_reset_index) {
1601 radeon_set_context_reg(cs,
1602 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1603 primitive_reset_index);
1604 state->last_primitive_reset_index = primitive_reset_index;
1605 }
1606 }
1607 }
1608
1609 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1610 VkPipelineStageFlags src_stage_mask)
1611 {
1612 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1613 VK_PIPELINE_STAGE_TRANSFER_BIT |
1614 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1615 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1616 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1617 }
1618
1619 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1620 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1621 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1622 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1623 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1624 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1625 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1626 VK_PIPELINE_STAGE_TRANSFER_BIT |
1627 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1628 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1629 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1630 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1631 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1632 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1633 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1634 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1635 }
1636 }
1637
1638 static enum radv_cmd_flush_bits
1639 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1640 VkAccessFlags src_flags)
1641 {
1642 enum radv_cmd_flush_bits flush_bits = 0;
1643 uint32_t b;
1644 for_each_bit(b, src_flags) {
1645 switch ((VkAccessFlagBits)(1 << b)) {
1646 case VK_ACCESS_SHADER_WRITE_BIT:
1647 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1648 break;
1649 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1650 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1651 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1652 break;
1653 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1654 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1655 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1656 break;
1657 case VK_ACCESS_TRANSFER_WRITE_BIT:
1658 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1659 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1660 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1661 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1662 RADV_CMD_FLAG_INV_GLOBAL_L2;
1663 break;
1664 default:
1665 break;
1666 }
1667 }
1668 return flush_bits;
1669 }
1670
1671 static enum radv_cmd_flush_bits
1672 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1673 VkAccessFlags dst_flags,
1674 struct radv_image *image)
1675 {
1676 enum radv_cmd_flush_bits flush_bits = 0;
1677 uint32_t b;
1678 for_each_bit(b, dst_flags) {
1679 switch ((VkAccessFlagBits)(1 << b)) {
1680 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1681 case VK_ACCESS_INDEX_READ_BIT:
1682 break;
1683 case VK_ACCESS_UNIFORM_READ_BIT:
1684 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1685 break;
1686 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1687 case VK_ACCESS_SHADER_READ_BIT:
1688 case VK_ACCESS_TRANSFER_READ_BIT:
1689 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1690 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1691 RADV_CMD_FLAG_INV_GLOBAL_L2;
1692 break;
1693 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1694 /* TODO: change to image && when the image gets passed
1695 * through from the subpass. */
1696 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1697 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1698 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1699 break;
1700 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1701 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1702 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1703 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1704 break;
1705 default:
1706 break;
1707 }
1708 }
1709 return flush_bits;
1710 }
1711
1712 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1713 {
1714 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1715 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1716 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1717 NULL);
1718 }
1719
1720 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1721 VkAttachmentReference att)
1722 {
1723 unsigned idx = att.attachment;
1724 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1725 VkImageSubresourceRange range;
1726 range.aspectMask = 0;
1727 range.baseMipLevel = view->base_mip;
1728 range.levelCount = 1;
1729 range.baseArrayLayer = view->base_layer;
1730 range.layerCount = cmd_buffer->state.framebuffer->layers;
1731
1732 radv_handle_image_transition(cmd_buffer,
1733 view->image,
1734 cmd_buffer->state.attachments[idx].current_layout,
1735 att.layout, 0, 0, &range,
1736 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1737
1738 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1739
1740
1741 }
1742
1743 void
1744 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1745 const struct radv_subpass *subpass, bool transitions)
1746 {
1747 if (transitions) {
1748 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1749
1750 for (unsigned i = 0; i < subpass->color_count; ++i) {
1751 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1752 radv_handle_subpass_image_transition(cmd_buffer,
1753 subpass->color_attachments[i]);
1754 }
1755
1756 for (unsigned i = 0; i < subpass->input_count; ++i) {
1757 radv_handle_subpass_image_transition(cmd_buffer,
1758 subpass->input_attachments[i]);
1759 }
1760
1761 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1762 radv_handle_subpass_image_transition(cmd_buffer,
1763 subpass->depth_stencil_attachment);
1764 }
1765 }
1766
1767 cmd_buffer->state.subpass = subpass;
1768
1769 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
1770 }
1771
1772 static VkResult
1773 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1774 struct radv_render_pass *pass,
1775 const VkRenderPassBeginInfo *info)
1776 {
1777 struct radv_cmd_state *state = &cmd_buffer->state;
1778
1779 if (pass->attachment_count == 0) {
1780 state->attachments = NULL;
1781 return VK_SUCCESS;
1782 }
1783
1784 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1785 pass->attachment_count *
1786 sizeof(state->attachments[0]),
1787 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1788 if (state->attachments == NULL) {
1789 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1790 return cmd_buffer->record_result;
1791 }
1792
1793 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1794 struct radv_render_pass_attachment *att = &pass->attachments[i];
1795 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1796 VkImageAspectFlags clear_aspects = 0;
1797
1798 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1799 /* color attachment */
1800 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1801 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1802 }
1803 } else {
1804 /* depthstencil attachment */
1805 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1806 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1807 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1808 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1809 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1810 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1811 }
1812 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1813 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1814 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1815 }
1816 }
1817
1818 state->attachments[i].pending_clear_aspects = clear_aspects;
1819 state->attachments[i].cleared_views = 0;
1820 if (clear_aspects && info) {
1821 assert(info->clearValueCount > i);
1822 state->attachments[i].clear_value = info->pClearValues[i];
1823 }
1824
1825 state->attachments[i].current_layout = att->initial_layout;
1826 }
1827
1828 return VK_SUCCESS;
1829 }
1830
1831 VkResult radv_AllocateCommandBuffers(
1832 VkDevice _device,
1833 const VkCommandBufferAllocateInfo *pAllocateInfo,
1834 VkCommandBuffer *pCommandBuffers)
1835 {
1836 RADV_FROM_HANDLE(radv_device, device, _device);
1837 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1838
1839 VkResult result = VK_SUCCESS;
1840 uint32_t i;
1841
1842 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1843
1844 if (!list_empty(&pool->free_cmd_buffers)) {
1845 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1846
1847 list_del(&cmd_buffer->pool_link);
1848 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1849
1850 result = radv_reset_cmd_buffer(cmd_buffer);
1851 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1852 cmd_buffer->level = pAllocateInfo->level;
1853
1854 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1855 } else {
1856 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1857 &pCommandBuffers[i]);
1858 }
1859 if (result != VK_SUCCESS)
1860 break;
1861 }
1862
1863 if (result != VK_SUCCESS) {
1864 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1865 i, pCommandBuffers);
1866
1867 /* From the Vulkan 1.0.66 spec:
1868 *
1869 * "vkAllocateCommandBuffers can be used to create multiple
1870 * command buffers. If the creation of any of those command
1871 * buffers fails, the implementation must destroy all
1872 * successfully created command buffer objects from this
1873 * command, set all entries of the pCommandBuffers array to
1874 * NULL and return the error."
1875 */
1876 memset(pCommandBuffers, 0,
1877 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1878 }
1879
1880 return result;
1881 }
1882
1883 void radv_FreeCommandBuffers(
1884 VkDevice device,
1885 VkCommandPool commandPool,
1886 uint32_t commandBufferCount,
1887 const VkCommandBuffer *pCommandBuffers)
1888 {
1889 for (uint32_t i = 0; i < commandBufferCount; i++) {
1890 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1891
1892 if (cmd_buffer) {
1893 if (cmd_buffer->pool) {
1894 list_del(&cmd_buffer->pool_link);
1895 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1896 } else
1897 radv_cmd_buffer_destroy(cmd_buffer);
1898
1899 }
1900 }
1901 }
1902
1903 VkResult radv_ResetCommandBuffer(
1904 VkCommandBuffer commandBuffer,
1905 VkCommandBufferResetFlags flags)
1906 {
1907 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1908 return radv_reset_cmd_buffer(cmd_buffer);
1909 }
1910
1911 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1912 {
1913 struct radv_device *device = cmd_buffer->device;
1914 if (device->gfx_init) {
1915 uint64_t va = radv_buffer_get_va(device->gfx_init);
1916 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
1917 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1918 radeon_emit(cmd_buffer->cs, va);
1919 radeon_emit(cmd_buffer->cs, va >> 32);
1920 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1921 } else
1922 si_init_config(cmd_buffer);
1923 }
1924
1925 VkResult radv_BeginCommandBuffer(
1926 VkCommandBuffer commandBuffer,
1927 const VkCommandBufferBeginInfo *pBeginInfo)
1928 {
1929 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1930 VkResult result = VK_SUCCESS;
1931
1932 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
1933 /* If the command buffer has already been resetted with
1934 * vkResetCommandBuffer, no need to do it again.
1935 */
1936 result = radv_reset_cmd_buffer(cmd_buffer);
1937 if (result != VK_SUCCESS)
1938 return result;
1939 }
1940
1941 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1942 cmd_buffer->state.last_primitive_reset_en = -1;
1943 cmd_buffer->state.last_index_type = -1;
1944 cmd_buffer->state.last_num_instances = -1;
1945 cmd_buffer->state.last_vertex_offset = -1;
1946 cmd_buffer->state.last_first_instance = -1;
1947 cmd_buffer->usage_flags = pBeginInfo->flags;
1948
1949 /* setup initial configuration into command buffer */
1950 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1951 switch (cmd_buffer->queue_family_index) {
1952 case RADV_QUEUE_GENERAL:
1953 emit_gfx_buffer_state(cmd_buffer);
1954 break;
1955 case RADV_QUEUE_COMPUTE:
1956 si_init_compute(cmd_buffer);
1957 break;
1958 case RADV_QUEUE_TRANSFER:
1959 default:
1960 break;
1961 }
1962 }
1963
1964 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1965 assert(pBeginInfo->pInheritanceInfo);
1966 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1967 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1968
1969 struct radv_subpass *subpass =
1970 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1971
1972 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1973 if (result != VK_SUCCESS)
1974 return result;
1975
1976 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1977 }
1978
1979 if (unlikely(cmd_buffer->device->trace_bo))
1980 radv_cmd_buffer_trace_emit(cmd_buffer);
1981
1982 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
1983
1984 return result;
1985 }
1986
1987 void radv_CmdBindVertexBuffers(
1988 VkCommandBuffer commandBuffer,
1989 uint32_t firstBinding,
1990 uint32_t bindingCount,
1991 const VkBuffer* pBuffers,
1992 const VkDeviceSize* pOffsets)
1993 {
1994 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1995 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
1996 bool changed = false;
1997
1998 /* We have to defer setting up vertex buffer since we need the buffer
1999 * stride from the pipeline. */
2000
2001 assert(firstBinding + bindingCount <= MAX_VBS);
2002 for (uint32_t i = 0; i < bindingCount; i++) {
2003 uint32_t idx = firstBinding + i;
2004
2005 if (!changed &&
2006 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2007 vb[idx].offset != pOffsets[i])) {
2008 changed = true;
2009 }
2010
2011 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2012 vb[idx].offset = pOffsets[i];
2013
2014 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2015 vb[idx].buffer->bo, 8);
2016 }
2017
2018 if (!changed) {
2019 /* No state changes. */
2020 return;
2021 }
2022
2023 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2024 }
2025
2026 void radv_CmdBindIndexBuffer(
2027 VkCommandBuffer commandBuffer,
2028 VkBuffer buffer,
2029 VkDeviceSize offset,
2030 VkIndexType indexType)
2031 {
2032 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2033 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2034
2035 if (cmd_buffer->state.index_buffer == index_buffer &&
2036 cmd_buffer->state.index_offset == offset &&
2037 cmd_buffer->state.index_type == indexType) {
2038 /* No state changes. */
2039 return;
2040 }
2041
2042 cmd_buffer->state.index_buffer = index_buffer;
2043 cmd_buffer->state.index_offset = offset;
2044 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2045 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2046 cmd_buffer->state.index_va += index_buffer->offset + offset;
2047
2048 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2049 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2050 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2051 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2052 }
2053
2054
2055 static void
2056 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2057 VkPipelineBindPoint bind_point,
2058 struct radv_descriptor_set *set, unsigned idx)
2059 {
2060 struct radeon_winsys *ws = cmd_buffer->device->ws;
2061
2062 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2063 if (!set)
2064 return;
2065
2066 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2067
2068 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2069 if (set->descriptors[j])
2070 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2071
2072 if(set->bo)
2073 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2074 }
2075
2076 void radv_CmdBindDescriptorSets(
2077 VkCommandBuffer commandBuffer,
2078 VkPipelineBindPoint pipelineBindPoint,
2079 VkPipelineLayout _layout,
2080 uint32_t firstSet,
2081 uint32_t descriptorSetCount,
2082 const VkDescriptorSet* pDescriptorSets,
2083 uint32_t dynamicOffsetCount,
2084 const uint32_t* pDynamicOffsets)
2085 {
2086 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2087 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2088 unsigned dyn_idx = 0;
2089
2090 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2091 unsigned idx = i + firstSet;
2092 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2093 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2094
2095 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2096 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2097 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2098 assert(dyn_idx < dynamicOffsetCount);
2099
2100 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2101 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2102 dst[0] = va;
2103 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2104 dst[2] = range->size;
2105 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2106 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2107 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2108 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2109 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2110 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2111 cmd_buffer->push_constant_stages |=
2112 set->layout->dynamic_shader_stages;
2113 }
2114 }
2115 }
2116
2117 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2118 struct radv_descriptor_set *set,
2119 struct radv_descriptor_set_layout *layout,
2120 VkPipelineBindPoint bind_point)
2121 {
2122 struct radv_descriptor_state *descriptors_state =
2123 radv_get_descriptors_state(cmd_buffer, bind_point);
2124 set->size = layout->size;
2125 set->layout = layout;
2126
2127 if (descriptors_state->push_set.capacity < set->size) {
2128 size_t new_size = MAX2(set->size, 1024);
2129 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2130 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2131
2132 free(set->mapped_ptr);
2133 set->mapped_ptr = malloc(new_size);
2134
2135 if (!set->mapped_ptr) {
2136 descriptors_state->push_set.capacity = 0;
2137 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2138 return false;
2139 }
2140
2141 descriptors_state->push_set.capacity = new_size;
2142 }
2143
2144 return true;
2145 }
2146
2147 void radv_meta_push_descriptor_set(
2148 struct radv_cmd_buffer* cmd_buffer,
2149 VkPipelineBindPoint pipelineBindPoint,
2150 VkPipelineLayout _layout,
2151 uint32_t set,
2152 uint32_t descriptorWriteCount,
2153 const VkWriteDescriptorSet* pDescriptorWrites)
2154 {
2155 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2156 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2157 unsigned bo_offset;
2158
2159 assert(set == 0);
2160 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2161
2162 push_set->size = layout->set[set].layout->size;
2163 push_set->layout = layout->set[set].layout;
2164
2165 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2166 &bo_offset,
2167 (void**) &push_set->mapped_ptr))
2168 return;
2169
2170 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2171 push_set->va += bo_offset;
2172
2173 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2174 radv_descriptor_set_to_handle(push_set),
2175 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2176
2177 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2178 }
2179
2180 void radv_CmdPushDescriptorSetKHR(
2181 VkCommandBuffer commandBuffer,
2182 VkPipelineBindPoint pipelineBindPoint,
2183 VkPipelineLayout _layout,
2184 uint32_t set,
2185 uint32_t descriptorWriteCount,
2186 const VkWriteDescriptorSet* pDescriptorWrites)
2187 {
2188 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2189 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2190 struct radv_descriptor_state *descriptors_state =
2191 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2192 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2193
2194 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2195
2196 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2197 layout->set[set].layout,
2198 pipelineBindPoint))
2199 return;
2200
2201 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2202 radv_descriptor_set_to_handle(push_set),
2203 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2204
2205 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2206 descriptors_state->push_dirty = true;
2207 }
2208
2209 void radv_CmdPushDescriptorSetWithTemplateKHR(
2210 VkCommandBuffer commandBuffer,
2211 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2212 VkPipelineLayout _layout,
2213 uint32_t set,
2214 const void* pData)
2215 {
2216 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2217 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2218 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2219 struct radv_descriptor_state *descriptors_state =
2220 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2221 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2222
2223 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2224
2225 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2226 layout->set[set].layout,
2227 templ->bind_point))
2228 return;
2229
2230 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2231 descriptorUpdateTemplate, pData);
2232
2233 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2234 descriptors_state->push_dirty = true;
2235 }
2236
2237 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2238 VkPipelineLayout layout,
2239 VkShaderStageFlags stageFlags,
2240 uint32_t offset,
2241 uint32_t size,
2242 const void* pValues)
2243 {
2244 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2245 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2246 cmd_buffer->push_constant_stages |= stageFlags;
2247 }
2248
2249 VkResult radv_EndCommandBuffer(
2250 VkCommandBuffer commandBuffer)
2251 {
2252 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2253
2254 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2255 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2256 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2257 si_emit_cache_flush(cmd_buffer);
2258 }
2259
2260 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2261
2262 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2263 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2264
2265 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2266
2267 return cmd_buffer->record_result;
2268 }
2269
2270 static void
2271 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2272 {
2273 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2274
2275 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2276 return;
2277
2278 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2279
2280 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2281 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2282
2283 cmd_buffer->compute_scratch_size_needed =
2284 MAX2(cmd_buffer->compute_scratch_size_needed,
2285 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2286
2287 if (unlikely(cmd_buffer->device->trace_bo))
2288 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2289 }
2290
2291 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2292 VkPipelineBindPoint bind_point)
2293 {
2294 struct radv_descriptor_state *descriptors_state =
2295 radv_get_descriptors_state(cmd_buffer, bind_point);
2296
2297 descriptors_state->dirty |= descriptors_state->valid;
2298 }
2299
2300 void radv_CmdBindPipeline(
2301 VkCommandBuffer commandBuffer,
2302 VkPipelineBindPoint pipelineBindPoint,
2303 VkPipeline _pipeline)
2304 {
2305 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2306 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2307
2308 switch (pipelineBindPoint) {
2309 case VK_PIPELINE_BIND_POINT_COMPUTE:
2310 if (cmd_buffer->state.compute_pipeline == pipeline)
2311 return;
2312 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2313
2314 cmd_buffer->state.compute_pipeline = pipeline;
2315 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2316 break;
2317 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2318 if (cmd_buffer->state.pipeline == pipeline)
2319 return;
2320 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2321
2322 cmd_buffer->state.pipeline = pipeline;
2323 if (!pipeline)
2324 break;
2325
2326 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2327 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2328
2329 /* the new vertex shader might not have the same user regs */
2330 cmd_buffer->state.last_first_instance = -1;
2331 cmd_buffer->state.last_vertex_offset = -1;
2332
2333 /* Prefetch all pipeline shaders at first draw time. */
2334 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2335
2336 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2337
2338 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2339 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2340 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2341 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2342
2343 if (radv_pipeline_has_tess(pipeline))
2344 cmd_buffer->tess_rings_needed = true;
2345
2346 if (radv_pipeline_has_gs(pipeline)) {
2347 struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2348 AC_UD_SCRATCH_RING_OFFSETS);
2349 if (cmd_buffer->ring_offsets_idx == -1)
2350 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2351 else if (loc->sgpr_idx != -1)
2352 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2353 }
2354 break;
2355 default:
2356 assert(!"invalid bind point");
2357 break;
2358 }
2359 }
2360
2361 void radv_CmdSetViewport(
2362 VkCommandBuffer commandBuffer,
2363 uint32_t firstViewport,
2364 uint32_t viewportCount,
2365 const VkViewport* pViewports)
2366 {
2367 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2368 struct radv_cmd_state *state = &cmd_buffer->state;
2369 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2370
2371 assert(firstViewport < MAX_VIEWPORTS);
2372 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2373
2374 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2375 /* Try to skip unnecessary PS partial flushes when the viewports
2376 * don't change.
2377 */
2378 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2379 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2380 !memcmp(state->dynamic.viewport.viewports + firstViewport,
2381 pViewports, viewportCount * sizeof(*pViewports))) {
2382 return;
2383 }
2384 }
2385
2386 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2387 viewportCount * sizeof(*pViewports));
2388
2389 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2390 }
2391
2392 void radv_CmdSetScissor(
2393 VkCommandBuffer commandBuffer,
2394 uint32_t firstScissor,
2395 uint32_t scissorCount,
2396 const VkRect2D* pScissors)
2397 {
2398 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2399 struct radv_cmd_state *state = &cmd_buffer->state;
2400 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2401
2402 assert(firstScissor < MAX_SCISSORS);
2403 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2404
2405 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2406 /* Try to skip unnecessary PS partial flushes when the scissors
2407 * don't change.
2408 */
2409 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2410 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2411 !memcmp(state->dynamic.scissor.scissors + firstScissor,
2412 pScissors, scissorCount * sizeof(*pScissors))) {
2413 return;
2414 }
2415 }
2416
2417 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2418 scissorCount * sizeof(*pScissors));
2419
2420 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2421 }
2422
2423 void radv_CmdSetLineWidth(
2424 VkCommandBuffer commandBuffer,
2425 float lineWidth)
2426 {
2427 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2428 cmd_buffer->state.dynamic.line_width = lineWidth;
2429 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2430 }
2431
2432 void radv_CmdSetDepthBias(
2433 VkCommandBuffer commandBuffer,
2434 float depthBiasConstantFactor,
2435 float depthBiasClamp,
2436 float depthBiasSlopeFactor)
2437 {
2438 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2439
2440 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2441 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2442 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2443
2444 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2445 }
2446
2447 void radv_CmdSetBlendConstants(
2448 VkCommandBuffer commandBuffer,
2449 const float blendConstants[4])
2450 {
2451 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2452
2453 memcpy(cmd_buffer->state.dynamic.blend_constants,
2454 blendConstants, sizeof(float) * 4);
2455
2456 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2457 }
2458
2459 void radv_CmdSetDepthBounds(
2460 VkCommandBuffer commandBuffer,
2461 float minDepthBounds,
2462 float maxDepthBounds)
2463 {
2464 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2465
2466 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2467 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2468
2469 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2470 }
2471
2472 void radv_CmdSetStencilCompareMask(
2473 VkCommandBuffer commandBuffer,
2474 VkStencilFaceFlags faceMask,
2475 uint32_t compareMask)
2476 {
2477 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2478
2479 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2480 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2481 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2482 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2483
2484 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2485 }
2486
2487 void radv_CmdSetStencilWriteMask(
2488 VkCommandBuffer commandBuffer,
2489 VkStencilFaceFlags faceMask,
2490 uint32_t writeMask)
2491 {
2492 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2493
2494 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2495 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2496 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2497 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2498
2499 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2500 }
2501
2502 void radv_CmdSetStencilReference(
2503 VkCommandBuffer commandBuffer,
2504 VkStencilFaceFlags faceMask,
2505 uint32_t reference)
2506 {
2507 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2508
2509 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2510 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2511 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2512 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2513
2514 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2515 }
2516
2517 void radv_CmdSetDiscardRectangleEXT(
2518 VkCommandBuffer commandBuffer,
2519 uint32_t firstDiscardRectangle,
2520 uint32_t discardRectangleCount,
2521 const VkRect2D* pDiscardRectangles)
2522 {
2523 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2524 struct radv_cmd_state *state = &cmd_buffer->state;
2525 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2526
2527 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2528 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2529
2530 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2531 pDiscardRectangles, discardRectangleCount);
2532
2533 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2534 }
2535
2536 void radv_CmdExecuteCommands(
2537 VkCommandBuffer commandBuffer,
2538 uint32_t commandBufferCount,
2539 const VkCommandBuffer* pCmdBuffers)
2540 {
2541 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2542
2543 assert(commandBufferCount > 0);
2544
2545 /* Emit pending flushes on primary prior to executing secondary */
2546 si_emit_cache_flush(primary);
2547
2548 for (uint32_t i = 0; i < commandBufferCount; i++) {
2549 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2550
2551 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2552 secondary->scratch_size_needed);
2553 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2554 secondary->compute_scratch_size_needed);
2555
2556 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2557 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2558 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2559 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2560 if (secondary->tess_rings_needed)
2561 primary->tess_rings_needed = true;
2562 if (secondary->sample_positions_needed)
2563 primary->sample_positions_needed = true;
2564
2565 if (secondary->ring_offsets_idx != -1) {
2566 if (primary->ring_offsets_idx == -1)
2567 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2568 else
2569 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2570 }
2571 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2572
2573
2574 /* When the secondary command buffer is compute only we don't
2575 * need to re-emit the current graphics pipeline.
2576 */
2577 if (secondary->state.emitted_pipeline) {
2578 primary->state.emitted_pipeline =
2579 secondary->state.emitted_pipeline;
2580 }
2581
2582 /* When the secondary command buffer is graphics only we don't
2583 * need to re-emit the current compute pipeline.
2584 */
2585 if (secondary->state.emitted_compute_pipeline) {
2586 primary->state.emitted_compute_pipeline =
2587 secondary->state.emitted_compute_pipeline;
2588 }
2589
2590 /* Only re-emit the draw packets when needed. */
2591 if (secondary->state.last_primitive_reset_en != -1) {
2592 primary->state.last_primitive_reset_en =
2593 secondary->state.last_primitive_reset_en;
2594 }
2595
2596 if (secondary->state.last_primitive_reset_index) {
2597 primary->state.last_primitive_reset_index =
2598 secondary->state.last_primitive_reset_index;
2599 }
2600
2601 if (secondary->state.last_ia_multi_vgt_param) {
2602 primary->state.last_ia_multi_vgt_param =
2603 secondary->state.last_ia_multi_vgt_param;
2604 }
2605
2606 if (secondary->state.last_first_instance != -1) {
2607 primary->state.last_first_instance =
2608 secondary->state.last_first_instance;
2609 }
2610
2611 if (secondary->state.last_num_instances != -1) {
2612 primary->state.last_num_instances =
2613 secondary->state.last_num_instances;
2614 }
2615
2616 if (secondary->state.last_vertex_offset != -1) {
2617 primary->state.last_vertex_offset =
2618 secondary->state.last_vertex_offset;
2619 }
2620
2621 if (secondary->state.last_index_type != -1) {
2622 primary->state.last_index_type =
2623 secondary->state.last_index_type;
2624 }
2625 }
2626
2627 /* After executing commands from secondary buffers we have to dirty
2628 * some states.
2629 */
2630 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2631 RADV_CMD_DIRTY_INDEX_BUFFER |
2632 RADV_CMD_DIRTY_DYNAMIC_ALL;
2633 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2634 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2635 }
2636
2637 VkResult radv_CreateCommandPool(
2638 VkDevice _device,
2639 const VkCommandPoolCreateInfo* pCreateInfo,
2640 const VkAllocationCallbacks* pAllocator,
2641 VkCommandPool* pCmdPool)
2642 {
2643 RADV_FROM_HANDLE(radv_device, device, _device);
2644 struct radv_cmd_pool *pool;
2645
2646 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2647 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2648 if (pool == NULL)
2649 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2650
2651 if (pAllocator)
2652 pool->alloc = *pAllocator;
2653 else
2654 pool->alloc = device->alloc;
2655
2656 list_inithead(&pool->cmd_buffers);
2657 list_inithead(&pool->free_cmd_buffers);
2658
2659 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2660
2661 *pCmdPool = radv_cmd_pool_to_handle(pool);
2662
2663 return VK_SUCCESS;
2664
2665 }
2666
2667 void radv_DestroyCommandPool(
2668 VkDevice _device,
2669 VkCommandPool commandPool,
2670 const VkAllocationCallbacks* pAllocator)
2671 {
2672 RADV_FROM_HANDLE(radv_device, device, _device);
2673 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2674
2675 if (!pool)
2676 return;
2677
2678 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2679 &pool->cmd_buffers, pool_link) {
2680 radv_cmd_buffer_destroy(cmd_buffer);
2681 }
2682
2683 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2684 &pool->free_cmd_buffers, pool_link) {
2685 radv_cmd_buffer_destroy(cmd_buffer);
2686 }
2687
2688 vk_free2(&device->alloc, pAllocator, pool);
2689 }
2690
2691 VkResult radv_ResetCommandPool(
2692 VkDevice device,
2693 VkCommandPool commandPool,
2694 VkCommandPoolResetFlags flags)
2695 {
2696 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2697 VkResult result;
2698
2699 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2700 &pool->cmd_buffers, pool_link) {
2701 result = radv_reset_cmd_buffer(cmd_buffer);
2702 if (result != VK_SUCCESS)
2703 return result;
2704 }
2705
2706 return VK_SUCCESS;
2707 }
2708
2709 void radv_TrimCommandPool(
2710 VkDevice device,
2711 VkCommandPool commandPool,
2712 VkCommandPoolTrimFlagsKHR flags)
2713 {
2714 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2715
2716 if (!pool)
2717 return;
2718
2719 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2720 &pool->free_cmd_buffers, pool_link) {
2721 radv_cmd_buffer_destroy(cmd_buffer);
2722 }
2723 }
2724
2725 void radv_CmdBeginRenderPass(
2726 VkCommandBuffer commandBuffer,
2727 const VkRenderPassBeginInfo* pRenderPassBegin,
2728 VkSubpassContents contents)
2729 {
2730 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2731 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2732 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2733
2734 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2735 cmd_buffer->cs, 2048);
2736 MAYBE_UNUSED VkResult result;
2737
2738 cmd_buffer->state.framebuffer = framebuffer;
2739 cmd_buffer->state.pass = pass;
2740 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2741
2742 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2743 if (result != VK_SUCCESS)
2744 return;
2745
2746 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2747 assert(cmd_buffer->cs->cdw <= cdw_max);
2748
2749 radv_cmd_buffer_clear_subpass(cmd_buffer);
2750 }
2751
2752 void radv_CmdNextSubpass(
2753 VkCommandBuffer commandBuffer,
2754 VkSubpassContents contents)
2755 {
2756 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2757
2758 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2759
2760 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2761 2048);
2762
2763 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2764 radv_cmd_buffer_clear_subpass(cmd_buffer);
2765 }
2766
2767 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2768 {
2769 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2770 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2771 if (!pipeline->shaders[stage])
2772 continue;
2773 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2774 if (loc->sgpr_idx == -1)
2775 continue;
2776 uint32_t base_reg = pipeline->user_data_0[stage];
2777 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2778
2779 }
2780 if (pipeline->gs_copy_shader) {
2781 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2782 if (loc->sgpr_idx != -1) {
2783 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2784 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2785 }
2786 }
2787 }
2788
2789 static void
2790 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2791 uint32_t vertex_count)
2792 {
2793 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2794 radeon_emit(cmd_buffer->cs, vertex_count);
2795 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2796 S_0287F0_USE_OPAQUE(0));
2797 }
2798
2799 static void
2800 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2801 uint64_t index_va,
2802 uint32_t index_count)
2803 {
2804 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2805 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2806 radeon_emit(cmd_buffer->cs, index_va);
2807 radeon_emit(cmd_buffer->cs, index_va >> 32);
2808 radeon_emit(cmd_buffer->cs, index_count);
2809 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2810 }
2811
2812 static void
2813 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2814 bool indexed,
2815 uint32_t draw_count,
2816 uint64_t count_va,
2817 uint32_t stride)
2818 {
2819 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2820 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2821 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2822 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
2823 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2824 assert(base_reg);
2825
2826 /* just reset draw state for vertex data */
2827 cmd_buffer->state.last_first_instance = -1;
2828 cmd_buffer->state.last_num_instances = -1;
2829 cmd_buffer->state.last_vertex_offset = -1;
2830
2831 if (draw_count == 1 && !count_va && !draw_id_enable) {
2832 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2833 PKT3_DRAW_INDIRECT, 3, false));
2834 radeon_emit(cs, 0);
2835 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2836 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2837 radeon_emit(cs, di_src_sel);
2838 } else {
2839 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2840 PKT3_DRAW_INDIRECT_MULTI,
2841 8, false));
2842 radeon_emit(cs, 0);
2843 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2844 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2845 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2846 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2847 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2848 radeon_emit(cs, draw_count); /* count */
2849 radeon_emit(cs, count_va); /* count_addr */
2850 radeon_emit(cs, count_va >> 32);
2851 radeon_emit(cs, stride); /* stride */
2852 radeon_emit(cs, di_src_sel);
2853 }
2854 }
2855
2856 struct radv_draw_info {
2857 /**
2858 * Number of vertices.
2859 */
2860 uint32_t count;
2861
2862 /**
2863 * Index of the first vertex.
2864 */
2865 int32_t vertex_offset;
2866
2867 /**
2868 * First instance id.
2869 */
2870 uint32_t first_instance;
2871
2872 /**
2873 * Number of instances.
2874 */
2875 uint32_t instance_count;
2876
2877 /**
2878 * First index (indexed draws only).
2879 */
2880 uint32_t first_index;
2881
2882 /**
2883 * Whether it's an indexed draw.
2884 */
2885 bool indexed;
2886
2887 /**
2888 * Indirect draw parameters resource.
2889 */
2890 struct radv_buffer *indirect;
2891 uint64_t indirect_offset;
2892 uint32_t stride;
2893
2894 /**
2895 * Draw count parameters resource.
2896 */
2897 struct radv_buffer *count_buffer;
2898 uint64_t count_buffer_offset;
2899 };
2900
2901 static void
2902 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
2903 const struct radv_draw_info *info)
2904 {
2905 struct radv_cmd_state *state = &cmd_buffer->state;
2906 struct radeon_winsys *ws = cmd_buffer->device->ws;
2907 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2908
2909 if (info->indirect) {
2910 uint64_t va = radv_buffer_get_va(info->indirect->bo);
2911 uint64_t count_va = 0;
2912
2913 va += info->indirect->offset + info->indirect_offset;
2914
2915 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
2916
2917 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2918 radeon_emit(cs, 1);
2919 radeon_emit(cs, va);
2920 radeon_emit(cs, va >> 32);
2921
2922 if (info->count_buffer) {
2923 count_va = radv_buffer_get_va(info->count_buffer->bo);
2924 count_va += info->count_buffer->offset +
2925 info->count_buffer_offset;
2926
2927 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
2928 }
2929
2930 if (!state->subpass->view_mask) {
2931 radv_cs_emit_indirect_draw_packet(cmd_buffer,
2932 info->indexed,
2933 info->count,
2934 count_va,
2935 info->stride);
2936 } else {
2937 unsigned i;
2938 for_each_bit(i, state->subpass->view_mask) {
2939 radv_emit_view_index(cmd_buffer, i);
2940
2941 radv_cs_emit_indirect_draw_packet(cmd_buffer,
2942 info->indexed,
2943 info->count,
2944 count_va,
2945 info->stride);
2946 }
2947 }
2948 } else {
2949 assert(state->pipeline->graphics.vtx_base_sgpr);
2950
2951 if (info->vertex_offset != state->last_vertex_offset ||
2952 info->first_instance != state->last_first_instance) {
2953 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
2954 state->pipeline->graphics.vtx_emit_num);
2955
2956 radeon_emit(cs, info->vertex_offset);
2957 radeon_emit(cs, info->first_instance);
2958 if (state->pipeline->graphics.vtx_emit_num == 3)
2959 radeon_emit(cs, 0);
2960 state->last_first_instance = info->first_instance;
2961 state->last_vertex_offset = info->vertex_offset;
2962 }
2963
2964 if (state->last_num_instances != info->instance_count) {
2965 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
2966 radeon_emit(cs, info->instance_count);
2967 state->last_num_instances = info->instance_count;
2968 }
2969
2970 if (info->indexed) {
2971 int index_size = state->index_type ? 4 : 2;
2972 uint64_t index_va;
2973
2974 index_va = state->index_va;
2975 index_va += info->first_index * index_size;
2976
2977 if (!state->subpass->view_mask) {
2978 radv_cs_emit_draw_indexed_packet(cmd_buffer,
2979 index_va,
2980 info->count);
2981 } else {
2982 unsigned i;
2983 for_each_bit(i, state->subpass->view_mask) {
2984 radv_emit_view_index(cmd_buffer, i);
2985
2986 radv_cs_emit_draw_indexed_packet(cmd_buffer,
2987 index_va,
2988 info->count);
2989 }
2990 }
2991 } else {
2992 if (!state->subpass->view_mask) {
2993 radv_cs_emit_draw_packet(cmd_buffer, info->count);
2994 } else {
2995 unsigned i;
2996 for_each_bit(i, state->subpass->view_mask) {
2997 radv_emit_view_index(cmd_buffer, i);
2998
2999 radv_cs_emit_draw_packet(cmd_buffer,
3000 info->count);
3001 }
3002 }
3003 }
3004 }
3005 }
3006
3007 static void
3008 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3009 const struct radv_draw_info *info)
3010 {
3011 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3012 radv_emit_graphics_pipeline(cmd_buffer);
3013
3014 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3015 radv_emit_framebuffer_state(cmd_buffer);
3016
3017 if (info->indexed) {
3018 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3019 radv_emit_index_buffer(cmd_buffer);
3020 } else {
3021 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3022 * so the state must be re-emitted before the next indexed
3023 * draw.
3024 */
3025 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3026 cmd_buffer->state.last_index_type = -1;
3027 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3028 }
3029 }
3030
3031 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3032
3033 radv_emit_draw_registers(cmd_buffer, info->indexed,
3034 info->instance_count > 1, info->indirect,
3035 info->indirect ? 0 : info->count);
3036 }
3037
3038 static void
3039 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3040 const struct radv_draw_info *info)
3041 {
3042 bool pipeline_is_dirty =
3043 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3044 cmd_buffer->state.pipeline &&
3045 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3046
3047 MAYBE_UNUSED unsigned cdw_max =
3048 radeon_check_space(cmd_buffer->device->ws,
3049 cmd_buffer->cs, 4096);
3050
3051 /* Use optimal packet order based on whether we need to sync the
3052 * pipeline.
3053 */
3054 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3055 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3056 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3057 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3058 /* If we have to wait for idle, set all states first, so that
3059 * all SET packets are processed in parallel with previous draw
3060 * calls. Then upload descriptors, set shader pointers, and
3061 * draw, and prefetch at the end. This ensures that the time
3062 * the CUs are idle is very short. (there are only SET_SH
3063 * packets between the wait and the draw)
3064 */
3065 radv_emit_all_graphics_states(cmd_buffer, info);
3066 si_emit_cache_flush(cmd_buffer);
3067 /* <-- CUs are idle here --> */
3068
3069 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3070 return;
3071
3072 radv_emit_draw_packets(cmd_buffer, info);
3073 /* <-- CUs are busy here --> */
3074
3075 /* Start prefetches after the draw has been started. Both will
3076 * run in parallel, but starting the draw first is more
3077 * important.
3078 */
3079 if (cmd_buffer->state.prefetch_L2_mask) {
3080 radv_emit_prefetch(cmd_buffer,
3081 cmd_buffer->state.pipeline);
3082 }
3083 } else {
3084 /* If we don't wait for idle, start prefetches first, then set
3085 * states, and draw at the end.
3086 */
3087 si_emit_cache_flush(cmd_buffer);
3088
3089 if (cmd_buffer->state.prefetch_L2_mask) {
3090 radv_emit_prefetch(cmd_buffer,
3091 cmd_buffer->state.pipeline);
3092 }
3093
3094 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3095 return;
3096
3097 radv_emit_all_graphics_states(cmd_buffer, info);
3098 radv_emit_draw_packets(cmd_buffer, info);
3099 }
3100
3101 assert(cmd_buffer->cs->cdw <= cdw_max);
3102 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3103 }
3104
3105 void radv_CmdDraw(
3106 VkCommandBuffer commandBuffer,
3107 uint32_t vertexCount,
3108 uint32_t instanceCount,
3109 uint32_t firstVertex,
3110 uint32_t firstInstance)
3111 {
3112 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3113 struct radv_draw_info info = {};
3114
3115 info.count = vertexCount;
3116 info.instance_count = instanceCount;
3117 info.first_instance = firstInstance;
3118 info.vertex_offset = firstVertex;
3119
3120 radv_draw(cmd_buffer, &info);
3121 }
3122
3123 void radv_CmdDrawIndexed(
3124 VkCommandBuffer commandBuffer,
3125 uint32_t indexCount,
3126 uint32_t instanceCount,
3127 uint32_t firstIndex,
3128 int32_t vertexOffset,
3129 uint32_t firstInstance)
3130 {
3131 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3132 struct radv_draw_info info = {};
3133
3134 info.indexed = true;
3135 info.count = indexCount;
3136 info.instance_count = instanceCount;
3137 info.first_index = firstIndex;
3138 info.vertex_offset = vertexOffset;
3139 info.first_instance = firstInstance;
3140
3141 radv_draw(cmd_buffer, &info);
3142 }
3143
3144 void radv_CmdDrawIndirect(
3145 VkCommandBuffer commandBuffer,
3146 VkBuffer _buffer,
3147 VkDeviceSize offset,
3148 uint32_t drawCount,
3149 uint32_t stride)
3150 {
3151 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3152 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3153 struct radv_draw_info info = {};
3154
3155 info.count = drawCount;
3156 info.indirect = buffer;
3157 info.indirect_offset = offset;
3158 info.stride = stride;
3159
3160 radv_draw(cmd_buffer, &info);
3161 }
3162
3163 void radv_CmdDrawIndexedIndirect(
3164 VkCommandBuffer commandBuffer,
3165 VkBuffer _buffer,
3166 VkDeviceSize offset,
3167 uint32_t drawCount,
3168 uint32_t stride)
3169 {
3170 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3171 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3172 struct radv_draw_info info = {};
3173
3174 info.indexed = true;
3175 info.count = drawCount;
3176 info.indirect = buffer;
3177 info.indirect_offset = offset;
3178 info.stride = stride;
3179
3180 radv_draw(cmd_buffer, &info);
3181 }
3182
3183 void radv_CmdDrawIndirectCountAMD(
3184 VkCommandBuffer commandBuffer,
3185 VkBuffer _buffer,
3186 VkDeviceSize offset,
3187 VkBuffer _countBuffer,
3188 VkDeviceSize countBufferOffset,
3189 uint32_t maxDrawCount,
3190 uint32_t stride)
3191 {
3192 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3193 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3194 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3195 struct radv_draw_info info = {};
3196
3197 info.count = maxDrawCount;
3198 info.indirect = buffer;
3199 info.indirect_offset = offset;
3200 info.count_buffer = count_buffer;
3201 info.count_buffer_offset = countBufferOffset;
3202 info.stride = stride;
3203
3204 radv_draw(cmd_buffer, &info);
3205 }
3206
3207 void radv_CmdDrawIndexedIndirectCountAMD(
3208 VkCommandBuffer commandBuffer,
3209 VkBuffer _buffer,
3210 VkDeviceSize offset,
3211 VkBuffer _countBuffer,
3212 VkDeviceSize countBufferOffset,
3213 uint32_t maxDrawCount,
3214 uint32_t stride)
3215 {
3216 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3217 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3218 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3219 struct radv_draw_info info = {};
3220
3221 info.indexed = true;
3222 info.count = maxDrawCount;
3223 info.indirect = buffer;
3224 info.indirect_offset = offset;
3225 info.count_buffer = count_buffer;
3226 info.count_buffer_offset = countBufferOffset;
3227 info.stride = stride;
3228
3229 radv_draw(cmd_buffer, &info);
3230 }
3231
3232 struct radv_dispatch_info {
3233 /**
3234 * Determine the layout of the grid (in block units) to be used.
3235 */
3236 uint32_t blocks[3];
3237
3238 /**
3239 * A starting offset for the grid. If unaligned is set, the offset
3240 * must still be aligned.
3241 */
3242 uint32_t offsets[3];
3243 /**
3244 * Whether it's an unaligned compute dispatch.
3245 */
3246 bool unaligned;
3247
3248 /**
3249 * Indirect compute parameters resource.
3250 */
3251 struct radv_buffer *indirect;
3252 uint64_t indirect_offset;
3253 };
3254
3255 static void
3256 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3257 const struct radv_dispatch_info *info)
3258 {
3259 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3260 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3261 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3262 struct radeon_winsys *ws = cmd_buffer->device->ws;
3263 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3264 struct radv_userdata_info *loc;
3265
3266 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3267 AC_UD_CS_GRID_SIZE);
3268
3269 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3270
3271 if (info->indirect) {
3272 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3273
3274 va += info->indirect->offset + info->indirect_offset;
3275
3276 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3277
3278 if (loc->sgpr_idx != -1) {
3279 for (unsigned i = 0; i < 3; ++i) {
3280 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3281 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3282 COPY_DATA_DST_SEL(COPY_DATA_REG));
3283 radeon_emit(cs, (va + 4 * i));
3284 radeon_emit(cs, (va + 4 * i) >> 32);
3285 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3286 + loc->sgpr_idx * 4) >> 2) + i);
3287 radeon_emit(cs, 0);
3288 }
3289 }
3290
3291 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3292 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3293 PKT3_SHADER_TYPE_S(1));
3294 radeon_emit(cs, va);
3295 radeon_emit(cs, va >> 32);
3296 radeon_emit(cs, dispatch_initiator);
3297 } else {
3298 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3299 PKT3_SHADER_TYPE_S(1));
3300 radeon_emit(cs, 1);
3301 radeon_emit(cs, va);
3302 radeon_emit(cs, va >> 32);
3303
3304 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3305 PKT3_SHADER_TYPE_S(1));
3306 radeon_emit(cs, 0);
3307 radeon_emit(cs, dispatch_initiator);
3308 }
3309 } else {
3310 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3311 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3312
3313 if (info->unaligned) {
3314 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3315 unsigned remainder[3];
3316
3317 /* If aligned, these should be an entire block size,
3318 * not 0.
3319 */
3320 remainder[0] = blocks[0] + cs_block_size[0] -
3321 align_u32_npot(blocks[0], cs_block_size[0]);
3322 remainder[1] = blocks[1] + cs_block_size[1] -
3323 align_u32_npot(blocks[1], cs_block_size[1]);
3324 remainder[2] = blocks[2] + cs_block_size[2] -
3325 align_u32_npot(blocks[2], cs_block_size[2]);
3326
3327 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3328 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3329 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3330
3331 for(unsigned i = 0; i < 3; ++i) {
3332 assert(offsets[i] % cs_block_size[i] == 0);
3333 offsets[i] /= cs_block_size[i];
3334 }
3335
3336 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3337 radeon_emit(cs,
3338 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3339 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3340 radeon_emit(cs,
3341 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3342 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3343 radeon_emit(cs,
3344 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3345 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3346
3347 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3348 }
3349
3350 if (loc->sgpr_idx != -1) {
3351 assert(!loc->indirect);
3352 assert(loc->num_sgprs == 3);
3353
3354 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3355 loc->sgpr_idx * 4, 3);
3356 radeon_emit(cs, blocks[0]);
3357 radeon_emit(cs, blocks[1]);
3358 radeon_emit(cs, blocks[2]);
3359 }
3360
3361 if (offsets[0] || offsets[1] || offsets[2]) {
3362 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3363 radeon_emit(cs, offsets[0]);
3364 radeon_emit(cs, offsets[1]);
3365 radeon_emit(cs, offsets[2]);
3366
3367 /* The blocks in the packet are not counts but end values. */
3368 for (unsigned i = 0; i < 3; ++i)
3369 blocks[i] += offsets[i];
3370 } else {
3371 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3372 }
3373
3374 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3375 PKT3_SHADER_TYPE_S(1));
3376 radeon_emit(cs, blocks[0]);
3377 radeon_emit(cs, blocks[1]);
3378 radeon_emit(cs, blocks[2]);
3379 radeon_emit(cs, dispatch_initiator);
3380 }
3381
3382 assert(cmd_buffer->cs->cdw <= cdw_max);
3383 }
3384
3385 static void
3386 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3387 {
3388 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3389 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3390 VK_SHADER_STAGE_COMPUTE_BIT);
3391 }
3392
3393 static void
3394 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3395 const struct radv_dispatch_info *info)
3396 {
3397 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3398 bool pipeline_is_dirty = pipeline &&
3399 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3400
3401 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3402 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3403 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3404 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3405 /* If we have to wait for idle, set all states first, so that
3406 * all SET packets are processed in parallel with previous draw
3407 * calls. Then upload descriptors, set shader pointers, and
3408 * dispatch, and prefetch at the end. This ensures that the
3409 * time the CUs are idle is very short. (there are only SET_SH
3410 * packets between the wait and the draw)
3411 */
3412 radv_emit_compute_pipeline(cmd_buffer);
3413 si_emit_cache_flush(cmd_buffer);
3414 /* <-- CUs are idle here --> */
3415
3416 radv_upload_compute_shader_descriptors(cmd_buffer);
3417
3418 radv_emit_dispatch_packets(cmd_buffer, info);
3419 /* <-- CUs are busy here --> */
3420
3421 /* Start prefetches after the dispatch has been started. Both
3422 * will run in parallel, but starting the dispatch first is
3423 * more important.
3424 */
3425 if (pipeline_is_dirty) {
3426 radv_emit_shader_prefetch(cmd_buffer,
3427 pipeline->shaders[MESA_SHADER_COMPUTE]);
3428 }
3429 } else {
3430 /* If we don't wait for idle, start prefetches first, then set
3431 * states, and dispatch at the end.
3432 */
3433 si_emit_cache_flush(cmd_buffer);
3434
3435 if (pipeline_is_dirty) {
3436 radv_emit_shader_prefetch(cmd_buffer,
3437 pipeline->shaders[MESA_SHADER_COMPUTE]);
3438 }
3439
3440 radv_upload_compute_shader_descriptors(cmd_buffer);
3441
3442 radv_emit_compute_pipeline(cmd_buffer);
3443 radv_emit_dispatch_packets(cmd_buffer, info);
3444 }
3445
3446 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3447 }
3448
3449 void radv_CmdDispatchBase(
3450 VkCommandBuffer commandBuffer,
3451 uint32_t base_x,
3452 uint32_t base_y,
3453 uint32_t base_z,
3454 uint32_t x,
3455 uint32_t y,
3456 uint32_t z)
3457 {
3458 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3459 struct radv_dispatch_info info = {};
3460
3461 info.blocks[0] = x;
3462 info.blocks[1] = y;
3463 info.blocks[2] = z;
3464
3465 info.offsets[0] = base_x;
3466 info.offsets[1] = base_y;
3467 info.offsets[2] = base_z;
3468 radv_dispatch(cmd_buffer, &info);
3469 }
3470
3471 void radv_CmdDispatch(
3472 VkCommandBuffer commandBuffer,
3473 uint32_t x,
3474 uint32_t y,
3475 uint32_t z)
3476 {
3477 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3478 }
3479
3480 void radv_CmdDispatchIndirect(
3481 VkCommandBuffer commandBuffer,
3482 VkBuffer _buffer,
3483 VkDeviceSize offset)
3484 {
3485 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3486 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3487 struct radv_dispatch_info info = {};
3488
3489 info.indirect = buffer;
3490 info.indirect_offset = offset;
3491
3492 radv_dispatch(cmd_buffer, &info);
3493 }
3494
3495 void radv_unaligned_dispatch(
3496 struct radv_cmd_buffer *cmd_buffer,
3497 uint32_t x,
3498 uint32_t y,
3499 uint32_t z)
3500 {
3501 struct radv_dispatch_info info = {};
3502
3503 info.blocks[0] = x;
3504 info.blocks[1] = y;
3505 info.blocks[2] = z;
3506 info.unaligned = 1;
3507
3508 radv_dispatch(cmd_buffer, &info);
3509 }
3510
3511 void radv_CmdEndRenderPass(
3512 VkCommandBuffer commandBuffer)
3513 {
3514 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3515
3516 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3517
3518 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3519
3520 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3521 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3522 radv_handle_subpass_image_transition(cmd_buffer,
3523 (VkAttachmentReference){i, layout});
3524 }
3525
3526 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3527
3528 cmd_buffer->state.pass = NULL;
3529 cmd_buffer->state.subpass = NULL;
3530 cmd_buffer->state.attachments = NULL;
3531 cmd_buffer->state.framebuffer = NULL;
3532 }
3533
3534 /*
3535 * For HTILE we have the following interesting clear words:
3536 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3537 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3538 * 0xfffffff0: Clear depth to 1.0
3539 * 0x00000000: Clear depth to 0.0
3540 */
3541 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3542 struct radv_image *image,
3543 const VkImageSubresourceRange *range,
3544 uint32_t clear_word)
3545 {
3546 assert(range->baseMipLevel == 0);
3547 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3548 unsigned layer_count = radv_get_layerCount(image, range);
3549 uint64_t size = image->surface.htile_slice_size * layer_count;
3550 uint64_t offset = image->offset + image->htile_offset +
3551 image->surface.htile_slice_size * range->baseArrayLayer;
3552 struct radv_cmd_state *state = &cmd_buffer->state;
3553
3554 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3555 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3556
3557 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3558 size, clear_word);
3559
3560 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3561 }
3562
3563 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3564 struct radv_image *image,
3565 VkImageLayout src_layout,
3566 VkImageLayout dst_layout,
3567 unsigned src_queue_mask,
3568 unsigned dst_queue_mask,
3569 const VkImageSubresourceRange *range,
3570 VkImageAspectFlags pending_clears)
3571 {
3572 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3573 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3574 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3575 cmd_buffer->state.render_area.extent.width == image->info.width &&
3576 cmd_buffer->state.render_area.extent.height == image->info.height) {
3577 /* The clear will initialize htile. */
3578 return;
3579 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3580 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3581 /* TODO: merge with the clear if applicable */
3582 radv_initialize_htile(cmd_buffer, image, range, 0);
3583 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3584 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3585 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3586 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3587 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3588 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3589 VkImageSubresourceRange local_range = *range;
3590 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3591 local_range.baseMipLevel = 0;
3592 local_range.levelCount = 1;
3593
3594 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3595 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3596
3597 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3598
3599 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3600 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3601 }
3602 }
3603
3604 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3605 struct radv_image *image, uint32_t value)
3606 {
3607 struct radv_cmd_state *state = &cmd_buffer->state;
3608
3609 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3610 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3611
3612 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3613 image->offset + image->cmask.offset,
3614 image->cmask.size, value);
3615
3616 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3617 }
3618
3619 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3620 struct radv_image *image,
3621 VkImageLayout src_layout,
3622 VkImageLayout dst_layout,
3623 unsigned src_queue_mask,
3624 unsigned dst_queue_mask,
3625 const VkImageSubresourceRange *range)
3626 {
3627 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3628 if (image->fmask.size)
3629 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3630 else
3631 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3632 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3633 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3634 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3635 }
3636 }
3637
3638 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3639 struct radv_image *image, uint32_t value)
3640 {
3641 struct radv_cmd_state *state = &cmd_buffer->state;
3642
3643 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3644 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3645
3646 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3647 image->offset + image->dcc_offset,
3648 image->surface.dcc_size, value);
3649
3650 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3651 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3652 }
3653
3654 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3655 struct radv_image *image,
3656 VkImageLayout src_layout,
3657 VkImageLayout dst_layout,
3658 unsigned src_queue_mask,
3659 unsigned dst_queue_mask,
3660 const VkImageSubresourceRange *range)
3661 {
3662 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
3663 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
3664 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3665 radv_initialize_dcc(cmd_buffer, image,
3666 radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ?
3667 0x20202020u : 0xffffffffu);
3668 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3669 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3670 radv_decompress_dcc(cmd_buffer, image, range);
3671 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3672 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3673 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3674 }
3675 }
3676
3677 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3678 struct radv_image *image,
3679 VkImageLayout src_layout,
3680 VkImageLayout dst_layout,
3681 uint32_t src_family,
3682 uint32_t dst_family,
3683 const VkImageSubresourceRange *range,
3684 VkImageAspectFlags pending_clears)
3685 {
3686 if (image->exclusive && src_family != dst_family) {
3687 /* This is an acquire or a release operation and there will be
3688 * a corresponding release/acquire. Do the transition in the
3689 * most flexible queue. */
3690
3691 assert(src_family == cmd_buffer->queue_family_index ||
3692 dst_family == cmd_buffer->queue_family_index);
3693
3694 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3695 return;
3696
3697 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3698 (src_family == RADV_QUEUE_GENERAL ||
3699 dst_family == RADV_QUEUE_GENERAL))
3700 return;
3701 }
3702
3703 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3704 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3705
3706 if (image->surface.htile_size)
3707 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3708 dst_layout, src_queue_mask,
3709 dst_queue_mask, range,
3710 pending_clears);
3711
3712 if (image->cmask.size || image->fmask.size)
3713 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3714 dst_layout, src_queue_mask,
3715 dst_queue_mask, range);
3716
3717 if (image->surface.dcc_size)
3718 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3719 dst_layout, src_queue_mask,
3720 dst_queue_mask, range);
3721 }
3722
3723 void radv_CmdPipelineBarrier(
3724 VkCommandBuffer commandBuffer,
3725 VkPipelineStageFlags srcStageMask,
3726 VkPipelineStageFlags destStageMask,
3727 VkBool32 byRegion,
3728 uint32_t memoryBarrierCount,
3729 const VkMemoryBarrier* pMemoryBarriers,
3730 uint32_t bufferMemoryBarrierCount,
3731 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3732 uint32_t imageMemoryBarrierCount,
3733 const VkImageMemoryBarrier* pImageMemoryBarriers)
3734 {
3735 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3736 enum radv_cmd_flush_bits src_flush_bits = 0;
3737 enum radv_cmd_flush_bits dst_flush_bits = 0;
3738
3739 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3740 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3741 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3742 NULL);
3743 }
3744
3745 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3746 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3747 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3748 NULL);
3749 }
3750
3751 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3752 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3753 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3754 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3755 image);
3756 }
3757
3758 radv_stage_flush(cmd_buffer, srcStageMask);
3759 cmd_buffer->state.flush_bits |= src_flush_bits;
3760
3761 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3762 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3763 radv_handle_image_transition(cmd_buffer, image,
3764 pImageMemoryBarriers[i].oldLayout,
3765 pImageMemoryBarriers[i].newLayout,
3766 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3767 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3768 &pImageMemoryBarriers[i].subresourceRange,
3769 0);
3770 }
3771
3772 cmd_buffer->state.flush_bits |= dst_flush_bits;
3773 }
3774
3775
3776 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3777 struct radv_event *event,
3778 VkPipelineStageFlags stageMask,
3779 unsigned value)
3780 {
3781 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3782 uint64_t va = radv_buffer_get_va(event->bo);
3783
3784 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3785
3786 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3787
3788 /* TODO: this is overkill. Probably should figure something out from
3789 * the stage mask. */
3790
3791 si_cs_emit_write_event_eop(cs,
3792 cmd_buffer->state.predicating,
3793 cmd_buffer->device->physical_device->rad_info.chip_class,
3794 radv_cmd_buffer_uses_mec(cmd_buffer),
3795 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3796 1, va, 2, value);
3797
3798 assert(cmd_buffer->cs->cdw <= cdw_max);
3799 }
3800
3801 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3802 VkEvent _event,
3803 VkPipelineStageFlags stageMask)
3804 {
3805 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3806 RADV_FROM_HANDLE(radv_event, event, _event);
3807
3808 write_event(cmd_buffer, event, stageMask, 1);
3809 }
3810
3811 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3812 VkEvent _event,
3813 VkPipelineStageFlags stageMask)
3814 {
3815 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3816 RADV_FROM_HANDLE(radv_event, event, _event);
3817
3818 write_event(cmd_buffer, event, stageMask, 0);
3819 }
3820
3821 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3822 uint32_t eventCount,
3823 const VkEvent* pEvents,
3824 VkPipelineStageFlags srcStageMask,
3825 VkPipelineStageFlags dstStageMask,
3826 uint32_t memoryBarrierCount,
3827 const VkMemoryBarrier* pMemoryBarriers,
3828 uint32_t bufferMemoryBarrierCount,
3829 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3830 uint32_t imageMemoryBarrierCount,
3831 const VkImageMemoryBarrier* pImageMemoryBarriers)
3832 {
3833 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3834 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3835
3836 for (unsigned i = 0; i < eventCount; ++i) {
3837 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3838 uint64_t va = radv_buffer_get_va(event->bo);
3839
3840 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3841
3842 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3843
3844 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3845 assert(cmd_buffer->cs->cdw <= cdw_max);
3846 }
3847
3848
3849 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3850 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3851
3852 radv_handle_image_transition(cmd_buffer, image,
3853 pImageMemoryBarriers[i].oldLayout,
3854 pImageMemoryBarriers[i].newLayout,
3855 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3856 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3857 &pImageMemoryBarriers[i].subresourceRange,
3858 0);
3859 }
3860
3861 /* TODO: figure out how to do memory barriers without waiting */
3862 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3863 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3864 RADV_CMD_FLAG_INV_VMEM_L1 |
3865 RADV_CMD_FLAG_INV_SMEM_L1;
3866 }
3867
3868
3869 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
3870 uint32_t deviceMask)
3871 {
3872 /* No-op */
3873 }