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radv: allow launching waves out-of-order for compute
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
83 const struct radv_dynamic_state *src,
84 uint32_t copy_mask)
85 {
86 /* Make sure to copy the number of viewports/scissors because they can
87 * only be specified at pipeline creation time.
88 */
89 dest->viewport.count = src->viewport.count;
90 dest->scissor.count = src->scissor.count;
91
92 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
93 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
94 src->viewport.count);
95 }
96
97 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
98 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
99 src->scissor.count);
100 }
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
103 dest->line_width = src->line_width;
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
106 dest->depth_bias = src->depth_bias;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
109 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
112 dest->depth_bounds = src->depth_bounds;
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
115 dest->stencil_compare_mask = src->stencil_compare_mask;
116
117 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
118 dest->stencil_write_mask = src->stencil_write_mask;
119
120 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
121 dest->stencil_reference = src->stencil_reference;
122 }
123
124 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
125 {
126 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
127 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
128 }
129
130 enum ring_type radv_queue_family_to_ring(int f) {
131 switch (f) {
132 case RADV_QUEUE_GENERAL:
133 return RING_GFX;
134 case RADV_QUEUE_COMPUTE:
135 return RING_COMPUTE;
136 case RADV_QUEUE_TRANSFER:
137 return RING_DMA;
138 default:
139 unreachable("Unknown queue family");
140 }
141 }
142
143 static VkResult radv_create_cmd_buffer(
144 struct radv_device * device,
145 struct radv_cmd_pool * pool,
146 VkCommandBufferLevel level,
147 VkCommandBuffer* pCommandBuffer)
148 {
149 struct radv_cmd_buffer *cmd_buffer;
150 unsigned ring;
151 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
152 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
153 if (cmd_buffer == NULL)
154 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
155
156 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
157 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
158 cmd_buffer->device = device;
159 cmd_buffer->pool = pool;
160 cmd_buffer->level = level;
161
162 if (pool) {
163 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
164 cmd_buffer->queue_family_index = pool->queue_family_index;
165
166 } else {
167 /* Init the pool_link so we can safefly call list_del when we destroy
168 * the command buffer
169 */
170 list_inithead(&cmd_buffer->pool_link);
171 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
172 }
173
174 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
175
176 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
177 if (!cmd_buffer->cs) {
178 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
179 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
180 }
181
182 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
183
184 cmd_buffer->upload.offset = 0;
185 cmd_buffer->upload.size = 0;
186 list_inithead(&cmd_buffer->upload.list);
187
188 return VK_SUCCESS;
189 }
190
191 static void
192 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
193 {
194 list_del(&cmd_buffer->pool_link);
195
196 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
197 &cmd_buffer->upload.list, list) {
198 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
199 list_del(&up->list);
200 free(up);
201 }
202
203 if (cmd_buffer->upload.upload_bo)
204 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
205 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
206 free(cmd_buffer->push_descriptors.set.mapped_ptr);
207 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
208 }
209
210 static VkResult
211 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
212 {
213
214 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
215
216 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
217 &cmd_buffer->upload.list, list) {
218 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
219 list_del(&up->list);
220 free(up);
221 }
222
223 cmd_buffer->push_constant_stages = 0;
224 cmd_buffer->scratch_size_needed = 0;
225 cmd_buffer->compute_scratch_size_needed = 0;
226 cmd_buffer->esgs_ring_size_needed = 0;
227 cmd_buffer->gsvs_ring_size_needed = 0;
228 cmd_buffer->tess_rings_needed = false;
229 cmd_buffer->sample_positions_needed = false;
230
231 if (cmd_buffer->upload.upload_bo)
232 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
233 cmd_buffer->upload.upload_bo, 8);
234 cmd_buffer->upload.offset = 0;
235
236 cmd_buffer->record_result = VK_SUCCESS;
237
238 cmd_buffer->ring_offsets_idx = -1;
239
240 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
241 void *fence_ptr;
242 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
243 &cmd_buffer->gfx9_fence_offset,
244 &fence_ptr);
245 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
246 }
247
248 return cmd_buffer->record_result;
249 }
250
251 static bool
252 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
253 uint64_t min_needed)
254 {
255 uint64_t new_size;
256 struct radeon_winsys_bo *bo;
257 struct radv_cmd_buffer_upload *upload;
258 struct radv_device *device = cmd_buffer->device;
259
260 new_size = MAX2(min_needed, 16 * 1024);
261 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
262
263 bo = device->ws->buffer_create(device->ws,
264 new_size, 4096,
265 RADEON_DOMAIN_GTT,
266 RADEON_FLAG_CPU_ACCESS);
267
268 if (!bo) {
269 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
270 return false;
271 }
272
273 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
274 if (cmd_buffer->upload.upload_bo) {
275 upload = malloc(sizeof(*upload));
276
277 if (!upload) {
278 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
279 device->ws->buffer_destroy(bo);
280 return false;
281 }
282
283 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
284 list_add(&upload->list, &cmd_buffer->upload.list);
285 }
286
287 cmd_buffer->upload.upload_bo = bo;
288 cmd_buffer->upload.size = new_size;
289 cmd_buffer->upload.offset = 0;
290 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
291
292 if (!cmd_buffer->upload.map) {
293 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
294 return false;
295 }
296
297 return true;
298 }
299
300 bool
301 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
302 unsigned size,
303 unsigned alignment,
304 unsigned *out_offset,
305 void **ptr)
306 {
307 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
308 if (offset + size > cmd_buffer->upload.size) {
309 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
310 return false;
311 offset = 0;
312 }
313
314 *out_offset = offset;
315 *ptr = cmd_buffer->upload.map + offset;
316
317 cmd_buffer->upload.offset = offset + size;
318 return true;
319 }
320
321 bool
322 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
323 unsigned size, unsigned alignment,
324 const void *data, unsigned *out_offset)
325 {
326 uint8_t *ptr;
327
328 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
329 out_offset, (void **)&ptr))
330 return false;
331
332 if (ptr)
333 memcpy(ptr, data, size);
334
335 return true;
336 }
337
338 static void
339 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
340 unsigned count, const uint32_t *data)
341 {
342 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
343 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
344 S_370_WR_CONFIRM(1) |
345 S_370_ENGINE_SEL(V_370_ME));
346 radeon_emit(cs, va);
347 radeon_emit(cs, va >> 32);
348 radeon_emit_array(cs, data, count);
349 }
350
351 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
352 {
353 struct radv_device *device = cmd_buffer->device;
354 struct radeon_winsys_cs *cs = cmd_buffer->cs;
355 uint64_t va;
356
357 if (!device->trace_bo)
358 return;
359
360 va = radv_buffer_get_va(device->trace_bo);
361 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
362 va += 4;
363
364 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
365
366 ++cmd_buffer->state.trace_id;
367 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
368 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
369 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
370 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
371 }
372
373 static void
374 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
375 {
376 if (cmd_buffer->device->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
377 enum radv_cmd_flush_bits flags;
378
379 /* Force wait for graphics/compute engines to be idle. */
380 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
381 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
382
383 si_cs_emit_cache_flush(cmd_buffer->cs, false,
384 cmd_buffer->device->physical_device->rad_info.chip_class,
385 NULL, 0,
386 radv_cmd_buffer_uses_mec(cmd_buffer),
387 flags);
388 }
389
390 radv_cmd_buffer_trace_emit(cmd_buffer);
391 }
392
393 static void
394 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
395 struct radv_pipeline *pipeline, enum ring_type ring)
396 {
397 struct radv_device *device = cmd_buffer->device;
398 struct radeon_winsys_cs *cs = cmd_buffer->cs;
399 uint32_t data[2];
400 uint64_t va;
401
402 if (!device->trace_bo)
403 return;
404
405 va = radv_buffer_get_va(device->trace_bo);
406
407 switch (ring) {
408 case RING_GFX:
409 va += 8;
410 break;
411 case RING_COMPUTE:
412 va += 16;
413 break;
414 default:
415 assert(!"invalid ring type");
416 }
417
418 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
419 cmd_buffer->cs, 6);
420
421 data[0] = (uintptr_t)pipeline;
422 data[1] = (uintptr_t)pipeline >> 32;
423
424 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
425 radv_emit_write_data_packet(cs, va, 2, data);
426 }
427
428 static void
429 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
430 {
431 struct radv_device *device = cmd_buffer->device;
432 struct radeon_winsys_cs *cs = cmd_buffer->cs;
433 uint32_t data[MAX_SETS * 2] = {};
434 uint64_t va;
435
436 if (!device->trace_bo)
437 return;
438
439 va = radv_buffer_get_va(device->trace_bo) + 24;
440
441 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
442 cmd_buffer->cs, 4 + MAX_SETS * 2);
443
444 for (int i = 0; i < MAX_SETS; i++) {
445 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
446 if (!set)
447 continue;
448
449 data[i * 2] = (uintptr_t)set;
450 data[i * 2 + 1] = (uintptr_t)set >> 32;
451 }
452
453 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
454 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
455 }
456
457 static void
458 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
459 struct radv_pipeline *pipeline)
460 {
461 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
462 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
463 8);
464 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
465 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
466
467 if (cmd_buffer->device->physical_device->has_rbplus) {
468
469 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
470 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
471
472 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
473 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
474 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
475 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
476 }
477 }
478
479 static void
480 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
481 struct radv_pipeline *pipeline)
482 {
483 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
484 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
485 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
486
487 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
488 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
489 }
490
491 /* 12.4 fixed-point */
492 static unsigned radv_pack_float_12p4(float x)
493 {
494 return x <= 0 ? 0 :
495 x >= 4096 ? 0xffff : x * 16;
496 }
497
498 struct ac_userdata_info *
499 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
500 gl_shader_stage stage,
501 int idx)
502 {
503 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
504 }
505
506 static void
507 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
508 struct radv_pipeline *pipeline,
509 gl_shader_stage stage,
510 int idx, uint64_t va)
511 {
512 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
513 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
514 if (loc->sgpr_idx == -1)
515 return;
516 assert(loc->num_sgprs == 2);
517 assert(!loc->indirect);
518 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
519 radeon_emit(cmd_buffer->cs, va);
520 radeon_emit(cmd_buffer->cs, va >> 32);
521 }
522
523 static void
524 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
525 struct radv_pipeline *pipeline)
526 {
527 int num_samples = pipeline->graphics.ms.num_samples;
528 struct radv_multisample_state *ms = &pipeline->graphics.ms;
529 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
530
531 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
532 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
533 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
534
535 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
536 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
537
538 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
539 return;
540
541 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
542 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
543 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
544
545 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
546
547 /* GFX9: Flush DFSM when the AA mode changes. */
548 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
549 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
550 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
551 }
552 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
553 uint32_t offset;
554 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
555 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
556 if (loc->sgpr_idx == -1)
557 return;
558 assert(loc->num_sgprs == 1);
559 assert(!loc->indirect);
560 switch (num_samples) {
561 default:
562 offset = 0;
563 break;
564 case 2:
565 offset = 1;
566 break;
567 case 4:
568 offset = 3;
569 break;
570 case 8:
571 offset = 7;
572 break;
573 case 16:
574 offset = 15;
575 break;
576 }
577
578 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
579 cmd_buffer->sample_positions_needed = true;
580 }
581 }
582
583 static void
584 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
585 struct radv_pipeline *pipeline)
586 {
587 struct radv_raster_state *raster = &pipeline->graphics.raster;
588
589 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
590 raster->pa_cl_clip_cntl);
591
592 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
593 raster->spi_interp_control);
594
595 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
596 unsigned tmp = (unsigned)(1.0 * 8.0);
597 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
598 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
599 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
600
601 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
602 raster->pa_su_vtx_cntl);
603
604 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
605 raster->pa_su_sc_mode_cntl);
606 }
607
608 static inline void
609 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
610 unsigned size)
611 {
612 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
613 si_cp_dma_prefetch(cmd_buffer, va, size);
614 }
615
616 static void
617 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
618 struct radv_pipeline *pipeline,
619 struct radv_shader_variant *shader,
620 struct ac_vs_output_info *outinfo)
621 {
622 struct radeon_winsys *ws = cmd_buffer->device->ws;
623 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
624 unsigned export_count;
625
626 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
627 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
628
629 export_count = MAX2(1, outinfo->param_exports);
630 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
631 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
632
633 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
634 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
635 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
636 V_02870C_SPI_SHADER_4COMP :
637 V_02870C_SPI_SHADER_NONE) |
638 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
639 V_02870C_SPI_SHADER_4COMP :
640 V_02870C_SPI_SHADER_NONE) |
641 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
642 V_02870C_SPI_SHADER_4COMP :
643 V_02870C_SPI_SHADER_NONE));
644
645
646 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
647 radeon_emit(cmd_buffer->cs, va >> 8);
648 radeon_emit(cmd_buffer->cs, va >> 40);
649 radeon_emit(cmd_buffer->cs, shader->rsrc1);
650 radeon_emit(cmd_buffer->cs, shader->rsrc2);
651
652 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
653 S_028818_VTX_W0_FMT(1) |
654 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
655 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
656 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
657
658
659 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
660 pipeline->graphics.pa_cl_vs_out_cntl);
661
662 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
663 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
664 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
665 }
666
667 static void
668 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
669 struct radv_shader_variant *shader,
670 struct ac_es_output_info *outinfo)
671 {
672 struct radeon_winsys *ws = cmd_buffer->device->ws;
673 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
674
675 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
676 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
677
678 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
679 outinfo->esgs_itemsize / 4);
680 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
681 radeon_emit(cmd_buffer->cs, va >> 8);
682 radeon_emit(cmd_buffer->cs, va >> 40);
683 radeon_emit(cmd_buffer->cs, shader->rsrc1);
684 radeon_emit(cmd_buffer->cs, shader->rsrc2);
685 }
686
687 static void
688 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
689 struct radv_shader_variant *shader)
690 {
691 struct radeon_winsys *ws = cmd_buffer->device->ws;
692 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
693 uint32_t rsrc2 = shader->rsrc2;
694
695 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
696 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
697
698 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
699 radeon_emit(cmd_buffer->cs, va >> 8);
700 radeon_emit(cmd_buffer->cs, va >> 40);
701
702 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
703 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
704 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
705 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
706
707 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
708 radeon_emit(cmd_buffer->cs, shader->rsrc1);
709 radeon_emit(cmd_buffer->cs, rsrc2);
710 }
711
712 static void
713 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
714 struct radv_shader_variant *shader)
715 {
716 struct radeon_winsys *ws = cmd_buffer->device->ws;
717 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
718
719 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
720 radv_emit_prefetch(cmd_buffer, va, shader->code_size);
721
722 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
723 radeon_emit(cmd_buffer->cs, va >> 8);
724 radeon_emit(cmd_buffer->cs, va >> 40);
725 radeon_emit(cmd_buffer->cs, shader->rsrc1);
726 radeon_emit(cmd_buffer->cs, shader->rsrc2);
727 }
728
729 static void
730 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
731 struct radv_pipeline *pipeline)
732 {
733 struct radv_shader_variant *vs;
734
735 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
736
737 vs = pipeline->shaders[MESA_SHADER_VERTEX];
738
739 if (vs->info.vs.as_ls)
740 radv_emit_hw_ls(cmd_buffer, vs);
741 else if (vs->info.vs.as_es)
742 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
743 else
744 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
745
746 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
747 }
748
749
750 static void
751 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
752 struct radv_pipeline *pipeline)
753 {
754 if (!radv_pipeline_has_tess(pipeline))
755 return;
756
757 struct radv_shader_variant *tes, *tcs;
758
759 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
760 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
761
762 if (tes->info.tes.as_es)
763 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
764 else
765 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
766
767 radv_emit_hw_hs(cmd_buffer, tcs);
768
769 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
770 pipeline->graphics.tess.tf_param);
771
772 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
773 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
774 pipeline->graphics.tess.ls_hs_config);
775 else
776 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
777 pipeline->graphics.tess.ls_hs_config);
778
779 struct ac_userdata_info *loc;
780
781 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
782 if (loc->sgpr_idx != -1) {
783 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
784 assert(loc->num_sgprs == 4);
785 assert(!loc->indirect);
786 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
787 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
788 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
789 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
790 pipeline->graphics.tess.num_tcs_input_cp << 26);
791 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
792 }
793
794 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
795 if (loc->sgpr_idx != -1) {
796 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
797 assert(loc->num_sgprs == 1);
798 assert(!loc->indirect);
799
800 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
801 pipeline->graphics.tess.offchip_layout);
802 }
803
804 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
805 if (loc->sgpr_idx != -1) {
806 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
807 assert(loc->num_sgprs == 1);
808 assert(!loc->indirect);
809
810 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
811 pipeline->graphics.tess.tcs_in_layout);
812 }
813 }
814
815 static void
816 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
817 struct radv_pipeline *pipeline)
818 {
819 struct radeon_winsys *ws = cmd_buffer->device->ws;
820 struct radv_shader_variant *gs;
821 uint64_t va;
822
823 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
824
825 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
826 if (!gs)
827 return;
828
829 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
830
831 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
832 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
833 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
834 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
835
836 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
837
838 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
839
840 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
841 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
842 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
843 radeon_emit(cmd_buffer->cs, 0);
844 radeon_emit(cmd_buffer->cs, 0);
845 radeon_emit(cmd_buffer->cs, 0);
846
847 uint32_t gs_num_invocations = gs->info.gs.invocations;
848 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
849 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
850 S_028B90_ENABLE(gs_num_invocations > 0));
851
852 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
853 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
854 radv_emit_prefetch(cmd_buffer, va, gs->code_size);
855
856 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
857 radeon_emit(cmd_buffer->cs, va >> 8);
858 radeon_emit(cmd_buffer->cs, va >> 40);
859 radeon_emit(cmd_buffer->cs, gs->rsrc1);
860 radeon_emit(cmd_buffer->cs, gs->rsrc2);
861
862 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
863
864 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
865 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
866 if (loc->sgpr_idx != -1) {
867 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
868 uint32_t num_entries = 64;
869 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
870
871 if (is_vi)
872 num_entries *= stride;
873
874 stride = S_008F04_STRIDE(stride);
875 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
876 radeon_emit(cmd_buffer->cs, stride);
877 radeon_emit(cmd_buffer->cs, num_entries);
878 }
879 }
880
881 static void
882 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
883 struct radv_pipeline *pipeline)
884 {
885 struct radeon_winsys *ws = cmd_buffer->device->ws;
886 struct radv_shader_variant *ps;
887 uint64_t va;
888 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
889 struct radv_blend_state *blend = &pipeline->graphics.blend;
890 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
891
892 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
893 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
894 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
895 radv_emit_prefetch(cmd_buffer, va, ps->code_size);
896
897 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
898 radeon_emit(cmd_buffer->cs, va >> 8);
899 radeon_emit(cmd_buffer->cs, va >> 40);
900 radeon_emit(cmd_buffer->cs, ps->rsrc1);
901 radeon_emit(cmd_buffer->cs, ps->rsrc2);
902
903 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
904 pipeline->graphics.db_shader_control);
905
906 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
907 ps->config.spi_ps_input_ena);
908
909 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
910 ps->config.spi_ps_input_addr);
911
912 if (ps->info.info.ps.force_persample)
913 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
914
915 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
916 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
917
918 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
919
920 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
921 pipeline->graphics.shader_z_format);
922
923 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
924
925 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
926 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
927
928 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
929 /* optimise this? */
930 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
931 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
932 }
933
934 if (pipeline->graphics.ps_input_cntl_num) {
935 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
936 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
937 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
938 }
939 }
940 }
941
942 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
943 struct radv_pipeline *pipeline)
944 {
945 uint32_t vtx_reuse_depth = 30;
946 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
947 return;
948
949 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
950 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
951 vtx_reuse_depth = 14;
952 }
953 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
954 vtx_reuse_depth);
955 }
956
957 static void
958 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
959 {
960 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
961
962 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
963 return;
964
965 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
966 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
967 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
968 radv_update_multisample_state(cmd_buffer, pipeline);
969 radv_emit_vertex_shader(cmd_buffer, pipeline);
970 radv_emit_tess_shaders(cmd_buffer, pipeline);
971 radv_emit_geometry_shader(cmd_buffer, pipeline);
972 radv_emit_fragment_shader(cmd_buffer, pipeline);
973 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
974
975 cmd_buffer->scratch_size_needed =
976 MAX2(cmd_buffer->scratch_size_needed,
977 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
978
979 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
980 S_0286E8_WAVES(pipeline->max_waves) |
981 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
982
983 if (!cmd_buffer->state.emitted_pipeline ||
984 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
985 pipeline->graphics.can_use_guardband)
986 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
987
988 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
989
990 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
991 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
992 } else {
993 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
994 }
995 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
996
997 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
998
999 cmd_buffer->state.emitted_pipeline = pipeline;
1000 }
1001
1002 static void
1003 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1004 {
1005 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1006 cmd_buffer->state.dynamic.viewport.viewports);
1007 }
1008
1009 static void
1010 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1011 {
1012 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1013
1014 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1015 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1016 si_emit_cache_flush(cmd_buffer);
1017 }
1018 si_write_scissors(cmd_buffer->cs, 0, count,
1019 cmd_buffer->state.dynamic.scissor.scissors,
1020 cmd_buffer->state.dynamic.viewport.viewports,
1021 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1022 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1023 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1024 }
1025
1026 static void
1027 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1028 {
1029 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1030
1031 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1032 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1033 }
1034
1035 static void
1036 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1037 {
1038 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1039
1040 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1041 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1042 }
1043
1044 static void
1045 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1046 {
1047 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1048
1049 radeon_set_context_reg_seq(cmd_buffer->cs,
1050 R_028430_DB_STENCILREFMASK, 2);
1051 radeon_emit(cmd_buffer->cs,
1052 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1053 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1054 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1055 S_028430_STENCILOPVAL(1));
1056 radeon_emit(cmd_buffer->cs,
1057 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1058 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1059 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1060 S_028434_STENCILOPVAL_BF(1));
1061 }
1062
1063 static void
1064 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1065 {
1066 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1067
1068 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1069 fui(d->depth_bounds.min));
1070 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1071 fui(d->depth_bounds.max));
1072 }
1073
1074 static void
1075 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1076 {
1077 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1078 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1079 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1080 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1081
1082 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1083 radeon_set_context_reg_seq(cmd_buffer->cs,
1084 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1085 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1086 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1087 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1088 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1089 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1090 }
1091 }
1092
1093 static void
1094 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1095 int index,
1096 struct radv_color_buffer_info *cb)
1097 {
1098 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1099
1100 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1101 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1102 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1103 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1104 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1105 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1106 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1107 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1108 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1109 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1110 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1111 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1112 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1113
1114 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1115 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1116 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1117
1118 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1119 cb->gfx9_epitch);
1120 } else {
1121 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1122 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1123 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1124 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1125 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1126 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1127 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1128 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1129 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1130 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1131 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1132 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1133
1134 if (is_vi) { /* DCC BASE */
1135 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1136 }
1137 }
1138 }
1139
1140 static void
1141 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1142 struct radv_ds_buffer_info *ds,
1143 struct radv_image *image,
1144 VkImageLayout layout)
1145 {
1146 uint32_t db_z_info = ds->db_z_info;
1147 uint32_t db_stencil_info = ds->db_stencil_info;
1148
1149 if (!radv_layout_has_htile(image, layout,
1150 radv_image_queue_family_mask(image,
1151 cmd_buffer->queue_family_index,
1152 cmd_buffer->queue_family_index))) {
1153 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1154 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1155 }
1156
1157 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1158 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1159
1160
1161 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1162 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1163 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1164 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1165 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1166
1167 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1168 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1169 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1170 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1171 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1172 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1173 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1174 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1175 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1176 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1177 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1178
1179 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1180 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1181 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1182 } else {
1183 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1184
1185 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1186 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1187 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1188 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1189 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1190 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1191 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1192 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1193 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1194 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1195
1196 }
1197
1198 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1199 ds->pa_su_poly_offset_db_fmt_cntl);
1200 }
1201
1202 void
1203 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1204 struct radv_image *image,
1205 VkClearDepthStencilValue ds_clear_value,
1206 VkImageAspectFlags aspects)
1207 {
1208 uint64_t va = radv_buffer_get_va(image->bo);
1209 va += image->offset + image->clear_value_offset;
1210 unsigned reg_offset = 0, reg_count = 0;
1211
1212 if (!image->surface.htile_size || !aspects)
1213 return;
1214
1215 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1216 ++reg_count;
1217 } else {
1218 ++reg_offset;
1219 va += 4;
1220 }
1221 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1222 ++reg_count;
1223
1224 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1225
1226 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1227 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1228 S_370_WR_CONFIRM(1) |
1229 S_370_ENGINE_SEL(V_370_PFP));
1230 radeon_emit(cmd_buffer->cs, va);
1231 radeon_emit(cmd_buffer->cs, va >> 32);
1232 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1233 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1234 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1235 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1236
1237 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1238 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1239 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1240 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1241 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1242 }
1243
1244 static void
1245 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1246 struct radv_image *image)
1247 {
1248 uint64_t va = radv_buffer_get_va(image->bo);
1249 va += image->offset + image->clear_value_offset;
1250
1251 if (!image->surface.htile_size)
1252 return;
1253
1254 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1255
1256 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1257 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1258 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1259 COPY_DATA_COUNT_SEL);
1260 radeon_emit(cmd_buffer->cs, va);
1261 radeon_emit(cmd_buffer->cs, va >> 32);
1262 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1263 radeon_emit(cmd_buffer->cs, 0);
1264
1265 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1266 radeon_emit(cmd_buffer->cs, 0);
1267 }
1268
1269 /*
1270 *with DCC some colors don't require CMASK elimiation before being
1271 * used as a texture. This sets a predicate value to determine if the
1272 * cmask eliminate is required.
1273 */
1274 void
1275 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1276 struct radv_image *image,
1277 bool value)
1278 {
1279 uint64_t pred_val = value;
1280 uint64_t va = radv_buffer_get_va(image->bo);
1281 va += image->offset + image->dcc_pred_offset;
1282
1283 if (!image->surface.dcc_size)
1284 return;
1285
1286 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1287
1288 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1289 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1290 S_370_WR_CONFIRM(1) |
1291 S_370_ENGINE_SEL(V_370_PFP));
1292 radeon_emit(cmd_buffer->cs, va);
1293 radeon_emit(cmd_buffer->cs, va >> 32);
1294 radeon_emit(cmd_buffer->cs, pred_val);
1295 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1296 }
1297
1298 void
1299 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1300 struct radv_image *image,
1301 int idx,
1302 uint32_t color_values[2])
1303 {
1304 uint64_t va = radv_buffer_get_va(image->bo);
1305 va += image->offset + image->clear_value_offset;
1306
1307 if (!image->cmask.size && !image->surface.dcc_size)
1308 return;
1309
1310 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1311
1312 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1313 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1314 S_370_WR_CONFIRM(1) |
1315 S_370_ENGINE_SEL(V_370_PFP));
1316 radeon_emit(cmd_buffer->cs, va);
1317 radeon_emit(cmd_buffer->cs, va >> 32);
1318 radeon_emit(cmd_buffer->cs, color_values[0]);
1319 radeon_emit(cmd_buffer->cs, color_values[1]);
1320
1321 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1322 radeon_emit(cmd_buffer->cs, color_values[0]);
1323 radeon_emit(cmd_buffer->cs, color_values[1]);
1324 }
1325
1326 static void
1327 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1328 struct radv_image *image,
1329 int idx)
1330 {
1331 uint64_t va = radv_buffer_get_va(image->bo);
1332 va += image->offset + image->clear_value_offset;
1333
1334 if (!image->cmask.size && !image->surface.dcc_size)
1335 return;
1336
1337 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1338 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1339
1340 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1341 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1342 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1343 COPY_DATA_COUNT_SEL);
1344 radeon_emit(cmd_buffer->cs, va);
1345 radeon_emit(cmd_buffer->cs, va >> 32);
1346 radeon_emit(cmd_buffer->cs, reg >> 2);
1347 radeon_emit(cmd_buffer->cs, 0);
1348
1349 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1350 radeon_emit(cmd_buffer->cs, 0);
1351 }
1352
1353 void
1354 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1355 {
1356 int i;
1357 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1358 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1359
1360 /* this may happen for inherited secondary recording */
1361 if (!framebuffer)
1362 return;
1363
1364 for (i = 0; i < 8; ++i) {
1365 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1366 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1367 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1368 continue;
1369 }
1370
1371 int idx = subpass->color_attachments[i].attachment;
1372 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1373
1374 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1375
1376 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1377 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1378
1379 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1380 }
1381
1382 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1383 int idx = subpass->depth_stencil_attachment.attachment;
1384 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1385 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1386 struct radv_image *image = att->attachment->image;
1387 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1388 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1389 cmd_buffer->queue_family_index,
1390 cmd_buffer->queue_family_index);
1391 /* We currently don't support writing decompressed HTILE */
1392 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1393 radv_layout_is_htile_compressed(image, layout, queue_mask));
1394
1395 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1396
1397 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1398 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1399 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1400 }
1401 radv_load_depth_clear_regs(cmd_buffer, image);
1402 } else {
1403 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1404 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1405 else
1406 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1407
1408 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1409 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1410 }
1411 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1412 S_028208_BR_X(framebuffer->width) |
1413 S_028208_BR_Y(framebuffer->height));
1414
1415 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1416 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1417 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1418 }
1419 }
1420
1421 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1422 {
1423 uint32_t db_count_control;
1424
1425 if(!cmd_buffer->state.active_occlusion_queries) {
1426 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1427 db_count_control = 0;
1428 } else {
1429 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1430 }
1431 } else {
1432 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1433 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1434 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1435 S_028004_ZPASS_ENABLE(1) |
1436 S_028004_SLICE_EVEN_ENABLE(1) |
1437 S_028004_SLICE_ODD_ENABLE(1);
1438 } else {
1439 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1440 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1441 }
1442 }
1443
1444 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1445 }
1446
1447 static void
1448 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1449 {
1450 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1451 return;
1452
1453 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1454 radv_emit_viewport(cmd_buffer);
1455
1456 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1457 radv_emit_scissor(cmd_buffer);
1458
1459 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1460 radv_emit_line_width(cmd_buffer);
1461
1462 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1463 radv_emit_blend_constants(cmd_buffer);
1464
1465 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1466 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1467 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1468 radv_emit_stencil(cmd_buffer);
1469
1470 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1471 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS))
1472 radv_emit_depth_bounds(cmd_buffer);
1473
1474 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1475 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1476 radv_emit_depth_biais(cmd_buffer);
1477
1478 cmd_buffer->state.dirty = 0;
1479 }
1480
1481 static void
1482 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1483 struct radv_pipeline *pipeline,
1484 int idx,
1485 uint64_t va,
1486 gl_shader_stage stage)
1487 {
1488 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1489 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1490
1491 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1492 return;
1493
1494 assert(!desc_set_loc->indirect);
1495 assert(desc_set_loc->num_sgprs == 2);
1496 radeon_set_sh_reg_seq(cmd_buffer->cs,
1497 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1498 radeon_emit(cmd_buffer->cs, va);
1499 radeon_emit(cmd_buffer->cs, va >> 32);
1500 }
1501
1502 static void
1503 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1504 VkShaderStageFlags stages,
1505 struct radv_descriptor_set *set,
1506 unsigned idx)
1507 {
1508 if (cmd_buffer->state.pipeline) {
1509 radv_foreach_stage(stage, stages) {
1510 if (cmd_buffer->state.pipeline->shaders[stage])
1511 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1512 idx, set->va,
1513 stage);
1514 }
1515 }
1516
1517 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1518 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1519 idx, set->va,
1520 MESA_SHADER_COMPUTE);
1521 }
1522
1523 static void
1524 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1525 {
1526 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1527 unsigned bo_offset;
1528
1529 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1530 set->mapped_ptr,
1531 &bo_offset))
1532 return;
1533
1534 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1535 set->va += bo_offset;
1536 }
1537
1538 static void
1539 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1540 {
1541 uint32_t size = MAX_SETS * 2 * 4;
1542 uint32_t offset;
1543 void *ptr;
1544
1545 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1546 256, &offset, &ptr))
1547 return;
1548
1549 for (unsigned i = 0; i < MAX_SETS; i++) {
1550 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1551 uint64_t set_va = 0;
1552 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1553 if (set)
1554 set_va = set->va;
1555 uptr[0] = set_va & 0xffffffff;
1556 uptr[1] = set_va >> 32;
1557 }
1558
1559 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1560 va += offset;
1561
1562 if (cmd_buffer->state.pipeline) {
1563 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1564 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1565 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1566
1567 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1568 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1569 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1570
1571 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1572 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1573 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1574
1575 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1576 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1577 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1578
1579 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1580 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1581 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1582 }
1583
1584 if (cmd_buffer->state.compute_pipeline)
1585 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1586 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1587 }
1588
1589 static void
1590 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1591 VkShaderStageFlags stages)
1592 {
1593 unsigned i;
1594
1595 if (!cmd_buffer->state.descriptors_dirty)
1596 return;
1597
1598 if (cmd_buffer->state.push_descriptors_dirty)
1599 radv_flush_push_descriptors(cmd_buffer);
1600
1601 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1602 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1603 radv_flush_indirect_descriptor_sets(cmd_buffer);
1604 }
1605
1606 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1607 cmd_buffer->cs,
1608 MAX_SETS * MESA_SHADER_STAGES * 4);
1609
1610 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1611 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1612 if (!set)
1613 continue;
1614
1615 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1616 }
1617 cmd_buffer->state.descriptors_dirty = 0;
1618 cmd_buffer->state.push_descriptors_dirty = false;
1619
1620 radv_save_descriptors(cmd_buffer);
1621
1622 assert(cmd_buffer->cs->cdw <= cdw_max);
1623 }
1624
1625 static void
1626 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1627 struct radv_pipeline *pipeline,
1628 VkShaderStageFlags stages)
1629 {
1630 struct radv_pipeline_layout *layout = pipeline->layout;
1631 unsigned offset;
1632 void *ptr;
1633 uint64_t va;
1634
1635 stages &= cmd_buffer->push_constant_stages;
1636 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1637 return;
1638
1639 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1640 16 * layout->dynamic_offset_count,
1641 256, &offset, &ptr))
1642 return;
1643
1644 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1645 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1646 16 * layout->dynamic_offset_count);
1647
1648 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1649 va += offset;
1650
1651 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1652 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1653
1654 radv_foreach_stage(stage, stages) {
1655 if (pipeline->shaders[stage]) {
1656 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1657 AC_UD_PUSH_CONSTANTS, va);
1658 }
1659 }
1660
1661 cmd_buffer->push_constant_stages &= ~stages;
1662 assert(cmd_buffer->cs->cdw <= cdw_max);
1663 }
1664
1665 static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
1666 bool indexed_draw)
1667 {
1668 int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
1669
1670 if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
1671 cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
1672 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1673 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1674 primitive_reset_en);
1675 } else {
1676 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1677 primitive_reset_en);
1678 }
1679 }
1680
1681 if (primitive_reset_en) {
1682 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
1683
1684 if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
1685 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
1686 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1687 primitive_reset_index);
1688 }
1689 }
1690 }
1691
1692 static bool
1693 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
1694 {
1695 struct radv_device *device = cmd_buffer->device;
1696
1697 if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) &&
1698 cmd_buffer->state.pipeline->vertex_elements.count &&
1699 cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) {
1700 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1701 unsigned vb_offset;
1702 void *vb_ptr;
1703 uint32_t i = 0;
1704 uint32_t count = velems->count;
1705 uint64_t va;
1706
1707 /* allocate some descriptor state for vertex buffers */
1708 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1709 &vb_offset, &vb_ptr))
1710 return false;
1711
1712 for (i = 0; i < count; i++) {
1713 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1714 uint32_t offset;
1715 int vb = velems->binding[i];
1716 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1717 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1718
1719 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1720 va = radv_buffer_get_va(buffer->bo);
1721
1722 offset = cmd_buffer->state.vertex_bindings[vb].offset + velems->offset[i];
1723 va += offset + buffer->offset;
1724 desc[0] = va;
1725 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1726 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1727 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1728 else
1729 desc[2] = buffer->size - offset;
1730 desc[3] = velems->rsrc_word3[i];
1731 }
1732
1733 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1734 va += vb_offset;
1735
1736 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1737 AC_UD_VS_VERTEX_BUFFERS, va);
1738 }
1739 cmd_buffer->state.vb_dirty = false;
1740
1741 return true;
1742 }
1743
1744 static void
1745 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1746 bool indexed_draw, bool instanced_draw,
1747 bool indirect_draw,
1748 uint32_t draw_vertex_count)
1749 {
1750 uint32_t ia_multi_vgt_param;
1751
1752 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1753 cmd_buffer->cs, 4096);
1754
1755 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer))
1756 return;
1757
1758 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1759 radv_emit_graphics_pipeline(cmd_buffer);
1760
1761 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1762 radv_emit_framebuffer_state(cmd_buffer);
1763
1764 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1765 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1766 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1767 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
1768 else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1769 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1770 else
1771 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1772 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1773 }
1774
1775 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1776
1777 radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
1778
1779 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1780 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1781 VK_SHADER_STAGE_ALL_GRAPHICS);
1782
1783 assert(cmd_buffer->cs->cdw <= cdw_max);
1784
1785 si_emit_cache_flush(cmd_buffer);
1786 }
1787
1788 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1789 VkPipelineStageFlags src_stage_mask)
1790 {
1791 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1792 VK_PIPELINE_STAGE_TRANSFER_BIT |
1793 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1794 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1795 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1796 }
1797
1798 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1799 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1800 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1801 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1802 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1803 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1804 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1805 VK_PIPELINE_STAGE_TRANSFER_BIT |
1806 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1807 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1808 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1809 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1810 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1811 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1812 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1813 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1814 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1815 }
1816 }
1817
1818 static enum radv_cmd_flush_bits
1819 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1820 VkAccessFlags src_flags)
1821 {
1822 enum radv_cmd_flush_bits flush_bits = 0;
1823 uint32_t b;
1824 for_each_bit(b, src_flags) {
1825 switch ((VkAccessFlagBits)(1 << b)) {
1826 case VK_ACCESS_SHADER_WRITE_BIT:
1827 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1828 break;
1829 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1830 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1831 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1832 break;
1833 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1834 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1835 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1836 break;
1837 case VK_ACCESS_TRANSFER_WRITE_BIT:
1838 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1839 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1840 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1841 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1842 RADV_CMD_FLAG_INV_GLOBAL_L2;
1843 break;
1844 default:
1845 break;
1846 }
1847 }
1848 return flush_bits;
1849 }
1850
1851 static enum radv_cmd_flush_bits
1852 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1853 VkAccessFlags dst_flags,
1854 struct radv_image *image)
1855 {
1856 enum radv_cmd_flush_bits flush_bits = 0;
1857 uint32_t b;
1858 for_each_bit(b, dst_flags) {
1859 switch ((VkAccessFlagBits)(1 << b)) {
1860 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1861 case VK_ACCESS_INDEX_READ_BIT:
1862 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1863 break;
1864 case VK_ACCESS_UNIFORM_READ_BIT:
1865 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1866 break;
1867 case VK_ACCESS_SHADER_READ_BIT:
1868 case VK_ACCESS_TRANSFER_READ_BIT:
1869 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1870 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1871 RADV_CMD_FLAG_INV_GLOBAL_L2;
1872 break;
1873 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1874 /* TODO: change to image && when the image gets passed
1875 * through from the subpass. */
1876 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1877 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1878 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1879 break;
1880 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1881 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1882 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1883 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1884 break;
1885 default:
1886 break;
1887 }
1888 }
1889 return flush_bits;
1890 }
1891
1892 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1893 {
1894 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1895 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1896 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1897 NULL);
1898 }
1899
1900 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1901 VkAttachmentReference att)
1902 {
1903 unsigned idx = att.attachment;
1904 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1905 VkImageSubresourceRange range;
1906 range.aspectMask = 0;
1907 range.baseMipLevel = view->base_mip;
1908 range.levelCount = 1;
1909 range.baseArrayLayer = view->base_layer;
1910 range.layerCount = cmd_buffer->state.framebuffer->layers;
1911
1912 radv_handle_image_transition(cmd_buffer,
1913 view->image,
1914 cmd_buffer->state.attachments[idx].current_layout,
1915 att.layout, 0, 0, &range,
1916 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1917
1918 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1919
1920
1921 }
1922
1923 void
1924 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1925 const struct radv_subpass *subpass, bool transitions)
1926 {
1927 if (transitions) {
1928 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1929
1930 for (unsigned i = 0; i < subpass->color_count; ++i) {
1931 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1932 radv_handle_subpass_image_transition(cmd_buffer,
1933 subpass->color_attachments[i]);
1934 }
1935
1936 for (unsigned i = 0; i < subpass->input_count; ++i) {
1937 radv_handle_subpass_image_transition(cmd_buffer,
1938 subpass->input_attachments[i]);
1939 }
1940
1941 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1942 radv_handle_subpass_image_transition(cmd_buffer,
1943 subpass->depth_stencil_attachment);
1944 }
1945 }
1946
1947 cmd_buffer->state.subpass = subpass;
1948
1949 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1950 }
1951
1952 static VkResult
1953 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1954 struct radv_render_pass *pass,
1955 const VkRenderPassBeginInfo *info)
1956 {
1957 struct radv_cmd_state *state = &cmd_buffer->state;
1958
1959 if (pass->attachment_count == 0) {
1960 state->attachments = NULL;
1961 return VK_SUCCESS;
1962 }
1963
1964 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1965 pass->attachment_count *
1966 sizeof(state->attachments[0]),
1967 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1968 if (state->attachments == NULL) {
1969 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1970 return cmd_buffer->record_result;
1971 }
1972
1973 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1974 struct radv_render_pass_attachment *att = &pass->attachments[i];
1975 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1976 VkImageAspectFlags clear_aspects = 0;
1977
1978 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1979 /* color attachment */
1980 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1981 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1982 }
1983 } else {
1984 /* depthstencil attachment */
1985 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1986 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1987 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1988 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1989 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1990 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1991 }
1992 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1993 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1994 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1995 }
1996 }
1997
1998 state->attachments[i].pending_clear_aspects = clear_aspects;
1999 state->attachments[i].cleared_views = 0;
2000 if (clear_aspects && info) {
2001 assert(info->clearValueCount > i);
2002 state->attachments[i].clear_value = info->pClearValues[i];
2003 }
2004
2005 state->attachments[i].current_layout = att->initial_layout;
2006 }
2007
2008 return VK_SUCCESS;
2009 }
2010
2011 VkResult radv_AllocateCommandBuffers(
2012 VkDevice _device,
2013 const VkCommandBufferAllocateInfo *pAllocateInfo,
2014 VkCommandBuffer *pCommandBuffers)
2015 {
2016 RADV_FROM_HANDLE(radv_device, device, _device);
2017 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2018
2019 VkResult result = VK_SUCCESS;
2020 uint32_t i;
2021
2022 memset(pCommandBuffers, 0,
2023 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
2024
2025 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2026
2027 if (!list_empty(&pool->free_cmd_buffers)) {
2028 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2029
2030 list_del(&cmd_buffer->pool_link);
2031 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2032
2033 result = radv_reset_cmd_buffer(cmd_buffer);
2034 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2035 cmd_buffer->level = pAllocateInfo->level;
2036
2037 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2038 } else {
2039 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2040 &pCommandBuffers[i]);
2041 }
2042 if (result != VK_SUCCESS)
2043 break;
2044 }
2045
2046 if (result != VK_SUCCESS)
2047 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2048 i, pCommandBuffers);
2049
2050 return result;
2051 }
2052
2053 void radv_FreeCommandBuffers(
2054 VkDevice device,
2055 VkCommandPool commandPool,
2056 uint32_t commandBufferCount,
2057 const VkCommandBuffer *pCommandBuffers)
2058 {
2059 for (uint32_t i = 0; i < commandBufferCount; i++) {
2060 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2061
2062 if (cmd_buffer) {
2063 if (cmd_buffer->pool) {
2064 list_del(&cmd_buffer->pool_link);
2065 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2066 } else
2067 radv_cmd_buffer_destroy(cmd_buffer);
2068
2069 }
2070 }
2071 }
2072
2073 VkResult radv_ResetCommandBuffer(
2074 VkCommandBuffer commandBuffer,
2075 VkCommandBufferResetFlags flags)
2076 {
2077 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2078 return radv_reset_cmd_buffer(cmd_buffer);
2079 }
2080
2081 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2082 {
2083 struct radv_device *device = cmd_buffer->device;
2084 if (device->gfx_init) {
2085 uint64_t va = radv_buffer_get_va(device->gfx_init);
2086 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
2087 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2088 radeon_emit(cmd_buffer->cs, va);
2089 radeon_emit(cmd_buffer->cs, va >> 32);
2090 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2091 } else
2092 si_init_config(cmd_buffer);
2093 }
2094
2095 VkResult radv_BeginCommandBuffer(
2096 VkCommandBuffer commandBuffer,
2097 const VkCommandBufferBeginInfo *pBeginInfo)
2098 {
2099 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2100 VkResult result;
2101
2102 result = radv_reset_cmd_buffer(cmd_buffer);
2103 if (result != VK_SUCCESS)
2104 return result;
2105
2106 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2107 cmd_buffer->state.last_primitive_reset_en = -1;
2108 cmd_buffer->usage_flags = pBeginInfo->flags;
2109
2110 /* setup initial configuration into command buffer */
2111 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2112 switch (cmd_buffer->queue_family_index) {
2113 case RADV_QUEUE_GENERAL:
2114 emit_gfx_buffer_state(cmd_buffer);
2115 radv_set_db_count_control(cmd_buffer);
2116 break;
2117 case RADV_QUEUE_COMPUTE:
2118 si_init_compute(cmd_buffer);
2119 break;
2120 case RADV_QUEUE_TRANSFER:
2121 default:
2122 break;
2123 }
2124 }
2125
2126 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2127 assert(pBeginInfo->pInheritanceInfo);
2128 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2129 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2130
2131 struct radv_subpass *subpass =
2132 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2133
2134 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2135 if (result != VK_SUCCESS)
2136 return result;
2137
2138 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2139 }
2140
2141 radv_cmd_buffer_trace_emit(cmd_buffer);
2142 return result;
2143 }
2144
2145 void radv_CmdBindVertexBuffers(
2146 VkCommandBuffer commandBuffer,
2147 uint32_t firstBinding,
2148 uint32_t bindingCount,
2149 const VkBuffer* pBuffers,
2150 const VkDeviceSize* pOffsets)
2151 {
2152 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2153 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2154
2155 /* We have to defer setting up vertex buffer since we need the buffer
2156 * stride from the pipeline. */
2157
2158 assert(firstBinding + bindingCount <= MAX_VBS);
2159 for (uint32_t i = 0; i < bindingCount; i++) {
2160 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
2161 vb[firstBinding + i].offset = pOffsets[i];
2162 }
2163
2164 cmd_buffer->state.vb_dirty = true;
2165 }
2166
2167 void radv_CmdBindIndexBuffer(
2168 VkCommandBuffer commandBuffer,
2169 VkBuffer buffer,
2170 VkDeviceSize offset,
2171 VkIndexType indexType)
2172 {
2173 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2174 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2175
2176 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2177 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2178 cmd_buffer->state.index_va += index_buffer->offset + offset;
2179
2180 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2181 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2182 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2183 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2184 }
2185
2186
2187 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2188 struct radv_descriptor_set *set,
2189 unsigned idx)
2190 {
2191 struct radeon_winsys *ws = cmd_buffer->device->ws;
2192
2193 cmd_buffer->state.descriptors[idx] = set;
2194 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2195 if (!set)
2196 return;
2197
2198 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2199
2200 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2201 if (set->descriptors[j])
2202 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2203
2204 if(set->bo)
2205 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2206 }
2207
2208 void radv_CmdBindDescriptorSets(
2209 VkCommandBuffer commandBuffer,
2210 VkPipelineBindPoint pipelineBindPoint,
2211 VkPipelineLayout _layout,
2212 uint32_t firstSet,
2213 uint32_t descriptorSetCount,
2214 const VkDescriptorSet* pDescriptorSets,
2215 uint32_t dynamicOffsetCount,
2216 const uint32_t* pDynamicOffsets)
2217 {
2218 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2219 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2220 unsigned dyn_idx = 0;
2221
2222 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2223 unsigned idx = i + firstSet;
2224 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2225 radv_bind_descriptor_set(cmd_buffer, set, idx);
2226
2227 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2228 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2229 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2230 assert(dyn_idx < dynamicOffsetCount);
2231
2232 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2233 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2234 dst[0] = va;
2235 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2236 dst[2] = range->size;
2237 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2238 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2239 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2240 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2241 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2242 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2243 cmd_buffer->push_constant_stages |=
2244 set->layout->dynamic_shader_stages;
2245 }
2246 }
2247 }
2248
2249 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2250 struct radv_descriptor_set *set,
2251 struct radv_descriptor_set_layout *layout)
2252 {
2253 set->size = layout->size;
2254 set->layout = layout;
2255
2256 if (cmd_buffer->push_descriptors.capacity < set->size) {
2257 size_t new_size = MAX2(set->size, 1024);
2258 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2259 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2260
2261 free(set->mapped_ptr);
2262 set->mapped_ptr = malloc(new_size);
2263
2264 if (!set->mapped_ptr) {
2265 cmd_buffer->push_descriptors.capacity = 0;
2266 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2267 return false;
2268 }
2269
2270 cmd_buffer->push_descriptors.capacity = new_size;
2271 }
2272
2273 return true;
2274 }
2275
2276 void radv_meta_push_descriptor_set(
2277 struct radv_cmd_buffer* cmd_buffer,
2278 VkPipelineBindPoint pipelineBindPoint,
2279 VkPipelineLayout _layout,
2280 uint32_t set,
2281 uint32_t descriptorWriteCount,
2282 const VkWriteDescriptorSet* pDescriptorWrites)
2283 {
2284 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2285 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2286 unsigned bo_offset;
2287
2288 assert(set == 0);
2289 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2290
2291 push_set->size = layout->set[set].layout->size;
2292 push_set->layout = layout->set[set].layout;
2293
2294 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2295 &bo_offset,
2296 (void**) &push_set->mapped_ptr))
2297 return;
2298
2299 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2300 push_set->va += bo_offset;
2301
2302 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2303 radv_descriptor_set_to_handle(push_set),
2304 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2305
2306 cmd_buffer->state.descriptors[set] = push_set;
2307 cmd_buffer->state.descriptors_dirty |= (1u << set);
2308 }
2309
2310 void radv_CmdPushDescriptorSetKHR(
2311 VkCommandBuffer commandBuffer,
2312 VkPipelineBindPoint pipelineBindPoint,
2313 VkPipelineLayout _layout,
2314 uint32_t set,
2315 uint32_t descriptorWriteCount,
2316 const VkWriteDescriptorSet* pDescriptorWrites)
2317 {
2318 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2319 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2320 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2321
2322 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2323
2324 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2325 return;
2326
2327 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2328 radv_descriptor_set_to_handle(push_set),
2329 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2330
2331 cmd_buffer->state.descriptors[set] = push_set;
2332 cmd_buffer->state.descriptors_dirty |= (1u << set);
2333 cmd_buffer->state.push_descriptors_dirty = true;
2334 }
2335
2336 void radv_CmdPushDescriptorSetWithTemplateKHR(
2337 VkCommandBuffer commandBuffer,
2338 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2339 VkPipelineLayout _layout,
2340 uint32_t set,
2341 const void* pData)
2342 {
2343 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2344 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2345 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2346
2347 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2348
2349 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2350 return;
2351
2352 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2353 descriptorUpdateTemplate, pData);
2354
2355 cmd_buffer->state.descriptors[set] = push_set;
2356 cmd_buffer->state.descriptors_dirty |= (1u << set);
2357 cmd_buffer->state.push_descriptors_dirty = true;
2358 }
2359
2360 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2361 VkPipelineLayout layout,
2362 VkShaderStageFlags stageFlags,
2363 uint32_t offset,
2364 uint32_t size,
2365 const void* pValues)
2366 {
2367 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2368 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2369 cmd_buffer->push_constant_stages |= stageFlags;
2370 }
2371
2372 VkResult radv_EndCommandBuffer(
2373 VkCommandBuffer commandBuffer)
2374 {
2375 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2376
2377 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2378 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2379 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2380 si_emit_cache_flush(cmd_buffer);
2381 }
2382
2383 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2384 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2385
2386 return cmd_buffer->record_result;
2387 }
2388
2389 static void
2390 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2391 {
2392 struct radeon_winsys *ws = cmd_buffer->device->ws;
2393 struct radv_shader_variant *compute_shader;
2394 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2395 uint64_t va;
2396
2397 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2398 return;
2399
2400 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2401
2402 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2403 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2404
2405 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
2406 radv_emit_prefetch(cmd_buffer, va, compute_shader->code_size);
2407
2408 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2409 cmd_buffer->cs, 16);
2410
2411 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2412 radeon_emit(cmd_buffer->cs, va >> 8);
2413 radeon_emit(cmd_buffer->cs, va >> 40);
2414
2415 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2416 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2417 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2418
2419
2420 cmd_buffer->compute_scratch_size_needed =
2421 MAX2(cmd_buffer->compute_scratch_size_needed,
2422 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2423
2424 /* change these once we have scratch support */
2425 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2426 S_00B860_WAVES(pipeline->max_waves) |
2427 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2428
2429 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2430 radeon_emit(cmd_buffer->cs,
2431 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2432 radeon_emit(cmd_buffer->cs,
2433 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2434 radeon_emit(cmd_buffer->cs,
2435 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2436
2437 assert(cmd_buffer->cs->cdw <= cdw_max);
2438 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2439 }
2440
2441 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2442 {
2443 for (unsigned i = 0; i < MAX_SETS; i++) {
2444 if (cmd_buffer->state.descriptors[i])
2445 cmd_buffer->state.descriptors_dirty |= (1u << i);
2446 }
2447 }
2448
2449 void radv_CmdBindPipeline(
2450 VkCommandBuffer commandBuffer,
2451 VkPipelineBindPoint pipelineBindPoint,
2452 VkPipeline _pipeline)
2453 {
2454 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2455 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2456
2457 switch (pipelineBindPoint) {
2458 case VK_PIPELINE_BIND_POINT_COMPUTE:
2459 if (cmd_buffer->state.compute_pipeline == pipeline)
2460 return;
2461 radv_mark_descriptor_sets_dirty(cmd_buffer);
2462
2463 cmd_buffer->state.compute_pipeline = pipeline;
2464 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2465 break;
2466 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2467 if (cmd_buffer->state.pipeline == pipeline)
2468 return;
2469 radv_mark_descriptor_sets_dirty(cmd_buffer);
2470
2471 cmd_buffer->state.pipeline = pipeline;
2472 if (!pipeline)
2473 break;
2474
2475 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2476 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2477
2478 /* Apply the dynamic state from the pipeline */
2479 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
2480 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
2481 &pipeline->dynamic_state,
2482 pipeline->dynamic_state_mask);
2483
2484 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2485 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2486 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2487 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2488
2489 if (radv_pipeline_has_tess(pipeline))
2490 cmd_buffer->tess_rings_needed = true;
2491
2492 if (radv_pipeline_has_gs(pipeline)) {
2493 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2494 AC_UD_SCRATCH_RING_OFFSETS);
2495 if (cmd_buffer->ring_offsets_idx == -1)
2496 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2497 else if (loc->sgpr_idx != -1)
2498 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2499 }
2500 break;
2501 default:
2502 assert(!"invalid bind point");
2503 break;
2504 }
2505 }
2506
2507 void radv_CmdSetViewport(
2508 VkCommandBuffer commandBuffer,
2509 uint32_t firstViewport,
2510 uint32_t viewportCount,
2511 const VkViewport* pViewports)
2512 {
2513 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2514 const uint32_t total_count = firstViewport + viewportCount;
2515
2516 assert(firstViewport < MAX_VIEWPORTS);
2517 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2518
2519 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2520 pViewports, viewportCount * sizeof(*pViewports));
2521
2522 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2523 }
2524
2525 void radv_CmdSetScissor(
2526 VkCommandBuffer commandBuffer,
2527 uint32_t firstScissor,
2528 uint32_t scissorCount,
2529 const VkRect2D* pScissors)
2530 {
2531 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2532 const uint32_t total_count = firstScissor + scissorCount;
2533
2534 assert(firstScissor < MAX_SCISSORS);
2535 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2536
2537 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2538 pScissors, scissorCount * sizeof(*pScissors));
2539 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2540 }
2541
2542 void radv_CmdSetLineWidth(
2543 VkCommandBuffer commandBuffer,
2544 float lineWidth)
2545 {
2546 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2547 cmd_buffer->state.dynamic.line_width = lineWidth;
2548 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2549 }
2550
2551 void radv_CmdSetDepthBias(
2552 VkCommandBuffer commandBuffer,
2553 float depthBiasConstantFactor,
2554 float depthBiasClamp,
2555 float depthBiasSlopeFactor)
2556 {
2557 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2558
2559 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2560 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2561 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2562
2563 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2564 }
2565
2566 void radv_CmdSetBlendConstants(
2567 VkCommandBuffer commandBuffer,
2568 const float blendConstants[4])
2569 {
2570 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2571
2572 memcpy(cmd_buffer->state.dynamic.blend_constants,
2573 blendConstants, sizeof(float) * 4);
2574
2575 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2576 }
2577
2578 void radv_CmdSetDepthBounds(
2579 VkCommandBuffer commandBuffer,
2580 float minDepthBounds,
2581 float maxDepthBounds)
2582 {
2583 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2584
2585 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2586 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2587
2588 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2589 }
2590
2591 void radv_CmdSetStencilCompareMask(
2592 VkCommandBuffer commandBuffer,
2593 VkStencilFaceFlags faceMask,
2594 uint32_t compareMask)
2595 {
2596 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2597
2598 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2599 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2600 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2601 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2602
2603 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2604 }
2605
2606 void radv_CmdSetStencilWriteMask(
2607 VkCommandBuffer commandBuffer,
2608 VkStencilFaceFlags faceMask,
2609 uint32_t writeMask)
2610 {
2611 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2612
2613 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2614 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2615 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2616 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2617
2618 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2619 }
2620
2621 void radv_CmdSetStencilReference(
2622 VkCommandBuffer commandBuffer,
2623 VkStencilFaceFlags faceMask,
2624 uint32_t reference)
2625 {
2626 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2627
2628 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2629 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2630 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2631 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2632
2633 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2634 }
2635
2636 void radv_CmdExecuteCommands(
2637 VkCommandBuffer commandBuffer,
2638 uint32_t commandBufferCount,
2639 const VkCommandBuffer* pCmdBuffers)
2640 {
2641 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2642
2643 /* Emit pending flushes on primary prior to executing secondary */
2644 si_emit_cache_flush(primary);
2645
2646 for (uint32_t i = 0; i < commandBufferCount; i++) {
2647 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2648
2649 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2650 secondary->scratch_size_needed);
2651 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2652 secondary->compute_scratch_size_needed);
2653
2654 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2655 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2656 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2657 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2658 if (secondary->tess_rings_needed)
2659 primary->tess_rings_needed = true;
2660 if (secondary->sample_positions_needed)
2661 primary->sample_positions_needed = true;
2662
2663 if (secondary->ring_offsets_idx != -1) {
2664 if (primary->ring_offsets_idx == -1)
2665 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2666 else
2667 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2668 }
2669 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2670
2671 primary->state.emitted_pipeline = secondary->state.emitted_pipeline;
2672 primary->state.emitted_compute_pipeline = secondary->state.emitted_compute_pipeline;
2673 primary->state.last_primitive_reset_en = secondary->state.last_primitive_reset_en;
2674 primary->state.last_primitive_reset_index = secondary->state.last_primitive_reset_index;
2675 }
2676
2677 /* if we execute secondary we need to mark some stuff to reset dirty */
2678 if (commandBufferCount) {
2679 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2680 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2681 radv_mark_descriptor_sets_dirty(primary);
2682 }
2683 }
2684
2685 VkResult radv_CreateCommandPool(
2686 VkDevice _device,
2687 const VkCommandPoolCreateInfo* pCreateInfo,
2688 const VkAllocationCallbacks* pAllocator,
2689 VkCommandPool* pCmdPool)
2690 {
2691 RADV_FROM_HANDLE(radv_device, device, _device);
2692 struct radv_cmd_pool *pool;
2693
2694 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2695 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2696 if (pool == NULL)
2697 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2698
2699 if (pAllocator)
2700 pool->alloc = *pAllocator;
2701 else
2702 pool->alloc = device->alloc;
2703
2704 list_inithead(&pool->cmd_buffers);
2705 list_inithead(&pool->free_cmd_buffers);
2706
2707 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2708
2709 *pCmdPool = radv_cmd_pool_to_handle(pool);
2710
2711 return VK_SUCCESS;
2712
2713 }
2714
2715 void radv_DestroyCommandPool(
2716 VkDevice _device,
2717 VkCommandPool commandPool,
2718 const VkAllocationCallbacks* pAllocator)
2719 {
2720 RADV_FROM_HANDLE(radv_device, device, _device);
2721 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2722
2723 if (!pool)
2724 return;
2725
2726 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2727 &pool->cmd_buffers, pool_link) {
2728 radv_cmd_buffer_destroy(cmd_buffer);
2729 }
2730
2731 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2732 &pool->free_cmd_buffers, pool_link) {
2733 radv_cmd_buffer_destroy(cmd_buffer);
2734 }
2735
2736 vk_free2(&device->alloc, pAllocator, pool);
2737 }
2738
2739 VkResult radv_ResetCommandPool(
2740 VkDevice device,
2741 VkCommandPool commandPool,
2742 VkCommandPoolResetFlags flags)
2743 {
2744 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2745 VkResult result;
2746
2747 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2748 &pool->cmd_buffers, pool_link) {
2749 result = radv_reset_cmd_buffer(cmd_buffer);
2750 if (result != VK_SUCCESS)
2751 return result;
2752 }
2753
2754 return VK_SUCCESS;
2755 }
2756
2757 void radv_TrimCommandPoolKHR(
2758 VkDevice device,
2759 VkCommandPool commandPool,
2760 VkCommandPoolTrimFlagsKHR flags)
2761 {
2762 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2763
2764 if (!pool)
2765 return;
2766
2767 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2768 &pool->free_cmd_buffers, pool_link) {
2769 radv_cmd_buffer_destroy(cmd_buffer);
2770 }
2771 }
2772
2773 void radv_CmdBeginRenderPass(
2774 VkCommandBuffer commandBuffer,
2775 const VkRenderPassBeginInfo* pRenderPassBegin,
2776 VkSubpassContents contents)
2777 {
2778 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2779 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2780 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2781
2782 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2783 cmd_buffer->cs, 2048);
2784 MAYBE_UNUSED VkResult result;
2785
2786 cmd_buffer->state.framebuffer = framebuffer;
2787 cmd_buffer->state.pass = pass;
2788 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2789
2790 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2791 if (result != VK_SUCCESS)
2792 return;
2793
2794 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2795 assert(cmd_buffer->cs->cdw <= cdw_max);
2796
2797 radv_cmd_buffer_clear_subpass(cmd_buffer);
2798 }
2799
2800 void radv_CmdNextSubpass(
2801 VkCommandBuffer commandBuffer,
2802 VkSubpassContents contents)
2803 {
2804 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2805
2806 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2807
2808 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2809 2048);
2810
2811 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2812 radv_cmd_buffer_clear_subpass(cmd_buffer);
2813 }
2814
2815 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2816 {
2817 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2818 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2819 if (!pipeline->shaders[stage])
2820 continue;
2821 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2822 if (loc->sgpr_idx == -1)
2823 continue;
2824 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2825 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2826
2827 }
2828 if (pipeline->gs_copy_shader) {
2829 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2830 if (loc->sgpr_idx != -1) {
2831 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2832 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2833 }
2834 }
2835 }
2836
2837 static void
2838 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2839 uint32_t vertex_count)
2840 {
2841 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2842 radeon_emit(cmd_buffer->cs, vertex_count);
2843 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2844 S_0287F0_USE_OPAQUE(0));
2845 }
2846
2847 void radv_CmdDraw(
2848 VkCommandBuffer commandBuffer,
2849 uint32_t vertexCount,
2850 uint32_t instanceCount,
2851 uint32_t firstVertex,
2852 uint32_t firstInstance)
2853 {
2854 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2855
2856 radv_cmd_buffer_flush_state(cmd_buffer, false, (instanceCount > 1), false, vertexCount);
2857
2858 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 20 * MAX_VIEWS);
2859
2860 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2861 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2862 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2863 radeon_emit(cmd_buffer->cs, firstVertex);
2864 radeon_emit(cmd_buffer->cs, firstInstance);
2865 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2866 radeon_emit(cmd_buffer->cs, 0);
2867
2868 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
2869 radeon_emit(cmd_buffer->cs, instanceCount);
2870
2871 if (!cmd_buffer->state.subpass->view_mask) {
2872 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2873 } else {
2874 unsigned i;
2875 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2876 radv_emit_view_index(cmd_buffer, i);
2877
2878 radv_cs_emit_draw_packet(cmd_buffer, vertexCount);
2879 }
2880 }
2881
2882 assert(cmd_buffer->cs->cdw <= cdw_max);
2883
2884 radv_cmd_buffer_after_draw(cmd_buffer);
2885 }
2886
2887
2888 static void
2889 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2890 uint64_t index_va,
2891 uint32_t index_count)
2892 {
2893 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2894 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2895 radeon_emit(cmd_buffer->cs, index_va);
2896 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2897 radeon_emit(cmd_buffer->cs, index_count);
2898 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2899 }
2900
2901 void radv_CmdDrawIndexed(
2902 VkCommandBuffer commandBuffer,
2903 uint32_t indexCount,
2904 uint32_t instanceCount,
2905 uint32_t firstIndex,
2906 int32_t vertexOffset,
2907 uint32_t firstInstance)
2908 {
2909 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2910 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2911 uint64_t index_va;
2912
2913 radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
2914
2915 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 26 * MAX_VIEWS);
2916
2917 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2918 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
2919 2, cmd_buffer->state.index_type);
2920 } else {
2921 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2922 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2923 }
2924
2925 assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
2926 radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
2927 cmd_buffer->state.pipeline->graphics.vtx_emit_num);
2928 radeon_emit(cmd_buffer->cs, vertexOffset);
2929 radeon_emit(cmd_buffer->cs, firstInstance);
2930 if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
2931 radeon_emit(cmd_buffer->cs, 0);
2932
2933 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2934 radeon_emit(cmd_buffer->cs, instanceCount);
2935
2936 index_va = cmd_buffer->state.index_va;
2937 index_va += firstIndex * index_size;
2938 if (!cmd_buffer->state.subpass->view_mask) {
2939 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2940 } else {
2941 unsigned i;
2942 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
2943 radv_emit_view_index(cmd_buffer, i);
2944
2945 radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, indexCount);
2946 }
2947 }
2948
2949 assert(cmd_buffer->cs->cdw <= cdw_max);
2950 radv_cmd_buffer_after_draw(cmd_buffer);
2951 }
2952
2953 static void
2954 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2955 bool indexed,
2956 uint32_t draw_count,
2957 uint64_t count_va,
2958 uint32_t stride)
2959 {
2960 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2961 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2962 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2963 bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
2964 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2965 assert(base_reg);
2966
2967 if (draw_count == 1 && !count_va && !draw_id_enable) {
2968 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2969 PKT3_DRAW_INDIRECT, 3, false));
2970 radeon_emit(cs, 0);
2971 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2972 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2973 radeon_emit(cs, di_src_sel);
2974 } else {
2975 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2976 PKT3_DRAW_INDIRECT_MULTI,
2977 8, false));
2978 radeon_emit(cs, 0);
2979 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2980 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2981 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2982 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2983 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2984 radeon_emit(cs, draw_count); /* count */
2985 radeon_emit(cs, count_va); /* count_addr */
2986 radeon_emit(cs, count_va >> 32);
2987 radeon_emit(cs, stride); /* stride */
2988 radeon_emit(cs, di_src_sel);
2989 }
2990 }
2991
2992 static void
2993 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2994 VkBuffer _buffer,
2995 VkDeviceSize offset,
2996 VkBuffer _count_buffer,
2997 VkDeviceSize count_offset,
2998 uint32_t draw_count,
2999 uint32_t stride,
3000 bool indexed)
3001 {
3002 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3003 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
3004 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3005
3006 uint64_t indirect_va = radv_buffer_get_va(buffer->bo);
3007 indirect_va += offset + buffer->offset;
3008 uint64_t count_va = 0;
3009
3010 if (count_buffer) {
3011 count_va = radv_buffer_get_va(count_buffer->bo);
3012 count_va += count_offset + count_buffer->offset;
3013 }
3014
3015 if (!draw_count)
3016 return;
3017
3018 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
3019
3020 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3021 radeon_emit(cs, 1);
3022 radeon_emit(cs, indirect_va);
3023 radeon_emit(cs, indirect_va >> 32);
3024
3025 if (!cmd_buffer->state.subpass->view_mask) {
3026 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
3027 } else {
3028 unsigned i;
3029 for_each_bit(i, cmd_buffer->state.subpass->view_mask) {
3030 radv_emit_view_index(cmd_buffer, i);
3031
3032 radv_cs_emit_indirect_draw_packet(cmd_buffer, indexed, draw_count, count_va, stride);
3033 }
3034 }
3035 radv_cmd_buffer_after_draw(cmd_buffer);
3036 }
3037
3038 static void
3039 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
3040 VkBuffer buffer,
3041 VkDeviceSize offset,
3042 VkBuffer countBuffer,
3043 VkDeviceSize countBufferOffset,
3044 uint32_t maxDrawCount,
3045 uint32_t stride)
3046 {
3047 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3048 radv_cmd_buffer_flush_state(cmd_buffer, false, false, true, 0);
3049
3050 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3051 cmd_buffer->cs, 24 * MAX_VIEWS);
3052
3053 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
3054 countBuffer, countBufferOffset, maxDrawCount, stride, false);
3055
3056 assert(cmd_buffer->cs->cdw <= cdw_max);
3057 }
3058
3059 static void
3060 radv_cmd_draw_indexed_indirect_count(
3061 VkCommandBuffer commandBuffer,
3062 VkBuffer buffer,
3063 VkDeviceSize offset,
3064 VkBuffer countBuffer,
3065 VkDeviceSize countBufferOffset,
3066 uint32_t maxDrawCount,
3067 uint32_t stride)
3068 {
3069 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3070 uint64_t index_va;
3071 radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
3072
3073 index_va = cmd_buffer->state.index_va;
3074
3075 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 31 * MAX_VIEWS);
3076
3077 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
3078 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
3079
3080 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
3081 radeon_emit(cmd_buffer->cs, index_va);
3082 radeon_emit(cmd_buffer->cs, index_va >> 32);
3083
3084 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
3085 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3086
3087 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
3088 countBuffer, countBufferOffset, maxDrawCount, stride, true);
3089
3090 assert(cmd_buffer->cs->cdw <= cdw_max);
3091 }
3092
3093 void radv_CmdDrawIndirect(
3094 VkCommandBuffer commandBuffer,
3095 VkBuffer buffer,
3096 VkDeviceSize offset,
3097 uint32_t drawCount,
3098 uint32_t stride)
3099 {
3100 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
3101 VK_NULL_HANDLE, 0, drawCount, stride);
3102 }
3103
3104 void radv_CmdDrawIndexedIndirect(
3105 VkCommandBuffer commandBuffer,
3106 VkBuffer buffer,
3107 VkDeviceSize offset,
3108 uint32_t drawCount,
3109 uint32_t stride)
3110 {
3111 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3112 VK_NULL_HANDLE, 0, drawCount, stride);
3113 }
3114
3115 void radv_CmdDrawIndirectCountAMD(
3116 VkCommandBuffer commandBuffer,
3117 VkBuffer buffer,
3118 VkDeviceSize offset,
3119 VkBuffer countBuffer,
3120 VkDeviceSize countBufferOffset,
3121 uint32_t maxDrawCount,
3122 uint32_t stride)
3123 {
3124 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
3125 countBuffer, countBufferOffset,
3126 maxDrawCount, stride);
3127 }
3128
3129 void radv_CmdDrawIndexedIndirectCountAMD(
3130 VkCommandBuffer commandBuffer,
3131 VkBuffer buffer,
3132 VkDeviceSize offset,
3133 VkBuffer countBuffer,
3134 VkDeviceSize countBufferOffset,
3135 uint32_t maxDrawCount,
3136 uint32_t stride)
3137 {
3138 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
3139 countBuffer, countBufferOffset,
3140 maxDrawCount, stride);
3141 }
3142
3143 struct radv_dispatch_info {
3144 /**
3145 * Determine the layout of the grid (in block units) to be used.
3146 */
3147 uint32_t blocks[3];
3148
3149 /**
3150 * Whether it's an unaligned compute dispatch.
3151 */
3152 bool unaligned;
3153
3154 /**
3155 * Indirect compute parameters resource.
3156 */
3157 struct radv_buffer *indirect;
3158 uint64_t indirect_offset;
3159 };
3160
3161 static void
3162 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3163 const struct radv_dispatch_info *info)
3164 {
3165 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3166 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3167 struct radeon_winsys *ws = cmd_buffer->device->ws;
3168 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3169 struct ac_userdata_info *loc;
3170 uint8_t grid_used;
3171
3172 grid_used = compute_shader->info.info.cs.grid_components_used;
3173
3174 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3175 AC_UD_CS_GRID_SIZE);
3176
3177 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3178
3179 if (info->indirect) {
3180 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3181
3182 va += info->indirect->offset + info->indirect_offset;
3183
3184 ws->cs_add_buffer(cs, info->indirect->bo, 8);
3185
3186 if (loc->sgpr_idx != -1) {
3187 for (unsigned i = 0; i < grid_used; ++i) {
3188 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3189 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3190 COPY_DATA_DST_SEL(COPY_DATA_REG));
3191 radeon_emit(cs, (va + 4 * i));
3192 radeon_emit(cs, (va + 4 * i) >> 32);
3193 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3194 + loc->sgpr_idx * 4) >> 2) + i);
3195 radeon_emit(cs, 0);
3196 }
3197 }
3198
3199 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3200 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3201 PKT3_SHADER_TYPE_S(1));
3202 radeon_emit(cs, va);
3203 radeon_emit(cs, va >> 32);
3204 radeon_emit(cs, 1);
3205 } else {
3206 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3207 PKT3_SHADER_TYPE_S(1));
3208 radeon_emit(cs, 1);
3209 radeon_emit(cs, va);
3210 radeon_emit(cs, va >> 32);
3211
3212 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3213 PKT3_SHADER_TYPE_S(1));
3214 radeon_emit(cs, 0);
3215 radeon_emit(cs, 1);
3216 }
3217 } else {
3218 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3219 unsigned dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3220 S_00B800_FORCE_START_AT_000(1);
3221
3222 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3223 /* If the KMD allows it (there is a KMD hw register for
3224 * it), allow launching waves out-of-order.
3225 */
3226 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3227 }
3228
3229 if (info->unaligned) {
3230 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3231 unsigned remainder[3];
3232
3233 /* If aligned, these should be an entire block size,
3234 * not 0.
3235 */
3236 remainder[0] = blocks[0] + cs_block_size[0] -
3237 align_u32_npot(blocks[0], cs_block_size[0]);
3238 remainder[1] = blocks[1] + cs_block_size[1] -
3239 align_u32_npot(blocks[1], cs_block_size[1]);
3240 remainder[2] = blocks[2] + cs_block_size[2] -
3241 align_u32_npot(blocks[2], cs_block_size[2]);
3242
3243 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3244 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3245 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3246
3247 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3248 radeon_emit(cs,
3249 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3250 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3251 radeon_emit(cs,
3252 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3253 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3254 radeon_emit(cs,
3255 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3256 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3257
3258 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3259 }
3260
3261 if (loc->sgpr_idx != -1) {
3262 assert(!loc->indirect);
3263 assert(loc->num_sgprs == grid_used);
3264
3265 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3266 loc->sgpr_idx * 4, grid_used);
3267 radeon_emit(cs, blocks[0]);
3268 if (grid_used > 1)
3269 radeon_emit(cs, blocks[1]);
3270 if (grid_used > 2)
3271 radeon_emit(cs, blocks[2]);
3272 }
3273
3274 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3275 PKT3_SHADER_TYPE_S(1));
3276 radeon_emit(cs, blocks[0]);
3277 radeon_emit(cs, blocks[1]);
3278 radeon_emit(cs, blocks[2]);
3279 radeon_emit(cs, dispatch_initiator);
3280 }
3281
3282 assert(cmd_buffer->cs->cdw <= cdw_max);
3283 }
3284
3285 static void
3286 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3287 const struct radv_dispatch_info *info)
3288 {
3289 radv_emit_compute_pipeline(cmd_buffer);
3290
3291 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3292 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3293 VK_SHADER_STAGE_COMPUTE_BIT);
3294
3295 si_emit_cache_flush(cmd_buffer);
3296
3297 radv_emit_dispatch_packets(cmd_buffer, info);
3298
3299 radv_cmd_buffer_after_draw(cmd_buffer);
3300 }
3301
3302 void radv_CmdDispatch(
3303 VkCommandBuffer commandBuffer,
3304 uint32_t x,
3305 uint32_t y,
3306 uint32_t z)
3307 {
3308 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3309 struct radv_dispatch_info info = {};
3310
3311 info.blocks[0] = x;
3312 info.blocks[1] = y;
3313 info.blocks[2] = z;
3314
3315 radv_dispatch(cmd_buffer, &info);
3316 }
3317
3318 void radv_CmdDispatchIndirect(
3319 VkCommandBuffer commandBuffer,
3320 VkBuffer _buffer,
3321 VkDeviceSize offset)
3322 {
3323 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3324 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3325 struct radv_dispatch_info info = {};
3326
3327 info.indirect = buffer;
3328 info.indirect_offset = offset;
3329
3330 radv_dispatch(cmd_buffer, &info);
3331 }
3332
3333 void radv_unaligned_dispatch(
3334 struct radv_cmd_buffer *cmd_buffer,
3335 uint32_t x,
3336 uint32_t y,
3337 uint32_t z)
3338 {
3339 struct radv_dispatch_info info = {};
3340
3341 info.blocks[0] = x;
3342 info.blocks[1] = y;
3343 info.blocks[2] = z;
3344 info.unaligned = 1;
3345
3346 radv_dispatch(cmd_buffer, &info);
3347 }
3348
3349 void radv_CmdEndRenderPass(
3350 VkCommandBuffer commandBuffer)
3351 {
3352 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3353
3354 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3355
3356 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3357
3358 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3359 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3360 radv_handle_subpass_image_transition(cmd_buffer,
3361 (VkAttachmentReference){i, layout});
3362 }
3363
3364 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3365
3366 cmd_buffer->state.pass = NULL;
3367 cmd_buffer->state.subpass = NULL;
3368 cmd_buffer->state.attachments = NULL;
3369 cmd_buffer->state.framebuffer = NULL;
3370 }
3371
3372 /*
3373 * For HTILE we have the following interesting clear words:
3374 * 0x0000030f: Uncompressed.
3375 * 0xfffffff0: Clear depth to 1.0
3376 * 0x00000000: Clear depth to 0.0
3377 */
3378 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3379 struct radv_image *image,
3380 const VkImageSubresourceRange *range,
3381 uint32_t clear_word)
3382 {
3383 assert(range->baseMipLevel == 0);
3384 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3385 unsigned layer_count = radv_get_layerCount(image, range);
3386 uint64_t size = image->surface.htile_slice_size * layer_count;
3387 uint64_t offset = image->offset + image->htile_offset +
3388 image->surface.htile_slice_size * range->baseArrayLayer;
3389
3390 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3391 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3392
3393 radv_fill_buffer(cmd_buffer, image->bo, offset, size, clear_word);
3394
3395 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
3396 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3397 RADV_CMD_FLAG_INV_VMEM_L1 |
3398 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3399 }
3400
3401 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3402 struct radv_image *image,
3403 VkImageLayout src_layout,
3404 VkImageLayout dst_layout,
3405 unsigned src_queue_mask,
3406 unsigned dst_queue_mask,
3407 const VkImageSubresourceRange *range,
3408 VkImageAspectFlags pending_clears)
3409 {
3410 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3411 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3412 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3413 cmd_buffer->state.render_area.extent.width == image->info.width &&
3414 cmd_buffer->state.render_area.extent.height == image->info.height) {
3415 /* The clear will initialize htile. */
3416 return;
3417 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3418 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3419 /* TODO: merge with the clear if applicable */
3420 radv_initialize_htile(cmd_buffer, image, range, 0);
3421 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3422 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3423 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3424 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3425 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3426 VkImageSubresourceRange local_range = *range;
3427 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3428 local_range.baseMipLevel = 0;
3429 local_range.levelCount = 1;
3430
3431 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3432 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3433
3434 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3435
3436 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3437 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3438 }
3439 }
3440
3441 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3442 struct radv_image *image, uint32_t value)
3443 {
3444 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3445 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3446
3447 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
3448 image->cmask.size, value);
3449
3450 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3451 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3452 RADV_CMD_FLAG_INV_VMEM_L1 |
3453 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3454 }
3455
3456 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3457 struct radv_image *image,
3458 VkImageLayout src_layout,
3459 VkImageLayout dst_layout,
3460 unsigned src_queue_mask,
3461 unsigned dst_queue_mask,
3462 const VkImageSubresourceRange *range)
3463 {
3464 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3465 if (image->fmask.size)
3466 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3467 else
3468 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3469 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3470 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3471 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3472 }
3473 }
3474
3475 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3476 struct radv_image *image, uint32_t value)
3477 {
3478
3479 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3480 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3481
3482 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
3483 image->surface.dcc_size, value);
3484
3485 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3486 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
3487 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
3488 RADV_CMD_FLAG_INV_VMEM_L1 |
3489 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
3490 }
3491
3492 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3493 struct radv_image *image,
3494 VkImageLayout src_layout,
3495 VkImageLayout dst_layout,
3496 unsigned src_queue_mask,
3497 unsigned dst_queue_mask,
3498 const VkImageSubresourceRange *range)
3499 {
3500 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3501 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3502 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3503 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3504 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3505 }
3506 }
3507
3508 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3509 struct radv_image *image,
3510 VkImageLayout src_layout,
3511 VkImageLayout dst_layout,
3512 uint32_t src_family,
3513 uint32_t dst_family,
3514 const VkImageSubresourceRange *range,
3515 VkImageAspectFlags pending_clears)
3516 {
3517 if (image->exclusive && src_family != dst_family) {
3518 /* This is an acquire or a release operation and there will be
3519 * a corresponding release/acquire. Do the transition in the
3520 * most flexible queue. */
3521
3522 assert(src_family == cmd_buffer->queue_family_index ||
3523 dst_family == cmd_buffer->queue_family_index);
3524
3525 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3526 return;
3527
3528 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3529 (src_family == RADV_QUEUE_GENERAL ||
3530 dst_family == RADV_QUEUE_GENERAL))
3531 return;
3532 }
3533
3534 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3535 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3536
3537 if (image->surface.htile_size)
3538 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3539 dst_layout, src_queue_mask,
3540 dst_queue_mask, range,
3541 pending_clears);
3542
3543 if (image->cmask.size)
3544 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3545 dst_layout, src_queue_mask,
3546 dst_queue_mask, range);
3547
3548 if (image->surface.dcc_size)
3549 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3550 dst_layout, src_queue_mask,
3551 dst_queue_mask, range);
3552 }
3553
3554 void radv_CmdPipelineBarrier(
3555 VkCommandBuffer commandBuffer,
3556 VkPipelineStageFlags srcStageMask,
3557 VkPipelineStageFlags destStageMask,
3558 VkBool32 byRegion,
3559 uint32_t memoryBarrierCount,
3560 const VkMemoryBarrier* pMemoryBarriers,
3561 uint32_t bufferMemoryBarrierCount,
3562 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3563 uint32_t imageMemoryBarrierCount,
3564 const VkImageMemoryBarrier* pImageMemoryBarriers)
3565 {
3566 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3567 enum radv_cmd_flush_bits src_flush_bits = 0;
3568 enum radv_cmd_flush_bits dst_flush_bits = 0;
3569
3570 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3571 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3572 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3573 NULL);
3574 }
3575
3576 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3577 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3578 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3579 NULL);
3580 }
3581
3582 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3583 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3584 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3585 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3586 image);
3587 }
3588
3589 radv_stage_flush(cmd_buffer, srcStageMask);
3590 cmd_buffer->state.flush_bits |= src_flush_bits;
3591
3592 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3593 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3594 radv_handle_image_transition(cmd_buffer, image,
3595 pImageMemoryBarriers[i].oldLayout,
3596 pImageMemoryBarriers[i].newLayout,
3597 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3598 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3599 &pImageMemoryBarriers[i].subresourceRange,
3600 0);
3601 }
3602
3603 cmd_buffer->state.flush_bits |= dst_flush_bits;
3604 }
3605
3606
3607 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3608 struct radv_event *event,
3609 VkPipelineStageFlags stageMask,
3610 unsigned value)
3611 {
3612 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3613 uint64_t va = radv_buffer_get_va(event->bo);
3614
3615 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3616
3617 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3618
3619 /* TODO: this is overkill. Probably should figure something out from
3620 * the stage mask. */
3621
3622 si_cs_emit_write_event_eop(cs,
3623 cmd_buffer->state.predicating,
3624 cmd_buffer->device->physical_device->rad_info.chip_class,
3625 false,
3626 EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
3627 1, va, 2, value);
3628
3629 assert(cmd_buffer->cs->cdw <= cdw_max);
3630 }
3631
3632 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3633 VkEvent _event,
3634 VkPipelineStageFlags stageMask)
3635 {
3636 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3637 RADV_FROM_HANDLE(radv_event, event, _event);
3638
3639 write_event(cmd_buffer, event, stageMask, 1);
3640 }
3641
3642 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3643 VkEvent _event,
3644 VkPipelineStageFlags stageMask)
3645 {
3646 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3647 RADV_FROM_HANDLE(radv_event, event, _event);
3648
3649 write_event(cmd_buffer, event, stageMask, 0);
3650 }
3651
3652 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3653 uint32_t eventCount,
3654 const VkEvent* pEvents,
3655 VkPipelineStageFlags srcStageMask,
3656 VkPipelineStageFlags dstStageMask,
3657 uint32_t memoryBarrierCount,
3658 const VkMemoryBarrier* pMemoryBarriers,
3659 uint32_t bufferMemoryBarrierCount,
3660 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3661 uint32_t imageMemoryBarrierCount,
3662 const VkImageMemoryBarrier* pImageMemoryBarriers)
3663 {
3664 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3665 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3666
3667 for (unsigned i = 0; i < eventCount; ++i) {
3668 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3669 uint64_t va = radv_buffer_get_va(event->bo);
3670
3671 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3672
3673 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3674
3675 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3676 assert(cmd_buffer->cs->cdw <= cdw_max);
3677 }
3678
3679
3680 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3681 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3682
3683 radv_handle_image_transition(cmd_buffer, image,
3684 pImageMemoryBarriers[i].oldLayout,
3685 pImageMemoryBarriers[i].newLayout,
3686 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3687 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3688 &pImageMemoryBarriers[i].subresourceRange,
3689 0);
3690 }
3691
3692 /* TODO: figure out how to do memory barriers without waiting */
3693 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3694 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3695 RADV_CMD_FLAG_INV_VMEM_L1 |
3696 RADV_CMD_FLAG_INV_SMEM_L1;
3697 }