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radv: port polaris vgt vertex reuse workaround.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_cs.h"
31 #include "sid.h"
32 #include "vk_format.h"
33 #include "radv_meta.h"
34
35 #include "ac_debug.h"
36
37 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
38 struct radv_image *image,
39 VkImageLayout src_layout,
40 VkImageLayout dst_layout,
41 uint32_t src_family,
42 uint32_t dst_family,
43 const VkImageSubresourceRange *range,
44 VkImageAspectFlags pending_clears);
45
46 const struct radv_dynamic_state default_dynamic_state = {
47 .viewport = {
48 .count = 0,
49 },
50 .scissor = {
51 .count = 0,
52 },
53 .line_width = 1.0f,
54 .depth_bias = {
55 .bias = 0.0f,
56 .clamp = 0.0f,
57 .slope = 0.0f,
58 },
59 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
60 .depth_bounds = {
61 .min = 0.0f,
62 .max = 1.0f,
63 },
64 .stencil_compare_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_write_mask = {
69 .front = ~0u,
70 .back = ~0u,
71 },
72 .stencil_reference = {
73 .front = 0u,
74 .back = 0u,
75 },
76 };
77
78 void
79 radv_dynamic_state_copy(struct radv_dynamic_state *dest,
80 const struct radv_dynamic_state *src,
81 uint32_t copy_mask)
82 {
83 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
84 dest->viewport.count = src->viewport.count;
85 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
86 src->viewport.count);
87 }
88
89 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
90 dest->scissor.count = src->scissor.count;
91 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
92 src->scissor.count);
93 }
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
96 dest->line_width = src->line_width;
97
98 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
99 dest->depth_bias = src->depth_bias;
100
101 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
102 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
103
104 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
105 dest->depth_bounds = src->depth_bounds;
106
107 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
108 dest->stencil_compare_mask = src->stencil_compare_mask;
109
110 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
111 dest->stencil_write_mask = src->stencil_write_mask;
112
113 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
114 dest->stencil_reference = src->stencil_reference;
115 }
116
117 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
118 {
119 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
120 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
121 }
122
123 enum ring_type radv_queue_family_to_ring(int f) {
124 switch (f) {
125 case RADV_QUEUE_GENERAL:
126 return RING_GFX;
127 case RADV_QUEUE_COMPUTE:
128 return RING_COMPUTE;
129 case RADV_QUEUE_TRANSFER:
130 return RING_DMA;
131 default:
132 unreachable("Unknown queue family");
133 }
134 }
135
136 static VkResult radv_create_cmd_buffer(
137 struct radv_device * device,
138 struct radv_cmd_pool * pool,
139 VkCommandBufferLevel level,
140 VkCommandBuffer* pCommandBuffer)
141 {
142 struct radv_cmd_buffer *cmd_buffer;
143 VkResult result;
144 unsigned ring;
145 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
147 if (cmd_buffer == NULL)
148 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
149
150 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
151 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
152 cmd_buffer->device = device;
153 cmd_buffer->pool = pool;
154 cmd_buffer->level = level;
155
156 if (pool) {
157 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
158 cmd_buffer->queue_family_index = pool->queue_family_index;
159
160 } else {
161 /* Init the pool_link so we can safefly call list_del when we destroy
162 * the command buffer
163 */
164 list_inithead(&cmd_buffer->pool_link);
165 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
166 }
167
168 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
169
170 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
171 if (!cmd_buffer->cs) {
172 result = VK_ERROR_OUT_OF_HOST_MEMORY;
173 goto fail;
174 }
175
176 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
177
178 cmd_buffer->upload.offset = 0;
179 cmd_buffer->upload.size = 0;
180 list_inithead(&cmd_buffer->upload.list);
181
182 return VK_SUCCESS;
183
184 fail:
185 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
186
187 return result;
188 }
189
190 static void
191 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
192 {
193 list_del(&cmd_buffer->pool_link);
194
195 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
196 &cmd_buffer->upload.list, list) {
197 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
198 list_del(&up->list);
199 free(up);
200 }
201
202 if (cmd_buffer->upload.upload_bo)
203 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
204 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
205 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
206 }
207
208 static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
209 {
210
211 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
212
213 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
214 &cmd_buffer->upload.list, list) {
215 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
216 list_del(&up->list);
217 free(up);
218 }
219
220 cmd_buffer->scratch_size_needed = 0;
221 cmd_buffer->compute_scratch_size_needed = 0;
222 cmd_buffer->esgs_ring_size_needed = 0;
223 cmd_buffer->gsvs_ring_size_needed = 0;
224 cmd_buffer->tess_rings_needed = false;
225
226 if (cmd_buffer->upload.upload_bo)
227 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
228 cmd_buffer->upload.upload_bo, 8);
229 cmd_buffer->upload.offset = 0;
230
231 cmd_buffer->record_fail = false;
232
233 cmd_buffer->ring_offsets_idx = -1;
234 }
235
236 static bool
237 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
238 uint64_t min_needed)
239 {
240 uint64_t new_size;
241 struct radeon_winsys_bo *bo;
242 struct radv_cmd_buffer_upload *upload;
243 struct radv_device *device = cmd_buffer->device;
244
245 new_size = MAX2(min_needed, 16 * 1024);
246 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
247
248 bo = device->ws->buffer_create(device->ws,
249 new_size, 4096,
250 RADEON_DOMAIN_GTT,
251 RADEON_FLAG_CPU_ACCESS);
252
253 if (!bo) {
254 cmd_buffer->record_fail = true;
255 return false;
256 }
257
258 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
259 if (cmd_buffer->upload.upload_bo) {
260 upload = malloc(sizeof(*upload));
261
262 if (!upload) {
263 cmd_buffer->record_fail = true;
264 device->ws->buffer_destroy(bo);
265 return false;
266 }
267
268 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
269 list_add(&upload->list, &cmd_buffer->upload.list);
270 }
271
272 cmd_buffer->upload.upload_bo = bo;
273 cmd_buffer->upload.size = new_size;
274 cmd_buffer->upload.offset = 0;
275 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
276
277 if (!cmd_buffer->upload.map) {
278 cmd_buffer->record_fail = true;
279 return false;
280 }
281
282 return true;
283 }
284
285 bool
286 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
287 unsigned size,
288 unsigned alignment,
289 unsigned *out_offset,
290 void **ptr)
291 {
292 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
293 if (offset + size > cmd_buffer->upload.size) {
294 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
295 return false;
296 offset = 0;
297 }
298
299 *out_offset = offset;
300 *ptr = cmd_buffer->upload.map + offset;
301
302 cmd_buffer->upload.offset = offset + size;
303 return true;
304 }
305
306 bool
307 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
308 unsigned size, unsigned alignment,
309 const void *data, unsigned *out_offset)
310 {
311 uint8_t *ptr;
312
313 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
314 out_offset, (void **)&ptr))
315 return false;
316
317 if (ptr)
318 memcpy(ptr, data, size);
319
320 return true;
321 }
322
323 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
324 {
325 struct radv_device *device = cmd_buffer->device;
326 struct radeon_winsys_cs *cs = cmd_buffer->cs;
327 uint64_t va;
328
329 if (!device->trace_bo)
330 return;
331
332 va = device->ws->buffer_get_va(device->trace_bo);
333
334 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
335
336 ++cmd_buffer->state.trace_id;
337 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
338 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
339 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
340 S_370_WR_CONFIRM(1) |
341 S_370_ENGINE_SEL(V_370_ME));
342 radeon_emit(cs, va);
343 radeon_emit(cs, va >> 32);
344 radeon_emit(cs, cmd_buffer->state.trace_id);
345 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
346 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
347 }
348
349 static void
350 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
351 struct radv_pipeline *pipeline)
352 {
353 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
354 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
355 8);
356 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
357 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
358 }
359
360 static void
361 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
362 struct radv_pipeline *pipeline)
363 {
364 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
365 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
366 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
367
368 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
369 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
370 }
371
372 /* 12.4 fixed-point */
373 static unsigned radv_pack_float_12p4(float x)
374 {
375 return x <= 0 ? 0 :
376 x >= 4096 ? 0xffff : x * 16;
377 }
378
379 static uint32_t
380 shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess)
381 {
382 switch (stage) {
383 case MESA_SHADER_FRAGMENT:
384 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
385 case MESA_SHADER_VERTEX:
386 if (has_tess)
387 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
388 else
389 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
390 case MESA_SHADER_GEOMETRY:
391 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
392 case MESA_SHADER_COMPUTE:
393 return R_00B900_COMPUTE_USER_DATA_0;
394 case MESA_SHADER_TESS_CTRL:
395 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
396 case MESA_SHADER_TESS_EVAL:
397 if (has_gs)
398 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
399 else
400 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
401 default:
402 unreachable("unknown shader");
403 }
404 }
405
406 static struct ac_userdata_info *
407 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
408 gl_shader_stage stage,
409 int idx)
410 {
411 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
412 }
413
414 static void
415 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
416 struct radv_pipeline *pipeline,
417 gl_shader_stage stage,
418 int idx, uint64_t va)
419 {
420 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
421 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
422 if (loc->sgpr_idx == -1)
423 return;
424 assert(loc->num_sgprs == 2);
425 assert(!loc->indirect);
426 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
427 radeon_emit(cmd_buffer->cs, va);
428 radeon_emit(cmd_buffer->cs, va >> 32);
429 }
430
431 static void
432 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
433 struct radv_pipeline *pipeline)
434 {
435 int num_samples = pipeline->graphics.ms.num_samples;
436 struct radv_multisample_state *ms = &pipeline->graphics.ms;
437 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
438
439 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
440 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
441 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
442
443 radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa);
444 radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
445
446 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
447 return;
448
449 radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
450 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
451 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
452
453 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
454
455 uint32_t samples_offset;
456 void *samples_ptr;
457 void *src;
458 radv_cmd_buffer_upload_alloc(cmd_buffer, num_samples * 4 * 2, 256, &samples_offset,
459 &samples_ptr);
460 switch (num_samples) {
461 case 1:
462 src = cmd_buffer->device->sample_locations_1x;
463 break;
464 case 2:
465 src = cmd_buffer->device->sample_locations_2x;
466 break;
467 case 4:
468 src = cmd_buffer->device->sample_locations_4x;
469 break;
470 case 8:
471 src = cmd_buffer->device->sample_locations_8x;
472 break;
473 case 16:
474 src = cmd_buffer->device->sample_locations_16x;
475 break;
476 default:
477 unreachable("unknown number of samples");
478 }
479 memcpy(samples_ptr, src, num_samples * 4 * 2);
480
481 uint64_t va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
482 va += samples_offset;
483
484 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
485 AC_UD_PS_SAMPLE_POS, va);
486 }
487
488 static void
489 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
490 struct radv_pipeline *pipeline)
491 {
492 struct radv_raster_state *raster = &pipeline->graphics.raster;
493
494 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
495 raster->pa_cl_clip_cntl);
496
497 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
498 raster->spi_interp_control);
499
500 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
501 unsigned tmp = (unsigned)(1.0 * 8.0);
502 radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
503 radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
504 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
505
506 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
507 raster->pa_su_vtx_cntl);
508
509 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
510 raster->pa_su_sc_mode_cntl);
511 }
512
513 static void
514 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
515 struct radv_pipeline *pipeline,
516 struct radv_shader_variant *shader,
517 struct ac_vs_output_info *outinfo)
518 {
519 struct radeon_winsys *ws = cmd_buffer->device->ws;
520 uint64_t va = ws->buffer_get_va(shader->bo);
521 unsigned export_count;
522
523 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
524
525 export_count = MAX2(1, outinfo->param_exports);
526 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
527 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
528
529 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
530 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
531 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
532 V_02870C_SPI_SHADER_4COMP :
533 V_02870C_SPI_SHADER_NONE) |
534 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
535 V_02870C_SPI_SHADER_4COMP :
536 V_02870C_SPI_SHADER_NONE) |
537 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
538 V_02870C_SPI_SHADER_4COMP :
539 V_02870C_SPI_SHADER_NONE));
540
541
542 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
543 radeon_emit(cmd_buffer->cs, va >> 8);
544 radeon_emit(cmd_buffer->cs, va >> 40);
545 radeon_emit(cmd_buffer->cs, shader->rsrc1);
546 radeon_emit(cmd_buffer->cs, shader->rsrc2);
547
548 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
549 S_028818_VTX_W0_FMT(1) |
550 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
551 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
552 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
553
554
555 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
556 pipeline->graphics.pa_cl_vs_out_cntl);
557
558 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
559 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
560 }
561
562 static void
563 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
564 struct radv_shader_variant *shader,
565 struct ac_es_output_info *outinfo)
566 {
567 struct radeon_winsys *ws = cmd_buffer->device->ws;
568 uint64_t va = ws->buffer_get_va(shader->bo);
569
570 ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
571
572 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
573 outinfo->esgs_itemsize / 4);
574 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
575 radeon_emit(cmd_buffer->cs, va >> 8);
576 radeon_emit(cmd_buffer->cs, va >> 40);
577 radeon_emit(cmd_buffer->cs, shader->rsrc1);
578 radeon_emit(cmd_buffer->cs, shader->rsrc2);
579 }
580
581 static void
582 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
583 struct radv_pipeline *pipeline)
584 {
585 struct radv_shader_variant *vs;
586
587 assert (pipeline->shaders[MESA_SHADER_VERTEX]);
588
589 vs = pipeline->shaders[MESA_SHADER_VERTEX];
590
591 if (vs->info.vs.as_es)
592 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
593 else
594 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
595
596 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
597 }
598
599
600 static void
601 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
602 struct radv_pipeline *pipeline)
603 {
604 struct radeon_winsys *ws = cmd_buffer->device->ws;
605 struct radv_shader_variant *gs;
606 uint64_t va;
607
608 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
609
610 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
611 if (!gs)
612 return;
613
614 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
615
616 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
617 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
618 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
619 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
620
621 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
622
623 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
624
625 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
626 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
627 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
628 radeon_emit(cmd_buffer->cs, 0);
629 radeon_emit(cmd_buffer->cs, 0);
630 radeon_emit(cmd_buffer->cs, 0);
631
632 uint32_t gs_num_invocations = gs->info.gs.invocations;
633 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
634 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
635 S_028B90_ENABLE(gs_num_invocations > 0));
636
637 va = ws->buffer_get_va(gs->bo);
638 ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
639 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
640 radeon_emit(cmd_buffer->cs, va >> 8);
641 radeon_emit(cmd_buffer->cs, va >> 40);
642 radeon_emit(cmd_buffer->cs, gs->rsrc1);
643 radeon_emit(cmd_buffer->cs, gs->rsrc2);
644
645 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
646
647 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
648 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
649 if (loc->sgpr_idx != -1) {
650 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
651 uint32_t num_entries = 64;
652 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
653
654 if (is_vi)
655 num_entries *= stride;
656
657 stride = S_008F04_STRIDE(stride);
658 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
659 radeon_emit(cmd_buffer->cs, stride);
660 radeon_emit(cmd_buffer->cs, num_entries);
661 }
662 }
663
664 static void
665 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
666 struct radv_pipeline *pipeline)
667 {
668 struct radeon_winsys *ws = cmd_buffer->device->ws;
669 struct radv_shader_variant *ps;
670 uint64_t va;
671 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
672 struct radv_blend_state *blend = &pipeline->graphics.blend;
673 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
674
675 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
676
677 va = ws->buffer_get_va(ps->bo);
678 ws->cs_add_buffer(cmd_buffer->cs, ps->bo, 8);
679
680 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
681 radeon_emit(cmd_buffer->cs, va >> 8);
682 radeon_emit(cmd_buffer->cs, va >> 40);
683 radeon_emit(cmd_buffer->cs, ps->rsrc1);
684 radeon_emit(cmd_buffer->cs, ps->rsrc2);
685
686 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
687 pipeline->graphics.db_shader_control);
688
689 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
690 ps->config.spi_ps_input_ena);
691
692 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
693 ps->config.spi_ps_input_addr);
694
695 if (ps->info.fs.force_persample)
696 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
697
698 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
699 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
700
701 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
702
703 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
704 pipeline->graphics.shader_z_format);
705
706 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
707
708 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
709 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
710
711 if (pipeline->graphics.ps_input_cntl_num) {
712 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
713 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
714 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
715 }
716 }
717 }
718
719 static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
720 struct radv_pipeline *pipeline)
721 {
722 uint32_t vtx_reuse_depth = 30;
723 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
724 return;
725
726 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
727 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
728 vtx_reuse_depth = 14;
729 }
730 radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
731 vtx_reuse_depth);
732 }
733
734 static void
735 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
736 struct radv_pipeline *pipeline)
737 {
738 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
739 return;
740
741 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
742 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
743 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
744 radv_update_multisample_state(cmd_buffer, pipeline);
745 radv_emit_vertex_shader(cmd_buffer, pipeline);
746 radv_emit_geometry_shader(cmd_buffer, pipeline);
747 radv_emit_fragment_shader(cmd_buffer, pipeline);
748 polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
749
750 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
751 pipeline->graphics.prim_restart_enable);
752
753 cmd_buffer->scratch_size_needed =
754 MAX2(cmd_buffer->scratch_size_needed,
755 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
756
757 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
758 S_0286E8_WAVES(pipeline->max_waves) |
759 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
760
761 if (!cmd_buffer->state.emitted_pipeline ||
762 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
763 pipeline->graphics.can_use_guardband)
764 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
765 cmd_buffer->state.emitted_pipeline = pipeline;
766 }
767
768 static void
769 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
770 {
771 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
772 cmd_buffer->state.dynamic.viewport.viewports);
773 }
774
775 static void
776 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
777 {
778 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
779 si_write_scissors(cmd_buffer->cs, 0, count,
780 cmd_buffer->state.dynamic.scissor.scissors,
781 cmd_buffer->state.dynamic.viewport.viewports,
782 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
783 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
784 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
785 }
786
787 static void
788 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
789 int index,
790 struct radv_color_buffer_info *cb)
791 {
792 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
793 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
794 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
795 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
796 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
797 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
798 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
799 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
800 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
801 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
802 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
803 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
804 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
805
806 if (is_vi) { /* DCC BASE */
807 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
808 }
809 }
810
811 static void
812 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
813 struct radv_ds_buffer_info *ds,
814 struct radv_image *image,
815 VkImageLayout layout)
816 {
817 uint32_t db_z_info = ds->db_z_info;
818
819 if (!radv_layout_has_htile(image, layout))
820 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
821
822 if (!radv_layout_can_expclear(image, layout))
823 db_z_info &= C_028040_ALLOW_EXPCLEAR & C_028044_ALLOW_EXPCLEAR;
824
825 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
826 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
827
828 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
829 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
830 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
831 radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
832 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
833 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
834 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
835 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
836 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
837 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
838
839 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
840 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
841 ds->pa_su_poly_offset_db_fmt_cntl);
842 }
843
844 /*
845 * To hw resolve multisample images both src and dst need to have the same
846 * micro tiling mode. However we don't always know in advance when creating
847 * the images. This function gets called if we have a resolve attachment,
848 * and tests if the attachment image has the same tiling mode, then it
849 * checks if the generated framebuffer data has the same tiling mode, and
850 * updates it if not.
851 */
852 static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
853 struct radv_attachment_info *att,
854 uint32_t micro_tile_mode)
855 {
856 struct radv_image *image = att->attachment->image;
857 uint32_t tile_mode_index;
858 if (image->surface.nsamples <= 1)
859 return;
860
861 if (image->surface.micro_tile_mode != micro_tile_mode) {
862 radv_image_set_optimal_micro_tile_mode(device, image, micro_tile_mode);
863 }
864
865 if (att->cb.micro_tile_mode != micro_tile_mode) {
866 tile_mode_index = image->surface.tiling_index[0];
867
868 att->cb.cb_color_attrib &= C_028C74_TILE_MODE_INDEX;
869 att->cb.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
870 att->cb.micro_tile_mode = micro_tile_mode;
871 }
872 }
873
874 void
875 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
876 struct radv_image *image,
877 VkClearDepthStencilValue ds_clear_value,
878 VkImageAspectFlags aspects)
879 {
880 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
881 va += image->offset + image->clear_value_offset;
882 unsigned reg_offset = 0, reg_count = 0;
883
884 if (!image->surface.htile_size || !aspects)
885 return;
886
887 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
888 ++reg_count;
889 } else {
890 ++reg_offset;
891 va += 4;
892 }
893 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
894 ++reg_count;
895
896 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
897
898 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
899 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
900 S_370_WR_CONFIRM(1) |
901 S_370_ENGINE_SEL(V_370_PFP));
902 radeon_emit(cmd_buffer->cs, va);
903 radeon_emit(cmd_buffer->cs, va >> 32);
904 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
905 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
906 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
907 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
908
909 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
910 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
911 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
912 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
913 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
914 }
915
916 static void
917 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
918 struct radv_image *image)
919 {
920 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
921 va += image->offset + image->clear_value_offset;
922
923 if (!image->surface.htile_size)
924 return;
925
926 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
927
928 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
929 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
930 COPY_DATA_DST_SEL(COPY_DATA_REG) |
931 COPY_DATA_COUNT_SEL);
932 radeon_emit(cmd_buffer->cs, va);
933 radeon_emit(cmd_buffer->cs, va >> 32);
934 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
935 radeon_emit(cmd_buffer->cs, 0);
936
937 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
938 radeon_emit(cmd_buffer->cs, 0);
939 }
940
941 void
942 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
943 struct radv_image *image,
944 int idx,
945 uint32_t color_values[2])
946 {
947 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
948 va += image->offset + image->clear_value_offset;
949
950 if (!image->cmask.size && !image->surface.dcc_size)
951 return;
952
953 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
954
955 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
956 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
957 S_370_WR_CONFIRM(1) |
958 S_370_ENGINE_SEL(V_370_PFP));
959 radeon_emit(cmd_buffer->cs, va);
960 radeon_emit(cmd_buffer->cs, va >> 32);
961 radeon_emit(cmd_buffer->cs, color_values[0]);
962 radeon_emit(cmd_buffer->cs, color_values[1]);
963
964 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
965 radeon_emit(cmd_buffer->cs, color_values[0]);
966 radeon_emit(cmd_buffer->cs, color_values[1]);
967 }
968
969 static void
970 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
971 struct radv_image *image,
972 int idx)
973 {
974 uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
975 va += image->offset + image->clear_value_offset;
976
977 if (!image->cmask.size && !image->surface.dcc_size)
978 return;
979
980 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
981 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
982
983 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
984 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
985 COPY_DATA_DST_SEL(COPY_DATA_REG) |
986 COPY_DATA_COUNT_SEL);
987 radeon_emit(cmd_buffer->cs, va);
988 radeon_emit(cmd_buffer->cs, va >> 32);
989 radeon_emit(cmd_buffer->cs, reg >> 2);
990 radeon_emit(cmd_buffer->cs, 0);
991
992 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
993 radeon_emit(cmd_buffer->cs, 0);
994 }
995
996 void
997 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
998 {
999 int i;
1000 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1001 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1002 int dst_resolve_micro_tile_mode = -1;
1003
1004 if (subpass->has_resolve) {
1005 uint32_t a = subpass->resolve_attachments[0].attachment;
1006 const struct radv_image *image = framebuffer->attachments[a].attachment->image;
1007 dst_resolve_micro_tile_mode = image->surface.micro_tile_mode;
1008 }
1009 for (i = 0; i < subpass->color_count; ++i) {
1010 int idx = subpass->color_attachments[i].attachment;
1011 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1012
1013 if (dst_resolve_micro_tile_mode != -1) {
1014 radv_set_optimal_micro_tile_mode(cmd_buffer->device,
1015 att, dst_resolve_micro_tile_mode);
1016 }
1017 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1018
1019 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1020 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1021
1022 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1023 }
1024
1025 for (i = subpass->color_count; i < 8; i++)
1026 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1027 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1028
1029 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1030 int idx = subpass->depth_stencil_attachment.attachment;
1031 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1032 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1033 struct radv_image *image = att->attachment->image;
1034 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1035
1036 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1037
1038 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1039 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1040 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1041 }
1042 radv_load_depth_clear_regs(cmd_buffer, image);
1043 } else {
1044 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1045 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1046 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1047 }
1048 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1049 S_028208_BR_X(framebuffer->width) |
1050 S_028208_BR_Y(framebuffer->height));
1051 }
1052
1053 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1054 {
1055 uint32_t db_count_control;
1056
1057 if(!cmd_buffer->state.active_occlusion_queries) {
1058 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1059 db_count_control = 0;
1060 } else {
1061 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1062 }
1063 } else {
1064 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1065 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1066 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1067 S_028004_ZPASS_ENABLE(1) |
1068 S_028004_SLICE_EVEN_ENABLE(1) |
1069 S_028004_SLICE_ODD_ENABLE(1);
1070 } else {
1071 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1072 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1073 }
1074 }
1075
1076 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1077 }
1078
1079 static void
1080 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1081 {
1082 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1083
1084 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1085 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1086 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1087 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1088 }
1089
1090 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
1091 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1092 radeon_emit_array(cmd_buffer->cs, (uint32_t*)d->blend_constants, 4);
1093 }
1094
1095 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1096 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1097 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)) {
1098 radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);
1099 radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1100 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1101 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1102 S_028430_STENCILOPVAL(1));
1103 radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1104 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1105 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1106 S_028434_STENCILOPVAL_BF(1));
1107 }
1108
1109 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1110 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
1111 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min));
1112 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max));
1113 }
1114
1115 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1116 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
1117 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1118 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1119 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1120
1121 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1122 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1123 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1124 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1125 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1126 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1127 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1128 }
1129 }
1130
1131 cmd_buffer->state.dirty = 0;
1132 }
1133
1134 static void
1135 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1136 struct radv_pipeline *pipeline,
1137 int idx,
1138 uint64_t va,
1139 gl_shader_stage stage)
1140 {
1141 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1142 uint32_t base_reg = shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1143
1144 if (desc_set_loc->sgpr_idx == -1)
1145 return;
1146
1147 assert(!desc_set_loc->indirect);
1148 assert(desc_set_loc->num_sgprs == 2);
1149 radeon_set_sh_reg_seq(cmd_buffer->cs,
1150 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1151 radeon_emit(cmd_buffer->cs, va);
1152 radeon_emit(cmd_buffer->cs, va >> 32);
1153 }
1154
1155 static void
1156 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1157 struct radv_pipeline *pipeline,
1158 VkShaderStageFlags stages,
1159 struct radv_descriptor_set *set,
1160 unsigned idx)
1161 {
1162 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1163 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1164 idx, set->va,
1165 MESA_SHADER_FRAGMENT);
1166
1167 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1168 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1169 idx, set->va,
1170 MESA_SHADER_VERTEX);
1171
1172 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1173 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1174 idx, set->va,
1175 MESA_SHADER_GEOMETRY);
1176
1177 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1178 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1179 idx, set->va,
1180 MESA_SHADER_TESS_CTRL);
1181
1182 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1183 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1184 idx, set->va,
1185 MESA_SHADER_TESS_EVAL);
1186
1187 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1188 emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
1189 idx, set->va,
1190 MESA_SHADER_COMPUTE);
1191 }
1192
1193 static void
1194 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1195 struct radv_pipeline *pipeline,
1196 VkShaderStageFlags stages)
1197 {
1198 unsigned i;
1199 if (!cmd_buffer->state.descriptors_dirty)
1200 return;
1201
1202 for (i = 0; i < MAX_SETS; i++) {
1203 if (!(cmd_buffer->state.descriptors_dirty & (1 << i)))
1204 continue;
1205 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1206 if (!set)
1207 continue;
1208
1209 radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
1210 }
1211 cmd_buffer->state.descriptors_dirty = 0;
1212 }
1213
1214 static void
1215 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1216 struct radv_pipeline *pipeline,
1217 VkShaderStageFlags stages)
1218 {
1219 struct radv_pipeline_layout *layout = pipeline->layout;
1220 unsigned offset;
1221 void *ptr;
1222 uint64_t va;
1223
1224 stages &= cmd_buffer->push_constant_stages;
1225 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1226 return;
1227
1228 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1229 16 * layout->dynamic_offset_count,
1230 256, &offset, &ptr))
1231 return;
1232
1233 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1234 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1235 16 * layout->dynamic_offset_count);
1236
1237 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1238 va += offset;
1239
1240 if (stages & VK_SHADER_STAGE_VERTEX_BIT)
1241 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1242 AC_UD_PUSH_CONSTANTS, va);
1243
1244 if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
1245 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,
1246 AC_UD_PUSH_CONSTANTS, va);
1247
1248 if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
1249 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,
1250 AC_UD_PUSH_CONSTANTS, va);
1251
1252 if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
1253 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL,
1254 AC_UD_PUSH_CONSTANTS, va);
1255
1256 if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
1257 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL,
1258 AC_UD_PUSH_CONSTANTS, va);
1259
1260 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
1261 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,
1262 AC_UD_PUSH_CONSTANTS, va);
1263
1264 cmd_buffer->push_constant_stages &= ~stages;
1265 }
1266
1267 static void
1268 radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
1269 bool instanced_draw, bool indirect_draw,
1270 uint32_t draw_vertex_count)
1271 {
1272 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1273 struct radv_device *device = cmd_buffer->device;
1274 uint32_t ia_multi_vgt_param;
1275 uint32_t ls_hs_config = 0;
1276
1277 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1278 cmd_buffer->cs, 4096);
1279
1280 if ((cmd_buffer->state.vertex_descriptors_dirty || cmd_buffer->state.vb_dirty) &&
1281 cmd_buffer->state.pipeline->num_vertex_attribs) {
1282 unsigned vb_offset;
1283 void *vb_ptr;
1284 uint32_t i = 0;
1285 uint32_t num_attribs = cmd_buffer->state.pipeline->num_vertex_attribs;
1286 uint64_t va;
1287
1288 /* allocate some descriptor state for vertex buffers */
1289 radv_cmd_buffer_upload_alloc(cmd_buffer, num_attribs * 16, 256,
1290 &vb_offset, &vb_ptr);
1291
1292 for (i = 0; i < num_attribs; i++) {
1293 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1294 uint32_t offset;
1295 int vb = cmd_buffer->state.pipeline->va_binding[i];
1296 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1297 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1298
1299 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1300 va = device->ws->buffer_get_va(buffer->bo);
1301
1302 offset = cmd_buffer->state.vertex_bindings[vb].offset + cmd_buffer->state.pipeline->va_offset[i];
1303 va += offset + buffer->offset;
1304 desc[0] = va;
1305 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1306 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1307 desc[2] = (buffer->size - offset - cmd_buffer->state.pipeline->va_format_size[i]) / stride + 1;
1308 else
1309 desc[2] = buffer->size - offset;
1310 desc[3] = cmd_buffer->state.pipeline->va_rsrc_word3[i];
1311 }
1312
1313 va = device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
1314 va += vb_offset;
1315
1316 radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
1317 AC_UD_VS_VERTEX_BUFFERS, va);
1318 }
1319
1320 cmd_buffer->state.vertex_descriptors_dirty = false;
1321 cmd_buffer->state.vb_dirty = 0;
1322 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
1323 radv_emit_graphics_pipeline(cmd_buffer, pipeline);
1324
1325 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
1326 radv_emit_framebuffer_state(cmd_buffer);
1327
1328 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1329 radv_emit_viewport(cmd_buffer);
1330
1331 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1332 radv_emit_scissor(cmd_buffer);
1333
1334 ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
1335 if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
1336 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
1337 radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1338 else
1339 radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1340 cmd_buffer->state.last_ia_multi_vgt_param = ia_multi_vgt_param;
1341 }
1342
1343 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) {
1344 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1345
1346 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1347 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
1348 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, cmd_buffer->state.pipeline->graphics.prim);
1349 } else {
1350 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, cmd_buffer->state.pipeline->graphics.prim);
1351 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
1352 }
1353 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, cmd_buffer->state.pipeline->graphics.gs_out);
1354 }
1355
1356 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
1357
1358 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
1359 VK_SHADER_STAGE_ALL_GRAPHICS);
1360 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1361 VK_SHADER_STAGE_ALL_GRAPHICS);
1362
1363 assert(cmd_buffer->cs->cdw <= cdw_max);
1364
1365 si_emit_cache_flush(cmd_buffer);
1366 }
1367
1368 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1369 VkPipelineStageFlags src_stage_mask)
1370 {
1371 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1372 VK_PIPELINE_STAGE_TRANSFER_BIT |
1373 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1374 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1375 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1376 }
1377
1378 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1379 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1380 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1381 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1382 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1383 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1384 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1385 VK_PIPELINE_STAGE_TRANSFER_BIT |
1386 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1387 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1388 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1389 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1390 } else if (src_stage_mask & (VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
1391 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1392 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1393 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1394 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1395 }
1396 }
1397
1398 static enum radv_cmd_flush_bits
1399 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1400 VkAccessFlags src_flags)
1401 {
1402 enum radv_cmd_flush_bits flush_bits = 0;
1403 uint32_t b;
1404 for_each_bit(b, src_flags) {
1405 switch ((VkAccessFlagBits)(1 << b)) {
1406 case VK_ACCESS_SHADER_WRITE_BIT:
1407 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1408 break;
1409 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1410 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1411 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1412 break;
1413 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1414 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1415 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1416 break;
1417 case VK_ACCESS_TRANSFER_WRITE_BIT:
1418 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1419 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1420 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1421 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1422 RADV_CMD_FLAG_INV_GLOBAL_L2;
1423 break;
1424 default:
1425 break;
1426 }
1427 }
1428 return flush_bits;
1429 }
1430
1431 static enum radv_cmd_flush_bits
1432 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1433 VkAccessFlags dst_flags,
1434 struct radv_image *image)
1435 {
1436 enum radv_cmd_flush_bits flush_bits = 0;
1437 uint32_t b;
1438 for_each_bit(b, dst_flags) {
1439 switch ((VkAccessFlagBits)(1 << b)) {
1440 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1441 case VK_ACCESS_INDEX_READ_BIT:
1442 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1443 break;
1444 case VK_ACCESS_UNIFORM_READ_BIT:
1445 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1446 break;
1447 case VK_ACCESS_SHADER_READ_BIT:
1448 case VK_ACCESS_TRANSFER_READ_BIT:
1449 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1450 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1451 RADV_CMD_FLAG_INV_GLOBAL_L2;
1452 break;
1453 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1454 /* TODO: change to image && when the image gets passed
1455 * through from the subpass. */
1456 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1457 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1458 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1459 break;
1460 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1461 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1462 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1463 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1464 break;
1465 default:
1466 break;
1467 }
1468 }
1469 return flush_bits;
1470 }
1471
1472 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1473 {
1474 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1475 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1476 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1477 NULL);
1478 }
1479
1480 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1481 VkAttachmentReference att)
1482 {
1483 unsigned idx = att.attachment;
1484 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1485 VkImageSubresourceRange range;
1486 range.aspectMask = 0;
1487 range.baseMipLevel = view->base_mip;
1488 range.levelCount = 1;
1489 range.baseArrayLayer = view->base_layer;
1490 range.layerCount = cmd_buffer->state.framebuffer->layers;
1491
1492 radv_handle_image_transition(cmd_buffer,
1493 view->image,
1494 cmd_buffer->state.attachments[idx].current_layout,
1495 att.layout, 0, 0, &range,
1496 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1497
1498 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1499
1500
1501 }
1502
1503 void
1504 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1505 const struct radv_subpass *subpass, bool transitions)
1506 {
1507 if (transitions) {
1508 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1509
1510 for (unsigned i = 0; i < subpass->color_count; ++i) {
1511 radv_handle_subpass_image_transition(cmd_buffer,
1512 subpass->color_attachments[i]);
1513 }
1514
1515 for (unsigned i = 0; i < subpass->input_count; ++i) {
1516 radv_handle_subpass_image_transition(cmd_buffer,
1517 subpass->input_attachments[i]);
1518 }
1519
1520 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1521 radv_handle_subpass_image_transition(cmd_buffer,
1522 subpass->depth_stencil_attachment);
1523 }
1524 }
1525
1526 cmd_buffer->state.subpass = subpass;
1527
1528 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RENDER_TARGETS;
1529 }
1530
1531 static void
1532 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1533 struct radv_render_pass *pass,
1534 const VkRenderPassBeginInfo *info)
1535 {
1536 struct radv_cmd_state *state = &cmd_buffer->state;
1537
1538 if (pass->attachment_count == 0) {
1539 state->attachments = NULL;
1540 return;
1541 }
1542
1543 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1544 pass->attachment_count *
1545 sizeof(state->attachments[0]),
1546 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1547 if (state->attachments == NULL) {
1548 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1549 abort();
1550 }
1551
1552 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1553 struct radv_render_pass_attachment *att = &pass->attachments[i];
1554 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1555 VkImageAspectFlags clear_aspects = 0;
1556
1557 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1558 /* color attachment */
1559 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1560 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1561 }
1562 } else {
1563 /* depthstencil attachment */
1564 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1565 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1566 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1567 }
1568 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1569 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1570 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1571 }
1572 }
1573
1574 state->attachments[i].pending_clear_aspects = clear_aspects;
1575 if (clear_aspects && info) {
1576 assert(info->clearValueCount > i);
1577 state->attachments[i].clear_value = info->pClearValues[i];
1578 }
1579
1580 state->attachments[i].current_layout = att->initial_layout;
1581 }
1582 }
1583
1584 VkResult radv_AllocateCommandBuffers(
1585 VkDevice _device,
1586 const VkCommandBufferAllocateInfo *pAllocateInfo,
1587 VkCommandBuffer *pCommandBuffers)
1588 {
1589 RADV_FROM_HANDLE(radv_device, device, _device);
1590 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1591
1592 VkResult result = VK_SUCCESS;
1593 uint32_t i;
1594
1595 memset(pCommandBuffers, 0,
1596 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
1597
1598 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1599
1600 if (!list_empty(&pool->free_cmd_buffers)) {
1601 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1602
1603 list_del(&cmd_buffer->pool_link);
1604 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1605
1606 radv_reset_cmd_buffer(cmd_buffer);
1607 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1608 cmd_buffer->level = pAllocateInfo->level;
1609
1610 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1611 result = VK_SUCCESS;
1612 } else {
1613 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1614 &pCommandBuffers[i]);
1615 }
1616 if (result != VK_SUCCESS)
1617 break;
1618 }
1619
1620 if (result != VK_SUCCESS)
1621 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1622 i, pCommandBuffers);
1623
1624 return result;
1625 }
1626
1627 void radv_FreeCommandBuffers(
1628 VkDevice device,
1629 VkCommandPool commandPool,
1630 uint32_t commandBufferCount,
1631 const VkCommandBuffer *pCommandBuffers)
1632 {
1633 for (uint32_t i = 0; i < commandBufferCount; i++) {
1634 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1635
1636 if (cmd_buffer) {
1637 if (cmd_buffer->pool) {
1638 list_del(&cmd_buffer->pool_link);
1639 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1640 } else
1641 radv_cmd_buffer_destroy(cmd_buffer);
1642
1643 }
1644 }
1645 }
1646
1647 VkResult radv_ResetCommandBuffer(
1648 VkCommandBuffer commandBuffer,
1649 VkCommandBufferResetFlags flags)
1650 {
1651 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1652 radv_reset_cmd_buffer(cmd_buffer);
1653 return VK_SUCCESS;
1654 }
1655
1656 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1657 {
1658 struct radv_device *device = cmd_buffer->device;
1659 if (device->gfx_init) {
1660 uint64_t va = device->ws->buffer_get_va(device->gfx_init);
1661 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
1662 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1663 radeon_emit(cmd_buffer->cs, va);
1664 radeon_emit(cmd_buffer->cs, (va >> 32) & 0xffff);
1665 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1666 } else
1667 si_init_config(cmd_buffer);
1668 }
1669
1670 VkResult radv_BeginCommandBuffer(
1671 VkCommandBuffer commandBuffer,
1672 const VkCommandBufferBeginInfo *pBeginInfo)
1673 {
1674 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1675 radv_reset_cmd_buffer(cmd_buffer);
1676
1677 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1678
1679 /* setup initial configuration into command buffer */
1680 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1681 switch (cmd_buffer->queue_family_index) {
1682 case RADV_QUEUE_GENERAL:
1683 emit_gfx_buffer_state(cmd_buffer);
1684 radv_set_db_count_control(cmd_buffer);
1685 break;
1686 case RADV_QUEUE_COMPUTE:
1687 si_init_compute(cmd_buffer);
1688 break;
1689 case RADV_QUEUE_TRANSFER:
1690 default:
1691 break;
1692 }
1693 }
1694
1695 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1696 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1697 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1698
1699 struct radv_subpass *subpass =
1700 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1701
1702 radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1703 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1704 }
1705
1706 return VK_SUCCESS;
1707 }
1708
1709 void radv_CmdBindVertexBuffers(
1710 VkCommandBuffer commandBuffer,
1711 uint32_t firstBinding,
1712 uint32_t bindingCount,
1713 const VkBuffer* pBuffers,
1714 const VkDeviceSize* pOffsets)
1715 {
1716 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1717 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
1718
1719 /* We have to defer setting up vertex buffer since we need the buffer
1720 * stride from the pipeline. */
1721
1722 assert(firstBinding + bindingCount < MAX_VBS);
1723 for (uint32_t i = 0; i < bindingCount; i++) {
1724 vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
1725 vb[firstBinding + i].offset = pOffsets[i];
1726 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
1727 }
1728 }
1729
1730 void radv_CmdBindIndexBuffer(
1731 VkCommandBuffer commandBuffer,
1732 VkBuffer buffer,
1733 VkDeviceSize offset,
1734 VkIndexType indexType)
1735 {
1736 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1737
1738 cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
1739 cmd_buffer->state.index_offset = offset;
1740 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1741 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1742 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
1743 }
1744
1745
1746 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1747 struct radv_descriptor_set *set,
1748 unsigned idx)
1749 {
1750 struct radeon_winsys *ws = cmd_buffer->device->ws;
1751
1752 cmd_buffer->state.descriptors[idx] = set;
1753 cmd_buffer->state.descriptors_dirty |= (1 << idx);
1754 if (!set)
1755 return;
1756
1757 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1758 if (set->descriptors[j])
1759 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
1760
1761 if(set->bo)
1762 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
1763 }
1764
1765 void radv_CmdBindDescriptorSets(
1766 VkCommandBuffer commandBuffer,
1767 VkPipelineBindPoint pipelineBindPoint,
1768 VkPipelineLayout _layout,
1769 uint32_t firstSet,
1770 uint32_t descriptorSetCount,
1771 const VkDescriptorSet* pDescriptorSets,
1772 uint32_t dynamicOffsetCount,
1773 const uint32_t* pDynamicOffsets)
1774 {
1775 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1776 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
1777 unsigned dyn_idx = 0;
1778
1779 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1780 cmd_buffer->cs, MAX_SETS * 4 * 6);
1781
1782 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1783 unsigned idx = i + firstSet;
1784 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
1785 radv_bind_descriptor_set(cmd_buffer, set, idx);
1786
1787 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1788 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1789 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
1790 assert(dyn_idx < dynamicOffsetCount);
1791
1792 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
1793 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
1794 dst[0] = va;
1795 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1796 dst[2] = range->size;
1797 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1798 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1799 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1800 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1801 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1802 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1803 cmd_buffer->push_constant_stages |=
1804 set->layout->dynamic_shader_stages;
1805 }
1806 }
1807
1808 assert(cmd_buffer->cs->cdw <= cdw_max);
1809 }
1810
1811 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
1812 VkPipelineLayout layout,
1813 VkShaderStageFlags stageFlags,
1814 uint32_t offset,
1815 uint32_t size,
1816 const void* pValues)
1817 {
1818 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1819 memcpy(cmd_buffer->push_constants + offset, pValues, size);
1820 cmd_buffer->push_constant_stages |= stageFlags;
1821 }
1822
1823 VkResult radv_EndCommandBuffer(
1824 VkCommandBuffer commandBuffer)
1825 {
1826 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1827
1828 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
1829 si_emit_cache_flush(cmd_buffer);
1830
1831 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
1832 cmd_buffer->record_fail)
1833 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1834 return VK_SUCCESS;
1835 }
1836
1837 static void
1838 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
1839 {
1840 struct radeon_winsys *ws = cmd_buffer->device->ws;
1841 struct radv_shader_variant *compute_shader;
1842 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
1843 uint64_t va;
1844
1845 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
1846 return;
1847
1848 cmd_buffer->state.emitted_compute_pipeline = pipeline;
1849
1850 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
1851 va = ws->buffer_get_va(compute_shader->bo);
1852
1853 ws->cs_add_buffer(cmd_buffer->cs, compute_shader->bo, 8);
1854
1855 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1856 cmd_buffer->cs, 16);
1857
1858 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
1859 radeon_emit(cmd_buffer->cs, va >> 8);
1860 radeon_emit(cmd_buffer->cs, va >> 40);
1861
1862 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1863 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
1864 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
1865
1866
1867 cmd_buffer->compute_scratch_size_needed =
1868 MAX2(cmd_buffer->compute_scratch_size_needed,
1869 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1870
1871 /* change these once we have scratch support */
1872 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
1873 S_00B860_WAVES(pipeline->max_waves) |
1874 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1875
1876 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
1877 radeon_emit(cmd_buffer->cs,
1878 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
1879 radeon_emit(cmd_buffer->cs,
1880 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
1881 radeon_emit(cmd_buffer->cs,
1882 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
1883
1884 assert(cmd_buffer->cs->cdw <= cdw_max);
1885 }
1886
1887
1888 void radv_CmdBindPipeline(
1889 VkCommandBuffer commandBuffer,
1890 VkPipelineBindPoint pipelineBindPoint,
1891 VkPipeline _pipeline)
1892 {
1893 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1894 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1895
1896 for (unsigned i = 0; i < MAX_SETS; i++) {
1897 if (cmd_buffer->state.descriptors[i])
1898 cmd_buffer->state.descriptors_dirty |= (1 << i);
1899 }
1900
1901 switch (pipelineBindPoint) {
1902 case VK_PIPELINE_BIND_POINT_COMPUTE:
1903 cmd_buffer->state.compute_pipeline = pipeline;
1904 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
1905 break;
1906 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1907 cmd_buffer->state.pipeline = pipeline;
1908 cmd_buffer->state.vertex_descriptors_dirty = true;
1909 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
1910 cmd_buffer->push_constant_stages |= pipeline->active_stages;
1911
1912 /* Apply the dynamic state from the pipeline */
1913 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
1914 radv_dynamic_state_copy(&cmd_buffer->state.dynamic,
1915 &pipeline->dynamic_state,
1916 pipeline->dynamic_state_mask);
1917
1918 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
1919 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
1920 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
1921 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
1922
1923 if (radv_pipeline_has_tess(pipeline))
1924 cmd_buffer->tess_rings_needed = true;
1925
1926 if (radv_pipeline_has_gs(pipeline)) {
1927 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1928 AC_UD_SCRATCH_RING_OFFSETS);
1929 if (cmd_buffer->ring_offsets_idx == -1)
1930 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
1931 else if (loc->sgpr_idx != -1)
1932 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
1933 }
1934 break;
1935 default:
1936 assert(!"invalid bind point");
1937 break;
1938 }
1939 }
1940
1941 void radv_CmdSetViewport(
1942 VkCommandBuffer commandBuffer,
1943 uint32_t firstViewport,
1944 uint32_t viewportCount,
1945 const VkViewport* pViewports)
1946 {
1947 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1948
1949 const uint32_t total_count = firstViewport + viewportCount;
1950 if (cmd_buffer->state.dynamic.viewport.count < total_count)
1951 cmd_buffer->state.dynamic.viewport.count = total_count;
1952
1953 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
1954 pViewports, viewportCount * sizeof(*pViewports));
1955
1956 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
1957 }
1958
1959 void radv_CmdSetScissor(
1960 VkCommandBuffer commandBuffer,
1961 uint32_t firstScissor,
1962 uint32_t scissorCount,
1963 const VkRect2D* pScissors)
1964 {
1965 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1966
1967 const uint32_t total_count = firstScissor + scissorCount;
1968 if (cmd_buffer->state.dynamic.scissor.count < total_count)
1969 cmd_buffer->state.dynamic.scissor.count = total_count;
1970
1971 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
1972 pScissors, scissorCount * sizeof(*pScissors));
1973 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1974 }
1975
1976 void radv_CmdSetLineWidth(
1977 VkCommandBuffer commandBuffer,
1978 float lineWidth)
1979 {
1980 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1981 cmd_buffer->state.dynamic.line_width = lineWidth;
1982 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1983 }
1984
1985 void radv_CmdSetDepthBias(
1986 VkCommandBuffer commandBuffer,
1987 float depthBiasConstantFactor,
1988 float depthBiasClamp,
1989 float depthBiasSlopeFactor)
1990 {
1991 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1992
1993 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
1994 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
1995 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
1996
1997 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1998 }
1999
2000 void radv_CmdSetBlendConstants(
2001 VkCommandBuffer commandBuffer,
2002 const float blendConstants[4])
2003 {
2004 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2005
2006 memcpy(cmd_buffer->state.dynamic.blend_constants,
2007 blendConstants, sizeof(float) * 4);
2008
2009 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2010 }
2011
2012 void radv_CmdSetDepthBounds(
2013 VkCommandBuffer commandBuffer,
2014 float minDepthBounds,
2015 float maxDepthBounds)
2016 {
2017 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2018
2019 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2020 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2021
2022 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2023 }
2024
2025 void radv_CmdSetStencilCompareMask(
2026 VkCommandBuffer commandBuffer,
2027 VkStencilFaceFlags faceMask,
2028 uint32_t compareMask)
2029 {
2030 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2031
2032 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2033 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2034 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2035 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2036
2037 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2038 }
2039
2040 void radv_CmdSetStencilWriteMask(
2041 VkCommandBuffer commandBuffer,
2042 VkStencilFaceFlags faceMask,
2043 uint32_t writeMask)
2044 {
2045 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2046
2047 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2048 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2049 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2050 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2051
2052 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2053 }
2054
2055 void radv_CmdSetStencilReference(
2056 VkCommandBuffer commandBuffer,
2057 VkStencilFaceFlags faceMask,
2058 uint32_t reference)
2059 {
2060 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2061
2062 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2063 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2064 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2065 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2066
2067 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2068 }
2069
2070
2071 void radv_CmdExecuteCommands(
2072 VkCommandBuffer commandBuffer,
2073 uint32_t commandBufferCount,
2074 const VkCommandBuffer* pCmdBuffers)
2075 {
2076 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2077
2078 /* Emit pending flushes on primary prior to executing secondary */
2079 si_emit_cache_flush(primary);
2080
2081 for (uint32_t i = 0; i < commandBufferCount; i++) {
2082 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2083
2084 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2085 secondary->scratch_size_needed);
2086 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2087 secondary->compute_scratch_size_needed);
2088
2089 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2090 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2091 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2092 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2093 if (secondary->tess_rings_needed)
2094 primary->tess_rings_needed = true;
2095
2096 if (secondary->ring_offsets_idx != -1) {
2097 if (primary->ring_offsets_idx == -1)
2098 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2099 else
2100 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2101 }
2102 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2103 }
2104
2105 /* if we execute secondary we need to re-emit out pipelines */
2106 if (commandBufferCount) {
2107 primary->state.emitted_pipeline = NULL;
2108 primary->state.emitted_compute_pipeline = NULL;
2109 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2110 primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
2111 }
2112 }
2113
2114 VkResult radv_CreateCommandPool(
2115 VkDevice _device,
2116 const VkCommandPoolCreateInfo* pCreateInfo,
2117 const VkAllocationCallbacks* pAllocator,
2118 VkCommandPool* pCmdPool)
2119 {
2120 RADV_FROM_HANDLE(radv_device, device, _device);
2121 struct radv_cmd_pool *pool;
2122
2123 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2124 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2125 if (pool == NULL)
2126 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2127
2128 if (pAllocator)
2129 pool->alloc = *pAllocator;
2130 else
2131 pool->alloc = device->alloc;
2132
2133 list_inithead(&pool->cmd_buffers);
2134 list_inithead(&pool->free_cmd_buffers);
2135
2136 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2137
2138 *pCmdPool = radv_cmd_pool_to_handle(pool);
2139
2140 return VK_SUCCESS;
2141
2142 }
2143
2144 void radv_DestroyCommandPool(
2145 VkDevice _device,
2146 VkCommandPool commandPool,
2147 const VkAllocationCallbacks* pAllocator)
2148 {
2149 RADV_FROM_HANDLE(radv_device, device, _device);
2150 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2151
2152 if (!pool)
2153 return;
2154
2155 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2156 &pool->cmd_buffers, pool_link) {
2157 radv_cmd_buffer_destroy(cmd_buffer);
2158 }
2159
2160 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2161 &pool->free_cmd_buffers, pool_link) {
2162 radv_cmd_buffer_destroy(cmd_buffer);
2163 }
2164
2165 vk_free2(&device->alloc, pAllocator, pool);
2166 }
2167
2168 VkResult radv_ResetCommandPool(
2169 VkDevice device,
2170 VkCommandPool commandPool,
2171 VkCommandPoolResetFlags flags)
2172 {
2173 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2174
2175 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2176 &pool->cmd_buffers, pool_link) {
2177 radv_reset_cmd_buffer(cmd_buffer);
2178 }
2179
2180 return VK_SUCCESS;
2181 }
2182
2183 void radv_TrimCommandPoolKHR(
2184 VkDevice device,
2185 VkCommandPool commandPool,
2186 VkCommandPoolTrimFlagsKHR flags)
2187 {
2188 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2189
2190 if (!pool)
2191 return;
2192
2193 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2194 &pool->free_cmd_buffers, pool_link) {
2195 radv_cmd_buffer_destroy(cmd_buffer);
2196 }
2197 }
2198
2199 void radv_CmdBeginRenderPass(
2200 VkCommandBuffer commandBuffer,
2201 const VkRenderPassBeginInfo* pRenderPassBegin,
2202 VkSubpassContents contents)
2203 {
2204 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2205 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2206 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2207
2208 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2209 cmd_buffer->cs, 2048);
2210
2211 cmd_buffer->state.framebuffer = framebuffer;
2212 cmd_buffer->state.pass = pass;
2213 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2214 radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2215
2216 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2217 assert(cmd_buffer->cs->cdw <= cdw_max);
2218
2219 radv_cmd_buffer_clear_subpass(cmd_buffer);
2220 }
2221
2222 void radv_CmdNextSubpass(
2223 VkCommandBuffer commandBuffer,
2224 VkSubpassContents contents)
2225 {
2226 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2227
2228 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2229
2230 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2231 2048);
2232
2233 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2234 radv_cmd_buffer_clear_subpass(cmd_buffer);
2235 }
2236
2237 void radv_CmdDraw(
2238 VkCommandBuffer commandBuffer,
2239 uint32_t vertexCount,
2240 uint32_t instanceCount,
2241 uint32_t firstVertex,
2242 uint32_t firstInstance)
2243 {
2244 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2245
2246 radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, vertexCount);
2247
2248 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2249
2250 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2251 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2252 if (loc->sgpr_idx != -1) {
2253 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2254 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2255 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2256 radeon_emit(cmd_buffer->cs, firstVertex);
2257 radeon_emit(cmd_buffer->cs, firstInstance);
2258 radeon_emit(cmd_buffer->cs, 0);
2259 }
2260 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2261 radeon_emit(cmd_buffer->cs, instanceCount);
2262
2263 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
2264 radeon_emit(cmd_buffer->cs, vertexCount);
2265 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2266 S_0287F0_USE_OPAQUE(0));
2267
2268 assert(cmd_buffer->cs->cdw <= cdw_max);
2269
2270 radv_cmd_buffer_trace_emit(cmd_buffer);
2271 }
2272
2273 static void radv_emit_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)
2274 {
2275 uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
2276
2277 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
2278 primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
2279 cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
2280 radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2281 primitive_reset_index);
2282 }
2283 }
2284
2285 void radv_CmdDrawIndexed(
2286 VkCommandBuffer commandBuffer,
2287 uint32_t indexCount,
2288 uint32_t instanceCount,
2289 uint32_t firstIndex,
2290 int32_t vertexOffset,
2291 uint32_t firstInstance)
2292 {
2293 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2294 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2295 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2296 uint64_t index_va;
2297
2298 radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, indexCount);
2299 radv_emit_primitive_reset_index(cmd_buffer);
2300
2301 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2302
2303 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2304 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2305
2306 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2307 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2308 if (loc->sgpr_idx != -1) {
2309 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2310 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2311 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 3);
2312 radeon_emit(cmd_buffer->cs, vertexOffset);
2313 radeon_emit(cmd_buffer->cs, firstInstance);
2314 radeon_emit(cmd_buffer->cs, 0);
2315 }
2316 radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2317 radeon_emit(cmd_buffer->cs, instanceCount);
2318
2319 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2320 index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2321 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2322 radeon_emit(cmd_buffer->cs, index_max_size);
2323 radeon_emit(cmd_buffer->cs, index_va);
2324 radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
2325 radeon_emit(cmd_buffer->cs, indexCount);
2326 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2327
2328 assert(cmd_buffer->cs->cdw <= cdw_max);
2329 radv_cmd_buffer_trace_emit(cmd_buffer);
2330 }
2331
2332 static void
2333 radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
2334 VkBuffer _buffer,
2335 VkDeviceSize offset,
2336 VkBuffer _count_buffer,
2337 VkDeviceSize count_offset,
2338 uint32_t draw_count,
2339 uint32_t stride,
2340 bool indexed)
2341 {
2342 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2343 RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
2344 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2345 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2346 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2347 uint64_t indirect_va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2348 indirect_va += offset + buffer->offset;
2349 uint64_t count_va = 0;
2350
2351 if (count_buffer) {
2352 count_va = cmd_buffer->device->ws->buffer_get_va(count_buffer->bo);
2353 count_va += count_offset + count_buffer->offset;
2354 }
2355
2356 if (!draw_count)
2357 return;
2358
2359 cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
2360
2361 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2362 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2363 uint32_t base_reg = shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
2364 radv_pipeline_has_tess(cmd_buffer->state.pipeline));
2365 assert(loc->sgpr_idx != -1);
2366 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2367 radeon_emit(cs, 1);
2368 radeon_emit(cs, indirect_va);
2369 radeon_emit(cs, indirect_va >> 32);
2370
2371 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2372 PKT3_DRAW_INDIRECT_MULTI,
2373 8, false));
2374 radeon_emit(cs, 0);
2375 radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
2376 radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
2377 radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
2378 S_2C3_DRAW_INDEX_ENABLE(1) |
2379 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2380 radeon_emit(cs, draw_count); /* count */
2381 radeon_emit(cs, count_va); /* count_addr */
2382 radeon_emit(cs, count_va >> 32);
2383 radeon_emit(cs, stride); /* stride */
2384 radeon_emit(cs, di_src_sel);
2385 radv_cmd_buffer_trace_emit(cmd_buffer);
2386 }
2387
2388 static void
2389 radv_cmd_draw_indirect_count(VkCommandBuffer commandBuffer,
2390 VkBuffer buffer,
2391 VkDeviceSize offset,
2392 VkBuffer countBuffer,
2393 VkDeviceSize countBufferOffset,
2394 uint32_t maxDrawCount,
2395 uint32_t stride)
2396 {
2397 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2398 radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0);
2399
2400 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2401 cmd_buffer->cs, 14);
2402
2403 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2404 countBuffer, countBufferOffset, maxDrawCount, stride, false);
2405
2406 assert(cmd_buffer->cs->cdw <= cdw_max);
2407 }
2408
2409 static void
2410 radv_cmd_draw_indexed_indirect_count(
2411 VkCommandBuffer commandBuffer,
2412 VkBuffer buffer,
2413 VkDeviceSize offset,
2414 VkBuffer countBuffer,
2415 VkDeviceSize countBufferOffset,
2416 uint32_t maxDrawCount,
2417 uint32_t stride)
2418 {
2419 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2420 int index_size = cmd_buffer->state.index_type ? 4 : 2;
2421 uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size;
2422 uint64_t index_va;
2423 radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0);
2424 radv_emit_primitive_reset_index(cmd_buffer);
2425
2426 index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
2427 index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
2428
2429 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
2430
2431 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2432 radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
2433
2434 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
2435 radeon_emit(cmd_buffer->cs, index_va);
2436 radeon_emit(cmd_buffer->cs, index_va >> 32);
2437
2438 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
2439 radeon_emit(cmd_buffer->cs, index_max_size);
2440
2441 radv_emit_indirect_draw(cmd_buffer, buffer, offset,
2442 countBuffer, countBufferOffset, maxDrawCount, stride, true);
2443
2444 assert(cmd_buffer->cs->cdw <= cdw_max);
2445 }
2446
2447 void radv_CmdDrawIndirect(
2448 VkCommandBuffer commandBuffer,
2449 VkBuffer buffer,
2450 VkDeviceSize offset,
2451 uint32_t drawCount,
2452 uint32_t stride)
2453 {
2454 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2455 VK_NULL_HANDLE, 0, drawCount, stride);
2456 }
2457
2458 void radv_CmdDrawIndexedIndirect(
2459 VkCommandBuffer commandBuffer,
2460 VkBuffer buffer,
2461 VkDeviceSize offset,
2462 uint32_t drawCount,
2463 uint32_t stride)
2464 {
2465 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2466 VK_NULL_HANDLE, 0, drawCount, stride);
2467 }
2468
2469 void radv_CmdDrawIndirectCountAMD(
2470 VkCommandBuffer commandBuffer,
2471 VkBuffer buffer,
2472 VkDeviceSize offset,
2473 VkBuffer countBuffer,
2474 VkDeviceSize countBufferOffset,
2475 uint32_t maxDrawCount,
2476 uint32_t stride)
2477 {
2478 radv_cmd_draw_indirect_count(commandBuffer, buffer, offset,
2479 countBuffer, countBufferOffset,
2480 maxDrawCount, stride);
2481 }
2482
2483 void radv_CmdDrawIndexedIndirectCountAMD(
2484 VkCommandBuffer commandBuffer,
2485 VkBuffer buffer,
2486 VkDeviceSize offset,
2487 VkBuffer countBuffer,
2488 VkDeviceSize countBufferOffset,
2489 uint32_t maxDrawCount,
2490 uint32_t stride)
2491 {
2492 radv_cmd_draw_indexed_indirect_count(commandBuffer, buffer, offset,
2493 countBuffer, countBufferOffset,
2494 maxDrawCount, stride);
2495 }
2496
2497 static void
2498 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
2499 {
2500 radv_emit_compute_pipeline(cmd_buffer);
2501 radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
2502 VK_SHADER_STAGE_COMPUTE_BIT);
2503 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
2504 VK_SHADER_STAGE_COMPUTE_BIT);
2505 si_emit_cache_flush(cmd_buffer);
2506 }
2507
2508 void radv_CmdDispatch(
2509 VkCommandBuffer commandBuffer,
2510 uint32_t x,
2511 uint32_t y,
2512 uint32_t z)
2513 {
2514 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2515
2516 radv_flush_compute_state(cmd_buffer);
2517
2518 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
2519
2520 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2521 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2522 if (loc->sgpr_idx != -1) {
2523 assert(!loc->indirect);
2524 assert(loc->num_sgprs == 3);
2525 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2526 radeon_emit(cmd_buffer->cs, x);
2527 radeon_emit(cmd_buffer->cs, y);
2528 radeon_emit(cmd_buffer->cs, z);
2529 }
2530
2531 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2532 PKT3_SHADER_TYPE_S(1));
2533 radeon_emit(cmd_buffer->cs, x);
2534 radeon_emit(cmd_buffer->cs, y);
2535 radeon_emit(cmd_buffer->cs, z);
2536 radeon_emit(cmd_buffer->cs, 1);
2537
2538 assert(cmd_buffer->cs->cdw <= cdw_max);
2539 radv_cmd_buffer_trace_emit(cmd_buffer);
2540 }
2541
2542 void radv_CmdDispatchIndirect(
2543 VkCommandBuffer commandBuffer,
2544 VkBuffer _buffer,
2545 VkDeviceSize offset)
2546 {
2547 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2548 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2549 uint64_t va = cmd_buffer->device->ws->buffer_get_va(buffer->bo);
2550 va += buffer->offset + offset;
2551
2552 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
2553
2554 radv_flush_compute_state(cmd_buffer);
2555
2556 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
2557 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2558 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2559 if (loc->sgpr_idx != -1) {
2560 for (unsigned i = 0; i < 3; ++i) {
2561 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
2562 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
2563 COPY_DATA_DST_SEL(COPY_DATA_REG));
2564 radeon_emit(cmd_buffer->cs, (va + 4 * i));
2565 radeon_emit(cmd_buffer->cs, (va + 4 * i) >> 32);
2566 radeon_emit(cmd_buffer->cs, ((R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4) >> 2) + i);
2567 radeon_emit(cmd_buffer->cs, 0);
2568 }
2569 }
2570
2571 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
2572 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
2573 PKT3_SHADER_TYPE_S(1));
2574 radeon_emit(cmd_buffer->cs, va);
2575 radeon_emit(cmd_buffer->cs, va >> 32);
2576 radeon_emit(cmd_buffer->cs, 1);
2577 } else {
2578 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_BASE, 2, 0) |
2579 PKT3_SHADER_TYPE_S(1));
2580 radeon_emit(cmd_buffer->cs, 1);
2581 radeon_emit(cmd_buffer->cs, va);
2582 radeon_emit(cmd_buffer->cs, va >> 32);
2583
2584 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
2585 PKT3_SHADER_TYPE_S(1));
2586 radeon_emit(cmd_buffer->cs, 0);
2587 radeon_emit(cmd_buffer->cs, 1);
2588 }
2589
2590 assert(cmd_buffer->cs->cdw <= cdw_max);
2591 radv_cmd_buffer_trace_emit(cmd_buffer);
2592 }
2593
2594 void radv_unaligned_dispatch(
2595 struct radv_cmd_buffer *cmd_buffer,
2596 uint32_t x,
2597 uint32_t y,
2598 uint32_t z)
2599 {
2600 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2601 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2602 uint32_t blocks[3], remainder[3];
2603
2604 blocks[0] = round_up_u32(x, compute_shader->info.cs.block_size[0]);
2605 blocks[1] = round_up_u32(y, compute_shader->info.cs.block_size[1]);
2606 blocks[2] = round_up_u32(z, compute_shader->info.cs.block_size[2]);
2607
2608 /* If aligned, these should be an entire block size, not 0 */
2609 remainder[0] = x + compute_shader->info.cs.block_size[0] - align_u32_npot(x, compute_shader->info.cs.block_size[0]);
2610 remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
2611 remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
2612
2613 radv_flush_compute_state(cmd_buffer);
2614
2615 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
2616
2617 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2618 radeon_emit(cmd_buffer->cs,
2619 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]) |
2620 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
2621 radeon_emit(cmd_buffer->cs,
2622 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]) |
2623 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
2624 radeon_emit(cmd_buffer->cs,
2625 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]) |
2626 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
2627
2628 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline,
2629 MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
2630 if (loc->sgpr_idx != -1) {
2631 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
2632 radeon_emit(cmd_buffer->cs, blocks[0]);
2633 radeon_emit(cmd_buffer->cs, blocks[1]);
2634 radeon_emit(cmd_buffer->cs, blocks[2]);
2635 }
2636 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
2637 PKT3_SHADER_TYPE_S(1));
2638 radeon_emit(cmd_buffer->cs, blocks[0]);
2639 radeon_emit(cmd_buffer->cs, blocks[1]);
2640 radeon_emit(cmd_buffer->cs, blocks[2]);
2641 radeon_emit(cmd_buffer->cs, S_00B800_COMPUTE_SHADER_EN(1) |
2642 S_00B800_PARTIAL_TG_EN(1));
2643
2644 assert(cmd_buffer->cs->cdw <= cdw_max);
2645 radv_cmd_buffer_trace_emit(cmd_buffer);
2646 }
2647
2648 void radv_CmdEndRenderPass(
2649 VkCommandBuffer commandBuffer)
2650 {
2651 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2652
2653 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
2654
2655 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2656
2657 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
2658 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
2659 radv_handle_subpass_image_transition(cmd_buffer,
2660 (VkAttachmentReference){i, layout});
2661 }
2662
2663 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2664
2665 cmd_buffer->state.pass = NULL;
2666 cmd_buffer->state.subpass = NULL;
2667 cmd_buffer->state.attachments = NULL;
2668 cmd_buffer->state.framebuffer = NULL;
2669 }
2670
2671
2672 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
2673 struct radv_image *image,
2674 const VkImageSubresourceRange *range)
2675 {
2676 assert(range->baseMipLevel == 0);
2677 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
2678 unsigned layer_count = radv_get_layerCount(image, range);
2679 uint64_t size = image->surface.htile_slice_size * layer_count;
2680 uint64_t offset = image->offset + image->htile_offset +
2681 image->surface.htile_slice_size * range->baseArrayLayer;
2682
2683 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2684 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2685
2686 radv_fill_buffer(cmd_buffer, image->bo, offset, size, 0xffffffff);
2687
2688 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2689 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2690 RADV_CMD_FLAG_INV_VMEM_L1 |
2691 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2692 }
2693
2694 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
2695 struct radv_image *image,
2696 VkImageLayout src_layout,
2697 VkImageLayout dst_layout,
2698 const VkImageSubresourceRange *range,
2699 VkImageAspectFlags pending_clears)
2700 {
2701 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
2702 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
2703 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
2704 cmd_buffer->state.render_area.extent.width == image->extent.width &&
2705 cmd_buffer->state.render_area.extent.height == image->extent.height) {
2706 /* The clear will initialize htile. */
2707 return;
2708 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
2709 radv_layout_has_htile(image, dst_layout)) {
2710 /* TODO: merge with the clear if applicable */
2711 radv_initialize_htile(cmd_buffer, image, range);
2712 } else if (!radv_layout_has_htile(image, src_layout) &&
2713 radv_layout_has_htile(image, dst_layout)) {
2714 radv_initialize_htile(cmd_buffer, image, range);
2715 } else if ((radv_layout_has_htile(image, src_layout) &&
2716 !radv_layout_has_htile(image, dst_layout)) ||
2717 (radv_layout_is_htile_compressed(image, src_layout) &&
2718 !radv_layout_is_htile_compressed(image, dst_layout))) {
2719 VkImageSubresourceRange local_range = *range;
2720 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
2721 local_range.baseMipLevel = 0;
2722 local_range.levelCount = 1;
2723
2724 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2725 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2726
2727 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
2728
2729 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2730 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2731 }
2732 }
2733
2734 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
2735 struct radv_image *image, uint32_t value)
2736 {
2737 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2738 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2739
2740 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset,
2741 image->cmask.size, value);
2742
2743 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2744 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2745 RADV_CMD_FLAG_INV_VMEM_L1 |
2746 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2747 }
2748
2749 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
2750 struct radv_image *image,
2751 VkImageLayout src_layout,
2752 VkImageLayout dst_layout,
2753 unsigned src_queue_mask,
2754 unsigned dst_queue_mask,
2755 const VkImageSubresourceRange *range,
2756 VkImageAspectFlags pending_clears)
2757 {
2758 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2759 if (image->fmask.size)
2760 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
2761 else
2762 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
2763 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2764 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2765 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
2766 }
2767 }
2768
2769 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2770 struct radv_image *image, uint32_t value)
2771 {
2772
2773 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2774 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2775
2776 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset,
2777 image->surface.dcc_size, value);
2778
2779 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2780 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2781 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
2782 RADV_CMD_FLAG_INV_VMEM_L1 |
2783 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2784 }
2785
2786 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
2787 struct radv_image *image,
2788 VkImageLayout src_layout,
2789 VkImageLayout dst_layout,
2790 unsigned src_queue_mask,
2791 unsigned dst_queue_mask,
2792 const VkImageSubresourceRange *range,
2793 VkImageAspectFlags pending_clears)
2794 {
2795 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
2796 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
2797 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
2798 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
2799 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
2800 }
2801 }
2802
2803 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
2804 struct radv_image *image,
2805 VkImageLayout src_layout,
2806 VkImageLayout dst_layout,
2807 uint32_t src_family,
2808 uint32_t dst_family,
2809 const VkImageSubresourceRange *range,
2810 VkImageAspectFlags pending_clears)
2811 {
2812 if (image->exclusive && src_family != dst_family) {
2813 /* This is an acquire or a release operation and there will be
2814 * a corresponding release/acquire. Do the transition in the
2815 * most flexible queue. */
2816
2817 assert(src_family == cmd_buffer->queue_family_index ||
2818 dst_family == cmd_buffer->queue_family_index);
2819
2820 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
2821 return;
2822
2823 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
2824 (src_family == RADV_QUEUE_GENERAL ||
2825 dst_family == RADV_QUEUE_GENERAL))
2826 return;
2827 }
2828
2829 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
2830 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
2831
2832 if (image->surface.htile_size)
2833 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
2834 dst_layout, range, pending_clears);
2835
2836 if (image->cmask.size)
2837 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
2838 dst_layout, src_queue_mask,
2839 dst_queue_mask, range,
2840 pending_clears);
2841
2842 if (image->surface.dcc_size)
2843 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
2844 dst_layout, src_queue_mask,
2845 dst_queue_mask, range,
2846 pending_clears);
2847 }
2848
2849 void radv_CmdPipelineBarrier(
2850 VkCommandBuffer commandBuffer,
2851 VkPipelineStageFlags srcStageMask,
2852 VkPipelineStageFlags destStageMask,
2853 VkBool32 byRegion,
2854 uint32_t memoryBarrierCount,
2855 const VkMemoryBarrier* pMemoryBarriers,
2856 uint32_t bufferMemoryBarrierCount,
2857 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2858 uint32_t imageMemoryBarrierCount,
2859 const VkImageMemoryBarrier* pImageMemoryBarriers)
2860 {
2861 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2862 enum radv_cmd_flush_bits src_flush_bits = 0;
2863 enum radv_cmd_flush_bits dst_flush_bits = 0;
2864
2865 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2866 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
2867 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
2868 NULL);
2869 }
2870
2871 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2872 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
2873 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
2874 NULL);
2875 }
2876
2877 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2878 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2879 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
2880 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
2881 image);
2882 }
2883
2884 radv_stage_flush(cmd_buffer, srcStageMask);
2885 cmd_buffer->state.flush_bits |= src_flush_bits;
2886
2887 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2888 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2889 radv_handle_image_transition(cmd_buffer, image,
2890 pImageMemoryBarriers[i].oldLayout,
2891 pImageMemoryBarriers[i].newLayout,
2892 pImageMemoryBarriers[i].srcQueueFamilyIndex,
2893 pImageMemoryBarriers[i].dstQueueFamilyIndex,
2894 &pImageMemoryBarriers[i].subresourceRange,
2895 0);
2896 }
2897
2898 cmd_buffer->state.flush_bits |= dst_flush_bits;
2899 }
2900
2901
2902 static void write_event(struct radv_cmd_buffer *cmd_buffer,
2903 struct radv_event *event,
2904 VkPipelineStageFlags stageMask,
2905 unsigned value)
2906 {
2907 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2908 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2909
2910 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2911
2912 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
2913
2914 /* TODO: this is overkill. Probably should figure something out from
2915 * the stage mask. */
2916
2917 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK) {
2918 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2919 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2920 EVENT_INDEX(5));
2921 radeon_emit(cs, va);
2922 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2923 radeon_emit(cs, 2);
2924 radeon_emit(cs, 0);
2925 }
2926
2927 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
2928 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
2929 EVENT_INDEX(5));
2930 radeon_emit(cs, va);
2931 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
2932 radeon_emit(cs, value);
2933 radeon_emit(cs, 0);
2934
2935 assert(cmd_buffer->cs->cdw <= cdw_max);
2936 }
2937
2938 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
2939 VkEvent _event,
2940 VkPipelineStageFlags stageMask)
2941 {
2942 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2943 RADV_FROM_HANDLE(radv_event, event, _event);
2944
2945 write_event(cmd_buffer, event, stageMask, 1);
2946 }
2947
2948 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
2949 VkEvent _event,
2950 VkPipelineStageFlags stageMask)
2951 {
2952 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2953 RADV_FROM_HANDLE(radv_event, event, _event);
2954
2955 write_event(cmd_buffer, event, stageMask, 0);
2956 }
2957
2958 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
2959 uint32_t eventCount,
2960 const VkEvent* pEvents,
2961 VkPipelineStageFlags srcStageMask,
2962 VkPipelineStageFlags dstStageMask,
2963 uint32_t memoryBarrierCount,
2964 const VkMemoryBarrier* pMemoryBarriers,
2965 uint32_t bufferMemoryBarrierCount,
2966 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2967 uint32_t imageMemoryBarrierCount,
2968 const VkImageMemoryBarrier* pImageMemoryBarriers)
2969 {
2970 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2971 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2972
2973 for (unsigned i = 0; i < eventCount; ++i) {
2974 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
2975 uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
2976
2977 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
2978
2979 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
2980
2981 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
2982 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
2983 radeon_emit(cs, va);
2984 radeon_emit(cs, va >> 32);
2985 radeon_emit(cs, 1); /* reference value */
2986 radeon_emit(cs, 0xffffffff); /* mask */
2987 radeon_emit(cs, 4); /* poll interval */
2988
2989 assert(cmd_buffer->cs->cdw <= cdw_max);
2990 }
2991
2992
2993 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2994 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
2995
2996 radv_handle_image_transition(cmd_buffer, image,
2997 pImageMemoryBarriers[i].oldLayout,
2998 pImageMemoryBarriers[i].newLayout,
2999 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3000 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3001 &pImageMemoryBarriers[i].subresourceRange,
3002 0);
3003 }
3004
3005 /* TODO: figure out how to do memory barriers without waiting */
3006 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3007 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3008 RADV_CMD_FLAG_INV_VMEM_L1 |
3009 RADV_CMD_FLAG_INV_SMEM_L1;
3010 }