2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
40 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
41 struct radv_image
*image
,
42 VkImageLayout src_layout
,
43 VkImageLayout dst_layout
,
46 const VkImageSubresourceRange
*range
,
47 VkImageAspectFlags pending_clears
);
49 const struct radv_dynamic_state default_dynamic_state
= {
62 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
67 .stencil_compare_mask
= {
71 .stencil_write_mask
= {
75 .stencil_reference
= {
82 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
83 const struct radv_dynamic_state
*src
)
85 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
86 uint32_t copy_mask
= src
->mask
;
87 uint32_t dest_mask
= 0;
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
92 dest
->viewport
.count
= src
->viewport
.count
;
93 dest
->scissor
.count
= src
->scissor
.count
;
95 if (copy_mask
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
96 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
97 src
->viewport
.count
* sizeof(VkViewport
))) {
98 typed_memcpy(dest
->viewport
.viewports
,
99 src
->viewport
.viewports
,
100 src
->viewport
.count
);
101 dest_mask
|= 1 << VK_DYNAMIC_STATE_VIEWPORT
;
105 if (copy_mask
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
106 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
107 src
->scissor
.count
* sizeof(VkRect2D
))) {
108 typed_memcpy(dest
->scissor
.scissors
,
109 src
->scissor
.scissors
, src
->scissor
.count
);
110 dest_mask
|= 1 << VK_DYNAMIC_STATE_SCISSOR
;
114 if (copy_mask
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
115 if (dest
->line_width
!= src
->line_width
) {
116 dest
->line_width
= src
->line_width
;
117 dest_mask
|= 1 << VK_DYNAMIC_STATE_LINE_WIDTH
;
121 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
122 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
123 sizeof(src
->depth_bias
))) {
124 dest
->depth_bias
= src
->depth_bias
;
125 dest_mask
|= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS
;
129 if (copy_mask
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
)) {
130 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
131 sizeof(src
->blend_constants
))) {
132 typed_memcpy(dest
->blend_constants
,
133 src
->blend_constants
, 4);
134 dest_mask
|= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
;
138 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
139 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
140 sizeof(src
->depth_bounds
))) {
141 dest
->depth_bounds
= src
->depth_bounds
;
142 dest_mask
|= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
;
146 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
147 if (memcmp(&dest
->stencil_compare_mask
,
148 &src
->stencil_compare_mask
,
149 sizeof(src
->stencil_compare_mask
))) {
150 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
151 dest_mask
|= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
;
155 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
156 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
157 sizeof(src
->stencil_write_mask
))) {
158 dest
->stencil_write_mask
= src
->stencil_write_mask
;
159 dest_mask
|= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
;
163 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
164 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
165 sizeof(src
->stencil_reference
))) {
166 dest
->stencil_reference
= src
->stencil_reference
;
167 dest_mask
|= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
;
171 cmd_buffer
->state
.dirty
|= dest_mask
;
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
176 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
177 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
;
180 enum ring_type
radv_queue_family_to_ring(int f
) {
182 case RADV_QUEUE_GENERAL
:
184 case RADV_QUEUE_COMPUTE
:
186 case RADV_QUEUE_TRANSFER
:
189 unreachable("Unknown queue family");
193 static VkResult
radv_create_cmd_buffer(
194 struct radv_device
* device
,
195 struct radv_cmd_pool
* pool
,
196 VkCommandBufferLevel level
,
197 VkCommandBuffer
* pCommandBuffer
)
199 struct radv_cmd_buffer
*cmd_buffer
;
201 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
203 if (cmd_buffer
== NULL
)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
206 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
207 cmd_buffer
->device
= device
;
208 cmd_buffer
->pool
= pool
;
209 cmd_buffer
->level
= level
;
212 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
213 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
216 /* Init the pool_link so we can safefly call list_del when we destroy
219 list_inithead(&cmd_buffer
->pool_link
);
220 cmd_buffer
->queue_family_index
= RADV_QUEUE_GENERAL
;
223 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
225 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
226 if (!cmd_buffer
->cs
) {
227 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
228 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
231 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
233 list_inithead(&cmd_buffer
->upload
.list
);
239 radv_cmd_buffer_destroy(struct radv_cmd_buffer
*cmd_buffer
)
241 list_del(&cmd_buffer
->pool_link
);
243 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
244 &cmd_buffer
->upload
.list
, list
) {
245 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
250 if (cmd_buffer
->upload
.upload_bo
)
251 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
252 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
253 free(cmd_buffer
->push_descriptors
.set
.mapped_ptr
);
254 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
258 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
261 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
263 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
264 &cmd_buffer
->upload
.list
, list
) {
265 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
270 cmd_buffer
->push_constant_stages
= 0;
271 cmd_buffer
->scratch_size_needed
= 0;
272 cmd_buffer
->compute_scratch_size_needed
= 0;
273 cmd_buffer
->esgs_ring_size_needed
= 0;
274 cmd_buffer
->gsvs_ring_size_needed
= 0;
275 cmd_buffer
->tess_rings_needed
= false;
276 cmd_buffer
->sample_positions_needed
= false;
278 if (cmd_buffer
->upload
.upload_bo
)
279 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
280 cmd_buffer
->upload
.upload_bo
, 8);
281 cmd_buffer
->upload
.offset
= 0;
283 cmd_buffer
->record_result
= VK_SUCCESS
;
285 cmd_buffer
->ring_offsets_idx
= -1;
287 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
289 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 0,
290 &cmd_buffer
->gfx9_fence_offset
,
292 cmd_buffer
->gfx9_fence_bo
= cmd_buffer
->upload
.upload_bo
;
295 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
297 return cmd_buffer
->record_result
;
301 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
305 struct radeon_winsys_bo
*bo
;
306 struct radv_cmd_buffer_upload
*upload
;
307 struct radv_device
*device
= cmd_buffer
->device
;
309 new_size
= MAX2(min_needed
, 16 * 1024);
310 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
312 bo
= device
->ws
->buffer_create(device
->ws
,
315 RADEON_FLAG_CPU_ACCESS
|
316 RADEON_FLAG_NO_INTERPROCESS_SHARING
);
319 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
323 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
, 8);
324 if (cmd_buffer
->upload
.upload_bo
) {
325 upload
= malloc(sizeof(*upload
));
328 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
329 device
->ws
->buffer_destroy(bo
);
333 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
334 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
337 cmd_buffer
->upload
.upload_bo
= bo
;
338 cmd_buffer
->upload
.size
= new_size
;
339 cmd_buffer
->upload
.offset
= 0;
340 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
342 if (!cmd_buffer
->upload
.map
) {
343 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
351 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
354 unsigned *out_offset
,
357 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
358 if (offset
+ size
> cmd_buffer
->upload
.size
) {
359 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
364 *out_offset
= offset
;
365 *ptr
= cmd_buffer
->upload
.map
+ offset
;
367 cmd_buffer
->upload
.offset
= offset
+ size
;
372 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
373 unsigned size
, unsigned alignment
,
374 const void *data
, unsigned *out_offset
)
378 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
379 out_offset
, (void **)&ptr
))
383 memcpy(ptr
, data
, size
);
389 radv_emit_write_data_packet(struct radeon_winsys_cs
*cs
, uint64_t va
,
390 unsigned count
, const uint32_t *data
)
392 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
393 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
394 S_370_WR_CONFIRM(1) |
395 S_370_ENGINE_SEL(V_370_ME
));
397 radeon_emit(cs
, va
>> 32);
398 radeon_emit_array(cs
, data
, count
);
401 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
403 struct radv_device
*device
= cmd_buffer
->device
;
404 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
407 va
= radv_buffer_get_va(device
->trace_bo
);
408 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
411 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 7);
413 ++cmd_buffer
->state
.trace_id
;
414 radv_cs_add_buffer(device
->ws
, cs
, device
->trace_bo
, 8);
415 radv_emit_write_data_packet(cs
, va
, 1, &cmd_buffer
->state
.trace_id
);
416 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
417 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
421 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
)
423 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
424 enum radv_cmd_flush_bits flags
;
426 /* Force wait for graphics/compute engines to be idle. */
427 flags
= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
428 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
430 si_cs_emit_cache_flush(cmd_buffer
->cs
, false,
431 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
433 radv_cmd_buffer_uses_mec(cmd_buffer
),
437 if (unlikely(cmd_buffer
->device
->trace_bo
))
438 radv_cmd_buffer_trace_emit(cmd_buffer
);
442 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
443 struct radv_pipeline
*pipeline
, enum ring_type ring
)
445 struct radv_device
*device
= cmd_buffer
->device
;
446 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
450 va
= radv_buffer_get_va(device
->trace_bo
);
460 assert(!"invalid ring type");
463 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
466 data
[0] = (uintptr_t)pipeline
;
467 data
[1] = (uintptr_t)pipeline
>> 32;
469 radv_cs_add_buffer(device
->ws
, cs
, device
->trace_bo
, 8);
470 radv_emit_write_data_packet(cs
, va
, 2, data
);
473 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
474 struct radv_descriptor_set
*set
,
477 cmd_buffer
->descriptors
[idx
] = set
;
479 cmd_buffer
->state
.valid_descriptors
|= (1u << idx
);
481 cmd_buffer
->state
.valid_descriptors
&= ~(1u << idx
);
482 cmd_buffer
->state
.descriptors_dirty
|= (1u << idx
);
487 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
489 struct radv_device
*device
= cmd_buffer
->device
;
490 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
491 uint32_t data
[MAX_SETS
* 2] = {};
494 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
496 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(device
->ws
,
497 cmd_buffer
->cs
, 4 + MAX_SETS
* 2);
499 for_each_bit(i
, cmd_buffer
->state
.valid_descriptors
) {
500 struct radv_descriptor_set
*set
= cmd_buffer
->descriptors
[i
];
501 data
[i
* 2] = (uintptr_t)set
;
502 data
[i
* 2 + 1] = (uintptr_t)set
>> 32;
505 radv_cs_add_buffer(device
->ws
, cs
, device
->trace_bo
, 8);
506 radv_emit_write_data_packet(cs
, va
, MAX_SETS
* 2, data
);
510 radv_emit_graphics_blend_state(struct radv_cmd_buffer
*cmd_buffer
,
511 struct radv_pipeline
*pipeline
)
513 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028780_CB_BLEND0_CONTROL
, 8);
514 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.cb_blend_control
,
516 radeon_set_context_reg(cmd_buffer
->cs
, R_028808_CB_COLOR_CONTROL
, pipeline
->graphics
.blend
.cb_color_control
);
517 radeon_set_context_reg(cmd_buffer
->cs
, R_028B70_DB_ALPHA_TO_MASK
, pipeline
->graphics
.blend
.db_alpha_to_mask
);
519 if (cmd_buffer
->device
->physical_device
->has_rbplus
) {
521 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
522 radeon_emit_array(cmd_buffer
->cs
, pipeline
->graphics
.blend
.sx_mrt_blend_opt
, 8);
524 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
525 radeon_emit(cmd_buffer
->cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
526 radeon_emit(cmd_buffer
->cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
527 radeon_emit(cmd_buffer
->cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
532 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer
*cmd_buffer
,
533 struct radv_pipeline
*pipeline
)
535 struct radv_depth_stencil_state
*ds
= &pipeline
->graphics
.ds
;
536 radeon_set_context_reg(cmd_buffer
->cs
, R_028800_DB_DEPTH_CONTROL
, ds
->db_depth_control
);
537 radeon_set_context_reg(cmd_buffer
->cs
, R_02842C_DB_STENCIL_CONTROL
, ds
->db_stencil_control
);
539 radeon_set_context_reg(cmd_buffer
->cs
, R_028000_DB_RENDER_CONTROL
, ds
->db_render_control
);
540 radeon_set_context_reg(cmd_buffer
->cs
, R_028010_DB_RENDER_OVERRIDE2
, ds
->db_render_override2
);
543 struct ac_userdata_info
*
544 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
545 gl_shader_stage stage
,
548 if (stage
== MESA_SHADER_VERTEX
) {
549 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
550 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.user_sgprs_locs
.shader_data
[idx
];
551 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
552 return &pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.user_sgprs_locs
.shader_data
[idx
];
553 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
554 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.user_sgprs_locs
.shader_data
[idx
];
555 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
556 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
557 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.user_sgprs_locs
.shader_data
[idx
];
558 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
559 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.user_sgprs_locs
.shader_data
[idx
];
561 return &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.shader_data
[idx
];
565 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
566 struct radv_pipeline
*pipeline
,
567 gl_shader_stage stage
,
568 int idx
, uint64_t va
)
570 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
571 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
572 if (loc
->sgpr_idx
== -1)
574 assert(loc
->num_sgprs
== 2);
575 assert(!loc
->indirect
);
576 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 2);
577 radeon_emit(cmd_buffer
->cs
, va
);
578 radeon_emit(cmd_buffer
->cs
, va
>> 32);
582 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
583 struct radv_pipeline
*pipeline
)
585 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
586 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
587 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
589 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
590 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[0]);
591 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_mask
[1]);
593 radeon_set_context_reg(cmd_buffer
->cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
594 radeon_set_context_reg(cmd_buffer
->cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
596 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
&&
597 old_pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
== pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
)
600 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
601 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_line_cntl
);
602 radeon_emit(cmd_buffer
->cs
, ms
->pa_sc_aa_config
);
604 radv_cayman_emit_msaa_sample_locs(cmd_buffer
->cs
, num_samples
);
606 /* GFX9: Flush DFSM when the AA mode changes. */
607 if (cmd_buffer
->device
->dfsm_allowed
) {
608 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
609 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
611 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.needs_sample_positions
) {
613 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_FRAGMENT
, AC_UD_PS_SAMPLE_POS_OFFSET
);
614 uint32_t base_reg
= pipeline
->user_data_0
[MESA_SHADER_FRAGMENT
];
615 if (loc
->sgpr_idx
== -1)
617 assert(loc
->num_sgprs
== 1);
618 assert(!loc
->indirect
);
619 switch (num_samples
) {
637 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, offset
);
638 cmd_buffer
->sample_positions_needed
= true;
643 radv_emit_graphics_raster_state(struct radv_cmd_buffer
*cmd_buffer
,
644 struct radv_pipeline
*pipeline
)
646 struct radv_raster_state
*raster
= &pipeline
->graphics
.raster
;
648 radeon_set_context_reg(cmd_buffer
->cs
, R_028810_PA_CL_CLIP_CNTL
,
649 raster
->pa_cl_clip_cntl
);
650 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
651 raster
->spi_interp_control
);
652 radeon_set_context_reg(cmd_buffer
->cs
, R_028BE4_PA_SU_VTX_CNTL
,
653 raster
->pa_su_vtx_cntl
);
654 radeon_set_context_reg(cmd_buffer
->cs
, R_028814_PA_SU_SC_MODE_CNTL
,
655 raster
->pa_su_sc_mode_cntl
);
659 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
662 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
663 si_cp_dma_prefetch(cmd_buffer
, va
, size
);
667 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer
*cmd_buffer
)
669 if (cmd_buffer
->state
.vb_prefetch_dirty
) {
670 radv_emit_prefetch_TC_L2_async(cmd_buffer
,
671 cmd_buffer
->state
.vb_va
,
672 cmd_buffer
->state
.vb_size
);
673 cmd_buffer
->state
.vb_prefetch_dirty
= false;
678 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
679 struct radv_shader_variant
*shader
)
681 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
682 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
688 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
690 radv_cs_add_buffer(ws
, cs
, shader
->bo
, 8);
691 radv_emit_prefetch_TC_L2_async(cmd_buffer
, va
, shader
->code_size
);
695 radv_emit_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
696 struct radv_pipeline
*pipeline
)
698 radv_emit_shader_prefetch(cmd_buffer
,
699 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
700 radv_emit_VBO_descriptors_prefetch(cmd_buffer
);
701 radv_emit_shader_prefetch(cmd_buffer
,
702 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
703 radv_emit_shader_prefetch(cmd_buffer
,
704 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
705 radv_emit_shader_prefetch(cmd_buffer
,
706 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
707 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
708 radv_emit_shader_prefetch(cmd_buffer
,
709 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
713 radv_emit_hw_vs(struct radv_cmd_buffer
*cmd_buffer
,
714 struct radv_pipeline
*pipeline
,
715 struct radv_shader_variant
*shader
)
717 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
719 radeon_set_context_reg(cmd_buffer
->cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
720 pipeline
->graphics
.vs
.spi_vs_out_config
);
722 radeon_set_context_reg(cmd_buffer
->cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
723 pipeline
->graphics
.vs
.spi_shader_pos_format
);
725 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
726 radeon_emit(cmd_buffer
->cs
, va
>> 8);
727 radeon_emit(cmd_buffer
->cs
, va
>> 40);
728 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
729 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
731 radeon_set_context_reg(cmd_buffer
->cs
, R_028818_PA_CL_VTE_CNTL
,
732 S_028818_VTX_W0_FMT(1) |
733 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
734 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
735 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
738 radeon_set_context_reg(cmd_buffer
->cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
739 pipeline
->graphics
.vs
.pa_cl_vs_out_cntl
);
741 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= VI
)
742 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB4_VGT_REUSE_OFF
,
743 pipeline
->graphics
.vs
.vgt_reuse_off
);
747 radv_emit_hw_es(struct radv_cmd_buffer
*cmd_buffer
,
748 struct radv_pipeline
*pipeline
,
749 struct radv_shader_variant
*shader
)
751 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
753 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
754 radeon_emit(cmd_buffer
->cs
, va
>> 8);
755 radeon_emit(cmd_buffer
->cs
, va
>> 40);
756 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
757 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
761 radv_emit_hw_ls(struct radv_cmd_buffer
*cmd_buffer
,
762 struct radv_shader_variant
*shader
)
764 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
765 uint32_t rsrc2
= shader
->rsrc2
;
767 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
768 radeon_emit(cmd_buffer
->cs
, va
>> 8);
769 radeon_emit(cmd_buffer
->cs
, va
>> 40);
771 rsrc2
|= S_00B52C_LDS_SIZE(cmd_buffer
->state
.pipeline
->graphics
.tess
.lds_size
);
772 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== CIK
&&
773 cmd_buffer
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
774 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
776 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
777 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
778 radeon_emit(cmd_buffer
->cs
, rsrc2
);
782 radv_emit_hw_hs(struct radv_cmd_buffer
*cmd_buffer
,
783 struct radv_shader_variant
*shader
)
785 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
787 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
788 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
789 radeon_emit(cmd_buffer
->cs
, va
>> 8);
790 radeon_emit(cmd_buffer
->cs
, va
>> 40);
792 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
793 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
794 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
|
795 S_00B42C_LDS_SIZE(cmd_buffer
->state
.pipeline
->graphics
.tess
.lds_size
));
797 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
798 radeon_emit(cmd_buffer
->cs
, va
>> 8);
799 radeon_emit(cmd_buffer
->cs
, va
>> 40);
800 radeon_emit(cmd_buffer
->cs
, shader
->rsrc1
);
801 radeon_emit(cmd_buffer
->cs
, shader
->rsrc2
);
806 radv_emit_vertex_shader(struct radv_cmd_buffer
*cmd_buffer
,
807 struct radv_pipeline
*pipeline
)
809 struct radv_shader_variant
*vs
;
811 radeon_set_context_reg(cmd_buffer
->cs
, R_028A84_VGT_PRIMITIVEID_EN
, pipeline
->graphics
.vgt_primitiveid_en
);
813 /* Skip shaders merged into HS/GS */
814 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
818 if (vs
->info
.vs
.as_ls
)
819 radv_emit_hw_ls(cmd_buffer
, vs
);
820 else if (vs
->info
.vs
.as_es
)
821 radv_emit_hw_es(cmd_buffer
, pipeline
, vs
);
823 radv_emit_hw_vs(cmd_buffer
, pipeline
, vs
);
828 radv_emit_tess_shaders(struct radv_cmd_buffer
*cmd_buffer
,
829 struct radv_pipeline
*pipeline
)
831 if (!radv_pipeline_has_tess(pipeline
))
834 struct radv_shader_variant
*tes
, *tcs
;
836 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
837 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
840 if (tes
->info
.tes
.as_es
)
841 radv_emit_hw_es(cmd_buffer
, pipeline
, tes
);
843 radv_emit_hw_vs(cmd_buffer
, pipeline
, tes
);
846 radv_emit_hw_hs(cmd_buffer
, tcs
);
848 radeon_set_context_reg(cmd_buffer
->cs
, R_028B6C_VGT_TF_PARAM
,
849 pipeline
->graphics
.tess
.tf_param
);
851 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
)
852 radeon_set_context_reg_idx(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
853 pipeline
->graphics
.tess
.ls_hs_config
);
855 radeon_set_context_reg(cmd_buffer
->cs
, R_028B58_VGT_LS_HS_CONFIG
,
856 pipeline
->graphics
.tess
.ls_hs_config
);
858 struct ac_userdata_info
*loc
;
860 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_CTRL
, AC_UD_TCS_OFFCHIP_LAYOUT
);
861 if (loc
->sgpr_idx
!= -1) {
862 uint32_t base_reg
= pipeline
->user_data_0
[MESA_SHADER_TESS_CTRL
];
863 assert(loc
->num_sgprs
== 4);
864 assert(!loc
->indirect
);
865 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, 4);
866 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.offchip_layout
);
867 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_offsets
);
868 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_out_layout
|
869 pipeline
->graphics
.tess
.num_tcs_input_cp
<< 26);
870 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.tess
.tcs_in_layout
);
873 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_TESS_EVAL
, AC_UD_TES_OFFCHIP_LAYOUT
);
874 if (loc
->sgpr_idx
!= -1) {
875 uint32_t base_reg
= pipeline
->user_data_0
[MESA_SHADER_TESS_EVAL
];
876 assert(loc
->num_sgprs
== 1);
877 assert(!loc
->indirect
);
879 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
880 pipeline
->graphics
.tess
.offchip_layout
);
883 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
, AC_UD_VS_LS_TCS_IN_LAYOUT
);
884 if (loc
->sgpr_idx
!= -1) {
885 uint32_t base_reg
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
886 assert(loc
->num_sgprs
== 1);
887 assert(!loc
->indirect
);
889 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
890 pipeline
->graphics
.tess
.tcs_in_layout
);
895 radv_emit_geometry_shader(struct radv_cmd_buffer
*cmd_buffer
,
896 struct radv_pipeline
*pipeline
)
898 struct radv_shader_variant
*gs
;
901 radeon_set_context_reg(cmd_buffer
->cs
, R_028A40_VGT_GS_MODE
, pipeline
->graphics
.vgt_gs_mode
);
903 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
907 uint32_t gsvs_itemsize
= gs
->info
.gs
.max_gsvs_emit_size
>> 2;
909 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
910 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
911 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
912 radeon_emit(cmd_buffer
->cs
, gsvs_itemsize
);
914 radeon_set_context_reg(cmd_buffer
->cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
);
916 radeon_set_context_reg(cmd_buffer
->cs
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs
->info
.gs
.vertices_out
);
918 uint32_t gs_vert_itemsize
= gs
->info
.gs
.gsvs_vertex_size
;
919 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
920 radeon_emit(cmd_buffer
->cs
, gs_vert_itemsize
>> 2);
921 radeon_emit(cmd_buffer
->cs
, 0);
922 radeon_emit(cmd_buffer
->cs
, 0);
923 radeon_emit(cmd_buffer
->cs
, 0);
925 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
926 radeon_set_context_reg(cmd_buffer
->cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
927 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
928 S_028B90_ENABLE(gs_num_invocations
> 0));
930 radeon_set_context_reg(cmd_buffer
->cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
931 pipeline
->graphics
.gs
.vgt_esgs_ring_itemsize
);
933 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
935 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
936 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
937 radeon_emit(cmd_buffer
->cs
, va
>> 8);
938 radeon_emit(cmd_buffer
->cs
, va
>> 40);
940 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
941 radeon_emit(cmd_buffer
->cs
, gs
->rsrc1
);
942 radeon_emit(cmd_buffer
->cs
, gs
->rsrc2
|
943 S_00B22C_LDS_SIZE(pipeline
->graphics
.gs
.lds_size
));
945 radeon_set_context_reg(cmd_buffer
->cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, pipeline
->graphics
.gs
.vgt_gs_onchip_cntl
);
946 radeon_set_context_reg(cmd_buffer
->cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, pipeline
->graphics
.gs
.vgt_gs_max_prims_per_subgroup
);
948 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
949 radeon_emit(cmd_buffer
->cs
, va
>> 8);
950 radeon_emit(cmd_buffer
->cs
, va
>> 40);
951 radeon_emit(cmd_buffer
->cs
, gs
->rsrc1
);
952 radeon_emit(cmd_buffer
->cs
, gs
->rsrc2
);
955 radv_emit_hw_vs(cmd_buffer
, pipeline
, pipeline
->gs_copy_shader
);
957 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
958 AC_UD_GS_VS_RING_STRIDE_ENTRIES
);
959 if (loc
->sgpr_idx
!= -1) {
960 uint32_t stride
= gs
->info
.gs
.max_gsvs_emit_size
;
961 uint32_t num_entries
= 64;
962 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
965 num_entries
*= stride
;
967 stride
= S_008F04_STRIDE(stride
);
968 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
+ loc
->sgpr_idx
* 4, 2);
969 radeon_emit(cmd_buffer
->cs
, stride
);
970 radeon_emit(cmd_buffer
->cs
, num_entries
);
975 radv_emit_fragment_shader(struct radv_cmd_buffer
*cmd_buffer
,
976 struct radv_pipeline
*pipeline
)
978 struct radv_shader_variant
*ps
;
980 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
981 struct radv_blend_state
*blend
= &pipeline
->graphics
.blend
;
982 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
984 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
985 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
987 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
988 radeon_emit(cmd_buffer
->cs
, va
>> 8);
989 radeon_emit(cmd_buffer
->cs
, va
>> 40);
990 radeon_emit(cmd_buffer
->cs
, ps
->rsrc1
);
991 radeon_emit(cmd_buffer
->cs
, ps
->rsrc2
);
993 radeon_set_context_reg(cmd_buffer
->cs
, R_02880C_DB_SHADER_CONTROL
,
994 pipeline
->graphics
.db_shader_control
);
996 radeon_set_context_reg(cmd_buffer
->cs
, R_0286CC_SPI_PS_INPUT_ENA
,
997 ps
->config
.spi_ps_input_ena
);
999 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
1000 ps
->config
.spi_ps_input_addr
);
1002 if (ps
->info
.info
.ps
.force_persample
)
1003 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1005 radeon_set_context_reg(cmd_buffer
->cs
, R_0286D8_SPI_PS_IN_CONTROL
,
1006 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
1008 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
1010 radeon_set_context_reg(cmd_buffer
->cs
, R_028710_SPI_SHADER_Z_FORMAT
,
1011 pipeline
->graphics
.shader_z_format
);
1013 radeon_set_context_reg(cmd_buffer
->cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
1015 radeon_set_context_reg(cmd_buffer
->cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
1016 radeon_set_context_reg(cmd_buffer
->cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
1018 if (cmd_buffer
->device
->dfsm_allowed
) {
1019 /* optimise this? */
1020 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1021 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
1024 if (pipeline
->graphics
.ps_input_cntl_num
) {
1025 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028644_SPI_PS_INPUT_CNTL_0
, pipeline
->graphics
.ps_input_cntl_num
);
1026 for (unsigned i
= 0; i
< pipeline
->graphics
.ps_input_cntl_num
; i
++) {
1027 radeon_emit(cmd_buffer
->cs
, pipeline
->graphics
.ps_input_cntl
[i
]);
1033 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer
*cmd_buffer
,
1034 struct radv_pipeline
*pipeline
)
1036 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1038 if (cmd_buffer
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
)
1041 radeon_set_context_reg(cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1042 pipeline
->graphics
.vtx_reuse_depth
);
1046 radv_emit_binning_state(struct radv_cmd_buffer
*cmd_buffer
,
1047 struct radv_pipeline
*pipeline
)
1049 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1051 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
1054 radeon_set_context_reg(cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
1055 pipeline
->graphics
.bin
.pa_sc_binner_cntl_0
);
1056 radeon_set_context_reg(cs
, R_028060_DB_DFSM_CONTROL
,
1057 pipeline
->graphics
.bin
.db_dfsm_control
);
1061 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1063 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1065 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
1068 radv_emit_graphics_depth_stencil_state(cmd_buffer
, pipeline
);
1069 radv_emit_graphics_blend_state(cmd_buffer
, pipeline
);
1070 radv_emit_graphics_raster_state(cmd_buffer
, pipeline
);
1071 radv_update_multisample_state(cmd_buffer
, pipeline
);
1072 radv_emit_vertex_shader(cmd_buffer
, pipeline
);
1073 radv_emit_tess_shaders(cmd_buffer
, pipeline
);
1074 radv_emit_geometry_shader(cmd_buffer
, pipeline
);
1075 radv_emit_fragment_shader(cmd_buffer
, pipeline
);
1076 radv_emit_vgt_vertex_reuse(cmd_buffer
, pipeline
);
1077 radv_emit_binning_state(cmd_buffer
, pipeline
);
1079 cmd_buffer
->scratch_size_needed
=
1080 MAX2(cmd_buffer
->scratch_size_needed
,
1081 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
1083 radeon_set_context_reg(cmd_buffer
->cs
, R_0286E8_SPI_TMPRING_SIZE
,
1084 S_0286E8_WAVES(pipeline
->max_waves
) |
1085 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
1087 if (!cmd_buffer
->state
.emitted_pipeline
||
1088 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1089 pipeline
->graphics
.can_use_guardband
)
1090 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1092 radeon_set_context_reg(cmd_buffer
->cs
, R_028B54_VGT_SHADER_STAGES_EN
, pipeline
->graphics
.vgt_shader_stages_en
);
1094 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1095 radeon_set_uconfig_reg_idx(cmd_buffer
->cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, pipeline
->graphics
.prim
);
1097 radeon_set_config_reg(cmd_buffer
->cs
, R_008958_VGT_PRIMITIVE_TYPE
, pipeline
->graphics
.prim
);
1099 radeon_set_context_reg(cmd_buffer
->cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, pipeline
->graphics
.gs_out
);
1101 if (unlikely(cmd_buffer
->device
->trace_bo
))
1102 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1104 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1106 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1110 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1112 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1113 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1117 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1119 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1121 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
1122 * scissor registers are changed. There is also a more efficient but
1123 * more involved alternative workaround.
1125 if (cmd_buffer
->device
->physical_device
->has_scissor_bug
) {
1126 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1127 si_emit_cache_flush(cmd_buffer
);
1129 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1130 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1131 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1132 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1133 radeon_set_context_reg(cmd_buffer
->cs
, R_028A48_PA_SC_MODE_CNTL_0
,
1134 cmd_buffer
->state
.pipeline
->graphics
.ms
.pa_sc_mode_cntl_0
| S_028A48_VPORT_SCISSOR_ENABLE(count
? 1 : 0));
1138 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1140 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1142 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1143 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFF)));
1147 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1149 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1151 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1152 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1156 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1158 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1160 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1161 R_028430_DB_STENCILREFMASK
, 2);
1162 radeon_emit(cmd_buffer
->cs
,
1163 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1164 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1165 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1166 S_028430_STENCILOPVAL(1));
1167 radeon_emit(cmd_buffer
->cs
,
1168 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1169 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1170 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1171 S_028434_STENCILOPVAL_BF(1));
1175 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1177 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1179 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1180 fui(d
->depth_bounds
.min
));
1181 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1182 fui(d
->depth_bounds
.max
));
1186 radv_emit_depth_biais(struct radv_cmd_buffer
*cmd_buffer
)
1188 struct radv_raster_state
*raster
= &cmd_buffer
->state
.pipeline
->graphics
.raster
;
1189 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1190 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1191 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1193 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster
->pa_su_sc_mode_cntl
)) {
1194 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1195 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1196 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1197 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1198 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1199 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1200 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1205 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1207 struct radv_attachment_info
*att
,
1208 struct radv_image
*image
,
1209 VkImageLayout layout
)
1211 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= VI
;
1212 struct radv_color_buffer_info
*cb
= &att
->cb
;
1213 uint32_t cb_color_info
= cb
->cb_color_info
;
1215 if (!radv_layout_dcc_compressed(image
, layout
,
1216 radv_image_queue_family_mask(image
,
1217 cmd_buffer
->queue_family_index
,
1218 cmd_buffer
->queue_family_index
))) {
1219 cb_color_info
&= C_028C70_DCC_ENABLE
;
1222 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1223 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1224 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1225 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
>> 32);
1226 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1227 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1228 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1229 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1230 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1231 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1232 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
>> 32);
1233 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1234 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
>> 32);
1236 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1237 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1238 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
>> 32);
1240 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1241 S_0287A0_EPITCH(att
->attachment
->image
->surface
.u
.gfx9
.surf
.epitch
));
1243 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1244 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1245 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1246 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1247 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1248 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1249 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1250 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1251 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1252 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1253 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1254 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1256 if (is_vi
) { /* DCC BASE */
1257 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1263 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1264 struct radv_ds_buffer_info
*ds
,
1265 struct radv_image
*image
,
1266 VkImageLayout layout
)
1268 uint32_t db_z_info
= ds
->db_z_info
;
1269 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1271 if (!radv_layout_has_htile(image
, layout
,
1272 radv_image_queue_family_mask(image
,
1273 cmd_buffer
->queue_family_index
,
1274 cmd_buffer
->queue_family_index
))) {
1275 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1276 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1279 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1280 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1283 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1284 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1285 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1286 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1287 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1289 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1290 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1291 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1292 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1293 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32); /* DB_Z_READ_BASE_HI */
1294 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1295 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
1296 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1297 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
>> 32); /* DB_Z_WRITE_BASE_HI */
1298 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1299 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
1301 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1302 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1303 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1305 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1307 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1308 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1309 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1310 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1311 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1312 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1313 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1314 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1315 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1316 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1320 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1321 ds
->pa_su_poly_offset_db_fmt_cntl
);
1325 radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1326 struct radv_image
*image
,
1327 VkClearDepthStencilValue ds_clear_value
,
1328 VkImageAspectFlags aspects
)
1330 uint64_t va
= radv_buffer_get_va(image
->bo
);
1331 va
+= image
->offset
+ image
->clear_value_offset
;
1332 unsigned reg_offset
= 0, reg_count
= 0;
1334 assert(image
->surface
.htile_size
);
1336 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1342 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1345 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + reg_count
, 0));
1346 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1347 S_370_WR_CONFIRM(1) |
1348 S_370_ENGINE_SEL(V_370_PFP
));
1349 radeon_emit(cmd_buffer
->cs
, va
);
1350 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1351 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1352 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
);
1353 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1354 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
));
1356 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
, reg_count
);
1357 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
1358 radeon_emit(cmd_buffer
->cs
, ds_clear_value
.stencil
); /* R_028028_DB_STENCIL_CLEAR */
1359 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1360 radeon_emit(cmd_buffer
->cs
, fui(ds_clear_value
.depth
)); /* R_02802C_DB_DEPTH_CLEAR */
1364 radv_load_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1365 struct radv_image
*image
)
1367 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
1368 uint64_t va
= radv_buffer_get_va(image
->bo
);
1369 va
+= image
->offset
+ image
->clear_value_offset
;
1370 unsigned reg_offset
= 0, reg_count
= 0;
1372 if (!image
->surface
.htile_size
)
1375 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1381 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
1384 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1385 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1386 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1387 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
1388 radeon_emit(cmd_buffer
->cs
, va
);
1389 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1390 radeon_emit(cmd_buffer
->cs
, (R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
) >> 2);
1391 radeon_emit(cmd_buffer
->cs
, 0);
1393 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1394 radeon_emit(cmd_buffer
->cs
, 0);
1398 *with DCC some colors don't require CMASK elimiation before being
1399 * used as a texture. This sets a predicate value to determine if the
1400 * cmask eliminate is required.
1403 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1404 struct radv_image
*image
,
1407 uint64_t pred_val
= value
;
1408 uint64_t va
= radv_buffer_get_va(image
->bo
);
1409 va
+= image
->offset
+ image
->dcc_pred_offset
;
1411 assert(image
->surface
.dcc_size
);
1413 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1414 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1415 S_370_WR_CONFIRM(1) |
1416 S_370_ENGINE_SEL(V_370_PFP
));
1417 radeon_emit(cmd_buffer
->cs
, va
);
1418 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1419 radeon_emit(cmd_buffer
->cs
, pred_val
);
1420 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
1424 radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1425 struct radv_image
*image
,
1427 uint32_t color_values
[2])
1429 uint64_t va
= radv_buffer_get_va(image
->bo
);
1430 va
+= image
->offset
+ image
->clear_value_offset
;
1432 assert(image
->cmask
.size
|| image
->surface
.dcc_size
);
1434 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 4, 0));
1435 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1436 S_370_WR_CONFIRM(1) |
1437 S_370_ENGINE_SEL(V_370_PFP
));
1438 radeon_emit(cmd_buffer
->cs
, va
);
1439 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1440 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1441 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1443 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c, 2);
1444 radeon_emit(cmd_buffer
->cs
, color_values
[0]);
1445 radeon_emit(cmd_buffer
->cs
, color_values
[1]);
1449 radv_load_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1450 struct radv_image
*image
,
1453 uint64_t va
= radv_buffer_get_va(image
->bo
);
1454 va
+= image
->offset
+ image
->clear_value_offset
;
1456 if (!image
->cmask
.size
&& !image
->surface
.dcc_size
)
1459 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ idx
* 0x3c;
1461 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
1462 radeon_emit(cmd_buffer
->cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
1463 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
1464 COPY_DATA_COUNT_SEL
);
1465 radeon_emit(cmd_buffer
->cs
, va
);
1466 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1467 radeon_emit(cmd_buffer
->cs
, reg
>> 2);
1468 radeon_emit(cmd_buffer
->cs
, 0);
1470 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
1471 radeon_emit(cmd_buffer
->cs
, 0);
1475 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
1478 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1479 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1481 /* this may happen for inherited secondary recording */
1485 for (i
= 0; i
< 8; ++i
) {
1486 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1487 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
1488 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
1492 int idx
= subpass
->color_attachments
[i
].attachment
;
1493 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1494 struct radv_image
*image
= att
->attachment
->image
;
1495 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
1497 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1499 assert(att
->attachment
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
);
1500 radv_emit_fb_color_state(cmd_buffer
, i
, att
, image
, layout
);
1502 radv_load_color_clear_regs(cmd_buffer
, image
, i
);
1505 if(subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1506 int idx
= subpass
->depth_stencil_attachment
.attachment
;
1507 VkImageLayout layout
= subpass
->depth_stencil_attachment
.layout
;
1508 struct radv_attachment_info
*att
= &framebuffer
->attachments
[idx
];
1509 struct radv_image
*image
= att
->attachment
->image
;
1510 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, att
->attachment
->bo
, 8);
1511 MAYBE_UNUSED
uint32_t queue_mask
= radv_image_queue_family_mask(image
,
1512 cmd_buffer
->queue_family_index
,
1513 cmd_buffer
->queue_family_index
);
1514 /* We currently don't support writing decompressed HTILE */
1515 assert(radv_layout_has_htile(image
, layout
, queue_mask
) ==
1516 radv_layout_is_htile_compressed(image
, layout
, queue_mask
));
1518 radv_emit_fb_ds_state(cmd_buffer
, &att
->ds
, image
, layout
);
1520 if (att
->ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
1521 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
1522 cmd_buffer
->state
.offset_scale
= att
->ds
.offset_scale
;
1524 radv_load_depth_clear_regs(cmd_buffer
, image
);
1526 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1527 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
1529 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
1531 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
1532 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
1534 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
1535 S_028208_BR_X(framebuffer
->width
) |
1536 S_028208_BR_Y(framebuffer
->height
));
1538 if (cmd_buffer
->device
->dfsm_allowed
) {
1539 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1540 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1543 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
1547 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
)
1549 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1550 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1552 if (state
->index_type
!= state
->last_index_type
) {
1553 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1554 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
1555 2, state
->index_type
);
1557 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1558 radeon_emit(cs
, state
->index_type
);
1561 state
->last_index_type
= state
->index_type
;
1564 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
1565 radeon_emit(cs
, state
->index_va
);
1566 radeon_emit(cs
, state
->index_va
>> 32);
1568 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1569 radeon_emit(cs
, state
->max_index_count
);
1571 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
1574 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
1576 uint32_t db_count_control
;
1578 if(!cmd_buffer
->state
.active_occlusion_queries
) {
1579 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1580 db_count_control
= 0;
1582 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1585 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1586 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1587 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1588 S_028004_ZPASS_ENABLE(1) |
1589 S_028004_SLICE_EVEN_ENABLE(1) |
1590 S_028004_SLICE_ODD_ENABLE(1);
1592 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
1593 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1597 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
1601 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
1603 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer
->state
.pipeline
->graphics
.raster
.pa_cl_clip_cntl
))
1606 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1607 radv_emit_viewport(cmd_buffer
);
1609 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
1610 radv_emit_scissor(cmd_buffer
);
1612 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
1613 radv_emit_line_width(cmd_buffer
);
1615 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1616 radv_emit_blend_constants(cmd_buffer
);
1618 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
1619 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
1620 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
1621 radv_emit_stencil(cmd_buffer
);
1623 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
1624 radv_emit_depth_bounds(cmd_buffer
);
1626 if (cmd_buffer
->state
.dirty
& (RADV_CMD_DIRTY_PIPELINE
|
1627 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
))
1628 radv_emit_depth_biais(cmd_buffer
);
1630 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
1634 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1635 struct radv_pipeline
*pipeline
,
1638 gl_shader_stage stage
)
1640 struct ac_userdata_info
*desc_set_loc
= &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
.descriptor_sets
[idx
];
1641 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
1643 if (desc_set_loc
->sgpr_idx
== -1 || desc_set_loc
->indirect
)
1646 assert(!desc_set_loc
->indirect
);
1647 assert(desc_set_loc
->num_sgprs
== 2);
1648 radeon_set_sh_reg_seq(cmd_buffer
->cs
,
1649 base_reg
+ desc_set_loc
->sgpr_idx
* 4, 2);
1650 radeon_emit(cmd_buffer
->cs
, va
);
1651 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1655 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer
*cmd_buffer
,
1656 VkShaderStageFlags stages
,
1657 struct radv_descriptor_set
*set
,
1660 if (cmd_buffer
->state
.pipeline
) {
1661 radv_foreach_stage(stage
, stages
) {
1662 if (cmd_buffer
->state
.pipeline
->shaders
[stage
])
1663 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1669 if (cmd_buffer
->state
.compute_pipeline
&& (stages
& VK_SHADER_STAGE_COMPUTE_BIT
))
1670 emit_stage_descriptor_set_userdata(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
1672 MESA_SHADER_COMPUTE
);
1676 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
1678 struct radv_descriptor_set
*set
= &cmd_buffer
->push_descriptors
.set
;
1681 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
1686 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1687 set
->va
+= bo_offset
;
1691 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
)
1693 uint32_t size
= MAX_SETS
* 2 * 4;
1697 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
1698 256, &offset
, &ptr
))
1701 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
1702 uint32_t *uptr
= ((uint32_t *)ptr
) + i
* 2;
1703 uint64_t set_va
= 0;
1704 struct radv_descriptor_set
*set
= cmd_buffer
->descriptors
[i
];
1705 if (cmd_buffer
->state
.valid_descriptors
& (1u << i
))
1707 uptr
[0] = set_va
& 0xffffffff;
1708 uptr
[1] = set_va
>> 32;
1711 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1714 if (cmd_buffer
->state
.pipeline
) {
1715 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
1716 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1717 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1719 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
1720 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
1721 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1723 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
1724 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
1725 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1727 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1728 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
1729 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1731 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
1732 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
1733 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1736 if (cmd_buffer
->state
.compute_pipeline
)
1737 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
1738 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
1742 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
1743 VkShaderStageFlags stages
)
1747 if (!cmd_buffer
->state
.descriptors_dirty
)
1750 if (cmd_buffer
->state
.push_descriptors_dirty
)
1751 radv_flush_push_descriptors(cmd_buffer
);
1753 if ((cmd_buffer
->state
.pipeline
&& cmd_buffer
->state
.pipeline
->need_indirect_descriptor_sets
) ||
1754 (cmd_buffer
->state
.compute_pipeline
&& cmd_buffer
->state
.compute_pipeline
->need_indirect_descriptor_sets
)) {
1755 radv_flush_indirect_descriptor_sets(cmd_buffer
);
1758 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1760 MAX_SETS
* MESA_SHADER_STAGES
* 4);
1762 for_each_bit(i
, cmd_buffer
->state
.descriptors_dirty
) {
1763 struct radv_descriptor_set
*set
= cmd_buffer
->descriptors
[i
];
1764 if (!(cmd_buffer
->state
.valid_descriptors
& (1u << i
)))
1767 radv_emit_descriptor_set_userdata(cmd_buffer
, stages
, set
, i
);
1769 cmd_buffer
->state
.descriptors_dirty
= 0;
1770 cmd_buffer
->state
.push_descriptors_dirty
= false;
1772 if (unlikely(cmd_buffer
->device
->trace_bo
))
1773 radv_save_descriptors(cmd_buffer
);
1775 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1779 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
1780 struct radv_pipeline
*pipeline
,
1781 VkShaderStageFlags stages
)
1783 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
1788 stages
&= cmd_buffer
->push_constant_stages
;
1790 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
1793 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
1794 16 * layout
->dynamic_offset_count
,
1795 256, &offset
, &ptr
))
1798 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
1799 memcpy((char*)ptr
+ layout
->push_constant_size
, cmd_buffer
->dynamic_buffers
,
1800 16 * layout
->dynamic_offset_count
);
1802 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1805 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
1806 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
1808 radv_foreach_stage(stage
, stages
) {
1809 if (pipeline
->shaders
[stage
]) {
1810 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
1811 AC_UD_PUSH_CONSTANTS
, va
);
1815 cmd_buffer
->push_constant_stages
&= ~stages
;
1816 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
1820 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
1822 if ((pipeline_is_dirty
||
1823 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
1824 cmd_buffer
->state
.pipeline
->vertex_elements
.count
&&
1825 radv_get_vertex_shader(cmd_buffer
->state
.pipeline
)->info
.info
.vs
.has_vertex_buffers
) {
1826 struct radv_vertex_elements_info
*velems
= &cmd_buffer
->state
.pipeline
->vertex_elements
;
1830 uint32_t count
= velems
->count
;
1833 /* allocate some descriptor state for vertex buffers */
1834 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
1835 &vb_offset
, &vb_ptr
))
1838 for (i
= 0; i
< count
; i
++) {
1839 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
1841 int vb
= velems
->binding
[i
];
1842 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[vb
].buffer
;
1843 uint32_t stride
= cmd_buffer
->state
.pipeline
->binding_stride
[vb
];
1845 va
= radv_buffer_get_va(buffer
->bo
);
1847 offset
= cmd_buffer
->vertex_bindings
[vb
].offset
+ velems
->offset
[i
];
1848 va
+= offset
+ buffer
->offset
;
1850 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
1851 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
<= CIK
&& stride
)
1852 desc
[2] = (buffer
->size
- offset
- velems
->format_size
[i
]) / stride
+ 1;
1854 desc
[2] = buffer
->size
- offset
;
1855 desc
[3] = velems
->rsrc_word3
[i
];
1858 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
1861 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
1862 AC_UD_VS_VERTEX_BUFFERS
, va
);
1864 cmd_buffer
->state
.vb_va
= va
;
1865 cmd_buffer
->state
.vb_size
= count
* 16;
1866 cmd_buffer
->state
.vb_prefetch_dirty
= true;
1868 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
1874 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
1876 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
))
1879 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
1880 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.pipeline
,
1881 VK_SHADER_STAGE_ALL_GRAPHICS
);
1887 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
, bool indexed_draw
,
1888 bool instanced_draw
, bool indirect_draw
,
1889 uint32_t draw_vertex_count
)
1891 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
1892 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1893 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
1894 uint32_t ia_multi_vgt_param
;
1895 int32_t primitive_reset_en
;
1898 ia_multi_vgt_param
=
1899 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
1900 indirect_draw
, draw_vertex_count
);
1902 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
1903 if (info
->chip_class
>= GFX9
) {
1904 radeon_set_uconfig_reg_idx(cs
,
1905 R_030960_IA_MULTI_VGT_PARAM
,
1906 4, ia_multi_vgt_param
);
1907 } else if (info
->chip_class
>= CIK
) {
1908 radeon_set_context_reg_idx(cs
,
1909 R_028AA8_IA_MULTI_VGT_PARAM
,
1910 1, ia_multi_vgt_param
);
1912 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
1913 ia_multi_vgt_param
);
1915 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
1918 /* Primitive restart. */
1919 primitive_reset_en
=
1920 indexed_draw
&& state
->pipeline
->graphics
.prim_restart_enable
;
1922 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
1923 state
->last_primitive_reset_en
= primitive_reset_en
;
1924 if (info
->chip_class
>= GFX9
) {
1925 radeon_set_uconfig_reg(cs
,
1926 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
1927 primitive_reset_en
);
1929 radeon_set_context_reg(cs
,
1930 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
1931 primitive_reset_en
);
1935 if (primitive_reset_en
) {
1936 uint32_t primitive_reset_index
=
1937 state
->index_type
? 0xffffffffu
: 0xffffu
;
1939 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
1940 radeon_set_context_reg(cs
,
1941 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
1942 primitive_reset_index
);
1943 state
->last_primitive_reset_index
= primitive_reset_index
;
1948 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
1949 VkPipelineStageFlags src_stage_mask
)
1951 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
1952 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1953 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1954 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1955 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
1958 if (src_stage_mask
& (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
1959 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
1960 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
1961 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
1962 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
1963 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
1964 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
1965 VK_PIPELINE_STAGE_TRANSFER_BIT
|
1966 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
1967 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
1968 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
1969 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
1970 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
1971 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
1972 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
)) {
1973 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
1977 static enum radv_cmd_flush_bits
1978 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
1979 VkAccessFlags src_flags
)
1981 enum radv_cmd_flush_bits flush_bits
= 0;
1983 for_each_bit(b
, src_flags
) {
1984 switch ((VkAccessFlagBits
)(1 << b
)) {
1985 case VK_ACCESS_SHADER_WRITE_BIT
:
1986 flush_bits
|= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
1988 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1989 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1990 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1992 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1993 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1994 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
1996 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1997 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1998 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1999 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2000 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
|
2001 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2010 static enum radv_cmd_flush_bits
2011 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
2012 VkAccessFlags dst_flags
,
2013 struct radv_image
*image
)
2015 enum radv_cmd_flush_bits flush_bits
= 0;
2017 for_each_bit(b
, dst_flags
) {
2018 switch ((VkAccessFlagBits
)(1 << b
)) {
2019 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2020 case VK_ACCESS_INDEX_READ_BIT
:
2022 case VK_ACCESS_UNIFORM_READ_BIT
:
2023 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
| RADV_CMD_FLAG_INV_SMEM_L1
;
2025 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2026 case VK_ACCESS_SHADER_READ_BIT
:
2027 case VK_ACCESS_TRANSFER_READ_BIT
:
2028 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2029 flush_bits
|= RADV_CMD_FLAG_INV_VMEM_L1
|
2030 RADV_CMD_FLAG_INV_GLOBAL_L2
;
2032 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
2033 /* TODO: change to image && when the image gets passed
2034 * through from the subpass. */
2035 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
2036 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2037 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
2039 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
2040 if (!image
|| (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
))
2041 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
2042 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
2051 static void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
, const struct radv_subpass_barrier
*barrier
)
2053 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
);
2054 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
2055 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
2059 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
2060 VkAttachmentReference att
)
2062 unsigned idx
= att
.attachment
;
2063 struct radv_image_view
*view
= cmd_buffer
->state
.framebuffer
->attachments
[idx
].attachment
;
2064 VkImageSubresourceRange range
;
2065 range
.aspectMask
= 0;
2066 range
.baseMipLevel
= view
->base_mip
;
2067 range
.levelCount
= 1;
2068 range
.baseArrayLayer
= view
->base_layer
;
2069 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
2071 radv_handle_image_transition(cmd_buffer
,
2073 cmd_buffer
->state
.attachments
[idx
].current_layout
,
2074 att
.layout
, 0, 0, &range
,
2075 cmd_buffer
->state
.attachments
[idx
].pending_clear_aspects
);
2077 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
2083 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
2084 const struct radv_subpass
*subpass
, bool transitions
)
2087 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
2089 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
2090 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
2091 radv_handle_subpass_image_transition(cmd_buffer
,
2092 subpass
->color_attachments
[i
]);
2095 for (unsigned i
= 0; i
< subpass
->input_count
; ++i
) {
2096 radv_handle_subpass_image_transition(cmd_buffer
,
2097 subpass
->input_attachments
[i
]);
2100 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
2101 radv_handle_subpass_image_transition(cmd_buffer
,
2102 subpass
->depth_stencil_attachment
);
2106 cmd_buffer
->state
.subpass
= subpass
;
2108 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
2112 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
2113 struct radv_render_pass
*pass
,
2114 const VkRenderPassBeginInfo
*info
)
2116 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2118 if (pass
->attachment_count
== 0) {
2119 state
->attachments
= NULL
;
2123 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
2124 pass
->attachment_count
*
2125 sizeof(state
->attachments
[0]),
2126 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2127 if (state
->attachments
== NULL
) {
2128 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2129 return cmd_buffer
->record_result
;
2132 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
2133 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
2134 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
2135 VkImageAspectFlags clear_aspects
= 0;
2137 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2138 /* color attachment */
2139 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2140 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
2143 /* depthstencil attachment */
2144 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2145 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2146 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
2147 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2148 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
2149 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2151 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
2152 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
2153 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
2157 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
2158 state
->attachments
[i
].cleared_views
= 0;
2159 if (clear_aspects
&& info
) {
2160 assert(info
->clearValueCount
> i
);
2161 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
2164 state
->attachments
[i
].current_layout
= att
->initial_layout
;
2170 VkResult
radv_AllocateCommandBuffers(
2172 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
2173 VkCommandBuffer
*pCommandBuffers
)
2175 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2176 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
2178 VkResult result
= VK_SUCCESS
;
2181 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
2183 if (!list_empty(&pool
->free_cmd_buffers
)) {
2184 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
2186 list_del(&cmd_buffer
->pool_link
);
2187 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
2189 result
= radv_reset_cmd_buffer(cmd_buffer
);
2190 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2191 cmd_buffer
->level
= pAllocateInfo
->level
;
2193 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
2195 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
2196 &pCommandBuffers
[i
]);
2198 if (result
!= VK_SUCCESS
)
2202 if (result
!= VK_SUCCESS
) {
2203 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
2204 i
, pCommandBuffers
);
2206 /* From the Vulkan 1.0.66 spec:
2208 * "vkAllocateCommandBuffers can be used to create multiple
2209 * command buffers. If the creation of any of those command
2210 * buffers fails, the implementation must destroy all
2211 * successfully created command buffer objects from this
2212 * command, set all entries of the pCommandBuffers array to
2213 * NULL and return the error."
2215 memset(pCommandBuffers
, 0,
2216 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
2222 void radv_FreeCommandBuffers(
2224 VkCommandPool commandPool
,
2225 uint32_t commandBufferCount
,
2226 const VkCommandBuffer
*pCommandBuffers
)
2228 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2229 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
2232 if (cmd_buffer
->pool
) {
2233 list_del(&cmd_buffer
->pool_link
);
2234 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
2236 radv_cmd_buffer_destroy(cmd_buffer
);
2242 VkResult
radv_ResetCommandBuffer(
2243 VkCommandBuffer commandBuffer
,
2244 VkCommandBufferResetFlags flags
)
2246 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2247 return radv_reset_cmd_buffer(cmd_buffer
);
2250 static void emit_gfx_buffer_state(struct radv_cmd_buffer
*cmd_buffer
)
2252 struct radv_device
*device
= cmd_buffer
->device
;
2253 if (device
->gfx_init
) {
2254 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2255 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, device
->gfx_init
, 8);
2256 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2257 radeon_emit(cmd_buffer
->cs
, va
);
2258 radeon_emit(cmd_buffer
->cs
, va
>> 32);
2259 radeon_emit(cmd_buffer
->cs
, device
->gfx_init_size_dw
& 0xffff);
2261 si_init_config(cmd_buffer
);
2264 VkResult
radv_BeginCommandBuffer(
2265 VkCommandBuffer commandBuffer
,
2266 const VkCommandBufferBeginInfo
*pBeginInfo
)
2268 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2269 VkResult result
= VK_SUCCESS
;
2271 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
2272 /* If the command buffer has already been resetted with
2273 * vkResetCommandBuffer, no need to do it again.
2275 result
= radv_reset_cmd_buffer(cmd_buffer
);
2276 if (result
!= VK_SUCCESS
)
2280 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
2281 cmd_buffer
->state
.last_primitive_reset_en
= -1;
2282 cmd_buffer
->state
.last_index_type
= -1;
2283 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
2285 /* setup initial configuration into command buffer */
2286 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
2287 switch (cmd_buffer
->queue_family_index
) {
2288 case RADV_QUEUE_GENERAL
:
2289 emit_gfx_buffer_state(cmd_buffer
);
2291 case RADV_QUEUE_COMPUTE
:
2292 si_init_compute(cmd_buffer
);
2294 case RADV_QUEUE_TRANSFER
:
2300 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2301 assert(pBeginInfo
->pInheritanceInfo
);
2302 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
2303 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
2305 struct radv_subpass
*subpass
=
2306 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
2308 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
2309 if (result
!= VK_SUCCESS
)
2312 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
2315 if (unlikely(cmd_buffer
->device
->trace_bo
))
2316 radv_cmd_buffer_trace_emit(cmd_buffer
);
2318 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
2323 void radv_CmdBindVertexBuffers(
2324 VkCommandBuffer commandBuffer
,
2325 uint32_t firstBinding
,
2326 uint32_t bindingCount
,
2327 const VkBuffer
* pBuffers
,
2328 const VkDeviceSize
* pOffsets
)
2330 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2331 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
2332 bool changed
= false;
2334 /* We have to defer setting up vertex buffer since we need the buffer
2335 * stride from the pipeline. */
2337 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
2338 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2339 uint32_t idx
= firstBinding
+ i
;
2342 (vb
[idx
].buffer
!= radv_buffer_from_handle(pBuffers
[i
]) ||
2343 vb
[idx
].offset
!= pOffsets
[i
])) {
2347 vb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
2348 vb
[idx
].offset
= pOffsets
[i
];
2350 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
2351 vb
[idx
].buffer
->bo
, 8);
2355 /* No state changes. */
2359 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
2362 void radv_CmdBindIndexBuffer(
2363 VkCommandBuffer commandBuffer
,
2365 VkDeviceSize offset
,
2366 VkIndexType indexType
)
2368 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2369 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
2371 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
2372 cmd_buffer
->state
.index_offset
== offset
&&
2373 cmd_buffer
->state
.index_type
== indexType
) {
2374 /* No state changes. */
2378 cmd_buffer
->state
.index_buffer
= index_buffer
;
2379 cmd_buffer
->state
.index_offset
= offset
;
2380 cmd_buffer
->state
.index_type
= indexType
; /* vk matches hw */
2381 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
2382 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
2384 int index_size_shift
= cmd_buffer
->state
.index_type
? 2 : 1;
2385 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) >> index_size_shift
;
2386 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
2387 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
, 8);
2392 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2393 struct radv_descriptor_set
*set
, unsigned idx
)
2395 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
2397 radv_set_descriptor_set(cmd_buffer
, set
, idx
);
2401 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
2403 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2404 if (set
->descriptors
[j
])
2405 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
], 7);
2408 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
, 8);
2411 void radv_CmdBindDescriptorSets(
2412 VkCommandBuffer commandBuffer
,
2413 VkPipelineBindPoint pipelineBindPoint
,
2414 VkPipelineLayout _layout
,
2416 uint32_t descriptorSetCount
,
2417 const VkDescriptorSet
* pDescriptorSets
,
2418 uint32_t dynamicOffsetCount
,
2419 const uint32_t* pDynamicOffsets
)
2421 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2422 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2423 unsigned dyn_idx
= 0;
2425 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
2426 unsigned idx
= i
+ firstSet
;
2427 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
2428 radv_bind_descriptor_set(cmd_buffer
, set
, idx
);
2430 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
2431 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
2432 uint32_t *dst
= cmd_buffer
->dynamic_buffers
+ idx
* 4;
2433 assert(dyn_idx
< dynamicOffsetCount
);
2435 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
2436 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
2438 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2439 dst
[2] = range
->size
;
2440 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2441 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2442 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2443 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2444 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2445 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2446 cmd_buffer
->push_constant_stages
|=
2447 set
->layout
->dynamic_shader_stages
;
2452 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2453 struct radv_descriptor_set
*set
,
2454 struct radv_descriptor_set_layout
*layout
)
2456 set
->size
= layout
->size
;
2457 set
->layout
= layout
;
2459 if (cmd_buffer
->push_descriptors
.capacity
< set
->size
) {
2460 size_t new_size
= MAX2(set
->size
, 1024);
2461 new_size
= MAX2(new_size
, 2 * cmd_buffer
->push_descriptors
.capacity
);
2462 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
2464 free(set
->mapped_ptr
);
2465 set
->mapped_ptr
= malloc(new_size
);
2467 if (!set
->mapped_ptr
) {
2468 cmd_buffer
->push_descriptors
.capacity
= 0;
2469 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2473 cmd_buffer
->push_descriptors
.capacity
= new_size
;
2479 void radv_meta_push_descriptor_set(
2480 struct radv_cmd_buffer
* cmd_buffer
,
2481 VkPipelineBindPoint pipelineBindPoint
,
2482 VkPipelineLayout _layout
,
2484 uint32_t descriptorWriteCount
,
2485 const VkWriteDescriptorSet
* pDescriptorWrites
)
2487 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2488 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
2492 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2494 push_set
->size
= layout
->set
[set
].layout
->size
;
2495 push_set
->layout
= layout
->set
[set
].layout
;
2497 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
2499 (void**) &push_set
->mapped_ptr
))
2502 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2503 push_set
->va
+= bo_offset
;
2505 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2506 radv_descriptor_set_to_handle(push_set
),
2507 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2509 radv_set_descriptor_set(cmd_buffer
, push_set
, set
);
2512 void radv_CmdPushDescriptorSetKHR(
2513 VkCommandBuffer commandBuffer
,
2514 VkPipelineBindPoint pipelineBindPoint
,
2515 VkPipelineLayout _layout
,
2517 uint32_t descriptorWriteCount
,
2518 const VkWriteDescriptorSet
* pDescriptorWrites
)
2520 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2521 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2522 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2524 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2526 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2529 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
2530 radv_descriptor_set_to_handle(push_set
),
2531 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
2533 radv_set_descriptor_set(cmd_buffer
, push_set
, set
);
2534 cmd_buffer
->state
.push_descriptors_dirty
= true;
2537 void radv_CmdPushDescriptorSetWithTemplateKHR(
2538 VkCommandBuffer commandBuffer
,
2539 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
2540 VkPipelineLayout _layout
,
2544 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2545 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
2546 struct radv_descriptor_set
*push_set
= &cmd_buffer
->push_descriptors
.set
;
2548 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
2550 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
, layout
->set
[set
].layout
))
2553 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
2554 descriptorUpdateTemplate
, pData
);
2556 radv_set_descriptor_set(cmd_buffer
, push_set
, set
);
2557 cmd_buffer
->state
.push_descriptors_dirty
= true;
2560 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
2561 VkPipelineLayout layout
,
2562 VkShaderStageFlags stageFlags
,
2565 const void* pValues
)
2567 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2568 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
2569 cmd_buffer
->push_constant_stages
|= stageFlags
;
2572 VkResult
radv_EndCommandBuffer(
2573 VkCommandBuffer commandBuffer
)
2575 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2577 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
2578 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== SI
)
2579 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
2580 si_emit_cache_flush(cmd_buffer
);
2583 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
2585 if (!cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
))
2586 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2588 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
2590 return cmd_buffer
->record_result
;
2594 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
2596 struct radv_shader_variant
*compute_shader
;
2597 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2598 struct radv_device
*device
= cmd_buffer
->device
;
2599 unsigned compute_resource_limits
;
2600 unsigned waves_per_threadgroup
;
2603 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
2606 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
2608 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
2609 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
2611 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2612 cmd_buffer
->cs
, 19);
2614 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
2615 radeon_emit(cmd_buffer
->cs
, va
>> 8);
2616 radeon_emit(cmd_buffer
->cs
, va
>> 40);
2618 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
2619 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc1
);
2620 radeon_emit(cmd_buffer
->cs
, compute_shader
->rsrc2
);
2623 cmd_buffer
->compute_scratch_size_needed
=
2624 MAX2(cmd_buffer
->compute_scratch_size_needed
,
2625 pipeline
->max_waves
* pipeline
->scratch_bytes_per_wave
);
2627 /* change these once we have scratch support */
2628 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
2629 S_00B860_WAVES(pipeline
->max_waves
) |
2630 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
2632 /* Calculate best compute resource limits. */
2633 waves_per_threadgroup
=
2634 DIV_ROUND_UP(compute_shader
->info
.cs
.block_size
[0] *
2635 compute_shader
->info
.cs
.block_size
[1] *
2636 compute_shader
->info
.cs
.block_size
[2], 64);
2637 compute_resource_limits
=
2638 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup
% 4 == 0);
2640 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
2641 unsigned num_cu_per_se
=
2642 device
->physical_device
->rad_info
.num_good_compute_units
/
2643 device
->physical_device
->rad_info
.max_se
;
2645 /* Force even distribution on all SIMDs in CU if the workgroup
2646 * size is 64. This has shown some good improvements if # of
2647 * CUs per SE is not a multiple of 4.
2649 if (num_cu_per_se
% 4 && waves_per_threadgroup
== 1)
2650 compute_resource_limits
|= S_00B854_FORCE_SIMD_DIST(1);
2653 radeon_set_sh_reg(cmd_buffer
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
2654 compute_resource_limits
);
2656 radeon_set_sh_reg_seq(cmd_buffer
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
2657 radeon_emit(cmd_buffer
->cs
,
2658 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
2659 radeon_emit(cmd_buffer
->cs
,
2660 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
2661 radeon_emit(cmd_buffer
->cs
,
2662 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
2664 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2666 if (unlikely(cmd_buffer
->device
->trace_bo
))
2667 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
2670 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
)
2672 cmd_buffer
->state
.descriptors_dirty
|= cmd_buffer
->state
.valid_descriptors
;
2675 void radv_CmdBindPipeline(
2676 VkCommandBuffer commandBuffer
,
2677 VkPipelineBindPoint pipelineBindPoint
,
2678 VkPipeline _pipeline
)
2680 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2681 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
2683 switch (pipelineBindPoint
) {
2684 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2685 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
2687 radv_mark_descriptor_sets_dirty(cmd_buffer
);
2689 cmd_buffer
->state
.compute_pipeline
= pipeline
;
2690 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2692 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2693 if (cmd_buffer
->state
.pipeline
== pipeline
)
2695 radv_mark_descriptor_sets_dirty(cmd_buffer
);
2697 cmd_buffer
->state
.pipeline
= pipeline
;
2701 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
2702 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
2704 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
2706 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
2707 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
2708 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
2709 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
2711 if (radv_pipeline_has_tess(pipeline
))
2712 cmd_buffer
->tess_rings_needed
= true;
2714 if (radv_pipeline_has_gs(pipeline
)) {
2715 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2716 AC_UD_SCRATCH_RING_OFFSETS
);
2717 if (cmd_buffer
->ring_offsets_idx
== -1)
2718 cmd_buffer
->ring_offsets_idx
= loc
->sgpr_idx
;
2719 else if (loc
->sgpr_idx
!= -1)
2720 assert(loc
->sgpr_idx
== cmd_buffer
->ring_offsets_idx
);
2724 assert(!"invalid bind point");
2729 void radv_CmdSetViewport(
2730 VkCommandBuffer commandBuffer
,
2731 uint32_t firstViewport
,
2732 uint32_t viewportCount
,
2733 const VkViewport
* pViewports
)
2735 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2736 MAYBE_UNUSED
const uint32_t total_count
= firstViewport
+ viewportCount
;
2738 assert(firstViewport
< MAX_VIEWPORTS
);
2739 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
2741 memcpy(cmd_buffer
->state
.dynamic
.viewport
.viewports
+ firstViewport
,
2742 pViewports
, viewportCount
* sizeof(*pViewports
));
2744 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2747 void radv_CmdSetScissor(
2748 VkCommandBuffer commandBuffer
,
2749 uint32_t firstScissor
,
2750 uint32_t scissorCount
,
2751 const VkRect2D
* pScissors
)
2753 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2754 MAYBE_UNUSED
const uint32_t total_count
= firstScissor
+ scissorCount
;
2756 assert(firstScissor
< MAX_SCISSORS
);
2757 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
2759 memcpy(cmd_buffer
->state
.dynamic
.scissor
.scissors
+ firstScissor
,
2760 pScissors
, scissorCount
* sizeof(*pScissors
));
2761 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2764 void radv_CmdSetLineWidth(
2765 VkCommandBuffer commandBuffer
,
2768 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2769 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
2770 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2773 void radv_CmdSetDepthBias(
2774 VkCommandBuffer commandBuffer
,
2775 float depthBiasConstantFactor
,
2776 float depthBiasClamp
,
2777 float depthBiasSlopeFactor
)
2779 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2781 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
2782 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
2783 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
2785 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2788 void radv_CmdSetBlendConstants(
2789 VkCommandBuffer commandBuffer
,
2790 const float blendConstants
[4])
2792 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2794 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
2795 blendConstants
, sizeof(float) * 4);
2797 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2800 void radv_CmdSetDepthBounds(
2801 VkCommandBuffer commandBuffer
,
2802 float minDepthBounds
,
2803 float maxDepthBounds
)
2805 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2807 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
2808 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
2810 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2813 void radv_CmdSetStencilCompareMask(
2814 VkCommandBuffer commandBuffer
,
2815 VkStencilFaceFlags faceMask
,
2816 uint32_t compareMask
)
2818 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2820 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2821 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2822 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2823 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2825 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2828 void radv_CmdSetStencilWriteMask(
2829 VkCommandBuffer commandBuffer
,
2830 VkStencilFaceFlags faceMask
,
2833 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2835 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2836 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2837 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2838 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2840 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2843 void radv_CmdSetStencilReference(
2844 VkCommandBuffer commandBuffer
,
2845 VkStencilFaceFlags faceMask
,
2848 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2850 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2851 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
2852 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2853 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
2855 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2858 void radv_CmdExecuteCommands(
2859 VkCommandBuffer commandBuffer
,
2860 uint32_t commandBufferCount
,
2861 const VkCommandBuffer
* pCmdBuffers
)
2863 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
2865 assert(commandBufferCount
> 0);
2867 /* Emit pending flushes on primary prior to executing secondary */
2868 si_emit_cache_flush(primary
);
2870 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2871 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2873 primary
->scratch_size_needed
= MAX2(primary
->scratch_size_needed
,
2874 secondary
->scratch_size_needed
);
2875 primary
->compute_scratch_size_needed
= MAX2(primary
->compute_scratch_size_needed
,
2876 secondary
->compute_scratch_size_needed
);
2878 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
2879 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
2880 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
2881 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
2882 if (secondary
->tess_rings_needed
)
2883 primary
->tess_rings_needed
= true;
2884 if (secondary
->sample_positions_needed
)
2885 primary
->sample_positions_needed
= true;
2887 if (secondary
->ring_offsets_idx
!= -1) {
2888 if (primary
->ring_offsets_idx
== -1)
2889 primary
->ring_offsets_idx
= secondary
->ring_offsets_idx
;
2891 assert(secondary
->ring_offsets_idx
== primary
->ring_offsets_idx
);
2893 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
2896 /* When the secondary command buffer is compute only we don't
2897 * need to re-emit the current graphics pipeline.
2899 if (secondary
->state
.emitted_pipeline
) {
2900 primary
->state
.emitted_pipeline
=
2901 secondary
->state
.emitted_pipeline
;
2904 /* When the secondary command buffer is graphics only we don't
2905 * need to re-emit the current compute pipeline.
2907 if (secondary
->state
.emitted_compute_pipeline
) {
2908 primary
->state
.emitted_compute_pipeline
=
2909 secondary
->state
.emitted_compute_pipeline
;
2912 /* Only re-emit the draw packets when needed. */
2913 if (secondary
->state
.last_primitive_reset_en
!= -1) {
2914 primary
->state
.last_primitive_reset_en
=
2915 secondary
->state
.last_primitive_reset_en
;
2918 if (secondary
->state
.last_primitive_reset_index
) {
2919 primary
->state
.last_primitive_reset_index
=
2920 secondary
->state
.last_primitive_reset_index
;
2923 if (secondary
->state
.last_ia_multi_vgt_param
) {
2924 primary
->state
.last_ia_multi_vgt_param
=
2925 secondary
->state
.last_ia_multi_vgt_param
;
2928 if (secondary
->state
.last_index_type
!= -1) {
2929 primary
->state
.last_index_type
=
2930 secondary
->state
.last_index_type
;
2934 /* After executing commands from secondary buffers we have to dirty
2937 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
2938 RADV_CMD_DIRTY_INDEX_BUFFER
|
2939 RADV_CMD_DIRTY_DYNAMIC_ALL
;
2940 radv_mark_descriptor_sets_dirty(primary
);
2943 VkResult
radv_CreateCommandPool(
2945 const VkCommandPoolCreateInfo
* pCreateInfo
,
2946 const VkAllocationCallbacks
* pAllocator
,
2947 VkCommandPool
* pCmdPool
)
2949 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2950 struct radv_cmd_pool
*pool
;
2952 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2953 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2955 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2958 pool
->alloc
= *pAllocator
;
2960 pool
->alloc
= device
->alloc
;
2962 list_inithead(&pool
->cmd_buffers
);
2963 list_inithead(&pool
->free_cmd_buffers
);
2965 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2967 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
2973 void radv_DestroyCommandPool(
2975 VkCommandPool commandPool
,
2976 const VkAllocationCallbacks
* pAllocator
)
2978 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2979 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
2984 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2985 &pool
->cmd_buffers
, pool_link
) {
2986 radv_cmd_buffer_destroy(cmd_buffer
);
2989 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
2990 &pool
->free_cmd_buffers
, pool_link
) {
2991 radv_cmd_buffer_destroy(cmd_buffer
);
2994 vk_free2(&device
->alloc
, pAllocator
, pool
);
2997 VkResult
radv_ResetCommandPool(
2999 VkCommandPool commandPool
,
3000 VkCommandPoolResetFlags flags
)
3002 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3005 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
3006 &pool
->cmd_buffers
, pool_link
) {
3007 result
= radv_reset_cmd_buffer(cmd_buffer
);
3008 if (result
!= VK_SUCCESS
)
3015 void radv_TrimCommandPoolKHR(
3017 VkCommandPool commandPool
,
3018 VkCommandPoolTrimFlagsKHR flags
)
3020 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
3025 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
3026 &pool
->free_cmd_buffers
, pool_link
) {
3027 radv_cmd_buffer_destroy(cmd_buffer
);
3031 void radv_CmdBeginRenderPass(
3032 VkCommandBuffer commandBuffer
,
3033 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3034 VkSubpassContents contents
)
3036 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3037 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3038 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3040 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
3041 cmd_buffer
->cs
, 2048);
3042 MAYBE_UNUSED VkResult result
;
3044 cmd_buffer
->state
.framebuffer
= framebuffer
;
3045 cmd_buffer
->state
.pass
= pass
;
3046 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3048 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
3049 if (result
!= VK_SUCCESS
)
3052 radv_cmd_buffer_set_subpass(cmd_buffer
, pass
->subpasses
, true);
3053 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3055 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3058 void radv_CmdNextSubpass(
3059 VkCommandBuffer commandBuffer
,
3060 VkSubpassContents contents
)
3062 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3064 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3066 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
3069 radv_cmd_buffer_set_subpass(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1, true);
3070 radv_cmd_buffer_clear_subpass(cmd_buffer
);
3073 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
3075 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
3076 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
3077 if (!pipeline
->shaders
[stage
])
3079 struct ac_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
3080 if (loc
->sgpr_idx
== -1)
3082 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
3083 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3086 if (pipeline
->gs_copy_shader
) {
3087 struct ac_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
3088 if (loc
->sgpr_idx
!= -1) {
3089 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3090 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
3096 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3097 uint32_t vertex_count
)
3099 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
3100 radeon_emit(cmd_buffer
->cs
, vertex_count
);
3101 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
3102 S_0287F0_USE_OPAQUE(0));
3106 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
3108 uint32_t index_count
)
3110 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, false));
3111 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
3112 radeon_emit(cmd_buffer
->cs
, index_va
);
3113 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
3114 radeon_emit(cmd_buffer
->cs
, index_count
);
3115 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
3119 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
3121 uint32_t draw_count
,
3125 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3126 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
3127 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
3128 bool draw_id_enable
= radv_get_vertex_shader(cmd_buffer
->state
.pipeline
)->info
.info
.vs
.needs_draw_id
;
3129 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
3132 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
3133 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
3134 PKT3_DRAW_INDIRECT
, 3, false));
3136 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3137 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3138 radeon_emit(cs
, di_src_sel
);
3140 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
3141 PKT3_DRAW_INDIRECT_MULTI
,
3144 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
3145 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
3146 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
3147 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
3148 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
3149 radeon_emit(cs
, draw_count
); /* count */
3150 radeon_emit(cs
, count_va
); /* count_addr */
3151 radeon_emit(cs
, count_va
>> 32);
3152 radeon_emit(cs
, stride
); /* stride */
3153 radeon_emit(cs
, di_src_sel
);
3157 struct radv_draw_info
{
3159 * Number of vertices.
3164 * Index of the first vertex.
3166 int32_t vertex_offset
;
3169 * First instance id.
3171 uint32_t first_instance
;
3174 * Number of instances.
3176 uint32_t instance_count
;
3179 * First index (indexed draws only).
3181 uint32_t first_index
;
3184 * Whether it's an indexed draw.
3189 * Indirect draw parameters resource.
3191 struct radv_buffer
*indirect
;
3192 uint64_t indirect_offset
;
3196 * Draw count parameters resource.
3198 struct radv_buffer
*count_buffer
;
3199 uint64_t count_buffer_offset
;
3203 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
3204 const struct radv_draw_info
*info
)
3206 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3207 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3208 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3210 if (info
->indirect
) {
3211 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3212 uint64_t count_va
= 0;
3214 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3216 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
, 8);
3218 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
3220 radeon_emit(cs
, va
);
3221 radeon_emit(cs
, va
>> 32);
3223 if (info
->count_buffer
) {
3224 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
3225 count_va
+= info
->count_buffer
->offset
+
3226 info
->count_buffer_offset
;
3228 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
, 8);
3231 if (!state
->subpass
->view_mask
) {
3232 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3239 for_each_bit(i
, state
->subpass
->view_mask
) {
3240 radv_emit_view_index(cmd_buffer
, i
);
3242 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
3250 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
3251 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
3252 state
->pipeline
->graphics
.vtx_emit_num
);
3253 radeon_emit(cs
, info
->vertex_offset
);
3254 radeon_emit(cs
, info
->first_instance
);
3255 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
3258 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, state
->predicating
));
3259 radeon_emit(cs
, info
->instance_count
);
3261 if (info
->indexed
) {
3262 int index_size
= state
->index_type
? 4 : 2;
3265 index_va
= state
->index_va
;
3266 index_va
+= info
->first_index
* index_size
;
3268 if (!state
->subpass
->view_mask
) {
3269 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3274 for_each_bit(i
, state
->subpass
->view_mask
) {
3275 radv_emit_view_index(cmd_buffer
, i
);
3277 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
3283 if (!state
->subpass
->view_mask
) {
3284 radv_cs_emit_draw_packet(cmd_buffer
, info
->count
);
3287 for_each_bit(i
, state
->subpass
->view_mask
) {
3288 radv_emit_view_index(cmd_buffer
, i
);
3290 radv_cs_emit_draw_packet(cmd_buffer
,
3299 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
3300 const struct radv_draw_info
*info
)
3302 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
3303 radv_emit_graphics_pipeline(cmd_buffer
);
3305 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
3306 radv_emit_framebuffer_state(cmd_buffer
);
3308 if (info
->indexed
) {
3309 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
3310 radv_emit_index_buffer(cmd_buffer
);
3312 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3313 * so the state must be re-emitted before the next indexed
3316 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3317 cmd_buffer
->state
.last_index_type
= -1;
3318 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3322 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
3324 radv_emit_draw_registers(cmd_buffer
, info
->indexed
,
3325 info
->instance_count
> 1, info
->indirect
,
3326 info
->indirect
? 0 : info
->count
);
3330 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
3331 const struct radv_draw_info
*info
)
3333 bool pipeline_is_dirty
=
3334 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
3335 cmd_buffer
->state
.pipeline
&&
3336 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
3338 MAYBE_UNUSED
unsigned cdw_max
=
3339 radeon_check_space(cmd_buffer
->device
->ws
,
3340 cmd_buffer
->cs
, 4096);
3342 /* Use optimal packet order based on whether we need to sync the
3345 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3346 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3347 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
3348 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
3349 /* If we have to wait for idle, set all states first, so that
3350 * all SET packets are processed in parallel with previous draw
3351 * calls. Then upload descriptors, set shader pointers, and
3352 * draw, and prefetch at the end. This ensures that the time
3353 * the CUs are idle is very short. (there are only SET_SH
3354 * packets between the wait and the draw)
3356 radv_emit_all_graphics_states(cmd_buffer
, info
);
3357 si_emit_cache_flush(cmd_buffer
);
3358 /* <-- CUs are idle here --> */
3360 if (!radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
))
3363 radv_emit_draw_packets(cmd_buffer
, info
);
3364 /* <-- CUs are busy here --> */
3366 /* Start prefetches after the draw has been started. Both will
3367 * run in parallel, but starting the draw first is more
3370 if (pipeline_is_dirty
) {
3371 radv_emit_prefetch(cmd_buffer
,
3372 cmd_buffer
->state
.pipeline
);
3375 /* If we don't wait for idle, start prefetches first, then set
3376 * states, and draw at the end.
3378 si_emit_cache_flush(cmd_buffer
);
3380 if (pipeline_is_dirty
) {
3381 radv_emit_prefetch(cmd_buffer
,
3382 cmd_buffer
->state
.pipeline
);
3385 if (!radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
))
3388 radv_emit_all_graphics_states(cmd_buffer
, info
);
3389 radv_emit_draw_packets(cmd_buffer
, info
);
3392 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3393 radv_cmd_buffer_after_draw(cmd_buffer
);
3397 VkCommandBuffer commandBuffer
,
3398 uint32_t vertexCount
,
3399 uint32_t instanceCount
,
3400 uint32_t firstVertex
,
3401 uint32_t firstInstance
)
3403 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3404 struct radv_draw_info info
= {};
3406 info
.count
= vertexCount
;
3407 info
.instance_count
= instanceCount
;
3408 info
.first_instance
= firstInstance
;
3409 info
.vertex_offset
= firstVertex
;
3411 radv_draw(cmd_buffer
, &info
);
3414 void radv_CmdDrawIndexed(
3415 VkCommandBuffer commandBuffer
,
3416 uint32_t indexCount
,
3417 uint32_t instanceCount
,
3418 uint32_t firstIndex
,
3419 int32_t vertexOffset
,
3420 uint32_t firstInstance
)
3422 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3423 struct radv_draw_info info
= {};
3425 info
.indexed
= true;
3426 info
.count
= indexCount
;
3427 info
.instance_count
= instanceCount
;
3428 info
.first_index
= firstIndex
;
3429 info
.vertex_offset
= vertexOffset
;
3430 info
.first_instance
= firstInstance
;
3432 radv_draw(cmd_buffer
, &info
);
3435 void radv_CmdDrawIndirect(
3436 VkCommandBuffer commandBuffer
,
3438 VkDeviceSize offset
,
3442 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3443 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3444 struct radv_draw_info info
= {};
3446 info
.count
= drawCount
;
3447 info
.indirect
= buffer
;
3448 info
.indirect_offset
= offset
;
3449 info
.stride
= stride
;
3451 radv_draw(cmd_buffer
, &info
);
3454 void radv_CmdDrawIndexedIndirect(
3455 VkCommandBuffer commandBuffer
,
3457 VkDeviceSize offset
,
3461 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3462 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3463 struct radv_draw_info info
= {};
3465 info
.indexed
= true;
3466 info
.count
= drawCount
;
3467 info
.indirect
= buffer
;
3468 info
.indirect_offset
= offset
;
3469 info
.stride
= stride
;
3471 radv_draw(cmd_buffer
, &info
);
3474 void radv_CmdDrawIndirectCountAMD(
3475 VkCommandBuffer commandBuffer
,
3477 VkDeviceSize offset
,
3478 VkBuffer _countBuffer
,
3479 VkDeviceSize countBufferOffset
,
3480 uint32_t maxDrawCount
,
3483 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3484 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3485 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3486 struct radv_draw_info info
= {};
3488 info
.count
= maxDrawCount
;
3489 info
.indirect
= buffer
;
3490 info
.indirect_offset
= offset
;
3491 info
.count_buffer
= count_buffer
;
3492 info
.count_buffer_offset
= countBufferOffset
;
3493 info
.stride
= stride
;
3495 radv_draw(cmd_buffer
, &info
);
3498 void radv_CmdDrawIndexedIndirectCountAMD(
3499 VkCommandBuffer commandBuffer
,
3501 VkDeviceSize offset
,
3502 VkBuffer _countBuffer
,
3503 VkDeviceSize countBufferOffset
,
3504 uint32_t maxDrawCount
,
3507 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3508 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3509 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
3510 struct radv_draw_info info
= {};
3512 info
.indexed
= true;
3513 info
.count
= maxDrawCount
;
3514 info
.indirect
= buffer
;
3515 info
.indirect_offset
= offset
;
3516 info
.count_buffer
= count_buffer
;
3517 info
.count_buffer_offset
= countBufferOffset
;
3518 info
.stride
= stride
;
3520 radv_draw(cmd_buffer
, &info
);
3523 struct radv_dispatch_info
{
3525 * Determine the layout of the grid (in block units) to be used.
3530 * Whether it's an unaligned compute dispatch.
3535 * Indirect compute parameters resource.
3537 struct radv_buffer
*indirect
;
3538 uint64_t indirect_offset
;
3542 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
3543 const struct radv_dispatch_info
*info
)
3545 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3546 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
3547 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
3548 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3549 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
3550 struct ac_userdata_info
*loc
;
3552 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
3553 AC_UD_CS_GRID_SIZE
);
3555 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
3557 if (info
->indirect
) {
3558 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
3560 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
3562 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
, 8);
3564 if (loc
->sgpr_idx
!= -1) {
3565 for (unsigned i
= 0; i
< 3; ++i
) {
3566 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3567 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
3568 COPY_DATA_DST_SEL(COPY_DATA_REG
));
3569 radeon_emit(cs
, (va
+ 4 * i
));
3570 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
3571 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
3572 + loc
->sgpr_idx
* 4) >> 2) + i
);
3577 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
3578 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, 0) |
3579 PKT3_SHADER_TYPE_S(1));
3580 radeon_emit(cs
, va
);
3581 radeon_emit(cs
, va
>> 32);
3582 radeon_emit(cs
, dispatch_initiator
);
3584 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
3585 PKT3_SHADER_TYPE_S(1));
3587 radeon_emit(cs
, va
);
3588 radeon_emit(cs
, va
>> 32);
3590 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, 0) |
3591 PKT3_SHADER_TYPE_S(1));
3593 radeon_emit(cs
, dispatch_initiator
);
3596 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
3598 if (info
->unaligned
) {
3599 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
3600 unsigned remainder
[3];
3602 /* If aligned, these should be an entire block size,
3605 remainder
[0] = blocks
[0] + cs_block_size
[0] -
3606 align_u32_npot(blocks
[0], cs_block_size
[0]);
3607 remainder
[1] = blocks
[1] + cs_block_size
[1] -
3608 align_u32_npot(blocks
[1], cs_block_size
[1]);
3609 remainder
[2] = blocks
[2] + cs_block_size
[2] -
3610 align_u32_npot(blocks
[2], cs_block_size
[2]);
3612 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
3613 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
3614 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
3616 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
3618 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
3619 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
3621 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
3622 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
3624 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
3625 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
3627 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
3630 if (loc
->sgpr_idx
!= -1) {
3631 assert(!loc
->indirect
);
3632 assert(loc
->num_sgprs
== 3);
3634 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
3635 loc
->sgpr_idx
* 4, 3);
3636 radeon_emit(cs
, blocks
[0]);
3637 radeon_emit(cs
, blocks
[1]);
3638 radeon_emit(cs
, blocks
[2]);
3641 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
3642 PKT3_SHADER_TYPE_S(1));
3643 radeon_emit(cs
, blocks
[0]);
3644 radeon_emit(cs
, blocks
[1]);
3645 radeon_emit(cs
, blocks
[2]);
3646 radeon_emit(cs
, dispatch_initiator
);
3649 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
3653 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
3655 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
3656 radv_flush_constants(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
,
3657 VK_SHADER_STAGE_COMPUTE_BIT
);
3661 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
3662 const struct radv_dispatch_info
*info
)
3664 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
3665 bool pipeline_is_dirty
= pipeline
&&
3666 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
3668 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3669 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3670 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
3671 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
3672 /* If we have to wait for idle, set all states first, so that
3673 * all SET packets are processed in parallel with previous draw
3674 * calls. Then upload descriptors, set shader pointers, and
3675 * dispatch, and prefetch at the end. This ensures that the
3676 * time the CUs are idle is very short. (there are only SET_SH
3677 * packets between the wait and the draw)
3679 radv_emit_compute_pipeline(cmd_buffer
);
3680 si_emit_cache_flush(cmd_buffer
);
3681 /* <-- CUs are idle here --> */
3683 radv_upload_compute_shader_descriptors(cmd_buffer
);
3685 radv_emit_dispatch_packets(cmd_buffer
, info
);
3686 /* <-- CUs are busy here --> */
3688 /* Start prefetches after the dispatch has been started. Both
3689 * will run in parallel, but starting the dispatch first is
3692 if (pipeline_is_dirty
) {
3693 radv_emit_shader_prefetch(cmd_buffer
,
3694 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
3697 /* If we don't wait for idle, start prefetches first, then set
3698 * states, and dispatch at the end.
3700 si_emit_cache_flush(cmd_buffer
);
3702 if (pipeline_is_dirty
) {
3703 radv_emit_shader_prefetch(cmd_buffer
,
3704 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
3707 radv_upload_compute_shader_descriptors(cmd_buffer
);
3709 radv_emit_compute_pipeline(cmd_buffer
);
3710 radv_emit_dispatch_packets(cmd_buffer
, info
);
3713 radv_cmd_buffer_after_draw(cmd_buffer
);
3716 void radv_CmdDispatch(
3717 VkCommandBuffer commandBuffer
,
3722 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3723 struct radv_dispatch_info info
= {};
3729 radv_dispatch(cmd_buffer
, &info
);
3732 void radv_CmdDispatchIndirect(
3733 VkCommandBuffer commandBuffer
,
3735 VkDeviceSize offset
)
3737 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3738 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3739 struct radv_dispatch_info info
= {};
3741 info
.indirect
= buffer
;
3742 info
.indirect_offset
= offset
;
3744 radv_dispatch(cmd_buffer
, &info
);
3747 void radv_unaligned_dispatch(
3748 struct radv_cmd_buffer
*cmd_buffer
,
3753 struct radv_dispatch_info info
= {};
3760 radv_dispatch(cmd_buffer
, &info
);
3763 void radv_CmdEndRenderPass(
3764 VkCommandBuffer commandBuffer
)
3766 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3768 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
3770 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
3772 for (unsigned i
= 0; i
< cmd_buffer
->state
.framebuffer
->attachment_count
; ++i
) {
3773 VkImageLayout layout
= cmd_buffer
->state
.pass
->attachments
[i
].final_layout
;
3774 radv_handle_subpass_image_transition(cmd_buffer
,
3775 (VkAttachmentReference
){i
, layout
});
3778 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3780 cmd_buffer
->state
.pass
= NULL
;
3781 cmd_buffer
->state
.subpass
= NULL
;
3782 cmd_buffer
->state
.attachments
= NULL
;
3783 cmd_buffer
->state
.framebuffer
= NULL
;
3787 * For HTILE we have the following interesting clear words:
3788 * 0x0000030f: Uncompressed for depth+stencil HTILE.
3789 * 0x0000000f: Uncompressed for depth only HTILE.
3790 * 0xfffffff0: Clear depth to 1.0
3791 * 0x00000000: Clear depth to 0.0
3793 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
3794 struct radv_image
*image
,
3795 const VkImageSubresourceRange
*range
,
3796 uint32_t clear_word
)
3798 assert(range
->baseMipLevel
== 0);
3799 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
3800 unsigned layer_count
= radv_get_layerCount(image
, range
);
3801 uint64_t size
= image
->surface
.htile_slice_size
* layer_count
;
3802 uint64_t offset
= image
->offset
+ image
->htile_offset
+
3803 image
->surface
.htile_slice_size
* range
->baseArrayLayer
;
3804 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3806 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3807 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3809 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
, offset
,
3812 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3815 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3816 struct radv_image
*image
,
3817 VkImageLayout src_layout
,
3818 VkImageLayout dst_layout
,
3819 unsigned src_queue_mask
,
3820 unsigned dst_queue_mask
,
3821 const VkImageSubresourceRange
*range
,
3822 VkImageAspectFlags pending_clears
)
3824 if (dst_layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
&&
3825 (pending_clears
& vk_format_aspects(image
->vk_format
)) == vk_format_aspects(image
->vk_format
) &&
3826 cmd_buffer
->state
.render_area
.offset
.x
== 0 && cmd_buffer
->state
.render_area
.offset
.y
== 0 &&
3827 cmd_buffer
->state
.render_area
.extent
.width
== image
->info
.width
&&
3828 cmd_buffer
->state
.render_area
.extent
.height
== image
->info
.height
) {
3829 /* The clear will initialize htile. */
3831 } else if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
&&
3832 radv_layout_has_htile(image
, dst_layout
, dst_queue_mask
)) {
3833 /* TODO: merge with the clear if applicable */
3834 radv_initialize_htile(cmd_buffer
, image
, range
, 0);
3835 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3836 radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3837 uint32_t clear_value
= vk_format_is_stencil(image
->vk_format
) ? 0x30f : 0xf;
3838 radv_initialize_htile(cmd_buffer
, image
, range
, clear_value
);
3839 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_queue_mask
) &&
3840 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_queue_mask
)) {
3841 VkImageSubresourceRange local_range
= *range
;
3842 local_range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
3843 local_range
.baseMipLevel
= 0;
3844 local_range
.levelCount
= 1;
3846 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3847 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3849 radv_decompress_depth_image_inplace(cmd_buffer
, image
, &local_range
);
3851 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3852 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3856 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
3857 struct radv_image
*image
, uint32_t value
)
3859 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3861 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3862 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3864 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
,
3865 image
->offset
+ image
->cmask
.offset
,
3866 image
->cmask
.size
, value
);
3868 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3871 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3872 struct radv_image
*image
,
3873 VkImageLayout src_layout
,
3874 VkImageLayout dst_layout
,
3875 unsigned src_queue_mask
,
3876 unsigned dst_queue_mask
,
3877 const VkImageSubresourceRange
*range
)
3879 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3880 if (image
->fmask
.size
)
3881 radv_initialise_cmask(cmd_buffer
, image
, 0xccccccccu
);
3883 radv_initialise_cmask(cmd_buffer
, image
, 0xffffffffu
);
3884 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3885 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3886 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3890 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
3891 struct radv_image
*image
, uint32_t value
)
3893 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3895 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3896 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3898 state
->flush_bits
|= radv_fill_buffer(cmd_buffer
, image
->bo
,
3899 image
->offset
+ image
->dcc_offset
,
3900 image
->surface
.dcc_size
, value
);
3902 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3903 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3906 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3907 struct radv_image
*image
,
3908 VkImageLayout src_layout
,
3909 VkImageLayout dst_layout
,
3910 unsigned src_queue_mask
,
3911 unsigned dst_queue_mask
,
3912 const VkImageSubresourceRange
*range
)
3914 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
3915 radv_initialize_dcc(cmd_buffer
, image
,
3916 radv_layout_dcc_compressed(image
, dst_layout
, dst_queue_mask
) ?
3917 0x20202020u
: 0xffffffffu
);
3918 } else if (radv_layout_dcc_compressed(image
, src_layout
, src_queue_mask
) &&
3919 !radv_layout_dcc_compressed(image
, dst_layout
, dst_queue_mask
)) {
3920 radv_decompress_dcc(cmd_buffer
, image
, range
);
3921 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_queue_mask
) &&
3922 !radv_layout_can_fast_clear(image
, dst_layout
, dst_queue_mask
)) {
3923 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
3927 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3928 struct radv_image
*image
,
3929 VkImageLayout src_layout
,
3930 VkImageLayout dst_layout
,
3931 uint32_t src_family
,
3932 uint32_t dst_family
,
3933 const VkImageSubresourceRange
*range
,
3934 VkImageAspectFlags pending_clears
)
3936 if (image
->exclusive
&& src_family
!= dst_family
) {
3937 /* This is an acquire or a release operation and there will be
3938 * a corresponding release/acquire. Do the transition in the
3939 * most flexible queue. */
3941 assert(src_family
== cmd_buffer
->queue_family_index
||
3942 dst_family
== cmd_buffer
->queue_family_index
);
3944 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
3947 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
3948 (src_family
== RADV_QUEUE_GENERAL
||
3949 dst_family
== RADV_QUEUE_GENERAL
))
3953 unsigned src_queue_mask
= radv_image_queue_family_mask(image
, src_family
, cmd_buffer
->queue_family_index
);
3954 unsigned dst_queue_mask
= radv_image_queue_family_mask(image
, dst_family
, cmd_buffer
->queue_family_index
);
3956 if (image
->surface
.htile_size
)
3957 radv_handle_depth_image_transition(cmd_buffer
, image
, src_layout
,
3958 dst_layout
, src_queue_mask
,
3959 dst_queue_mask
, range
,
3962 if (image
->cmask
.size
|| image
->fmask
.size
)
3963 radv_handle_cmask_image_transition(cmd_buffer
, image
, src_layout
,
3964 dst_layout
, src_queue_mask
,
3965 dst_queue_mask
, range
);
3967 if (image
->surface
.dcc_size
)
3968 radv_handle_dcc_image_transition(cmd_buffer
, image
, src_layout
,
3969 dst_layout
, src_queue_mask
,
3970 dst_queue_mask
, range
);
3973 void radv_CmdPipelineBarrier(
3974 VkCommandBuffer commandBuffer
,
3975 VkPipelineStageFlags srcStageMask
,
3976 VkPipelineStageFlags destStageMask
,
3978 uint32_t memoryBarrierCount
,
3979 const VkMemoryBarrier
* pMemoryBarriers
,
3980 uint32_t bufferMemoryBarrierCount
,
3981 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
3982 uint32_t imageMemoryBarrierCount
,
3983 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
3985 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3986 enum radv_cmd_flush_bits src_flush_bits
= 0;
3987 enum radv_cmd_flush_bits dst_flush_bits
= 0;
3989 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3990 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
);
3991 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
3995 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3996 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
);
3997 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
4001 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4002 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4003 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
);
4004 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
4008 radv_stage_flush(cmd_buffer
, srcStageMask
);
4009 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
4011 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4012 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4013 radv_handle_image_transition(cmd_buffer
, image
,
4014 pImageMemoryBarriers
[i
].oldLayout
,
4015 pImageMemoryBarriers
[i
].newLayout
,
4016 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
4017 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
4018 &pImageMemoryBarriers
[i
].subresourceRange
,
4022 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
4026 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
4027 struct radv_event
*event
,
4028 VkPipelineStageFlags stageMask
,
4031 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
4032 uint64_t va
= radv_buffer_get_va(event
->bo
);
4034 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
, 8);
4036 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 18);
4038 /* TODO: this is overkill. Probably should figure something out from
4039 * the stage mask. */
4041 si_cs_emit_write_event_eop(cs
,
4042 cmd_buffer
->state
.predicating
,
4043 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
4044 radv_cmd_buffer_uses_mec(cmd_buffer
),
4045 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
4048 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4051 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
4053 VkPipelineStageFlags stageMask
)
4055 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4056 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4058 write_event(cmd_buffer
, event
, stageMask
, 1);
4061 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
4063 VkPipelineStageFlags stageMask
)
4065 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4066 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4068 write_event(cmd_buffer
, event
, stageMask
, 0);
4071 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
4072 uint32_t eventCount
,
4073 const VkEvent
* pEvents
,
4074 VkPipelineStageFlags srcStageMask
,
4075 VkPipelineStageFlags dstStageMask
,
4076 uint32_t memoryBarrierCount
,
4077 const VkMemoryBarrier
* pMemoryBarriers
,
4078 uint32_t bufferMemoryBarrierCount
,
4079 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4080 uint32_t imageMemoryBarrierCount
,
4081 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4083 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4084 struct radeon_winsys_cs
*cs
= cmd_buffer
->cs
;
4086 for (unsigned i
= 0; i
< eventCount
; ++i
) {
4087 RADV_FROM_HANDLE(radv_event
, event
, pEvents
[i
]);
4088 uint64_t va
= radv_buffer_get_va(event
->bo
);
4090 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
, 8);
4092 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
4094 si_emit_wait_fence(cs
, false, va
, 1, 0xffffffff);
4095 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4099 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
4100 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
4102 radv_handle_image_transition(cmd_buffer
, image
,
4103 pImageMemoryBarriers
[i
].oldLayout
,
4104 pImageMemoryBarriers
[i
].newLayout
,
4105 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
4106 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
4107 &pImageMemoryBarriers
[i
].subresourceRange
,
4111 /* TODO: figure out how to do memory barriers without waiting */
4112 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
|
4113 RADV_CMD_FLAG_INV_GLOBAL_L2
|
4114 RADV_CMD_FLAG_INV_VMEM_L1
|
4115 RADV_CMD_FLAG_INV_SMEM_L1
;